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-rw-r--r--arch/arm/mach-pxa/lpd270.c99
1 files changed, 54 insertions, 45 deletions
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index b7038948d1d4..de3f67daaacf 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -40,7 +40,7 @@
40 40
41#include <mach/pxa-regs.h> 41#include <mach/pxa-regs.h>
42#include <mach/pxa2xx-regs.h> 42#include <mach/pxa2xx-regs.h>
43#include <mach/pxa2xx-gpio.h> 43#include <mach/mfp-pxa27x.h>
44#include <mach/lpd270.h> 44#include <mach/lpd270.h>
45#include <mach/audio.h> 45#include <mach/audio.h>
46#include <mach/pxafb.h> 46#include <mach/pxafb.h>
@@ -51,6 +51,43 @@
51#include "generic.h" 51#include "generic.h"
52#include "devices.h" 52#include "devices.h"
53 53
54static unsigned long lpd270_pin_config[] __initdata = {
55 /* Chip Selects */
56 GPIO15_nCS_1, /* Mainboard Flash */
57 GPIO78_nCS_2, /* CPLD + Ethernet */
58
59 /* LCD - 16bpp Active TFT */
60 GPIO58_LCD_LDD_0,
61 GPIO59_LCD_LDD_1,
62 GPIO60_LCD_LDD_2,
63 GPIO61_LCD_LDD_3,
64 GPIO62_LCD_LDD_4,
65 GPIO63_LCD_LDD_5,
66 GPIO64_LCD_LDD_6,
67 GPIO65_LCD_LDD_7,
68 GPIO66_LCD_LDD_8,
69 GPIO67_LCD_LDD_9,
70 GPIO68_LCD_LDD_10,
71 GPIO69_LCD_LDD_11,
72 GPIO70_LCD_LDD_12,
73 GPIO71_LCD_LDD_13,
74 GPIO72_LCD_LDD_14,
75 GPIO73_LCD_LDD_15,
76 GPIO74_LCD_FCLK,
77 GPIO75_LCD_LCLK,
78 GPIO76_LCD_PCLK,
79 GPIO77_LCD_BIAS,
80 GPIO16_PWM0_OUT, /* Backlight */
81
82 /* USB Host */
83 GPIO88_USBH1_PWR,
84 GPIO89_USBH1_PEN,
85
86 /* AC97 */
87 GPIO45_AC97_SYSCLK,
88
89 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
90};
54 91
55static unsigned int lpd270_irq_enabled; 92static unsigned int lpd270_irq_enabled;
56 93
@@ -88,8 +125,7 @@ static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
88 GEDR(0) = GPIO_bit(0); /* clear useless edge notification */ 125 GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
89 if (likely(pending)) { 126 if (likely(pending)) {
90 irq = LPD270_IRQ(0) + __ffs(pending); 127 irq = LPD270_IRQ(0) + __ffs(pending);
91 desc = irq_desc + irq; 128 generic_handle_irq(irq);
92 desc_handle_irq(irq, desc);
93 129
94 pending = __raw_readw(LPD270_INT_STATUS) & 130 pending = __raw_readw(LPD270_INT_STATUS) &
95 lpd270_irq_enabled; 131 lpd270_irq_enabled;
@@ -265,8 +301,8 @@ static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
265static struct pxafb_mach_info sharp_lq057q3dc02 = { 301static struct pxafb_mach_info sharp_lq057q3dc02 = {
266 .modes = &sharp_lq057q3dc02_mode, 302 .modes = &sharp_lq057q3dc02_mode,
267 .num_modes = 1, 303 .num_modes = 1,
268 .lccr0 = 0x07800080, 304 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
269 .lccr3 = 0x00400000, 305 LCD_ALTERNATE_MAPPING,
270}; 306};
271 307
272/* 12.1" TFT SVGA (LoLo display number 2) */ 308/* 12.1" TFT SVGA (LoLo display number 2) */
@@ -287,8 +323,8 @@ static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
287static struct pxafb_mach_info sharp_lq121s1dg31 = { 323static struct pxafb_mach_info sharp_lq121s1dg31 = {
288 .modes = &sharp_lq121s1dg31_mode, 324 .modes = &sharp_lq121s1dg31_mode,
289 .num_modes = 1, 325 .num_modes = 1,
290 .lccr0 = 0x07800080, 326 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
291 .lccr3 = 0x00400000, 327 LCD_ALTERNATE_MAPPING,
292}; 328};
293 329
294/* 3.6" TFT QVGA (LoLo display number 3) */ 330/* 3.6" TFT QVGA (LoLo display number 3) */
@@ -309,8 +345,8 @@ static struct pxafb_mode_info sharp_lq036q1da01_mode = {
309static struct pxafb_mach_info sharp_lq036q1da01 = { 345static struct pxafb_mach_info sharp_lq036q1da01 = {
310 .modes = &sharp_lq036q1da01_mode, 346 .modes = &sharp_lq036q1da01_mode,
311 .num_modes = 1, 347 .num_modes = 1,
312 .lccr0 = 0x07800080, 348 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
313 .lccr3 = 0x00400000, 349 LCD_ALTERNATE_MAPPING,
314}; 350};
315 351
316/* 6.4" TFT VGA (LoLo display number 5) */ 352/* 6.4" TFT VGA (LoLo display number 5) */
@@ -331,8 +367,8 @@ static struct pxafb_mode_info sharp_lq64d343_mode = {
331static struct pxafb_mach_info sharp_lq64d343 = { 367static struct pxafb_mach_info sharp_lq64d343 = {
332 .modes = &sharp_lq64d343_mode, 368 .modes = &sharp_lq64d343_mode,
333 .num_modes = 1, 369 .num_modes = 1,
334 .lccr0 = 0x07800080, 370 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
335 .lccr3 = 0x00400000, 371 LCD_ALTERNATE_MAPPING,
336}; 372};
337 373
338/* 10.4" TFT VGA (LoLo display number 7) */ 374/* 10.4" TFT VGA (LoLo display number 7) */
@@ -353,8 +389,8 @@ static struct pxafb_mode_info sharp_lq10d368_mode = {
353static struct pxafb_mach_info sharp_lq10d368 = { 389static struct pxafb_mach_info sharp_lq10d368 = {
354 .modes = &sharp_lq10d368_mode, 390 .modes = &sharp_lq10d368_mode,
355 .num_modes = 1, 391 .num_modes = 1,
356 .lccr0 = 0x07800080, 392 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
357 .lccr3 = 0x00400000, 393 LCD_ALTERNATE_MAPPING,
358}; 394};
359 395
360/* 3.5" TFT QVGA (LoLo display number 8) */ 396/* 3.5" TFT QVGA (LoLo display number 8) */
@@ -375,8 +411,8 @@ static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
375static struct pxafb_mach_info sharp_lq035q7db02_20 = { 411static struct pxafb_mach_info sharp_lq035q7db02_20 = {
376 .modes = &sharp_lq035q7db02_20_mode, 412 .modes = &sharp_lq035q7db02_20_mode,
377 .num_modes = 1, 413 .num_modes = 1,
378 .lccr0 = 0x07800080, 414 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
379 .lccr3 = 0x00400000, 415 LCD_ALTERNATE_MAPPING,
380}; 416};
381 417
382static struct pxafb_mach_info *lpd270_lcd_to_use; 418static struct pxafb_mach_info *lpd270_lcd_to_use;
@@ -411,27 +447,15 @@ static struct platform_device *platform_devices[] __initdata = {
411 &lpd270_flash_device[1], 447 &lpd270_flash_device[1],
412}; 448};
413 449
414static int lpd270_ohci_init(struct device *dev)
415{
416 /* setup Port1 GPIO pin. */
417 pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
418 pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
419
420 /* Set the Power Control Polarity Low and Power Sense
421 Polarity Low to active low. */
422 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
423 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
424
425 return 0;
426}
427
428static struct pxaohci_platform_data lpd270_ohci_platform_data = { 450static struct pxaohci_platform_data lpd270_ohci_platform_data = {
429 .port_mode = PMM_PERPORT_MODE, 451 .port_mode = PMM_PERPORT_MODE,
430 .init = lpd270_ohci_init, 452 .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
431}; 453};
432 454
433static void __init lpd270_init(void) 455static void __init lpd270_init(void)
434{ 456{
457 pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
458
435 lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; 459 lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
436 lpd270_flash_data[1].width = 4; 460 lpd270_flash_data[1].width = 4;
437 461
@@ -442,12 +466,6 @@ static void __init lpd270_init(void)
442 */ 466 */
443 ARB_CNTRL = ARB_CORE_PARK | 0x234; 467 ARB_CNTRL = ARB_CORE_PARK | 0x234;
444 468
445 /*
446 * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
447 */
448 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
449 pxa_gpio_mode(GPIO16_PWM0_MD);
450
451 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 469 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
452 470
453 pxa_set_ac97_info(NULL); 471 pxa_set_ac97_info(NULL);
@@ -473,15 +491,6 @@ static void __init lpd270_map_io(void)
473 pxa_map_io(); 491 pxa_map_io();
474 iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); 492 iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
475 493
476 /* initialize sleep mode regs (wake-up sources, etc) */
477 PGSR0 = 0x00008800;
478 PGSR1 = 0x00000002;
479 PGSR2 = 0x0001FC00;
480 PGSR3 = 0x00001F81;
481 PWER = 0xC0000002;
482 PRER = 0x00000002;
483 PFER = 0x00000002;
484
485 /* for use I SRAM as framebuffer. */ 494 /* for use I SRAM as framebuffer. */
486 PSLR |= 0x00000F04; 495 PSLR |= 0x00000F04;
487 PCFR = 0x00000066; 496 PCFR = 0x00000066;