1 files changed, 50 insertions, 56 deletions

diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 4619d5fe606c..4b867b0789d5 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -30,12 +30,12 @@
 
 static void pxa_mask_low_irq(unsigned int irq)
 {
-        ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
+        ICMR &= ~(1 << irq);
 }
 
 static void pxa_unmask_low_irq(unsigned int irq)
 {
-        ICMR |= (1 << (irq + PXA_IRQ_SKIP));
+        ICMR |= (1 << irq);
 }
 
 static int pxa_set_wake(unsigned int irq, unsigned int on)
@@ -67,7 +67,27 @@ static struct irq_chip pxa_internal_chip_low = {
         .set_wake       = pxa_set_wake,
 };
 
-#if PXA_INTERNAL_IRQS > 32
+void __init pxa_init_irq_low(void)
+{
+        int irq;
+
+        /* disable all IRQs */
+        ICMR = 0;
+
+        /* all IRQs are IRQ, not FIQ */
+        ICLR = 0;
+
+        /* only unmasked interrupts kick us out of idle */
+        ICCR = 1;
+
+        for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
+                set_irq_chip(irq, &pxa_internal_chip_low);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
+
+#ifdef CONFIG_PXA27x
 
 /*
  * This is for the second set of internal IRQs as found on the PXA27x.
@@ -75,12 +95,12 @@ static struct irq_chip pxa_internal_chip_low = {
 
 static void pxa_mask_high_irq(unsigned int irq)
 {
-        ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP));
+        ICMR2 &= ~(1 << (irq - 32));
 }
 
 static void pxa_unmask_high_irq(unsigned int irq)
 {
-        ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP));
+        ICMR2 |= (1 << (irq - 32));
 }
 
 static struct irq_chip pxa_internal_chip_high = {
@@ -90,6 +110,19 @@ static struct irq_chip pxa_internal_chip_high = {
         .unmask         = pxa_unmask_high_irq,
 };
 
+void __init pxa_init_irq_high(void)
+{
+        int irq;
+
+        ICMR2 = 0;
+        ICLR2 = 0;
+
+        for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
+                set_irq_chip(irq, &pxa_internal_chip_high);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
 #endif
 
 /* Note that if an input/irq line ever gets changed to an output during
@@ -217,7 +250,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
         do {
                 loop = 0;
 
-                mask = GEDR0 & ~3;
+                mask = GEDR0 & GPIO_IRQ_mask[0] & ~3;
                 if (mask) {
                         GEDR0 = mask;
                         irq = IRQ_GPIO(2);
@@ -233,7 +266,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                         loop = 1;
                 }
 
-                mask = GEDR1;
+                mask = GEDR1 & GPIO_IRQ_mask[1];
                 if (mask) {
                         GEDR1 = mask;
                         irq = IRQ_GPIO(32);
@@ -248,7 +281,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                         loop = 1;
                 }
 
-                mask = GEDR2;
+                mask = GEDR2 & GPIO_IRQ_mask[2];
                 if (mask) {
                         GEDR2 = mask;
                         irq = IRQ_GPIO(64);
@@ -263,8 +296,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                         loop = 1;
                 }
 
-#if PXA_LAST_GPIO >= 96
-                mask = GEDR3;
+                mask = GEDR3 & GPIO_IRQ_mask[3];
                 if (mask) {
                         GEDR3 = mask;
                         irq = IRQ_GPIO(96);
@@ -278,7 +310,6 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                         } while (mask);
                         loop = 1;
                 }
-#endif
         } while (loop);
 }
 
@@ -314,64 +345,27 @@ static struct irq_chip pxa_muxed_gpio_chip = {
         .set_wake       = pxa_set_gpio_wake,
 };
 
-
-void __init pxa_init_irq(void)
+void __init pxa_init_irq_gpio(int gpio_nr)
 {
-        int irq;
-
-        /* disable all IRQs */
-        ICMR = 0;
-
-        /* all IRQs are IRQ, not FIQ */
-        ICLR = 0;
+        int irq, i;
 
         /* clear all GPIO edge detects */
-        GFER0 = 0;
-        GFER1 = 0;
-        GFER2 = 0;
-        GRER0 = 0;
-        GRER1 = 0;
-        GRER2 = 0;
-        GEDR0 = GEDR0;
-        GEDR1 = GEDR1;
-        GEDR2 = GEDR2;
-
-#ifdef CONFIG_PXA27x
-        /* And similarly for the extra regs on the PXA27x */
-        ICMR2 = 0;
-        ICLR2 = 0;
-        GFER3 = 0;
-        GRER3 = 0;
-        GEDR3 = GEDR3;
-#endif
-
-        /* only unmasked interrupts kick us out of idle */
-        ICCR = 1;
+        for (i = 0; i < gpio_nr; i += 32) {
+                GFER(i) = 0;
+                GRER(i) = 0;
+                GEDR(i) = GEDR(i);
+        }
 
         /* GPIO 0 and 1 must have their mask bit always set */
         GPIO_IRQ_mask[0] = 3;
 
-        for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
-                set_irq_chip(irq, &pxa_internal_chip_low);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-
-#if PXA_INTERNAL_IRQS > 32
-        for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
-                set_irq_chip(irq, &pxa_internal_chip_high);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-#endif
-
         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
                 set_irq_chip(irq, &pxa_low_gpio_chip);
                 set_irq_handler(irq, handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
+        for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(gpio_nr); irq++) {
                 set_irq_chip(irq, &pxa_muxed_gpio_chip);
                 set_irq_handler(irq, handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);