diff options
Diffstat (limited to 'arch/arm/mach-pxa/irq.c')
-rw-r--r-- | arch/arm/mach-pxa/irq.c | 41 |
1 files changed, 17 insertions, 24 deletions
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 42b2da2f213e..256f8d2b3d9b 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -347,43 +347,27 @@ static struct irq_chip pxa_muxed_gpio_chip = { | |||
347 | .set_wake = pxa_set_gpio_wake, | 347 | .set_wake = pxa_set_gpio_wake, |
348 | }; | 348 | }; |
349 | 349 | ||
350 | void __init pxa_init_irq(void) | 350 | void __init pxa_init_irq_gpio(int gpio_nr) |
351 | { | 351 | { |
352 | int irq; | 352 | int irq, i; |
353 | 353 | ||
354 | /* clear all GPIO edge detects */ | 354 | /* clear all GPIO edge detects */ |
355 | GFER0 = 0; | 355 | for (i = 0; i < gpio_nr; i += 32) { |
356 | GFER1 = 0; | 356 | GFER(i) = 0; |
357 | GFER2 = 0; | 357 | GRER(i) = 0; |
358 | GRER0 = 0; | 358 | GEDR(i) = GEDR(i); |
359 | GRER1 = 0; | 359 | } |
360 | GRER2 = 0; | ||
361 | GEDR0 = GEDR0; | ||
362 | GEDR1 = GEDR1; | ||
363 | GEDR2 = GEDR2; | ||
364 | |||
365 | #ifdef CONFIG_PXA27x | ||
366 | /* And similarly for the extra regs on the PXA27x */ | ||
367 | GFER3 = 0; | ||
368 | GRER3 = 0; | ||
369 | GEDR3 = GEDR3; | ||
370 | #endif | ||
371 | 360 | ||
372 | /* GPIO 0 and 1 must have their mask bit always set */ | 361 | /* GPIO 0 and 1 must have their mask bit always set */ |
373 | GPIO_IRQ_mask[0] = 3; | 362 | GPIO_IRQ_mask[0] = 3; |
374 | 363 | ||
375 | pxa_init_irq_low(); | ||
376 | #ifdef CONFIG_PXA27x | ||
377 | pxa_init_irq_high(); | ||
378 | #endif | ||
379 | |||
380 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | 364 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { |
381 | set_irq_chip(irq, &pxa_low_gpio_chip); | 365 | set_irq_chip(irq, &pxa_low_gpio_chip); |
382 | set_irq_handler(irq, handle_edge_irq); | 366 | set_irq_handler(irq, handle_edge_irq); |
383 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 367 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
384 | } | 368 | } |
385 | 369 | ||
386 | for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) { | 370 | for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(gpio_nr); irq++) { |
387 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | 371 | set_irq_chip(irq, &pxa_muxed_gpio_chip); |
388 | set_irq_handler(irq, handle_edge_irq); | 372 | set_irq_handler(irq, handle_edge_irq); |
389 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 373 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
@@ -393,3 +377,12 @@ void __init pxa_init_irq(void) | |||
393 | set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); | 377 | set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); |
394 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | 378 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); |
395 | } | 379 | } |
380 | |||
381 | void __init pxa_init_irq(void) | ||
382 | { | ||
383 | pxa_init_irq_low(); | ||
384 | #ifdef CONFIG_PXA27x | ||
385 | pxa_init_irq_high(); | ||
386 | #endif | ||
387 | pxa_init_irq_gpio(PXA_LAST_GPIO + 1); | ||
388 | } | ||