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-rw-r--r--arch/arm/mach-pxa/include/mach/pxa25x.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa27x.h19
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h20
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa300.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa320.h9
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa930.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ssp.h1
8 files changed, 56 insertions, 19 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h
new file mode 100644
index 000000000000..508c3ba1f4d0
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa25x.h
@@ -0,0 +1,8 @@
1#ifndef __MACH_PXA25x_H
2#define __MACH_PXA25x_H
3
4#include <mach/hardware.h>
5#include <mach/pxa2xx-regs.h>
6#include <mach/mfp-pxa25x.h>
7
8#endif /* __MACH_PXA25x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h
new file mode 100644
index 000000000000..6876e16c2970
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa27x.h
@@ -0,0 +1,19 @@
1#ifndef __MACH_PXA27x_H
2#define __MACH_PXA27x_H
3
4#include <mach/hardware.h>
5#include <mach/pxa2xx-regs.h>
6#include <mach/mfp-pxa27x.h>
7
8#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
9
10#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
11#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
12#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
13#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
14#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
15#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
16#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
17#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
18#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
19#endif /* __MACH_PXA27x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 77102d695cc7..0b4ffd05a39a 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -14,6 +14,8 @@
14#ifndef __PXA2XX_REGS_H 14#ifndef __PXA2XX_REGS_H
15#define __PXA2XX_REGS_H 15#define __PXA2XX_REGS_H
16 16
17#include <mach/pxa-regs.h>
18
17/* 19/*
18 * Memory controller 20 * Memory controller
19 */ 21 */
@@ -69,24 +71,6 @@
69#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ 71#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
70#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ 72#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
71 73
72
73#ifdef CONFIG_PXA27x
74
75#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
76
77#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
78#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
79#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
80#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
81#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
82#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
83#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
84#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
85#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
86
87#endif
88
89
90/* 74/*
91 * Power Manager 75 * Power Manager
92 */ 76 */
diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h
new file mode 100644
index 000000000000..2f33076c9e48
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa300.h
@@ -0,0 +1,8 @@
1#ifndef __MACH_PXA300_H
2#define __MACH_PXA300_H
3
4#include <mach/hardware.h>
5#include <mach/pxa3xx-regs.h>
6#include <mach/mfp-pxa300.h>
7
8#endif /* __MACH_PXA300_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h
new file mode 100644
index 000000000000..cab78e903273
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa320.h
@@ -0,0 +1,9 @@
1#ifndef __MACH_PXA320_H
2#define __MACH_PXA320_H
3
4#include <mach/hardware.h>
5#include <mach/pxa3xx-regs.h>
6#include <mach/mfp-pxa320.h>
7
8#endif /* __MACH_PXA320_H */
9
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index bcf3fb2c4b3a..15b3b0be7f58 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_PXA3XX_REGS_H 13#ifndef __ASM_ARCH_PXA3XX_REGS_H
14#define __ASM_ARCH_PXA3XX_REGS_H 14#define __ASM_ARCH_PXA3XX_REGS_H
15 15
16#include <mach/hardware.h>
17
16/* 18/*
17 * Oscillator Configuration Register (OSCC) 19 * Oscillator Configuration Register (OSCC)
18 */ 20 */
diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h
new file mode 100644
index 000000000000..d45f76a9b54d
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa930.h
@@ -0,0 +1,8 @@
1#ifndef __MACH_PXA930_H
2#define __MACH_PXA930_H
3
4#include <mach/hardware.h>
5#include <mach/pxa3xx-regs.h>
6#include <mach/mfp-pxa930.h>
7
8#endif /* __MACH_PXA930_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
index cf31986f6f05..8152be683881 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h
@@ -37,7 +37,6 @@
37#if defined(CONFIG_PXA25x) 37#if defined(CONFIG_PXA25x)
38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ 38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ 39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
40
41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 40#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ 41#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ 42#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */