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-rw-r--r--arch/arm/mach-pxa/include/mach/akita.h32
-rw-r--r--arch/arm/mach-pxa/include/mach/corgi.h11
-rw-r--r--arch/arm/mach-pxa/include/mach/littleton.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/memory.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa25x.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa320.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp.h5
-rw-r--r--arch/arm/mach-pxa/include/mach/mioa701.h67
-rw-r--r--arch/arm/mach-pxa/include/mach/palmz72.h67
-rw-r--r--arch/arm/mach-pxa/include/mach/poodle.h9
-rw-r--r--arch/arm/mach-pxa/include/mach/spitz.h42
-rw-r--r--arch/arm/mach-pxa/include/mach/trizeps4.h84
-rw-r--r--arch/arm/mach-pxa/include/mach/viper.h96
13 files changed, 369 insertions, 62 deletions
diff --git a/arch/arm/mach-pxa/include/mach/akita.h b/arch/arm/mach-pxa/include/mach/akita.h
deleted file mode 100644
index 5d8cc1d9cb10..000000000000
--- a/arch/arm/mach-pxa/include/mach/akita.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * Hardware specific definitions for SL-C1000 (Akita)
3 *
4 * Copyright (c) 2005 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/* Akita IO Expander GPIOs */
13
14#define AKITA_IOEXP_RESERVED_7 (1 << 7)
15#define AKITA_IOEXP_IR_ON (1 << 6)
16#define AKITA_IOEXP_AKIN_PULLUP (1 << 5)
17#define AKITA_IOEXP_BACKLIGHT_CONT (1 << 4)
18#define AKITA_IOEXP_BACKLIGHT_ON (1 << 3)
19#define AKITA_IOEXP_MIC_BIAS (1 << 2)
20#define AKITA_IOEXP_RESERVED_1 (1 << 1)
21#define AKITA_IOEXP_RESERVED_0 (1 << 0)
22
23/* Direction Bitfield 0=output 1=input */
24#define AKITA_IOEXP_IO_DIR 0
25/* Default Values */
26#define AKITA_IOEXP_IO_OUT (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP)
27
28extern struct platform_device akitaioexp_device;
29
30void akita_set_ioexp(struct device *dev, unsigned char bitmask);
31void akita_reset_ioexp(struct device *dev, unsigned char bitmask);
32
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index bf856503baf6..585970ef08ce 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -98,12 +98,21 @@
98 CORGI_SCP_MIC_BIAS ) 98 CORGI_SCP_MIC_BIAS )
99#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) 99#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
100 100
101#define CORGI_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO)
102#define CORGI_GPIO_LED_GREEN (CORGI_SCOOP_GPIO_BASE + 0)
103#define CORGI_GPIO_SWA (CORGI_SCOOP_GPIO_BASE + 1) /* Hinge Switch A */
104#define CORGI_GPIO_SWB (CORGI_SCOOP_GPIO_BASE + 2) /* Hinge Switch B */
105#define CORGI_GPIO_MUTE_L (CORGI_SCOOP_GPIO_BASE + 3)
106#define CORGI_GPIO_MUTE_R (CORGI_SCOOP_GPIO_BASE + 4)
107#define CORGI_GPIO_AKIN_PULLUP (CORGI_SCOOP_GPIO_BASE + 5)
108#define CORGI_GPIO_APM_ON (CORGI_SCOOP_GPIO_BASE + 6)
109#define CORGI_GPIO_BACKLIGHT_CONT (CORGI_SCOOP_GPIO_BASE + 7)
110#define CORGI_GPIO_MIC_BIAS (CORGI_SCOOP_GPIO_BASE + 8)
101 111
102/* 112/*
103 * Shared data structures 113 * Shared data structures
104 */ 114 */
105extern struct platform_device corgiscoop_device; 115extern struct platform_device corgiscoop_device;
106extern struct platform_device corgissp_device;
107 116
108#endif /* __ASM_ARCH_CORGI_H */ 117#endif /* __ASM_ARCH_CORGI_H */
109 118
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 79d209b826f4..5c4e320c1437 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -3,4 +3,6 @@
3 3
4#define LITTLETON_ETH_PHYS 0x30000000 4#define LITTLETON_ETH_PHYS 0x30000000
5 5
6#define LITTLETON_GPIO_LCD_CS (17)
7
6#endif /* __ASM_ARCH_ZYLONITE_H */ 8#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 552eb7fa6579..59aef89808d6 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -40,11 +40,11 @@
40#define NODE_MEM_SIZE_BITS 26 40#define NODE_MEM_SIZE_BITS 26
41 41
42#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) 42#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
43void cmx270_pci_adjust_zones(int node, unsigned long *size, 43void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
44 unsigned long *holes); 44 unsigned long *holes);
45 45
46#define arch_adjust_zones(node, size, holes) \ 46#define arch_adjust_zones(node, size, holes) \
47 cmx270_pci_adjust_zones(node, size, holes) 47 cmx2xx_pci_adjust_zones(node, size, holes)
48 48
49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) 49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
50#endif 50#endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index 6c8e72238bfd..617cab2cc8d0 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -17,7 +17,7 @@
17 17
18/* Crystal and Clock Signals */ 18/* Crystal and Clock Signals */
19#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) 19#define GPIO10_RTCCLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
20#define GPIO70_RTC_CLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW) 20#define GPIO70_RTCCLK MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
21#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW) 21#define GPIO7_48MHz MFP_CFG_OUT(GPIO7, AF1, DRIVE_LOW)
22#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) 22#define GPIO11_3_6MHz MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
23#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW) 23#define GPIO71_3_6MHz MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
@@ -156,6 +156,6 @@
156#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) 156#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
157#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) 157#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) 158#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
159#define GPIO77_LCD_ACBIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) 159#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
160 160
161#endif /* __ASM_ARCH_MFP_PXA25X_H */ 161#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
index 74990510cf34..67f8385ea548 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
@@ -257,10 +257,10 @@
257#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) 257#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2)
258#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) 258#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5)
259 259
260#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT) 260#define GPIO69_SSP3_SCLK MFP_CFG_X(GPIO69, AF2, DS08X, FLOAT)
261#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW) 261#define GPIO70_SSP3_FRM MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
262#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT) 262#define GPIO89_SSP3_SCLK MFP_CFG_X(GPIO89, AF1, DS08X, FLOAT)
263#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW) 263#define GPIO90_SSP3_FRM MFP_CFG_X(GPIO90, AF1, DS08X, DRIVE_LOW)
264#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) 264#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
265#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) 265#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
266#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) 266#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h
index 8769567b389b..482185053a92 100644
--- a/arch/arm/mach-pxa/include/mach/mfp.h
+++ b/arch/arm/mach-pxa/include/mach/mfp.h
@@ -274,12 +274,13 @@ typedef unsigned long mfp_cfg_t;
274#define MFP_DS_MASK (0x7 << 13) 274#define MFP_DS_MASK (0x7 << 13)
275#define MFP_DS(x) (((x) >> 13) & 0x7) 275#define MFP_DS(x) (((x) >> 13) & 0x7)
276 276
277#define MFP_LPM_INPUT (0x0 << 16) 277#define MFP_LPM_DEFAULT (0x0 << 16)
278#define MFP_LPM_DRIVE_LOW (0x1 << 16) 278#define MFP_LPM_DRIVE_LOW (0x1 << 16)
279#define MFP_LPM_DRIVE_HIGH (0x2 << 16) 279#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
280#define MFP_LPM_PULL_LOW (0x3 << 16) 280#define MFP_LPM_PULL_LOW (0x3 << 16)
281#define MFP_LPM_PULL_HIGH (0x4 << 16) 281#define MFP_LPM_PULL_HIGH (0x4 << 16)
282#define MFP_LPM_FLOAT (0x5 << 16) 282#define MFP_LPM_FLOAT (0x5 << 16)
283#define MFP_LPM_INPUT (0x6 << 16)
283#define MFP_LPM_STATE_MASK (0x7 << 16) 284#define MFP_LPM_STATE_MASK (0x7 << 16)
284#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) 285#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
285 286
@@ -297,7 +298,7 @@ typedef unsigned long mfp_cfg_t;
297#define MFP_PULL_MASK (0x3 << 21) 298#define MFP_PULL_MASK (0x3 << 21)
298#define MFP_PULL(x) (((x) >> 21) & 0x3) 299#define MFP_PULL(x) (((x) >> 21) & 0x3)
299 300
300#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\ 301#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
301 MFP_LPM_EDGE_NONE | MFP_PULL_NONE) 302 MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
302 303
303#define MFP_CFG(pin, af) \ 304#define MFP_CFG(pin, af) \
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h
new file mode 100644
index 000000000000..8483cb511831
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/mioa701.h
@@ -0,0 +1,67 @@
1#ifndef _MIOA701_H_
2#define _MIOA701_H_
3
4#define MIO_CFG_IN(pin, af) \
5 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
6 (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN))
7
8#define MIO_CFG_OUT(pin, af, state) \
9 ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
10 (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
11
12/* Global GPIOs */
13#define GPIO9_CHARGE_nEN 9
14#define GPIO18_POWEROFF 18
15#define GPIO87_LCD_POWER 87
16
17/* USB */
18#define GPIO13_USB_DETECT 13
19#define GPIO22_USB_ENABLE 22
20
21/* SDIO bits */
22#define GPIO78_SDIO_RO 78
23#define GPIO15_SDIO_INSERT 15
24#define GPIO91_SDIO_EN 91
25
26/* Bluetooth */
27#define GPIO83_BT_ON 83
28
29/* GPS */
30#define GPIO23_GPS_UNKNOWN1 23
31#define GPIO26_GPS_ON 26
32#define GPIO27_GPS_RESET 27
33#define GPIO106_GPS_UNKNOWN2 106
34#define GPIO107_GPS_UNKNOWN3 107
35
36/* GSM */
37#define GPIO24_GSM_MOD_RESET_CMD 24
38#define GPIO88_GSM_nMOD_ON_CMD 88
39#define GPIO90_GSM_nMOD_OFF_CMD 90
40#define GPIO114_GSM_nMOD_DTE_UART_STATE 114
41#define GPIO25_GSM_MOD_ON_STATE 25
42#define GPIO113_GSM_EVENT 113
43
44/* SOUND */
45#define GPIO12_HPJACK_INSERT 12
46
47/* LEDS */
48#define GPIO10_LED_nCharging 10
49#define GPIO97_LED_nBlue 97
50#define GPIO98_LED_nOrange 98
51#define GPIO82_LED_nVibra 82
52#define GPIO115_LED_nKeyboard 115
53
54/* Keyboard */
55#define GPIO0_KEY_POWER 0
56#define GPIO93_KEY_VOLUME_UP 93
57#define GPIO94_KEY_VOLUME_DOWN 94
58
59extern struct input_dev *mioa701_evdev;
60extern void mioa701_gpio_lpm_set(unsigned long mfp_pin);
61
62/* Assembler externals mioa701_bootresume.S */
63extern u32 mioa701_bootstrap;
64extern u32 mioa701_jumpaddr;
65extern u32 mioa701_bootstrap_lg;
66
67#endif /* _MIOA701_H */
diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h
new file mode 100644
index 000000000000..8fd30bcecb7c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmz72.h
@@ -0,0 +1,67 @@
1/*
2 * GPIOs and interrupts for Palm Zire72 Handheld Computer
3 *
4 * Authors: Alex Osborne <bobofdoom@gmail.com>
5 * Jan Herman <2hp@seznam.cz>
6 * Sergey Lapin <slapin@ossfans.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef _INCLUDE_PALMZ72_H_
15#define _INCLUDE_PALMZ72_H_
16
17/* Power and control */
18#define GPIO_NR_PALMZ72_GPIO_RESET 1
19#define GPIO_NR_PALMZ72_POWER_DETECT 0
20
21/* SD/MMC */
22#define GPIO_NR_PALMZ72_SD_DETECT_N 14
23#define GPIO_NR_PALMZ72_SD_POWER_N 98
24#define GPIO_NR_PALMZ72_SD_RO 115
25
26/* Touchscreen */
27#define GPIO_NR_PALMZ72_WM9712_IRQ 27
28
29/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
30#define GPIO_NR_PALMZ72_IR_DISABLE 49
31
32/* USB */
33#define GPIO_NR_PALMZ72_USB_DETECT_N 15
34#define GPIO_NR_PALMZ72_USB_POWER 95
35#define GPIO_NR_PALMZ72_USB_PULLUP 12
36
37/* LCD/Backlight */
38#define GPIO_NR_PALMZ72_BL_POWER 20
39#define GPIO_NR_PALMZ72_LCD_POWER 96
40
41/* LED */
42#define GPIO_NR_PALMZ72_LED_GREEN 88
43
44/* Bluetooth */
45#define GPIO_NR_PALMZ72_BT_POWER 17
46#define GPIO_NR_PALMZ72_BT_RESET 83
47
48/** Initial values **/
49
50/* Battery */
51#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
52#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
53#define PALMZ72_BAT_MAX_CURRENT 0 /* unknokn */
54#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */
55#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */
56#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */
57#define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */
58
59/* Backlight */
60#define PALMZ72_MAX_INTENSITY 0xFE
61#define PALMZ72_DEFAULT_INTENSITY 0x7E
62#define PALMZ72_LIMIT_MASK 0x7F
63#define PALMZ72_PRESCALER 0x3F
64#define PALMZ72_PERIOD_NS 3500
65
66#endif
67
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 67debc47e8c6..0b3e6d051c64 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -23,6 +23,7 @@
23#define POODLE_GPIO_AC_IN (1) 23#define POODLE_GPIO_AC_IN (1)
24#define POODLE_GPIO_CO 16 24#define POODLE_GPIO_CO 16
25#define POODLE_GPIO_TP_INT (5) 25#define POODLE_GPIO_TP_INT (5)
26#define POODLE_GPIO_TP_CS (24)
26#define POODLE_GPIO_WAKEUP (11) /* change battery */ 27#define POODLE_GPIO_WAKEUP (11) /* change battery */
27#define POODLE_GPIO_GA_INT (10) 28#define POODLE_GPIO_GA_INT (10)
28#define POODLE_GPIO_IR_ON (22) 29#define POODLE_GPIO_IR_ON (22)
@@ -70,6 +71,14 @@
70#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) 71#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
71#define POODLE_SCOOP_IO_OUT ( 0 ) 72#define POODLE_SCOOP_IO_OUT ( 0 )
72 73
74#define POODLE_SCOOP_GPIO_BASE (NR_BUILTIN_GPIO)
75#define POODLE_GPIO_CHARGE_ON (POODLE_SCOOP_GPIO_BASE + 0)
76#define POODLE_GPIO_CP401 (POODLE_SCOOP_GPIO_BASE + 2)
77#define POODLE_GPIO_VPEN (POODLE_SCOOP_GPIO_BASE + 7)
78#define POODLE_GPIO_L_PCLK (POODLE_SCOOP_GPIO_BASE + 9)
79#define POODLE_GPIO_L_LCLK (POODLE_SCOOP_GPIO_BASE + 10)
80#define POODLE_GPIO_HS_OUT (POODLE_SCOOP_GPIO_BASE + 11)
81
73#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8) 82#define POODLE_LOCOMO_GPIO_AMP_ON LOCOMO_GPIO(8)
74#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10) 83#define POODLE_LOCOMO_GPIO_MUTE_L LOCOMO_GPIO(10)
75#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11) 84#define POODLE_LOCOMO_GPIO_MUTE_R LOCOMO_GPIO(11)
diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index bd14365f7ed5..31ac26b55bc1 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -16,6 +16,7 @@
16#endif 16#endif
17 17
18#include <linux/fb.h> 18#include <linux/fb.h>
19#include <linux/gpio.h>
19 20
20/* Spitz/Akita GPIOs */ 21/* Spitz/Akita GPIOs */
21 22
@@ -100,13 +101,24 @@
100#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */ 101#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */
101#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */ 102#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */
102 103
103#define SPITZ_SCP_IO_DIR (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \ 104#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
104 SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \ 105 SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \
105 SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) 106 SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
106#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R) 107#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
107#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) 108#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
108#define SPITZ_SCP_SUS_SET 0 109#define SPITZ_SCP_SUS_SET 0
109 110
111#define SPITZ_SCP_GPIO_BASE (NR_BUILTIN_GPIO)
112#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0)
113#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1)
114#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2)
115#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3)
116#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4)
117#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5)
118#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6)
119#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7)
120#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8)
121
110/* Spitz Scoop Device (No. 2) GPIOs */ 122/* Spitz Scoop Device (No. 2) GPIOs */
111/* Suspend States in comments */ 123/* Suspend States in comments */
112#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */ 124#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */
@@ -119,15 +131,36 @@
119#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */ 131#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */
120#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */ 132#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */
121 133
122#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \ 134#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
123 SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ 135 SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
124 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) 136 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
125 137
126#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1) 138#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
127#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ 139#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
128 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) 140 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
129#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) 141#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
130 142
143#define SPITZ_SCP2_GPIO_BASE (NR_BUILTIN_GPIO + 12)
144#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0)
145#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1
146#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2)
147#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3)
148#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4)
149#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5)
150#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6)
151#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7)
152#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8)
153
154/* Akita IO Expander GPIOs */
155#define AKITA_IOEXP_GPIO_BASE (NR_BUILTIN_GPIO + 12)
156#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0)
157#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1)
158#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2)
159#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3)
160#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4)
161#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5)
162#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6)
163#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7)
131 164
132/* Spitz IRQ Definitions */ 165/* Spitz IRQ Definitions */
133 166
@@ -154,5 +187,4 @@
154 */ 187 */
155extern struct platform_device spitzscoop_device; 188extern struct platform_device spitzscoop_device;
156extern struct platform_device spitzscoop2_device; 189extern struct platform_device spitzscoop2_device;
157extern struct platform_device spitzssp_device;
158extern struct sharpsl_charger_machinfo spitz_pm_machinfo; 190extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
index 641d0ec110bb..903e1a2e6641 100644
--- a/arch/arm/mach-pxa/include/mach/trizeps4.h
+++ b/arch/arm/mach-pxa/include/mach/trizeps4.h
@@ -17,11 +17,16 @@
17#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ 17#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */
18#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ 18#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */
19 19
20#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */ 20 /* Logic on ConXS-board CSFR register*/
21#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */ 21#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS)
22#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/ 22 /* Logic on ConXS-board BOCR register*/
23#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/ 23#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000)
24#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/ 24 /* Logic on ConXS-board IRCR register*/
25#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000)
26 /* Logic on ConXS-board UPSR register*/
27#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000)
28 /* Logic on ConXS-board DICR register*/
29#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000)
25 30
26/* virtual memory regions */ 31/* virtual memory regions */
27#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ 32#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */
@@ -54,6 +59,15 @@
54#define GPIO_MMC_DET 12 59#define GPIO_MMC_DET 12
55#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) 60#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET)
56 61
62/* DOC NAND chip */
63#define GPIO_DOC_LOCK 94
64#define GPIO_DOC_IRQ 93
65#define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ)
66
67/* SPI interface */
68#define GPIO_SPI 53
69#define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI)
70
57/* LEDS using tx2 / rx2 */ 71/* LEDS using tx2 / rx2 */
58#define GPIO_SYS_BUSY_LED 46 72#define GPIO_SYS_BUSY_LED 46
59#define GPIO_HEARTBEAT_LED 47 73#define GPIO_HEARTBEAT_LED 47
@@ -62,24 +76,66 @@
62#define GPIO_PIC 0 76#define GPIO_PIC 0
63#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) 77#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC)
64 78
65#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) 79#ifdef CONFIG_MACH_TRIZEPS_CONXS
66#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) 80/* for CONXS base board define these registers */
81#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
82#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
67 83
68#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) 84#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
69#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) 85#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
70 86
71#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) 87#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
72#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) 88#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
89
90#define IRCR_P2V(x) ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
91#define IRCR_V2P(x) ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
73 92
74#ifndef __ASSEMBLY__ 93#ifndef __ASSEMBLY__
75#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000))) 94static inline unsigned short CFSR_readw(void)
76#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000))) 95{
77#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000))) 96 /* [Compact Flash Status Register] is read only */
97 return *((unsigned short *)CFSR_P2V(0x0C000000));
98}
99static inline void BCR_writew(unsigned short value)
100{
101 /* [Board Control Regsiter] is write only */
102 *((unsigned short *)BCR_P2V(0x0E000000)) = value;
103}
104static inline void DCR_writew(unsigned short value)
105{
106 /* [Display Control Register] is write only */
107 *((unsigned short *)DCR_P2V(0x0E000000)) = value;
108}
109static inline void IRCR_writew(unsigned short value)
110{
111 /* [InfraRed data Control Register] is write only */
112 *((unsigned short *)IRCR_P2V(0x0E000000)) = value;
113}
78#else 114#else
79#define ConXS_CFSR CFSR_P2V(0x0C000000) 115#define ConXS_CFSR CFSR_P2V(0x0C000000)
80#define ConXS_BCR BCR_P2V(0x0E000000) 116#define ConXS_BCR BCR_P2V(0x0E000000)
81#define ConXS_DCR DCR_P2V(0x0F800000) 117#define ConXS_DCR DCR_P2V(0x0F800000)
118#define ConXS_IRCR IRCR_P2V(0x0F800000)
82#endif 119#endif
120#else
121/* for whatever baseboard define function registers */
122static inline unsigned short CFSR_readw(void)
123{
124 return 0;
125}
126static inline void BCR_writew(unsigned short value)
127{
128 ;
129}
130static inline void DCR_writew(unsigned short value)
131{
132 ;
133}
134static inline void IRCR_writew(unsigned short value)
135{
136 ;
137}
138#endif /* CONFIG_MACH_TRIZEPS_CONXS */
83 139
84#define ConXS_CFSR_BVD_MASK 0x0003 140#define ConXS_CFSR_BVD_MASK 0x0003
85#define ConXS_CFSR_BVD1 (1 << 0) 141#define ConXS_CFSR_BVD1 (1 << 0)
diff --git a/arch/arm/mach-pxa/include/mach/viper.h b/arch/arm/mach-pxa/include/mach/viper.h
new file mode 100644
index 000000000000..10988c270ca3
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/viper.h
@@ -0,0 +1,96 @@
1/*
2 * arch/arm/mach-pxa/include/mach/viper.h
3 *
4 * Author: Ian Campbell
5 * Created: Feb 03, 2003
6 * Copyright: Arcom Control Systems.
7 *
8 * Maintained by Marc Zyngier <maz@misterjones.org>
9 * <marc.zyngier@altran.com>
10 *
11 * Created based on lubbock.h:
12 * Author: Nicolas Pitre
13 * Created: Jun 15, 2001
14 * Copyright: MontaVista Software Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef ARCH_VIPER_H
22#define ARCH_VIPER_H
23
24#define VIPER_BOOT_PHYS PXA_CS0_PHYS
25#define VIPER_FLASH_PHYS PXA_CS1_PHYS
26#define VIPER_ETH_PHYS PXA_CS2_PHYS
27#define VIPER_USB_PHYS PXA_CS3_PHYS
28#define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS
29#define VIPER_CPLD_PHYS PXA_CS5_PHYS
30
31#define VIPER_CPLD_BASE (0xf0000000)
32#define VIPER_PC104IO_BASE (0xf1000000)
33#define VIPER_USB_BASE (0xf1800000)
34
35#define VIPER_ETH_GPIO (0)
36#define VIPER_CPLD_GPIO (1)
37#define VIPER_USB_GPIO (2)
38#define VIPER_UARTA_GPIO (4)
39#define VIPER_UARTB_GPIO (3)
40#define VIPER_CF_CD_GPIO (32)
41#define VIPER_CF_RDY_GPIO (8)
42#define VIPER_BCKLIGHT_EN_GPIO (9)
43#define VIPER_LCD_EN_GPIO (10)
44#define VIPER_PSU_DATA_GPIO (6)
45#define VIPER_PSU_CLK_GPIO (11)
46#define VIPER_UART_SHDN_GPIO (12)
47#define VIPER_BRIGHTNESS_GPIO (16)
48#define VIPER_PSU_nCS_LD_GPIO (19)
49#define VIPER_UPS_GPIO (20)
50#define VIPER_CF_POWER_GPIO (82)
51#define VIPER_TPM_I2C_SDA_GPIO (26)
52#define VIPER_TPM_I2C_SCL_GPIO (27)
53#define VIPER_RTC_I2C_SDA_GPIO (83)
54#define VIPER_RTC_I2C_SCL_GPIO (84)
55
56#define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE)
57#define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS)
58
59#ifndef __ASSEMBLY__
60# define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x)))
61#endif
62
63/* board level registers in the CPLD: (offsets from CPLD_BASE) ... */
64
65/* ... Physical addresses */
66#define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000)
67#define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002)
68#define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004)
69#define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006)
70#define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010)
71#define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000)
72#define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000)
73
74/* ... Virtual addresses */
75#define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS)
76#define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS)
77#define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS)
78#define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS)
79
80/* Decode VIPER_VERSION register */
81#define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7)
82#define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3)
83#define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7)
84
85/* Interrupt and Configuration Register (VIPER_ICR) */
86/* This is a write only register. Only CF_RST is used under Linux */
87
88extern void viper_cf_rst(int state);
89
90#define VIPER_ICR_RETRIG (1 << 0)
91#define VIPER_ICR_AUTO_CLR (1 << 1)
92#define VIPER_ICR_R_DIS (1 << 2)
93#define VIPER_ICR_CF_RST (1 << 3)
94
95#endif
96
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 03:53:04 -0500