3 files changed, 4 insertions, 2 deletions

diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 811743c56147..5f2ba8d9015c 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -2,6 +2,7 @@
 #define _COLIBRI_H_
 
 #include <net/ax88796.h>
+#include <mach/mfp.h>
 
 /*
  * common settings for all modules
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 7515757d6911..3d8d8cb09685 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -202,7 +202,7 @@
 #define __cpu_is_pxa950(id)                             \
         ({                                              \
                 unsigned int _id = (id) >> 4 & 0xfff;   \
-                id == 0x697;                            \
+                _id == 0x697;                           \
          })
 #else
 #define __cpu_is_pxa950(id)     (0)
diff --git a/arch/arm/mach-pxa/include/mach/regs-u2d.h b/arch/arm/mach-pxa/include/mach/regs-u2d.h
index 44b0b20b69a4..c15c0c57de08 100644
--- a/arch/arm/mach-pxa/include/mach/regs-u2d.h
+++ b/arch/arm/mach-pxa/include/mach/regs-u2d.h
@@ -166,7 +166,8 @@
 #define U2DMACSR_BUSERRTYPE     (7 << 10)       /* PX Bus Error Type */
 #define U2DMACSR_EORINTR        (1 << 9)        /* End Of Receive */
 #define U2DMACSR_REQPEND        (1 << 8)        /* Request Pending */
-#define U2DMACSR_RASINTR        (1 << 4)        /* Request After Channel Stopped (read / write 1 clear) */#define U2DMACSR_STOPINTR     (1 << 3)        /* Stop Interrupt (read only) */
+#define U2DMACSR_RASINTR        (1 << 4)        /* Request After Channel Stopped (read / write 1 clear) */
+#define U2DMACSR_STOPINTR       (1 << 3)        /* Stop Interrupt (read only) */
 #define U2DMACSR_ENDINTR        (1 << 2)        /* End Interrupt (read / write 1 clear) */
 #define U2DMACSR_STARTINTR      (1 << 1)        /* Start Interrupt (read / write 1 clear) */
 #define U2DMACSR_BUSERRINTR     (1 << 0)        /* Bus Error Interrupt (read / write 1 clear) */