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-rw-r--r--arch/arm/mach-pxa/include/mach/audio.h10
-rw-r--r--arch/arm/mach-pxa/include/mach/colibri.h39
-rw-r--r--arch/arm/mach-pxa/include/mach/csb726.h26
-rw-r--r--arch/arm/mach-pxa/include/mach/dma.h33
-rw-r--r--arch/arm/mach-pxa/include/mach/eseries-gpio.h15
-rw-r--r--arch/arm/mach-pxa/include/mach/gpio.h126
-rw-r--r--arch/arm/mach-pxa/include/mach/gumstix.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/lubbock.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/magician.h6
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa25x.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa27x.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa300.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa320.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h130
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp-pxa930.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/mtd-xip.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/palmasoc.h7
-rw-r--r--arch/arm/mach-pxa/include/mach/palmld.h110
-rw-r--r--arch/arm/mach-pxa/include/mach/palmt5.h84
-rw-r--r--arch/arm/mach-pxa/include/mach/palmte2.h68
-rw-r--r--arch/arm/mach-pxa/include/mach/palmtx.h3
-rw-r--r--arch/arm/mach-pxa/include/mach/pm.h10
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h263
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa25x.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa27x.h19
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h31
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx_spi.h1
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa300.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa320.h9
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h11
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx_nand.h3
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa930.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-intc.h23
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ost.h34
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-rtc.h23
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ssp.h8
-rw-r--r--arch/arm/mach-pxa/include/mach/system.h3
-rw-r--r--arch/arm/mach-pxa/include/mach/uncompress.h3
40 files changed, 658 insertions, 481 deletions
diff --git a/arch/arm/mach-pxa/include/mach/audio.h b/arch/arm/mach-pxa/include/mach/audio.h
index f82f96dd1053..16eb02552d5d 100644
--- a/arch/arm/mach-pxa/include/mach/audio.h
+++ b/arch/arm/mach-pxa/include/mach/audio.h
@@ -4,12 +4,22 @@
4#include <sound/core.h> 4#include <sound/core.h>
5#include <sound/pcm.h> 5#include <sound/pcm.h>
6 6
7/*
8 * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
9 * a -1 value means no gpio will be used for reset
10
11 * reset_gpio should only be specified for pxa27x CPUs where a silicon
12 * bug prevents correct operation of the reset line. If not specified,
13 * the default behaviour on these CPUs is to consider gpio 113 as the
14 * AC97 reset line, which is the default on most boards.
15 */
7typedef struct { 16typedef struct {
8 int (*startup)(struct snd_pcm_substream *, void *); 17 int (*startup)(struct snd_pcm_substream *, void *);
9 void (*shutdown)(struct snd_pcm_substream *, void *); 18 void (*shutdown)(struct snd_pcm_substream *, void *);
10 void (*suspend)(void *); 19 void (*suspend)(void *);
11 void (*resume)(void *); 20 void (*resume)(void *);
12 void *priv; 21 void *priv;
22 int reset_gpio;
13} pxa2xx_audio_ops_t; 23} pxa2xx_audio_ops_t;
14 24
15extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops); 25extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 2ae373fb5675..a88d7caff0d1 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -1,19 +1,38 @@
1#ifndef _COLIBRI_H_ 1#ifndef _COLIBRI_H_
2#define _COLIBRI_H_ 2#define _COLIBRI_H_
3 3
4#include <net/ax88796.h>
5
6/*
7 * common settings for all modules
8 */
9
10#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
11extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin);
12#else
13static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) {}
14#endif
15
16#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
17extern void colibri_pxa3xx_init_lcd(int bl_pin);
18#else
19static inline void colibri_pxa3xx_init_lcd(int bl_pin) {}
20#endif
21
22#if defined(CONFIG_AX88796)
23extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data);
24#endif
25
4/* physical memory regions */ 26/* physical memory regions */
5#define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
6#define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */
7#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ 27#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
8 28
9/* virtual memory regions */ 29/* definitions for Colibri PXA270 */
10#define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */
11
12/* size of flash */
13#define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */
14 30
15/* Ethernet Controller Davicom DM9000 */ 31#define COLIBRI_PXA270_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
16#define GPIO_DM9000 114 32#define COLIBRI_PXA270_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet */
17#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000) 33#define COLIBRI_PXA270_ETH_IRQ_GPIO 114
34#define COLIBRI_PXA270_ETH_IRQ \
35 gpio_to_irq(mfp_to_gpio(COLIBRI_PXA270_ETH_IRQ_GPIO))
18 36
19#endif /* _COLIBRI_H_ */ 37#endif /* _COLIBRI_H_ */
38
diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h
new file mode 100644
index 000000000000..747ab1a71f2f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/csb726.h
@@ -0,0 +1,26 @@
1/*
2 * Support for Cogent CSB726
3 *
4 * Copyright (c) 2008 Dmitry Baryshkov
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#ifndef CSB726_H
12#define CSB726_H
13
14#define CSB726_GPIO_IRQ_LAN 52
15#define CSB726_GPIO_IRQ_SM501 53
16#define CSB726_GPIO_MMC_DETECT 100
17#define CSB726_GPIO_MMC_RO 101
18
19#define CSB726_FLASH_SIZE (64 * 1024 * 1024)
20#define CSB726_FLASH_uMON (8 * 1024 * 1024)
21
22#define CSB726_IRQ_LAN gpio_to_irq(CSB726_GPIO_IRQ_LAN)
23#define CSB726_IRQ_SM501 gpio_to_irq(CSB726_GPIO_IRQ_SM501)
24
25#endif
26
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
index 7804637a6df3..5bd55894a48d 100644
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -12,35 +12,10 @@
12#ifndef __ASM_ARCH_DMA_H 12#ifndef __ASM_ARCH_DMA_H
13#define __ASM_ARCH_DMA_H 13#define __ASM_ARCH_DMA_H
14 14
15/* 15#include <mach/hardware.h>
16 * Descriptor structure for PXA's DMA engine
17 * Note: this structure must always be aligned to a 16-byte boundary.
18 */
19
20typedef struct pxa_dma_desc {
21 volatile u32 ddadr; /* Points to the next descriptor + flags */
22 volatile u32 dsadr; /* DSADR value for the current transfer */
23 volatile u32 dtadr; /* DTADR value for the current transfer */
24 volatile u32 dcmd; /* DCMD value for the current transfer */
25} pxa_dma_desc;
26
27typedef enum {
28 DMA_PRIO_HIGH = 0,
29 DMA_PRIO_MEDIUM = 1,
30 DMA_PRIO_LOW = 2
31} pxa_dma_prio;
32
33/*
34 * DMA registration
35 */
36
37int __init pxa_init_dma(int num_ch);
38
39int pxa_request_dma (char *name,
40 pxa_dma_prio prio,
41 void (*irq_handler)(int, void *),
42 void *data);
43 16
44void pxa_free_dma (int dma_ch); 17/* DMA Controller Registers Definitions */
18#define DMAC_REGS_VIRT io_p2v(0x40000000)
45 19
20#include <plat/dma.h>
46#endif /* _ASM_ARCH_DMA_H */ 21#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
index efbd2aa9ecec..f3e5509820d7 100644
--- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
@@ -45,6 +45,21 @@
45/* e7xx IrDA power control */ 45/* e7xx IrDA power control */
46#define GPIO_E7XX_IR_OFF 38 46#define GPIO_E7XX_IR_OFF 38
47 47
48/* e740 audio control GPIOs */
49#define GPIO_E740_WM9705_nAVDD2 16
50#define GPIO_E740_MIC_ON 40
51#define GPIO_E740_AMP_ON 41
52
53/* e750 audio control GPIOs */
54#define GPIO_E750_HP_AMP_OFF 4
55#define GPIO_E750_SPK_AMP_OFF 7
56#define GPIO_E750_HP_DETECT 37
57
58/* e800 audio control GPIOs */
59#define GPIO_E800_HP_DETECT 81
60#define GPIO_E800_HP_AMP_OFF 82
61#define GPIO_E800_SPK_AMP_ON 83
62
48/* ASIC related GPIOs */ 63/* ASIC related GPIOs */
49#define GPIO_ESERIES_TMIO_IRQ 5 64#define GPIO_ESERIES_TMIO_IRQ 5
50#define GPIO_ESERIES_TMIO_PCLR 19 65#define GPIO_ESERIES_TMIO_PCLR 19
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index 2c538d8c362d..b024a8b37439 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -24,42 +24,118 @@
24#ifndef __ASM_ARCH_PXA_GPIO_H 24#ifndef __ASM_ARCH_PXA_GPIO_H
25#define __ASM_ARCH_PXA_GPIO_H 25#define __ASM_ARCH_PXA_GPIO_H
26 26
27#include <mach/pxa-regs.h> 27#include <mach/irqs.h>
28#include <asm/irq.h>
29#include <mach/hardware.h> 28#include <mach/hardware.h>
30
31#include <asm-generic/gpio.h> 29#include <asm-generic/gpio.h>
32 30
31#define GPIO_REGS_VIRT io_p2v(0x40E00000)
32
33#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
34#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
35
36/* GPIO Pin Level Registers */
37#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00)
38#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00)
39#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00)
40#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00)
41
42/* GPIO Pin Direction Registers */
43#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c)
44#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c)
45#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c)
46#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c)
47
48/* GPIO Pin Output Set Registers */
49#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18)
50#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18)
51#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18)
52#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18)
53
54/* GPIO Pin Output Clear Registers */
55#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24)
56#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24)
57#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24)
58#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24)
59
60/* GPIO Rising Edge Detect Registers */
61#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30)
62#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30)
63#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30)
64#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30)
65
66/* GPIO Falling Edge Detect Registers */
67#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c)
68#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c)
69#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c)
70#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c)
71
72/* GPIO Edge Detect Status Registers */
73#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48)
74#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48)
75#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48)
76#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48)
77
78/* GPIO Alternate Function Select Registers */
79#define GAFR0_L GPIO_REG(0x0054)
80#define GAFR0_U GPIO_REG(0x0058)
81#define GAFR1_L GPIO_REG(0x005C)
82#define GAFR1_U GPIO_REG(0x0060)
83#define GAFR2_L GPIO_REG(0x0064)
84#define GAFR2_U GPIO_REG(0x0068)
85#define GAFR3_L GPIO_REG(0x006C)
86#define GAFR3_U GPIO_REG(0x0070)
87
88/* More handy macros. The argument is a literal GPIO number. */
89
90#define GPIO_bit(x) (1 << ((x) & 0x1f))
91
92#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
93#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
94#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
95#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
96#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
97#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
98#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
99#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
100
33 101
34/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
35 * Those cases currently cause holes in the GPIO number space.
36 */
37#define NR_BUILTIN_GPIO 128 102#define NR_BUILTIN_GPIO 128
38 103
39static inline int gpio_get_value(unsigned gpio) 104#define gpio_to_bank(gpio) ((gpio) >> 5)
105#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
106#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
107
108#ifdef CONFIG_CPU_PXA26x
109/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
110 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
111 */
112static inline int __gpio_is_inverted(unsigned gpio)
40{ 113{
41 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) 114 return cpu_is_pxa25x() && gpio > 85;
42 return GPLR(gpio) & GPIO_bit(gpio);
43 else
44 return __gpio_get_value(gpio);
45} 115}
116#else
117static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
118#endif
46 119
47static inline void gpio_set_value(unsigned gpio, int value) 120/*
121 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
122 * function of a GPIO, and GPDRx cannot be altered once configured. It
123 * is attributed as "occupied" here (I know this terminology isn't
124 * accurate, you are welcome to propose a better one :-)
125 */
126static inline int __gpio_is_occupied(unsigned gpio)
48{ 127{
49 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { 128 if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
50 if (value) 129 int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
51 GPSR(gpio) = GPIO_bit(gpio); 130 int dir = GPDR(gpio) & GPIO_bit(gpio);
131
132 if (__gpio_is_inverted(gpio))
133 return af != 1 || dir == 0;
52 else 134 else
53 GPCR(gpio) = GPIO_bit(gpio); 135 return af != 0 || dir != 0;
54 } else { 136 } else
55 __gpio_set_value(gpio, value); 137 return GPDR(gpio) & GPIO_bit(gpio);
56 }
57} 138}
58 139
59#define gpio_cansleep __gpio_cansleep 140#include <plat/gpio.h>
60
61#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
62#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
63
64
65#endif 141#endif
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
index 099f54a41de4..06abd4160607 100644
--- a/arch/arm/mach-pxa/include/mach/gumstix.h
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -97,4 +97,5 @@ has detected a cable insertion; driven low otherwise. */
97 97
98/* for expansion boards that can't be programatically detected */ 98/* for expansion boards that can't be programatically detected */
99extern int am200_init(void); 99extern int am200_init(void);
100extern int am300_init(void);
100 101
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index 4cb24154a5a8..751b74811d0f 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -25,7 +25,6 @@
25 25
26/* FPGA register virtual addresses */ 26/* FPGA register virtual addresses */
27#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) 27#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
28#define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
29#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) 28#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
30#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) 29#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
31#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) 30#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 38d68d99f585..20ef37d4a9a7 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -27,7 +27,7 @@
27#define GPIO22_MAGICIAN_VIBRA_EN 22 27#define GPIO22_MAGICIAN_VIBRA_EN 22
28#define GPIO26_MAGICIAN_GSM_POWER 26 28#define GPIO26_MAGICIAN_GSM_POWER 26
29#define GPIO27_MAGICIAN_USBC_PUEN 27 29#define GPIO27_MAGICIAN_USBC_PUEN 27
30#define GPIO30_MAGICIAN_nCHARGE_EN 30 30#define GPIO30_MAGICIAN_BQ24022_nCHARGE_EN 30
31#define GPIO37_MAGICIAN_KEY_HANGUP 37 31#define GPIO37_MAGICIAN_KEY_HANGUP 37
32#define GPIO38_MAGICIAN_KEY_CONTACTS 38 32#define GPIO38_MAGICIAN_KEY_CONTACTS 38
33#define GPIO40_MAGICIAN_GSM_OUT2 40 33#define GPIO40_MAGICIAN_GSM_OUT2 40
@@ -69,7 +69,7 @@
69#define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) 69#define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0)
70#define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) 70#define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1)
71#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) 71#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2)
72#define IRQ_MAGICIAN_AC (IRQ_BOARD_START + 3) 72#define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3)
73 73
74/* 74/*
75 * CPLD EGPIOs 75 * CPLD EGPIOs
@@ -98,7 +98,7 @@
98#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL MAGICIAN_EGPIO(2, 2) 98#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL MAGICIAN_EGPIO(2, 2)
99#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3) 99#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3)
100#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4) 100#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4)
101#define EGPIO_MAGICIAN_CHARGE_EN MAGICIAN_EGPIO(2, 5) 101#define EGPIO_MAGICIAN_BQ24022_ISET2 MAGICIAN_EGPIO(2, 5)
102#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7) 102#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7)
103 103
104/* input */ 104/* input */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
index a72869b73ee3..b13dc0269a6d 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h
@@ -1,7 +1,6 @@
1#ifndef __ASM_ARCH_MFP_PXA25X_H 1#ifndef __ASM_ARCH_MFP_PXA25X_H
2#define __ASM_ARCH_MFP_PXA25X_H 2#define __ASM_ARCH_MFP_PXA25X_H
3 3
4#include <mach/mfp.h>
5#include <mach/mfp-pxa2xx.h> 4#include <mach/mfp-pxa2xx.h>
6 5
7/* GPIO */ 6/* GPIO */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index da4f85a4f990..6543c05f47ed 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -8,7 +8,6 @@
8 * specific controller, and this should work in most cases. 8 * specific controller, and this should work in most cases.
9 */ 9 */
10 10
11#include <mach/mfp.h>
12#include <mach/mfp-pxa2xx.h> 11#include <mach/mfp-pxa2xx.h>
13 12
14/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN 13/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index 3e9211591e20..658b28ed129b 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_ARCH_MFP_PXA2XX_H 1#ifndef __ASM_ARCH_MFP_PXA2XX_H
2#define __ASM_ARCH_MFP_PXA2XX_H 2#define __ASM_ARCH_MFP_PXA2XX_H
3 3
4#include <mach/mfp.h> 4#include <plat/mfp.h>
5 5
6/* 6/*
7 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: 7 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
index bc1fb33a6e70..ae8441192ef0 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
@@ -15,7 +15,6 @@
15#ifndef __ASM_ARCH_MFP_PXA300_H 15#ifndef __ASM_ARCH_MFP_PXA300_H
16#define __ASM_ARCH_MFP_PXA300_H 16#define __ASM_ARCH_MFP_PXA300_H
17 17
18#include <mach/mfp.h>
19#include <mach/mfp-pxa3xx.h> 18#include <mach/mfp-pxa3xx.h>
20 19
21/* GPIO */ 20/* GPIO */
@@ -41,6 +40,7 @@
41#endif 40#endif
42 41
43/* Chip Select */ 42/* Chip Select */
43#define GPIO1_nCS2 MFP_CFG(GPIO1, AF1)
44#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) 44#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1)
45 45
46/* AC97 */ 46/* AC97 */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
index 67f8385ea548..07897e61d05a 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h
@@ -15,7 +15,6 @@
15#ifndef __ASM_ARCH_MFP_PXA320_H 15#ifndef __ASM_ARCH_MFP_PXA320_H
16#define __ASM_ARCH_MFP_PXA320_H 16#define __ASM_ARCH_MFP_PXA320_H
17 17
18#include <mach/mfp.h>
19#include <mach/mfp-pxa3xx.h> 18#include <mach/mfp-pxa3xx.h>
20 19
21/* GPIO */ 20/* GPIO */
@@ -38,6 +37,7 @@
38#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) 37#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0)
39 38
40/* Chip Select */ 39/* Chip Select */
40#define GPIO3_nCS2 MFP_CFG(GPIO3, AF1)
41#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) 41#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1)
42 42
43/* AC97 */ 43/* AC97 */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
index 1f6b35c015d0..d375195d982b 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h
@@ -1,68 +1,9 @@
1#ifndef __ASM_ARCH_MFP_PXA3XX_H 1#ifndef __ASM_ARCH_MFP_PXA3XX_H
2#define __ASM_ARCH_MFP_PXA3XX_H 2#define __ASM_ARCH_MFP_PXA3XX_H
3 3
4#define MFPR_BASE (0x40e10000) 4#include <plat/mfp.h>
5#define MFPR_SIZE (PAGE_SIZE)
6
7/* MFPR register bit definitions */
8#define MFPR_PULL_SEL (0x1 << 15)
9#define MFPR_PULLUP_EN (0x1 << 14)
10#define MFPR_PULLDOWN_EN (0x1 << 13)
11#define MFPR_SLEEP_SEL (0x1 << 9)
12#define MFPR_SLEEP_OE_N (0x1 << 7)
13#define MFPR_EDGE_CLEAR (0x1 << 6)
14#define MFPR_EDGE_FALL_EN (0x1 << 5)
15#define MFPR_EDGE_RISE_EN (0x1 << 4)
16
17#define MFPR_SLEEP_DATA(x) ((x) << 8)
18#define MFPR_DRIVE(x) (((x) & 0x7) << 10)
19#define MFPR_AF_SEL(x) (((x) & 0x7) << 0)
20 5
21#define MFPR_EDGE_NONE (0) 6#define MFPR_BASE (0x40e10000)
22#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN)
23#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN)
24#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL)
25
26/*
27 * Table that determines the low power modes outputs, with actual settings
28 * used in parentheses for don't-care values. Except for the float output,
29 * the configured driven and pulled levels match, so if there is a need for
30 * non-LPM pulled output, the same configuration could probably be used.
31 *
32 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
33 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
34 *
35 * Input 0 X(0) X(0) X(0) 0
36 * Drive 0 0 0 0 X(1) 0
37 * Drive 1 0 1 X(1) 0 0
38 * Pull hi (1) 1 X(1) 1 0 0
39 * Pull lo (0) 1 X(0) 0 1 0
40 * Z (float) 1 X(0) 0 0 0
41 */
42#define MFPR_LPM_INPUT (0)
43#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
44#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
45#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N)
46#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
47#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N)
48#define MFPR_LPM_MASK (0xe080)
49
50/*
51 * The pullup and pulldown state of the MFP pin at run mode is by default
52 * determined by the selected alternate function. In case that some buggy
53 * devices need to override this default behavior, the definitions below
54 * indicates the setting of corresponding MFPR bits
55 *
56 * Definition pull_sel pullup_en pulldown_en
57 * MFPR_PULL_NONE 0 0 0
58 * MFPR_PULL_LOW 1 0 1
59 * MFPR_PULL_HIGH 1 1 0
60 * MFPR_PULL_BOTH 1 1 1
61 */
62#define MFPR_PULL_NONE (0)
63#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
64#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN)
65#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN)
66 7
67/* PXA3xx common MFP configurations - processor specific ones defined 8/* PXA3xx common MFP configurations - processor specific ones defined
68 * in mfp-pxa300.h and mfp-pxa320.h 9 * in mfp-pxa300.h and mfp-pxa320.h
@@ -197,56 +138,21 @@
197#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) 138#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
198#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) 139#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
199 140
200/* 141/* NOTE: usage of these two functions is not recommended,
201 * each MFP pin will have a MFPR register, since the offset of the 142 * use pxa3xx_mfp_config() instead.
202 * register varies between processors, the processor specific code
203 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
204 *
205 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
206 * structure, which represents a range of MFP pins from "start" to
207 * "end", with the offset begining at "offset", to define a single
208 * pin, let "end" = -1
209 *
210 * use
211 *
212 * MFP_ADDR_X() to define a range of pins
213 * MFP_ADDR() to define a single pin
214 * MFP_ADDR_END to signal the end of pin offset definitions
215 */
216struct pxa3xx_mfp_addr_map {
217 unsigned int start;
218 unsigned int end;
219 unsigned long offset;
220};
221
222#define MFP_ADDR_X(start, end, offset) \
223 { MFP_PIN_##start, MFP_PIN_##end, offset }
224
225#define MFP_ADDR(pin, offset) \
226 { MFP_PIN_##pin, -1, offset }
227
228#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
229
230/*
231 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
232 * to the MFPR register
233 */
234unsigned long pxa3xx_mfp_read(int mfp);
235void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
236
237/*
238 * pxa3xx_mfp_config - configure the MFPR registers
239 *
240 * used by board specific initialization code
241 */
242void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num);
243
244/*
245 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
246 * index and MFPR register offset
247 *
248 * used by processor specific code
249 */ 143 */
250void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); 144static inline unsigned long pxa3xx_mfp_read(int mfp)
251void __init pxa3xx_init_mfp(void); 145{
146 return mfp_read(mfp);
147}
148
149static inline void pxa3xx_mfp_write(int mfp, unsigned long val)
150{
151 mfp_write(mfp, val);
152}
153
154static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num)
155{
156 mfp_config(mfp_cfg, num);
157}
252#endif /* __ASM_ARCH_MFP_PXA3XX_H */ 158#endif /* __ASM_ARCH_MFP_PXA3XX_H */
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index fa73f56a1372..0d119d3b9221 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -13,7 +13,6 @@
13#ifndef __ASM_ARCH_MFP_PXA9xx_H 13#ifndef __ASM_ARCH_MFP_PXA9xx_H
14#define __ASM_ARCH_MFP_PXA9xx_H 14#define __ASM_ARCH_MFP_PXA9xx_H
15 15
16#include <mach/mfp.h>
17#include <mach/mfp-pxa3xx.h> 16#include <mach/mfp-pxa3xx.h>
18 17
19/* GPIO */ 18/* GPIO */
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h
index cfca8155be72..297387ec3618 100644
--- a/arch/arm/mach-pxa/include/mach/mtd-xip.h
+++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h
@@ -15,8 +15,8 @@
15#ifndef __ARCH_PXA_MTD_XIP_H__ 15#ifndef __ARCH_PXA_MTD_XIP_H__
16#define __ARCH_PXA_MTD_XIP_H__ 16#define __ARCH_PXA_MTD_XIP_H__
17 17
18#include <mach/hardware.h> 18#include <mach/regs-ost.h>
19#include <mach/pxa-regs.h> 19#include <mach/regs-intc.h>
20 20
21#define xip_irqpending() (ICIP & ICMR) 21#define xip_irqpending() (ICIP & ICMR)
22 22
diff --git a/arch/arm/mach-pxa/include/mach/palmasoc.h b/arch/arm/mach-pxa/include/mach/palmasoc.h
index 6c4b1f7de20a..58afb30d5298 100644
--- a/arch/arm/mach-pxa/include/mach/palmasoc.h
+++ b/arch/arm/mach-pxa/include/mach/palmasoc.h
@@ -1,13 +1,8 @@
1#ifndef _INCLUDE_PALMASOC_H_ 1#ifndef _INCLUDE_PALMASOC_H_
2#define _INCLUDE_PALMASOC_H_ 2#define _INCLUDE_PALMASOC_H_
3
3struct palm27x_asoc_info { 4struct palm27x_asoc_info {
4 int jack_gpio; 5 int jack_gpio;
5}; 6};
6 7
7#ifdef CONFIG_SND_PXA2XX_SOC_PALM27X
8void __init palm27x_asoc_set_pdata(struct palm27x_asoc_info *data);
9#else
10static inline void palm27x_asoc_set_pdata(struct palm27x_asoc_info *data) {}
11#endif
12
13#endif 8#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h
new file mode 100644
index 000000000000..fb13c82ad6dc
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmld.h
@@ -0,0 +1,110 @@
1/*
2 * GPIOs and interrupts for Palm LifeDrive Handheld Computer
3 *
4 * Authors: Alex Osborne <ato@meshy.org>
5 * Marek Vasut <marek.vasut@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#ifndef _INCLUDE_PALMLD_H_
14#define _INCLUDE_PALMLD_H_
15
16/** HERE ARE GPIOs **/
17
18/* GPIOs */
19#define GPIO_NR_PALMLD_GPIO_RESET 1
20#define GPIO_NR_PALMLD_POWER_DETECT 4
21#define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10
22#define GPIO_NR_PALMLD_POWER_SWITCH 12
23#define GPIO_NR_PALMLD_EARPHONE_DETECT 13
24#define GPIO_NR_PALMLD_LOCK_SWITCH 15
25
26/* SD/MMC */
27#define GPIO_NR_PALMLD_SD_DETECT_N 14
28#define GPIO_NR_PALMLD_SD_POWER 114
29#define GPIO_NR_PALMLD_SD_READONLY 116
30
31/* TOUCHSCREEN */
32#define GPIO_NR_PALMLD_WM9712_IRQ 27
33
34/* IRDA */
35#define GPIO_NR_PALMLD_IR_DISABLE 108
36
37/* LCD/BACKLIGHT */
38#define GPIO_NR_PALMLD_BL_POWER 19
39#define GPIO_NR_PALMLD_LCD_POWER 96
40
41/* LCD BORDER */
42#define GPIO_NR_PALMLD_BORDER_SWITCH 21
43#define GPIO_NR_PALMLD_BORDER_SELECT 22
44
45/* BLUETOOTH */
46#define GPIO_NR_PALMLD_BT_POWER 17
47#define GPIO_NR_PALMLD_BT_RESET 83
48
49/* PCMCIA (WiFi) */
50#define GPIO_NR_PALMLD_PCMCIA_READY 38
51#define GPIO_NR_PALMLD_PCMCIA_POWER 36
52#define GPIO_NR_PALMLD_PCMCIA_RESET 81
53
54/* LEDs */
55#define GPIO_NR_PALMLD_LED_GREEN 52
56#define GPIO_NR_PALMLD_LED_AMBER 94
57
58/* IDE */
59#define GPIO_NR_PALMLD_IDE_IRQ 95
60#define GPIO_NR_PALMLD_IDE_RESET 98
61#define GPIO_NR_PALMLD_IDE_PWEN 115
62
63/* USB */
64#define GPIO_NR_PALMLD_USB_DETECT_N 3
65#define GPIO_NR_PALMLD_USB_READY 86
66#define GPIO_NR_PALMLD_USB_RESET 88
67#define GPIO_NR_PALMLD_USB_INT 106
68#define GPIO_NR_PALMLD_USB_POWER 118
69/* 20, 53 and 86 are usb related too */
70
71/* INTERRUPTS */
72#define IRQ_GPIO_PALMLD_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET)
73#define IRQ_GPIO_PALMLD_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N)
74#define IRQ_GPIO_PALMLD_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ)
75#define IRQ_GPIO_PALMLD_IDE_IRQ IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ)
76
77
78/** HERE ARE INIT VALUES **/
79
80/* IO mappings */
81#define PALMLD_USB_PHYS PXA_CS2_PHYS
82#define PALMLD_USB_VIRT 0xf0000000
83#define PALMLD_USB_SIZE 0x00100000
84
85#define PALMLD_IDE_PHYS 0x20000000
86#define PALMLD_IDE_VIRT 0xf1000000
87#define PALMLD_IDE_SIZE 0x00100000
88
89#define PALMLD_PHYS_IO_START 0x40000000
90#define PALMLD_STR_BASE 0xa0200000
91
92/* BATTERY */
93#define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */
94#define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */
95#define PALMLD_BAT_MAX_CURRENT 0 /* unknokn */
96#define PALMLD_BAT_MIN_CURRENT 0 /* unknown */
97#define PALMLD_BAT_MAX_CHARGE 1 /* unknown */
98#define PALMLD_BAT_MIN_CHARGE 1 /* unknown */
99#define PALMLD_MAX_LIFE_MINS 240 /* on-life in minutes */
100
101#define PALMLD_BAT_MEASURE_DELAY (HZ * 1)
102
103/* BACKLIGHT */
104#define PALMLD_MAX_INTENSITY 0xFE
105#define PALMLD_DEFAULT_INTENSITY 0x7E
106#define PALMLD_LIMIT_MASK 0x7F
107#define PALMLD_PRESCALER 0x3F
108#define PALMLD_PERIOD_NS 3500
109
110#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h
new file mode 100644
index 000000000000..d15662aba008
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmt5.h
@@ -0,0 +1,84 @@
1/*
2 * GPIOs and interrupts for Palm Tungsten|T5 Handheld Computer
3 *
4 * Authors: Ales Snuparek <snuparek@atlas.cz>
5 * Marek Vasut <marek.vasut@gmail.com>
6 * Justin Kendrick <twilightsentry@gmail.com>
7 * RichardT5 <richard_t5@users.sourceforge.net>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#ifndef _INCLUDE_PALMT5_H_
16#define _INCLUDE_PALMT5_H_
17
18/** HERE ARE GPIOs **/
19
20/* GPIOs */
21#define GPIO_NR_PALMT5_GPIO_RESET 1
22
23#define GPIO_NR_PALMT5_POWER_DETECT 90
24#define GPIO_NR_PALMT5_HOTSYNC_BUTTON_N 10
25#define GPIO_NR_PALMT5_EARPHONE_DETECT 107
26
27/* SD/MMC */
28#define GPIO_NR_PALMT5_SD_DETECT_N 14
29#define GPIO_NR_PALMT5_SD_POWER 114
30#define GPIO_NR_PALMT5_SD_READONLY 115
31
32/* TOUCHSCREEN */
33#define GPIO_NR_PALMT5_WM9712_IRQ 27
34
35/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
36#define GPIO_NR_PALMT5_IR_DISABLE 40
37
38/* USB */
39#define GPIO_NR_PALMT5_USB_DETECT_N 15
40#define GPIO_NR_PALMT5_USB_PULLUP 93
41
42/* LCD/BACKLIGHT */
43#define GPIO_NR_PALMT5_BL_POWER 84
44#define GPIO_NR_PALMT5_LCD_POWER 96
45
46/* BLUETOOTH */
47#define GPIO_NR_PALMT5_BT_POWER 17
48#define GPIO_NR_PALMT5_BT_RESET 83
49
50/* INTERRUPTS */
51#define IRQ_GPIO_PALMT5_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N)
52#define IRQ_GPIO_PALMT5_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ)
53#define IRQ_GPIO_PALMT5_USB_DETECT IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT)
54#define IRQ_GPIO_PALMT5_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET)
55
56/** HERE ARE INIT VALUES **/
57
58/* Various addresses */
59#define PALMT5_PHYS_RAM_START 0xa0000000
60#define PALMT5_PHYS_IO_START 0x40000000
61#define PALMT5_STR_BASE 0xa0200000
62
63/* TOUCHSCREEN */
64#define AC97_LINK_FRAME 21
65
66/* BATTERY */
67#define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
68#define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
69#define PALMT5_BAT_MAX_CURRENT 0 /* unknokn */
70#define PALMT5_BAT_MIN_CURRENT 0 /* unknown */
71#define PALMT5_BAT_MAX_CHARGE 1 /* unknown */
72#define PALMT5_BAT_MIN_CHARGE 1 /* unknown */
73#define PALMT5_MAX_LIFE_MINS 360 /* on-life in minutes */
74
75#define PALMT5_BAT_MEASURE_DELAY (HZ * 1)
76
77/* BACKLIGHT */
78#define PALMT5_MAX_INTENSITY 0xFE
79#define PALMT5_DEFAULT_INTENSITY 0x7E
80#define PALMT5_LIMIT_MASK 0x7F
81#define PALMT5_PRESCALER 0x3F
82#define PALMT5_PERIOD_NS 3500
83
84#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmte2.h b/arch/arm/mach-pxa/include/mach/palmte2.h
new file mode 100644
index 000000000000..12361341f9d8
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/palmte2.h
@@ -0,0 +1,68 @@
1/*
2 * GPIOs and interrupts for Palm Tungsten|E2 Handheld Computer
3 *
4 * Author:
5 * Carlos Eduardo Medaglia Dyonisio <cadu@nerdfeliz.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#ifndef _INCLUDE_PALMTE2_H_
14#define _INCLUDE_PALMTE2_H_
15
16/** HERE ARE GPIOs **/
17
18/* GPIOs */
19#define GPIO_NR_PALMTE2_POWER_DETECT 9
20#define GPIO_NR_PALMTE2_HOTSYNC_BUTTON_N 4
21#define GPIO_NR_PALMTE2_EARPHONE_DETECT 15
22
23/* SD/MMC */
24#define GPIO_NR_PALMTE2_SD_DETECT_N 10
25#define GPIO_NR_PALMTE2_SD_POWER 55
26#define GPIO_NR_PALMTE2_SD_READONLY 51
27
28/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */
29#define GPIO_NR_PALMTE2_IR_DISABLE 48
30
31/* USB */
32#define GPIO_NR_PALMTE2_USB_DETECT_N 35
33#define GPIO_NR_PALMTE2_USB_PULLUP 53
34
35/* LCD/BACKLIGHT */
36#define GPIO_NR_PALMTE2_BL_POWER 56
37#define GPIO_NR_PALMTE2_LCD_POWER 37
38
39/* KEYS */
40#define GPIO_NR_PALMTE2_KEY_NOTES 5
41#define GPIO_NR_PALMTE2_KEY_TASKS 7
42#define GPIO_NR_PALMTE2_KEY_CALENDAR 11
43#define GPIO_NR_PALMTE2_KEY_CONTACTS 13
44#define GPIO_NR_PALMTE2_KEY_CENTER 14
45#define GPIO_NR_PALMTE2_KEY_LEFT 19
46#define GPIO_NR_PALMTE2_KEY_RIGHT 20
47#define GPIO_NR_PALMTE2_KEY_DOWN 21
48#define GPIO_NR_PALMTE2_KEY_UP 22
49
50/** HERE ARE INIT VALUES **/
51
52/* BACKLIGHT */
53#define PALMTE2_MAX_INTENSITY 0xFE
54#define PALMTE2_DEFAULT_INTENSITY 0x7E
55#define PALMTE2_LIMIT_MASK 0x7F
56#define PALMTE2_PRESCALER 0x3F
57#define PALMTE2_PERIOD_NS 3500
58
59/* BATTERY */
60#define PALMTE2_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */
61#define PALMTE2_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */
62#define PALMTE2_BAT_MAX_CURRENT 0 /* unknokn */
63#define PALMTE2_BAT_MIN_CURRENT 0 /* unknown */
64#define PALMTE2_BAT_MAX_CHARGE 1 /* unknown */
65#define PALMTE2_BAT_MIN_CHARGE 1 /* unknown */
66#define PALMTE2_MAX_LIFE_MINS 360 /* on-life in minutes */
67
68#endif
diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h
index 1e8bccbda510..e74082c872e1 100644
--- a/arch/arm/mach-pxa/include/mach/palmtx.h
+++ b/arch/arm/mach-pxa/include/mach/palmtx.h
@@ -38,7 +38,6 @@
38 38
39/* USB */ 39/* USB */
40#define GPIO_NR_PALMTX_USB_DETECT_N 13 40#define GPIO_NR_PALMTX_USB_DETECT_N 13
41#define GPIO_NR_PALMTX_USB_POWER 95
42#define GPIO_NR_PALMTX_USB_PULLUP 93 41#define GPIO_NR_PALMTX_USB_PULLUP 93
43 42
44/* LCD/BACKLIGHT */ 43/* LCD/BACKLIGHT */
@@ -78,6 +77,8 @@
78#define PALMTX_PHYS_RAM_START 0xa0000000 77#define PALMTX_PHYS_RAM_START 0xa0000000
79#define PALMTX_PHYS_IO_START 0x40000000 78#define PALMTX_PHYS_IO_START 0x40000000
80 79
80#define PALMTX_STR_BASE 0xa0200000
81
81#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */ 82#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
82#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */ 83#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */
83 84
diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h
index 83342469acac..a6eeef8a075f 100644
--- a/arch/arm/mach-pxa/include/mach/pm.h
+++ b/arch/arm/mach-pxa/include/mach/pm.h
@@ -27,3 +27,13 @@ extern void pxa27x_cpu_suspend(unsigned int);
27extern void pxa_cpu_resume(void); 27extern void pxa_cpu_resume(void);
28 28
29extern int pxa_pm_enter(suspend_state_t state); 29extern int pxa_pm_enter(suspend_state_t state);
30
31/* NOTE: this is for PM debugging on Lubbock, it's really a big
32 * ugly, but let's keep the crap minimum here, instead of direct
33 * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c
34 */
35#ifdef CONFIG_ARCH_LUBBOCK
36extern void lubbock_set_hexled(uint32_t value);
37#else
38#define lubbock_set_hexled(x)
39#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
deleted file mode 100644
index 31d615aa7723..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ /dev/null
@@ -1,263 +0,0 @@
1/*
2 * arch/arm/mach-pxa/include/mach/pxa-regs.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PXA_REGS_H
14#define __PXA_REGS_H
15
16#include <mach/hardware.h>
17
18/*
19 * PXA Chip selects
20 */
21
22#define PXA_CS0_PHYS 0x00000000
23#define PXA_CS1_PHYS 0x04000000
24#define PXA_CS2_PHYS 0x08000000
25#define PXA_CS3_PHYS 0x0C000000
26#define PXA_CS4_PHYS 0x10000000
27#define PXA_CS5_PHYS 0x14000000
28
29
30/*
31 * Personal Computer Memory Card International Association (PCMCIA) sockets
32 */
33
34#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
35#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
36#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
37#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
38#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
39
40#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
41#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
42#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
43#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
44
45#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
46#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
47#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
48#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
49
50#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
51 (0x20000000 + (Nb)*PCMCIASp)
52#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
53#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
54 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
55#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
56 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
57
58#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
59#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
60#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
61#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
62
63#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
64#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
65#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
66#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
67
68
69
70/*
71 * DMA Controller
72 */
73#define DCSR(x) __REG2(0x40000000, (x) << 2)
74
75#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
76#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
77#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
78#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
79#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
80#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
81#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
82#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
83
84#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
85#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
86#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
87#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
88#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
89#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
90#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
91#define DCSR_EORINTR (1 << 9) /* The end of Receive */
92#endif
93
94#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
95#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
96
97#define DRCMR(n) (*(((n) < 64) ? \
98 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
99 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
100
101#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
102#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
103
104#define DDADR(x) __REG2(0x40000200, (x) << 4)
105#define DSADR(x) __REG2(0x40000204, (x) << 4)
106#define DTADR(x) __REG2(0x40000208, (x) << 4)
107#define DCMD(x) __REG2(0x4000020c, (x) << 4)
108
109#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
110#define DDADR_STOP (1 << 0) /* Stop (read / write) */
111
112#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
113#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
114#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
115#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
116#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
117#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
118#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
119#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
120#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
121#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
122#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
123#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
124#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
125#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
126
127/*
128 * Real Time Clock
129 */
130
131#define RCNR __REG(0x40900000) /* RTC Count Register */
132#define RTAR __REG(0x40900004) /* RTC Alarm Register */
133#define RTSR __REG(0x40900008) /* RTC Status Register */
134#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
135#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
136
137#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
138#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
139#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
140#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
141#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
142#define RTSR_AL (1 << 0) /* RTC alarm detected */
143
144
145/*
146 * OS Timer & Match Registers
147 */
148
149#define OSMR0 __REG(0x40A00000) /* */
150#define OSMR1 __REG(0x40A00004) /* */
151#define OSMR2 __REG(0x40A00008) /* */
152#define OSMR3 __REG(0x40A0000C) /* */
153#define OSMR4 __REG(0x40A00080) /* */
154#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
155#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
156#define OMCR4 __REG(0x40A000C0) /* */
157#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
158#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
159#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
160
161#define OSSR_M3 (1 << 3) /* Match status channel 3 */
162#define OSSR_M2 (1 << 2) /* Match status channel 2 */
163#define OSSR_M1 (1 << 1) /* Match status channel 1 */
164#define OSSR_M0 (1 << 0) /* Match status channel 0 */
165
166#define OWER_WME (1 << 0) /* Watchdog Match Enable */
167
168#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
169#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
170#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
171#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
172
173
174/*
175 * Interrupt Controller
176 */
177
178#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
179#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
180#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
181#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
182#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
183#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
184
185#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
186#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
187#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
188#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
189#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
190
191/*
192 * General Purpose I/O
193 */
194
195#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
196#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
197#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
198
199#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
200#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
201#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
202
203#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
204#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
205#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
206
207#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
208#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
209#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
210
211#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
212#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
213#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
214
215#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
216#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
217#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
218
219#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
220#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
221#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
222
223#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
224#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
225#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
226#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
227#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
228#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
229#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
230#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
231
232#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
233#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
234#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
235#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
236#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
237#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
238#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
239
240/* More handy macros. The argument is a literal GPIO number. */
241
242#define GPIO_bit(x) (1 << ((x) & 0x1f))
243
244#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
245#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
246#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
247#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
248#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
249#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
250#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
251#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
252
253#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
254#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
255#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
256#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
257#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
258#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
259#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
260#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
261 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
262
263#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h
new file mode 100644
index 000000000000..508c3ba1f4d0
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa25x.h
@@ -0,0 +1,8 @@
1#ifndef __MACH_PXA25x_H
2#define __MACH_PXA25x_H
3
4#include <mach/hardware.h>
5#include <mach/pxa2xx-regs.h>
6#include <mach/mfp-pxa25x.h>
7
8#endif /* __MACH_PXA25x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h
new file mode 100644
index 000000000000..6876e16c2970
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa27x.h
@@ -0,0 +1,19 @@
1#ifndef __MACH_PXA27x_H
2#define __MACH_PXA27x_H
3
4#include <mach/hardware.h>
5#include <mach/pxa2xx-regs.h>
6#include <mach/mfp-pxa27x.h>
7
8#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
9
10#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
11#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
12#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
13#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
14#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
15#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
16#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
17#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
18#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
19#endif /* __MACH_PXA27x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
index d83393e25273..1209c44aa6f1 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h
@@ -3,6 +3,8 @@
3 3
4#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h 4#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
5 5
6#include <mach/gpio.h>
7
6/* GPIO alternate function assignments */ 8/* GPIO alternate function assignments */
7 9
8#define GPIO1_RST 1 /* reset */ 10#define GPIO1_RST 1 /* reset */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 77102d695cc7..4fcddd9cab76 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -14,6 +14,19 @@
14#ifndef __PXA2XX_REGS_H 14#ifndef __PXA2XX_REGS_H
15#define __PXA2XX_REGS_H 15#define __PXA2XX_REGS_H
16 16
17#include <mach/hardware.h>
18
19/*
20 * PXA Chip selects
21 */
22
23#define PXA_CS0_PHYS 0x00000000
24#define PXA_CS1_PHYS 0x04000000
25#define PXA_CS2_PHYS 0x08000000
26#define PXA_CS3_PHYS 0x0C000000
27#define PXA_CS4_PHYS 0x10000000
28#define PXA_CS5_PHYS 0x14000000
29
17/* 30/*
18 * Memory controller 31 * Memory controller
19 */ 32 */
@@ -69,24 +82,6 @@
69#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ 82#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
70#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ 83#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
71 84
72
73#ifdef CONFIG_PXA27x
74
75#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
76
77#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
78#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
79#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
80#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
81#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
82#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
83#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
84#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
85#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
86
87#endif
88
89
90/* 85/*
91 * Power Manager 86 * Power Manager
92 */ 87 */
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h b/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
index 2206cb61a9f9..b87cecd9bbdc 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
@@ -38,6 +38,7 @@ struct pxa2xx_spi_chip {
38 u8 dma_burst_size; 38 u8 dma_burst_size;
39 u32 timeout; 39 u32 timeout;
40 u8 enable_loopback; 40 u8 enable_loopback;
41 int gpio_cs;
41 void (*cs_control)(u32 command); 42 void (*cs_control)(u32 command);
42}; 43};
43 44
diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h
new file mode 100644
index 000000000000..2f33076c9e48
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa300.h
@@ -0,0 +1,8 @@
1#ifndef __MACH_PXA300_H
2#define __MACH_PXA300_H
3
4#include <mach/hardware.h>
5#include <mach/pxa3xx-regs.h>
6#include <mach/mfp-pxa300.h>
7
8#endif /* __MACH_PXA300_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h
new file mode 100644
index 000000000000..cab78e903273
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa320.h
@@ -0,0 +1,9 @@
1#ifndef __MACH_PXA320_H
2#define __MACH_PXA320_H
3
4#include <mach/hardware.h>
5#include <mach/pxa3xx-regs.h>
6#include <mach/mfp-pxa320.h>
7
8#endif /* __MACH_PXA320_H */
9
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index bcf3fb2c4b3a..7d1a059b3d43 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -13,6 +13,17 @@
13#ifndef __ASM_ARCH_PXA3XX_REGS_H 13#ifndef __ASM_ARCH_PXA3XX_REGS_H
14#define __ASM_ARCH_PXA3XX_REGS_H 14#define __ASM_ARCH_PXA3XX_REGS_H
15 15
16#include <mach/hardware.h>
17
18/*
19 * Static Chip Selects
20 */
21
22#define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */
23#define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */
24#define PXA3xx_CS2_PHYS (0x10000000)
25#define PXA3xx_CS3_PHYS (0x14000000)
26
16/* 27/*
17 * Oscillator Configuration Register (OSCC) 28 * Oscillator Configuration Register (OSCC)
18 */ 29 */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h b/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h
index eb35fca9aea5..3478eae32d8a 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h
@@ -49,6 +49,9 @@ struct pxa3xx_nand_platform_data {
49 */ 49 */
50 int enable_arbiter; 50 int enable_arbiter;
51 51
52 /* allow platform code to keep OBM/bootloader defined NFC config */
53 int keep_config;
54
52 const struct mtd_partition *parts; 55 const struct mtd_partition *parts;
53 unsigned int nr_parts; 56 unsigned int nr_parts;
54 57
diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h
new file mode 100644
index 000000000000..d45f76a9b54d
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa930.h
@@ -0,0 +1,8 @@
1#ifndef __MACH_PXA930_H
2#define __MACH_PXA930_H
3
4#include <mach/hardware.h>
5#include <mach/pxa3xx-regs.h>
6#include <mach/mfp-pxa930.h>
7
8#endif /* __MACH_PXA930_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
new file mode 100644
index 000000000000..ad23e74b762f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-intc.h
@@ -0,0 +1,23 @@
1#ifndef __ASM_MACH_REGS_INTC_H
2#define __ASM_MACH_REGS_INTC_H
3
4#include <mach/hardware.h>
5
6/*
7 * Interrupt Controller
8 */
9
10#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
11#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
12#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
13#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
14#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
15#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
16
17#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
18#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
19#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
20#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
21#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
22
23#endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h
new file mode 100644
index 000000000000..a3e5f86ef67e
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-ost.h
@@ -0,0 +1,34 @@
1#ifndef __ASM_MACH_REGS_OST_H
2#define __ASM_MACH_REGS_OST_H
3
4#include <mach/hardware.h>
5
6/*
7 * OS Timer & Match Registers
8 */
9
10#define OSMR0 __REG(0x40A00000) /* */
11#define OSMR1 __REG(0x40A00004) /* */
12#define OSMR2 __REG(0x40A00008) /* */
13#define OSMR3 __REG(0x40A0000C) /* */
14#define OSMR4 __REG(0x40A00080) /* */
15#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
16#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
17#define OMCR4 __REG(0x40A000C0) /* */
18#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
19#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
20#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
21
22#define OSSR_M3 (1 << 3) /* Match status channel 3 */
23#define OSSR_M2 (1 << 2) /* Match status channel 2 */
24#define OSSR_M1 (1 << 1) /* Match status channel 1 */
25#define OSSR_M0 (1 << 0) /* Match status channel 0 */
26
27#define OWER_WME (1 << 0) /* Watchdog Match Enable */
28
29#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
30#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
31#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
32#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
33
34#endif /* __ASM_MACH_REGS_OST_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-rtc.h b/arch/arm/mach-pxa/include/mach/regs-rtc.h
new file mode 100644
index 000000000000..f0e4a589bbe1
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-rtc.h
@@ -0,0 +1,23 @@
1#ifndef __ASM_MACH_REGS_RTC_H
2#define __ASM_MACH_REGS_RTC_H
3
4#include <mach/hardware.h>
5
6/*
7 * Real Time Clock
8 */
9
10#define RCNR __REG(0x40900000) /* RTC Count Register */
11#define RTAR __REG(0x40900004) /* RTC Alarm Register */
12#define RTSR __REG(0x40900008) /* RTC Status Register */
13#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
14#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
15
16#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
17#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
18#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
19#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
20#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
21#define RTSR_AL (1 << 0) /* RTC alarm detected */
22
23#endif /* __ASM_MACH_REGS_RTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
index cf31986f6f05..6a2ed35acd59 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h
@@ -37,7 +37,6 @@
37#if defined(CONFIG_PXA25x) 37#if defined(CONFIG_PXA25x)
38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ 38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ 39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
40
41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 40#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ 41#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ 42#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
@@ -50,7 +49,7 @@
50#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ 49#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
51#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ 50#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
52#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ 51#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
53#define SSCR0_ADC (1 << 30) /* Audio clock select */ 52#define SSCR0_ACS (1 << 30) /* Audio clock select */
54#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ 53#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
55#endif 54#endif
56 55
@@ -109,6 +108,11 @@
109#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ 108#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
110#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ 109#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
111 110
111#if defined(CONFIG_PXA3xx)
112#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
113#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
114#endif
115
112#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ 116#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
113#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ 117#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
114#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ 118#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h
index 0f381e692999..d1fce8b6d105 100644
--- a/arch/arm/mach-pxa/include/mach/system.h
+++ b/arch/arm/mach-pxa/include/mach/system.h
@@ -13,7 +13,6 @@
13#include <asm/proc-fns.h> 13#include <asm/proc-fns.h>
14#include "hardware.h" 14#include "hardware.h"
15#include "pxa2xx-regs.h" 15#include "pxa2xx-regs.h"
16#include "pxa-regs.h"
17 16
18static inline void arch_idle(void) 17static inline void arch_idle(void)
19{ 18{
@@ -21,4 +20,4 @@ static inline void arch_idle(void)
21} 20}
22 21
23 22
24void arch_reset(char mode); 23void arch_reset(char mode, const char *cmd);
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index f4b029c03957..5706cea95d11 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -35,7 +35,8 @@ static inline void flush(void)
35 35
36static inline void arch_decomp_setup(void) 36static inline void arch_decomp_setup(void)
37{ 37{
38 if (machine_is_littleton() || machine_is_intelmote2()) 38 if (machine_is_littleton() || machine_is_intelmote2()
39 || machine_is_csb726())
39 UART = STUART; 40 UART = STUART;
40} 41}
41 42
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 02:38:13 -0500