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-rw-r--r--arch/arm/mach-pxa/include/mach/mtd-xip.h4
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h82
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h2
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-intc.h23
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ost.h34
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-rtc.h23
-rw-r--r--arch/arm/mach-pxa/include/mach/system.h1
7 files changed, 83 insertions, 86 deletions
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h
index cfca8155be72..297387ec3618 100644
--- a/arch/arm/mach-pxa/include/mach/mtd-xip.h
+++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h
@@ -15,8 +15,8 @@
15#ifndef __ARCH_PXA_MTD_XIP_H__ 15#ifndef __ARCH_PXA_MTD_XIP_H__
16#define __ARCH_PXA_MTD_XIP_H__ 16#define __ARCH_PXA_MTD_XIP_H__
17 17
18#include <mach/hardware.h> 18#include <mach/regs-ost.h>
19#include <mach/pxa-regs.h> 19#include <mach/regs-intc.h>
20 20
21#define xip_irqpending() (ICIP & ICMR) 21#define xip_irqpending() (ICIP & ICMR)
22 22
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
deleted file mode 100644
index 7e1e33a41b81..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * arch/arm/mach-pxa/include/mach/pxa-regs.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PXA_REGS_H
14#define __PXA_REGS_H
15
16#include <mach/hardware.h>
17
18/*
19 * Real Time Clock
20 */
21
22#define RCNR __REG(0x40900000) /* RTC Count Register */
23#define RTAR __REG(0x40900004) /* RTC Alarm Register */
24#define RTSR __REG(0x40900008) /* RTC Status Register */
25#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
26#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
27
28#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
29#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
30#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
31#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
32#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
33#define RTSR_AL (1 << 0) /* RTC alarm detected */
34
35
36/*
37 * OS Timer & Match Registers
38 */
39
40#define OSMR0 __REG(0x40A00000) /* */
41#define OSMR1 __REG(0x40A00004) /* */
42#define OSMR2 __REG(0x40A00008) /* */
43#define OSMR3 __REG(0x40A0000C) /* */
44#define OSMR4 __REG(0x40A00080) /* */
45#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
46#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
47#define OMCR4 __REG(0x40A000C0) /* */
48#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
49#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
50#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
51
52#define OSSR_M3 (1 << 3) /* Match status channel 3 */
53#define OSSR_M2 (1 << 2) /* Match status channel 2 */
54#define OSSR_M1 (1 << 1) /* Match status channel 1 */
55#define OSSR_M0 (1 << 0) /* Match status channel 0 */
56
57#define OWER_WME (1 << 0) /* Watchdog Match Enable */
58
59#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
60#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
61#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
62#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
63
64
65/*
66 * Interrupt Controller
67 */
68
69#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
70#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
71#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
72#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
73#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
74#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
75
76#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
77#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
78#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
79#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
80#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
81
82#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 2f834de5b748..4fcddd9cab76 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -14,7 +14,7 @@
14#ifndef __PXA2XX_REGS_H 14#ifndef __PXA2XX_REGS_H
15#define __PXA2XX_REGS_H 15#define __PXA2XX_REGS_H
16 16
17#include <mach/pxa-regs.h> 17#include <mach/hardware.h>
18 18
19/* 19/*
20 * PXA Chip selects 20 * PXA Chip selects
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
new file mode 100644
index 000000000000..ad23e74b762f
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-intc.h
@@ -0,0 +1,23 @@
1#ifndef __ASM_MACH_REGS_INTC_H
2#define __ASM_MACH_REGS_INTC_H
3
4#include <mach/hardware.h>
5
6/*
7 * Interrupt Controller
8 */
9
10#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
11#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
12#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
13#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
14#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
15#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
16
17#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
18#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
19#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
20#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
21#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
22
23#endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h
new file mode 100644
index 000000000000..a3e5f86ef67e
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-ost.h
@@ -0,0 +1,34 @@
1#ifndef __ASM_MACH_REGS_OST_H
2#define __ASM_MACH_REGS_OST_H
3
4#include <mach/hardware.h>
5
6/*
7 * OS Timer & Match Registers
8 */
9
10#define OSMR0 __REG(0x40A00000) /* */
11#define OSMR1 __REG(0x40A00004) /* */
12#define OSMR2 __REG(0x40A00008) /* */
13#define OSMR3 __REG(0x40A0000C) /* */
14#define OSMR4 __REG(0x40A00080) /* */
15#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
16#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
17#define OMCR4 __REG(0x40A000C0) /* */
18#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
19#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
20#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
21
22#define OSSR_M3 (1 << 3) /* Match status channel 3 */
23#define OSSR_M2 (1 << 2) /* Match status channel 2 */
24#define OSSR_M1 (1 << 1) /* Match status channel 1 */
25#define OSSR_M0 (1 << 0) /* Match status channel 0 */
26
27#define OWER_WME (1 << 0) /* Watchdog Match Enable */
28
29#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
30#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
31#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
32#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
33
34#endif /* __ASM_MACH_REGS_OST_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-rtc.h b/arch/arm/mach-pxa/include/mach/regs-rtc.h
new file mode 100644
index 000000000000..f0e4a589bbe1
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/regs-rtc.h
@@ -0,0 +1,23 @@
1#ifndef __ASM_MACH_REGS_RTC_H
2#define __ASM_MACH_REGS_RTC_H
3
4#include <mach/hardware.h>
5
6/*
7 * Real Time Clock
8 */
9
10#define RCNR __REG(0x40900000) /* RTC Count Register */
11#define RTAR __REG(0x40900004) /* RTC Alarm Register */
12#define RTSR __REG(0x40900008) /* RTC Status Register */
13#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
14#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
15
16#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
17#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
18#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
19#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
20#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
21#define RTSR_AL (1 << 0) /* RTC alarm detected */
22
23#endif /* __ASM_MACH_REGS_RTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h
index 0f381e692999..0a587c4ec709 100644
--- a/arch/arm/mach-pxa/include/mach/system.h
+++ b/arch/arm/mach-pxa/include/mach/system.h
@@ -13,7 +13,6 @@
13#include <asm/proc-fns.h> 13#include <asm/proc-fns.h>
14#include "hardware.h" 14#include "hardware.h"
15#include "pxa2xx-regs.h" 15#include "pxa2xx-regs.h"
16#include "pxa-regs.h"
17 16
18static inline void arch_idle(void) 17static inline void arch_idle(void)
19{ 18{
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 06:57:25 -0500