aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-pxa/include/mach/regs-lcd.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/regs-lcd.h')
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-lcd.h34
1 files changed, 25 insertions, 9 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
index aff3b876a7bf..f82dcea792d9 100644
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h
@@ -12,7 +12,8 @@
12#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ 12#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
13#define LCCR4 (0x010) /* LCD Controller Control Register 4 */ 13#define LCCR4 (0x010) /* LCD Controller Control Register 4 */
14#define LCCR5 (0x014) /* LCD Controller Control Register 5 */ 14#define LCCR5 (0x014) /* LCD Controller Control Register 5 */
15#define LCSR (0x038) /* LCD Controller Status Register */ 15#define LCSR (0x038) /* LCD Controller Status Register 0 */
16#define LCSR1 (0x034) /* LCD Controller Status Register 1 */
16#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ 17#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */
17#define TMEDRGBR (0x040) /* TMED RGB Seed Register */ 18#define TMEDRGBR (0x040) /* TMED RGB Seed Register */
18#define TMEDCR (0x044) /* TMED Control Register */ 19#define TMEDCR (0x044) /* TMED Control Register */
@@ -25,6 +26,11 @@
25#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ 26#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
26#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ 27#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
27 28
29#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */
30#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */
31#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */
32#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */
33
28#define CMDCR (0x100) /* Command Control Register */ 34#define CMDCR (0x100) /* Command Control Register */
29#define PRSR (0x104) /* Panel Read Status Register */ 35#define PRSR (0x104) /* Panel Read Status Register */
30 36
@@ -42,16 +48,12 @@
42#define LCCR4_PAL_FOR_MASK (3 << 15) 48#define LCCR4_PAL_FOR_MASK (3 << 15)
43 49
44#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ 50#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
45#define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */
46#define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */
47#define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */
48#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ 51#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
49#define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */ 52#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */
50#define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */ 53#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */
51#define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */ 54#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */
55#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */
52#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ 56#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
53#define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */
54#define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */
55 57
56#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ 58#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
57#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ 59#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
@@ -151,8 +153,22 @@
151#define LCSR_RD_ST (1 << 11) /* read status */ 153#define LCSR_RD_ST (1 << 11) /* read status */
152#define LCSR_CMD_INT (1 << 12) /* command interrupt */ 154#define LCSR_CMD_INT (1 << 12) /* command interrupt */
153 155
156#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */
157#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */
158#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */
159#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */
160
154#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ 161#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
155 162
163/* overlay control registers */
164#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */
165#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */
166#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */
167#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */
168#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */
169#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */
170#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */
171
156/* smartpanel related */ 172/* smartpanel related */
157#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ 173#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */
158#define PRSR_A0 (1 << 8) /* Read Data Source */ 174#define PRSR_A0 (1 << 8) /* Read Data Source */