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-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 806ecfea44bf..77102d695cc7 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -49,6 +49,11 @@
49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ 49#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ 50#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
51 51
52#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
53#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
54#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
55#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
56
52#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ 57#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
53#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ 58#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
54#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ 59#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
@@ -243,4 +248,11 @@
243#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ 248#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
244#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ 249#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
245 250
251/* PWRMODE register M field values */
252
253#define PWRMODE_IDLE 0x1
254#define PWRMODE_STANDBY 0x2
255#define PWRMODE_SLEEP 0x3
256#define PWRMODE_DEEPSLEEP 0x7
257
246#endif 258#endif