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Diffstat (limited to 'arch/arm/mach-pxa/include/mach/pxa27x-udc.h')
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa27x-udc.h257
1 files changed, 257 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x-udc.h b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h
new file mode 100644
index 000000000000..ab1443f8bd89
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h
@@ -0,0 +1,257 @@
1#ifndef _ASM_ARCH_PXA27X_UDC_H
2#define _ASM_ARCH_PXA27X_UDC_H
3
4#ifdef _ASM_ARCH_PXA25X_UDC_H
5#error You cannot include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDCCR __REG(0x40600000) /* UDC Control Register */
9#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
10#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
11 Protocol Port Support */
12#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
13 Support */
14#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
15 Enable */
16#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
17#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
18#define UDCCR_ACN_S 11
19#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
20#define UDCCR_AIN_S 8
21#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
22 Setting Number */
23#define UDCCR_AAISN_S 5
24#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
25 Configuration */
26#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
27 Error */
28#define UDCCR_UDR (1 << 2) /* UDC Resume */
29#define UDCCR_UDA (1 << 1) /* UDC Active */
30#define UDCCR_UDE (1 << 0) /* UDC Enable */
31
32#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
34#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
35#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
36
37#define UDC_INT_FIFOERROR (0x2)
38#define UDC_INT_PACKETCMP (0x1)
39
40#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
41#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
42#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
43#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
44#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
45#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
46
47#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
49#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
50#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
51#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
52#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
53#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
54#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
55
56#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
58#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
59#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
60 Rising Edge Interrupt Enable */
61#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
62 Falling Edge Interrupt Enable */
63#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
64 Interrupt Enable */
65#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
66 Interrupt Enable */
67#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
68 Interrupt Enable */
69#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
70 Interrupt Enable */
71#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
72 Interrupt Enable */
73#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
74 Interrupt Enable */
75#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
76 Edge Interrupt Enable */
77#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
78 Edge Interrupt Enable */
79#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
80 Interrupt Enable */
81#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
82 Interrupt Enable */
83
84#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
85#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
86
87#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
88#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
89#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
90#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
91#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
92#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
93#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
94#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
95#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
96#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
97#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
98#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
99#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
100#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */
101
102#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
103#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
104#define UDCCSR0_SA (1 << 7) /* Setup Active */
105#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
106#define UDCCSR0_FST (1 << 5) /* Force Stall */
107#define UDCCSR0_SST (1 << 4) /* Sent Stall */
108#define UDCCSR0_DME (1 << 3) /* DMA Enable */
109#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
110#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
111#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
112
113#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
114#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
115#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
116#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
117#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
118#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
119#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
120#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
121#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
122#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
123#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
124#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
125#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
126#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
127#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
128#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
129#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
130#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
131#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
132#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
133#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
134#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
135#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
136
137#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
138#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
139#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
140#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
141#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
142#define UDCCSR_FST (1 << 5) /* Force STALL */
143#define UDCCSR_SST (1 << 4) /* Sent STALL */
144#define UDCCSR_DME (1 << 3) /* DMA Enable */
145#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
146#define UDCCSR_PC (1 << 1) /* Packet Complete */
147#define UDCCSR_FS (1 << 0) /* FIFO needs service */
148
149#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
150#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
151#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
152#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
153#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
154#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
155#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
156#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
157#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
158#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
159#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
160#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
161#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
162#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
163#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
164#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
165#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
166#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
167#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
168#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
169#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
170#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
171#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
172#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
173#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
174
175#define UDCDN(x) __REG2(0x40600300, (x)<<2)
176#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
177#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
178#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
179#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
180#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
181#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
182#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
183#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
184#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
185#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
186#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
187#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
188#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
189#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
190#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
191#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
192#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
193#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
194#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
195#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
196#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
197#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
198#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
199#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
200#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
201#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
202
203#define UDCCN(x) __REG2(0x40600400, (x)<<2)
204#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
205#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
206#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
207#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
208#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
209#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
210#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
211#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
212#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
213#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
214#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
215#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
216#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
217#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
218#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
219#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
220#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
221#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
222#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
223#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
224#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
225#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
226#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
227
228#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
229#define UDCCONR_CN_S (25)
230#define UDCCONR_IN (0x07 << 22) /* Interface Number */
231#define UDCCONR_IN_S (22)
232#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
233#define UDCCONR_AISN_S (19)
234#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
235#define UDCCONR_EN_S (15)
236#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
237#define UDCCONR_ET_S (13)
238#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
239#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
240#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
241#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
242#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
243#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
244#define UDCCONR_MPS_S (2)
245#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
246#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
247
248
249#define UDC_INT_FIFOERROR (0x2)
250#define UDC_INT_PACKETCMP (0x1)
251
252#define UDC_FNR_MASK (0x7ff)
253
254#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
255#define UDC_BCR_MASK (0x3ff)
256
257#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 00:32:48 -0500