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-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h320
1 files changed, 9 insertions, 311 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index 12288ca3cbb2..15295d960000 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -69,30 +69,18 @@
69/* 69/*
70 * DMA Controller 70 * DMA Controller
71 */ 71 */
72
73#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
74#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
75#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
76#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
77#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
78#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
79#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
80#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
81#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
82#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
83#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
84#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
85#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
86#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
87#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
88#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
89
90#define DCSR(x) __REG2(0x40000000, (x) << 2) 72#define DCSR(x) __REG2(0x40000000, (x) << 2)
91 73
92#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ 74#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
93#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ 75#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
94#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ 76#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
95#ifdef CONFIG_PXA27x 77#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
78#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
79#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
80#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
81#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
82
83#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
96#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ 84#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
97#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ 85#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
98#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ 86#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
@@ -101,11 +89,6 @@
101#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ 89#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
102#define DCSR_EORINTR (1 << 9) /* The end of Receive */ 90#define DCSR_EORINTR (1 << 9) /* The end of Receive */
103#endif 91#endif
104#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
105#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
106#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
107#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
108#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
109 92
110#define DALGN __REG(0x400000a0) /* DMA Alignment Register */ 93#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
111#define DINT __REG(0x400000f0) /* DMA Interrupt Register */ 94#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
@@ -114,145 +97,9 @@
114 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \ 97 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
115 &__REG2(0x40001100, ((n) & 0x3f) << 2))) 98 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
116 99
117#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
118#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
119#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
120#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
121#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
122#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
123#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
124#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
125#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
126#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
127#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
128#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
129#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
130#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
131#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
132#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
133#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
134#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
135#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
136#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
137#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
138#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
139#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
140#define DRCMR23 __REG(0x4000015c) /* Reserved */
141#define DRCMR24 __REG(0x40000160) /* Reserved */
142#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
143#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
144#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
145#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
146#define DRCMR29 __REG(0x40000174) /* Reserved */
147#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
148#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
149#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
150#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
151#define DRCMR34 __REG(0x40000188) /* Reserved */
152#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
153#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
154#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
155#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
156#define DRCMR39 __REG(0x4000019C) /* Reserved */
157#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
158#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
159#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
160#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
161#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
162
163#define DRCMRRXSADR DRCMR2
164#define DRCMRTXSADR DRCMR3
165#define DRCMRRXBTRBR DRCMR4
166#define DRCMRTXBTTHR DRCMR5
167#define DRCMRRXFFRBR DRCMR6
168#define DRCMRTXFFTHR DRCMR7
169#define DRCMRRXMCDR DRCMR8
170#define DRCMRRXMODR DRCMR9
171#define DRCMRTXMODR DRCMR10
172#define DRCMRRXPCDR DRCMR11
173#define DRCMRTXPCDR DRCMR12
174#define DRCMRRXSSDR DRCMR13
175#define DRCMRTXSSDR DRCMR14
176#define DRCMRRXSS2DR DRCMR15
177#define DRCMRTXSS2DR DRCMR16
178#define DRCMRRXICDR DRCMR17
179#define DRCMRTXICDR DRCMR18
180#define DRCMRRXSTRBR DRCMR19
181#define DRCMRTXSTTHR DRCMR20
182#define DRCMRRXMMC DRCMR21
183#define DRCMRTXMMC DRCMR22
184#define DRCMRRXSS3DR DRCMR66
185#define DRCMRTXSS3DR DRCMR67
186#define DRCMRUDC(x) DRCMR((x) + 24)
187
188#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ 100#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
189#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ 101#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
190 102
191#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
192#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
193#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
194#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
195#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
196#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
197#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
198#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
199#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
200#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
201#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
202#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
203#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
204#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
205#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
206#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
207#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
208#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
209#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
210#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
211#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
212#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
213#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
214#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
215#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
216#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
217#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
218#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
219#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
220#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
221#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
222#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
223#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
224#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
225#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
226#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
227#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
228#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
229#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
230#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
231#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
232#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
233#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
234#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
235#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
236#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
237#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
238#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
239#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
240#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
241#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
242#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
243#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
244#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
245#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
246#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
247#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
248#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
249#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
250#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
251#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
252#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
253#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
254#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
255
256#define DDADR(x) __REG2(0x40000200, (x) << 4) 103#define DDADR(x) __REG2(0x40000200, (x) << 4)
257#define DSADR(x) __REG2(0x40000204, (x) << 4) 104#define DSADR(x) __REG2(0x40000204, (x) << 4)
258#define DTADR(x) __REG2(0x40000208, (x) << 4) 105#define DTADR(x) __REG2(0x40000208, (x) << 4)
@@ -418,91 +265,13 @@
418 265
419 266
420/* 267/*
421 * I2C registers 268 * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
422 */ 269 */
423 270
424#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
425#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
426#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
427#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
428#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
429
430#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
431#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
432#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
433#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
434#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
435
436#define ICR_START (1 << 0) /* start bit */
437#define ICR_STOP (1 << 1) /* stop bit */
438#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
439#define ICR_TB (1 << 3) /* transfer byte bit */
440#define ICR_MA (1 << 4) /* master abort */
441#define ICR_SCLE (1 << 5) /* master clock enable */
442#define ICR_IUE (1 << 6) /* unit enable */
443#define ICR_GCD (1 << 7) /* general call disable */
444#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
445#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
446#define ICR_BEIE (1 << 10) /* enable bus error ints */
447#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
448#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
449#define ICR_SADIE (1 << 13) /* slave address detected int enable */
450#define ICR_UR (1 << 14) /* unit reset */
451
452#define ISR_RWM (1 << 0) /* read/write mode */
453#define ISR_ACKNAK (1 << 1) /* ack/nak status */
454#define ISR_UB (1 << 2) /* unit busy */
455#define ISR_IBB (1 << 3) /* bus busy */
456#define ISR_SSD (1 << 4) /* slave stop detected */
457#define ISR_ALD (1 << 5) /* arbitration loss detected */
458#define ISR_ITE (1 << 6) /* tx buffer empty */
459#define ISR_IRF (1 << 7) /* rx buffer full */
460#define ISR_GCAD (1 << 8) /* general call address detected */
461#define ISR_SAD (1 << 9) /* slave address detected */
462#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
463
464
465/* 271/*
466 * Serial Audio Controller 272 * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
467 */ 273 */
468 274
469#define SACR0 __REG(0x40400000) /* Global Control Register */
470#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
471#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
472#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
473#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
474#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
475#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
476
477#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
478#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
479#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
480#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
481#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
482#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
483#define SACR0_ENB (1 << 0) /* Enable I2S Link */
484#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
485#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
486#define SACR1_DREC (1 << 3) /* Disable Recording Function */
487#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
488
489#define SASR0_I2SOFF (1 << 7) /* Controller Status */
490#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
491#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
492#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
493#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
494#define SASR0_BSY (1 << 2) /* I2S Busy */
495#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
496#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
497
498#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
499#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
500
501#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
502#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
503#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
504#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
505
506/* 275/*
507 * AC97 Controller registers 276 * AC97 Controller registers
508 */ 277 */
@@ -989,77 +758,6 @@
989 758
990#endif 759#endif
991 760
992#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
993/*
994 * UHC: USB Host Controller (OHCI-like) register definitions
995 */
996#define UHC_BASE_PHYS (0x4C000000)
997#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
998#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
999#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
1000#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
1001#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
1002#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
1003#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
1004#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
1005#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
1006#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
1007#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
1008#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
1009#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
1010#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
1011#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
1012#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
1013#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
1014#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
1015
1016#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
1017#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
1018
1019#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
1020#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
1021#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
1022#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
1023#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
1024
1025#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
1026#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
1027#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
1028#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
1029#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
1030#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
1031#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
1032#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
1033#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
1034#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
1035
1036#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
1037#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
1038#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
1039#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
1040#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
1041#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
1042#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
1043#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
1044#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
1045#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
1046#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
1047#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
1048
1049#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
1050#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
1051#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
1052#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
1053#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
1054#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
1055 Interrupt Enable*/
1056#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
1057#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
1058
1059#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
1060
1061#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
1062
1063/* PWRMODE register M field values */ 761/* PWRMODE register M field values */
1064 762
1065#define PWRMODE_IDLE 0x1 763#define PWRMODE_IDLE 0x1
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 19:22:41 -0500