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-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h263
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diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
deleted file mode 100644
index 31d615aa7723..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ /dev/null
@@ -1,263 +0,0 @@
1/*
2 * arch/arm/mach-pxa/include/mach/pxa-regs.h
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PXA_REGS_H
14#define __PXA_REGS_H
15
16#include <mach/hardware.h>
17
18/*
19 * PXA Chip selects
20 */
21
22#define PXA_CS0_PHYS 0x00000000
23#define PXA_CS1_PHYS 0x04000000
24#define PXA_CS2_PHYS 0x08000000
25#define PXA_CS3_PHYS 0x0C000000
26#define PXA_CS4_PHYS 0x10000000
27#define PXA_CS5_PHYS 0x14000000
28
29
30/*
31 * Personal Computer Memory Card International Association (PCMCIA) sockets
32 */
33
34#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
35#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
36#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
37#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
38#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
39
40#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
41#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
42#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
43#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
44
45#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
46#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
47#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
48#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
49
50#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
51 (0x20000000 + (Nb)*PCMCIASp)
52#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
53#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
54 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
55#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
56 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
57
58#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
59#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
60#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
61#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
62
63#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
64#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
65#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
66#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
67
68
69
70/*
71 * DMA Controller
72 */
73#define DCSR(x) __REG2(0x40000000, (x) << 2)
74
75#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
76#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
77#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
78#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
79#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
80#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
81#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
82#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
83
84#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
85#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
86#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
87#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
88#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
89#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
90#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
91#define DCSR_EORINTR (1 << 9) /* The end of Receive */
92#endif
93
94#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
95#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
96
97#define DRCMR(n) (*(((n) < 64) ? \
98 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
99 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
100
101#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
102#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
103
104#define DDADR(x) __REG2(0x40000200, (x) << 4)
105#define DSADR(x) __REG2(0x40000204, (x) << 4)
106#define DTADR(x) __REG2(0x40000208, (x) << 4)
107#define DCMD(x) __REG2(0x4000020c, (x) << 4)
108
109#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
110#define DDADR_STOP (1 << 0) /* Stop (read / write) */
111
112#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
113#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
114#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
115#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
116#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
117#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
118#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
119#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
120#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
121#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
122#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
123#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
124#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
125#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
126
127/*
128 * Real Time Clock
129 */
130
131#define RCNR __REG(0x40900000) /* RTC Count Register */
132#define RTAR __REG(0x40900004) /* RTC Alarm Register */
133#define RTSR __REG(0x40900008) /* RTC Status Register */
134#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
135#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
136
137#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
138#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
139#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
140#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
141#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
142#define RTSR_AL (1 << 0) /* RTC alarm detected */
143
144
145/*
146 * OS Timer & Match Registers
147 */
148
149#define OSMR0 __REG(0x40A00000) /* */
150#define OSMR1 __REG(0x40A00004) /* */
151#define OSMR2 __REG(0x40A00008) /* */
152#define OSMR3 __REG(0x40A0000C) /* */
153#define OSMR4 __REG(0x40A00080) /* */
154#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
155#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
156#define OMCR4 __REG(0x40A000C0) /* */
157#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
158#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
159#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
160
161#define OSSR_M3 (1 << 3) /* Match status channel 3 */
162#define OSSR_M2 (1 << 2) /* Match status channel 2 */
163#define OSSR_M1 (1 << 1) /* Match status channel 1 */
164#define OSSR_M0 (1 << 0) /* Match status channel 0 */
165
166#define OWER_WME (1 << 0) /* Watchdog Match Enable */
167
168#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
169#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
170#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
171#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
172
173
174/*
175 * Interrupt Controller
176 */
177
178#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
179#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
180#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
181#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
182#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
183#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
184
185#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
186#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
187#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
188#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
189#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
190
191/*
192 * General Purpose I/O
193 */
194
195#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
196#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
197#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
198
199#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
200#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
201#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
202
203#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
204#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
205#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
206
207#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
208#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
209#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
210
211#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
212#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
213#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
214
215#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
216#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
217#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
218
219#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
220#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
221#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
222
223#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
224#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
225#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
226#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
227#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
228#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
229#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
230#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
231
232#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
233#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
234#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
235#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
236#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
237#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
238#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
239
240/* More handy macros. The argument is a literal GPIO number. */
241
242#define GPIO_bit(x) (1 << ((x) & 0x1f))
243
244#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
245#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
246#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
247#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
248#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
249#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
250#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
251#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
252
253#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
254#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
255#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
256#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
257#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
258#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
259#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
260#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
261 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
262
263#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 09:48:34 -0500