diff options
Diffstat (limited to 'arch/arm/mach-prima2/rstc.c')
| -rw-r--r-- | arch/arm/mach-prima2/rstc.c | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c index 4887a2a4c698..3dffcb2d714e 100644 --- a/arch/arm/mach-prima2/rstc.c +++ b/arch/arm/mach-prima2/rstc.c | |||
| @@ -36,27 +36,33 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev, | |||
| 36 | 36 | ||
| 37 | if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) { | 37 | if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) { |
| 38 | /* | 38 | /* |
| 39 | * Writing 1 to this bit resets corresponding block. Writing 0 to this | 39 | * Writing 1 to this bit resets corresponding block. |
| 40 | * bit de-asserts reset signal of the corresponding block. | 40 | * Writing 0 to this bit de-asserts reset signal of the |
| 41 | * datasheet doesn't require explicit delay between the set and clear | 41 | * corresponding block. datasheet doesn't require explicit |
| 42 | * of reset bit. it could be shorter if tests pass. | 42 | * delay between the set and clear of reset bit. it could |
| 43 | * be shorter if tests pass. | ||
| 43 | */ | 44 | */ |
| 44 | writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit), | 45 | writel(readl(sirfsoc_rstc_base + |
| 46 | (reset_bit / 32) * 4) | (1 << reset_bit), | ||
| 45 | sirfsoc_rstc_base + (reset_bit / 32) * 4); | 47 | sirfsoc_rstc_base + (reset_bit / 32) * 4); |
| 46 | msleep(10); | 48 | msleep(20); |
| 47 | writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit), | 49 | writel(readl(sirfsoc_rstc_base + |
| 50 | (reset_bit / 32) * 4) & ~(1 << reset_bit), | ||
| 48 | sirfsoc_rstc_base + (reset_bit / 32) * 4); | 51 | sirfsoc_rstc_base + (reset_bit / 32) * 4); |
| 49 | } else { | 52 | } else { |
| 50 | /* | 53 | /* |
| 51 | * For MARCO and POLO | 54 | * For MARCO and POLO |
| 52 | * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR | 55 | * Writing 1 to SET register resets corresponding block. |
| 53 | * register de-asserts reset signal of the corresponding block. | 56 | * Writing 1 to CLEAR register de-asserts reset signal of the |
| 54 | * datasheet doesn't require explicit delay between the set and clear | 57 | * corresponding block. |
| 55 | * of reset bit. it could be shorter if tests pass. | 58 | * datasheet doesn't require explicit delay between the set and |
| 59 | * clear of reset bit. it could be shorter if tests pass. | ||
| 56 | */ | 60 | */ |
| 57 | writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8); | 61 | writel(1 << reset_bit, |
| 58 | msleep(10); | 62 | sirfsoc_rstc_base + (reset_bit / 32) * 8); |
| 59 | writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4); | 63 | msleep(20); |
| 64 | writel(1 << reset_bit, | ||
| 65 | sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4); | ||
| 60 | } | 66 | } |
| 61 | 67 | ||
| 62 | mutex_unlock(&rstc_lock); | 68 | mutex_unlock(&rstc_lock); |