diff options
Diffstat (limited to 'arch/arm/mach-orion')
-rw-r--r-- | arch/arm/mach-orion/addr-map.c | 144 | ||||
-rw-r--r-- | arch/arm/mach-orion/common.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-orion/common.h | 23 | ||||
-rw-r--r-- | arch/arm/mach-orion/db88f5281-setup.c | 13 | ||||
-rw-r--r-- | arch/arm/mach-orion/dns323-setup.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-orion/kurobox_pro-setup.c | 12 | ||||
-rw-r--r-- | arch/arm/mach-orion/rd88f5182-setup.c | 11 | ||||
-rw-r--r-- | arch/arm/mach-orion/ts209-setup.c | 8 |
8 files changed, 76 insertions, 144 deletions
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c index 3de5de9ac656..ca641db6214d 100644 --- a/arch/arm/mach-orion/addr-map.c +++ b/arch/arm/mach-orion/addr-map.c | |||
@@ -25,10 +25,10 @@ | |||
25 | * CPU address decoding -- | 25 | * CPU address decoding -- |
26 | * Linux assumes that it is the boot loader that already setup the access to | 26 | * Linux assumes that it is the boot loader that already setup the access to |
27 | * DDR and internal registers. | 27 | * DDR and internal registers. |
28 | * Setup access to PCI and PCI-E IO/MEM space is issued by core.c. | 28 | * Setup access to PCI and PCI-E IO/MEM space is issued by this file. |
29 | * Setup access to various devices located on the device bus interface (e.g. | 29 | * Setup access to various devices located on the device bus interface (e.g. |
30 | * flashes, RTC, etc) should be issued by machine-setup.c according to | 30 | * flashes, RTC, etc) should be issued by machine-setup.c according to |
31 | * specific board population (by using orion_setup_cpu_win()). | 31 | * specific board population (by using orion_setup_*_win()). |
32 | * | 32 | * |
33 | * Non-CPU Masters address decoding -- | 33 | * Non-CPU Masters address decoding -- |
34 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR | 34 | * Unlike the CPU, we setup the access from Orion's master interfaces to DDR |
@@ -53,6 +53,7 @@ | |||
53 | ((n) == 3) ? 0x7 : 0xf) | 53 | ((n) == 3) ? 0x7 : 0xf) |
54 | #define ATTR_PCIE_MEM 0x59 | 54 | #define ATTR_PCIE_MEM 0x59 |
55 | #define ATTR_PCIE_IO 0x51 | 55 | #define ATTR_PCIE_IO 0x51 |
56 | #define ATTR_PCIE_WA 0x79 | ||
56 | #define ATTR_PCI_MEM 0x59 | 57 | #define ATTR_PCI_MEM 0x59 |
57 | #define ATTR_PCI_IO 0x51 | 58 | #define ATTR_PCI_IO 0x51 |
58 | #define ATTR_DEV_CS0 0x1e | 59 | #define ATTR_DEV_CS0 0x1e |
@@ -78,19 +79,6 @@ | |||
78 | #define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) | 79 | #define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4)) |
79 | #define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) | 80 | #define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4)) |
80 | #define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) | 81 | #define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4)) |
81 | #define CPU_MAX_WIN 8 | ||
82 | |||
83 | /* | ||
84 | * Use this CPU address decode windows allocation | ||
85 | */ | ||
86 | #define CPU_WIN_PCIE_IO 0 | ||
87 | #define CPU_WIN_PCI_IO 1 | ||
88 | #define CPU_WIN_PCIE_MEM 2 | ||
89 | #define CPU_WIN_PCI_MEM 3 | ||
90 | #define CPU_WIN_DEV_BOOT 4 | ||
91 | #define CPU_WIN_DEV_CS0 5 | ||
92 | #define CPU_WIN_DEV_CS1 6 | ||
93 | #define CPU_WIN_DEV_CS2 7 | ||
94 | 82 | ||
95 | /* | 83 | /* |
96 | * Gigabit Ethernet Address Decode Windows registers | 84 | * Gigabit Ethernet Address Decode Windows registers |
@@ -106,7 +94,7 @@ | |||
106 | 94 | ||
107 | struct mbus_dram_target_info orion_mbus_dram_info; | 95 | struct mbus_dram_target_info orion_mbus_dram_info; |
108 | 96 | ||
109 | static int __init orion_cpu_win_can_remap(u32 win) | 97 | static int __init orion_cpu_win_can_remap(int win) |
110 | { | 98 | { |
111 | u32 dev, rev; | 99 | u32 dev, rev; |
112 | 100 | ||
@@ -119,88 +107,31 @@ static int __init orion_cpu_win_can_remap(u32 win) | |||
119 | return 0; | 107 | return 0; |
120 | } | 108 | } |
121 | 109 | ||
122 | void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap) | 110 | static void __init setup_cpu_win(int win, u32 base, u32 size, |
111 | u8 target, u8 attr, int remap) | ||
123 | { | 112 | { |
124 | u32 win, attr, ctrl; | 113 | orion_write(CPU_WIN_BASE(win), base & 0xffff0000); |
125 | 114 | orion_write(CPU_WIN_CTRL(win), | |
126 | switch (target) { | 115 | ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); |
127 | case ORION_PCIE_IO: | ||
128 | target = TARGET_PCIE; | ||
129 | attr = ATTR_PCIE_IO; | ||
130 | win = CPU_WIN_PCIE_IO; | ||
131 | break; | ||
132 | case ORION_PCI_IO: | ||
133 | target = TARGET_PCI; | ||
134 | attr = ATTR_PCI_IO; | ||
135 | win = CPU_WIN_PCI_IO; | ||
136 | break; | ||
137 | case ORION_PCIE_MEM: | ||
138 | target = TARGET_PCIE; | ||
139 | attr = ATTR_PCIE_MEM; | ||
140 | win = CPU_WIN_PCIE_MEM; | ||
141 | break; | ||
142 | case ORION_PCI_MEM: | ||
143 | target = TARGET_PCI; | ||
144 | attr = ATTR_PCI_MEM; | ||
145 | win = CPU_WIN_PCI_MEM; | ||
146 | break; | ||
147 | case ORION_DEV_BOOT: | ||
148 | target = TARGET_DEV_BUS; | ||
149 | attr = ATTR_DEV_BOOT; | ||
150 | win = CPU_WIN_DEV_BOOT; | ||
151 | break; | ||
152 | case ORION_DEV0: | ||
153 | target = TARGET_DEV_BUS; | ||
154 | attr = ATTR_DEV_CS0; | ||
155 | win = CPU_WIN_DEV_CS0; | ||
156 | break; | ||
157 | case ORION_DEV1: | ||
158 | target = TARGET_DEV_BUS; | ||
159 | attr = ATTR_DEV_CS1; | ||
160 | win = CPU_WIN_DEV_CS1; | ||
161 | break; | ||
162 | case ORION_DEV2: | ||
163 | target = TARGET_DEV_BUS; | ||
164 | attr = ATTR_DEV_CS2; | ||
165 | win = CPU_WIN_DEV_CS2; | ||
166 | break; | ||
167 | case ORION_DDR: | ||
168 | case ORION_REGS: | ||
169 | /* | ||
170 | * Must be mapped by bootloader. | ||
171 | */ | ||
172 | default: | ||
173 | target = attr = win = -1; | ||
174 | BUG(); | ||
175 | } | ||
176 | |||
177 | base &= 0xffff0000; | ||
178 | ctrl = (((size - 1) & 0xffff0000) | (attr << 8) | | ||
179 | (target << 4) | WIN_EN); | ||
180 | |||
181 | orion_write(CPU_WIN_BASE(win), base); | ||
182 | orion_write(CPU_WIN_CTRL(win), ctrl); | ||
183 | 116 | ||
184 | if (orion_cpu_win_can_remap(win)) { | 117 | if (orion_cpu_win_can_remap(win)) { |
185 | if (remap >= 0) { | 118 | if (remap < 0) |
186 | orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); | 119 | remap = base; |
187 | orion_write(CPU_WIN_REMAP_HI(win), 0); | 120 | |
188 | } else { | 121 | orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); |
189 | orion_write(CPU_WIN_REMAP_LO(win), base); | 122 | orion_write(CPU_WIN_REMAP_HI(win), 0); |
190 | orion_write(CPU_WIN_REMAP_HI(win), 0); | ||
191 | } | ||
192 | } | 123 | } |
193 | } | 124 | } |
194 | 125 | ||
195 | void __init orion_setup_cpu_wins(void) | 126 | void __init orion_setup_cpu_mbus_bridge(void) |
196 | { | 127 | { |
197 | int i; | 128 | int i; |
198 | int cs; | 129 | int cs; |
199 | 130 | ||
200 | /* | 131 | /* |
201 | * First, disable and clear windows | 132 | * First, disable and clear windows. |
202 | */ | 133 | */ |
203 | for (i = 0; i < CPU_MAX_WIN; i++) { | 134 | for (i = 0; i < 8; i++) { |
204 | orion_write(CPU_WIN_BASE(i), 0); | 135 | orion_write(CPU_WIN_BASE(i), 0); |
205 | orion_write(CPU_WIN_CTRL(i), 0); | 136 | orion_write(CPU_WIN_CTRL(i), 0); |
206 | if (orion_cpu_win_can_remap(i)) { | 137 | if (orion_cpu_win_can_remap(i)) { |
@@ -212,14 +143,14 @@ void __init orion_setup_cpu_wins(void) | |||
212 | /* | 143 | /* |
213 | * Setup windows for PCI+PCIe IO+MEM space. | 144 | * Setup windows for PCI+PCIe IO+MEM space. |
214 | */ | 145 | */ |
215 | orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE, | 146 | setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE, |
216 | ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE); | 147 | TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE); |
217 | orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE, | 148 | setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE, |
218 | ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE); | 149 | TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE); |
219 | orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE, | 150 | setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE, |
220 | ORION_PCIE_MEM_SIZE, -1); | 151 | TARGET_PCIE, ATTR_PCIE_MEM, -1); |
221 | orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE, | 152 | setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE, |
222 | ORION_PCI_MEM_SIZE, -1); | 153 | TARGET_PCI, ATTR_PCI_MEM, -1); |
223 | 154 | ||
224 | /* | 155 | /* |
225 | * Setup MBUS dram target info. | 156 | * Setup MBUS dram target info. |
@@ -246,6 +177,31 @@ void __init orion_setup_cpu_wins(void) | |||
246 | orion_mbus_dram_info.num_cs = cs; | 177 | orion_mbus_dram_info.num_cs = cs; |
247 | } | 178 | } |
248 | 179 | ||
180 | void __init orion_setup_dev_boot_win(u32 base, u32 size) | ||
181 | { | ||
182 | setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); | ||
183 | } | ||
184 | |||
185 | void __init orion_setup_dev0_win(u32 base, u32 size) | ||
186 | { | ||
187 | setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); | ||
188 | } | ||
189 | |||
190 | void __init orion_setup_dev1_win(u32 base, u32 size) | ||
191 | { | ||
192 | setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); | ||
193 | } | ||
194 | |||
195 | void __init orion_setup_dev2_win(u32 base, u32 size) | ||
196 | { | ||
197 | setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); | ||
198 | } | ||
199 | |||
200 | void __init orion_setup_pcie_wa_win(u32 base, u32 size) | ||
201 | { | ||
202 | setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); | ||
203 | } | ||
204 | |||
249 | void __init orion_setup_eth_wins(void) | 205 | void __init orion_setup_eth_wins(void) |
250 | { | 206 | { |
251 | int i; | 207 | int i; |
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c index 1b5ed72899e5..e271994d27fe 100644 --- a/arch/arm/mach-orion/common.c +++ b/arch/arm/mach-orion/common.c | |||
@@ -359,7 +359,7 @@ void __init orion_init(void) | |||
359 | /* | 359 | /* |
360 | * Setup Orion address map | 360 | * Setup Orion address map |
361 | */ | 361 | */ |
362 | orion_setup_cpu_wins(); | 362 | orion_setup_cpu_mbus_bridge(); |
363 | orion_setup_eth_wins(); | 363 | orion_setup_eth_wins(); |
364 | 364 | ||
365 | /* | 365 | /* |
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h index 3898e1b78ee4..74f23e61c401 100644 --- a/arch/arm/mach-orion/common.h +++ b/arch/arm/mach-orion/common.h | |||
@@ -15,24 +15,13 @@ extern struct sys_timer orion_timer; | |||
15 | * functions to map its interfaces and by the machine-setup to map its on- | 15 | * functions to map its interfaces and by the machine-setup to map its on- |
16 | * board devices. Details in /mach-orion/addr-map.c | 16 | * board devices. Details in /mach-orion/addr-map.c |
17 | */ | 17 | */ |
18 | |||
19 | enum orion_target { | ||
20 | ORION_DEV_BOOT = 0, | ||
21 | ORION_DEV0, | ||
22 | ORION_DEV1, | ||
23 | ORION_DEV2, | ||
24 | ORION_PCIE_MEM, | ||
25 | ORION_PCIE_IO, | ||
26 | ORION_PCI_MEM, | ||
27 | ORION_PCI_IO, | ||
28 | ORION_DDR, | ||
29 | ORION_REGS, | ||
30 | ORION_MAX_TARGETS | ||
31 | }; | ||
32 | |||
33 | extern struct mbus_dram_target_info orion_mbus_dram_info; | 18 | extern struct mbus_dram_target_info orion_mbus_dram_info; |
34 | void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap); | 19 | void orion_setup_cpu_mbus_bridge(void); |
35 | void orion_setup_cpu_wins(void); | 20 | void orion_setup_dev_boot_win(u32 base, u32 size); |
21 | void orion_setup_dev0_win(u32 base, u32 size); | ||
22 | void orion_setup_dev1_win(u32 base, u32 size); | ||
23 | void orion_setup_dev2_win(u32 base, u32 size); | ||
24 | void orion_setup_pcie_wa_win(u32 base, u32 size); | ||
36 | void orion_setup_eth_wins(void); | 25 | void orion_setup_eth_wins(void); |
37 | 26 | ||
38 | /* | 27 | /* |
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c index 5cf65fedfae2..aad62efa1daf 100644 --- a/arch/arm/mach-orion/db88f5281-setup.c +++ b/arch/arm/mach-orion/db88f5281-setup.c | |||
@@ -317,14 +317,11 @@ static void __init db88f5281_init(void) | |||
317 | /* | 317 | /* |
318 | * Setup the CPU address decode windows for our on-board devices | 318 | * Setup the CPU address decode windows for our on-board devices |
319 | */ | 319 | */ |
320 | orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE, | 320 | orion_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, |
321 | DB88F5281_NOR_BOOT_SIZE, -1); | 321 | DB88F5281_NOR_BOOT_SIZE); |
322 | orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE, | 322 | orion_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); |
323 | DB88F5281_7SEG_SIZE, -1); | 323 | orion_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); |
324 | orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE, | 324 | orion_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); |
325 | DB88F5281_NOR_SIZE, -1); | ||
326 | orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE, | ||
327 | DB88F5281_NAND_SIZE, -1); | ||
328 | 325 | ||
329 | /* | 326 | /* |
330 | * Setup Multiplexing Pins: | 327 | * Setup Multiplexing Pins: |
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c index 38593784d76f..88991f764794 100644 --- a/arch/arm/mach-orion/dns323-setup.c +++ b/arch/arm/mach-orion/dns323-setup.c | |||
@@ -251,16 +251,13 @@ static void __init dns323_init(void) | |||
251 | /* setup flash mapping | 251 | /* setup flash mapping |
252 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 | 252 | * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 |
253 | */ | 253 | */ |
254 | orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE, | 254 | orion_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); |
255 | DNS323_NOR_BOOT_SIZE, -1); | ||
256 | 255 | ||
257 | /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE | 256 | /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE |
258 | * | 257 | * |
259 | * Open a special address decode windows for the PCIE WA. | 258 | * Open a special address decode windows for the PCIE WA. |
260 | */ | 259 | */ |
261 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 260 | orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); |
262 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, | ||
263 | (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
264 | 261 | ||
265 | /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ | 262 | /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ |
266 | orion_write(MPP_0_7_CTRL, 0); | 263 | orion_write(MPP_0_7_CTRL, 0); |
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c index feae4839830b..bf7034df8a62 100644 --- a/arch/arm/mach-orion/kurobox_pro-setup.c +++ b/arch/arm/mach-orion/kurobox_pro-setup.c | |||
@@ -193,16 +193,14 @@ static void __init kurobox_pro_init(void) | |||
193 | /* | 193 | /* |
194 | * Setup the CPU address decode windows for our devices | 194 | * Setup the CPU address decode windows for our devices |
195 | */ | 195 | */ |
196 | orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE, | 196 | orion_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, |
197 | KUROBOX_PRO_NOR_BOOT_SIZE, -1); | 197 | KUROBOX_PRO_NOR_BOOT_SIZE); |
198 | orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE, | 198 | orion_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); |
199 | KUROBOX_PRO_NAND_SIZE, -1); | 199 | |
200 | /* | 200 | /* |
201 | * Open a special address decode windows for the PCIE WA. | 201 | * Open a special address decode windows for the PCIE WA. |
202 | */ | 202 | */ |
203 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 203 | orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); |
204 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | ||
205 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
206 | 204 | ||
207 | /* | 205 | /* |
208 | * Setup Multiplexing Pins -- | 206 | * Setup Multiplexing Pins -- |
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c index e3cc757a4ca1..662c097ca333 100644 --- a/arch/arm/mach-orion/rd88f5182-setup.c +++ b/arch/arm/mach-orion/rd88f5182-setup.c | |||
@@ -254,17 +254,14 @@ static void __init rd88f5182_init(void) | |||
254 | /* | 254 | /* |
255 | * Setup the CPU address decode windows for our devices | 255 | * Setup the CPU address decode windows for our devices |
256 | */ | 256 | */ |
257 | orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE, | 257 | orion_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, |
258 | RD88F5182_NOR_BOOT_SIZE, -1); | 258 | RD88F5182_NOR_BOOT_SIZE); |
259 | orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE, | 259 | orion_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); |
260 | RD88F5182_NOR_SIZE, -1); | ||
261 | 260 | ||
262 | /* | 261 | /* |
263 | * Open a special address decode windows for the PCIE WA. | 262 | * Open a special address decode windows for the PCIE WA. |
264 | */ | 263 | */ |
265 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 264 | orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); |
266 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | ||
267 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
268 | 265 | ||
269 | /* | 266 | /* |
270 | * Setup Multiplexing Pins -- | 267 | * Setup Multiplexing Pins -- |
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c index 86583e4856a1..8eca070006f1 100644 --- a/arch/arm/mach-orion/ts209-setup.c +++ b/arch/arm/mach-orion/ts209-setup.c | |||
@@ -288,15 +288,13 @@ static void __init qnap_ts209_init(void) | |||
288 | /* | 288 | /* |
289 | * Setup flash mapping | 289 | * Setup flash mapping |
290 | */ | 290 | */ |
291 | orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE, | 291 | orion_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, |
292 | QNAP_TS209_NOR_BOOT_SIZE, -1); | 292 | QNAP_TS209_NOR_BOOT_SIZE); |
293 | 293 | ||
294 | /* | 294 | /* |
295 | * Open a special address decode windows for the PCIE WA. | 295 | * Open a special address decode windows for the PCIE WA. |
296 | */ | 296 | */ |
297 | orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE); | 297 | orion_setup_pcie_wa_win(ORION_PCIE_WA_PHYS_BASE, ORION_PCIE_WA_SIZE); |
298 | orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 | | ||
299 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16)); | ||
300 | 298 | ||
301 | /* | 299 | /* |
302 | * Setup Multiplexing Pins -- | 300 | * Setup Multiplexing Pins -- |