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-rw-r--r--arch/arm/mach-orion/Kconfig41
-rw-r--r--arch/arm/mach-orion/Makefile6
-rw-r--r--arch/arm/mach-orion/Makefile.boot3
-rw-r--r--arch/arm/mach-orion/addr-map.c484
-rw-r--r--arch/arm/mach-orion/common.c315
-rw-r--r--arch/arm/mach-orion/common.h78
-rw-r--r--arch/arm/mach-orion/db88f5281-setup.c364
-rw-r--r--arch/arm/mach-orion/dns323-setup.c322
-rw-r--r--arch/arm/mach-orion/gpio.c225
-rw-r--r--arch/arm/mach-orion/irq.c241
-rw-r--r--arch/arm/mach-orion/kurobox_pro-setup.c234
-rw-r--r--arch/arm/mach-orion/pci.c557
-rw-r--r--arch/arm/mach-orion/rd88f5182-setup.c306
-rw-r--r--arch/arm/mach-orion/time.c181
-rw-r--r--arch/arm/mach-orion/ts209-setup.c335
15 files changed, 3692 insertions, 0 deletions
diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion/Kconfig
new file mode 100644
index 000000000000..1dcbb6ac5a30
--- /dev/null
+++ b/arch/arm/mach-orion/Kconfig
@@ -0,0 +1,41 @@
1if ARCH_ORION
2
3menu "Orion Implementations"
4
5config MACH_DB88F5281
6 bool "Marvell Orion-2 Development Board"
7 select I2C_BOARDINFO
8 help
9 Say 'Y' here if you want your kernel to support the
10 Marvell Orion-2 (88F5281) Development Board
11
12config MACH_RD88F5182
13 bool "Marvell Orion-NAS Reference Design"
14 select I2C_BOARDINFO
15 help
16 Say 'Y' here if you want your kernel to support the
17 Marvell Orion-NAS (88F5182) RD2
18
19config MACH_KUROBOX_PRO
20 bool "KuroBox Pro"
21 select I2C_BOARDINFO
22 help
23 Say 'Y' here if you want your kernel to support the
24 KuroBox Pro platform.
25
26config MACH_DNS323
27 bool "D-Link DNS-323"
28 select I2C_BOARDINFO
29 help
30 Say 'Y' here if you want your kernel to support the
31 D-Link DNS-323 platform.
32
33config MACH_TS209
34 bool "QNAP TS-109/TS-209"
35 help
36 Say 'Y' here if you want your kernel to support the
37 QNAP TS-109/TS-209 platform.
38
39endmenu
40
41endif
diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion/Makefile
new file mode 100644
index 000000000000..f91d937a73e8
--- /dev/null
+++ b/arch/arm/mach-orion/Makefile
@@ -0,0 +1,6 @@
1obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o
2obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
3obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
4obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
5obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
6obj-$(CONFIG_MACH_TS209) += ts209-setup.o
diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-orion/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
new file mode 100644
index 000000000000..488da3811a68
--- /dev/null
+++ b/arch/arm/mach-orion/addr-map.c
@@ -0,0 +1,484 @@
1/*
2 * arch/arm/mach-orion/addr-map.c
3 *
4 * Address map functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <asm/hardware.h>
16#include "common.h"
17
18/*
19 * The Orion has fully programable address map. There's a separate address
20 * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
21 * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
22 * address decode windows that allow it to access any of the Orion resources.
23 *
24 * CPU address decoding --
25 * Linux assumes that it is the boot loader that already setup the access to
26 * DDR and internal registers.
27 * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
28 * Setup access to various devices located on the device bus interface (e.g.
29 * flashes, RTC, etc) should be issued by machine-setup.c according to
30 * specific board population (by using orion_setup_cpu_win()).
31 *
32 * Non-CPU Masters address decoding --
33 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
34 * banks only (the typical use case).
35 * Setup access for each master to DDR is issued by common.c.
36 *
37 * Note: although orion_setbits() and orion_clrbits() are not atomic
38 * no locking is necessary here since code in this file is only called
39 * at boot time when there is no concurrency issues.
40 */
41
42/*
43 * Generic Address Decode Windows bit settings
44 */
45#define TARGET_DDR 0
46#define TARGET_PCI 3
47#define TARGET_PCIE 4
48#define TARGET_DEV_BUS 1
49#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
50 ((n) == 1) ? 0xd : \
51 ((n) == 2) ? 0xb : \
52 ((n) == 3) ? 0x7 : 0xf)
53#define ATTR_PCIE_MEM 0x59
54#define ATTR_PCIE_IO 0x51
55#define ATTR_PCI_MEM 0x59
56#define ATTR_PCI_IO 0x51
57#define ATTR_DEV_CS0 0x1e
58#define ATTR_DEV_CS1 0x1d
59#define ATTR_DEV_CS2 0x1b
60#define ATTR_DEV_BOOT 0xf
61#define WIN_EN 1
62
63/*
64 * Helpers to get DDR banks info
65 */
66#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8))
67#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8))
68#define DDR_MAX_CS 4
69#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
70#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
71#define DDR_BANK_EN 1
72
73/*
74 * CPU Address Decode Windows registers
75 */
76#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4))
77#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4))
78#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4))
79#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4))
80#define CPU_MAX_WIN 8
81
82/*
83 * Use this CPU address decode windows allocation
84 */
85#define CPU_WIN_PCIE_IO 0
86#define CPU_WIN_PCI_IO 1
87#define CPU_WIN_PCIE_MEM 2
88#define CPU_WIN_PCI_MEM 3
89#define CPU_WIN_DEV_BOOT 4
90#define CPU_WIN_DEV_CS0 5
91#define CPU_WIN_DEV_CS1 6
92#define CPU_WIN_DEV_CS2 7
93
94/*
95 * PCIE Address Decode Windows registers
96 */
97#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
98#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8))
99#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8))
100#define PCIE_WIN_CTRL(n) ORION_PCIE_REG(0x1820 + ((n) << 4))
101#define PCIE_WIN_BASE(n) ORION_PCIE_REG(0x1824 + ((n) << 4))
102#define PCIE_WIN_REMAP(n) ORION_PCIE_REG(0x182c + ((n) << 4))
103#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0)
104#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0)
105#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4)
106#define PCIE_MAX_BARS 3
107#define PCIE_MAX_WINS 5
108
109/*
110 * Use PCIE BAR '1' for all DDR banks
111 */
112#define PCIE_DRAM_BAR 1
113
114/*
115 * PCI Address Decode Windows registers
116 */
117#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \
118 ((n) == 1) ? ORION_PCI_REG(0xd08) : \
119 ((n) == 2) ? ORION_PCI_REG(0xc0c) : \
120 ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
121#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
122 ((n) == 1) ? ORION_PCI_REG(0xd48) : \
123 ((n) == 2) ? ORION_PCI_REG(0xc4c) : \
124 ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
125#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c)
126#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4))
127#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4))
128#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4))
129#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c)
130
131/*
132 * PCI configuration heleprs for BAR settings
133 */
134#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
135#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
136#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
137
138/*
139 * Gigabit Ethernet Address Decode Windows registers
140 */
141#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8))
142#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8))
143#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4))
144#define ETH_WIN_EN ORION_ETH_REG(0x290)
145#define ETH_WIN_PROT ORION_ETH_REG(0x294)
146#define ETH_MAX_WIN 6
147#define ETH_MAX_REMAP_WIN 4
148
149/*
150 * USB Address Decode Windows registers
151 */
152#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
153 : ORION_USB1_REG(0x320 + ((w) << 4)))
154#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
155 : ORION_USB1_REG(0x324 + ((w) << 4)))
156#define USB_MAX_WIN 4
157
158/*
159 * SATA Address Decode Windows registers
160 */
161#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10))
162#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10))
163#define SATA_MAX_WIN 4
164
165static int __init orion_cpu_win_can_remap(u32 win)
166{
167 u32 dev, rev;
168
169 orion_pcie_id(&dev, &rev);
170 if ((dev == MV88F5281_DEV_ID && win < 4)
171 || (dev == MV88F5182_DEV_ID && win < 2)
172 || (dev == MV88F5181_DEV_ID && win < 2))
173 return 1;
174
175 return 0;
176}
177
178void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
179{
180 u32 win, attr, ctrl;
181
182 switch (target) {
183 case ORION_PCIE_IO:
184 target = TARGET_PCIE;
185 attr = ATTR_PCIE_IO;
186 win = CPU_WIN_PCIE_IO;
187 break;
188 case ORION_PCI_IO:
189 target = TARGET_PCI;
190 attr = ATTR_PCI_IO;
191 win = CPU_WIN_PCI_IO;
192 break;
193 case ORION_PCIE_MEM:
194 target = TARGET_PCIE;
195 attr = ATTR_PCIE_MEM;
196 win = CPU_WIN_PCIE_MEM;
197 break;
198 case ORION_PCI_MEM:
199 target = TARGET_PCI;
200 attr = ATTR_PCI_MEM;
201 win = CPU_WIN_PCI_MEM;
202 break;
203 case ORION_DEV_BOOT:
204 target = TARGET_DEV_BUS;
205 attr = ATTR_DEV_BOOT;
206 win = CPU_WIN_DEV_BOOT;
207 break;
208 case ORION_DEV0:
209 target = TARGET_DEV_BUS;
210 attr = ATTR_DEV_CS0;
211 win = CPU_WIN_DEV_CS0;
212 break;
213 case ORION_DEV1:
214 target = TARGET_DEV_BUS;
215 attr = ATTR_DEV_CS1;
216 win = CPU_WIN_DEV_CS1;
217 break;
218 case ORION_DEV2:
219 target = TARGET_DEV_BUS;
220 attr = ATTR_DEV_CS2;
221 win = CPU_WIN_DEV_CS2;
222 break;
223 case ORION_DDR:
224 case ORION_REGS:
225 /*
226 * Must be mapped by bootloader.
227 */
228 default:
229 target = attr = win = -1;
230 BUG();
231 }
232
233 base &= 0xffff0000;
234 ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
235 (target << 4) | WIN_EN);
236
237 orion_write(CPU_WIN_BASE(win), base);
238 orion_write(CPU_WIN_CTRL(win), ctrl);
239
240 if (orion_cpu_win_can_remap(win)) {
241 if (remap >= 0) {
242 orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
243 orion_write(CPU_WIN_REMAP_HI(win), 0);
244 } else {
245 orion_write(CPU_WIN_REMAP_LO(win), base);
246 orion_write(CPU_WIN_REMAP_HI(win), 0);
247 }
248 }
249}
250
251void __init orion_setup_cpu_wins(void)
252{
253 int i;
254
255 /*
256 * First, disable and clear windows
257 */
258 for (i = 0; i < CPU_MAX_WIN; i++) {
259 orion_write(CPU_WIN_BASE(i), 0);
260 orion_write(CPU_WIN_CTRL(i), 0);
261 if (orion_cpu_win_can_remap(i)) {
262 orion_write(CPU_WIN_REMAP_LO(i), 0);
263 orion_write(CPU_WIN_REMAP_HI(i), 0);
264 }
265 }
266
267 /*
268 * Setup windows for PCI+PCIE IO+MAM space
269 */
270 orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE,
271 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP);
272 orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE,
273 ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP);
274 orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE,
275 ORION_PCIE_MEM_SIZE, -1);
276 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE,
277 ORION_PCI_MEM_SIZE, -1);
278}
279
280/*
281 * Setup PCIE BARs and Address Decode Wins:
282 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
283 * WIN[0-3] -> DRAM bank[0-3]
284 */
285void __init orion_setup_pcie_wins(void)
286{
287 u32 base, size, i;
288
289 /*
290 * First, disable and clear BARs and windows
291 */
292 for (i = 1; i < PCIE_MAX_BARS; i++) {
293 orion_write(PCIE_BAR_CTRL(i), 0);
294 orion_write(PCIE_BAR_LO(i), 0);
295 orion_write(PCIE_BAR_HI(i), 0);
296 }
297
298 for (i = 0; i < PCIE_MAX_WINS; i++) {
299 orion_write(PCIE_WIN_CTRL(i), 0);
300 orion_write(PCIE_WIN_BASE(i), 0);
301 orion_write(PCIE_WIN_REMAP(i), 0);
302 }
303
304 /*
305 * Setup windows for DDR banks. Count total DDR size on the fly.
306 */
307 base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
308 size = 0;
309 for (i = 0; i < DDR_MAX_CS; i++) {
310 u32 bank_base, bank_size;
311 bank_size = orion_read(DDR_SIZE_CS(i));
312 bank_base = orion_read(DDR_BASE_CS(i));
313 if (bank_size & DDR_BANK_EN) {
314 bank_size = DDR_REG_TO_SIZE(bank_size);
315 bank_base = DDR_REG_TO_BASE(bank_base);
316 orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
317 orion_write(PCIE_WIN_REMAP(i), 0);
318 orion_write(PCIE_WIN_CTRL(i),
319 ((bank_size-1) & 0xffff0000) |
320 (ATTR_DDR_CS(i) << 8) |
321 (TARGET_DDR << 4) |
322 (PCIE_DRAM_BAR << 1) | WIN_EN);
323 size += bank_size;
324 }
325 }
326
327 /*
328 * Setup BAR[1] to all DRAM banks
329 */
330 orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
331 orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
332 orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
333 ((size - 1) & 0xffff0000) | WIN_EN);
334}
335
336void __init orion_setup_pci_wins(void)
337{
338 u32 base, size, i;
339
340 /*
341 * First, disable windows
342 */
343 orion_write(PCI_BAR_ENABLE, 0xffffffff);
344
345 /*
346 * Setup windows for DDR banks.
347 */
348 for (i = 0; i < DDR_MAX_CS; i++) {
349 base = orion_read(DDR_BASE_CS(i));
350 size = orion_read(DDR_SIZE_CS(i));
351 if (size & DDR_BANK_EN) {
352 u32 bus, dev, func, reg, val;
353 size = DDR_REG_TO_SIZE(size);
354 base = DDR_REG_TO_BASE(base);
355 bus = orion_pci_local_bus_nr();
356 dev = orion_pci_local_dev_nr();
357 func = PCI_CONF_FUNC_BAR_CS(i);
358 reg = PCI_CONF_REG_BAR_LO_CS(i);
359 orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
360 orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
361 (base & 0xfffff000) | (val & 0xfff));
362 reg = PCI_CONF_REG_BAR_HI_CS(i);
363 orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
364 orion_write(PCI_BAR_SIZE_DDR_CS(i),
365 (size - 1) & 0xfffff000);
366 orion_write(PCI_BAR_REMAP_DDR_CS(i),
367 base & 0xfffff000);
368 orion_clrbits(PCI_BAR_ENABLE, (1 << i));
369 }
370 }
371
372 /*
373 * Disable automatic update of address remaping when writing to BARs
374 */
375 orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
376}
377
378void __init orion_setup_usb_wins(void)
379{
380 int i;
381 u32 usb_if, dev, rev;
382 u32 max_usb_if = 1;
383
384 orion_pcie_id(&dev, &rev);
385 if (dev == MV88F5182_DEV_ID)
386 max_usb_if = 2;
387
388 for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
389 /*
390 * First, disable and clear windows
391 */
392 for (i = 0; i < USB_MAX_WIN; i++) {
393 orion_write(USB_WIN_BASE(usb_if, i), 0);
394 orion_write(USB_WIN_CTRL(usb_if, i), 0);
395 }
396
397 /*
398 * Setup windows for DDR banks.
399 */
400 for (i = 0; i < DDR_MAX_CS; i++) {
401 u32 base, size;
402 size = orion_read(DDR_SIZE_CS(i));
403 base = orion_read(DDR_BASE_CS(i));
404 if (size & DDR_BANK_EN) {
405 base = DDR_REG_TO_BASE(base);
406 size = DDR_REG_TO_SIZE(size);
407 orion_write(USB_WIN_CTRL(usb_if, i),
408 ((size-1) & 0xffff0000) |
409 (ATTR_DDR_CS(i) << 8) |
410 (TARGET_DDR << 4) | WIN_EN);
411 orion_write(USB_WIN_BASE(usb_if, i),
412 base & 0xffff0000);
413 }
414 }
415 }
416}
417
418void __init orion_setup_eth_wins(void)
419{
420 int i;
421
422 /*
423 * First, disable and clear windows
424 */
425 for (i = 0; i < ETH_MAX_WIN; i++) {
426 orion_write(ETH_WIN_BASE(i), 0);
427 orion_write(ETH_WIN_SIZE(i), 0);
428 orion_setbits(ETH_WIN_EN, 1 << i);
429 orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
430 if (i < ETH_MAX_REMAP_WIN)
431 orion_write(ETH_WIN_REMAP(i), 0);
432 }
433
434 /*
435 * Setup windows for DDR banks.
436 */
437 for (i = 0; i < DDR_MAX_CS; i++) {
438 u32 base, size;
439 size = orion_read(DDR_SIZE_CS(i));
440 base = orion_read(DDR_BASE_CS(i));
441 if (size & DDR_BANK_EN) {
442 base = DDR_REG_TO_BASE(base);
443 size = DDR_REG_TO_SIZE(size);
444 orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
445 orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
446 (ATTR_DDR_CS(i) << 8) |
447 TARGET_DDR);
448 orion_clrbits(ETH_WIN_EN, 1 << i);
449 orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
450 }
451 }
452}
453
454void __init orion_setup_sata_wins(void)
455{
456 int i;
457
458 /*
459 * First, disable and clear windows
460 */
461 for (i = 0; i < SATA_MAX_WIN; i++) {
462 orion_write(SATA_WIN_BASE(i), 0);
463 orion_write(SATA_WIN_CTRL(i), 0);
464 }
465
466 /*
467 * Setup windows for DDR banks.
468 */
469 for (i = 0; i < DDR_MAX_CS; i++) {
470 u32 base, size;
471 size = orion_read(DDR_SIZE_CS(i));
472 base = orion_read(DDR_BASE_CS(i));
473 if (size & DDR_BANK_EN) {
474 base = DDR_REG_TO_BASE(base);
475 size = DDR_REG_TO_SIZE(size);
476 orion_write(SATA_WIN_CTRL(i),
477 ((size-1) & 0xffff0000) |
478 (ATTR_DDR_CS(i) << 8) |
479 (TARGET_DDR << 4) | WIN_EN);
480 orion_write(SATA_WIN_BASE(i),
481 base & 0xffff0000);
482 }
483 }
484}
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c
new file mode 100644
index 000000000000..5e20b6b32508
--- /dev/null
+++ b/arch/arm/mach-orion/common.c
@@ -0,0 +1,315 @@
1/*
2 * arch/arm/mach-orion/common.c
3 *
4 * Core functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/serial_8250.h>
17#include <linux/mv643xx_eth.h>
18#include <linux/mv643xx_i2c.h>
19#include <asm/page.h>
20#include <asm/timex.h>
21#include <asm/mach/map.h>
22#include <asm/arch/orion.h>
23#include "common.h"
24
25/*****************************************************************************
26 * I/O Address Mapping
27 ****************************************************************************/
28static struct map_desc orion_io_desc[] __initdata = {
29 {
30 .virtual = ORION_REGS_BASE,
31 .pfn = __phys_to_pfn(ORION_REGS_BASE),
32 .length = ORION_REGS_SIZE,
33 .type = MT_DEVICE
34 },
35 {
36 .virtual = ORION_PCIE_IO_BASE,
37 .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
38 .length = ORION_PCIE_IO_SIZE,
39 .type = MT_DEVICE
40 },
41 {
42 .virtual = ORION_PCI_IO_BASE,
43 .pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
44 .length = ORION_PCI_IO_SIZE,
45 .type = MT_DEVICE
46 },
47 {
48 .virtual = ORION_PCIE_WA_BASE,
49 .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
50 .length = ORION_PCIE_WA_SIZE,
51 .type = MT_DEVICE
52 },
53};
54
55void __init orion_map_io(void)
56{
57 iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
58}
59
60/*****************************************************************************
61 * UART
62 ****************************************************************************/
63
64static struct resource orion_uart_resources[] = {
65 {
66 .start = UART0_BASE,
67 .end = UART0_BASE + 0xff,
68 .flags = IORESOURCE_MEM,
69 },
70 {
71 .start = IRQ_ORION_UART0,
72 .end = IRQ_ORION_UART0,
73 .flags = IORESOURCE_IRQ,
74 },
75 {
76 .start = UART1_BASE,
77 .end = UART1_BASE + 0xff,
78 .flags = IORESOURCE_MEM,
79 },
80 {
81 .start = IRQ_ORION_UART1,
82 .end = IRQ_ORION_UART1,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87static struct plat_serial8250_port orion_uart_data[] = {
88 {
89 .mapbase = UART0_BASE,
90 .membase = (char *)UART0_BASE,
91 .irq = IRQ_ORION_UART0,
92 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
93 .iotype = UPIO_MEM,
94 .regshift = 2,
95 .uartclk = ORION_TCLK,
96 },
97 {
98 .mapbase = UART1_BASE,
99 .membase = (char *)UART1_BASE,
100 .irq = IRQ_ORION_UART1,
101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
102 .iotype = UPIO_MEM,
103 .regshift = 2,
104 .uartclk = ORION_TCLK,
105 },
106 { },
107};
108
109static struct platform_device orion_uart = {
110 .name = "serial8250",
111 .id = PLAT8250_DEV_PLATFORM,
112 .dev = {
113 .platform_data = orion_uart_data,
114 },
115 .resource = orion_uart_resources,
116 .num_resources = ARRAY_SIZE(orion_uart_resources),
117};
118
119/*******************************************************************************
120 * USB Controller - 2 interfaces
121 ******************************************************************************/
122
123static struct resource orion_ehci0_resources[] = {
124 {
125 .start = ORION_USB0_REG_BASE,
126 .end = ORION_USB0_REG_BASE + SZ_4K,
127 .flags = IORESOURCE_MEM,
128 },
129 {
130 .start = IRQ_ORION_USB0_CTRL,
131 .end = IRQ_ORION_USB0_CTRL,
132 .flags = IORESOURCE_IRQ,
133 },
134};
135
136static struct resource orion_ehci1_resources[] = {
137 {
138 .start = ORION_USB1_REG_BASE,
139 .end = ORION_USB1_REG_BASE + SZ_4K,
140 .flags = IORESOURCE_MEM,
141 },
142 {
143 .start = IRQ_ORION_USB1_CTRL,
144 .end = IRQ_ORION_USB1_CTRL,
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static u64 ehci_dmamask = 0xffffffffUL;
150
151static struct platform_device orion_ehci0 = {
152 .name = "orion-ehci",
153 .id = 0,
154 .dev = {
155 .dma_mask = &ehci_dmamask,
156 .coherent_dma_mask = 0xffffffff,
157 },
158 .resource = orion_ehci0_resources,
159 .num_resources = ARRAY_SIZE(orion_ehci0_resources),
160};
161
162static struct platform_device orion_ehci1 = {
163 .name = "orion-ehci",
164 .id = 1,
165 .dev = {
166 .dma_mask = &ehci_dmamask,
167 .coherent_dma_mask = 0xffffffff,
168 },
169 .resource = orion_ehci1_resources,
170 .num_resources = ARRAY_SIZE(orion_ehci1_resources),
171};
172
173/*****************************************************************************
174 * Gigabit Ethernet port
175 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
176 ****************************************************************************/
177
178static struct resource orion_eth_shared_resources[] = {
179 {
180 .start = ORION_ETH_REG_BASE,
181 .end = ORION_ETH_REG_BASE + 0xffff,
182 .flags = IORESOURCE_MEM,
183 },
184};
185
186static struct platform_device orion_eth_shared = {
187 .name = MV643XX_ETH_SHARED_NAME,
188 .id = 0,
189 .num_resources = 1,
190 .resource = orion_eth_shared_resources,
191};
192
193static struct resource orion_eth_resources[] = {
194 {
195 .name = "eth irq",
196 .start = IRQ_ORION_ETH_SUM,
197 .end = IRQ_ORION_ETH_SUM,
198 .flags = IORESOURCE_IRQ,
199 }
200};
201
202static struct platform_device orion_eth = {
203 .name = MV643XX_ETH_NAME,
204 .id = 0,
205 .num_resources = 1,
206 .resource = orion_eth_resources,
207};
208
209void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
210{
211 orion_eth.dev.platform_data = eth_data;
212 platform_device_register(&orion_eth_shared);
213 platform_device_register(&orion_eth);
214}
215
216/*****************************************************************************
217 * I2C controller
218 * (The Orion and Discovery (MV643xx) families share the same I2C controller)
219 ****************************************************************************/
220
221static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
222 .freq_m = 8, /* assumes 166 MHz TCLK */
223 .freq_n = 3,
224 .timeout = 1000, /* Default timeout of 1 second */
225};
226
227static struct resource orion_i2c_resources[] = {
228 {
229 .name = "i2c base",
230 .start = I2C_BASE,
231 .end = I2C_BASE + 0x20 -1,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .name = "i2c irq",
236 .start = IRQ_ORION_I2C,
237 .end = IRQ_ORION_I2C,
238 .flags = IORESOURCE_IRQ,
239 },
240};
241
242static struct platform_device orion_i2c = {
243 .name = MV64XXX_I2C_CTLR_NAME,
244 .id = 0,
245 .num_resources = ARRAY_SIZE(orion_i2c_resources),
246 .resource = orion_i2c_resources,
247 .dev = {
248 .platform_data = &orion_i2c_pdata,
249 },
250};
251
252/*****************************************************************************
253 * General
254 ****************************************************************************/
255
256/*
257 * Identify device ID and rev from PCIE configuration header space '0'.
258 */
259static void orion_id(u32 *dev, u32 *rev, char **dev_name)
260{
261 orion_pcie_id(dev, rev);
262
263 if (*dev == MV88F5281_DEV_ID) {
264 if (*rev == MV88F5281_REV_D2) {
265 *dev_name = "MV88F5281-D2";
266 } else if (*rev == MV88F5281_REV_D1) {
267 *dev_name = "MV88F5281-D1";
268 } else {
269 *dev_name = "MV88F5281-Rev-Unsupported";
270 }
271 } else if (*dev == MV88F5182_DEV_ID) {
272 if (*rev == MV88F5182_REV_A2) {
273 *dev_name = "MV88F5182-A2";
274 } else {
275 *dev_name = "MV88F5182-Rev-Unsupported";
276 }
277 } else if (*dev == MV88F5181_DEV_ID) {
278 if (*rev == MV88F5181_REV_B1) {
279 *dev_name = "MV88F5181-Rev-B1";
280 } else {
281 *dev_name = "MV88F5181-Rev-Unsupported";
282 }
283 } else {
284 *dev_name = "Device-Unknown";
285 }
286}
287
288void __init orion_init(void)
289{
290 char *dev_name;
291 u32 dev, rev;
292
293 orion_id(&dev, &rev, &dev_name);
294 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK);
295
296 /*
297 * Setup Orion address map
298 */
299 orion_setup_cpu_wins();
300 orion_setup_usb_wins();
301 orion_setup_eth_wins();
302 orion_setup_pci_wins();
303 orion_setup_pcie_wins();
304 if (dev == MV88F5182_DEV_ID)
305 orion_setup_sata_wins();
306
307 /*
308 * REgister devices
309 */
310 platform_device_register(&orion_uart);
311 platform_device_register(&orion_ehci0);
312 if (dev == MV88F5182_DEV_ID)
313 platform_device_register(&orion_ehci1);
314 platform_device_register(&orion_i2c);
315}
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h
new file mode 100644
index 000000000000..06c10c06f03e
--- /dev/null
+++ b/arch/arm/mach-orion/common.h
@@ -0,0 +1,78 @@
1#ifndef __ARCH_ORION_COMMON_H__
2#define __ARCH_ORION_COMMON_H__
3
4/*
5 * Basic Orion init functions used early by machine-setup.
6 */
7
8void __init orion_map_io(void);
9void __init orion_init_irq(void);
10void __init orion_init(void);
11
12/*
13 * Enumerations and functions for Orion windows mapping. Used by Orion core
14 * functions to map its interfaces and by the machine-setup to map its on-
15 * board devices. Details in /mach-orion/addr-map.c
16 */
17
18enum orion_target {
19 ORION_DEV_BOOT = 0,
20 ORION_DEV0,
21 ORION_DEV1,
22 ORION_DEV2,
23 ORION_PCIE_MEM,
24 ORION_PCIE_IO,
25 ORION_PCI_MEM,
26 ORION_PCI_IO,
27 ORION_DDR,
28 ORION_REGS,
29 ORION_MAX_TARGETS
30};
31
32void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
33void orion_setup_cpu_wins(void);
34void orion_setup_eth_wins(void);
35void orion_setup_usb_wins(void);
36void orion_setup_pci_wins(void);
37void orion_setup_pcie_wins(void);
38void orion_setup_sata_wins(void);
39
40/*
41 * Shared code used internally by other Orion core functions.
42 * (/mach-orion/pci.c)
43 */
44
45struct pci_sys_data;
46struct pci_bus;
47
48void orion_pcie_id(u32 *dev, u32 *rev);
49u32 orion_pcie_local_bus_nr(void);
50u32 orion_pci_local_bus_nr(void);
51u32 orion_pci_local_dev_nr(void);
52int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
53struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
54int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
55int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
56
57/*
58 * Valid GPIO pins according to MPP setup, used by machine-setup.
59 * (/mach-orion/gpio.c).
60 */
61
62void __init orion_gpio_set_valid_pins(u32 pins);
63void gpio_display(void); /* debug */
64
65/*
66 * Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
67 */
68extern struct sys_timer orion_timer;
69
70/*
71 * Pull in Orion Ethernet platform_data, used by machine-setup
72 */
73
74struct mv643xx_eth_platform_data;
75
76void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
77
78#endif /* __ARCH_ORION_COMMON_H__ */
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c
new file mode 100644
index 000000000000..cb2a95ce5b57
--- /dev/null
+++ b/arch/arm/mach-orion/db88f5281-setup.c
@@ -0,0 +1,364 @@
1/*
2 * arch/arm/mach-orion/db88f5281-setup.c
3 *
4 * Marvell Orion-2 Development Board Setup
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mtd/nand.h>
20#include <linux/timer.h>
21#include <linux/mv643xx_eth.h>
22#include <linux/i2c.h>
23#include <asm/mach-types.h>
24#include <asm/gpio.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/pci.h>
27#include <asm/arch/orion.h>
28#include <asm/arch/platform.h>
29#include "common.h"
30
31/*****************************************************************************
32 * DB-88F5281 on board devices
33 ****************************************************************************/
34
35/*
36 * 512K NOR flash Device bus boot chip select
37 */
38
39#define DB88F5281_NOR_BOOT_BASE 0xf4000000
40#define DB88F5281_NOR_BOOT_SIZE SZ_512K
41
42/*
43 * 7-Segment on Device bus chip select 0
44 */
45
46#define DB88F5281_7SEG_BASE 0xfa000000
47#define DB88F5281_7SEG_SIZE SZ_1K
48
49/*
50 * 32M NOR flash on Device bus chip select 1
51 */
52
53#define DB88F5281_NOR_BASE 0xfc000000
54#define DB88F5281_NOR_SIZE SZ_32M
55
56/*
57 * 32M NAND flash on Device bus chip select 2
58 */
59
60#define DB88F5281_NAND_BASE 0xfa800000
61#define DB88F5281_NAND_SIZE SZ_1K
62
63/*
64 * PCI
65 */
66
67#define DB88F5281_PCI_SLOT0_OFFS 7
68#define DB88F5281_PCI_SLOT0_IRQ_PIN 12
69#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
70
71/*****************************************************************************
72 * 512M NOR Flash on Device bus Boot CS
73 ****************************************************************************/
74
75static struct physmap_flash_data db88f5281_boot_flash_data = {
76 .width = 1, /* 8 bit bus width */
77};
78
79static struct resource db88f5281_boot_flash_resource = {
80 .flags = IORESOURCE_MEM,
81 .start = DB88F5281_NOR_BOOT_BASE,
82 .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
83};
84
85static struct platform_device db88f5281_boot_flash = {
86 .name = "physmap-flash",
87 .id = 0,
88 .dev = {
89 .platform_data = &db88f5281_boot_flash_data,
90 },
91 .num_resources = 1,
92 .resource = &db88f5281_boot_flash_resource,
93};
94
95/*****************************************************************************
96 * 32M NOR Flash on Device bus CS1
97 ****************************************************************************/
98
99static struct physmap_flash_data db88f5281_nor_flash_data = {
100 .width = 4, /* 32 bit bus width */
101};
102
103static struct resource db88f5281_nor_flash_resource = {
104 .flags = IORESOURCE_MEM,
105 .start = DB88F5281_NOR_BASE,
106 .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
107};
108
109static struct platform_device db88f5281_nor_flash = {
110 .name = "physmap-flash",
111 .id = 1,
112 .dev = {
113 .platform_data = &db88f5281_nor_flash_data,
114 },
115 .num_resources = 1,
116 .resource = &db88f5281_nor_flash_resource,
117};
118
119/*****************************************************************************
120 * 32M NAND Flash on Device bus CS2
121 ****************************************************************************/
122
123static struct mtd_partition db88f5281_nand_parts[] = {
124 {
125 .name = "kernel",
126 .offset = 0,
127 .size = SZ_2M,
128 },
129 {
130 .name = "root",
131 .offset = SZ_2M,
132 .size = (SZ_16M - SZ_2M),
133 },
134 {
135 .name = "user",
136 .offset = SZ_16M,
137 .size = SZ_8M,
138 },
139 {
140 .name = "recovery",
141 .offset = (SZ_16M + SZ_8M),
142 .size = SZ_8M,
143 },
144};
145
146static struct resource db88f5281_nand_resource = {
147 .flags = IORESOURCE_MEM,
148 .start = DB88F5281_NAND_BASE,
149 .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
150};
151
152static struct orion_nand_data db88f5281_nand_data = {
153 .parts = db88f5281_nand_parts,
154 .nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
155 .cle = 0,
156 .ale = 1,
157 .width = 8,
158};
159
160static struct platform_device db88f5281_nand_flash = {
161 .name = "orion_nand",
162 .id = -1,
163 .dev = {
164 .platform_data = &db88f5281_nand_data,
165 },
166 .resource = &db88f5281_nand_resource,
167 .num_resources = 1,
168};
169
170/*****************************************************************************
171 * 7-Segment on Device bus CS0
172 * Dummy counter every 2 sec
173 ****************************************************************************/
174
175static void __iomem *db88f5281_7seg;
176static struct timer_list db88f5281_timer;
177
178static void db88f5281_7seg_event(unsigned long data)
179{
180 static int count = 0;
181 writel(0, db88f5281_7seg + (count << 4));
182 count = (count + 1) & 7;
183 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
184}
185
186static int __init db88f5281_7seg_init(void)
187{
188 if (machine_is_db88f5281()) {
189 db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
190 DB88F5281_7SEG_SIZE);
191 if (!db88f5281_7seg) {
192 printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
193 return -EIO;
194 }
195 setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
196 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
197 }
198
199 return 0;
200}
201
202__initcall(db88f5281_7seg_init);
203
204/*****************************************************************************
205 * PCI
206 ****************************************************************************/
207
208void __init db88f5281_pci_preinit(void)
209{
210 int pin;
211
212 /*
213 * Configure PCI GPIO IRQ pins
214 */
215 pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
216 if (gpio_request(pin, "PCI Int1") == 0) {
217 if (gpio_direction_input(pin) == 0) {
218 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
219 } else {
220 printk(KERN_ERR "db88f5281_pci_preinit faield to "
221 "set_irq_type pin %d\n", pin);
222 gpio_free(pin);
223 }
224 } else {
225 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
226 }
227
228 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
229 if (gpio_request(pin, "PCI Int2") == 0) {
230 if (gpio_direction_input(pin) == 0) {
231 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
232 } else {
233 printk(KERN_ERR "db88f5281_pci_preinit faield "
234 "to set_irq_type pin %d\n", pin);
235 gpio_free(pin);
236 }
237 } else {
238 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
239 }
240}
241
242static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
243{
244 /*
245 * PCIE IRQ is connected internally (not GPIO)
246 */
247 if (dev->bus->number == orion_pcie_local_bus_nr())
248 return IRQ_ORION_PCIE0_INT;
249
250 /*
251 * PCI IRQs are connected via GPIOs
252 */
253 switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
254 case 0:
255 return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
256 case 1:
257 case 2:
258 return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
259 default:
260 return -1;
261 }
262}
263
264static struct hw_pci db88f5281_pci __initdata = {
265 .nr_controllers = 2,
266 .preinit = db88f5281_pci_preinit,
267 .swizzle = pci_std_swizzle,
268 .setup = orion_pci_sys_setup,
269 .scan = orion_pci_sys_scan_bus,
270 .map_irq = db88f5281_pci_map_irq,
271};
272
273static int __init db88f5281_pci_init(void)
274{
275 if (machine_is_db88f5281())
276 pci_common_init(&db88f5281_pci);
277
278 return 0;
279}
280
281subsys_initcall(db88f5281_pci_init);
282
283/*****************************************************************************
284 * Ethernet
285 ****************************************************************************/
286static struct mv643xx_eth_platform_data db88f5281_eth_data = {
287 .phy_addr = 8,
288 .force_phy_addr = 1,
289};
290
291/*****************************************************************************
292 * RTC DS1339 on I2C bus
293 ****************************************************************************/
294static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
295 .driver_name = "rtc-ds1307",
296 .type = "ds1339",
297 .addr = 0x68,
298};
299
300/*****************************************************************************
301 * General Setup
302 ****************************************************************************/
303
304static struct platform_device *db88f5281_devs[] __initdata = {
305 &db88f5281_boot_flash,
306 &db88f5281_nor_flash,
307 &db88f5281_nand_flash,
308};
309
310static void __init db88f5281_init(void)
311{
312 /*
313 * Basic Orion setup. Need to be called early.
314 */
315 orion_init();
316
317 /*
318 * Setup the CPU address decode windows for our on-board devices
319 */
320 orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
321 DB88F5281_NOR_BOOT_SIZE, -1);
322 orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
323 DB88F5281_7SEG_SIZE, -1);
324 orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
325 DB88F5281_NOR_SIZE, -1);
326 orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
327 DB88F5281_NAND_SIZE, -1);
328
329 /*
330 * Setup Multiplexing Pins:
331 * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input)
332 * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2]
333 * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3]
334 * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1)
335 * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3)
336 * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator)
337 * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2)
338 * MPP14: NAND_REn[2] MPP15: NAND_WEn[2]
339 * MPP16: UART1_RX MPP17: UART1_TX
340 * MPP18: UART1_CTS MPP19: UART1_RTS
341 * MPP-DEV: DEV_D[16:31]
342 */
343 orion_write(MPP_0_7_CTRL, 0x00222203);
344 orion_write(MPP_8_15_CTRL, 0x44000000);
345 orion_write(MPP_16_19_CTRL, 0);
346 orion_write(MPP_DEV_CTRL, 0);
347
348 orion_gpio_set_valid_pins(0x00003fc3);
349
350 platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
351 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
352 orion_eth_init(&db88f5281_eth_data);
353}
354
355MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
356 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
357 .phys_io = ORION_REGS_BASE,
358 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc,
359 .boot_params = 0x00000100,
360 .init_machine = db88f5281_init,
361 .map_io = orion_map_io,
362 .init_irq = orion_init_irq,
363 .timer = &orion_timer,
364MACHINE_END
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c
new file mode 100644
index 000000000000..c8a806f249c6
--- /dev/null
+++ b/arch/arm/mach-orion/dns323-setup.c
@@ -0,0 +1,322 @@
1/*
2 * arch/arm/mach-orion/dns323-setup.c
3 *
4 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/leds.h>
21#include <linux/gpio_keys.h>
22#include <linux/input.h>
23#include <linux/i2c.h>
24#include <asm/mach-types.h>
25#include <asm/gpio.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/pci.h>
28#include <asm/arch/orion.h>
29#include <asm/arch/platform.h>
30#include "common.h"
31
32#define DNS323_GPIO_LED_RIGHT_AMBER 1
33#define DNS323_GPIO_LED_LEFT_AMBER 2
34#define DNS323_GPIO_LED_POWER 5
35#define DNS323_GPIO_OVERTEMP 6
36#define DNS323_GPIO_RTC 7
37#define DNS323_GPIO_POWER_OFF 8
38#define DNS323_GPIO_KEY_POWER 9
39#define DNS323_GPIO_KEY_RESET 10
40
41/****************************************************************************
42 * PCI setup
43 */
44
45static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
46{
47 /* PCI-E */
48 if (dev->bus->number == orion_pcie_local_bus_nr())
49 return IRQ_ORION_PCIE0_INT;
50
51 pr_err("%s: requested mapping for unknown bus\n", __func__);
52
53 return -1;
54}
55
56static struct hw_pci dns323_pci __initdata = {
57 .nr_controllers = 1,
58 .swizzle = pci_std_swizzle,
59 .setup = orion_pci_sys_setup,
60 .scan = orion_pci_sys_scan_bus,
61 .map_irq = dns323_pci_map_irq,
62};
63
64static int __init dns323_pci_init(void)
65{
66 if (machine_is_dns323())
67 pci_common_init(&dns323_pci);
68
69 return 0;
70}
71
72subsys_initcall(dns323_pci_init);
73
74/****************************************************************************
75 * Ethernet
76 */
77
78static struct mv643xx_eth_platform_data dns323_eth_data = {
79 .phy_addr = 8,
80 .force_phy_addr = 1,
81};
82
83/****************************************************************************
84 * 8MiB NOR flash (Spansion S29GL064M90TFIR4)
85 *
86 * Layout as used by D-Link:
87 * 0x00000000-0x00010000 : "MTD1"
88 * 0x00010000-0x00020000 : "MTD2"
89 * 0x00020000-0x001a0000 : "Linux Kernel"
90 * 0x001a0000-0x007d0000 : "File System"
91 * 0x007d0000-0x00800000 : "u-boot"
92 */
93
94#define DNS323_NOR_BOOT_BASE 0xf4000000
95#define DNS323_NOR_BOOT_SIZE SZ_8M
96
97static struct mtd_partition dns323_partitions[] = {
98 {
99 .name = "MTD1",
100 .size = 0x00010000,
101 .offset = 0,
102 }, {
103 .name = "MTD2",
104 .size = 0x00010000,
105 .offset = 0x00010000,
106 }, {
107 .name = "Linux Kernel",
108 .size = 0x00180000,
109 .offset = 0x00020000,
110 }, {
111 .name = "File System",
112 .size = 0x00630000,
113 .offset = 0x001A0000,
114 }, {
115 .name = "u-boot",
116 .size = 0x00030000,
117 .offset = 0x007d0000,
118 }
119};
120
121static struct physmap_flash_data dns323_nor_flash_data = {
122 .width = 1,
123 .parts = dns323_partitions,
124 .nr_parts = ARRAY_SIZE(dns323_partitions)
125};
126
127static struct resource dns323_nor_flash_resource = {
128 .flags = IORESOURCE_MEM,
129 .start = DNS323_NOR_BOOT_BASE,
130 .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1,
131};
132
133static struct platform_device dns323_nor_flash = {
134 .name = "physmap-flash",
135 .id = 0,
136 .dev = { .platform_data = &dns323_nor_flash_data, },
137 .resource = &dns323_nor_flash_resource,
138 .num_resources = 1,
139};
140
141/****************************************************************************
142 * GPIO LEDs (simple - doesn't use hardware blinking support)
143 */
144
145static struct gpio_led dns323_leds[] = {
146 {
147 .name = "power:blue",
148 .gpio = DNS323_GPIO_LED_POWER,
149 .active_low = 1,
150 }, {
151 .name = "right:amber",
152 .gpio = DNS323_GPIO_LED_RIGHT_AMBER,
153 .active_low = 1,
154 }, {
155 .name = "left:amber",
156 .gpio = DNS323_GPIO_LED_LEFT_AMBER,
157 .active_low = 1,
158 },
159};
160
161static struct gpio_led_platform_data dns323_led_data = {
162 .num_leds = ARRAY_SIZE(dns323_leds),
163 .leds = dns323_leds,
164};
165
166static struct platform_device dns323_gpio_leds = {
167 .name = "leds-gpio",
168 .id = -1,
169 .dev = { .platform_data = &dns323_led_data, },
170};
171
172/****************************************************************************
173 * GPIO Attached Keys
174 */
175
176static struct gpio_keys_button dns323_buttons[] = {
177 {
178 .code = KEY_RESTART,
179 .gpio = DNS323_GPIO_KEY_RESET,
180 .desc = "Reset Button",
181 .active_low = 1,
182 },
183 {
184 .code = KEY_POWER,
185 .gpio = DNS323_GPIO_KEY_POWER,
186 .desc = "Power Button",
187 .active_low = 1,
188 }
189};
190
191static struct gpio_keys_platform_data dns323_button_data = {
192 .buttons = dns323_buttons,
193 .nbuttons = ARRAY_SIZE(dns323_buttons),
194};
195
196static struct platform_device dns323_button_device = {
197 .name = "gpio-keys",
198 .id = -1,
199 .num_resources = 0,
200 .dev = { .platform_data = &dns323_button_data, },
201};
202
203/****************************************************************************
204 * General Setup
205 */
206
207static struct platform_device *dns323_plat_devices[] __initdata = {
208 &dns323_nor_flash,
209 &dns323_gpio_leds,
210 &dns323_button_device,
211};
212
213/*
214 * On the DNS-323 the following devices are attached via I2C:
215 *
216 * i2c addr | chip | description
217 * 0x3e | GMT G760Af | fan speed PWM controller
218 * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
219 * 0x68 | ST M41T80 | RTC w/ alarm
220 */
221static struct i2c_board_info __initdata dns323_i2c_devices[] = {
222 {
223 I2C_BOARD_INFO("g760a", 0x3e),
224 .type = "g760a",
225 },
226#if 0
227 /* this entry requires the new-style driver model lm75 driver,
228 * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */
229 {
230 I2C_BOARD_INFO("lm75", 0x48),
231 .type = "g751",
232 },
233#endif
234 {
235 I2C_BOARD_INFO("rtc-m41t80", 0x68),
236 .type = "m41t80",
237 }
238};
239
240/* DNS-323 specific power off method */
241static void dns323_power_off(void)
242{
243 pr_info("%s: triggering power-off...\n", __func__);
244 gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
245}
246
247static void __init dns323_init(void)
248{
249 /* Setup basic Orion functions. Need to be called early. */
250 orion_init();
251
252 /* setup flash mapping
253 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
254 */
255 orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE,
256 DNS323_NOR_BOOT_SIZE, -1);
257
258 /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
259 *
260 * Open a special address decode windows for the PCIE WA.
261 */
262 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
263 orion_write(ORION_REGS_BASE | 0x20070,
264 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
265
266 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
267 orion_write(MPP_0_7_CTRL, 0);
268 orion_write(MPP_8_15_CTRL, 0);
269 orion_write(MPP_16_19_CTRL, 0);
270 orion_write(MPP_DEV_CTRL, 0);
271
272 /* Define used GPIO pins
273
274 GPIO Map:
275
276 | 0 | | PEX_RST_OUT (not controlled by GPIO)
277 | 1 | Out | right amber LED (= sata ch0 LED) (low-active)
278 | 2 | Out | left amber LED (= sata ch1 LED) (low-active)
279 | 3 | Out | //unknown//
280 | 4 | Out | power button LED (low-active, together with pin #5)
281 | 5 | Out | power button LED (low-active, together with pin #4)
282 | 6 | In | GMT G751-2f overtemp. shutdown signal (low-active)
283 | 7 | In | M41T80 nIRQ/OUT/SQW signal
284 | 8 | Out | triggers power off (high-active)
285 | 9 | In | power button switch (low-active)
286 | 10 | In | reset button switch (low-active)
287 | 11 | Out | //unknown//
288 | 12 | Out | //unknown//
289 | 13 | Out | //unknown//
290 | 14 | Out | //unknown//
291 | 15 | Out | //unknown//
292 */
293 orion_gpio_set_valid_pins(0x07f6);
294
295 /* register dns323 specific power-off method */
296 if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
297 || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0))
298 pr_err("DNS323: failed to setup power-off GPIO\n");
299
300 pm_power_off = dns323_power_off;
301
302 /* register flash and other platform devices */
303 platform_add_devices(dns323_plat_devices,
304 ARRAY_SIZE(dns323_plat_devices));
305
306 i2c_register_board_info(0, dns323_i2c_devices,
307 ARRAY_SIZE(dns323_i2c_devices));
308
309 orion_eth_init(&dns323_eth_data);
310}
311
312/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
313MACHINE_START(DNS323, "D-Link DNS-323")
314 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
315 .phys_io = ORION_REGS_BASE,
316 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
317 .boot_params = 0x00000100,
318 .init_machine = dns323_init,
319 .map_io = orion_map_io,
320 .init_irq = orion_init_irq,
321 .timer = &orion_timer,
322MACHINE_END
diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c
new file mode 100644
index 000000000000..d5f00c86d616
--- /dev/null
+++ b/arch/arm/mach-orion/gpio.c
@@ -0,0 +1,225 @@
1/*
2 * arch/arm/mach-orion/gpio.c
3 *
4 * GPIO functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/bitops.h>
18#include <asm/gpio.h>
19#include <asm/arch/orion.h>
20#include "common.h"
21
22static DEFINE_SPINLOCK(gpio_lock);
23static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
24static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */
25
26void __init orion_gpio_set_valid_pins(u32 pins)
27{
28 gpio_valid[0] = pins;
29}
30
31/*
32 * GENERIC_GPIO primitives
33 */
34int gpio_direction_input(unsigned pin)
35{
36 unsigned long flags;
37
38 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
39 pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
40 return -EINVAL;
41 }
42
43 spin_lock_irqsave(&gpio_lock, flags);
44
45 /*
46 * Some callers might have not used the gpio_request(),
47 * so flag this pin as requested now.
48 */
49 if (!gpio_label[pin])
50 gpio_label[pin] = "?";
51
52 orion_setbits(GPIO_IO_CONF, 1 << pin);
53
54 spin_unlock_irqrestore(&gpio_lock, flags);
55 return 0;
56}
57EXPORT_SYMBOL(gpio_direction_input);
58
59int gpio_direction_output(unsigned pin, int value)
60{
61 unsigned long flags;
62 int mask;
63
64 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
65 pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
66 return -EINVAL;
67 }
68
69 spin_lock_irqsave(&gpio_lock, flags);
70
71 /*
72 * Some callers might have not used the gpio_request(),
73 * so flag this pin as requested now.
74 */
75 if (!gpio_label[pin])
76 gpio_label[pin] = "?";
77
78 mask = 1 << pin;
79 orion_clrbits(GPIO_BLINK_EN, mask);
80 if (value)
81 orion_setbits(GPIO_OUT, mask);
82 else
83 orion_clrbits(GPIO_OUT, mask);
84 orion_clrbits(GPIO_IO_CONF, mask);
85
86 spin_unlock_irqrestore(&gpio_lock, flags);
87 return 0;
88}
89EXPORT_SYMBOL(gpio_direction_output);
90
91int gpio_get_value(unsigned pin)
92{
93 int val, mask = 1 << pin;
94
95 if (orion_read(GPIO_IO_CONF) & mask)
96 val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL);
97 else
98 val = orion_read(GPIO_OUT);
99
100 return val & mask;
101}
102EXPORT_SYMBOL(gpio_get_value);
103
104void gpio_set_value(unsigned pin, int value)
105{
106 unsigned long flags;
107 int mask = 1 << pin;
108
109 spin_lock_irqsave(&gpio_lock, flags);
110
111 orion_clrbits(GPIO_BLINK_EN, mask);
112 if (value)
113 orion_setbits(GPIO_OUT, mask);
114 else
115 orion_clrbits(GPIO_OUT, mask);
116
117 spin_unlock_irqrestore(&gpio_lock, flags);
118}
119EXPORT_SYMBOL(gpio_set_value);
120
121void orion_gpio_set_blink(unsigned pin, int blink)
122{
123 unsigned long flags;
124 int mask = 1 << pin;
125
126 spin_lock_irqsave(&gpio_lock, flags);
127
128 orion_clrbits(GPIO_OUT, mask);
129 if (blink)
130 orion_setbits(GPIO_BLINK_EN, mask);
131 else
132 orion_clrbits(GPIO_BLINK_EN, mask);
133
134 spin_unlock_irqrestore(&gpio_lock, flags);
135}
136EXPORT_SYMBOL(orion_gpio_set_blink);
137
138int gpio_request(unsigned pin, const char *label)
139{
140 int ret = 0;
141 unsigned long flags;
142
143 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
144 pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
145 return -EINVAL;
146 }
147
148 spin_lock_irqsave(&gpio_lock, flags);
149
150 if (gpio_label[pin]) {
151 pr_debug("%s: GPIO %d already used as %s\n",
152 __FUNCTION__, pin, gpio_label[pin]);
153 ret = -EBUSY;
154 } else
155 gpio_label[pin] = label ? label : "?";
156
157 spin_unlock_irqrestore(&gpio_lock, flags);
158 return ret;
159}
160EXPORT_SYMBOL(gpio_request);
161
162void gpio_free(unsigned pin)
163{
164 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
165 pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
166 return;
167 }
168
169 if (!gpio_label[pin])
170 pr_warning("%s: GPIO %d already freed\n", __FUNCTION__, pin);
171 else
172 gpio_label[pin] = NULL;
173}
174EXPORT_SYMBOL(gpio_free);
175
176/* Debug helper */
177void gpio_display(void)
178{
179 int i;
180
181 for (i = 0; i < GPIO_MAX; i++) {
182 printk(KERN_DEBUG "Pin-%d: ", i);
183
184 if (!test_bit(i, gpio_valid)) {
185 printk("non-GPIO\n");
186 } else if (!gpio_label[i]) {
187 printk("GPIO, free\n");
188 } else {
189 printk("GPIO, used by %s, ", gpio_label[i]);
190 if (orion_read(GPIO_IO_CONF) & (1 << i)) {
191 printk("input, active %s, level %s, edge %s\n",
192 ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
193 ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
194 ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
195 } else {
196 printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1);
197 }
198 }
199 }
200
201 printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
202 MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL));
203 printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
204 MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL));
205 printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
206 MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL));
207 printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
208 MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL));
209 printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
210 GPIO_OUT, orion_read(GPIO_OUT));
211 printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
212 GPIO_IO_CONF, orion_read(GPIO_IO_CONF));
213 printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
214 GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN));
215 printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
216 GPIO_IN_POL, orion_read(GPIO_IN_POL));
217 printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
218 GPIO_DATA_IN, orion_read(GPIO_DATA_IN));
219 printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
220 GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK));
221 printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
222 GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE));
223 printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
224 GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK));
225}
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c
new file mode 100644
index 000000000000..df7e12ad378b
--- /dev/null
+++ b/arch/arm/mach-orion/irq.c
@@ -0,0 +1,241 @@
1/*
2 * arch/arm/mach-orion/irq.c
3 *
4 * Core IRQ functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <asm/gpio.h>
17#include <asm/arch/orion.h>
18#include "common.h"
19
20/*****************************************************************************
21 * Orion GPIO IRQ
22 *
23 * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
24 * value of the line or the opposite value.
25 *
26 * Level IRQ handlers: DATA_IN is used directly as cause register.
27 * Interrupt are masked by LEVEL_MASK registers.
28 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
29 * Interrupt are masked by EDGE_MASK registers.
30 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
31 * the polarity to catch the next line transaction.
32 * This is a race condition that might not perfectly
33 * work on some use cases.
34 *
35 * Every eight GPIO lines are grouped (OR'ed) before going up to main
36 * cause register.
37 *
38 * EDGE cause mask
39 * data-in /--------| |-----| |----\
40 * -----| |----- ---- to main cause reg
41 * X \----------------| |----/
42 * polarity LEVEL mask
43 *
44 ****************************************************************************/
45static void orion_gpio_irq_ack(u32 irq)
46{
47 int pin = irq_to_gpio(irq);
48 if (irq_desc[irq].status & IRQ_LEVEL)
49 /*
50 * Mask bit for level interrupt
51 */
52 orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
53 else
54 /*
55 * Clear casue bit for egde interrupt
56 */
57 orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
58}
59
60static void orion_gpio_irq_mask(u32 irq)
61{
62 int pin = irq_to_gpio(irq);
63 if (irq_desc[irq].status & IRQ_LEVEL)
64 orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
65 else
66 orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
67}
68
69static void orion_gpio_irq_unmask(u32 irq)
70{
71 int pin = irq_to_gpio(irq);
72 if (irq_desc[irq].status & IRQ_LEVEL)
73 orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
74 else
75 orion_setbits(GPIO_EDGE_MASK, 1 << pin);
76}
77
78static int orion_gpio_set_irq_type(u32 irq, u32 type)
79{
80 int pin = irq_to_gpio(irq);
81 struct irq_desc *desc;
82
83 if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
84 printk(KERN_ERR "orion_gpio_set_irq_type failed "
85 "(irq %d, pin %d).\n", irq, pin);
86 return -EINVAL;
87 }
88
89 desc = irq_desc + irq;
90
91 switch (type) {
92 case IRQT_HIGH:
93 desc->handle_irq = handle_level_irq;
94 desc->status |= IRQ_LEVEL;
95 orion_clrbits(GPIO_IN_POL, (1 << pin));
96 break;
97 case IRQT_LOW:
98 desc->handle_irq = handle_level_irq;
99 desc->status |= IRQ_LEVEL;
100 orion_setbits(GPIO_IN_POL, (1 << pin));
101 break;
102 case IRQT_RISING:
103 desc->handle_irq = handle_edge_irq;
104 desc->status &= ~IRQ_LEVEL;
105 orion_clrbits(GPIO_IN_POL, (1 << pin));
106 break;
107 case IRQT_FALLING:
108 desc->handle_irq = handle_edge_irq;
109 desc->status &= ~IRQ_LEVEL;
110 orion_setbits(GPIO_IN_POL, (1 << pin));
111 break;
112 case IRQT_BOTHEDGE:
113 desc->handle_irq = handle_edge_irq;
114 desc->status &= ~IRQ_LEVEL;
115 /*
116 * set initial polarity based on current input level
117 */
118 if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
119 & (1 << pin))
120 orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
121 else
122 orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
123
124 break;
125 default:
126 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
127 return -EINVAL;
128 }
129
130 desc->status &= ~IRQ_TYPE_SENSE_MASK;
131 desc->status |= type & IRQ_TYPE_SENSE_MASK;
132
133 return 0;
134}
135
136static struct irq_chip orion_gpio_irq_chip = {
137 .name = "Orion-IRQ-GPIO",
138 .ack = orion_gpio_irq_ack,
139 .mask = orion_gpio_irq_mask,
140 .unmask = orion_gpio_irq_unmask,
141 .set_type = orion_gpio_set_irq_type,
142};
143
144static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
145{
146 u32 cause, offs, pin;
147
148 BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
149 offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
150 cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
151 (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
152
153 for (pin = offs; pin < offs + 8; pin++) {
154 if (cause & (1 << pin)) {
155 irq = gpio_to_irq(pin);
156 desc = irq_desc + irq;
157 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
158 /* Swap polarity (race with GPIO line) */
159 u32 polarity = orion_read(GPIO_IN_POL);
160 polarity ^= 1 << pin;
161 orion_write(GPIO_IN_POL, polarity);
162 }
163 desc_handle_irq(irq, desc);
164 }
165 }
166}
167
168static void __init orion_init_gpio_irq(void)
169{
170 int i;
171 struct irq_desc *desc;
172
173 /*
174 * Mask and clear GPIO IRQ interrupts
175 */
176 orion_write(GPIO_LEVEL_MASK, 0x0);
177 orion_write(GPIO_EDGE_MASK, 0x0);
178 orion_write(GPIO_EDGE_CAUSE, 0x0);
179
180 /*
181 * Register chained level handlers for GPIO IRQs by default.
182 * User can use set_type() if he wants to use edge types handlers.
183 */
184 for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
185 set_irq_chip(i, &orion_gpio_irq_chip);
186 set_irq_handler(i, handle_level_irq);
187 desc = irq_desc + i;
188 desc->status |= IRQ_LEVEL;
189 set_irq_flags(i, IRQF_VALID);
190 }
191 set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
192 set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
193 set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
194 set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
195}
196
197/*****************************************************************************
198 * Orion Main IRQ
199 ****************************************************************************/
200static void orion_main_irq_mask(u32 irq)
201{
202 orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
203}
204
205static void orion_main_irq_unmask(u32 irq)
206{
207 orion_setbits(MAIN_IRQ_MASK, 1 << irq);
208}
209
210static struct irq_chip orion_main_irq_chip = {
211 .name = "Orion-IRQ-Main",
212 .ack = orion_main_irq_mask,
213 .mask = orion_main_irq_mask,
214 .unmask = orion_main_irq_unmask,
215};
216
217static void __init orion_init_main_irq(void)
218{
219 int i;
220
221 /*
222 * Mask and clear Main IRQ interrupts
223 */
224 orion_write(MAIN_IRQ_MASK, 0x0);
225 orion_write(MAIN_IRQ_CAUSE, 0x0);
226
227 /*
228 * Register level handler for Main IRQs
229 */
230 for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
231 set_irq_chip(i, &orion_main_irq_chip);
232 set_irq_handler(i, handle_level_irq);
233 set_irq_flags(i, IRQF_VALID);
234 }
235}
236
237void __init orion_init_irq(void)
238{
239 orion_init_main_irq();
240 orion_init_gpio_irq();
241}
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c
new file mode 100644
index 000000000000..2d812ed6b5c7
--- /dev/null
+++ b/arch/arm/mach-orion/kurobox_pro-setup.c
@@ -0,0 +1,234 @@
1/*
2 * arch/arm/mach-orion/kurobox_pro-setup.c
3 *
4 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mtd/nand.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/i2c.h>
20#include <asm/mach-types.h>
21#include <asm/gpio.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/pci.h>
24#include <asm/arch/orion.h>
25#include <asm/arch/platform.h>
26#include "common.h"
27
28/*****************************************************************************
29 * KUROBOX-PRO Info
30 ****************************************************************************/
31
32/*
33 * 256K NOR flash Device bus boot chip select
34 */
35
36#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000
37#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K
38
39/*
40 * 256M NAND flash on Device bus chip select 1
41 */
42
43#define KUROBOX_PRO_NAND_BASE 0xfc000000
44#define KUROBOX_PRO_NAND_SIZE SZ_2M
45
46/*****************************************************************************
47 * 256MB NAND Flash on Device bus CS0
48 ****************************************************************************/
49
50static struct mtd_partition kurobox_pro_nand_parts[] = {
51 {
52 .name = "uImage",
53 .offset = 0,
54 .size = SZ_4M,
55 },
56 {
57 .name = "rootfs",
58 .offset = SZ_4M,
59 .size = SZ_64M,
60 },
61 {
62 .name = "extra",
63 .offset = SZ_4M + SZ_64M,
64 .size = SZ_256M - (SZ_4M + SZ_64M),
65 },
66};
67
68static struct resource kurobox_pro_nand_resource = {
69 .flags = IORESOURCE_MEM,
70 .start = KUROBOX_PRO_NAND_BASE,
71 .end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1,
72};
73
74static struct orion_nand_data kurobox_pro_nand_data = {
75 .parts = kurobox_pro_nand_parts,
76 .nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts),
77 .cle = 0,
78 .ale = 1,
79 .width = 8,
80};
81
82static struct platform_device kurobox_pro_nand_flash = {
83 .name = "orion_nand",
84 .id = -1,
85 .dev = {
86 .platform_data = &kurobox_pro_nand_data,
87 },
88 .resource = &kurobox_pro_nand_resource,
89 .num_resources = 1,
90};
91
92/*****************************************************************************
93 * 256KB NOR Flash on BOOT Device
94 ****************************************************************************/
95
96static struct physmap_flash_data kurobox_pro_nor_flash_data = {
97 .width = 1,
98};
99
100static struct resource kurobox_pro_nor_flash_resource = {
101 .flags = IORESOURCE_MEM,
102 .start = KUROBOX_PRO_NOR_BOOT_BASE,
103 .end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1,
104};
105
106static struct platform_device kurobox_pro_nor_flash = {
107 .name = "physmap-flash",
108 .id = 0,
109 .dev = {
110 .platform_data = &kurobox_pro_nor_flash_data,
111 },
112 .num_resources = 1,
113 .resource = &kurobox_pro_nor_flash_resource,
114};
115
116/*****************************************************************************
117 * PCI
118 ****************************************************************************/
119
120static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
121{
122 /*
123 * PCI isn't used on the Kuro
124 */
125 if (dev->bus->number == orion_pcie_local_bus_nr())
126 return IRQ_ORION_PCIE0_INT;
127 else
128 printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
129
130 return -1;
131}
132
133static struct hw_pci kurobox_pro_pci __initdata = {
134 .nr_controllers = 1,
135 .swizzle = pci_std_swizzle,
136 .setup = orion_pci_sys_setup,
137 .scan = orion_pci_sys_scan_bus,
138 .map_irq = kurobox_pro_pci_map_irq,
139};
140
141static int __init kurobox_pro_pci_init(void)
142{
143 if (machine_is_kurobox_pro())
144 pci_common_init(&kurobox_pro_pci);
145
146 return 0;
147}
148
149subsys_initcall(kurobox_pro_pci_init);
150
151/*****************************************************************************
152 * Ethernet
153 ****************************************************************************/
154
155static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
156 .phy_addr = 8,
157 .force_phy_addr = 1,
158};
159
160/*****************************************************************************
161 * RTC 5C372a on I2C bus
162 ****************************************************************************/
163static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
164 .driver_name = "rtc-rs5c372",
165 .type = "rs5c372a",
166 .addr = 0x32,
167};
168
169/*****************************************************************************
170 * General Setup
171 ****************************************************************************/
172
173static struct platform_device *kurobox_pro_devices[] __initdata = {
174 &kurobox_pro_nor_flash,
175 &kurobox_pro_nand_flash,
176};
177
178static void __init kurobox_pro_init(void)
179{
180 /*
181 * Setup basic Orion functions. Need to be called early.
182 */
183 orion_init();
184
185 /*
186 * Setup the CPU address decode windows for our devices
187 */
188 orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE,
189 KUROBOX_PRO_NOR_BOOT_SIZE, -1);
190 orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE,
191 KUROBOX_PRO_NAND_SIZE, -1);
192 /*
193 * Open a special address decode windows for the PCIE WA.
194 */
195 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
196 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
197 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
198
199 /*
200 * Setup Multiplexing Pins --
201 * MPP[0-1] Not used
202 * MPP[2] GPIO Micon
203 * MPP[3] GPIO RTC
204 * MPP[4-5] Not used
205 * MPP[6] Nand Flash REn
206 * MPP[7] Nand Flash WEn
207 * MPP[8-11] Not used
208 * MPP[12] SATA 0 presence Indication
209 * MPP[13] SATA 1 presence Indication
210 * MPP[14] SATA 0 active Indication
211 * MPP[15] SATA 1 active indication
212 * MPP[16-19] Not used
213 */
214 orion_write(MPP_0_7_CTRL, 0x44220003);
215 orion_write(MPP_8_15_CTRL, 0x55550000);
216 orion_write(MPP_16_19_CTRL, 0x0);
217
218 orion_gpio_set_valid_pins(0x0000000c);
219
220 platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
221 i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
222 orion_eth_init(&kurobox_pro_eth_data);
223}
224
225MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
226 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
227 .phys_io = ORION_REGS_BASE,
228 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
229 .boot_params = 0x00000100,
230 .init_machine = kurobox_pro_init,
231 .map_io = orion_map_io,
232 .init_irq = orion_init_irq,
233 .timer = &orion_timer,
234MACHINE_END
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c
new file mode 100644
index 000000000000..0498d7c69b30
--- /dev/null
+++ b/arch/arm/mach-orion/pci.c
@@ -0,0 +1,557 @@
1/*
2 * arch/arm/mach-orion/pci.c
3 *
4 * PCI and PCIE functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <asm/mach/pci.h>
16#include "common.h"
17
18/*****************************************************************************
19 * Orion has one PCIE controller and one PCI controller.
20 *
21 * Note1: The local PCIE bus number is '0'. The local PCI bus number
22 * follows the scanned PCIE bridged busses, if any.
23 *
24 * Note2: It is possible for PCI/PCIE agents to access many subsystem's
25 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
26 * device bus, Orion registers, etc. However this code only enable the
27 * access to DDR banks.
28 ****************************************************************************/
29
30
31/*****************************************************************************
32 * PCIE controller
33 ****************************************************************************/
34#define PCIE_CTRL ORION_PCIE_REG(0x1a00)
35#define PCIE_STAT ORION_PCIE_REG(0x1a04)
36#define PCIE_DEV_ID ORION_PCIE_REG(0x0000)
37#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004)
38#define PCIE_DEV_REV ORION_PCIE_REG(0x0008)
39#define PCIE_MASK ORION_PCIE_REG(0x1910)
40#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8)
41#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc)
42
43/*
44 * PCIE_STAT bits
45 */
46#define PCIE_STAT_LINK_DOWN 1
47#define PCIE_STAT_BUS_OFFS 8
48#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS)
49#define PCIE_STAT_DEV_OFFS 20
50#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS)
51
52/*
53 * PCIE_CONF_ADDR bits
54 */
55#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc))
56#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
57#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
58#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
59#define PCIE_CONF_ADDR_EN (1 << 31)
60
61/*
62 * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
63 * and then reading the PCIE_CONF_DATA register. Need to make sure these
64 * transactions are atomic.
65 */
66static DEFINE_SPINLOCK(orion_pcie_lock);
67
68void orion_pcie_id(u32 *dev, u32 *rev)
69{
70 *dev = orion_read(PCIE_DEV_ID) >> 16;
71 *rev = orion_read(PCIE_DEV_REV) & 0xff;
72}
73
74u32 orion_pcie_local_bus_nr(void)
75{
76 u32 stat = orion_read(PCIE_STAT);
77 return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
78}
79
80static u32 orion_pcie_local_dev_nr(void)
81{
82 u32 stat = orion_read(PCIE_STAT);
83 return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
84}
85
86static u32 orion_pcie_no_link(void)
87{
88 u32 stat = orion_read(PCIE_STAT);
89 return(stat & PCIE_STAT_LINK_DOWN);
90}
91
92static void orion_pcie_set_bus_nr(int nr)
93{
94 orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
95 orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
96}
97
98static void orion_pcie_master_slave_enable(void)
99{
100 orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
101 PCI_COMMAND_IO |
102 PCI_COMMAND_MEMORY);
103}
104
105static void orion_pcie_enable_interrupts(void)
106{
107 /*
108 * Enable interrupts lines
109 * INTA[24] INTB[25] INTC[26] INTD[27]
110 */
111 orion_setbits(PCIE_MASK, 0xf<<24);
112}
113
114static int orion_pcie_valid_config(u32 bus, u32 dev)
115{
116 /*
117 * Don't go out when trying to access --
118 * 1. our own device
119 * 2. where there's no device connected (no link)
120 * 3. nonexisting devices on local bus
121 */
122
123 if ((orion_pcie_local_bus_nr() == bus) &&
124 (orion_pcie_local_dev_nr() == dev))
125 return 0;
126
127 if (orion_pcie_no_link())
128 return 0;
129
130 if (bus == orion_pcie_local_bus_nr())
131 if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
132 ((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
133 return 0;
134
135 return 1;
136}
137
138static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
139 int size, u32 *val)
140{
141 unsigned long flags;
142 unsigned int dev, rev, pcie_addr;
143
144 if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
145 *val = 0xffffffff;
146 return PCIBIOS_DEVICE_NOT_FOUND;
147 }
148
149 spin_lock_irqsave(&orion_pcie_lock, flags);
150
151 orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
152 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
153 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
154 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
155
156 orion_pcie_id(&dev, &rev);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 /* extended register space */
159 pcie_addr = ORION_PCIE_WA_BASE;
160 pcie_addr |= PCIE_CONF_BUS(bus->number) |
161 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
163 PCIE_CONF_REG(where);
164 *val = orion_read(pcie_addr);
165 } else
166 *val = orion_read(PCIE_CONF_DATA);
167
168 if (size == 1)
169 *val = (*val >> (8*(where & 0x3))) & 0xff;
170 else if (size == 2)
171 *val = (*val >> (8*(where & 0x3))) & 0xffff;
172
173 spin_unlock_irqrestore(&orion_pcie_lock, flags);
174
175 return PCIBIOS_SUCCESSFUL;
176}
177
178
179static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
180 int size, u32 val)
181{
182 unsigned long flags;
183 int ret;
184
185 if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
186 return PCIBIOS_DEVICE_NOT_FOUND;
187
188 spin_lock_irqsave(&orion_pcie_lock, flags);
189
190 ret = PCIBIOS_SUCCESSFUL;
191
192 orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
193 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
194 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
195 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
196
197 if (size == 4) {
198 __raw_writel(val, PCIE_CONF_DATA);
199 } else if (size == 2) {
200 __raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
201 } else if (size == 1) {
202 __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
203 } else {
204 ret = PCIBIOS_BAD_REGISTER_NUMBER;
205 }
206
207 spin_unlock_irqrestore(&orion_pcie_lock, flags);
208
209 return ret;
210}
211
212struct pci_ops orion_pcie_ops = {
213 .read = orion_pcie_rd_conf,
214 .write = orion_pcie_wr_conf,
215};
216
217
218static int orion_pcie_setup(struct pci_sys_data *sys)
219{
220 struct resource *res;
221
222 /*
223 * Master + Slave enable
224 */
225 orion_pcie_master_slave_enable();
226
227 /*
228 * Enable interrupts lines A-D
229 */
230 orion_pcie_enable_interrupts();
231
232 /*
233 * Request resource
234 */
235 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
236 if (!res)
237 panic("orion_pci_setup unable to alloc resources");
238
239 /*
240 * IORESOURCE_IO
241 */
242 res[0].name = "PCI-EX I/O Space";
243 res[0].flags = IORESOURCE_IO;
244 res[0].start = ORION_PCIE_IO_REMAP;
245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
246 if (request_resource(&ioport_resource, &res[0]))
247 panic("Request PCIE IO resource failed\n");
248 sys->resource[0] = &res[0];
249
250 /*
251 * IORESOURCE_MEM
252 */
253 res[1].name = "PCI-EX Memory Space";
254 res[1].flags = IORESOURCE_MEM;
255 res[1].start = ORION_PCIE_MEM_BASE;
256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
257 if (request_resource(&iomem_resource, &res[1]))
258 panic("Request PCIE Memory resource failed\n");
259 sys->resource[1] = &res[1];
260
261 sys->resource[2] = NULL;
262 sys->io_offset = 0;
263
264 return 1;
265}
266
267/*****************************************************************************
268 * PCI controller
269 ****************************************************************************/
270#define PCI_MODE ORION_PCI_REG(0xd00)
271#define PCI_CMD ORION_PCI_REG(0xc00)
272#define PCI_P2P_CONF ORION_PCI_REG(0x1d14)
273#define PCI_CONF_ADDR ORION_PCI_REG(0xc78)
274#define PCI_CONF_DATA ORION_PCI_REG(0xc7c)
275
276/*
277 * PCI_MODE bits
278 */
279#define PCI_MODE_64BIT (1 << 2)
280#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
281
282/*
283 * PCI_CMD bits
284 */
285#define PCI_CMD_HOST_REORDER (1 << 29)
286
287/*
288 * PCI_P2P_CONF bits
289 */
290#define PCI_P2P_BUS_OFFS 16
291#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
292#define PCI_P2P_DEV_OFFS 24
293#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
294
295/*
296 * PCI_CONF_ADDR bits
297 */
298#define PCI_CONF_REG(reg) ((reg) & 0xfc)
299#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
300#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
301#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
302#define PCI_CONF_ADDR_EN (1 << 31)
303
304/*
305 * Internal configuration space
306 */
307#define PCI_CONF_FUNC_STAT_CMD 0
308#define PCI_CONF_REG_STAT_CMD 4
309#define PCIX_STAT 0x64
310#define PCIX_STAT_BUS_OFFS 8
311#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
312
313/*
314 * PCI config cycles are done by programming the PCI_CONF_ADDR register
315 * and then reading the PCI_CONF_DATA register. Need to make sure these
316 * transactions are atomic.
317 */
318static DEFINE_SPINLOCK(orion_pci_lock);
319
320u32 orion_pci_local_bus_nr(void)
321{
322 u32 conf = orion_read(PCI_P2P_CONF);
323 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
324}
325
326u32 orion_pci_local_dev_nr(void)
327{
328 u32 conf = orion_read(PCI_P2P_CONF);
329 return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
330}
331
332int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
333 u32 where, u32 size, u32 *val)
334{
335 unsigned long flags;
336 spin_lock_irqsave(&orion_pci_lock, flags);
337
338 orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
339 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
340 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
341
342 *val = orion_read(PCI_CONF_DATA);
343
344 if (size == 1)
345 *val = (*val >> (8*(where & 0x3))) & 0xff;
346 else if (size == 2)
347 *val = (*val >> (8*(where & 0x3))) & 0xffff;
348
349 spin_unlock_irqrestore(&orion_pci_lock, flags);
350
351 return PCIBIOS_SUCCESSFUL;
352}
353
354int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
355 u32 where, u32 size, u32 val)
356{
357 unsigned long flags;
358 int ret = PCIBIOS_SUCCESSFUL;
359
360 spin_lock_irqsave(&orion_pci_lock, flags);
361
362 orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
363 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
364 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
365
366 if (size == 4) {
367 __raw_writel(val, PCI_CONF_DATA);
368 } else if (size == 2) {
369 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
370 } else if (size == 1) {
371 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
372 } else {
373 ret = PCIBIOS_BAD_REGISTER_NUMBER;
374 }
375
376 spin_unlock_irqrestore(&orion_pci_lock, flags);
377
378 return ret;
379}
380
381static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
382 int where, int size, u32 *val)
383{
384 /*
385 * Don't go out for local device
386 */
387 if ((orion_pci_local_bus_nr() == bus->number) &&
388 (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
389 *val = 0xffffffff;
390 return PCIBIOS_DEVICE_NOT_FOUND;
391 }
392
393 return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
394 PCI_FUNC(devfn), where, size, val);
395}
396
397static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
398 int where, int size, u32 val)
399{
400 /*
401 * Don't go out for local device
402 */
403 if ((orion_pci_local_bus_nr() == bus->number) &&
404 (orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
405 return PCIBIOS_DEVICE_NOT_FOUND;
406
407 return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
408 PCI_FUNC(devfn), where, size, val);
409}
410
411struct pci_ops orion_pci_ops = {
412 .read = orion_pci_rd_conf,
413 .write = orion_pci_wr_conf,
414};
415
416static void orion_pci_set_bus_nr(int nr)
417{
418 u32 p2p = orion_read(PCI_P2P_CONF);
419
420 if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
421 /*
422 * PCI-X mode
423 */
424 u32 pcix_status, bus, dev;
425 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
426 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
427 orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
428 pcix_status &= ~PCIX_STAT_BUS_MASK;
429 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
430 orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
431 } else {
432 /*
433 * PCI Conventional mode
434 */
435 p2p &= ~PCI_P2P_BUS_MASK;
436 p2p |= (nr << PCI_P2P_BUS_OFFS);
437 orion_write(PCI_P2P_CONF, p2p);
438 }
439}
440
441static void orion_pci_master_slave_enable(void)
442{
443 u32 bus_nr, dev_nr, func, reg, val;
444
445 bus_nr = orion_pci_local_bus_nr();
446 dev_nr = orion_pci_local_dev_nr();
447 func = PCI_CONF_FUNC_STAT_CMD;
448 reg = PCI_CONF_REG_STAT_CMD;
449 orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
450 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
451 orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
452}
453
454static int orion_pci_setup(struct pci_sys_data *sys)
455{
456 struct resource *res;
457
458 /*
459 * Master + Slave enable
460 */
461 orion_pci_master_slave_enable();
462
463 /*
464 * Force ordering
465 */
466 orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
467
468 /*
469 * Request resources
470 */
471 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
472 if (!res)
473 panic("orion_pci_setup unable to alloc resources");
474
475 /*
476 * IORESOURCE_IO
477 */
478 res[0].name = "PCI I/O Space";
479 res[0].flags = IORESOURCE_IO;
480 res[0].start = ORION_PCI_IO_REMAP;
481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
482 if (request_resource(&ioport_resource, &res[0]))
483 panic("Request PCI IO resource failed\n");
484 sys->resource[0] = &res[0];
485
486 /*
487 * IORESOURCE_MEM
488 */
489 res[1].name = "PCI Memory Space";
490 res[1].flags = IORESOURCE_MEM;
491 res[1].start = ORION_PCI_MEM_BASE;
492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
493 if (request_resource(&iomem_resource, &res[1]))
494 panic("Request PCI Memory resource failed\n");
495 sys->resource[1] = &res[1];
496
497 sys->resource[2] = NULL;
498 sys->io_offset = 0;
499
500 return 1;
501}
502
503
504/*****************************************************************************
505 * General PCIE + PCI
506 ****************************************************************************/
507int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
508{
509 int ret = 0;
510
511 if (nr == 0) {
512 /*
513 * PCIE setup
514 */
515 orion_pcie_set_bus_nr(0);
516 ret = orion_pcie_setup(sys);
517 } else if (nr == 1) {
518 /*
519 * PCI setup
520 */
521 ret = orion_pci_setup(sys);
522 }
523
524 return ret;
525}
526
527struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
528{
529 struct pci_ops *ops;
530 struct pci_bus *bus;
531
532
533 if (nr == 0) {
534 u32 pci_bus;
535 /*
536 * PCIE scan
537 */
538 ops = &orion_pcie_ops;
539 bus = pci_scan_bus(sys->busnr, ops, sys);
540 /*
541 * Set local PCI bus number to follow PCIE bridges (if any)
542 */
543 pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
544 orion_pci_set_bus_nr(pci_bus);
545 } else if (nr == 1) {
546 /*
547 * PCI scan
548 */
549 ops = &orion_pci_ops;
550 bus = pci_scan_bus(sys->busnr, ops, sys);
551 } else {
552 BUG();
553 bus = NULL;
554 }
555
556 return bus;
557}
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c
new file mode 100644
index 000000000000..026d74325d01
--- /dev/null
+++ b/arch/arm/mach-orion/rd88f5182-setup.c
@@ -0,0 +1,306 @@
1/*
2 * arch/arm/mach-orion/rd88f5182-setup.c
3 *
4 * Marvell Orion-NAS Reference Design Setup
5 *
6 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/i2c.h>
21#include <asm/mach-types.h>
22#include <asm/gpio.h>
23#include <asm/leds.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/pci.h>
26#include <asm/arch/orion.h>
27#include <asm/arch/platform.h>
28#include "common.h"
29
30/*****************************************************************************
31 * RD-88F5182 Info
32 ****************************************************************************/
33
34/*
35 * 512K NOR flash Device bus boot chip select
36 */
37
38#define RD88F5182_NOR_BOOT_BASE 0xf4000000
39#define RD88F5182_NOR_BOOT_SIZE SZ_512K
40
41/*
42 * 16M NOR flash on Device bus chip select 1
43 */
44
45#define RD88F5182_NOR_BASE 0xfc000000
46#define RD88F5182_NOR_SIZE SZ_16M
47
48/*
49 * PCI
50 */
51
52#define RD88F5182_PCI_SLOT0_OFFS 7
53#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
54#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
55
56/*
57 * GPIO Debug LED
58 */
59
60#define RD88F5182_GPIO_DBG_LED 0
61
62/*****************************************************************************
63 * 16M NOR Flash on Device bus CS1
64 ****************************************************************************/
65
66static struct physmap_flash_data rd88f5182_nor_flash_data = {
67 .width = 1,
68};
69
70static struct resource rd88f5182_nor_flash_resource = {
71 .flags = IORESOURCE_MEM,
72 .start = RD88F5182_NOR_BASE,
73 .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
74};
75
76static struct platform_device rd88f5182_nor_flash = {
77 .name = "physmap-flash",
78 .id = 0,
79 .dev = {
80 .platform_data = &rd88f5182_nor_flash_data,
81 },
82 .num_resources = 1,
83 .resource = &rd88f5182_nor_flash_resource,
84};
85
86#ifdef CONFIG_LEDS
87
88/*****************************************************************************
89 * Use GPIO debug led as CPU active indication
90 ****************************************************************************/
91
92static void rd88f5182_dbgled_event(led_event_t evt)
93{
94 int val;
95
96 if (evt == led_idle_end)
97 val = 1;
98 else if (evt == led_idle_start)
99 val = 0;
100 else
101 return;
102
103 gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
104}
105
106static int __init rd88f5182_dbgled_init(void)
107{
108 int pin;
109
110 if (machine_is_rd88f5182()) {
111 pin = RD88F5182_GPIO_DBG_LED;
112
113 if (gpio_request(pin, "DBGLED") == 0) {
114 if (gpio_direction_output(pin, 0) != 0) {
115 printk(KERN_ERR "rd88f5182_dbgled_init failed "
116 "to set output pin %d\n", pin);
117 gpio_free(pin);
118 return 0;
119 }
120 } else {
121 printk(KERN_ERR "rd88f5182_dbgled_init failed "
122 "to request gpio %d\n", pin);
123 return 0;
124 }
125
126 leds_event = rd88f5182_dbgled_event;
127 }
128 return 0;
129}
130
131__initcall(rd88f5182_dbgled_init);
132
133#endif
134
135/*****************************************************************************
136 * PCI
137 ****************************************************************************/
138
139void __init rd88f5182_pci_preinit(void)
140{
141 int pin;
142
143 /*
144 * Configure PCI GPIO IRQ pins
145 */
146 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
147 if (gpio_request(pin, "PCI IntA") == 0) {
148 if (gpio_direction_input(pin) == 0) {
149 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
150 } else {
151 printk(KERN_ERR "rd88f5182_pci_preinit faield to "
152 "set_irq_type pin %d\n", pin);
153 gpio_free(pin);
154 }
155 } else {
156 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
157 }
158
159 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
160 if (gpio_request(pin, "PCI IntB") == 0) {
161 if (gpio_direction_input(pin) == 0) {
162 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
163 } else {
164 printk(KERN_ERR "rd88f5182_pci_preinit faield to "
165 "set_irq_type pin %d\n", pin);
166 gpio_free(pin);
167 }
168 } else {
169 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
170 }
171}
172
173static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
174{
175 /*
176 * PCI-E isn't used on the RD2
177 */
178 if (dev->bus->number == orion_pcie_local_bus_nr())
179 return IRQ_ORION_PCIE0_INT;
180
181 /*
182 * PCI IRQs are connected via GPIOs
183 */
184 switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
185 case 0:
186 if (pin == 1)
187 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
188 else
189 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
190 default:
191 return -1;
192 }
193}
194
195static struct hw_pci rd88f5182_pci __initdata = {
196 .nr_controllers = 2,
197 .preinit = rd88f5182_pci_preinit,
198 .swizzle = pci_std_swizzle,
199 .setup = orion_pci_sys_setup,
200 .scan = orion_pci_sys_scan_bus,
201 .map_irq = rd88f5182_pci_map_irq,
202};
203
204static int __init rd88f5182_pci_init(void)
205{
206 if (machine_is_rd88f5182())
207 pci_common_init(&rd88f5182_pci);
208
209 return 0;
210}
211
212subsys_initcall(rd88f5182_pci_init);
213
214/*****************************************************************************
215 * Ethernet
216 ****************************************************************************/
217
218static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
219 .phy_addr = 8,
220 .force_phy_addr = 1,
221};
222
223/*****************************************************************************
224 * RTC DS1338 on I2C bus
225 ****************************************************************************/
226static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
227 .driver_name = "rtc-ds1307",
228 .type = "ds1338",
229 .addr = 0x68,
230};
231
232/*****************************************************************************
233 * General Setup
234 ****************************************************************************/
235
236static struct platform_device *rd88f5182_devices[] __initdata = {
237 &rd88f5182_nor_flash,
238};
239
240static void __init rd88f5182_init(void)
241{
242 /*
243 * Setup basic Orion functions. Need to be called early.
244 */
245 orion_init();
246
247 /*
248 * Setup the CPU address decode windows for our devices
249 */
250 orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE,
251 RD88F5182_NOR_BOOT_SIZE, -1);
252 orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE,
253 RD88F5182_NOR_SIZE, -1);
254
255 /*
256 * Open a special address decode windows for the PCIE WA.
257 */
258 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
259 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
260 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
261
262 /*
263 * Setup Multiplexing Pins --
264 * MPP[0] Debug Led (GPIO - Out)
265 * MPP[1] Debug Led (GPIO - Out)
266 * MPP[2] N/A
267 * MPP[3] RTC_Int (GPIO - In)
268 * MPP[4] GPIO
269 * MPP[5] GPIO
270 * MPP[6] PCI_intA (GPIO - In)
271 * MPP[7] PCI_intB (GPIO - In)
272 * MPP[8-11] N/A
273 * MPP[12] SATA 0 presence Indication
274 * MPP[13] SATA 1 presence Indication
275 * MPP[14] SATA 0 active Indication
276 * MPP[15] SATA 1 active indication
277 * MPP[16-19] Not used
278 * MPP[20] PCI Clock to MV88F5182
279 * MPP[21] PCI Clock to mini PCI CON11
280 * MPP[22] USB 0 over current indication
281 * MPP[23] USB 1 over current indication
282 * MPP[24] USB 1 over current enable
283 * MPP[25] USB 0 over current enable
284 */
285
286 orion_write(MPP_0_7_CTRL, 0x00000003);
287 orion_write(MPP_8_15_CTRL, 0x55550000);
288 orion_write(MPP_16_19_CTRL, 0x5555);
289
290 orion_gpio_set_valid_pins(0x000000fb);
291
292 platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
293 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
294 orion_eth_init(&rd88f5182_eth_data);
295}
296
297MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
298 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
299 .phys_io = ORION_REGS_BASE,
300 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
301 .boot_params = 0x00000100,
302 .init_machine = rd88f5182_init,
303 .map_io = orion_map_io,
304 .init_irq = orion_init_irq,
305 .timer = &orion_timer,
306MACHINE_END
diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c
new file mode 100644
index 000000000000..bd4262da4f40
--- /dev/null
+++ b/arch/arm/mach-orion/time.c
@@ -0,0 +1,181 @@
1/*
2 * arch/arm/mach-orion/time.c
3 *
4 * Core time functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/clockchips.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <asm/mach/time.h>
18#include <asm/arch/orion.h>
19#include "common.h"
20
21/*
22 * Timer0: clock_event_device, Tick.
23 * Timer1: clocksource, Free running.
24 * WatchDog: Not used.
25 *
26 * Timers are counting down.
27 */
28#define CLOCKEVENT 0
29#define CLOCKSOURCE 1
30
31/*
32 * Timers bits
33 */
34#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1))
35#define TIMER_EN(x) (1 << ((x) * 2))
36#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1))
37#define BRIDGE_INT_TIMER_WD (1 << 3)
38#define TIMER_WD_EN (1 << 4)
39#define TIMER_WD_RELOAD_EN (1 << 5)
40
41static cycle_t orion_clksrc_read(void)
42{
43 return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
44}
45
46static struct clocksource orion_clksrc = {
47 .name = "orion_clocksource",
48 .shift = 20,
49 .rating = 300,
50 .read = orion_clksrc_read,
51 .mask = CLOCKSOURCE_MASK(32),
52 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
53};
54
55static int
56orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
57{
58 unsigned long flags;
59
60 if (delta == 0)
61 return -ETIME;
62
63 local_irq_save(flags);
64
65 /*
66 * Clear and enable timer interrupt bit
67 */
68 orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
69 orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
70
71 /*
72 * Setup new timer value
73 */
74 orion_write(TIMER_VAL(CLOCKEVENT), delta);
75
76 /*
77 * Disable auto reload and kickoff the timer
78 */
79 orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
80 orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
81
82 local_irq_restore(flags);
83
84 return 0;
85}
86
87static void
88orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
89{
90 unsigned long flags;
91
92 local_irq_save(flags);
93
94 if (mode == CLOCK_EVT_MODE_PERIODIC) {
95 /*
96 * Setup latch cycles in timer and enable reload interrupt.
97 */
98 orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
99 orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
100 orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
101 orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
102 TIMER_EN(CLOCKEVENT));
103 } else {
104 /*
105 * Disable timer and interrupt
106 */
107 orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
108 orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
109 orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
110 TIMER_EN(CLOCKEVENT));
111 }
112
113 local_irq_restore(flags);
114}
115
116static struct clock_event_device orion_clkevt = {
117 .name = "orion_tick",
118 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
119 .shift = 32,
120 .rating = 300,
121 .cpumask = CPU_MASK_CPU0,
122 .set_next_event = orion_clkevt_next_event,
123 .set_mode = orion_clkevt_mode,
124};
125
126static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
127{
128 /*
129 * Clear cause bit and do event
130 */
131 orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
132 orion_clkevt.event_handler(&orion_clkevt);
133 return IRQ_HANDLED;
134}
135
136static struct irqaction orion_timer_irq = {
137 .name = "orion_tick",
138 .flags = IRQF_DISABLED | IRQF_TIMER,
139 .handler = orion_timer_interrupt
140};
141
142static void orion_timer_init(void)
143{
144 /*
145 * Setup clocksource free running timer (no interrupt on reload)
146 */
147 orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
148 orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
149 orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
150 orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) |
151 TIMER_EN(CLOCKSOURCE));
152
153 /*
154 * Register clocksource
155 */
156 orion_clksrc.mult =
157 clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
158
159 clocksource_register(&orion_clksrc);
160
161 /*
162 * Connect and enable tick handler
163 */
164 setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
165
166 /*
167 * Register clockevent
168 */
169 orion_clkevt.mult =
170 div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
171 orion_clkevt.max_delta_ns =
172 clockevent_delta2ns(0xfffffffe, &orion_clkevt);
173 orion_clkevt.min_delta_ns =
174 clockevent_delta2ns(1, &orion_clkevt);
175
176 clockevents_register_device(&orion_clkevt);
177}
178
179struct sys_timer orion_timer = {
180 .init = orion_timer_init,
181};
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c
new file mode 100644
index 000000000000..e3e930efd155
--- /dev/null
+++ b/arch/arm/mach-orion/ts209-setup.c
@@ -0,0 +1,335 @@
1/*
2 * QNAP TS-109/TS-209 Board Setup
3 *
4 * Maintainer: Byron Bradley <byron.bbradley@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/irq.h>
17#include <linux/mtd/physmap.h>
18#include <linux/mtd/nand.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/gpio_keys.h>
21#include <linux/input.h>
22#include <linux/i2c.h>
23#include <linux/serial_reg.h>
24#include <asm/mach-types.h>
25#include <asm/gpio.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/pci.h>
28#include <asm/arch/orion.h>
29#include <asm/arch/platform.h>
30#include "common.h"
31
32#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
33#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
34
35/****************************************************************************
36 * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
37 * partitions on the device because we want to keep compatability with
38 * existing QNAP firmware.
39 *
40 * Layout as used by QNAP:
41 * [2] 0x00000000-0x00200000 : "Kernel"
42 * [3] 0x00200000-0x00600000 : "RootFS1"
43 * [4] 0x00600000-0x00700000 : "RootFS2"
44 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
45 * [5] 0x00760000-0x00780000 : "U-Boot Config"
46 * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
47 ***************************************************************************/
48static struct mtd_partition qnap_ts209_partitions[] = {
49 {
50 .name = "U-Boot",
51 .size = 0x00080000,
52 .offset = 0x00780000,
53 .mask_flags = MTD_WRITEABLE,
54 }, {
55 .name = "Kernel",
56 .size = 0x00200000,
57 .offset = 0,
58 }, {
59 .name = "RootFS1",
60 .size = 0x00400000,
61 .offset = 0x00200000,
62 }, {
63 .name = "RootFS2",
64 .size = 0x00100000,
65 .offset = 0x00600000,
66 }, {
67 .name = "U-Boot Config",
68 .size = 0x00020000,
69 .offset = 0x00760000,
70 }, {
71 .name = "NAS Config",
72 .size = 0x00060000,
73 .offset = 0x00700000,
74 .mask_flags = MTD_WRITEABLE,
75 }
76};
77
78static struct physmap_flash_data qnap_ts209_nor_flash_data = {
79 .width = 1,
80 .parts = qnap_ts209_partitions,
81 .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
82};
83
84static struct resource qnap_ts209_nor_flash_resource = {
85 .flags = IORESOURCE_MEM,
86 .start = QNAP_TS209_NOR_BOOT_BASE,
87 .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
88};
89
90static struct platform_device qnap_ts209_nor_flash = {
91 .name = "physmap-flash",
92 .id = 0,
93 .dev = { .platform_data = &qnap_ts209_nor_flash_data, },
94 .resource = &qnap_ts209_nor_flash_resource,
95 .num_resources = 1,
96};
97
98/*****************************************************************************
99 * PCI
100 ****************************************************************************/
101
102#define QNAP_TS209_PCI_SLOT0_OFFS 7
103#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6
104#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7
105
106void __init qnap_ts209_pci_preinit(void)
107{
108 int pin;
109
110 /*
111 * Configure PCI GPIO IRQ pins
112 */
113 pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
114 if (gpio_request(pin, "PCI Int1") == 0) {
115 if (gpio_direction_input(pin) == 0) {
116 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
117 } else {
118 printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
119 "set_irq_type pin %d\n", pin);
120 gpio_free(pin);
121 }
122 } else {
123 printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
124 "%d\n", pin);
125 }
126
127 pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
128 if (gpio_request(pin, "PCI Int2") == 0) {
129 if (gpio_direction_input(pin) == 0) {
130 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
131 } else {
132 printk(KERN_ERR "qnap_ts209_pci_preinit failed "
133 "to set_irq_type pin %d\n", pin);
134 gpio_free(pin);
135 }
136 } else {
137 printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
138 "%d\n", pin);
139 }
140}
141
142static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
143{
144 /*
145 * PCIE IRQ is connected internally (not GPIO)
146 */
147 if (dev->bus->number == orion_pcie_local_bus_nr())
148 return IRQ_ORION_PCIE0_INT;
149
150 /*
151 * PCI IRQs are connected via GPIOs
152 */
153 switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) {
154 case 0:
155 return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN);
156 case 1:
157 return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN);
158 default:
159 return -1;
160 }
161}
162
163static struct hw_pci qnap_ts209_pci __initdata = {
164 .nr_controllers = 2,
165 .preinit = qnap_ts209_pci_preinit,
166 .swizzle = pci_std_swizzle,
167 .setup = orion_pci_sys_setup,
168 .scan = orion_pci_sys_scan_bus,
169 .map_irq = qnap_ts209_pci_map_irq,
170};
171
172static int __init qnap_ts209_pci_init(void)
173{
174 if (machine_is_ts_x09())
175 pci_common_init(&qnap_ts209_pci);
176
177 return 0;
178}
179
180subsys_initcall(qnap_ts209_pci_init);
181
182/*****************************************************************************
183 * Ethernet
184 ****************************************************************************/
185
186static struct mv643xx_eth_platform_data qnap_ts209_eth_data = {
187 .phy_addr = 8,
188 .force_phy_addr = 1,
189};
190
191/*****************************************************************************
192 * RTC S35390A on I2C bus
193 ****************************************************************************/
194static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
195 .driver_name = "rtc-s35390a",
196 .addr = 0x30,
197};
198
199/****************************************************************************
200 * GPIO Attached Keys
201 * Power button is attached to the PIC microcontroller
202 ****************************************************************************/
203
204#define QNAP_TS209_GPIO_KEY_MEDIA 1
205#define QNAP_TS209_GPIO_KEY_RESET 2
206
207static struct gpio_keys_button qnap_ts209_buttons[] = {
208 {
209 .code = KEY_RESTART,
210 .gpio = QNAP_TS209_GPIO_KEY_MEDIA,
211 .desc = "USB Copy Button",
212 .active_low = 1,
213 },
214 {
215 .code = KEY_POWER,
216 .gpio = QNAP_TS209_GPIO_KEY_RESET,
217 .desc = "Reset Button",
218 .active_low = 1,
219 }
220};
221
222static struct gpio_keys_platform_data qnap_ts209_button_data = {
223 .buttons = qnap_ts209_buttons,
224 .nbuttons = ARRAY_SIZE(qnap_ts209_buttons),
225};
226
227static struct platform_device qnap_ts209_button_device = {
228 .name = "gpio-keys",
229 .id = -1,
230 .num_resources = 0,
231 .dev = { .platform_data = &qnap_ts209_button_data, },
232};
233
234/*****************************************************************************
235 * General Setup
236 ****************************************************************************/
237
238static struct platform_device *qnap_ts209_devices[] __initdata = {
239 &qnap_ts209_nor_flash,
240 &qnap_ts209_button_device,
241};
242
243/*
244 * QNAP TS-[12]09 specific power off method via UART1-attached PIC
245 */
246
247#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2))
248
249static void qnap_ts209_power_off(void)
250{
251 /* 19200 baud divisor */
252 const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200));
253
254 pr_info("%s: triggering power-off...\n", __func__);
255
256 /* hijack uart1 and reset into sane state (19200,8n1) */
257 orion_write(UART1_REG(LCR), 0x83);
258 orion_write(UART1_REG(DLL), divisor & 0xff);
259 orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
260 orion_write(UART1_REG(LCR), 0x03);
261 orion_write(UART1_REG(IER), 0x00);
262 orion_write(UART1_REG(FCR), 0x00);
263 orion_write(UART1_REG(MCR), 0x00);
264
265 /* send the power-off command 'A' to PIC */
266 orion_write(UART1_REG(TX), 'A');
267}
268
269static void __init qnap_ts209_init(void)
270{
271 /*
272 * Setup basic Orion functions. Need to be called early.
273 */
274 orion_init();
275
276 /*
277 * Setup flash mapping
278 */
279 orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE,
280 QNAP_TS209_NOR_BOOT_SIZE, -1);
281
282 /*
283 * Open a special address decode windows for the PCIE WA.
284 */
285 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
286 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
287 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
288
289 /*
290 * Setup Multiplexing Pins --
291 * MPP[0] Reserved
292 * MPP[1] USB copy button (0 active)
293 * MPP[2] Load defaults button (0 active)
294 * MPP[3] GPIO RTC
295 * MPP[4-5] Reserved
296 * MPP[6] PCI Int A
297 * MPP[7] PCI Int B
298 * MPP[8-11] Reserved
299 * MPP[12] SATA 0 presence
300 * MPP[13] SATA 1 presence
301 * MPP[14] SATA 0 active
302 * MPP[15] SATA 1 active
303 * MPP[16] UART1 RXD
304 * MPP[17] UART1 TXD
305 * MPP[18] SW_RST (0 active)
306 * MPP[19] Reserved
307 * MPP[20] PCI clock 0
308 * MPP[21] PCI clock 1
309 * MPP[22] USB 0 over current
310 * MPP[23-25] Reserved
311 */
312 orion_write(MPP_0_7_CTRL, 0x3);
313 orion_write(MPP_8_15_CTRL, 0x55550000);
314 orion_write(MPP_16_19_CTRL, 0x5500);
315 orion_gpio_set_valid_pins(0x3cc0fff);
316
317 /* register ts209 specific power-off method */
318 pm_power_off = qnap_ts209_power_off;
319
320 platform_add_devices(qnap_ts209_devices,
321 ARRAY_SIZE(qnap_ts209_devices));
322 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
323 orion_eth_init(&qnap_ts209_eth_data);
324}
325
326MACHINE_START(TS209, "QNAP TS-109/TS-209")
327 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
328 .phys_io = ORION_REGS_BASE,
329 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
330 .boot_params = 0x00000100,
331 .init_machine = qnap_ts209_init,
332 .map_io = orion_map_io,
333 .init_irq = orion_init_irq,
334 .timer = &orion_timer,
335MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 20:50:20 -0500