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-rw-r--r--arch/arm/mach-orion5x/Makefile2
-rw-r--r--arch/arm/mach-orion5x/common.c1
-rw-r--r--arch/arm/mach-orion5x/common.h7
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c174
-rw-r--r--arch/arm/mach-orion5x/gpio.c231
-rw-r--r--arch/arm/mach-orion5x/include/mach/dma.h1
-rw-r--r--arch/arm/mach-orion5x/include/mach/gpio.h29
-rw-r--r--arch/arm/mach-orion5x/include/mach/io.h7
-rw-r--r--arch/arm/mach-orion5x/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-orion5x/include/mach/memory.h4
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h9
-rw-r--r--arch/arm/mach-orion5x/irq.c183
-rw-r--r--arch/arm/mach-orion5x/mpp.c6
13 files changed, 197 insertions, 461 deletions
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 3d4a1bc12355..edc38e2c856f 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,4 +1,4 @@
1obj-y += common.o addr-map.o pci.o gpio.o irq.o mpp.o 1obj-y += common.o addr-map.o pci.o irq.o mpp.o
2obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o 2obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
3obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o 3obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
4obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o 4obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 437065c25c9c..0a623379789f 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -72,6 +72,7 @@ void __init orion5x_map_io(void)
72 ****************************************************************************/ 72 ****************************************************************************/
73static struct orion_ehci_data orion5x_ehci_data = { 73static struct orion_ehci_data orion5x_ehci_data = {
74 .dram = &orion5x_mbus_dram_info, 74 .dram = &orion5x_mbus_dram_info,
75 .phy_version = EHCI_PHY_ORION,
75}; 76};
76 77
77static u64 ehci_dmamask = 0xffffffffUL; 78static u64 ehci_dmamask = 0xffffffffUL;
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index a000c7c6ee96..798b9a5e3da9 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -51,13 +51,6 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
51struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); 51struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
52int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); 52int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
53 53
54/*
55 * Valid GPIO pins according to MPP setup, used by machine-setup.
56 * (/mach-orion/gpio.c).
57 */
58void orion5x_gpio_set_valid(unsigned pin, int valid);
59void gpio_display(void); /* debug */
60
61struct machine_desc; 54struct machine_desc;
62struct meminfo; 55struct meminfo;
63struct tag; 56struct tag;
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 3e66098340a5..0722d6510df1 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -21,6 +21,7 @@
21#include <linux/gpio_keys.h> 21#include <linux/gpio_keys.h>
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/i2c.h> 23#include <linux/i2c.h>
24#include <linux/ata_platform.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25#include <asm/gpio.h> 26#include <asm/gpio.h>
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
@@ -64,9 +65,21 @@ static struct hw_pci dns323_pci __initdata = {
64 .map_irq = dns323_pci_map_irq, 65 .map_irq = dns323_pci_map_irq,
65}; 66};
66 67
68static int __init dns323_dev_id(void)
69{
70 u32 dev, rev;
71
72 orion5x_pcie_id(&dev, &rev);
73
74 return dev;
75}
76
67static int __init dns323_pci_init(void) 77static int __init dns323_pci_init(void)
68{ 78{
69 if (machine_is_dns323()) 79 /* The 5182 doesn't really use it's PCI bus, and initialising PCI
80 * gets in the way of initialising the SATA controller.
81 */
82 if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID)
70 pci_common_init(&dns323_pci); 83 pci_common_init(&dns323_pci);
71 84
72 return 0; 85 return 0;
@@ -75,14 +88,6 @@ static int __init dns323_pci_init(void)
75subsys_initcall(dns323_pci_init); 88subsys_initcall(dns323_pci_init);
76 89
77/**************************************************************************** 90/****************************************************************************
78 * Ethernet
79 */
80
81static struct mv643xx_eth_platform_data dns323_eth_data = {
82 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
83};
84
85/****************************************************************************
86 * 8MiB NOR flash (Spansion S29GL064M90TFIR4) 91 * 8MiB NOR flash (Spansion S29GL064M90TFIR4)
87 * 92 *
88 * Layout as used by D-Link: 93 * Layout as used by D-Link:
@@ -143,6 +148,90 @@ static struct platform_device dns323_nor_flash = {
143}; 148};
144 149
145/**************************************************************************** 150/****************************************************************************
151 * Ethernet
152 */
153
154static struct mv643xx_eth_platform_data dns323_eth_data = {
155 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
156};
157
158/* dns323_parse_hex_*() taken from tsx09-common.c; should a common copy of these
159 * functions be kept somewhere?
160 */
161static int __init dns323_parse_hex_nibble(char n)
162{
163 if (n >= '0' && n <= '9')
164 return n - '0';
165
166 if (n >= 'A' && n <= 'F')
167 return n - 'A' + 10;
168
169 if (n >= 'a' && n <= 'f')
170 return n - 'a' + 10;
171
172 return -1;
173}
174
175static int __init dns323_parse_hex_byte(const char *b)
176{
177 int hi;
178 int lo;
179
180 hi = dns323_parse_hex_nibble(b[0]);
181 lo = dns323_parse_hex_nibble(b[1]);
182
183 if (hi < 0 || lo < 0)
184 return -1;
185
186 return (hi << 4) | lo;
187}
188
189static int __init dns323_read_mac_addr(void)
190{
191 u_int8_t addr[6];
192 int i;
193 char *mac_page;
194
195 /* MAC address is stored as a regular ol' string in /dev/mtdblock4
196 * (0x007d0000-0x00800000) starting at offset 196480 (0x2ff80).
197 */
198 mac_page = ioremap(DNS323_NOR_BOOT_BASE + 0x7d0000 + 196480, 1024);
199 if (!mac_page)
200 return -ENOMEM;
201
202 /* Sanity check the string we're looking at */
203 for (i = 0; i < 5; i++) {
204 if (*(mac_page + (i * 3) + 2) != ':') {
205 goto error_fail;
206 }
207 }
208
209 for (i = 0; i < 6; i++) {
210 int byte;
211
212 byte = dns323_parse_hex_byte(mac_page + (i * 3));
213 if (byte < 0) {
214 goto error_fail;
215 }
216
217 addr[i] = byte;
218 }
219
220 iounmap(mac_page);
221 printk("DNS323: Found ethernet MAC address: ");
222 for (i = 0; i < 6; i++)
223 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
224
225 memcpy(dns323_eth_data.mac_addr, addr, 6);
226
227 return 0;
228
229error_fail:
230 iounmap(mac_page);
231 return -EINVAL;
232}
233
234/****************************************************************************
146 * GPIO LEDs (simple - doesn't use hardware blinking support) 235 * GPIO LEDs (simple - doesn't use hardware blinking support)
147 */ 236 */
148 237
@@ -207,10 +296,17 @@ static struct platform_device dns323_button_device = {
207 }, 296 },
208}; 297};
209 298
299/*****************************************************************************
300 * SATA
301 */
302static struct mv_sata_platform_data dns323_sata_data = {
303 .n_ports = 2,
304};
305
210/**************************************************************************** 306/****************************************************************************
211 * General Setup 307 * General Setup
212 */ 308 */
213static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = { 309static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
214 { 0, MPP_PCIE_RST_OUTn }, 310 { 0, MPP_PCIE_RST_OUTn },
215 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 311 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
216 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 312 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
@@ -234,6 +330,30 @@ static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = {
234 { -1 }, 330 { -1 },
235}; 331};
236 332
333static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
334 { 0, MPP_UNUSED },
335 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
336 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
337 { 3, MPP_UNUSED },
338 { 4, MPP_GPIO }, /* power button LED */
339 { 5, MPP_GPIO }, /* power button LED */
340 { 6, MPP_GPIO }, /* GMT G751-2f overtemp */
341 { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */
342 { 8, MPP_GPIO }, /* triggers power off */
343 { 9, MPP_GPIO }, /* power button switch */
344 { 10, MPP_GPIO }, /* reset button switch */
345 { 11, MPP_UNUSED },
346 { 12, MPP_SATA_LED },
347 { 13, MPP_SATA_LED },
348 { 14, MPP_SATA_LED },
349 { 15, MPP_SATA_LED },
350 { 16, MPP_UNUSED },
351 { 17, MPP_UNUSED },
352 { 18, MPP_UNUSED },
353 { 19, MPP_UNUSED },
354 { -1 },
355};
356
237/* 357/*
238 * On the DNS-323 the following devices are attached via I2C: 358 * On the DNS-323 the following devices are attached via I2C:
239 * 359 *
@@ -264,16 +384,15 @@ static void __init dns323_init(void)
264 /* Setup basic Orion functions. Need to be called early. */ 384 /* Setup basic Orion functions. Need to be called early. */
265 orion5x_init(); 385 orion5x_init();
266 386
267 orion5x_mpp_conf(dns323_mpp_modes); 387 /* Just to be tricky, the 5182 has a completely different
268 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ 388 * set of MPP modes to the 5181.
269
270 /*
271 * Configure peripherals.
272 */ 389 */
273 orion5x_ehci0_init(); 390 if (dns323_dev_id() == MV88F5182_DEV_ID)
274 orion5x_eth_init(&dns323_eth_data); 391 orion5x_mpp_conf(dns323_mv88f5182_mpp_modes);
275 orion5x_i2c_init(); 392 else {
276 orion5x_uart0_init(); 393 orion5x_mpp_conf(dns323_mv88f5181_mpp_modes);
394 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
395 }
277 396
278 /* setup flash mapping 397 /* setup flash mapping
279 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 398 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
@@ -288,6 +407,23 @@ static void __init dns323_init(void)
288 i2c_register_board_info(0, dns323_i2c_devices, 407 i2c_register_board_info(0, dns323_i2c_devices,
289 ARRAY_SIZE(dns323_i2c_devices)); 408 ARRAY_SIZE(dns323_i2c_devices));
290 409
410 /*
411 * Configure peripherals.
412 */
413 if (dns323_read_mac_addr() < 0)
414 printk("DNS323: Failed to read MAC address\n");
415
416 orion5x_ehci0_init();
417 orion5x_eth_init(&dns323_eth_data);
418 orion5x_i2c_init();
419 orion5x_uart0_init();
420
421 /* The 5182 has it's SATA controller on-chip, and needs it's own little
422 * init routine.
423 */
424 if (dns323_dev_id() == MV88F5182_DEV_ID)
425 orion5x_sata_init(&dns323_sata_data);
426
291 /* register dns323 specific power-off method */ 427 /* register dns323 specific power-off method */
292 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || 428 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
293 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) 429 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c
deleted file mode 100644
index f99d08811e5a..000000000000
--- a/arch/arm/mach-orion5x/gpio.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * arch/arm/mach-orion5x/gpio.c
3 *
4 * GPIO functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <asm/gpio.h>
20#include <mach/orion5x.h>
21#include "common.h"
22
23static DEFINE_SPINLOCK(gpio_lock);
24static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
25static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */
26
27void __init orion5x_gpio_set_valid(unsigned pin, int valid)
28{
29 if (valid)
30 __set_bit(pin, gpio_valid);
31 else
32 __clear_bit(pin, gpio_valid);
33}
34
35/*
36 * GENERIC_GPIO primitives
37 */
38int gpio_direction_input(unsigned pin)
39{
40 unsigned long flags;
41
42 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
43 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
44 return -EINVAL;
45 }
46
47 spin_lock_irqsave(&gpio_lock, flags);
48
49 /*
50 * Some callers might have not used the gpio_request(),
51 * so flag this pin as requested now.
52 */
53 if (!gpio_label[pin])
54 gpio_label[pin] = "?";
55
56 orion5x_setbits(GPIO_IO_CONF, 1 << pin);
57
58 spin_unlock_irqrestore(&gpio_lock, flags);
59 return 0;
60}
61EXPORT_SYMBOL(gpio_direction_input);
62
63int gpio_direction_output(unsigned pin, int value)
64{
65 unsigned long flags;
66 int mask;
67
68 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
69 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
70 return -EINVAL;
71 }
72
73 spin_lock_irqsave(&gpio_lock, flags);
74
75 /*
76 * Some callers might have not used the gpio_request(),
77 * so flag this pin as requested now.
78 */
79 if (!gpio_label[pin])
80 gpio_label[pin] = "?";
81
82 mask = 1 << pin;
83 orion5x_clrbits(GPIO_BLINK_EN, mask);
84 if (value)
85 orion5x_setbits(GPIO_OUT, mask);
86 else
87 orion5x_clrbits(GPIO_OUT, mask);
88 orion5x_clrbits(GPIO_IO_CONF, mask);
89
90 spin_unlock_irqrestore(&gpio_lock, flags);
91 return 0;
92}
93EXPORT_SYMBOL(gpio_direction_output);
94
95int gpio_get_value(unsigned pin)
96{
97 int val, mask = 1 << pin;
98
99 if (readl(GPIO_IO_CONF) & mask)
100 val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL);
101 else
102 val = readl(GPIO_OUT);
103
104 return val & mask;
105}
106EXPORT_SYMBOL(gpio_get_value);
107
108void gpio_set_value(unsigned pin, int value)
109{
110 unsigned long flags;
111 int mask = 1 << pin;
112
113 spin_lock_irqsave(&gpio_lock, flags);
114
115 orion5x_clrbits(GPIO_BLINK_EN, mask);
116 if (value)
117 orion5x_setbits(GPIO_OUT, mask);
118 else
119 orion5x_clrbits(GPIO_OUT, mask);
120
121 spin_unlock_irqrestore(&gpio_lock, flags);
122}
123EXPORT_SYMBOL(gpio_set_value);
124
125void orion5x_gpio_set_blink(unsigned pin, int blink)
126{
127 unsigned long flags;
128 int mask = 1 << pin;
129
130 spin_lock_irqsave(&gpio_lock, flags);
131
132 orion5x_clrbits(GPIO_OUT, mask);
133 if (blink)
134 orion5x_setbits(GPIO_BLINK_EN, mask);
135 else
136 orion5x_clrbits(GPIO_BLINK_EN, mask);
137
138 spin_unlock_irqrestore(&gpio_lock, flags);
139}
140EXPORT_SYMBOL(orion5x_gpio_set_blink);
141
142int gpio_request(unsigned pin, const char *label)
143{
144 int ret = 0;
145 unsigned long flags;
146
147 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
148 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
149 return -EINVAL;
150 }
151
152 spin_lock_irqsave(&gpio_lock, flags);
153
154 if (gpio_label[pin]) {
155 pr_debug("%s: GPIO %d already used as %s\n",
156 __func__, pin, gpio_label[pin]);
157 ret = -EBUSY;
158 } else
159 gpio_label[pin] = label ? label : "?";
160
161 spin_unlock_irqrestore(&gpio_lock, flags);
162 return ret;
163}
164EXPORT_SYMBOL(gpio_request);
165
166void gpio_free(unsigned pin)
167{
168 might_sleep();
169
170 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
171 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
172 return;
173 }
174
175 if (!gpio_label[pin])
176 pr_warning("%s: GPIO %d already freed\n", __func__, pin);
177 else
178 gpio_label[pin] = NULL;
179}
180EXPORT_SYMBOL(gpio_free);
181
182/* Debug helper */
183void gpio_display(void)
184{
185 int i;
186
187 for (i = 0; i < GPIO_MAX; i++) {
188 printk(KERN_DEBUG "Pin-%d: ", i);
189
190 if (!test_bit(i, gpio_valid)) {
191 printk("non-GPIO\n");
192 } else if (!gpio_label[i]) {
193 printk("GPIO, free\n");
194 } else {
195 printk("GPIO, used by %s, ", gpio_label[i]);
196 if (readl(GPIO_IO_CONF) & (1 << i)) {
197 printk("input, active %s, level %s, edge %s\n",
198 ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
199 ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
200 ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
201 } else {
202 printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1);
203 }
204 }
205 }
206
207 printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
208 MPP_0_7_CTRL, readl(MPP_0_7_CTRL));
209 printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
210 MPP_8_15_CTRL, readl(MPP_8_15_CTRL));
211 printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
212 MPP_16_19_CTRL, readl(MPP_16_19_CTRL));
213 printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
214 MPP_DEV_CTRL, readl(MPP_DEV_CTRL));
215 printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
216 GPIO_OUT, readl(GPIO_OUT));
217 printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
218 GPIO_IO_CONF, readl(GPIO_IO_CONF));
219 printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
220 GPIO_BLINK_EN, readl(GPIO_BLINK_EN));
221 printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
222 GPIO_IN_POL, readl(GPIO_IN_POL));
223 printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
224 GPIO_DATA_IN, readl(GPIO_DATA_IN));
225 printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
226 GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK));
227 printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
228 GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE));
229 printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
230 GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK));
231}
diff --git a/arch/arm/mach-orion5x/include/mach/dma.h b/arch/arm/mach-orion5x/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-orion5x/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1/* empty */
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
index 65dc136a86f7..d8182e87ac16 100644
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ b/arch/arm/mach-orion5x/include/mach/gpio.h
@@ -2,18 +2,26 @@
2 * arch/arm/mach-orion5x/include/mach/gpio.h 2 * arch/arm/mach-orion5x/include/mach/gpio.h
3 * 3 *
4 * This file is licensed under the terms of the GNU General Public 4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any 5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied. 6 * warranty of any kind, whether express or implied.
7 */ 7 */
8 8
9extern int gpio_request(unsigned pin, const char *label); 9#ifndef __ASM_ARCH_GPIO_H
10extern void gpio_free(unsigned pin); 10#define __ASM_ARCH_GPIO_H
11extern int gpio_direction_input(unsigned pin); 11
12extern int gpio_direction_output(unsigned pin, int value); 12#include <mach/irqs.h>
13extern int gpio_get_value(unsigned pin); 13#include <plat/gpio.h>
14extern void gpio_set_value(unsigned pin, int value); 14#include <asm-generic/gpio.h> /* cansleep wrappers */
15extern void orion5x_gpio_set_blink(unsigned pin, int blink); 15
16extern void gpio_display(void); /* debug */ 16#define GPIO_MAX 32
17#define GPIO_OUT(pin) ORION5X_DEV_BUS_REG(0x100)
18#define GPIO_IO_CONF(pin) ORION5X_DEV_BUS_REG(0x104)
19#define GPIO_BLINK_EN(pin) ORION5X_DEV_BUS_REG(0x108)
20#define GPIO_IN_POL(pin) ORION5X_DEV_BUS_REG(0x10c)
21#define GPIO_DATA_IN(pin) ORION5X_DEV_BUS_REG(0x110)
22#define GPIO_EDGE_CAUSE(pin) ORION5X_DEV_BUS_REG(0x114)
23#define GPIO_EDGE_MASK(pin) ORION5X_DEV_BUS_REG(0x118)
24#define GPIO_LEVEL_MASK(pin) ORION5X_DEV_BUS_REG(0x11c)
17 25
18static inline int gpio_to_irq(int pin) 26static inline int gpio_to_irq(int pin)
19{ 27{
@@ -25,4 +33,5 @@ static inline int irq_to_gpio(int irq)
25 return irq - IRQ_ORION5X_GPIO_START; 33 return irq - IRQ_ORION5X_GPIO_START;
26} 34}
27 35
28#include <asm-generic/gpio.h> /* cansleep wrappers */ 36
37#endif
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index f24b2513f7f3..c47b033bd999 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -38,14 +38,9 @@ __arch_iounmap(void __iomem *addr)
38 __iounmap(addr); 38 __iounmap(addr);
39} 39}
40 40
41static inline void __iomem *__io(unsigned long addr)
42{
43 return (void __iomem *)addr;
44}
45
46#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) 41#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
47#define __arch_iounmap(a) __arch_iounmap(a) 42#define __arch_iounmap(a) __arch_iounmap(a)
48#define __io(a) __io(a) 43#define __io(a) __typesafe_io(a)
49#define __mem_pci(a) (a) 44#define __mem_pci(a) (a)
50 45
51 46
diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h
index d5b0fbf6b965..a6fa9d8f12d8 100644
--- a/arch/arm/mach-orion5x/include/mach/irqs.h
+++ b/arch/arm/mach-orion5x/include/mach/irqs.h
@@ -13,8 +13,6 @@
13#ifndef __ASM_ARCH_IRQS_H 13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H 14#define __ASM_ARCH_IRQS_H
15 15
16#include "orion5x.h" /* need GPIO_MAX */
17
18/* 16/*
19 * Orion Main Interrupt Controller 17 * Orion Main Interrupt Controller
20 */ 18 */
@@ -54,7 +52,7 @@
54 * Orion General Purpose Pins 52 * Orion General Purpose Pins
55 */ 53 */
56#define IRQ_ORION5X_GPIO_START 32 54#define IRQ_ORION5X_GPIO_START 32
57#define NR_GPIO_IRQS GPIO_MAX 55#define NR_GPIO_IRQS 32
58 56
59#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) 57#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
60 58
diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h
index 54dd76b013f2..52a2955d0f87 100644
--- a/arch/arm/mach-orion5x/include/mach/memory.h
+++ b/arch/arm/mach-orion5x/include/mach/memory.h
@@ -9,8 +9,4 @@
9 9
10#define PHYS_OFFSET UL(0x00000000) 10#define PHYS_OFFSET UL(0x00000000)
11 11
12#define __virt_to_bus(x) __virt_to_phys(x)
13#define __bus_to_virt(x) __phys_to_virt(x)
14
15
16#endif 12#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 9f5ce1ce5840..67bda31406dd 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -134,14 +134,6 @@
134#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) 134#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
135#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) 135#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
136#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) 136#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
137#define GPIO_OUT ORION5X_DEV_BUS_REG(0x100)
138#define GPIO_IO_CONF ORION5X_DEV_BUS_REG(0x104)
139#define GPIO_BLINK_EN ORION5X_DEV_BUS_REG(0x108)
140#define GPIO_IN_POL ORION5X_DEV_BUS_REG(0x10c)
141#define GPIO_DATA_IN ORION5X_DEV_BUS_REG(0x110)
142#define GPIO_EDGE_CAUSE ORION5X_DEV_BUS_REG(0x114)
143#define GPIO_EDGE_MASK ORION5X_DEV_BUS_REG(0x118)
144#define GPIO_LEVEL_MASK ORION5X_DEV_BUS_REG(0x11c)
145#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) 137#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
146#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) 138#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
147#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) 139#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
@@ -149,7 +141,6 @@
149#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) 141#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
150#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) 142#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
151#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) 143#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
152#define GPIO_MAX 32
153 144
154/*************************************************************************** 145/***************************************************************************
155 * Orion CPU Bridge Registers 146 * Orion CPU Bridge Registers
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 632a36f5cf14..0caae43301e5 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -19,193 +19,38 @@
19#include <plat/irq.h> 19#include <plat/irq.h>
20#include "common.h" 20#include "common.h"
21 21
22/***************************************************************************** 22static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
23 * Orion GPIO IRQ
24 *
25 * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
26 * value of the line or the opposite value.
27 *
28 * Level IRQ handlers: DATA_IN is used directly as cause register.
29 * Interrupt are masked by LEVEL_MASK registers.
30 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
31 * Interrupt are masked by EDGE_MASK registers.
32 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
33 * the polarity to catch the next line transaction.
34 * This is a race condition that might not perfectly
35 * work on some use cases.
36 *
37 * Every eight GPIO lines are grouped (OR'ed) before going up to main
38 * cause register.
39 *
40 * EDGE cause mask
41 * data-in /--------| |-----| |----\
42 * -----| |----- ---- to main cause reg
43 * X \----------------| |----/
44 * polarity LEVEL mask
45 *
46 ****************************************************************************/
47static void orion5x_gpio_irq_ack(u32 irq)
48{
49 int pin = irq_to_gpio(irq);
50 if (irq_desc[irq].status & IRQ_LEVEL)
51 /*
52 * Mask bit for level interrupt
53 */
54 orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
55 else
56 /*
57 * Clear casue bit for egde interrupt
58 */
59 orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
60}
61
62static void orion5x_gpio_irq_mask(u32 irq)
63{
64 int pin = irq_to_gpio(irq);
65 if (irq_desc[irq].status & IRQ_LEVEL)
66 orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
67 else
68 orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
69}
70
71static void orion5x_gpio_irq_unmask(u32 irq)
72{ 23{
73 int pin = irq_to_gpio(irq);
74 if (irq_desc[irq].status & IRQ_LEVEL)
75 orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
76 else
77 orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
78}
79
80static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
81{
82 int pin = irq_to_gpio(irq);
83 struct irq_desc *desc;
84
85 if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) {
86 printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
87 "(irq %d, pin %d).\n", irq, pin);
88 return -EINVAL;
89 }
90
91 desc = irq_desc + irq;
92
93 switch (type) {
94 case IRQ_TYPE_LEVEL_HIGH:
95 desc->handle_irq = handle_level_irq;
96 desc->status |= IRQ_LEVEL;
97 orion5x_clrbits(GPIO_IN_POL, (1 << pin));
98 break;
99 case IRQ_TYPE_LEVEL_LOW:
100 desc->handle_irq = handle_level_irq;
101 desc->status |= IRQ_LEVEL;
102 orion5x_setbits(GPIO_IN_POL, (1 << pin));
103 break;
104 case IRQ_TYPE_EDGE_RISING:
105 desc->handle_irq = handle_edge_irq;
106 desc->status &= ~IRQ_LEVEL;
107 orion5x_clrbits(GPIO_IN_POL, (1 << pin));
108 break;
109 case IRQ_TYPE_EDGE_FALLING:
110 desc->handle_irq = handle_edge_irq;
111 desc->status &= ~IRQ_LEVEL;
112 orion5x_setbits(GPIO_IN_POL, (1 << pin));
113 break;
114 case IRQ_TYPE_EDGE_BOTH:
115 desc->handle_irq = handle_edge_irq;
116 desc->status &= ~IRQ_LEVEL;
117 /*
118 * set initial polarity based on current input level
119 */
120 if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN))
121 & (1 << pin))
122 orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
123 else
124 orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
125
126 break;
127 default:
128 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
129 return -EINVAL;
130 }
131
132 desc->status &= ~IRQ_TYPE_SENSE_MASK;
133 desc->status |= type & IRQ_TYPE_SENSE_MASK;
134
135 return 0;
136}
137
138static struct irq_chip orion5x_gpio_irq_chip = {
139 .name = "Orion-IRQ-GPIO",
140 .ack = orion5x_gpio_irq_ack,
141 .mask = orion5x_gpio_irq_mask,
142 .unmask = orion5x_gpio_irq_unmask,
143 .set_type = orion5x_gpio_set_irq_type,
144};
145
146static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
147{
148 u32 cause, offs, pin;
149
150 BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); 24 BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
151 offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
152 cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) |
153 (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK));
154 25
155 for (pin = offs; pin < offs + 8; pin++) { 26 orion_gpio_irq_handler((irq - IRQ_ORION5X_GPIO_0_7) << 3);
156 if (cause & (1 << pin)) {
157 irq = gpio_to_irq(pin);
158 desc = irq_desc + irq;
159 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
160 /* Swap polarity (race with GPIO line) */
161 u32 polarity = readl(GPIO_IN_POL);
162 polarity ^= 1 << pin;
163 writel(polarity, GPIO_IN_POL);
164 }
165 generic_handle_irq(irq);
166 }
167 }
168} 27}
169 28
170static void __init orion5x_init_gpio_irq(void) 29void __init orion5x_init_irq(void)
171{ 30{
172 int i; 31 int i;
173 struct irq_desc *desc; 32
33 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
174 34
175 /* 35 /*
176 * Mask and clear GPIO IRQ interrupts 36 * Mask and clear GPIO IRQ interrupts
177 */ 37 */
178 writel(0x0, GPIO_LEVEL_MASK); 38 writel(0x0, GPIO_LEVEL_MASK(0));
179 writel(0x0, GPIO_EDGE_MASK); 39 writel(0x0, GPIO_EDGE_MASK(0));
180 writel(0x0, GPIO_EDGE_CAUSE); 40 writel(0x0, GPIO_EDGE_CAUSE(0));
181 41
182 /* 42 /*
183 * Register chained level handlers for GPIO IRQs by default. 43 * Register chained level handlers for GPIO IRQs by default.
184 * User can use set_type() if he wants to use edge types handlers. 44 * User can use set_type() if he wants to use edge types handlers.
185 */ 45 */
186 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { 46 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
187 set_irq_chip(i, &orion5x_gpio_irq_chip); 47 set_irq_chip(i, &orion_gpio_irq_level_chip);
188 set_irq_handler(i, handle_level_irq); 48 set_irq_handler(i, handle_level_irq);
189 desc = irq_desc + i; 49 irq_desc[i].status |= IRQ_LEVEL;
190 desc->status |= IRQ_LEVEL;
191 set_irq_flags(i, IRQF_VALID); 50 set_irq_flags(i, IRQF_VALID);
192 } 51 }
193 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler); 52 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
194 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler); 53 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
195 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler); 54 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
196 set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler); 55 set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
197}
198
199/*****************************************************************************
200 * Orion Main IRQ
201 ****************************************************************************/
202static void __init orion5x_init_main_irq(void)
203{
204 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
205}
206
207void __init orion5x_init_irq(void)
208{
209 orion5x_init_main_irq();
210 orion5x_init_gpio_irq();
211} 56}
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 640ea2a3fc6c..e23a3f91d6c6 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/gpio.h>
15#include <mach/hardware.h> 16#include <mach/hardware.h>
16#include "common.h" 17#include "common.h"
17#include "mpp.h" 18#include "mpp.h"
@@ -152,7 +153,10 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
152 *reg &= ~(0xf << shift); 153 *reg &= ~(0xf << shift);
153 *reg |= (num_type & 0xf) << shift; 154 *reg |= (num_type & 0xf) << shift;
154 155
155 orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); 156 if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182()))
157 orion_gpio_set_unused(mode->mpp);
158
159 orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
156 160
157 mode++; 161 mode++;
158 } 162 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 00:39:35 -0500