11 files changed, 142 insertions, 10 deletions

diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index c14d12137276..6f3f77d031d0 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
+#include <linux/errno.h>
 #include <mach/hardware.h>
 #include "common.h"
 
@@ -44,6 +45,7 @@
 #define TARGET_DEV_BUS          1
 #define TARGET_PCI              3
 #define TARGET_PCIE             4
+#define TARGET_SRAM             9
 #define ATTR_PCIE_MEM           0x59
 #define ATTR_PCIE_IO            0x51
 #define ATTR_PCIE_WA            0x79
@@ -53,6 +55,7 @@
 #define ATTR_DEV_CS1            0x1d
 #define ATTR_DEV_CS2            0x1b
 #define ATTR_DEV_BOOT           0xf
+#define ATTR_SRAM               0x0
 
 /*
  * Helpers to get DDR bank info
@@ -87,13 +90,13 @@ static int __init orion5x_cpu_win_can_remap(int win)
         return 0;
 }
 
-static void __init setup_cpu_win(int win, u32 base, u32 size,
+static int __init setup_cpu_win(int win, u32 base, u32 size,
                                  u8 target, u8 attr, int remap)
 {
         if (win >= 8) {
                 printk(KERN_ERR "setup_cpu_win: trying to allocate "
                                 "window %d\n", win);
-                return;
+                return -ENOSPC;
         }
 
         writel(base & 0xffff0000, CPU_WIN_BASE(win));
@@ -107,6 +110,7 @@ static void __init setup_cpu_win(int win, u32 base, u32 size,
                 writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
                 writel(0, CPU_WIN_REMAP_HI(win));
         }
+        return 0;
 }
 
 void __init orion5x_setup_cpu_mbus_bridge(void)
@@ -193,3 +197,9 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
         setup_cpu_win(win_alloc_count++, base, size,
                       TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
+
+int __init orion5x_setup_sram_win(void)
+{
+        return setup_cpu_win(win_alloc_count, ORION5X_SRAM_PHYS_BASE,
+                        ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
+}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b1c7778d9f96..eafcc49009ea 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -31,7 +31,7 @@
 #include <plat/ehci-orion.h>
 #include <plat/mv_xor.h>
 #include <plat/orion_nand.h>
-#include <plat/orion5x_wdt.h>
+#include <plat/orion_wdt.h>
 #include <plat/time.h>
 #include "common.h"
 
@@ -536,16 +536,52 @@ void __init orion5x_xor_init(void)
         platform_device_register(&orion5x_xor1_channel);
 }
 
+static struct resource orion5x_crypto_res[] = {
+        {
+                .name   = "regs",
+                .start  = ORION5X_CRYPTO_PHYS_BASE,
+                .end    = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sram",
+                .start  = ORION5X_SRAM_PHYS_BASE,
+                .end    = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "crypto interrupt",
+                .start  = IRQ_ORION5X_CESA,
+                .end    = IRQ_ORION5X_CESA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion5x_crypto_device = {
+        .name           = "mv_crypto",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(orion5x_crypto_res),
+        .resource       = orion5x_crypto_res,
+};
+
+int __init orion5x_crypto_init(void)
+{
+        int ret;
+
+        ret = orion5x_setup_sram_win();
+        if (ret)
+                return ret;
+
+        return platform_device_register(&orion5x_crypto_device);
+}
 
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static struct orion5x_wdt_platform_data orion5x_wdt_data = {
+static struct orion_wdt_platform_data orion5x_wdt_data = {
         .tclk                   = 0,
 };
 
 static struct platform_device orion5x_wdt_device = {
-        .name           = "orion5x_wdt",
+        .name           = "orion_wdt",
         .id             = -1,
         .dev            = {
                 .platform_data  = &orion5x_wdt_data,
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 798b9a5e3da9..de483e83edd7 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -26,6 +26,7 @@ void orion5x_setup_dev0_win(u32 base, u32 size);
 void orion5x_setup_dev1_win(u32 base, u32 size);
 void orion5x_setup_dev2_win(u32 base, u32 size);
 void orion5x_setup_pcie_wa_win(u32 base, u32 size);
+int orion5x_setup_sram_win(void);
 
 void orion5x_ehci0_init(void);
 void orion5x_ehci1_init(void);
@@ -37,6 +38,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
+int orion5x_crypto_init(void);
 
 /*
  * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index be896e59d3e7..5c9744cd8ef6 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -17,8 +17,8 @@
 
 #define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE | 0x104)
 
-#define CPU_RESET_MASK          (ORION5X_BRIDGE_VIRT_BASE | 0x108)
-#define WDT_RESET               0x0002
+#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define WDT_RESET_OUT_EN        0x0002
 
 #define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
 
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 377a773ae53f..2d8766570531 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -24,6 +24,7 @@
  * f1000000     on-chip peripheral registers
  * f2000000     PCIe I/O space
  * f2100000     PCI I/O space
+ * f2200000     SRAM dedicated for the crypto unit
  * f4000000     device bus mappings (boot)
  * fa000000     device bus mappings (cs0)
  * fa800000     device bus mappings (cs2)
@@ -49,6 +50,9 @@
 #define ORION5X_PCI_IO_BUS_BASE         0x00100000
 #define ORION5X_PCI_IO_SIZE             SZ_1M
 
+#define ORION5X_SRAM_PHYS_BASE          (0xf2200000)
+#define ORION5X_SRAM_SIZE               SZ_8K
+
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
 #define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
@@ -94,6 +98,8 @@
 #define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
 #define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
 
+#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x90000)
+
 #define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
 #define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
 
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index e912490fff23..60e734c10458 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -23,7 +23,7 @@ static inline void arch_reset(char mode, const char *cmd)
         /*
          * Enable and issue soft reset
          */
-        orion5x_setbits(CPU_RESET_MASK, (1 << 2));
+        orion5x_setbits(RSTOUTn_MASK, (1 << 2));
         orion5x_setbits(CPU_SOFT_RESET, 1);
 }
 
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index e23a3f91d6c6..bc4c3b9aaf83 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -124,6 +124,9 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
         u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
         u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
 
+        /* Initialize gpiolib. */
+        orion_gpio_init();
+
         while (mode->mpp >= 0) {
                 u32 *reg;
                 int num_type;
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 41e6d5033d54..61c086b66723 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -181,9 +181,9 @@ static void mss2_power_off(void)
         /*
          * Enable and issue soft reset
          */
-        reg = readl(CPU_RESET_MASK);
+        reg = readl(RSTOUTn_MASK);
         reg |= 1 << 2;
-        writel(reg, CPU_RESET_MASK);
+        writel(reg, RSTOUTn_MASK);
 
         reg = readl(CPU_SOFT_RESET);
         reg |= 1;
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
index 0f9cdf458952..37b3d4875291 100644
--- a/arch/arm/mach-orion5x/ts78xx-fpga.h
+++ b/arch/arm/mach-orion5x/ts78xx-fpga.h
@@ -25,6 +25,7 @@ struct fpga_devices {
         /* Technologic Systems */
         struct fpga_device      ts_rtc;
         struct fpga_device      ts_nand;
+        struct fpga_device      ts_rng;
 };
 
 struct ts78xx_fpga_data {
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 9a6b397f972d..5041d1bc26b1 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -17,6 +17,7 @@
 #include <linux/m48t86.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/timeriomem-rng.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -270,12 +271,57 @@ static void ts78xx_ts_nand_unload(void)
 }
 
 /*****************************************************************************
+ * HW RNG
+ ****************************************************************************/
+#define TS_RNG_DATA     (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
+
+static struct resource ts78xx_ts_rng_resource = {
+        .flags          = IORESOURCE_MEM,
+        .start          = TS_RNG_DATA,
+        .end            = TS_RNG_DATA + 4 - 1,
+};
+
+static struct timeriomem_rng_data ts78xx_ts_rng_data = {
+        .period         = 1000000, /* one second */
+};
+
+static struct platform_device ts78xx_ts_rng_device = {
+        .name           = "timeriomem_rng",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ts78xx_ts_rng_data,
+        },
+        .resource       = &ts78xx_ts_rng_resource,
+        .num_resources  = 1,
+};
+
+static int ts78xx_ts_rng_load(void)
+{
+        int rc;
+
+        if (ts78xx_fpga.supports.ts_rng.init == 0) {
+                rc = platform_device_register(&ts78xx_ts_rng_device);
+                if (!rc)
+                        ts78xx_fpga.supports.ts_rng.init = 1;
+        } else
+                rc = platform_device_add(&ts78xx_ts_rng_device);
+
+        return rc;
+};
+
+static void ts78xx_ts_rng_unload(void)
+{
+        platform_device_del(&ts78xx_ts_rng_device);
+}
+
+/*****************************************************************************
  * FPGA 'hotplug' support code
  ****************************************************************************/
 static void ts78xx_fpga_devices_zero_init(void)
 {
         ts78xx_fpga.supports.ts_rtc.init = 0;
         ts78xx_fpga.supports.ts_nand.init = 0;
+        ts78xx_fpga.supports.ts_rng.init = 0;
 }
 
 static void ts78xx_fpga_supports(void)
@@ -289,10 +335,12 @@ static void ts78xx_fpga_supports(void)
         case TS7800_REV_5:
                 ts78xx_fpga.supports.ts_rtc.present = 1;
                 ts78xx_fpga.supports.ts_nand.present = 1;
+                ts78xx_fpga.supports.ts_rng.present = 1;
                 break;
         default:
                 ts78xx_fpga.supports.ts_rtc.present = 0;
                 ts78xx_fpga.supports.ts_nand.present = 0;
+                ts78xx_fpga.supports.ts_rng.present = 0;
         }
 }
 
@@ -316,6 +364,14 @@ static int ts78xx_fpga_load_devices(void)
                 }
                 ret |= tmp;
         }
+        if (ts78xx_fpga.supports.ts_rng.present == 1) {
+                tmp = ts78xx_ts_rng_load();
+                if (tmp) {
+                        printk(KERN_INFO "TS-78xx: RNG not registered\n");
+                        ts78xx_fpga.supports.ts_rng.present = 0;
+                }
+                ret |= tmp;
+        }
 
         return ret;
 }
@@ -328,6 +384,8 @@ static int ts78xx_fpga_unload_devices(void)
                 ts78xx_ts_rtc_unload();
         if (ts78xx_fpga.supports.ts_nand.present == 1)
                 ts78xx_ts_nand_unload();
+        if (ts78xx_fpga.supports.ts_rng.present == 1)
+                ts78xx_ts_rng_unload();
 
         return ret;
 }
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 7ddc22c2bb54..69208217b220 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -15,6 +15,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ethtool.h>
+#include <net/dsa.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
@@ -97,6 +98,20 @@ static struct mv643xx_eth_platform_data wnr854t_eth_data = {
         .duplex         = DUPLEX_FULL,
 };
 
+static struct dsa_chip_data wnr854t_switch_chip_data = {
+        .port_names[0] = "lan3",
+        .port_names[1] = "lan4",
+        .port_names[2] = "wan",
+        .port_names[3] = "cpu",
+        .port_names[5] = "lan1",
+        .port_names[7] = "lan2",
+};
+
+static struct dsa_platform_data wnr854t_switch_plat_data = {
+        .nr_chips       = 1,
+        .chip           = &wnr854t_switch_chip_data,
+};
+
 static void __init wnr854t_init(void)
 {
         /*
@@ -110,6 +125,7 @@ static void __init wnr854t_init(void)
          * Configure peripherals.
          */
         orion5x_eth_init(&wnr854t_eth_data);
+        orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
         orion5x_uart0_init();
 
         orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE,