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Diffstat (limited to 'arch/arm/mach-orion5x/irq.c')
-rw-r--r--arch/arm/mach-orion5x/irq.c19
1 files changed, 2 insertions, 17 deletions
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index d7512b925a85..ed85891f8699 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -28,27 +28,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
28 28
29void __init orion5x_init_irq(void) 29void __init orion5x_init_irq(void)
30{ 30{
31 int i;
32
33 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); 31 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
34 32
35 /* 33 /*
36 * Mask and clear GPIO IRQ interrupts 34 * Initialize gpiolib for GPIOs 0-31.
37 */
38 writel(0x0, GPIO_LEVEL_MASK(0));
39 writel(0x0, GPIO_EDGE_MASK(0));
40 writel(0x0, GPIO_EDGE_CAUSE(0));
41
42 /*
43 * Register chained level handlers for GPIO IRQs by default.
44 * User can use set_type() if he wants to use edge types handlers.
45 */ 35 */
46 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { 36 orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
47 set_irq_chip(i, &orion_gpio_irq_chip);
48 set_irq_handler(i, handle_level_irq);
49 irq_desc[i].status |= IRQ_LEVEL;
50 set_irq_flags(i, IRQF_VALID);
51 }
52 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); 37 set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
53 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); 38 set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
54 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); 39 set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);