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Diffstat (limited to 'arch/arm/mach-orion5x/addr-map.c')
-rw-r--r--arch/arm/mach-orion5x/addr-map.c47
1 files changed, 0 insertions, 47 deletions
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 9608503d67f5..186f51ce7c11 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -81,17 +81,6 @@
81#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) 81#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
82#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) 82#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
83 83
84/*
85 * Gigabit Ethernet Address Decode Windows registers
86 */
87#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8))
88#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8))
89#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4))
90#define ETH_WIN_EN ORION5X_ETH_REG(0x290)
91#define ETH_WIN_PROT ORION5X_ETH_REG(0x294)
92#define ETH_MAX_WIN 6
93#define ETH_MAX_REMAP_WIN 4
94
95 84
96struct mbus_dram_target_info orion5x_mbus_dram_info; 85struct mbus_dram_target_info orion5x_mbus_dram_info;
97 86
@@ -202,39 +191,3 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
202{ 191{
203 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); 192 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
204} 193}
205
206void __init orion5x_setup_eth_wins(void)
207{
208 int i;
209
210 /*
211 * First, disable and clear windows
212 */
213 for (i = 0; i < ETH_MAX_WIN; i++) {
214 orion5x_write(ETH_WIN_BASE(i), 0);
215 orion5x_write(ETH_WIN_SIZE(i), 0);
216 orion5x_setbits(ETH_WIN_EN, 1 << i);
217 orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
218 if (i < ETH_MAX_REMAP_WIN)
219 orion5x_write(ETH_WIN_REMAP(i), 0);
220 }
221
222 /*
223 * Setup windows for DDR banks.
224 */
225 for (i = 0; i < DDR_MAX_CS; i++) {
226 u32 base, size;
227 size = orion5x_read(DDR_SIZE_CS(i));
228 base = orion5x_read(DDR_BASE_CS(i));
229 if (size & DDR_BANK_EN) {
230 base = DDR_REG_TO_BASE(base);
231 size = DDR_REG_TO_SIZE(size);
232 orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
233 orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
234 (ATTR_DDR_CS(i) << 8) |
235 TARGET_DDR);
236 orion5x_clrbits(ETH_WIN_EN, 1 << i);
237 orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
238 }
239 }
240}