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-rw-r--r--arch/arm/mach-orion/pci.c557
1 files changed, 0 insertions, 557 deletions
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c
deleted file mode 100644
index b109bb46681e..000000000000
--- a/arch/arm/mach-orion/pci.c
+++ /dev/null
@@ -1,557 +0,0 @@
1/*
2 * arch/arm/mach-orion/pci.c
3 *
4 * PCI and PCIE functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <asm/mach/pci.h>
16#include "common.h"
17
18/*****************************************************************************
19 * Orion has one PCIE controller and one PCI controller.
20 *
21 * Note1: The local PCIE bus number is '0'. The local PCI bus number
22 * follows the scanned PCIE bridged busses, if any.
23 *
24 * Note2: It is possible for PCI/PCIE agents to access many subsystem's
25 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
26 * device bus, Orion registers, etc. However this code only enable the
27 * access to DDR banks.
28 ****************************************************************************/
29
30
31/*****************************************************************************
32 * PCIE controller
33 ****************************************************************************/
34#define PCIE_CTRL ORION_PCIE_REG(0x1a00)
35#define PCIE_STAT ORION_PCIE_REG(0x1a04)
36#define PCIE_DEV_ID ORION_PCIE_REG(0x0000)
37#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004)
38#define PCIE_DEV_REV ORION_PCIE_REG(0x0008)
39#define PCIE_MASK ORION_PCIE_REG(0x1910)
40#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8)
41#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc)
42
43/*
44 * PCIE_STAT bits
45 */
46#define PCIE_STAT_LINK_DOWN 1
47#define PCIE_STAT_BUS_OFFS 8
48#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS)
49#define PCIE_STAT_DEV_OFFS 20
50#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS)
51
52/*
53 * PCIE_CONF_ADDR bits
54 */
55#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc))
56#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
57#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
58#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
59#define PCIE_CONF_ADDR_EN (1 << 31)
60
61/*
62 * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
63 * and then reading the PCIE_CONF_DATA register. Need to make sure these
64 * transactions are atomic.
65 */
66static DEFINE_SPINLOCK(orion_pcie_lock);
67
68void orion_pcie_id(u32 *dev, u32 *rev)
69{
70 *dev = orion_read(PCIE_DEV_ID) >> 16;
71 *rev = orion_read(PCIE_DEV_REV) & 0xff;
72}
73
74u32 orion_pcie_local_bus_nr(void)
75{
76 u32 stat = orion_read(PCIE_STAT);
77 return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
78}
79
80static u32 orion_pcie_local_dev_nr(void)
81{
82 u32 stat = orion_read(PCIE_STAT);
83 return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
84}
85
86static u32 orion_pcie_no_link(void)
87{
88 u32 stat = orion_read(PCIE_STAT);
89 return(stat & PCIE_STAT_LINK_DOWN);
90}
91
92static void orion_pcie_set_bus_nr(int nr)
93{
94 orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
95 orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
96}
97
98static void orion_pcie_master_slave_enable(void)
99{
100 orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
101 PCI_COMMAND_IO |
102 PCI_COMMAND_MEMORY);
103}
104
105static void orion_pcie_enable_interrupts(void)
106{
107 /*
108 * Enable interrupts lines
109 * INTA[24] INTB[25] INTC[26] INTD[27]
110 */
111 orion_setbits(PCIE_MASK, 0xf<<24);
112}
113
114static int orion_pcie_valid_config(u32 bus, u32 dev)
115{
116 /*
117 * Don't go out when trying to access --
118 * 1. our own device
119 * 2. where there's no device connected (no link)
120 * 3. nonexisting devices on local bus
121 */
122
123 if ((orion_pcie_local_bus_nr() == bus) &&
124 (orion_pcie_local_dev_nr() == dev))
125 return 0;
126
127 if (orion_pcie_no_link())
128 return 0;
129
130 if (bus == orion_pcie_local_bus_nr())
131 if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
132 ((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
133 return 0;
134
135 return 1;
136}
137
138static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
139 int size, u32 *val)
140{
141 unsigned long flags;
142 unsigned int dev, rev, pcie_addr;
143
144 if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
145 *val = 0xffffffff;
146 return PCIBIOS_DEVICE_NOT_FOUND;
147 }
148
149 spin_lock_irqsave(&orion_pcie_lock, flags);
150
151 orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
152 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
153 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
154 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
155
156 orion_pcie_id(&dev, &rev);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 /* extended register space */
159 pcie_addr = ORION_PCIE_WA_VIRT_BASE;
160 pcie_addr |= PCIE_CONF_BUS(bus->number) |
161 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
163 PCIE_CONF_REG(where);
164 *val = orion_read(pcie_addr);
165 } else
166 *val = orion_read(PCIE_CONF_DATA);
167
168 if (size == 1)
169 *val = (*val >> (8*(where & 0x3))) & 0xff;
170 else if (size == 2)
171 *val = (*val >> (8*(where & 0x3))) & 0xffff;
172
173 spin_unlock_irqrestore(&orion_pcie_lock, flags);
174
175 return PCIBIOS_SUCCESSFUL;
176}
177
178
179static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
180 int size, u32 val)
181{
182 unsigned long flags;
183 int ret;
184
185 if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
186 return PCIBIOS_DEVICE_NOT_FOUND;
187
188 spin_lock_irqsave(&orion_pcie_lock, flags);
189
190 ret = PCIBIOS_SUCCESSFUL;
191
192 orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
193 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
194 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
195 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
196
197 if (size == 4) {
198 __raw_writel(val, PCIE_CONF_DATA);
199 } else if (size == 2) {
200 __raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
201 } else if (size == 1) {
202 __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
203 } else {
204 ret = PCIBIOS_BAD_REGISTER_NUMBER;
205 }
206
207 spin_unlock_irqrestore(&orion_pcie_lock, flags);
208
209 return ret;
210}
211
212struct pci_ops orion_pcie_ops = {
213 .read = orion_pcie_rd_conf,
214 .write = orion_pcie_wr_conf,
215};
216
217
218static int orion_pcie_setup(struct pci_sys_data *sys)
219{
220 struct resource *res;
221
222 /*
223 * Master + Slave enable
224 */
225 orion_pcie_master_slave_enable();
226
227 /*
228 * Enable interrupts lines A-D
229 */
230 orion_pcie_enable_interrupts();
231
232 /*
233 * Request resource
234 */
235 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
236 if (!res)
237 panic("orion_pci_setup unable to alloc resources");
238
239 /*
240 * IORESOURCE_IO
241 */
242 res[0].name = "PCI-EX I/O Space";
243 res[0].flags = IORESOURCE_IO;
244 res[0].start = ORION_PCIE_IO_BUS_BASE;
245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
246 if (request_resource(&ioport_resource, &res[0]))
247 panic("Request PCIE IO resource failed\n");
248 sys->resource[0] = &res[0];
249
250 /*
251 * IORESOURCE_MEM
252 */
253 res[1].name = "PCI-EX Memory Space";
254 res[1].flags = IORESOURCE_MEM;
255 res[1].start = ORION_PCIE_MEM_PHYS_BASE;
256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
257 if (request_resource(&iomem_resource, &res[1]))
258 panic("Request PCIE Memory resource failed\n");
259 sys->resource[1] = &res[1];
260
261 sys->resource[2] = NULL;
262 sys->io_offset = 0;
263
264 return 1;
265}
266
267/*****************************************************************************
268 * PCI controller
269 ****************************************************************************/
270#define PCI_MODE ORION_PCI_REG(0xd00)
271#define PCI_CMD ORION_PCI_REG(0xc00)
272#define PCI_P2P_CONF ORION_PCI_REG(0x1d14)
273#define PCI_CONF_ADDR ORION_PCI_REG(0xc78)
274#define PCI_CONF_DATA ORION_PCI_REG(0xc7c)
275
276/*
277 * PCI_MODE bits
278 */
279#define PCI_MODE_64BIT (1 << 2)
280#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
281
282/*
283 * PCI_CMD bits
284 */
285#define PCI_CMD_HOST_REORDER (1 << 29)
286
287/*
288 * PCI_P2P_CONF bits
289 */
290#define PCI_P2P_BUS_OFFS 16
291#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
292#define PCI_P2P_DEV_OFFS 24
293#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
294
295/*
296 * PCI_CONF_ADDR bits
297 */
298#define PCI_CONF_REG(reg) ((reg) & 0xfc)
299#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
300#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
301#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
302#define PCI_CONF_ADDR_EN (1 << 31)
303
304/*
305 * Internal configuration space
306 */
307#define PCI_CONF_FUNC_STAT_CMD 0
308#define PCI_CONF_REG_STAT_CMD 4
309#define PCIX_STAT 0x64
310#define PCIX_STAT_BUS_OFFS 8
311#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
312
313/*
314 * PCI config cycles are done by programming the PCI_CONF_ADDR register
315 * and then reading the PCI_CONF_DATA register. Need to make sure these
316 * transactions are atomic.
317 */
318static DEFINE_SPINLOCK(orion_pci_lock);
319
320u32 orion_pci_local_bus_nr(void)
321{
322 u32 conf = orion_read(PCI_P2P_CONF);
323 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
324}
325
326u32 orion_pci_local_dev_nr(void)
327{
328 u32 conf = orion_read(PCI_P2P_CONF);
329 return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
330}
331
332int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
333 u32 where, u32 size, u32 *val)
334{
335 unsigned long flags;
336 spin_lock_irqsave(&orion_pci_lock, flags);
337
338 orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
339 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
340 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
341
342 *val = orion_read(PCI_CONF_DATA);
343
344 if (size == 1)
345 *val = (*val >> (8*(where & 0x3))) & 0xff;
346 else if (size == 2)
347 *val = (*val >> (8*(where & 0x3))) & 0xffff;
348
349 spin_unlock_irqrestore(&orion_pci_lock, flags);
350
351 return PCIBIOS_SUCCESSFUL;
352}
353
354int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
355 u32 where, u32 size, u32 val)
356{
357 unsigned long flags;
358 int ret = PCIBIOS_SUCCESSFUL;
359
360 spin_lock_irqsave(&orion_pci_lock, flags);
361
362 orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
363 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
364 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
365
366 if (size == 4) {
367 __raw_writel(val, PCI_CONF_DATA);
368 } else if (size == 2) {
369 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
370 } else if (size == 1) {
371 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
372 } else {
373 ret = PCIBIOS_BAD_REGISTER_NUMBER;
374 }
375
376 spin_unlock_irqrestore(&orion_pci_lock, flags);
377
378 return ret;
379}
380
381static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
382 int where, int size, u32 *val)
383{
384 /*
385 * Don't go out for local device
386 */
387 if ((orion_pci_local_bus_nr() == bus->number) &&
388 (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
389 *val = 0xffffffff;
390 return PCIBIOS_DEVICE_NOT_FOUND;
391 }
392
393 return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
394 PCI_FUNC(devfn), where, size, val);
395}
396
397static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
398 int where, int size, u32 val)
399{
400 /*
401 * Don't go out for local device
402 */
403 if ((orion_pci_local_bus_nr() == bus->number) &&
404 (orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
405 return PCIBIOS_DEVICE_NOT_FOUND;
406
407 return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
408 PCI_FUNC(devfn), where, size, val);
409}
410
411struct pci_ops orion_pci_ops = {
412 .read = orion_pci_rd_conf,
413 .write = orion_pci_wr_conf,
414};
415
416static void orion_pci_set_bus_nr(int nr)
417{
418 u32 p2p = orion_read(PCI_P2P_CONF);
419
420 if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
421 /*
422 * PCI-X mode
423 */
424 u32 pcix_status, bus, dev;
425 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
426 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
427 orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
428 pcix_status &= ~PCIX_STAT_BUS_MASK;
429 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
430 orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
431 } else {
432 /*
433 * PCI Conventional mode
434 */
435 p2p &= ~PCI_P2P_BUS_MASK;
436 p2p |= (nr << PCI_P2P_BUS_OFFS);
437 orion_write(PCI_P2P_CONF, p2p);
438 }
439}
440
441static void orion_pci_master_slave_enable(void)
442{
443 u32 bus_nr, dev_nr, func, reg, val;
444
445 bus_nr = orion_pci_local_bus_nr();
446 dev_nr = orion_pci_local_dev_nr();
447 func = PCI_CONF_FUNC_STAT_CMD;
448 reg = PCI_CONF_REG_STAT_CMD;
449 orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
450 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
451 orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
452}
453
454static int orion_pci_setup(struct pci_sys_data *sys)
455{
456 struct resource *res;
457
458 /*
459 * Master + Slave enable
460 */
461 orion_pci_master_slave_enable();
462
463 /*
464 * Force ordering
465 */
466 orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
467
468 /*
469 * Request resources
470 */
471 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
472 if (!res)
473 panic("orion_pci_setup unable to alloc resources");
474
475 /*
476 * IORESOURCE_IO
477 */
478 res[0].name = "PCI I/O Space";
479 res[0].flags = IORESOURCE_IO;
480 res[0].start = ORION_PCI_IO_BUS_BASE;
481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
482 if (request_resource(&ioport_resource, &res[0]))
483 panic("Request PCI IO resource failed\n");
484 sys->resource[0] = &res[0];
485
486 /*
487 * IORESOURCE_MEM
488 */
489 res[1].name = "PCI Memory Space";
490 res[1].flags = IORESOURCE_MEM;
491 res[1].start = ORION_PCI_MEM_PHYS_BASE;
492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
493 if (request_resource(&iomem_resource, &res[1]))
494 panic("Request PCI Memory resource failed\n");
495 sys->resource[1] = &res[1];
496
497 sys->resource[2] = NULL;
498 sys->io_offset = 0;
499
500 return 1;
501}
502
503
504/*****************************************************************************
505 * General PCIE + PCI
506 ****************************************************************************/
507int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
508{
509 int ret = 0;
510
511 if (nr == 0) {
512 /*
513 * PCIE setup
514 */
515 orion_pcie_set_bus_nr(0);
516 ret = orion_pcie_setup(sys);
517 } else if (nr == 1) {
518 /*
519 * PCI setup
520 */
521 ret = orion_pci_setup(sys);
522 }
523
524 return ret;
525}
526
527struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
528{
529 struct pci_ops *ops;
530 struct pci_bus *bus;
531
532
533 if (nr == 0) {
534 u32 pci_bus;
535 /*
536 * PCIE scan
537 */
538 ops = &orion_pcie_ops;
539 bus = pci_scan_bus(sys->busnr, ops, sys);
540 /*
541 * Set local PCI bus number to follow PCIE bridges (if any)
542 */
543 pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
544 orion_pci_set_bus_nr(pci_bus);
545 } else if (nr == 1) {
546 /*
547 * PCI scan
548 */
549 ops = &orion_pci_ops;
550 bus = pci_scan_bus(sys->busnr, ops, sys);
551 } else {
552 BUG();
553 bus = NULL;
554 }
555
556 return bus;
557}
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