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-rw-r--r--arch/arm/mach-orion/irq.c241
1 files changed, 241 insertions, 0 deletions
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c
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index 000000000000..df7e12ad378b
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1/*
2 * arch/arm/mach-orion/irq.c
3 *
4 * Core IRQ functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <asm/gpio.h>
17#include <asm/arch/orion.h>
18#include "common.h"
19
20/*****************************************************************************
21 * Orion GPIO IRQ
22 *
23 * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
24 * value of the line or the opposite value.
25 *
26 * Level IRQ handlers: DATA_IN is used directly as cause register.
27 * Interrupt are masked by LEVEL_MASK registers.
28 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
29 * Interrupt are masked by EDGE_MASK registers.
30 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
31 * the polarity to catch the next line transaction.
32 * This is a race condition that might not perfectly
33 * work on some use cases.
34 *
35 * Every eight GPIO lines are grouped (OR'ed) before going up to main
36 * cause register.
37 *
38 * EDGE cause mask
39 * data-in /--------| |-----| |----\
40 * -----| |----- ---- to main cause reg
41 * X \----------------| |----/
42 * polarity LEVEL mask
43 *
44 ****************************************************************************/
45static void orion_gpio_irq_ack(u32 irq)
46{
47 int pin = irq_to_gpio(irq);
48 if (irq_desc[irq].status & IRQ_LEVEL)
49 /*
50 * Mask bit for level interrupt
51 */
52 orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
53 else
54 /*
55 * Clear casue bit for egde interrupt
56 */
57 orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
58}
59
60static void orion_gpio_irq_mask(u32 irq)
61{
62 int pin = irq_to_gpio(irq);
63 if (irq_desc[irq].status & IRQ_LEVEL)
64 orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
65 else
66 orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
67}
68
69static void orion_gpio_irq_unmask(u32 irq)
70{
71 int pin = irq_to_gpio(irq);
72 if (irq_desc[irq].status & IRQ_LEVEL)
73 orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
74 else
75 orion_setbits(GPIO_EDGE_MASK, 1 << pin);
76}
77
78static int orion_gpio_set_irq_type(u32 irq, u32 type)
79{
80 int pin = irq_to_gpio(irq);
81 struct irq_desc *desc;
82
83 if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
84 printk(KERN_ERR "orion_gpio_set_irq_type failed "
85 "(irq %d, pin %d).\n", irq, pin);
86 return -EINVAL;
87 }
88
89 desc = irq_desc + irq;
90
91 switch (type) {
92 case IRQT_HIGH:
93 desc->handle_irq = handle_level_irq;
94 desc->status |= IRQ_LEVEL;
95 orion_clrbits(GPIO_IN_POL, (1 << pin));
96 break;
97 case IRQT_LOW:
98 desc->handle_irq = handle_level_irq;
99 desc->status |= IRQ_LEVEL;
100 orion_setbits(GPIO_IN_POL, (1 << pin));
101 break;
102 case IRQT_RISING:
103 desc->handle_irq = handle_edge_irq;
104 desc->status &= ~IRQ_LEVEL;
105 orion_clrbits(GPIO_IN_POL, (1 << pin));
106 break;
107 case IRQT_FALLING:
108 desc->handle_irq = handle_edge_irq;
109 desc->status &= ~IRQ_LEVEL;
110 orion_setbits(GPIO_IN_POL, (1 << pin));
111 break;
112 case IRQT_BOTHEDGE:
113 desc->handle_irq = handle_edge_irq;
114 desc->status &= ~IRQ_LEVEL;
115 /*
116 * set initial polarity based on current input level
117 */
118 if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
119 & (1 << pin))
120 orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
121 else
122 orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
123
124 break;
125 default:
126 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
127 return -EINVAL;
128 }
129
130 desc->status &= ~IRQ_TYPE_SENSE_MASK;
131 desc->status |= type & IRQ_TYPE_SENSE_MASK;
132
133 return 0;
134}
135
136static struct irq_chip orion_gpio_irq_chip = {
137 .name = "Orion-IRQ-GPIO",
138 .ack = orion_gpio_irq_ack,
139 .mask = orion_gpio_irq_mask,
140 .unmask = orion_gpio_irq_unmask,
141 .set_type = orion_gpio_set_irq_type,
142};
143
144static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
145{
146 u32 cause, offs, pin;
147
148 BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
149 offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
150 cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
151 (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
152
153 for (pin = offs; pin < offs + 8; pin++) {
154 if (cause & (1 << pin)) {
155 irq = gpio_to_irq(pin);
156 desc = irq_desc + irq;
157 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
158 /* Swap polarity (race with GPIO line) */
159 u32 polarity = orion_read(GPIO_IN_POL);
160 polarity ^= 1 << pin;
161 orion_write(GPIO_IN_POL, polarity);
162 }
163 desc_handle_irq(irq, desc);
164 }
165 }
166}
167
168static void __init orion_init_gpio_irq(void)
169{
170 int i;
171 struct irq_desc *desc;
172
173 /*
174 * Mask and clear GPIO IRQ interrupts
175 */
176 orion_write(GPIO_LEVEL_MASK, 0x0);
177 orion_write(GPIO_EDGE_MASK, 0x0);
178 orion_write(GPIO_EDGE_CAUSE, 0x0);
179
180 /*
181 * Register chained level handlers for GPIO IRQs by default.
182 * User can use set_type() if he wants to use edge types handlers.
183 */
184 for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
185 set_irq_chip(i, &orion_gpio_irq_chip);
186 set_irq_handler(i, handle_level_irq);
187 desc = irq_desc + i;
188 desc->status |= IRQ_LEVEL;
189 set_irq_flags(i, IRQF_VALID);
190 }
191 set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
192 set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
193 set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
194 set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
195}
196
197/*****************************************************************************
198 * Orion Main IRQ
199 ****************************************************************************/
200static void orion_main_irq_mask(u32 irq)
201{
202 orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
203}
204
205static void orion_main_irq_unmask(u32 irq)
206{
207 orion_setbits(MAIN_IRQ_MASK, 1 << irq);
208}
209
210static struct irq_chip orion_main_irq_chip = {
211 .name = "Orion-IRQ-Main",
212 .ack = orion_main_irq_mask,
213 .mask = orion_main_irq_mask,
214 .unmask = orion_main_irq_unmask,
215};
216
217static void __init orion_init_main_irq(void)
218{
219 int i;
220
221 /*
222 * Mask and clear Main IRQ interrupts
223 */
224 orion_write(MAIN_IRQ_MASK, 0x0);
225 orion_write(MAIN_IRQ_CAUSE, 0x0);
226
227 /*
228 * Register level handler for Main IRQs
229 */
230 for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
231 set_irq_chip(i, &orion_main_irq_chip);
232 set_irq_handler(i, handle_level_irq);
233 set_irq_flags(i, IRQF_VALID);
234 }
235}
236
237void __init orion_init_irq(void)
238{
239 orion_init_main_irq();
240 orion_init_gpio_irq();
241}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 02:15:00 -0500