aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig2
-rw-r--r--arch/arm/mach-omap2/Makefile7
-rw-r--r--arch/arm/mach-omap2/am35xx-emac.c90
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c3
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3logic.c3
-rw-r--r--arch/arm/mach-omap2/board-overo.c2
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c28
-rw-r--r--arch/arm/mach-omap2/clockdomain.h4
-rw-r--r--arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c1
-rw-r--r--arch/arm/mach-omap2/clockdomains3xxx_data.c157
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h4
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c22
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c8
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c8
-rw-r--r--arch/arm/mach-omap2/devices.c2
-rw-r--r--arch/arm/mach-omap2/include/mach/am35xx.h2
-rw-r--r--arch/arm/mach-omap2/irq.c8
-rw-r--r--arch/arm/mach-omap2/mailbox.c2
-rw-r--r--arch/arm/mach-omap2/omap-iommu.c6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c32
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c143
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c28
-rw-r--r--arch/arm/mach-omap2/opp.c3
-rw-r--r--arch/arm/mach-omap2/pm.h17
-rw-r--r--arch/arm/mach-omap2/pm34xx.c15
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c139
-rw-r--r--arch/arm/mach-omap2/prcm-common.h4
-rw-r--r--arch/arm/mach-omap2/prm_common.c8
-rw-r--r--arch/arm/mach-omap2/twl-common.c13
31 files changed, 577 insertions, 188 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 6c934778357b..2776eaacac5e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -39,6 +39,7 @@ config ARCH_OMAP3
39 select CPU_V7 39 select CPU_V7
40 select USB_ARCH_HAS_EHCI if USB_SUPPORT 40 select USB_ARCH_HAS_EHCI if USB_SUPPORT
41 select ARCH_HAS_OPP 41 select ARCH_HAS_OPP
42 select PM_RUNTIME if CPU_IDLE
42 select PM_OPP if PM 43 select PM_OPP if PM
43 select ARM_CPU_SUSPEND if PM 44 select ARM_CPU_SUSPEND if PM
44 select MULTI_IRQ_HANDLER 45 select MULTI_IRQ_HANDLER
@@ -57,6 +58,7 @@ config ARCH_OMAP4
57 select PL310_ERRATA_727915 58 select PL310_ERRATA_727915
58 select ARM_ERRATA_720789 59 select ARM_ERRATA_720789
59 select ARCH_HAS_OPP 60 select ARCH_HAS_OPP
61 select PM_RUNTIME if CPU_IDLE
60 select PM_OPP if PM 62 select PM_OPP if PM
61 select USB_ARCH_HAS_EHCI if USB_SUPPORT 63 select USB_ARCH_HAS_EHCI if USB_SUPPORT
62 select ARM_CPU_SUSPEND if PM 64 select ARM_CPU_SUSPEND if PM
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 240f1969f2ad..bdfd400b4996 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -68,9 +68,7 @@ ifeq ($(CONFIG_PM),y)
68obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o 68obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
69obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o 69obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
70obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o 70obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
71obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
72obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o 71obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
73obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
74obj-$(CONFIG_PM_DEBUG) += pm-debug.o 72obj-$(CONFIG_PM_DEBUG) += pm-debug.o
75obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o 73obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
76obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o 74obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
@@ -84,6 +82,11 @@ endif
84 82
85endif 83endif
86 84
85ifeq ($(CONFIG_CPU_IDLE),y)
86obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
87obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
88endif
89
87# PRCM 90# PRCM
88obj-y += prm_common.o 91obj-y += prm_common.o
89obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o 92obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 447682c4e11c..2c90ac686686 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -15,27 +15,13 @@
15 * General Public License for more details. 15 * General Public License for more details.
16 */ 16 */
17 17
18#include <linux/clk.h> 18#include <linux/err.h>
19#include <linux/davinci_emac.h> 19#include <linux/davinci_emac.h>
20#include <linux/platform_device.h> 20#include <asm/system.h>
21#include <plat/irqs.h> 21#include <plat/omap_device.h>
22#include <mach/am35xx.h> 22#include <mach/am35xx.h>
23
24#include "control.h" 23#include "control.h"
25 24#include "am35xx-emac.h"
26static struct mdio_platform_data am35xx_emac_mdio_pdata;
27
28static struct resource am35xx_emac_mdio_resources[] = {
29 DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
30};
31
32static struct platform_device am35xx_emac_mdio_device = {
33 .name = "davinci_mdio",
34 .id = 0,
35 .num_resources = ARRAY_SIZE(am35xx_emac_mdio_resources),
36 .resource = am35xx_emac_mdio_resources,
37 .dev.platform_data = &am35xx_emac_mdio_pdata,
38};
39 25
40static void am35xx_enable_emac_int(void) 26static void am35xx_enable_emac_int(void)
41{ 27{
@@ -69,41 +55,57 @@ static struct emac_platform_data am35xx_emac_pdata = {
69 .interrupt_disable = am35xx_disable_emac_int, 55 .interrupt_disable = am35xx_disable_emac_int,
70}; 56};
71 57
72static struct resource am35xx_emac_resources[] = { 58static struct mdio_platform_data am35xx_mdio_pdata;
73 DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
74 DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
75 DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
76 DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
77 DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
78};
79 59
80static struct platform_device am35xx_emac_device = { 60static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
81 .name = "davinci_emac", 61 void *pdata, int pdata_len)
82 .id = -1, 62{
83 .num_resources = ARRAY_SIZE(am35xx_emac_resources), 63 struct platform_device *pdev;
84 .resource = am35xx_emac_resources, 64
85 .dev = { 65 pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
86 .platform_data = &am35xx_emac_pdata, 66 NULL, 0, false);
87 }, 67 if (IS_ERR(pdev)) {
88}; 68 WARN(1, "Can't build omap_device for %s:%s.\n",
69 oh->class->name, oh->name);
70 return PTR_ERR(pdev);
71 }
72
73 return 0;
74}
89 75
90void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) 76void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
91{ 77{
78 struct omap_hwmod *oh;
92 u32 v; 79 u32 v;
93 int err; 80 int ret;
94 81
95 am35xx_emac_pdata.rmii_en = rmii_en; 82 oh = omap_hwmod_lookup("davinci_mdio");
96 am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq; 83 if (!oh) {
97 err = platform_device_register(&am35xx_emac_device); 84 pr_err("Could not find davinci_mdio hwmod\n");
98 if (err) { 85 return;
99 pr_err("AM35x: failed registering EMAC device: %d\n", err); 86 }
87
88 am35xx_mdio_pdata.bus_freq = mdio_bus_freq;
89
90 ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata,
91 sizeof(am35xx_mdio_pdata));
92 if (ret) {
93 pr_err("Could not build davinci_mdio hwmod device\n");
100 return; 94 return;
101 } 95 }
102 96
103 err = platform_device_register(&am35xx_emac_mdio_device); 97 oh = omap_hwmod_lookup("davinci_emac");
104 if (err) { 98 if (!oh) {
105 pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err); 99 pr_err("Could not find davinci_emac hwmod\n");
106 platform_device_unregister(&am35xx_emac_device); 100 return;
101 }
102
103 am35xx_emac_pdata.rmii_en = rmii_en;
104
105 ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata,
106 sizeof(am35xx_emac_pdata));
107 if (ret) {
108 pr_err("Could not build davinci_emac hwmod device\n");
107 return; 109 return;
108 } 110 }
109 111
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 6523aeabf9f2..9511584fdc4f 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
218}; 218};
219 219
220static struct twl4030_platform_data sdp2430_twldata = { 220static struct twl4030_platform_data sdp2430_twldata = {
221 .irq_base = TWL4030_IRQ_BASE,
222 .irq_end = TWL4030_IRQ_END,
223
224 /* platform_data for children goes here */ 221 /* platform_data for children goes here */
225 .gpio = &sdp2430_gpio_data, 222 .gpio = &sdp2430_gpio_data,
226 .vmmc1 = &sdp2430_vmmc1, 223 .vmmc1 = &sdp2430_vmmc1,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 580fd17208da..6202fc76e490 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -433,7 +433,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
433 433
434static const struct usbhs_omap_board_data usbhs_bdata __initconst = { 434static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
435 435
436 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 436 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
437 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 437 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
438 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 438 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
439 439
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 932e1778aff9..fca93d1afd43 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -93,9 +93,6 @@ static struct twl4030_usb_data omap3logic_usb_data = {
93 93
94 94
95static struct twl4030_platform_data omap3logic_twldata = { 95static struct twl4030_platform_data omap3logic_twldata = {
96 .irq_base = TWL4030_IRQ_BASE,
97 .irq_end = TWL4030_IRQ_END,
98
99 /* platform_data for children goes here */ 96 /* platform_data for children goes here */
100 .gpio = &omap3logic_gpio_data, 97 .gpio = &omap3logic_gpio_data,
101 .vmmc1 = &omap3logic_vmmc1, 98 .vmmc1 = &omap3logic_vmmc1,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 8fa2fc3a4c3c..779734d8ba37 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -494,8 +494,8 @@ static void __init overo_init(void)
494 494
495 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 495 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
496 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 496 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
497 omap_hsmmc_init(mmc);
498 overo_i2c_init(); 497 overo_i2c_init();
498 omap_hsmmc_init(mmc);
499 omap_display_init(&overo_dss_data); 499 omap_display_init(&overo_dss_data);
500 omap_serial_init(); 500 omap_serial_init();
501 omap_sdrc_init(mt46h32m32lf6_sdrc_params, 501 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 7300982a8e0e..c3e91d0dd2f2 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2490,13 +2490,13 @@ static struct clk uart4_fck = {
2490}; 2490};
2491 2491
2492static struct clk uart4_fck_am35xx = { 2492static struct clk uart4_fck_am35xx = {
2493 .name = "uart4_fck", 2493 .name = "uart4_fck",
2494 .ops = &clkops_omap2_dflt_wait, 2494 .ops = &clkops_omap2_dflt_wait,
2495 .parent = &per_48m_fck, 2495 .parent = &core_48m_fck,
2496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2497 .enable_bit = OMAP3430_EN_UART4_SHIFT, 2497 .enable_bit = AM35XX_EN_UART4_SHIFT,
2498 .clkdm_name = "core_l4_clkdm", 2498 .clkdm_name = "core_l4_clkdm",
2499 .recalc = &followparent_recalc, 2499 .recalc = &followparent_recalc,
2500}; 2500};
2501 2501
2502static struct clk gpt2_fck = { 2502static struct clk gpt2_fck = {
@@ -3201,8 +3201,12 @@ static struct clk vpfe_fck = {
3201}; 3201};
3202 3202
3203/* 3203/*
3204 * The UART1/2 functional clock acts as the functional 3204 * The UART1/2 functional clock acts as the functional clock for
3205 * clock for UART4. No separate fclk control available. 3205 * UART4. No separate fclk control available. XXX Well now we have a
3206 * uart4_fck that is apparently used as the UART4 functional clock,
3207 * but it also seems that uart1_fck or uart2_fck are still needed, at
3208 * least for UART4 softresets to complete. This really needs
3209 * clarification.
3206 */ 3210 */
3207static struct clk uart4_ick_am35xx = { 3211static struct clk uart4_ick_am35xx = {
3208 .name = "uart4_ick", 3212 .name = "uart4_ick",
@@ -3464,12 +3468,12 @@ static struct omap_clk omap3xxx_clks[] = {
3464 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), 3468 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3465 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), 3469 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3466 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), 3470 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3467 CLK("davinci_emac", NULL, &emac_ick, CK_AM35XX), 3471 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3468 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), 3472 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3469 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), 3473 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3470 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), 3474 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3471 CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), 3475 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3472 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), 3476 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3473 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), 3477 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3474 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), 3478 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3475 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), 3479 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 0a8c7b67858c..5601dc13785e 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -31,12 +31,16 @@
31 * 31 *
32 * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this 32 * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
33 * clockdomain. (Currently, this applies to OMAP3 clockdomains only.) 33 * clockdomain. (Currently, this applies to OMAP3 clockdomains only.)
34 * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
35 * active whenever the MPU is active. True for interconnects and
36 * the WKUP clockdomains.
34 */ 37 */
35#define CLKDM_CAN_FORCE_SLEEP (1 << 0) 38#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
36#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) 39#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
37#define CLKDM_CAN_ENABLE_AUTO (1 << 2) 40#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
38#define CLKDM_CAN_DISABLE_AUTO (1 << 3) 41#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
39#define CLKDM_NO_AUTODEPS (1 << 4) 42#define CLKDM_NO_AUTODEPS (1 << 4)
43#define CLKDM_ACTIVE_WITH_MPU (1 << 5)
40 44
41#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) 45#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
42#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) 46#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 839145e1cfbe..4972219653ce 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -88,4 +88,5 @@ struct clockdomain wkup_common_clkdm = {
88 .name = "wkup_clkdm", 88 .name = "wkup_clkdm",
89 .pwrdm = { .name = "wkup_pwrdm" }, 89 .pwrdm = { .name = "wkup_pwrdm" },
90 .dep_bit = OMAP_EN_WKUP_SHIFT, 90 .dep_bit = OMAP_EN_WKUP_SHIFT,
91 .flags = CLKDM_ACTIVE_WITH_MPU,
91}; 92};
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 2cdc17c9d2fa..56089c49142a 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -59,6 +59,12 @@ static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
59 { NULL }, 59 { NULL },
60}; 60};
61 61
62static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = {
63 { .clkdm_name = "mpu_clkdm" },
64 { .clkdm_name = "wkup_clkdm" },
65 { NULL },
66};
67
62/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ 68/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
63static struct clkdm_dep per_wkdeps[] = { 69static struct clkdm_dep per_wkdeps[] = {
64 { .clkdm_name = "core_l3_clkdm" }, 70 { .clkdm_name = "core_l3_clkdm" },
@@ -69,6 +75,14 @@ static struct clkdm_dep per_wkdeps[] = {
69 { NULL }, 75 { NULL },
70}; 76};
71 77
78static struct clkdm_dep per_am35x_wkdeps[] = {
79 { .clkdm_name = "core_l3_clkdm" },
80 { .clkdm_name = "core_l4_clkdm" },
81 { .clkdm_name = "mpu_clkdm" },
82 { .clkdm_name = "wkup_clkdm" },
83 { NULL },
84};
85
72/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ 86/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
73static struct clkdm_dep usbhost_wkdeps[] = { 87static struct clkdm_dep usbhost_wkdeps[] = {
74 { .clkdm_name = "core_l3_clkdm" }, 88 { .clkdm_name = "core_l3_clkdm" },
@@ -79,6 +93,14 @@ static struct clkdm_dep usbhost_wkdeps[] = {
79 { NULL }, 93 { NULL },
80}; 94};
81 95
96static struct clkdm_dep usbhost_am35x_wkdeps[] = {
97 { .clkdm_name = "core_l3_clkdm" },
98 { .clkdm_name = "core_l4_clkdm" },
99 { .clkdm_name = "mpu_clkdm" },
100 { .clkdm_name = "wkup_clkdm" },
101 { NULL },
102};
103
82/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ 104/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
83static struct clkdm_dep mpu_3xxx_wkdeps[] = { 105static struct clkdm_dep mpu_3xxx_wkdeps[] = {
84 { .clkdm_name = "core_l3_clkdm" }, 106 { .clkdm_name = "core_l3_clkdm" },
@@ -89,6 +111,14 @@ static struct clkdm_dep mpu_3xxx_wkdeps[] = {
89 { NULL }, 111 { NULL },
90}; 112};
91 113
114static struct clkdm_dep mpu_am35x_wkdeps[] = {
115 { .clkdm_name = "core_l3_clkdm" },
116 { .clkdm_name = "core_l4_clkdm" },
117 { .clkdm_name = "dss_clkdm" },
118 { .clkdm_name = "per_clkdm" },
119 { NULL },
120};
121
92/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ 122/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
93static struct clkdm_dep iva2_wkdeps[] = { 123static struct clkdm_dep iva2_wkdeps[] = {
94 { .clkdm_name = "core_l3_clkdm" }, 124 { .clkdm_name = "core_l3_clkdm" },
@@ -116,6 +146,12 @@ static struct clkdm_dep dss_wkdeps[] = {
116 { NULL }, 146 { NULL },
117}; 147};
118 148
149static struct clkdm_dep dss_am35x_wkdeps[] = {
150 { .clkdm_name = "mpu_clkdm" },
151 { .clkdm_name = "wkup_clkdm" },
152 { NULL },
153};
154
119/* 3430: PM_WKDEP_NEON: MPU */ 155/* 3430: PM_WKDEP_NEON: MPU */
120static struct clkdm_dep neon_wkdeps[] = { 156static struct clkdm_dep neon_wkdeps[] = {
121 { .clkdm_name = "mpu_clkdm" }, 157 { .clkdm_name = "mpu_clkdm" },
@@ -131,6 +167,11 @@ static struct clkdm_dep dss_sleepdeps[] = {
131 { NULL }, 167 { NULL },
132}; 168};
133 169
170static struct clkdm_dep dss_am35x_sleepdeps[] = {
171 { .clkdm_name = "mpu_clkdm" },
172 { NULL },
173};
174
134/* 3430: CM_SLEEPDEP_PER: MPU, IVA */ 175/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
135static struct clkdm_dep per_sleepdeps[] = { 176static struct clkdm_dep per_sleepdeps[] = {
136 { .clkdm_name = "mpu_clkdm" }, 177 { .clkdm_name = "mpu_clkdm" },
@@ -138,6 +179,11 @@ static struct clkdm_dep per_sleepdeps[] = {
138 { NULL }, 179 { NULL },
139}; 180};
140 181
182static struct clkdm_dep per_am35x_sleepdeps[] = {
183 { .clkdm_name = "mpu_clkdm" },
184 { NULL },
185};
186
141/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ 187/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
142static struct clkdm_dep usbhost_sleepdeps[] = { 188static struct clkdm_dep usbhost_sleepdeps[] = {
143 { .clkdm_name = "mpu_clkdm" }, 189 { .clkdm_name = "mpu_clkdm" },
@@ -145,6 +191,11 @@ static struct clkdm_dep usbhost_sleepdeps[] = {
145 { NULL }, 191 { NULL },
146}; 192};
147 193
194static struct clkdm_dep usbhost_am35x_sleepdeps[] = {
195 { .clkdm_name = "mpu_clkdm" },
196 { NULL },
197};
198
148/* 3430: CM_SLEEPDEP_CAM: MPU */ 199/* 3430: CM_SLEEPDEP_CAM: MPU */
149static struct clkdm_dep cam_sleepdeps[] = { 200static struct clkdm_dep cam_sleepdeps[] = {
150 { .clkdm_name = "mpu_clkdm" }, 201 { .clkdm_name = "mpu_clkdm" },
@@ -175,6 +226,15 @@ static struct clockdomain mpu_3xxx_clkdm = {
175 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, 226 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
176}; 227};
177 228
229static struct clockdomain mpu_am35x_clkdm = {
230 .name = "mpu_clkdm",
231 .pwrdm = { .name = "mpu_pwrdm" },
232 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
233 .dep_bit = OMAP3430_EN_MPU_SHIFT,
234 .wkdep_srcs = mpu_am35x_wkdeps,
235 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
236};
237
178static struct clockdomain neon_clkdm = { 238static struct clockdomain neon_clkdm = {
179 .name = "neon_clkdm", 239 .name = "neon_clkdm",
180 .pwrdm = { .name = "neon_pwrdm" }, 240 .pwrdm = { .name = "neon_pwrdm" },
@@ -210,6 +270,15 @@ static struct clockdomain sgx_clkdm = {
210 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, 270 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
211}; 271};
212 272
273static struct clockdomain sgx_am35x_clkdm = {
274 .name = "sgx_clkdm",
275 .pwrdm = { .name = "sgx_pwrdm" },
276 .flags = CLKDM_CAN_HWSUP_SWSUP,
277 .wkdep_srcs = gfx_sgx_am35x_wkdeps,
278 .sleepdep_srcs = gfx_sgx_sleepdeps,
279 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
280};
281
213/* 282/*
214 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but 283 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
215 * then that information was removed from the 34xx ES2+ TRM. It is 284 * then that information was removed from the 34xx ES2+ TRM. It is
@@ -261,6 +330,16 @@ static struct clockdomain dss_3xxx_clkdm = {
261 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, 330 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
262}; 331};
263 332
333static struct clockdomain dss_am35x_clkdm = {
334 .name = "dss_clkdm",
335 .pwrdm = { .name = "dss_pwrdm" },
336 .flags = CLKDM_CAN_HWSUP_SWSUP,
337 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
338 .wkdep_srcs = dss_am35x_wkdeps,
339 .sleepdep_srcs = dss_am35x_sleepdeps,
340 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
341};
342
264static struct clockdomain cam_clkdm = { 343static struct clockdomain cam_clkdm = {
265 .name = "cam_clkdm", 344 .name = "cam_clkdm",
266 .pwrdm = { .name = "cam_pwrdm" }, 345 .pwrdm = { .name = "cam_pwrdm" },
@@ -279,6 +358,15 @@ static struct clockdomain usbhost_clkdm = {
279 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, 358 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
280}; 359};
281 360
361static struct clockdomain usbhost_am35x_clkdm = {
362 .name = "usbhost_clkdm",
363 .pwrdm = { .name = "core_pwrdm" },
364 .flags = CLKDM_CAN_HWSUP_SWSUP,
365 .wkdep_srcs = usbhost_am35x_wkdeps,
366 .sleepdep_srcs = usbhost_am35x_sleepdeps,
367 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
368};
369
282static struct clockdomain per_clkdm = { 370static struct clockdomain per_clkdm = {
283 .name = "per_clkdm", 371 .name = "per_clkdm",
284 .pwrdm = { .name = "per_pwrdm" }, 372 .pwrdm = { .name = "per_pwrdm" },
@@ -289,6 +377,16 @@ static struct clockdomain per_clkdm = {
289 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, 377 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
290}; 378};
291 379
380static struct clockdomain per_am35x_clkdm = {
381 .name = "per_clkdm",
382 .pwrdm = { .name = "per_pwrdm" },
383 .flags = CLKDM_CAN_HWSUP_SWSUP,
384 .dep_bit = OMAP3430_EN_PER_SHIFT,
385 .wkdep_srcs = per_am35x_wkdeps,
386 .sleepdep_srcs = per_am35x_sleepdeps,
387 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
388};
389
292/* 390/*
293 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is 391 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
294 * switched of even if sdti is in use 392 * switched of even if sdti is in use
@@ -341,29 +439,42 @@ static struct clkdm_autodep clkdm_autodeps[] = {
341 } 439 }
342}; 440};
343 441
442static struct clkdm_autodep clkdm_am35x_autodeps[] = {
443 {
444 .clkdm = { .name = "mpu_clkdm" },
445 },
446 {
447 .clkdm = { .name = NULL },
448 }
449};
450
344/* 451/*
345 * 452 *
346 */ 453 */
347 454
348static struct clockdomain *clockdomains_omap3430_common[] __initdata = { 455static struct clockdomain *clockdomains_common[] __initdata = {
349 &wkup_common_clkdm, 456 &wkup_common_clkdm,
350 &mpu_3xxx_clkdm,
351 &neon_clkdm, 457 &neon_clkdm,
352 &iva2_clkdm,
353 &d2d_clkdm,
354 &core_l3_3xxx_clkdm, 458 &core_l3_3xxx_clkdm,
355 &core_l4_3xxx_clkdm, 459 &core_l4_3xxx_clkdm,
356 &dss_3xxx_clkdm,
357 &cam_clkdm,
358 &per_clkdm,
359 &emu_clkdm, 460 &emu_clkdm,
360 &dpll1_clkdm, 461 &dpll1_clkdm,
361 &dpll2_clkdm,
362 &dpll3_clkdm, 462 &dpll3_clkdm,
363 &dpll4_clkdm, 463 &dpll4_clkdm,
364 NULL 464 NULL
365}; 465};
366 466
467static struct clockdomain *clockdomains_omap3430[] __initdata = {
468 &mpu_3xxx_clkdm,
469 &iva2_clkdm,
470 &d2d_clkdm,
471 &dss_3xxx_clkdm,
472 &cam_clkdm,
473 &per_clkdm,
474 &dpll2_clkdm,
475 NULL
476};
477
367static struct clockdomain *clockdomains_omap3430es1[] __initdata = { 478static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
368 &gfx_3430es1_clkdm, 479 &gfx_3430es1_clkdm,
369 NULL, 480 NULL,
@@ -376,21 +487,41 @@ static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
376 NULL, 487 NULL,
377}; 488};
378 489
490static struct clockdomain *clockdomains_am35x[] __initdata = {
491 &mpu_am35x_clkdm,
492 &sgx_am35x_clkdm,
493 &dss_am35x_clkdm,
494 &per_am35x_clkdm,
495 &usbhost_am35x_clkdm,
496 &dpll5_clkdm,
497 NULL
498};
499
379void __init omap3xxx_clockdomains_init(void) 500void __init omap3xxx_clockdomains_init(void)
380{ 501{
381 struct clockdomain **sc; 502 struct clockdomain **sc;
503 unsigned int rev;
382 504
383 if (!cpu_is_omap34xx()) 505 if (!cpu_is_omap34xx())
384 return; 506 return;
385 507
386 clkdm_register_platform_funcs(&omap3_clkdm_operations); 508 clkdm_register_platform_funcs(&omap3_clkdm_operations);
387 clkdm_register_clkdms(clockdomains_omap3430_common); 509 clkdm_register_clkdms(clockdomains_common);
388 510
389 sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 : 511 rev = omap_rev();
390 clockdomains_omap3430es2plus;
391 512
392 clkdm_register_clkdms(sc); 513 if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
514 clkdm_register_clkdms(clockdomains_am35x);
515 clkdm_register_autodeps(clkdm_am35x_autodeps);
516 } else {
517 clkdm_register_clkdms(clockdomains_omap3430);
518
519 sc = (rev == OMAP3430_REV_ES1_0) ?
520 clockdomains_omap3430es1 : clockdomains_omap3430es2plus;
521
522 clkdm_register_clkdms(sc);
523 clkdm_register_autodeps(clkdm_autodeps);
524 }
393 525
394 clkdm_register_autodeps(clkdm_autodeps);
395 clkdm_complete_init(); 526 clkdm_complete_init();
396} 527}
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index bd7ed13515cc..63d60a773d3b 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -381,7 +381,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
381 .cm_inst = OMAP4430_PRM_WKUP_CM_INST, 381 .cm_inst = OMAP4430_PRM_WKUP_CM_INST,
382 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, 382 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
383 .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, 383 .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
384 .flags = CLKDM_CAN_HWSUP, 384 .flags = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU,
385}; 385};
386 386
387static struct clockdomain emu_sys_44xx_clkdm = { 387static struct clockdomain emu_sys_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 8083a8cdc55f..766338fe4d34 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -169,8 +169,6 @@
169/* AM35XX specific CM_ICLKEN1_CORE bits */ 169/* AM35XX specific CM_ICLKEN1_CORE bits */
170#define AM35XX_EN_IPSS_MASK (1 << 4) 170#define AM35XX_EN_IPSS_MASK (1 << 4)
171#define AM35XX_EN_IPSS_SHIFT 4 171#define AM35XX_EN_IPSS_SHIFT 4
172#define AM35XX_EN_UART4_MASK (1 << 23)
173#define AM35XX_EN_UART4_SHIFT 23
174 172
175/* CM_ICLKEN2_CORE */ 173/* CM_ICLKEN2_CORE */
176#define OMAP3430_EN_PKA_MASK (1 << 4) 174#define OMAP3430_EN_PKA_MASK (1 << 4)
@@ -207,6 +205,8 @@
207#define OMAP3430_ST_DES2_MASK (1 << 26) 205#define OMAP3430_ST_DES2_MASK (1 << 26)
208#define OMAP3430_ST_MSPRO_SHIFT 23 206#define OMAP3430_ST_MSPRO_SHIFT 23
209#define OMAP3430_ST_MSPRO_MASK (1 << 23) 207#define OMAP3430_ST_MSPRO_MASK (1 << 23)
208#define AM35XX_ST_UART4_SHIFT 23
209#define AM35XX_ST_UART4_MASK (1 << 23)
210#define OMAP3430_ST_HDQ_SHIFT 22 210#define OMAP3430_ST_HDQ_SHIFT 22
211#define OMAP3430_ST_HDQ_MASK (1 << 22) 211#define OMAP3430_ST_HDQ_MASK (1 << 22)
212#define OMAP3430ES1_ST_FAC_SHIFT 8 212#define OMAP3430ES1_ST_FAC_SHIFT 8
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 1706ebcec08d..c1875862679f 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -63,28 +63,30 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
63 struct spi_board_info *spi_bi = &ads7846_spi_board_info; 63 struct spi_board_info *spi_bi = &ads7846_spi_board_info;
64 int err; 64 int err;
65 65
66 if (board_pdata && board_pdata->get_pendown_state) { 66 err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
67 err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown"); 67 if (err) {
68 if (err) { 68 pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
69 pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err); 69 return;
70 return;
71 }
72 gpio_export(gpio_pendown, 0);
73
74 if (gpio_debounce)
75 gpio_set_debounce(gpio_pendown, gpio_debounce);
76 } 70 }
77 71
72 if (gpio_debounce)
73 gpio_set_debounce(gpio_pendown, gpio_debounce);
74
78 spi_bi->bus_num = bus_num; 75 spi_bi->bus_num = bus_num;
79 spi_bi->irq = gpio_to_irq(gpio_pendown); 76 spi_bi->irq = gpio_to_irq(gpio_pendown);
80 77
81 if (board_pdata) { 78 if (board_pdata) {
82 board_pdata->gpio_pendown = gpio_pendown; 79 board_pdata->gpio_pendown = gpio_pendown;
83 spi_bi->platform_data = board_pdata; 80 spi_bi->platform_data = board_pdata;
81 if (board_pdata->get_pendown_state)
82 gpio_export(gpio_pendown, 0);
84 } else { 83 } else {
85 ads7846_config.gpio_pendown = gpio_pendown; 84 ads7846_config.gpio_pendown = gpio_pendown;
86 } 85 }
87 86
87 if (!board_pdata || (board_pdata && !board_pdata->get_pendown_state))
88 gpio_free(gpio_pendown);
89
88 spi_register_board_info(&ads7846_spi_board_info, 1); 90 spi_register_board_info(&ads7846_spi_board_info, 1);
89} 91}
90#else 92#else
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 207bc1c7759f..31344528eb54 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -36,8 +36,6 @@
36#include "control.h" 36#include "control.h"
37#include "common.h" 37#include "common.h"
38 38
39#ifdef CONFIG_CPU_IDLE
40
41/* Mach specific information to be recorded in the C-state driver_data */ 39/* Mach specific information to be recorded in the C-state driver_data */
42struct omap3_idle_statedata { 40struct omap3_idle_statedata {
43 u32 mpu_state; 41 u32 mpu_state;
@@ -379,9 +377,3 @@ int __init omap3_idle_init(void)
379 377
380 return 0; 378 return 0;
381} 379}
382#else
383int __init omap3_idle_init(void)
384{
385 return 0;
386}
387#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index be1617ca84bd..02d15bbd4e35 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -22,8 +22,6 @@
22#include "pm.h" 22#include "pm.h"
23#include "prm.h" 23#include "prm.h"
24 24
25#ifdef CONFIG_CPU_IDLE
26
27/* Machine specific information */ 25/* Machine specific information */
28struct omap4_idle_statedata { 26struct omap4_idle_statedata {
29 u32 cpu_state; 27 u32 cpu_state;
@@ -199,9 +197,3 @@ int __init omap4_idle_init(void)
199 197
200 return 0; 198 return 0;
201} 199}
202#else
203int __init omap4_idle_init(void)
204{
205 return 0;
206}
207#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7b4b9327e543..527c0046064d 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -772,7 +772,7 @@ static int __init omap_init_wdt(void)
772 char *oh_name = "wd_timer2"; 772 char *oh_name = "wd_timer2";
773 char *dev_name = "omap_wdt"; 773 char *dev_name = "omap_wdt";
774 774
775 if (!cpu_class_is_omap2()) 775 if (!cpu_class_is_omap2() || of_have_populated_dt())
776 return 0; 776 return 0;
777 777
778 oh = omap_hwmod_lookup(oh_name); 778 oh = omap_hwmod_lookup(oh_name);
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h
index f1e13d1ca5e7..95594495fcf6 100644
--- a/arch/arm/mach-omap2/include/mach/am35xx.h
+++ b/arch/arm/mach-omap2/include/mach/am35xx.h
@@ -36,6 +36,8 @@
36#define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0) 36#define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0)
37#define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000) 37#define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000)
38#define AM35XX_EMAC_MDIO_OFFSET (0x30000) 38#define AM35XX_EMAC_MDIO_OFFSET (0x30000)
39#define AM35XX_IPSS_MDIO_BASE (AM35XX_IPSS_EMAC_BASE + \
40 AM35XX_EMAC_MDIO_OFFSET)
39#define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000) 41#define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000)
40#define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \ 42#define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \
41 AM3517_EMAC_CNTRL_RAM_OFFSET) 43 AM3517_EMAC_CNTRL_RAM_OFFSET)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index d5b34febd82d..a9c26b12cad2 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -262,7 +262,7 @@ int __init omap_intc_of_init(struct device_node *node,
262 struct device_node *parent) 262 struct device_node *parent)
263{ 263{
264 struct resource res; 264 struct resource res;
265 u32 nr_irqs = 96; 265 u32 nr_irq = 96;
266 266
267 if (WARN_ON(!node)) 267 if (WARN_ON(!node))
268 return -ENODEV; 268 return -ENODEV;
@@ -272,10 +272,10 @@ int __init omap_intc_of_init(struct device_node *node,
272 return -EINVAL; 272 return -EINVAL;
273 } 273 }
274 274
275 if (of_property_read_u32(node, "ti,intc-size", &nr_irqs)) 275 if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
276 pr_warn("unable to get intc-size, default to %d\n", nr_irqs); 276 pr_warn("unable to get intc-size, default to %d\n", nr_irq);
277 277
278 omap_init_irq(res.start, nr_irqs, of_node_get(node)); 278 omap_init_irq(res.start, nr_irq, of_node_get(node));
279 279
280 return 0; 280 return 0;
281} 281}
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 19b8b6774862..6875be837d9f 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -83,8 +83,6 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
83 l = mbox_read_reg(MAILBOX_REVISION); 83 l = mbox_read_reg(MAILBOX_REVISION);
84 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); 84 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
85 85
86 omap2_mbox_enable_irq(mbox, IRQ_RX);
87
88 return 0; 86 return 0;
89} 87}
90 88
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index ac49384d0285..1be8bcb52e93 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -73,19 +73,17 @@ static struct iommu_device omap4_devices[] = {
73 .da_end = 0xFFFFF000, 73 .da_end = 0xFFFFF000,
74 }, 74 },
75 }, 75 },
76#if defined(CONFIG_MPU_TESLA_IOMMU)
77 { 76 {
78 .base = OMAP4_MMU2_BASE, 77 .base = OMAP4_MMU2_BASE,
79 .irq = INT_44XX_DSP_MMU, 78 .irq = OMAP44XX_IRQ_TESLA_MMU,
80 .pdata = { 79 .pdata = {
81 .name = "tesla", 80 .name = "tesla",
82 .nr_tlb_entries = 32, 81 .nr_tlb_entries = 32,
83 .clk_name = "tesla_ick", 82 .clk_name = "dsp_fck",
84 .da_start = 0x0, 83 .da_start = 0x0,
85 .da_end = 0xFFFFF000, 84 .da_end = 0xFFFFF000,
86 }, 85 },
87 }, 86 },
88#endif
89}; 87};
90#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices) 88#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
91static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES]; 89static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index ff76ef1d7232..5d82bfca38c3 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1188,15 +1188,18 @@ static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap
1188 * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG 1188 * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
1189 * @oh: struct omap_hwmod * 1189 * @oh: struct omap_hwmod *
1190 * 1190 *
1191 * If module is marked as SWSUP_SIDLE, force the module out of slave 1191 * Ensure that the OCP_SYSCONFIG register for the IP block represented
1192 * idle; otherwise, configure it for smart-idle. If module is marked 1192 * by @oh is set to indicate to the PRCM that the IP block is active.
1193 * as SWSUP_MSUSPEND, force the module out of master standby; 1193 * Usually this means placing the module into smart-idle mode and
1194 * otherwise, configure it for smart-standby. No return value. 1194 * smart-standby, but if there is a bug in the automatic idle handling
1195 * for the IP block, it may need to be placed into the force-idle or
1196 * no-idle variants of these modes. No return value.
1195 */ 1197 */
1196static void _enable_sysc(struct omap_hwmod *oh) 1198static void _enable_sysc(struct omap_hwmod *oh)
1197{ 1199{
1198 u8 idlemode, sf; 1200 u8 idlemode, sf;
1199 u32 v; 1201 u32 v;
1202 bool clkdm_act;
1200 1203
1201 if (!oh->class->sysc) 1204 if (!oh->class->sysc)
1202 return; 1205 return;
@@ -1205,8 +1208,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
1205 sf = oh->class->sysc->sysc_flags; 1208 sf = oh->class->sysc->sysc_flags;
1206 1209
1207 if (sf & SYSC_HAS_SIDLEMODE) { 1210 if (sf & SYSC_HAS_SIDLEMODE) {
1208 idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? 1211 clkdm_act = ((oh->clkdm &&
1209 HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; 1212 oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) ||
1213 (oh->_clk && oh->_clk->clkdm &&
1214 oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU));
1215 if (clkdm_act && !(oh->class->sysc->idlemodes &
1216 (SIDLE_SMART | SIDLE_SMART_WKUP)))
1217 idlemode = HWMOD_IDLEMODE_FORCE;
1218 else
1219 idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
1220 HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
1210 _set_slave_idlemode(oh, idlemode, &v); 1221 _set_slave_idlemode(oh, idlemode, &v);
1211 } 1222 }
1212 1223
@@ -1272,8 +1283,13 @@ static void _idle_sysc(struct omap_hwmod *oh)
1272 sf = oh->class->sysc->sysc_flags; 1283 sf = oh->class->sysc->sysc_flags;
1273 1284
1274 if (sf & SYSC_HAS_SIDLEMODE) { 1285 if (sf & SYSC_HAS_SIDLEMODE) {
1275 idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? 1286 /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */
1276 HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; 1287 if (oh->flags & HWMOD_SWSUP_SIDLE ||
1288 !(oh->class->sysc->idlemodes &
1289 (SIDLE_SMART | SIDLE_SMART_WKUP)))
1290 idlemode = HWMOD_IDLEMODE_FORCE;
1291 else
1292 idlemode = HWMOD_IDLEMODE_SMART;
1277 _set_slave_idlemode(oh, idlemode, &v); 1293 _set_slave_idlemode(oh, idlemode, &v);
1278 } 1294 }
1279 1295
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 6491e057d9ce..cdb9637aab19 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -519,11 +519,27 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
519 519
520static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { 520static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
521 { .irq = INT_35XX_UART4_IRQ, }, 521 { .irq = INT_35XX_UART4_IRQ, },
522 { .irq = -1 }
522}; 523};
523 524
524static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { 525static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
525 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, 526 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
526 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, 527 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
528 { .dma_req = -1 }
529};
530
531/*
532 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
533 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
534 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
535 * should not be needed. The functional clock structure of the AM35xx
536 * UART4 is extremely unclear and opaque; it is unclear what the role
537 * of uart1/2_fck is for the UART4. Any clarification from either
538 * empirical testing or the AM3505/3517 hardware designers would be
539 * most welcome.
540 */
541static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
542 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
527}; 543};
528 544
529static struct omap_hwmod am35xx_uart4_hwmod = { 545static struct omap_hwmod am35xx_uart4_hwmod = {
@@ -535,11 +551,14 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
535 .omap2 = { 551 .omap2 = {
536 .module_offs = CORE_MOD, 552 .module_offs = CORE_MOD,
537 .prcm_reg_id = 1, 553 .prcm_reg_id = 1,
538 .module_bit = OMAP3430_EN_UART4_SHIFT, 554 .module_bit = AM35XX_EN_UART4_SHIFT,
539 .idlest_reg_id = 1, 555 .idlest_reg_id = 1,
540 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, 556 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
541 }, 557 },
542 }, 558 },
559 .opt_clks = am35xx_uart4_opt_clks,
560 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
561 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
543 .class = &omap2_uart_class, 562 .class = &omap2_uart_class,
544}; 563};
545 564
@@ -1651,25 +1670,20 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1651 1670
1652/* usb_otg_hs */ 1671/* usb_otg_hs */
1653static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { 1672static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1654
1655 { .name = "mc", .irq = 71 }, 1673 { .name = "mc", .irq = 71 },
1656 { .irq = -1 } 1674 { .irq = -1 }
1657}; 1675};
1658 1676
1659static struct omap_hwmod_class am35xx_usbotg_class = { 1677static struct omap_hwmod_class am35xx_usbotg_class = {
1660 .name = "am35xx_usbotg", 1678 .name = "am35xx_usbotg",
1661 .sysc = NULL,
1662}; 1679};
1663 1680
1664static struct omap_hwmod am35xx_usbhsotg_hwmod = { 1681static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1665 .name = "am35x_otg_hs", 1682 .name = "am35x_otg_hs",
1666 .mpu_irqs = am35xx_usbhsotg_mpu_irqs, 1683 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1667 .main_clk = NULL, 1684 .main_clk = "hsotgusb_fck",
1668 .prcm = {
1669 .omap2 = {
1670 },
1671 },
1672 .class = &am35xx_usbotg_class, 1685 .class = &am35xx_usbotg_class,
1686 .flags = HWMOD_NO_IDLEST,
1673}; 1687};
1674 1688
1675/* MMC/SD/SDIO common */ 1689/* MMC/SD/SDIO common */
@@ -2110,9 +2124,10 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2110static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { 2124static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2111 .master = &am35xx_usbhsotg_hwmod, 2125 .master = &am35xx_usbhsotg_hwmod,
2112 .slave = &omap3xxx_l3_main_hwmod, 2126 .slave = &omap3xxx_l3_main_hwmod,
2113 .clk = "core_l3_ick", 2127 .clk = "hsotgusb_ick",
2114 .user = OCP_USER_MPU, 2128 .user = OCP_USER_MPU,
2115}; 2129};
2130
2116/* L4_CORE -> L4_WKUP interface */ 2131/* L4_CORE -> L4_WKUP interface */
2117static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 2132static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2118 .master = &omap3xxx_l4_core_hwmod, 2133 .master = &omap3xxx_l4_core_hwmod,
@@ -2256,6 +2271,7 @@ static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2256 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, 2271 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2257 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2258 }, 2273 },
2274 { }
2259}; 2275};
2260 2276
2261static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 2277static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
@@ -2406,7 +2422,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2406static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 2422static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2407 .master = &omap3xxx_l4_core_hwmod, 2423 .master = &omap3xxx_l4_core_hwmod,
2408 .slave = &am35xx_usbhsotg_hwmod, 2424 .slave = &am35xx_usbhsotg_hwmod,
2409 .clk = "l4_ick", 2425 .clk = "hsotgusb_ick",
2410 .addr = am35xx_usbhsotg_addrs, 2426 .addr = am35xx_usbhsotg_addrs,
2411 .user = OCP_USER_MPU, 2427 .user = OCP_USER_MPU,
2412}; 2428};
@@ -3151,6 +3167,107 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3151 .user = OCP_USER_MPU | OCP_USER_SDMA, 3167 .user = OCP_USER_MPU | OCP_USER_SDMA,
3152}; 3168};
3153 3169
3170/* am35xx has Davinci MDIO & EMAC */
3171static struct omap_hwmod_class am35xx_mdio_class = {
3172 .name = "davinci_mdio",
3173};
3174
3175static struct omap_hwmod am35xx_mdio_hwmod = {
3176 .name = "davinci_mdio",
3177 .class = &am35xx_mdio_class,
3178 .flags = HWMOD_NO_IDLEST,
3179};
3180
3181/*
3182 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3183 * but this will probably require some additional hwmod core support,
3184 * so is left as a future to-do item.
3185 */
3186static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3187 .master = &am35xx_mdio_hwmod,
3188 .slave = &omap3xxx_l3_main_hwmod,
3189 .clk = "emac_fck",
3190 .user = OCP_USER_MPU,
3191};
3192
3193static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3194 {
3195 .pa_start = AM35XX_IPSS_MDIO_BASE,
3196 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3197 .flags = ADDR_TYPE_RT,
3198 },
3199 { }
3200};
3201
3202/* l4_core -> davinci mdio */
3203/*
3204 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3205 * but this will probably require some additional hwmod core support,
3206 * so is left as a future to-do item.
3207 */
3208static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3209 .master = &omap3xxx_l4_core_hwmod,
3210 .slave = &am35xx_mdio_hwmod,
3211 .clk = "emac_fck",
3212 .addr = am35xx_mdio_addrs,
3213 .user = OCP_USER_MPU,
3214};
3215
3216static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3217 { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
3218 { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
3219 { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
3220 { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
3221 { .irq = -1 }
3222};
3223
3224static struct omap_hwmod_class am35xx_emac_class = {
3225 .name = "davinci_emac",
3226};
3227
3228static struct omap_hwmod am35xx_emac_hwmod = {
3229 .name = "davinci_emac",
3230 .mpu_irqs = am35xx_emac_mpu_irqs,
3231 .class = &am35xx_emac_class,
3232 .flags = HWMOD_NO_IDLEST,
3233};
3234
3235/* l3_core -> davinci emac interface */
3236/*
3237 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3238 * but this will probably require some additional hwmod core support,
3239 * so is left as a future to-do item.
3240 */
3241static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3242 .master = &am35xx_emac_hwmod,
3243 .slave = &omap3xxx_l3_main_hwmod,
3244 .clk = "emac_ick",
3245 .user = OCP_USER_MPU,
3246};
3247
3248static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3249 {
3250 .pa_start = AM35XX_IPSS_EMAC_BASE,
3251 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3252 .flags = ADDR_TYPE_RT,
3253 },
3254 { }
3255};
3256
3257/* l4_core -> davinci emac */
3258/*
3259 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3260 * but this will probably require some additional hwmod core support,
3261 * so is left as a future to-do item.
3262 */
3263static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3264 .master = &omap3xxx_l4_core_hwmod,
3265 .slave = &am35xx_emac_hwmod,
3266 .clk = "emac_ick",
3267 .addr = am35xx_emac_addrs,
3268 .user = OCP_USER_MPU,
3269};
3270
3154static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 3271static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3155 &omap3xxx_l3_main__l4_core, 3272 &omap3xxx_l3_main__l4_core,
3156 &omap3xxx_l3_main__l4_per, 3273 &omap3xxx_l3_main__l4_per,
@@ -3279,6 +3396,10 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3279 &omap3xxx_l4_core__usb_tll_hs, 3396 &omap3xxx_l4_core__usb_tll_hs,
3280 &omap3xxx_l4_core__es3plus_mmc1, 3397 &omap3xxx_l4_core__es3plus_mmc1,
3281 &omap3xxx_l4_core__es3plus_mmc2, 3398 &omap3xxx_l4_core__es3plus_mmc2,
3399 &am35xx_mdio__l3,
3400 &am35xx_l4_core__mdio,
3401 &am35xx_emac__l3,
3402 &am35xx_l4_core__emac,
3282 NULL 3403 NULL
3283}; 3404};
3284 3405
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 1b1d04141c3d..5c2ce7e77838 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1928,7 +1928,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1928 1928
1929static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { 1929static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1930 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1930 { .role = "pad_fck", .clk = "pad_clks_ck" },
1931 { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, 1931 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1932}; 1932};
1933 1933
1934static struct omap_hwmod omap44xx_mcbsp1_hwmod = { 1934static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
@@ -1963,7 +1963,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1963 1963
1964static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { 1964static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1965 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1965 { .role = "pad_fck", .clk = "pad_clks_ck" },
1966 { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, 1966 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1967}; 1967};
1968 1968
1969static struct omap_hwmod omap44xx_mcbsp2_hwmod = { 1969static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
@@ -1998,7 +1998,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1998 1998
1999static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { 1999static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2000 { .role = "pad_fck", .clk = "pad_clks_ck" }, 2000 { .role = "pad_fck", .clk = "pad_clks_ck" },
2001 { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, 2001 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2002}; 2002};
2003 2003
2004static struct omap_hwmod omap44xx_mcbsp3_hwmod = { 2004static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
@@ -2033,7 +2033,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2033 2033
2034static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { 2034static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2035 { .role = "pad_fck", .clk = "pad_clks_ck" }, 2035 { .role = "pad_fck", .clk = "pad_clks_ck" },
2036 { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, 2036 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2037}; 2037};
2038 2038
2039static struct omap_hwmod omap44xx_mcbsp4_hwmod = { 2039static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
@@ -3855,7 +3855,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3855}; 3855};
3856 3856
3857/* usb_host_fs -> l3_main_2 */ 3857/* usb_host_fs -> l3_main_2 */
3858static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = { 3858static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3859 .master = &omap44xx_usb_host_fs_hwmod, 3859 .master = &omap44xx_usb_host_fs_hwmod,
3860 .slave = &omap44xx_l3_main_2_hwmod, 3860 .slave = &omap44xx_l3_main_2_hwmod,
3861 .clk = "l3_div_ck", 3861 .clk = "l3_div_ck",
@@ -3913,7 +3913,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3913}; 3913};
3914 3914
3915/* aess -> l4_abe */ 3915/* aess -> l4_abe */
3916static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { 3916static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3917 .master = &omap44xx_aess_hwmod, 3917 .master = &omap44xx_aess_hwmod,
3918 .slave = &omap44xx_l4_abe_hwmod, 3918 .slave = &omap44xx_l4_abe_hwmod,
3919 .clk = "ocp_abe_iclk", 3919 .clk = "ocp_abe_iclk",
@@ -4004,7 +4004,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4004}; 4004};
4005 4005
4006/* l4_abe -> aess */ 4006/* l4_abe -> aess */
4007static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { 4007static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4008 .master = &omap44xx_l4_abe_hwmod, 4008 .master = &omap44xx_l4_abe_hwmod,
4009 .slave = &omap44xx_aess_hwmod, 4009 .slave = &omap44xx_aess_hwmod,
4010 .clk = "ocp_abe_iclk", 4010 .clk = "ocp_abe_iclk",
@@ -4022,7 +4022,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4022}; 4022};
4023 4023
4024/* l4_abe -> aess (dma) */ 4024/* l4_abe -> aess (dma) */
4025static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { 4025static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4026 .master = &omap44xx_l4_abe_hwmod, 4026 .master = &omap44xx_l4_abe_hwmod,
4027 .slave = &omap44xx_aess_hwmod, 4027 .slave = &omap44xx_aess_hwmod,
4028 .clk = "ocp_abe_iclk", 4028 .clk = "ocp_abe_iclk",
@@ -5848,7 +5848,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5848}; 5848};
5849 5849
5850/* l4_cfg -> usb_host_fs */ 5850/* l4_cfg -> usb_host_fs */
5851static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = { 5851static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5852 .master = &omap44xx_l4_cfg_hwmod, 5852 .master = &omap44xx_l4_cfg_hwmod,
5853 .slave = &omap44xx_usb_host_fs_hwmod, 5853 .slave = &omap44xx_usb_host_fs_hwmod,
5854 .clk = "l4_div_ck", 5854 .clk = "l4_div_ck",
@@ -6005,13 +6005,13 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6005 &omap44xx_iva__l3_main_2, 6005 &omap44xx_iva__l3_main_2,
6006 &omap44xx_l3_main_1__l3_main_2, 6006 &omap44xx_l3_main_1__l3_main_2,
6007 &omap44xx_l4_cfg__l3_main_2, 6007 &omap44xx_l4_cfg__l3_main_2,
6008 &omap44xx_usb_host_fs__l3_main_2, 6008 /* &omap44xx_usb_host_fs__l3_main_2, */
6009 &omap44xx_usb_host_hs__l3_main_2, 6009 &omap44xx_usb_host_hs__l3_main_2,
6010 &omap44xx_usb_otg_hs__l3_main_2, 6010 &omap44xx_usb_otg_hs__l3_main_2,
6011 &omap44xx_l3_main_1__l3_main_3, 6011 &omap44xx_l3_main_1__l3_main_3,
6012 &omap44xx_l3_main_2__l3_main_3, 6012 &omap44xx_l3_main_2__l3_main_3,
6013 &omap44xx_l4_cfg__l3_main_3, 6013 &omap44xx_l4_cfg__l3_main_3,
6014 &omap44xx_aess__l4_abe, 6014 /* &omap44xx_aess__l4_abe, */
6015 &omap44xx_dsp__l4_abe, 6015 &omap44xx_dsp__l4_abe,
6016 &omap44xx_l3_main_1__l4_abe, 6016 &omap44xx_l3_main_1__l4_abe,
6017 &omap44xx_mpu__l4_abe, 6017 &omap44xx_mpu__l4_abe,
@@ -6020,8 +6020,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6020 &omap44xx_l4_cfg__l4_wkup, 6020 &omap44xx_l4_cfg__l4_wkup,
6021 &omap44xx_mpu__mpu_private, 6021 &omap44xx_mpu__mpu_private,
6022 &omap44xx_l4_cfg__ocp_wp_noc, 6022 &omap44xx_l4_cfg__ocp_wp_noc,
6023 &omap44xx_l4_abe__aess, 6023 /* &omap44xx_l4_abe__aess, */
6024 &omap44xx_l4_abe__aess_dma, 6024 /* &omap44xx_l4_abe__aess_dma, */
6025 &omap44xx_l3_main_2__c2c, 6025 &omap44xx_l3_main_2__c2c,
6026 &omap44xx_l4_wkup__counter_32k, 6026 &omap44xx_l4_wkup__counter_32k,
6027 &omap44xx_l4_cfg__ctrl_module_core, 6027 &omap44xx_l4_cfg__ctrl_module_core,
@@ -6127,7 +6127,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6127 &omap44xx_l4_per__uart2, 6127 &omap44xx_l4_per__uart2,
6128 &omap44xx_l4_per__uart3, 6128 &omap44xx_l4_per__uart3,
6129 &omap44xx_l4_per__uart4, 6129 &omap44xx_l4_per__uart4,
6130 &omap44xx_l4_cfg__usb_host_fs, 6130 /* &omap44xx_l4_cfg__usb_host_fs, */
6131 &omap44xx_l4_cfg__usb_host_hs, 6131 &omap44xx_l4_cfg__usb_host_hs,
6132 &omap44xx_l4_cfg__usb_otg_hs, 6132 &omap44xx_l4_cfg__usb_otg_hs,
6133 &omap44xx_l4_cfg__usb_tll_hs, 6133 &omap44xx_l4_cfg__usb_tll_hs,
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index de6d46451746..d8f6dbf45d16 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -53,7 +53,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
53 omap_table_init = 1; 53 omap_table_init = 1;
54 54
55 /* Lets now register with OPP library */ 55 /* Lets now register with OPP library */
56 for (i = 0; i < opp_def_size; i++) { 56 for (i = 0; i < opp_def_size; i++, opp_def++) {
57 struct omap_hwmod *oh; 57 struct omap_hwmod *oh;
58 struct device *dev; 58 struct device *dev;
59 59
@@ -86,7 +86,6 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
86 __func__, opp_def->freq, 86 __func__, opp_def->freq,
87 opp_def->hwmod_name, i, r); 87 opp_def->hwmod_name, i, r);
88 } 88 }
89 opp_def++;
90 } 89 }
91 90
92 return 0; 91 return 0;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 78564895e914..ab04d3bba2e7 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -15,12 +15,25 @@
15 15
16#include "powerdomain.h" 16#include "powerdomain.h"
17 17
18#ifdef CONFIG_CPU_IDLE
19extern int __init omap3_idle_init(void);
20extern int __init omap4_idle_init(void);
21#else
22static inline int omap3_idle_init(void)
23{
24 return 0;
25}
26
27static inline int omap4_idle_init(void)
28{
29 return 0;
30}
31#endif
32
18extern void *omap3_secure_ram_storage; 33extern void *omap3_secure_ram_storage;
19extern void omap3_pm_off_mode_enable(int); 34extern void omap3_pm_off_mode_enable(int);
20extern void omap_sram_idle(void); 35extern void omap_sram_idle(void);
21extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); 36extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
22extern int omap3_idle_init(void);
23extern int omap4_idle_init(void);
24extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); 37extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
25extern int (*omap_pm_suspend)(void); 38extern int (*omap_pm_suspend)(void);
26 39
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3a595e899724..9b463c987508 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -581,10 +581,13 @@ static void __init prcm_setup_regs(void)
581 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 581 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
582 582
583 /* Don't attach IVA interrupts */ 583 /* Don't attach IVA interrupts */
584 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 584 if (omap3_has_iva()) {
585 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); 585 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
586 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 586 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
587 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 587 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
588 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
589 OMAP3430_PM_IVAGRPSEL);
590 }
588 591
589 /* Clear any pending 'reset' flags */ 592 /* Clear any pending 'reset' flags */
590 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); 593 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
@@ -598,7 +601,9 @@ static void __init prcm_setup_regs(void)
598 /* Clear any pending PRCM interrupts */ 601 /* Clear any pending PRCM interrupts */
599 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 602 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
600 603
601 omap3_iva_idle(); 604 if (omap3_has_iva())
605 omap3_iva_idle();
606
602 omap3_d2d_idle(); 607 omap3_d2d_idle();
603} 608}
604 609
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index fb0a0a6869d1..bb883e463078 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -71,6 +71,22 @@ static struct powerdomain mpu_3xxx_pwrdm = {
71 .voltdm = { .name = "mpu_iva" }, 71 .voltdm = { .name = "mpu_iva" },
72}; 72};
73 73
74static struct powerdomain mpu_am35x_pwrdm = {
75 .name = "mpu_pwrdm",
76 .prcm_offs = MPU_MOD,
77 .pwrsts = PWRSTS_ON,
78 .pwrsts_logic_ret = PWRSTS_ON,
79 .flags = PWRDM_HAS_MPU_QUIRK,
80 .banks = 1,
81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_ON,
83 },
84 .pwrsts_mem_on = {
85 [0] = PWRSTS_ON,
86 },
87 .voltdm = { .name = "mpu_iva" },
88};
89
74/* 90/*
75 * The USBTLL Save-and-Restore mechanism is broken on 91 * The USBTLL Save-and-Restore mechanism is broken on
76 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature 92 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
@@ -120,6 +136,23 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
120 .voltdm = { .name = "core" }, 136 .voltdm = { .name = "core" },
121}; 137};
122 138
139static struct powerdomain core_am35x_pwrdm = {
140 .name = "core_pwrdm",
141 .prcm_offs = CORE_MOD,
142 .pwrsts = PWRSTS_ON,
143 .pwrsts_logic_ret = PWRSTS_ON,
144 .banks = 2,
145 .pwrsts_mem_ret = {
146 [0] = PWRSTS_ON, /* MEM1RETSTATE */
147 [1] = PWRSTS_ON, /* MEM2RETSTATE */
148 },
149 .pwrsts_mem_on = {
150 [0] = PWRSTS_ON, /* MEM1ONSTATE */
151 [1] = PWRSTS_ON, /* MEM2ONSTATE */
152 },
153 .voltdm = { .name = "core" },
154};
155
123static struct powerdomain dss_pwrdm = { 156static struct powerdomain dss_pwrdm = {
124 .name = "dss_pwrdm", 157 .name = "dss_pwrdm",
125 .prcm_offs = OMAP3430_DSS_MOD, 158 .prcm_offs = OMAP3430_DSS_MOD,
@@ -135,6 +168,21 @@ static struct powerdomain dss_pwrdm = {
135 .voltdm = { .name = "core" }, 168 .voltdm = { .name = "core" },
136}; 169};
137 170
171static struct powerdomain dss_am35x_pwrdm = {
172 .name = "dss_pwrdm",
173 .prcm_offs = OMAP3430_DSS_MOD,
174 .pwrsts = PWRSTS_ON,
175 .pwrsts_logic_ret = PWRSTS_ON,
176 .banks = 1,
177 .pwrsts_mem_ret = {
178 [0] = PWRSTS_ON, /* MEMRETSTATE */
179 },
180 .pwrsts_mem_on = {
181 [0] = PWRSTS_ON, /* MEMONSTATE */
182 },
183 .voltdm = { .name = "core" },
184};
185
138/* 186/*
139 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a 187 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
140 * possible SGX powerstate, the SGX device itself does not support 188 * possible SGX powerstate, the SGX device itself does not support
@@ -156,6 +204,21 @@ static struct powerdomain sgx_pwrdm = {
156 .voltdm = { .name = "core" }, 204 .voltdm = { .name = "core" },
157}; 205};
158 206
207static struct powerdomain sgx_am35x_pwrdm = {
208 .name = "sgx_pwrdm",
209 .prcm_offs = OMAP3430ES2_SGX_MOD,
210 .pwrsts = PWRSTS_ON,
211 .pwrsts_logic_ret = PWRSTS_ON,
212 .banks = 1,
213 .pwrsts_mem_ret = {
214 [0] = PWRSTS_ON, /* MEMRETSTATE */
215 },
216 .pwrsts_mem_on = {
217 [0] = PWRSTS_ON, /* MEMONSTATE */
218 },
219 .voltdm = { .name = "core" },
220};
221
159static struct powerdomain cam_pwrdm = { 222static struct powerdomain cam_pwrdm = {
160 .name = "cam_pwrdm", 223 .name = "cam_pwrdm",
161 .prcm_offs = OMAP3430_CAM_MOD, 224 .prcm_offs = OMAP3430_CAM_MOD,
@@ -186,6 +249,21 @@ static struct powerdomain per_pwrdm = {
186 .voltdm = { .name = "core" }, 249 .voltdm = { .name = "core" },
187}; 250};
188 251
252static struct powerdomain per_am35x_pwrdm = {
253 .name = "per_pwrdm",
254 .prcm_offs = OMAP3430_PER_MOD,
255 .pwrsts = PWRSTS_ON,
256 .pwrsts_logic_ret = PWRSTS_ON,
257 .banks = 1,
258 .pwrsts_mem_ret = {
259 [0] = PWRSTS_ON, /* MEMRETSTATE */
260 },
261 .pwrsts_mem_on = {
262 [0] = PWRSTS_ON, /* MEMONSTATE */
263 },
264 .voltdm = { .name = "core" },
265};
266
189static struct powerdomain emu_pwrdm = { 267static struct powerdomain emu_pwrdm = {
190 .name = "emu_pwrdm", 268 .name = "emu_pwrdm",
191 .prcm_offs = OMAP3430_EMU_MOD, 269 .prcm_offs = OMAP3430_EMU_MOD,
@@ -200,6 +278,14 @@ static struct powerdomain neon_pwrdm = {
200 .voltdm = { .name = "mpu_iva" }, 278 .voltdm = { .name = "mpu_iva" },
201}; 279};
202 280
281static struct powerdomain neon_am35x_pwrdm = {
282 .name = "neon_pwrdm",
283 .prcm_offs = OMAP3430_NEON_MOD,
284 .pwrsts = PWRSTS_ON,
285 .pwrsts_logic_ret = PWRSTS_ON,
286 .voltdm = { .name = "mpu_iva" },
287};
288
203static struct powerdomain usbhost_pwrdm = { 289static struct powerdomain usbhost_pwrdm = {
204 .name = "usbhost_pwrdm", 290 .name = "usbhost_pwrdm",
205 .prcm_offs = OMAP3430ES2_USBHOST_MOD, 291 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
@@ -293,6 +379,22 @@ static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
293 NULL 379 NULL
294}; 380};
295 381
382static struct powerdomain *powerdomains_am35x[] __initdata = {
383 &wkup_omap2_pwrdm,
384 &mpu_am35x_pwrdm,
385 &neon_am35x_pwrdm,
386 &core_am35x_pwrdm,
387 &sgx_am35x_pwrdm,
388 &dss_am35x_pwrdm,
389 &per_am35x_pwrdm,
390 &emu_pwrdm,
391 &dpll1_pwrdm,
392 &dpll3_pwrdm,
393 &dpll4_pwrdm,
394 &dpll5_pwrdm,
395 NULL
396};
397
296void __init omap3xxx_powerdomains_init(void) 398void __init omap3xxx_powerdomains_init(void)
297{ 399{
298 unsigned int rev; 400 unsigned int rev;
@@ -301,21 +403,34 @@ void __init omap3xxx_powerdomains_init(void)
301 return; 403 return;
302 404
303 pwrdm_register_platform_funcs(&omap3_pwrdm_operations); 405 pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
304 pwrdm_register_pwrdms(powerdomains_omap3430_common);
305 406
306 rev = omap_rev(); 407 rev = omap_rev();
307 408
308 if (rev == OMAP3430_REV_ES1_0) 409 if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
309 pwrdm_register_pwrdms(powerdomains_omap3430es1); 410 pwrdm_register_pwrdms(powerdomains_am35x);
310 else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 411 } else {
311 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0) 412 pwrdm_register_pwrdms(powerdomains_omap3430_common);
312 pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); 413
313 else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 || 414 switch (rev) {
314 rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 || 415 case OMAP3430_REV_ES1_0:
315 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) 416 pwrdm_register_pwrdms(powerdomains_omap3430es1);
316 pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); 417 break;
317 else 418 case OMAP3430_REV_ES2_0:
318 WARN(1, "OMAP3 powerdomain init: unknown chip type\n"); 419 case OMAP3430_REV_ES2_1:
420 case OMAP3430_REV_ES3_0:
421 case OMAP3630_REV_ES1_0:
422 pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
423 break;
424 case OMAP3430_REV_ES3_1:
425 case OMAP3430_REV_ES3_1_2:
426 case OMAP3630_REV_ES1_1:
427 case OMAP3630_REV_ES1_2:
428 pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
429 break;
430 default:
431 WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
432 }
433 }
319 434
320 pwrdm_complete_init(); 435 pwrdm_complete_init();
321} 436}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6da3ba483ad1..cc1398e8b469 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -203,8 +203,8 @@
203#define OMAP3430_EN_MMC2_SHIFT 25 203#define OMAP3430_EN_MMC2_SHIFT 25
204#define OMAP3430_EN_MMC1_MASK (1 << 24) 204#define OMAP3430_EN_MMC1_MASK (1 << 24)
205#define OMAP3430_EN_MMC1_SHIFT 24 205#define OMAP3430_EN_MMC1_SHIFT 24
206#define OMAP3430_EN_UART4_MASK (1 << 23) 206#define AM35XX_EN_UART4_MASK (1 << 23)
207#define OMAP3430_EN_UART4_SHIFT 23 207#define AM35XX_EN_UART4_SHIFT 23
208#define OMAP3430_EN_MCSPI4_MASK (1 << 21) 208#define OMAP3430_EN_MCSPI4_MASK (1 << 21)
209#define OMAP3430_EN_MCSPI4_SHIFT 21 209#define OMAP3430_EN_MCSPI4_SHIFT 21
210#define OMAP3430_EN_MCSPI3_MASK (1 << 20) 210#define OMAP3430_EN_MCSPI3_MASK (1 << 20)
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 663ade3b2f45..03b126d9ad94 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -85,7 +85,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
85 unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG]; 85 unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
86 struct irq_chip *chip = irq_desc_get_chip(desc); 86 struct irq_chip *chip = irq_desc_get_chip(desc);
87 unsigned int virtirq; 87 unsigned int virtirq;
88 int nr_irqs = prcm_irq_setup->nr_regs * 32; 88 int nr_irq = prcm_irq_setup->nr_regs * 32;
89 89
90 /* 90 /*
91 * If we are suspended, mask all interrupts from PRCM level, 91 * If we are suspended, mask all interrupts from PRCM level,
@@ -110,7 +110,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
110 prcm_irq_setup->read_pending_irqs(pending); 110 prcm_irq_setup->read_pending_irqs(pending);
111 111
112 /* No bit set, then all IRQs are handled */ 112 /* No bit set, then all IRQs are handled */
113 if (find_first_bit(pending, nr_irqs) >= nr_irqs) 113 if (find_first_bit(pending, nr_irq) >= nr_irq)
114 break; 114 break;
115 115
116 omap_prcm_events_filter_priority(pending, priority_pending); 116 omap_prcm_events_filter_priority(pending, priority_pending);
@@ -121,11 +121,11 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
121 */ 121 */
122 122
123 /* Serve priority events first */ 123 /* Serve priority events first */
124 for_each_set_bit(virtirq, priority_pending, nr_irqs) 124 for_each_set_bit(virtirq, priority_pending, nr_irq)
125 generic_handle_irq(prcm_irq_setup->base_irq + virtirq); 125 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
126 126
127 /* Serve normal events next */ 127 /* Serve normal events next */
128 for_each_set_bit(virtirq, pending, nr_irqs) 128 for_each_set_bit(virtirq, pending, nr_irq)
129 generic_handle_irq(prcm_irq_setup->base_irq + virtirq); 129 generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
130 } 130 }
131 if (chip->irq_ack) 131 if (chip->irq_ack)
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 119d5a910f3a..3882f3c7608c 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -32,6 +32,7 @@
32#include "twl-common.h" 32#include "twl-common.h"
33#include "pm.h" 33#include "pm.h"
34#include "voltage.h" 34#include "voltage.h"
35#include "mux.h"
35 36
36static struct i2c_board_info __initdata pmic_i2c_board_info = { 37static struct i2c_board_info __initdata pmic_i2c_board_info = {
37 .addr = 0x48, 38 .addr = 0x48,
@@ -48,6 +49,7 @@ static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
48 }, 49 },
49}; 50};
50 51
52#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
51static int twl_set_voltage(void *data, int target_uV) 53static int twl_set_voltage(void *data, int target_uV)
52{ 54{
53 struct voltagedomain *voltdm = (struct voltagedomain *)data; 55 struct voltagedomain *voltdm = (struct voltagedomain *)data;
@@ -59,6 +61,7 @@ static int twl_get_voltage(void *data)
59 struct voltagedomain *voltdm = (struct voltagedomain *)data; 61 struct voltagedomain *voltdm = (struct voltagedomain *)data;
60 return voltdm_get_voltage(voltdm); 62 return voltdm_get_voltage(voltdm);
61} 63}
64#endif
62 65
63void __init omap_pmic_init(int bus, u32 clkrate, 66void __init omap_pmic_init(int bus, u32 clkrate,
64 const char *pmic_type, int pmic_irq, 67 const char *pmic_type, int pmic_irq,
@@ -77,6 +80,7 @@ void __init omap4_pmic_init(const char *pmic_type,
77 struct twl6040_platform_data *twl6040_data, int twl6040_irq) 80 struct twl6040_platform_data *twl6040_data, int twl6040_irq)
78{ 81{
79 /* PMIC part*/ 82 /* PMIC part*/
83 omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
80 strncpy(omap4_i2c1_board_info[0].type, pmic_type, 84 strncpy(omap4_i2c1_board_info[0].type, pmic_type,
81 sizeof(omap4_i2c1_board_info[0].type)); 85 sizeof(omap4_i2c1_board_info[0].type));
82 omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N; 86 omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
@@ -211,10 +215,6 @@ static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
211void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, 215void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
212 u32 pdata_flags, u32 regulators_flags) 216 u32 pdata_flags, u32 regulators_flags)
213{ 217{
214 if (!pmic_data->irq_base)
215 pmic_data->irq_base = TWL4030_IRQ_BASE;
216 if (!pmic_data->irq_end)
217 pmic_data->irq_end = TWL4030_IRQ_END;
218 if (!pmic_data->vdd1) { 218 if (!pmic_data->vdd1) {
219 omap3_vdd1.driver_data = &omap3_vdd1_drvdata; 219 omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
220 omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva"); 220 omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
@@ -479,11 +479,6 @@ static struct regulator_init_data omap4_v2v1_idata = {
479void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, 479void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
480 u32 pdata_flags, u32 regulators_flags) 480 u32 pdata_flags, u32 regulators_flags)
481{ 481{
482 if (!pmic_data->irq_base)
483 pmic_data->irq_base = TWL6030_IRQ_BASE;
484 if (!pmic_data->irq_end)
485 pmic_data->irq_end = TWL6030_IRQ_END;
486
487 if (!pmic_data->vdd1) { 482 if (!pmic_data->vdd1) {
488 omap4_vdd1.driver_data = &omap4_vdd1_drvdata; 483 omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
489 omap4_vdd1_drvdata.data = voltdm_lookup("mpu"); 484 omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 17:16:39 -0400