6 files changed, 42 insertions, 28 deletions

diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 476b82066cb6..7f091c85384e 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -958,6 +958,14 @@ int __init am33xx_clk_init(void)
 
         clk_set_parent(&timer3_fck, &sys_clkin_ck);
         clk_set_parent(&timer6_fck, &sys_clkin_ck);
+        /*
+         * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+         * the design/spec, so as a result, for example, timer which supposed
+         * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+         * not expected by any use-case, so change WDT1 clock source to PRCM
+         * 32KHz clock.
+         */
+        clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3aed4b0b9563..6e9873ff1844 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -480,20 +480,22 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
         if (!dd)
                 return -EINVAL;
 
-        __clk_prepare(dd->clk_bypass);
-        clk_enable(dd->clk_bypass);
-        __clk_prepare(dd->clk_ref);
-        clk_enable(dd->clk_ref);
-
         if (__clk_get_rate(dd->clk_bypass) == rate &&
             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
                 pr_debug("%s: %s: set rate: entering bypass.\n",
                          __func__, __clk_get_name(hw->clk));
 
+                __clk_prepare(dd->clk_bypass);
+                clk_enable(dd->clk_bypass);
                 ret = _omap3_noncore_dpll_bypass(clk);
                 if (!ret)
                         new_parent = dd->clk_bypass;
+                clk_disable(dd->clk_bypass);
+                __clk_unprepare(dd->clk_bypass);
         } else {
+                __clk_prepare(dd->clk_ref);
+                clk_enable(dd->clk_ref);
+
                 if (dd->last_rounded_rate != rate)
                         rate = __clk_round_rate(hw->clk, rate);
 
@@ -514,6 +516,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
                 ret = omap3_noncore_dpll_program(clk, freqsel);
                 if (!ret)
                         new_parent = dd->clk_ref;
+                clk_disable(dd->clk_ref);
+                __clk_unprepare(dd->clk_ref);
         }
         /*
         * FIXME - this is all wrong.  common code handles reparenting and
@@ -525,11 +529,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
         if (!ret)
                 __clk_reparent(hw->clk, new_parent);
 
-        clk_disable(dd->clk_ref);
-        __clk_unprepare(dd->clk_ref);
-        clk_disable(dd->clk_bypass);
-        __clk_unprepare(dd->clk_bypass);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c2c798c08c2b..e5cafed8ef25 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -610,8 +610,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
-        oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
-
         return 0;
 }
 
@@ -645,8 +643,6 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
-        oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d43d9b608eda..28f4dea0512e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -477,15 +477,13 @@ struct omap_hwmod_omap4_prcm {
  * These are for internal use only and are managed by the omap_hwmod code.
  *
  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
- * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
  * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
  *     causes the first call to _enable() to only update the pinmux
  */
 #define _HWMOD_NO_MPU_PORT                      (1 << 0)
-#define _HWMOD_WAKEUP_ENABLED                   (1 << 1)
-#define _HWMOD_SYSCONFIG_LOADED                 (1 << 2)
-#define _HWMOD_SKIP_ENABLE                      (1 << 3)
+#define _HWMOD_SYSCONFIG_LOADED                 (1 << 1)
+#define _HWMOD_SKIP_ENABLE                      (1 << 2)
 
 /*
  * omap_hwmod._state definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 26eee4a556ad..31bea1ce3de1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -28,6 +28,7 @@
 #include "prm-regbits-33xx.h"
 #include "i2c.h"
 #include "mmc.h"
+#include "wd_timer.h"
 
 /*
  * IP blocks
@@ -2087,8 +2088,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
 };
 
 /* 'wd_timer' class */
+static struct omap_hwmod_class_sysconfig wdt_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
         .name           = "wd_timer",
+        .sysc           = &wdt_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
 };
 
 /*
@@ -2099,6 +2113,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = {
         .name           = "wd_timer2",
         .class          = &am33xx_wd_timer_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
         .main_clk       = "wdt1_fck",
         .prcm           = {
                 .omap4  = {
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 8e61d80bf6b3..89cad4a605dd 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -52,7 +52,6 @@ enum {
 #define ALREADYACTIVE_SWITCH            0
 #define FORCEWAKEUP_SWITCH              1
 #define LOWPOWERSTATE_SWITCH            2
-#define ERROR_SWITCH                    3
 
 /* pwrdm_list contains all registered struct powerdomains */
 static LIST_HEAD(pwrdm_list);
@@ -233,10 +232,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
 {
         u8 sleep_switch;
 
-        if (curr_pwrst < 0) {
-                WARN_ON(1);
-                sleep_switch = ERROR_SWITCH;
-        } else if (curr_pwrst < PWRDM_POWER_ON) {
+        if (curr_pwrst < PWRDM_POWER_ON) {
                 if (curr_pwrst > pwrst &&
                     pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
                     arch_pwrdm->pwrdm_set_lowpwrstchange) {
@@ -1091,7 +1087,8 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
  */
 int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
 {
-        u8 curr_pwrst, next_pwrst, sleep_switch;
+        u8 next_pwrst, sleep_switch;
+        int curr_pwrst;
         int ret = 0;
         bool hwsup = false;
 
@@ -1107,16 +1104,17 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
         pwrdm_lock(pwrdm);
 
         curr_pwrst = pwrdm_read_pwrst(pwrdm);
+        if (curr_pwrst < 0) {
+                ret = -EINVAL;
+                goto osps_out;
+        }
+
         next_pwrst = pwrdm_read_next_pwrst(pwrdm);
         if (curr_pwrst == pwrst && next_pwrst == pwrst)
                 goto osps_out;
 
         sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
                                                             pwrst, &hwsup);
-        if (sleep_switch == ERROR_SWITCH) {
-                ret = -EINVAL;
-                goto osps_out;
-        }
 
         ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
         if (ret)