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-rw-r--r--arch/arm/mach-omap2/Kconfig12
-rw-r--r--arch/arm/mach-omap2/Makefile10
-rw-r--r--arch/arm/mach-omap2/board-generic.c19
-rw-r--r--arch/arm/mach-omap2/clockdomain.h1
-rw-r--r--arch/arm/mach-omap2/clockdomains7xx_data.c740
-rw-r--r--arch/arm/mach-omap2/cm-regbits-7xx.h51
-rw-r--r--arch/arm/mach-omap2/cm1_7xx.h324
-rw-r--r--arch/arm/mach-omap2/cm2_7xx.h513
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/id.c4
-rw-r--r--arch/arm/mach-omap2/io.c25
-rw-r--r--arch/arm/mach-omap2/omap54xx.h4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c2724
-rw-r--r--arch/arm/mach-omap2/powerdomain.h1
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c454
-rw-r--r--arch/arm/mach-omap2/prcm44xx.h5
-rw-r--r--arch/arm/mach-omap2/prcm_mpu7xx.h78
-rw-r--r--arch/arm/mach-omap2/prm44xx.c12
-rw-r--r--arch/arm/mach-omap2/prm7xx.h678
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c20
-rw-r--r--arch/arm/mach-omap2/soc.h17
-rw-r--r--arch/arm/mach-omap2/timer.c3
24 files changed, 5686 insertions, 13 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 3eed0006d189..740f41b08b74 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -118,7 +118,7 @@ config ARCH_OMAP2PLUS_TYPICAL
118 select I2C 118 select I2C
119 select I2C_OMAP 119 select I2C_OMAP
120 select MENELAUS if ARCH_OMAP2 120 select MENELAUS if ARCH_OMAP2
121 select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 121 select NEON if CPU_V7
122 select PM_RUNTIME 122 select PM_RUNTIME
123 select REGULATOR 123 select REGULATOR
124 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 124 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
@@ -132,9 +132,17 @@ config SOC_HAS_OMAP2_SDRC
132 132
133config SOC_HAS_REALTIME_COUNTER 133config SOC_HAS_REALTIME_COUNTER
134 bool "Real time free running counter" 134 bool "Real time free running counter"
135 depends on SOC_OMAP5 135 depends on SOC_OMAP5 || SOC_DRA7XX
136 default y 136 default y
137 137
138config SOC_DRA7XX
139 bool "TI DRA7XX"
140 select ARM_ARCH_TIMER
141 select CPU_V7
142 select ARM_GIC
143 select HAVE_SMP
144 select COMMON_CLK
145
138comment "OMAP Core Type" 146comment "OMAP Core Type"
139 depends on ARCH_OMAP2 147 depends on ARCH_OMAP2
140 148
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4f671547c37..afb457c3135b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) 24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) 25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
26obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common)
26 27
27ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 28ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
28obj-y += mcbsp.o 29obj-y += mcbsp.o
@@ -39,6 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o
39obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o 40obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o
40obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o 41obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
41obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) 42obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
43obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y)
42 44
43plus_sec := $(call as-instr,.arch_extension sec,+sec) 45plus_sec := $(call as-instr,.arch_extension sec,+sec)
44AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) 46AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -61,6 +63,7 @@ obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
61obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o 63obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
62obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o 64obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o 65obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
66obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
64 67
65# Pin multiplexing 68# Pin multiplexing
66obj-$(CONFIG_SOC_OMAP2420) += mux2420.o 69obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
@@ -87,6 +90,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
87obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o 90obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
88obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o 91obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
89obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o 92obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
93obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
90obj-$(CONFIG_PM_DEBUG) += pm-debug.o 94obj-$(CONFIG_PM_DEBUG) += pm-debug.o
91 95
92obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o 96obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
@@ -114,6 +118,7 @@ omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
114 vc44xx_data.o vp44xx_data.o 118 vc44xx_data.o vp44xx_data.o
115obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) 119obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
116obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) 120obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
121obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
117 122
118# OMAP voltage domains 123# OMAP voltage domains
119voltagedomain-common := voltage.o vc.o vp.o 124voltagedomain-common := voltage.o vc.o vp.o
@@ -143,6 +148,8 @@ obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
143obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) 148obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
144obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) 149obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
145obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o 150obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
151obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
152obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
146 153
147# PRCM clockdomain control 154# PRCM clockdomain control
148clockdomain-common += clockdomain.o 155clockdomain-common += clockdomain.o
@@ -160,6 +167,8 @@ obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
160obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) 167obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
161obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) 168obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
162obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o 169obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
170obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
171obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
163 172
164# Clock framework 173# Clock framework
165obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 174obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -203,6 +212,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
203obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o 212obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
204obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 213obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
205obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o 214obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
215obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
206 216
207# EMU peripherals 217# EMU peripherals
208obj-$(CONFIG_OMAP3_EMU) += emu.o 218obj-$(CONFIG_OMAP3_EMU) += emu.o
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index be5d005ebad2..39c78387ddec 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -222,3 +222,22 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
222 .dt_compat = am43_boards_compat, 222 .dt_compat = am43_boards_compat,
223MACHINE_END 223MACHINE_END
224#endif 224#endif
225
226#ifdef CONFIG_SOC_DRA7XX
227static const char *dra7xx_boards_compat[] __initdata = {
228 "ti,dra7",
229 NULL,
230};
231
232DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
233 .reserve = omap_reserve,
234 .smp = smp_ops(omap4_smp_ops),
235 .map_io = omap5_map_io,
236 .init_early = dra7xx_init_early,
237 .init_irq = omap_gic_of_init,
238 .init_machine = omap_generic_init,
239 .init_time = omap5_realtime_timer_init,
240 .dt_compat = dra7xx_boards_compat,
241 .restart = omap44xx_restart,
242MACHINE_END
243#endif
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index daeecf1b89fa..4b03394fa0c5 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -217,6 +217,7 @@ extern void __init omap3xxx_clockdomains_init(void);
217extern void __init am33xx_clockdomains_init(void); 217extern void __init am33xx_clockdomains_init(void);
218extern void __init omap44xx_clockdomains_init(void); 218extern void __init omap44xx_clockdomains_init(void);
219extern void __init omap54xx_clockdomains_init(void); 219extern void __init omap54xx_clockdomains_init(void);
220extern void __init dra7xx_clockdomains_init(void);
220 221
221extern void clkdm_add_autodeps(struct clockdomain *clkdm); 222extern void clkdm_add_autodeps(struct clockdomain *clkdm);
222extern void clkdm_del_autodeps(struct clockdomain *clkdm); 223extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
new file mode 100644
index 000000000000..57d5df0c1fbd
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -0,0 +1,740 @@
1/*
2 * DRA7xx Clock domains framework
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Generated by code originally written by:
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/io.h>
25
26#include "clockdomain.h"
27#include "cm1_7xx.h"
28#include "cm2_7xx.h"
29
30#include "cm-regbits-7xx.h"
31#include "prm7xx.h"
32#include "prcm44xx.h"
33#include "prcm_mpu7xx.h"
34
35/* Static Dependencies for DRA7xx Clock Domains */
36
37static struct clkdm_dep cam_wkup_sleep_deps[] = {
38 { .clkdm_name = "emif_clkdm" },
39 { NULL },
40};
41
42static struct clkdm_dep dma_wkup_sleep_deps[] = {
43 { .clkdm_name = "dss_clkdm" },
44 { .clkdm_name = "emif_clkdm" },
45 { .clkdm_name = "ipu_clkdm" },
46 { .clkdm_name = "ipu1_clkdm" },
47 { .clkdm_name = "ipu2_clkdm" },
48 { .clkdm_name = "iva_clkdm" },
49 { .clkdm_name = "l3init_clkdm" },
50 { .clkdm_name = "l4cfg_clkdm" },
51 { .clkdm_name = "l4per_clkdm" },
52 { .clkdm_name = "l4per2_clkdm" },
53 { .clkdm_name = "l4per3_clkdm" },
54 { .clkdm_name = "l4sec_clkdm" },
55 { .clkdm_name = "pcie_clkdm" },
56 { .clkdm_name = "wkupaon_clkdm" },
57 { NULL },
58};
59
60static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
61 { .clkdm_name = "atl_clkdm" },
62 { .clkdm_name = "cam_clkdm" },
63 { .clkdm_name = "dsp2_clkdm" },
64 { .clkdm_name = "dss_clkdm" },
65 { .clkdm_name = "emif_clkdm" },
66 { .clkdm_name = "eve1_clkdm" },
67 { .clkdm_name = "eve2_clkdm" },
68 { .clkdm_name = "eve3_clkdm" },
69 { .clkdm_name = "eve4_clkdm" },
70 { .clkdm_name = "gmac_clkdm" },
71 { .clkdm_name = "gpu_clkdm" },
72 { .clkdm_name = "ipu_clkdm" },
73 { .clkdm_name = "ipu1_clkdm" },
74 { .clkdm_name = "ipu2_clkdm" },
75 { .clkdm_name = "iva_clkdm" },
76 { .clkdm_name = "l3init_clkdm" },
77 { .clkdm_name = "l4per_clkdm" },
78 { .clkdm_name = "l4per2_clkdm" },
79 { .clkdm_name = "l4per3_clkdm" },
80 { .clkdm_name = "l4sec_clkdm" },
81 { .clkdm_name = "pcie_clkdm" },
82 { .clkdm_name = "vpe_clkdm" },
83 { .clkdm_name = "wkupaon_clkdm" },
84 { NULL },
85};
86
87static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
88 { .clkdm_name = "atl_clkdm" },
89 { .clkdm_name = "cam_clkdm" },
90 { .clkdm_name = "dsp1_clkdm" },
91 { .clkdm_name = "dss_clkdm" },
92 { .clkdm_name = "emif_clkdm" },
93 { .clkdm_name = "eve1_clkdm" },
94 { .clkdm_name = "eve2_clkdm" },
95 { .clkdm_name = "eve3_clkdm" },
96 { .clkdm_name = "eve4_clkdm" },
97 { .clkdm_name = "gmac_clkdm" },
98 { .clkdm_name = "gpu_clkdm" },
99 { .clkdm_name = "ipu_clkdm" },
100 { .clkdm_name = "ipu1_clkdm" },
101 { .clkdm_name = "ipu2_clkdm" },
102 { .clkdm_name = "iva_clkdm" },
103 { .clkdm_name = "l3init_clkdm" },
104 { .clkdm_name = "l4per_clkdm" },
105 { .clkdm_name = "l4per2_clkdm" },
106 { .clkdm_name = "l4per3_clkdm" },
107 { .clkdm_name = "l4sec_clkdm" },
108 { .clkdm_name = "pcie_clkdm" },
109 { .clkdm_name = "vpe_clkdm" },
110 { .clkdm_name = "wkupaon_clkdm" },
111 { NULL },
112};
113
114static struct clkdm_dep dss_wkup_sleep_deps[] = {
115 { .clkdm_name = "emif_clkdm" },
116 { .clkdm_name = "iva_clkdm" },
117 { NULL },
118};
119
120static struct clkdm_dep eve1_wkup_sleep_deps[] = {
121 { .clkdm_name = "emif_clkdm" },
122 { .clkdm_name = "eve2_clkdm" },
123 { .clkdm_name = "eve3_clkdm" },
124 { .clkdm_name = "eve4_clkdm" },
125 { .clkdm_name = "iva_clkdm" },
126 { NULL },
127};
128
129static struct clkdm_dep eve2_wkup_sleep_deps[] = {
130 { .clkdm_name = "emif_clkdm" },
131 { .clkdm_name = "eve1_clkdm" },
132 { .clkdm_name = "eve3_clkdm" },
133 { .clkdm_name = "eve4_clkdm" },
134 { .clkdm_name = "iva_clkdm" },
135 { NULL },
136};
137
138static struct clkdm_dep eve3_wkup_sleep_deps[] = {
139 { .clkdm_name = "emif_clkdm" },
140 { .clkdm_name = "eve1_clkdm" },
141 { .clkdm_name = "eve2_clkdm" },
142 { .clkdm_name = "eve4_clkdm" },
143 { .clkdm_name = "iva_clkdm" },
144 { NULL },
145};
146
147static struct clkdm_dep eve4_wkup_sleep_deps[] = {
148 { .clkdm_name = "emif_clkdm" },
149 { .clkdm_name = "eve1_clkdm" },
150 { .clkdm_name = "eve2_clkdm" },
151 { .clkdm_name = "eve3_clkdm" },
152 { .clkdm_name = "iva_clkdm" },
153 { NULL },
154};
155
156static struct clkdm_dep gmac_wkup_sleep_deps[] = {
157 { .clkdm_name = "emif_clkdm" },
158 { .clkdm_name = "l4per2_clkdm" },
159 { NULL },
160};
161
162static struct clkdm_dep gpu_wkup_sleep_deps[] = {
163 { .clkdm_name = "emif_clkdm" },
164 { .clkdm_name = "iva_clkdm" },
165 { NULL },
166};
167
168static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
169 { .clkdm_name = "atl_clkdm" },
170 { .clkdm_name = "dsp1_clkdm" },
171 { .clkdm_name = "dsp2_clkdm" },
172 { .clkdm_name = "dss_clkdm" },
173 { .clkdm_name = "emif_clkdm" },
174 { .clkdm_name = "eve1_clkdm" },
175 { .clkdm_name = "eve2_clkdm" },
176 { .clkdm_name = "eve3_clkdm" },
177 { .clkdm_name = "eve4_clkdm" },
178 { .clkdm_name = "gmac_clkdm" },
179 { .clkdm_name = "gpu_clkdm" },
180 { .clkdm_name = "ipu_clkdm" },
181 { .clkdm_name = "ipu2_clkdm" },
182 { .clkdm_name = "iva_clkdm" },
183 { .clkdm_name = "l3init_clkdm" },
184 { .clkdm_name = "l3main1_clkdm" },
185 { .clkdm_name = "l4cfg_clkdm" },
186 { .clkdm_name = "l4per_clkdm" },
187 { .clkdm_name = "l4per2_clkdm" },
188 { .clkdm_name = "l4per3_clkdm" },
189 { .clkdm_name = "l4sec_clkdm" },
190 { .clkdm_name = "pcie_clkdm" },
191 { .clkdm_name = "vpe_clkdm" },
192 { .clkdm_name = "wkupaon_clkdm" },
193 { NULL },
194};
195
196static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
197 { .clkdm_name = "atl_clkdm" },
198 { .clkdm_name = "dsp1_clkdm" },
199 { .clkdm_name = "dsp2_clkdm" },
200 { .clkdm_name = "dss_clkdm" },
201 { .clkdm_name = "emif_clkdm" },
202 { .clkdm_name = "eve1_clkdm" },
203 { .clkdm_name = "eve2_clkdm" },
204 { .clkdm_name = "eve3_clkdm" },
205 { .clkdm_name = "eve4_clkdm" },
206 { .clkdm_name = "gmac_clkdm" },
207 { .clkdm_name = "gpu_clkdm" },
208 { .clkdm_name = "ipu_clkdm" },
209 { .clkdm_name = "ipu1_clkdm" },
210 { .clkdm_name = "iva_clkdm" },
211 { .clkdm_name = "l3init_clkdm" },
212 { .clkdm_name = "l3main1_clkdm" },
213 { .clkdm_name = "l4cfg_clkdm" },
214 { .clkdm_name = "l4per_clkdm" },
215 { .clkdm_name = "l4per2_clkdm" },
216 { .clkdm_name = "l4per3_clkdm" },
217 { .clkdm_name = "l4sec_clkdm" },
218 { .clkdm_name = "pcie_clkdm" },
219 { .clkdm_name = "vpe_clkdm" },
220 { .clkdm_name = "wkupaon_clkdm" },
221 { NULL },
222};
223
224static struct clkdm_dep iva_wkup_sleep_deps[] = {
225 { .clkdm_name = "emif_clkdm" },
226 { NULL },
227};
228
229static struct clkdm_dep l3init_wkup_sleep_deps[] = {
230 { .clkdm_name = "emif_clkdm" },
231 { .clkdm_name = "iva_clkdm" },
232 { .clkdm_name = "l4cfg_clkdm" },
233 { .clkdm_name = "l4per_clkdm" },
234 { .clkdm_name = "l4per3_clkdm" },
235 { .clkdm_name = "l4sec_clkdm" },
236 { .clkdm_name = "wkupaon_clkdm" },
237 { NULL },
238};
239
240static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
241 { .clkdm_name = "dsp1_clkdm" },
242 { .clkdm_name = "dsp2_clkdm" },
243 { .clkdm_name = "ipu1_clkdm" },
244 { .clkdm_name = "ipu2_clkdm" },
245 { NULL },
246};
247
248static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
249 { .clkdm_name = "emif_clkdm" },
250 { .clkdm_name = "l4per_clkdm" },
251 { NULL },
252};
253
254static struct clkdm_dep mpu_wkup_sleep_deps[] = {
255 { .clkdm_name = "cam_clkdm" },
256 { .clkdm_name = "dsp1_clkdm" },
257 { .clkdm_name = "dsp2_clkdm" },
258 { .clkdm_name = "dss_clkdm" },
259 { .clkdm_name = "emif_clkdm" },
260 { .clkdm_name = "eve1_clkdm" },
261 { .clkdm_name = "eve2_clkdm" },
262 { .clkdm_name = "eve3_clkdm" },
263 { .clkdm_name = "eve4_clkdm" },
264 { .clkdm_name = "gmac_clkdm" },
265 { .clkdm_name = "gpu_clkdm" },
266 { .clkdm_name = "ipu_clkdm" },
267 { .clkdm_name = "ipu1_clkdm" },
268 { .clkdm_name = "ipu2_clkdm" },
269 { .clkdm_name = "iva_clkdm" },
270 { .clkdm_name = "l3init_clkdm" },
271 { .clkdm_name = "l3main1_clkdm" },
272 { .clkdm_name = "l4cfg_clkdm" },
273 { .clkdm_name = "l4per_clkdm" },
274 { .clkdm_name = "l4per2_clkdm" },
275 { .clkdm_name = "l4per3_clkdm" },
276 { .clkdm_name = "l4sec_clkdm" },
277 { .clkdm_name = "pcie_clkdm" },
278 { .clkdm_name = "vpe_clkdm" },
279 { .clkdm_name = "wkupaon_clkdm" },
280 { NULL },
281};
282
283static struct clkdm_dep pcie_wkup_sleep_deps[] = {
284 { .clkdm_name = "atl_clkdm" },
285 { .clkdm_name = "cam_clkdm" },
286 { .clkdm_name = "dsp1_clkdm" },
287 { .clkdm_name = "dsp2_clkdm" },
288 { .clkdm_name = "dss_clkdm" },
289 { .clkdm_name = "emif_clkdm" },
290 { .clkdm_name = "eve1_clkdm" },
291 { .clkdm_name = "eve2_clkdm" },
292 { .clkdm_name = "eve3_clkdm" },
293 { .clkdm_name = "eve4_clkdm" },
294 { .clkdm_name = "gmac_clkdm" },
295 { .clkdm_name = "gpu_clkdm" },
296 { .clkdm_name = "ipu_clkdm" },
297 { .clkdm_name = "ipu1_clkdm" },
298 { .clkdm_name = "iva_clkdm" },
299 { .clkdm_name = "l3init_clkdm" },
300 { .clkdm_name = "l4cfg_clkdm" },
301 { .clkdm_name = "l4per_clkdm" },
302 { .clkdm_name = "l4per2_clkdm" },
303 { .clkdm_name = "l4per3_clkdm" },
304 { .clkdm_name = "l4sec_clkdm" },
305 { .clkdm_name = "vpe_clkdm" },
306 { NULL },
307};
308
309static struct clkdm_dep vpe_wkup_sleep_deps[] = {
310 { .clkdm_name = "emif_clkdm" },
311 { .clkdm_name = "l4per3_clkdm" },
312 { NULL },
313};
314
315static struct clockdomain l4per3_7xx_clkdm = {
316 .name = "l4per3_clkdm",
317 .pwrdm = { .name = "l4per_pwrdm" },
318 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
319 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
320 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
321 .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
322 .flags = CLKDM_CAN_HWSUP_SWSUP,
323};
324
325static struct clockdomain l4per2_7xx_clkdm = {
326 .name = "l4per2_clkdm",
327 .pwrdm = { .name = "l4per_pwrdm" },
328 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
329 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
330 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
331 .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
332 .wkdep_srcs = l4per2_wkup_sleep_deps,
333 .sleepdep_srcs = l4per2_wkup_sleep_deps,
334 .flags = CLKDM_CAN_HWSUP_SWSUP,
335};
336
337static struct clockdomain mpu0_7xx_clkdm = {
338 .name = "mpu0_clkdm",
339 .pwrdm = { .name = "cpu0_pwrdm" },
340 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
341 .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
342 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
343 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
344};
345
346static struct clockdomain iva_7xx_clkdm = {
347 .name = "iva_clkdm",
348 .pwrdm = { .name = "iva_pwrdm" },
349 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
350 .cm_inst = DRA7XX_CM_CORE_IVA_INST,
351 .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
352 .dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
353 .wkdep_srcs = iva_wkup_sleep_deps,
354 .sleepdep_srcs = iva_wkup_sleep_deps,
355 .flags = CLKDM_CAN_HWSUP_SWSUP,
356};
357
358static struct clockdomain coreaon_7xx_clkdm = {
359 .name = "coreaon_clkdm",
360 .pwrdm = { .name = "coreaon_pwrdm" },
361 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
362 .cm_inst = DRA7XX_CM_CORE_COREAON_INST,
363 .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
364 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
365};
366
367static struct clockdomain ipu1_7xx_clkdm = {
368 .name = "ipu1_clkdm",
369 .pwrdm = { .name = "ipu_pwrdm" },
370 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
371 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
372 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
373 .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
374 .wkdep_srcs = ipu1_wkup_sleep_deps,
375 .sleepdep_srcs = ipu1_wkup_sleep_deps,
376 .flags = CLKDM_CAN_HWSUP_SWSUP,
377};
378
379static struct clockdomain ipu2_7xx_clkdm = {
380 .name = "ipu2_clkdm",
381 .pwrdm = { .name = "core_pwrdm" },
382 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
383 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
384 .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
385 .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
386 .wkdep_srcs = ipu2_wkup_sleep_deps,
387 .sleepdep_srcs = ipu2_wkup_sleep_deps,
388 .flags = CLKDM_CAN_HWSUP_SWSUP,
389};
390
391static struct clockdomain l3init_7xx_clkdm = {
392 .name = "l3init_clkdm",
393 .pwrdm = { .name = "l3init_pwrdm" },
394 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
395 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
396 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
397 .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
398 .wkdep_srcs = l3init_wkup_sleep_deps,
399 .sleepdep_srcs = l3init_wkup_sleep_deps,
400 .flags = CLKDM_CAN_HWSUP_SWSUP,
401};
402
403static struct clockdomain l4sec_7xx_clkdm = {
404 .name = "l4sec_clkdm",
405 .pwrdm = { .name = "l4per_pwrdm" },
406 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
407 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
408 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
409 .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
410 .wkdep_srcs = l4sec_wkup_sleep_deps,
411 .sleepdep_srcs = l4sec_wkup_sleep_deps,
412 .flags = CLKDM_CAN_HWSUP_SWSUP,
413};
414
415static struct clockdomain l3main1_7xx_clkdm = {
416 .name = "l3main1_clkdm",
417 .pwrdm = { .name = "core_pwrdm" },
418 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
419 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
420 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
421 .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
422 .flags = CLKDM_CAN_HWSUP,
423};
424
425static struct clockdomain vpe_7xx_clkdm = {
426 .name = "vpe_clkdm",
427 .pwrdm = { .name = "vpe_pwrdm" },
428 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
429 .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
430 .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
431 .dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
432 .wkdep_srcs = vpe_wkup_sleep_deps,
433 .sleepdep_srcs = vpe_wkup_sleep_deps,
434 .flags = CLKDM_CAN_HWSUP_SWSUP,
435};
436
437static struct clockdomain mpu_7xx_clkdm = {
438 .name = "mpu_clkdm",
439 .pwrdm = { .name = "mpu_pwrdm" },
440 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
441 .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
442 .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
443 .wkdep_srcs = mpu_wkup_sleep_deps,
444 .sleepdep_srcs = mpu_wkup_sleep_deps,
445 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
446};
447
448static struct clockdomain custefuse_7xx_clkdm = {
449 .name = "custefuse_clkdm",
450 .pwrdm = { .name = "custefuse_pwrdm" },
451 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
452 .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
453 .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
454 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
455};
456
457static struct clockdomain ipu_7xx_clkdm = {
458 .name = "ipu_clkdm",
459 .pwrdm = { .name = "ipu_pwrdm" },
460 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
461 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
462 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
463 .dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
464 .flags = CLKDM_CAN_HWSUP_SWSUP,
465};
466
467static struct clockdomain mpu1_7xx_clkdm = {
468 .name = "mpu1_clkdm",
469 .pwrdm = { .name = "cpu1_pwrdm" },
470 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
471 .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
472 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
473 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
474};
475
476static struct clockdomain gmac_7xx_clkdm = {
477 .name = "gmac_clkdm",
478 .pwrdm = { .name = "l3init_pwrdm" },
479 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
480 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
481 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
482 .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
483 .wkdep_srcs = gmac_wkup_sleep_deps,
484 .sleepdep_srcs = gmac_wkup_sleep_deps,
485 .flags = CLKDM_CAN_HWSUP_SWSUP,
486};
487
488static struct clockdomain l4cfg_7xx_clkdm = {
489 .name = "l4cfg_clkdm",
490 .pwrdm = { .name = "core_pwrdm" },
491 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
492 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
493 .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
494 .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
495 .flags = CLKDM_CAN_HWSUP,
496};
497
498static struct clockdomain dma_7xx_clkdm = {
499 .name = "dma_clkdm",
500 .pwrdm = { .name = "core_pwrdm" },
501 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
502 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
503 .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
504 .wkdep_srcs = dma_wkup_sleep_deps,
505 .sleepdep_srcs = dma_wkup_sleep_deps,
506 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
507};
508
509static struct clockdomain rtc_7xx_clkdm = {
510 .name = "rtc_clkdm",
511 .pwrdm = { .name = "rtc_pwrdm" },
512 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
513 .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
514 .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
515 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
516};
517
518static struct clockdomain pcie_7xx_clkdm = {
519 .name = "pcie_clkdm",
520 .pwrdm = { .name = "l3init_pwrdm" },
521 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
522 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
523 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
524 .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
525 .wkdep_srcs = pcie_wkup_sleep_deps,
526 .sleepdep_srcs = pcie_wkup_sleep_deps,
527 .flags = CLKDM_CAN_HWSUP_SWSUP,
528};
529
530static struct clockdomain atl_7xx_clkdm = {
531 .name = "atl_clkdm",
532 .pwrdm = { .name = "core_pwrdm" },
533 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
534 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
535 .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
536 .dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
537 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
538};
539
540static struct clockdomain l3instr_7xx_clkdm = {
541 .name = "l3instr_clkdm",
542 .pwrdm = { .name = "core_pwrdm" },
543 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
544 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
545 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
546};
547
548static struct clockdomain dss_7xx_clkdm = {
549 .name = "dss_clkdm",
550 .pwrdm = { .name = "dss_pwrdm" },
551 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
552 .cm_inst = DRA7XX_CM_CORE_DSS_INST,
553 .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
554 .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
555 .wkdep_srcs = dss_wkup_sleep_deps,
556 .sleepdep_srcs = dss_wkup_sleep_deps,
557 .flags = CLKDM_CAN_HWSUP_SWSUP,
558};
559
560static struct clockdomain emif_7xx_clkdm = {
561 .name = "emif_clkdm",
562 .pwrdm = { .name = "core_pwrdm" },
563 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
564 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
565 .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
566 .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
567 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
568};
569
570static struct clockdomain emu_7xx_clkdm = {
571 .name = "emu_clkdm",
572 .pwrdm = { .name = "emu_pwrdm" },
573 .prcm_partition = DRA7XX_PRM_PARTITION,
574 .cm_inst = DRA7XX_PRM_EMU_CM_INST,
575 .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
576 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
577};
578
579static struct clockdomain dsp2_7xx_clkdm = {
580 .name = "dsp2_clkdm",
581 .pwrdm = { .name = "dsp2_pwrdm" },
582 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
583 .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
584 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
585 .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
586 .wkdep_srcs = dsp2_wkup_sleep_deps,
587 .sleepdep_srcs = dsp2_wkup_sleep_deps,
588 .flags = CLKDM_CAN_HWSUP_SWSUP,
589};
590
591static struct clockdomain dsp1_7xx_clkdm = {
592 .name = "dsp1_clkdm",
593 .pwrdm = { .name = "dsp1_pwrdm" },
594 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
595 .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
596 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
597 .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
598 .wkdep_srcs = dsp1_wkup_sleep_deps,
599 .sleepdep_srcs = dsp1_wkup_sleep_deps,
600 .flags = CLKDM_CAN_HWSUP_SWSUP,
601};
602
603static struct clockdomain cam_7xx_clkdm = {
604 .name = "cam_clkdm",
605 .pwrdm = { .name = "cam_pwrdm" },
606 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
607 .cm_inst = DRA7XX_CM_CORE_CAM_INST,
608 .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
609 .dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
610 .wkdep_srcs = cam_wkup_sleep_deps,
611 .sleepdep_srcs = cam_wkup_sleep_deps,
612 .flags = CLKDM_CAN_HWSUP_SWSUP,
613};
614
615static struct clockdomain l4per_7xx_clkdm = {
616 .name = "l4per_clkdm",
617 .pwrdm = { .name = "l4per_pwrdm" },
618 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
619 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
620 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
621 .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
622 .flags = CLKDM_CAN_HWSUP_SWSUP,
623};
624
625static struct clockdomain gpu_7xx_clkdm = {
626 .name = "gpu_clkdm",
627 .pwrdm = { .name = "gpu_pwrdm" },
628 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
629 .cm_inst = DRA7XX_CM_CORE_GPU_INST,
630 .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
631 .dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
632 .wkdep_srcs = gpu_wkup_sleep_deps,
633 .sleepdep_srcs = gpu_wkup_sleep_deps,
634 .flags = CLKDM_CAN_HWSUP_SWSUP,
635};
636
637static struct clockdomain eve4_7xx_clkdm = {
638 .name = "eve4_clkdm",
639 .pwrdm = { .name = "eve4_pwrdm" },
640 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
641 .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
642 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
643 .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
644 .wkdep_srcs = eve4_wkup_sleep_deps,
645 .sleepdep_srcs = eve4_wkup_sleep_deps,
646 .flags = CLKDM_CAN_HWSUP_SWSUP,
647};
648
649static struct clockdomain eve2_7xx_clkdm = {
650 .name = "eve2_clkdm",
651 .pwrdm = { .name = "eve2_pwrdm" },
652 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
653 .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
654 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
655 .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
656 .wkdep_srcs = eve2_wkup_sleep_deps,
657 .sleepdep_srcs = eve2_wkup_sleep_deps,
658 .flags = CLKDM_CAN_HWSUP_SWSUP,
659};
660
661static struct clockdomain eve3_7xx_clkdm = {
662 .name = "eve3_clkdm",
663 .pwrdm = { .name = "eve3_pwrdm" },
664 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
665 .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
666 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
667 .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
668 .wkdep_srcs = eve3_wkup_sleep_deps,
669 .sleepdep_srcs = eve3_wkup_sleep_deps,
670 .flags = CLKDM_CAN_HWSUP_SWSUP,
671};
672
673static struct clockdomain wkupaon_7xx_clkdm = {
674 .name = "wkupaon_clkdm",
675 .pwrdm = { .name = "wkupaon_pwrdm" },
676 .prcm_partition = DRA7XX_PRM_PARTITION,
677 .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
678 .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
679 .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
680 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
681};
682
683static struct clockdomain eve1_7xx_clkdm = {
684 .name = "eve1_clkdm",
685 .pwrdm = { .name = "eve1_pwrdm" },
686 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
687 .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
688 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
689 .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
690 .wkdep_srcs = eve1_wkup_sleep_deps,
691 .sleepdep_srcs = eve1_wkup_sleep_deps,
692 .flags = CLKDM_CAN_HWSUP_SWSUP,
693};
694
695/* As clockdomains are added or removed above, this list must also be changed */
696static struct clockdomain *clockdomains_dra7xx[] __initdata = {
697 &l4per3_7xx_clkdm,
698 &l4per2_7xx_clkdm,
699 &mpu0_7xx_clkdm,
700 &iva_7xx_clkdm,
701 &coreaon_7xx_clkdm,
702 &ipu1_7xx_clkdm,
703 &ipu2_7xx_clkdm,
704 &l3init_7xx_clkdm,
705 &l4sec_7xx_clkdm,
706 &l3main1_7xx_clkdm,
707 &vpe_7xx_clkdm,
708 &mpu_7xx_clkdm,
709 &custefuse_7xx_clkdm,
710 &ipu_7xx_clkdm,
711 &mpu1_7xx_clkdm,
712 &gmac_7xx_clkdm,
713 &l4cfg_7xx_clkdm,
714 &dma_7xx_clkdm,
715 &rtc_7xx_clkdm,
716 &pcie_7xx_clkdm,
717 &atl_7xx_clkdm,
718 &l3instr_7xx_clkdm,
719 &dss_7xx_clkdm,
720 &emif_7xx_clkdm,
721 &emu_7xx_clkdm,
722 &dsp2_7xx_clkdm,
723 &dsp1_7xx_clkdm,
724 &cam_7xx_clkdm,
725 &l4per_7xx_clkdm,
726 &gpu_7xx_clkdm,
727 &eve4_7xx_clkdm,
728 &eve2_7xx_clkdm,
729 &eve3_7xx_clkdm,
730 &wkupaon_7xx_clkdm,
731 &eve1_7xx_clkdm,
732 NULL
733};
734
735void __init dra7xx_clockdomains_init(void)
736{
737 clkdm_register_platform_funcs(&omap4_clkdm_operations);
738 clkdm_register_clkdms(clockdomains_dra7xx);
739 clkdm_complete_init();
740}
diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h
new file mode 100644
index 000000000000..ad8f81ce9b16
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-7xx.h
@@ -0,0 +1,51 @@
1/*
2 * DRA7xx Clock Management register bits
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
24
25#define DRA7XX_ATL_STATDEP_SHIFT 30
26#define DRA7XX_CAM_STATDEP_SHIFT 9
27#define DRA7XX_DSP1_STATDEP_SHIFT 1
28#define DRA7XX_DSP2_STATDEP_SHIFT 18
29#define DRA7XX_DSS_STATDEP_SHIFT 8
30#define DRA7XX_EMIF_STATDEP_SHIFT 4
31#define DRA7XX_EVE1_STATDEP_SHIFT 19
32#define DRA7XX_EVE2_STATDEP_SHIFT 20
33#define DRA7XX_EVE3_STATDEP_SHIFT 21
34#define DRA7XX_EVE4_STATDEP_SHIFT 22
35#define DRA7XX_GMAC_STATDEP_SHIFT 25
36#define DRA7XX_GPU_STATDEP_SHIFT 10
37#define DRA7XX_IPU1_STATDEP_SHIFT 23
38#define DRA7XX_IPU2_STATDEP_SHIFT 0
39#define DRA7XX_IPU_STATDEP_SHIFT 24
40#define DRA7XX_IVA_STATDEP_SHIFT 2
41#define DRA7XX_L3INIT_STATDEP_SHIFT 7
42#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5
43#define DRA7XX_L4CFG_STATDEP_SHIFT 12
44#define DRA7XX_L4PER2_STATDEP_SHIFT 26
45#define DRA7XX_L4PER3_STATDEP_SHIFT 27
46#define DRA7XX_L4PER_STATDEP_SHIFT 13
47#define DRA7XX_L4SEC_STATDEP_SHIFT 14
48#define DRA7XX_PCIE_STATDEP_SHIFT 29
49#define DRA7XX_VPE_STATDEP_SHIFT 28
50#define DRA7XX_WKUPAON_STATDEP_SHIFT 15
51#endif
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
new file mode 100644
index 000000000000..ca6fa1febaac
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -0,0 +1,324 @@
1/*
2 * DRA7xx CM1 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
24#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
25
26#include "cm_44xx_54xx.h"
27
28/* CM1 base address */
29#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
30
31#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
33
34/* CM_CORE_AON instances */
35#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
36#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
37#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
38#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
39#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
40#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
41#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
42#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
43#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
44#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
45#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
46#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
47#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
48#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
49
50/* CM_CORE_AON clockdomain register offsets (from instance start) */
51#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
52#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
53#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
54#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
55#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
56#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
57#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
58#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
59#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
60#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
61#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
62
63/* CM_CORE_AON */
64
65/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
66#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
67#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
68#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
69#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
70#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
71#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
72#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
73#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
74
75/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
76#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
77#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
78#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
79#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
80#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
81#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
82#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
83#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
84#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
85#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
86#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
87#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
88#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
89#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
90#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
91#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
92#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
93#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
94#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
95#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
96#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
97#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
98#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
99#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
100#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
101#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
102#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
103#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
104#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
105#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
106#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
107#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
108#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
109#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
110#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
111#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
112#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
113#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
114#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
115#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
116#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
117#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
118#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
119#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
120#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
121#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
122#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
123#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
124#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
125#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
126#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
127#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
128#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
129#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
130#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
131#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
132#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
133#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
134#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
135#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
136#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
137#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
138#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
139#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
140#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
141#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
142#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
143#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
144#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
145#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
146#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
147#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
148#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
149#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
150#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
151#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
152#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
153#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
154#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
155#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
156#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
157#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
158#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
159#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
160#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
161#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
162#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
163#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
164#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
165#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
166#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
167#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
168#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
169#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
170#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
171#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
172#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
173#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
174#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
175#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
176#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
177#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
178#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
179#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
180#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
181#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
182#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
183#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
184#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
185#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
186#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
187#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
188#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
189#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
190#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
191#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
192#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
193#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
194#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
195#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
196#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
197#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
198#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
199#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
200#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
201#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
202#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
203#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
204#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
205#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
206#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
207#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
208#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
209#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
210#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
211#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
212#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
213#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
214#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
215#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
216#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
217#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
218#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
219#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
220#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
221#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
222#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
223#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
224#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
225#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
226#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
227#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
228#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
229#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
230#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
231#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
232#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
233#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
234#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
235#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
236#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
237#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
238#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
239#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
240#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
241#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
242#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
243
244/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
245#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
246#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
247#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
248#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
249#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
250#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
251#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
252
253/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
254#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
255#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
256#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
257#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
258#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
259
260/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
261#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
262#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
263#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
264#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
265#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
266#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
267#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
268#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
269#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
270#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
271#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
272#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
273#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
274#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
275#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
276#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
277#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
278#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
279#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
280#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
281
282/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
283#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
284#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
285#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
286#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
287#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
288
289/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
290#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
291#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
292#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
293#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
294
295/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
296#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
297#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
298#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
299#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
300
301/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
302#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
303#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
304#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
305#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
306
307/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
308#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
309#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
310#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
311#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
312
313/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
314#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
315#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
316#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
317
318/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
319#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
320#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
321#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
322#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008
323
324#endif
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
new file mode 100644
index 000000000000..9ad7594e7622
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -0,0 +1,513 @@
1/*
2 * DRA7xx CM2 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
24
25#include "cm_44xx_54xx.h"
26
27/* CM2 base address */
28#define DRA7XX_CM_CORE_BASE 0x4a008000
29
30#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
32
33/* CM_CORE instances */
34#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
35#define DRA7XX_CM_CORE_CKGEN_INST 0x0104
36#define DRA7XX_CM_CORE_COREAON_INST 0x0600
37#define DRA7XX_CM_CORE_CORE_INST 0x0700
38#define DRA7XX_CM_CORE_IVA_INST 0x0f00
39#define DRA7XX_CM_CORE_CAM_INST 0x1000
40#define DRA7XX_CM_CORE_DSS_INST 0x1100
41#define DRA7XX_CM_CORE_GPU_INST 0x1200
42#define DRA7XX_CM_CORE_L3INIT_INST 0x1300
43#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600
44#define DRA7XX_CM_CORE_L4PER_INST 0x1700
45#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18
46
47/* CM_CORE clockdomain register offsets (from instance start) */
48#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
49#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
50#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200
51#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
52#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
53#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520
54#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
55#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
56#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
57#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
58#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
59#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
60#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
61#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0
62#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0
63#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
64#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
65#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180
66#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc
67#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210
68
69/* CM_CORE */
70
71/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
72#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
73#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
74#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
75#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0
76
77/* CM_CORE.CKGEN_CM_CORE register offsets */
78#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
79#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
80#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c
81#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
82#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040
83#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
84#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044
85#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
86#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048
87#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
88#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c
89#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
90#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050
91#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
92#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054
93#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
94#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058
95#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
96#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c
97#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
98#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060
99#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
100#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064
101#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068
102#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c
103#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
104#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080
105#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
106#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084
107#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
108#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088
109#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
110#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c
111#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
112#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4
113#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8
114#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0
115#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
116#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc
117#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
118#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100
119#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
120#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104
121#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
122#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108
123#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
124#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c
125#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
126#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110
127#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114
128#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118
129#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
130#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c
131#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
132#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120
133#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
134#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124
135#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
136
137/* CM_CORE.COREAON_CM_CORE register offsets */
138#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
139#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
140#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
141#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
142#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
143#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040
144#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
145#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
146#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
147#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058
148#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
149#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068
150#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
151#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078
152#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
153#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088
154#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
155#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098
156#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
157#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0
158#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
159#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0
160#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
161#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0
162#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
163#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0
164#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
165
166/* CM_CORE.CORE_CM_CORE register offsets */
167#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
168#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
169#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
170#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
171#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028
172#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
173#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030
174#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
175#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050
176#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
177#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058
178#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
179#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060
180#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
181#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068
182#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
183#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070
184#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
185#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078
186#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
187#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080
188#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
189#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088
190#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
191#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090
192#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
193#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098
194#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
195#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0
196#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
197#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8
198#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
199#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0
200#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
201#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8
202#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
203#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0
204#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
205#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8
206#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
207#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0
208#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
209#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8
210#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
211#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0
212#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
213#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8
214#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
215#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200
216#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204
217#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208
218#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220
219#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
220#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
221#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304
222#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
223#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
224#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
225#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
226#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
227#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
228#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
229#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
230#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
231#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
232#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
233#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
234#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
235#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
236#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500
237#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
238#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520
239#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
240#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
241#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
242#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
243#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
244#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
245#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630
246#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
247#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
248#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
249#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
250#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
251#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648
252#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
253#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650
254#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
255#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658
256#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
257#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660
258#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
259#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668
260#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
261#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670
262#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
263#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678
264#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
265#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680
266#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
267#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688
268#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
269#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690
270#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
271#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698
272#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
273#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0
274#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
275#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8
276#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
277#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0
278#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
279#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8
280#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
281#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0
282#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
283#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
284#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720
285#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
286#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
287#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
288#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
289#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
290#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
291#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
292#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
293#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
294
295/* CM_CORE.IVA_CM_CORE register offsets */
296#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
297#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004
298#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
299#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
300#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
301#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
302#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
303
304/* CM_CORE.CAM_CM_CORE register offsets */
305#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
306#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004
307#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020
308#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
309#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028
310#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
311#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030
312#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
313#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038
314#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
315#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040
316#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
317#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048
318#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
319
320/* CM_CORE.DSS_CM_CORE register offsets */
321#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
322#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004
323#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
324#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
325#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
326#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
327#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
328#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c
329#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
330
331/* CM_CORE.GPU_CM_CORE register offsets */
332#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
333#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004
334#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
335#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
336#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
337
338/* CM_CORE.L3INIT_CM_CORE register offsets */
339#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
340#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
341#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
342#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
343#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
344#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
345#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
346#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040
347#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
348#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048
349#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
350#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050
351#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
352#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058
353#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
354#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
355#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
356#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
360#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
361#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
362#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
363#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0
364#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
365#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
366#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
367#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
368#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
369#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0
370#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
371
372/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
373#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
374#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
375#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
376
377/* CM_CORE.L4PER_CM_CORE register offsets */
378#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
379#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
380#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c
381#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
382#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014
383#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
384#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018
385#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
386#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020
387#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
388#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028
389#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
390#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030
391#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
392#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038
393#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
394#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040
395#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
396#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048
397#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
398#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050
399#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
400#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
401#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
402#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
403#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
404#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
405#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
406#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
407#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
408#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
409#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
410#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
411#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
412#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
413#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
414#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090
415#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
416#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098
417#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
418#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
419#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
420#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
421#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
422#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
423#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
424#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
425#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
426#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0
427#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
428#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4
429#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
430#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8
431#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
432#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0
433#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
434#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8
435#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
436#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
437#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
438#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
439#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
440#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
441#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
442#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
443#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
444#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110
445#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
446#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118
447#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
448#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120
449#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
450#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128
451#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
452#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130
453#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
454#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138
455#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
456#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
457#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
458#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
459#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
460#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
461#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
462#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
463#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
464#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160
465#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
466#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168
467#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
468#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170
469#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
470#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178
471#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
472#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
473#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184
474#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
475#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190
476#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
477#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198
478#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
479#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
480#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
481#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
482#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
483#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
484#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
485#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8
486#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
487#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
488#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
489#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
490#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
491#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0
492#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
493#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8
494#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
495#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0
496#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
497#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8
498#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
499#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0
500#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
501#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8
502#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
503#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc
504#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200
505#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204
506#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
507#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208
508#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
509#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c
510#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210
511#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214
512
513#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index dfcc182ecff9..4a5684b96492 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -110,6 +110,7 @@ void omap3630_init_late(void);
110void am35xx_init_late(void); 110void am35xx_init_late(void);
111void ti81xx_init_late(void); 111void ti81xx_init_late(void);
112int omap2_common_pm_late_init(void); 112int omap2_common_pm_late_init(void);
113void dra7xx_init_early(void);
113 114
114#ifdef CONFIG_SOC_BUS 115#ifdef CONFIG_SOC_BUS
115void omap_soc_device_init(void); 116void omap_soc_device_init(void);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2dc62a25f2c3..0289adcb6efb 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -61,7 +61,7 @@ int omap_type(void)
61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
62 } else if (cpu_is_omap44xx()) { 62 } else if (cpu_is_omap44xx()) {
63 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 63 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
64 } else if (soc_is_omap54xx()) { 64 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
65 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); 65 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
66 val &= OMAP5_DEVICETYPE_MASK; 66 val &= OMAP5_DEVICETYPE_MASK;
67 val >>= 6; 67 val >>= 6;
@@ -116,7 +116,7 @@ static u16 tap_prod_id;
116 116
117void omap_get_die_id(struct omap_die_id *odi) 117void omap_get_die_id(struct omap_die_id *odi)
118{ 118{
119 if (cpu_is_omap44xx() || soc_is_omap54xx()) { 119 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
120 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 120 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
121 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 121 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
122 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 122 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4a3f06f02859..ff2113ce4014 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -251,7 +251,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
251}; 251};
252#endif 252#endif
253 253
254#ifdef CONFIG_SOC_OMAP5 254#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
255static struct map_desc omap54xx_io_desc[] __initdata = { 255static struct map_desc omap54xx_io_desc[] __initdata = {
256 { 256 {
257 .virtual = L3_54XX_VIRT, 257 .virtual = L3_54XX_VIRT,
@@ -333,7 +333,7 @@ void __init omap4_map_io(void)
333} 333}
334#endif 334#endif
335 335
336#ifdef CONFIG_SOC_OMAP5 336#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
337void __init omap5_map_io(void) 337void __init omap5_map_io(void)
338{ 338{
339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
@@ -653,6 +653,27 @@ void __init omap5_init_early(void)
653} 653}
654#endif 654#endif
655 655
656#ifdef CONFIG_SOC_DRA7XX
657void __init dra7xx_init_early(void)
658{
659 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
660 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
661 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
662 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
663 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
664 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
665 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
666 omap_prm_base_init();
667 omap_cm_base_init();
668 omap44xx_prm_init();
669 dra7xx_powerdomains_init();
670 dra7xx_clockdomains_init();
671 dra7xx_hwmod_init();
672 omap_hwmod_init_postsetup();
673}
674#endif
675
676
656void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 677void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
657 struct omap_sdrc_params *sdrc_cs1) 678 struct omap_sdrc_params *sdrc_cs1)
658{ 679{
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index a086ba15868b..2d35c5709408 100644
--- a/arch/arm/mach-omap2/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -30,4 +30,8 @@
30#define OMAP54XX_CTRL_BASE 0x4a002800 30#define OMAP54XX_CTRL_BASE 0x4a002800
31#define OMAP54XX_SAR_RAM_BASE 0x4ae26000 31#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
32 32
33#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
34#define DRA7XX_CTRL_BASE 0x4a003400
35#define DRA7XX_TAP_BASE 0x4ae0c000
36
33#endif /* __ASM_SOC_OMAP555554XX_H */ 37#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 03e9e2f5d9a7..d9ee0ff094d4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -4115,7 +4115,7 @@ void __init omap_hwmod_init(void)
4115 soc_ops.assert_hardreset = _omap2_assert_hardreset; 4115 soc_ops.assert_hardreset = _omap2_assert_hardreset;
4116 soc_ops.deassert_hardreset = _omap2_deassert_hardreset; 4116 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
4117 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; 4117 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
4118 } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { 4118 } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
4119 soc_ops.enable_module = _omap4_enable_module; 4119 soc_ops.enable_module = _omap4_enable_module;
4120 soc_ops.disable_module = _omap4_disable_module; 4120 soc_ops.disable_module = _omap4_disable_module;
4121 soc_ops.wait_target_ready = _omap4_wait_target_ready; 4121 soc_ops.wait_target_ready = _omap4_wait_target_ready;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index e1482a9b3bc2..d02acf9308d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -751,6 +751,7 @@ extern int omap3xxx_hwmod_init(void);
751extern int omap44xx_hwmod_init(void); 751extern int omap44xx_hwmod_init(void);
752extern int omap54xx_hwmod_init(void); 752extern int omap54xx_hwmod_init(void);
753extern int am33xx_hwmod_init(void); 753extern int am33xx_hwmod_init(void);
754extern int dra7xx_hwmod_init(void);
754 755
755extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 756extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
756 757
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
new file mode 100644
index 000000000000..db32d5380b11
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -0,0 +1,2724 @@
1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_7xx.h"
33#include "cm2_7xx.h"
34#include "prm7xx.h"
35#include "i2c.h"
36#include "mmc.h"
37#include "wd_timer.h"
38
39/* Base offset for all DRA7XX interrupts external to MPUSS */
40#define DRA7XX_IRQ_GIC_START 32
41
42/* Base offset for all DRA7XX dma requests */
43#define DRA7XX_DMA_REQ_START 1
44
45
46/*
47 * IP blocks
48 */
49
50/*
51 * 'l3' class
52 * instance(s): l3_instr, l3_main_1, l3_main_2
53 */
54static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
55 .name = "l3",
56};
57
58/* l3_instr */
59static struct omap_hwmod dra7xx_l3_instr_hwmod = {
60 .name = "l3_instr",
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
68 },
69 },
70};
71
72/* l3_main_1 */
73static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
74 .name = "l3_main_1",
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
77 .prcm = {
78 .omap4 = {
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
81 },
82 },
83};
84
85/* l3_main_2 */
86static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
87 .name = "l3_main_2",
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
90 .prcm = {
91 .omap4 = {
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
95 },
96 },
97};
98
99/*
100 * 'l4' class
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
102 */
103static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
104 .name = "l4",
105};
106
107/* l4_cfg */
108static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
109 .name = "l4_cfg",
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l4_per1 */
121static struct omap_hwmod dra7xx_l4_per1_hwmod = {
122 .name = "l4_per1",
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
129 },
130 },
131};
132
133/* l4_per2 */
134static struct omap_hwmod dra7xx_l4_per2_hwmod = {
135 .name = "l4_per2",
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
138 .prcm = {
139 .omap4 = {
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
142 },
143 },
144};
145
146/* l4_per3 */
147static struct omap_hwmod dra7xx_l4_per3_hwmod = {
148 .name = "l4_per3",
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 },
156 },
157};
158
159/* l4_wkup */
160static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
161 .name = "l4_wkup",
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
164 .prcm = {
165 .omap4 = {
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
168 },
169 },
170};
171
172/*
173 * 'atl' class
174 *
175 */
176
177static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
178 .name = "atl",
179};
180
181/* atl */
182static struct omap_hwmod dra7xx_atl_hwmod = {
183 .name = "atl",
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
192 },
193 },
194};
195
196/*
197 * 'bb2d' class
198 *
199 */
200
201static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
202 .name = "bb2d",
203};
204
205/* bb2d */
206static struct omap_hwmod dra7xx_bb2d_hwmod = {
207 .name = "bb2d",
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
211 .prcm = {
212 .omap4 = {
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
216 },
217 },
218};
219
220/*
221 * 'counter' class
222 *
223 */
224
225static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
226 .rev_offs = 0x0000,
227 .sysc_offs = 0x0010,
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
230 SIDLE_SMART_WKUP),
231 .sysc_fields = &omap_hwmod_sysc_type1,
232};
233
234static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
235 .name = "counter",
236 .sysc = &dra7xx_counter_sysc,
237};
238
239/* counter_32k */
240static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
246 .prcm = {
247 .omap4 = {
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
250 },
251 },
252};
253
254/*
255 * 'ctrl_module' class
256 *
257 */
258
259static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
261};
262
263/* ctrl_module_wkup */
264static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
268 .prcm = {
269 .omap4 = {
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
271 },
272 },
273};
274
275/*
276 * 'dcan' class
277 *
278 */
279
280static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
281 .name = "dcan",
282};
283
284/* dcan1 */
285static struct omap_hwmod dra7xx_dcan1_hwmod = {
286 .name = "dcan1",
287 .class = &dra7xx_dcan_hwmod_class,
288 .clkdm_name = "wkupaon_clkdm",
289 .main_clk = "dcan1_sys_clk_mux",
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297};
298
299/* dcan2 */
300static struct omap_hwmod dra7xx_dcan2_hwmod = {
301 .name = "dcan2",
302 .class = &dra7xx_dcan_hwmod_class,
303 .clkdm_name = "l4per2_clkdm",
304 .main_clk = "sys_clkin1",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
308 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
310 },
311 },
312};
313
314/*
315 * 'dma' class
316 *
317 */
318
319static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
320 .rev_offs = 0x0000,
321 .sysc_offs = 0x002c,
322 .syss_offs = 0x0028,
323 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
324 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
326 SYSS_HAS_RESET_STATUS),
327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
328 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
329 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
330 .sysc_fields = &omap_hwmod_sysc_type1,
331};
332
333static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
334 .name = "dma",
335 .sysc = &dra7xx_dma_sysc,
336};
337
338/* dma dev_attr */
339static struct omap_dma_dev_attr dma_dev_attr = {
340 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
341 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
342 .lch_count = 32,
343};
344
345/* dma_system */
346static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
351 { .irq = -1 }
352};
353
354static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div",
360 .prcm = {
361 .omap4 = {
362 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
363 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
364 },
365 },
366 .dev_attr = &dma_dev_attr,
367};
368
369/*
370 * 'dss' class
371 *
372 */
373
374static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
375 .rev_offs = 0x0000,
376 .syss_offs = 0x0014,
377 .sysc_flags = SYSS_HAS_RESET_STATUS,
378};
379
380static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
381 .name = "dss",
382 .sysc = &dra7xx_dss_sysc,
383 .reset = omap_dss_reset,
384};
385
386/* dss */
387static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
388 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
389 { .dma_req = -1 }
390};
391
392static struct omap_hwmod_opt_clk dss_opt_clks[] = {
393 { .role = "dss_clk", .clk = "dss_dss_clk" },
394 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
395 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
396 { .role = "video2_clk", .clk = "dss_video2_clk" },
397 { .role = "video1_clk", .clk = "dss_video1_clk" },
398 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
399};
400
401static struct omap_hwmod dra7xx_dss_hwmod = {
402 .name = "dss_core",
403 .class = &dra7xx_dss_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406 .sdma_reqs = dra7xx_dss_sdma_reqs,
407 .main_clk = "dss_dss_clk",
408 .prcm = {
409 .omap4 = {
410 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
412 .modulemode = MODULEMODE_SWCTRL,
413 },
414 },
415 .opt_clks = dss_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
417};
418
419/*
420 * 'dispc' class
421 * display controller
422 */
423
424static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
425 .rev_offs = 0x0000,
426 .sysc_offs = 0x0010,
427 .syss_offs = 0x0014,
428 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
429 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
430 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
431 SYSS_HAS_RESET_STATUS),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
435};
436
437static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
438 .name = "dispc",
439 .sysc = &dra7xx_dispc_sysc,
440};
441
442/* dss_dispc */
443/* dss_dispc dev_attr */
444static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
445 .has_framedonetv_irq = 1,
446 .manager_count = 4,
447};
448
449static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
450 .name = "dss_dispc",
451 .class = &dra7xx_dispc_hwmod_class,
452 .clkdm_name = "dss_clkdm",
453 .main_clk = "dss_dss_clk",
454 .prcm = {
455 .omap4 = {
456 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
457 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
458 },
459 },
460 .dev_attr = &dss_dispc_dev_attr,
461};
462
463/*
464 * 'hdmi' class
465 * hdmi controller
466 */
467
468static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
469 .rev_offs = 0x0000,
470 .sysc_offs = 0x0010,
471 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
472 SYSC_HAS_SOFTRESET),
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
474 SIDLE_SMART_WKUP),
475 .sysc_fields = &omap_hwmod_sysc_type2,
476};
477
478static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
479 .name = "hdmi",
480 .sysc = &dra7xx_hdmi_sysc,
481};
482
483/* dss_hdmi */
484
485static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
486 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
487};
488
489static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
490 .name = "dss_hdmi",
491 .class = &dra7xx_hdmi_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_48mhz_clk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
498 },
499 },
500 .opt_clks = dss_hdmi_opt_clks,
501 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
502};
503
504/*
505 * 'elm' class
506 *
507 */
508
509static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
510 .rev_offs = 0x0000,
511 .sysc_offs = 0x0010,
512 .syss_offs = 0x0014,
513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
514 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSS_HAS_RESET_STATUS),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
517 SIDLE_SMART_WKUP),
518 .sysc_fields = &omap_hwmod_sysc_type1,
519};
520
521static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
522 .name = "elm",
523 .sysc = &dra7xx_elm_sysc,
524};
525
526/* elm */
527
528static struct omap_hwmod dra7xx_elm_hwmod = {
529 .name = "elm",
530 .class = &dra7xx_elm_hwmod_class,
531 .clkdm_name = "l4per_clkdm",
532 .main_clk = "l3_iclk_div",
533 .prcm = {
534 .omap4 = {
535 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
537 },
538 },
539};
540
541/*
542 * 'gpio' class
543 *
544 */
545
546static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
547 .rev_offs = 0x0000,
548 .sysc_offs = 0x0010,
549 .syss_offs = 0x0114,
550 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
551 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
552 SYSS_HAS_RESET_STATUS),
553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
554 SIDLE_SMART_WKUP),
555 .sysc_fields = &omap_hwmod_sysc_type1,
556};
557
558static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
559 .name = "gpio",
560 .sysc = &dra7xx_gpio_sysc,
561 .rev = 2,
562};
563
564/* gpio dev_attr */
565static struct omap_gpio_dev_attr gpio_dev_attr = {
566 .bank_width = 32,
567 .dbck_flag = true,
568};
569
570/* gpio1 */
571static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
572 { .role = "dbclk", .clk = "gpio1_dbclk" },
573};
574
575static struct omap_hwmod dra7xx_gpio1_hwmod = {
576 .name = "gpio1",
577 .class = &dra7xx_gpio_hwmod_class,
578 .clkdm_name = "wkupaon_clkdm",
579 .main_clk = "wkupaon_iclk_mux",
580 .prcm = {
581 .omap4 = {
582 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
583 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
584 .modulemode = MODULEMODE_HWCTRL,
585 },
586 },
587 .opt_clks = gpio1_opt_clks,
588 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
589 .dev_attr = &gpio_dev_attr,
590};
591
592/* gpio2 */
593static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
594 { .role = "dbclk", .clk = "gpio2_dbclk" },
595};
596
597static struct omap_hwmod dra7xx_gpio2_hwmod = {
598 .name = "gpio2",
599 .class = &dra7xx_gpio_hwmod_class,
600 .clkdm_name = "l4per_clkdm",
601 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
602 .main_clk = "l3_iclk_div",
603 .prcm = {
604 .omap4 = {
605 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
606 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
607 .modulemode = MODULEMODE_HWCTRL,
608 },
609 },
610 .opt_clks = gpio2_opt_clks,
611 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
612 .dev_attr = &gpio_dev_attr,
613};
614
615/* gpio3 */
616static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
617 { .role = "dbclk", .clk = "gpio3_dbclk" },
618};
619
620static struct omap_hwmod dra7xx_gpio3_hwmod = {
621 .name = "gpio3",
622 .class = &dra7xx_gpio_hwmod_class,
623 .clkdm_name = "l4per_clkdm",
624 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
625 .main_clk = "l3_iclk_div",
626 .prcm = {
627 .omap4 = {
628 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
629 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
631 },
632 },
633 .opt_clks = gpio3_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
635 .dev_attr = &gpio_dev_attr,
636};
637
638/* gpio4 */
639static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
640 { .role = "dbclk", .clk = "gpio4_dbclk" },
641};
642
643static struct omap_hwmod dra7xx_gpio4_hwmod = {
644 .name = "gpio4",
645 .class = &dra7xx_gpio_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .main_clk = "l3_iclk_div",
649 .prcm = {
650 .omap4 = {
651 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
652 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_HWCTRL,
654 },
655 },
656 .opt_clks = gpio4_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
658 .dev_attr = &gpio_dev_attr,
659};
660
661/* gpio5 */
662static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
663 { .role = "dbclk", .clk = "gpio5_dbclk" },
664};
665
666static struct omap_hwmod dra7xx_gpio5_hwmod = {
667 .name = "gpio5",
668 .class = &dra7xx_gpio_hwmod_class,
669 .clkdm_name = "l4per_clkdm",
670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
671 .main_clk = "l3_iclk_div",
672 .prcm = {
673 .omap4 = {
674 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
675 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
676 .modulemode = MODULEMODE_HWCTRL,
677 },
678 },
679 .opt_clks = gpio5_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
681 .dev_attr = &gpio_dev_attr,
682};
683
684/* gpio6 */
685static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
686 { .role = "dbclk", .clk = "gpio6_dbclk" },
687};
688
689static struct omap_hwmod dra7xx_gpio6_hwmod = {
690 .name = "gpio6",
691 .class = &dra7xx_gpio_hwmod_class,
692 .clkdm_name = "l4per_clkdm",
693 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694 .main_clk = "l3_iclk_div",
695 .prcm = {
696 .omap4 = {
697 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
698 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
700 },
701 },
702 .opt_clks = gpio6_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
704 .dev_attr = &gpio_dev_attr,
705};
706
707/* gpio7 */
708static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio7_dbclk" },
710};
711
712static struct omap_hwmod dra7xx_gpio7_hwmod = {
713 .name = "gpio7",
714 .class = &dra7xx_gpio_hwmod_class,
715 .clkdm_name = "l4per_clkdm",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .main_clk = "l3_iclk_div",
718 .prcm = {
719 .omap4 = {
720 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
721 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
722 .modulemode = MODULEMODE_HWCTRL,
723 },
724 },
725 .opt_clks = gpio7_opt_clks,
726 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
727 .dev_attr = &gpio_dev_attr,
728};
729
730/* gpio8 */
731static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
732 { .role = "dbclk", .clk = "gpio8_dbclk" },
733};
734
735static struct omap_hwmod dra7xx_gpio8_hwmod = {
736 .name = "gpio8",
737 .class = &dra7xx_gpio_hwmod_class,
738 .clkdm_name = "l4per_clkdm",
739 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
740 .main_clk = "l3_iclk_div",
741 .prcm = {
742 .omap4 = {
743 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
744 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
745 .modulemode = MODULEMODE_HWCTRL,
746 },
747 },
748 .opt_clks = gpio8_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
750 .dev_attr = &gpio_dev_attr,
751};
752
753/*
754 * 'gpmc' class
755 *
756 */
757
758static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
759 .rev_offs = 0x0000,
760 .sysc_offs = 0x0010,
761 .syss_offs = 0x0014,
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
765 SIDLE_SMART_WKUP),
766 .sysc_fields = &omap_hwmod_sysc_type1,
767};
768
769static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
770 .name = "gpmc",
771 .sysc = &dra7xx_gpmc_sysc,
772};
773
774/* gpmc */
775
776static struct omap_hwmod dra7xx_gpmc_hwmod = {
777 .name = "gpmc",
778 .class = &dra7xx_gpmc_hwmod_class,
779 .clkdm_name = "l3main1_clkdm",
780 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
781 .main_clk = "l3_iclk_div",
782 .prcm = {
783 .omap4 = {
784 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
787 },
788 },
789};
790
791/*
792 * 'hdq1w' class
793 *
794 */
795
796static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
797 .rev_offs = 0x0000,
798 .sysc_offs = 0x0014,
799 .syss_offs = 0x0018,
800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
801 SYSS_HAS_RESET_STATUS),
802 .sysc_fields = &omap_hwmod_sysc_type1,
803};
804
805static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
806 .name = "hdq1w",
807 .sysc = &dra7xx_hdq1w_sysc,
808};
809
810/* hdq1w */
811
812static struct omap_hwmod dra7xx_hdq1w_hwmod = {
813 .name = "hdq1w",
814 .class = &dra7xx_hdq1w_hwmod_class,
815 .clkdm_name = "l4per_clkdm",
816 .flags = HWMOD_INIT_NO_RESET,
817 .main_clk = "func_12m_fclk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825};
826
827/*
828 * 'i2c' class
829 *
830 */
831
832static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
833 .sysc_offs = 0x0010,
834 .syss_offs = 0x0090,
835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
836 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
837 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
839 SIDLE_SMART_WKUP),
840 .clockact = CLOCKACT_TEST_ICLK,
841 .sysc_fields = &omap_hwmod_sysc_type1,
842};
843
844static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
845 .name = "i2c",
846 .sysc = &dra7xx_i2c_sysc,
847 .reset = &omap_i2c_reset,
848 .rev = OMAP_I2C_IP_VERSION_2,
849};
850
851/* i2c dev_attr */
852static struct omap_i2c_dev_attr i2c_dev_attr = {
853 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
854};
855
856/* i2c1 */
857static struct omap_hwmod dra7xx_i2c1_hwmod = {
858 .name = "i2c1",
859 .class = &dra7xx_i2c_hwmod_class,
860 .clkdm_name = "l4per_clkdm",
861 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
862 .main_clk = "func_96m_fclk",
863 .prcm = {
864 .omap4 = {
865 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
866 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
868 },
869 },
870 .dev_attr = &i2c_dev_attr,
871};
872
873/* i2c2 */
874static struct omap_hwmod dra7xx_i2c2_hwmod = {
875 .name = "i2c2",
876 .class = &dra7xx_i2c_hwmod_class,
877 .clkdm_name = "l4per_clkdm",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .main_clk = "func_96m_fclk",
880 .prcm = {
881 .omap4 = {
882 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
883 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
884 .modulemode = MODULEMODE_SWCTRL,
885 },
886 },
887 .dev_attr = &i2c_dev_attr,
888};
889
890/* i2c3 */
891static struct omap_hwmod dra7xx_i2c3_hwmod = {
892 .name = "i2c3",
893 .class = &dra7xx_i2c_hwmod_class,
894 .clkdm_name = "l4per_clkdm",
895 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
896 .main_clk = "func_96m_fclk",
897 .prcm = {
898 .omap4 = {
899 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
900 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
902 },
903 },
904 .dev_attr = &i2c_dev_attr,
905};
906
907/* i2c4 */
908static struct omap_hwmod dra7xx_i2c4_hwmod = {
909 .name = "i2c4",
910 .class = &dra7xx_i2c_hwmod_class,
911 .clkdm_name = "l4per_clkdm",
912 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
913 .main_clk = "func_96m_fclk",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
917 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
919 },
920 },
921 .dev_attr = &i2c_dev_attr,
922};
923
924/* i2c5 */
925static struct omap_hwmod dra7xx_i2c5_hwmod = {
926 .name = "i2c5",
927 .class = &dra7xx_i2c_hwmod_class,
928 .clkdm_name = "ipu_clkdm",
929 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
930 .main_clk = "func_96m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &i2c_dev_attr,
939};
940
941/*
942 * 'mcspi' class
943 *
944 */
945
946static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
950 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
952 SIDLE_SMART_WKUP),
953 .sysc_fields = &omap_hwmod_sysc_type2,
954};
955
956static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
957 .name = "mcspi",
958 .sysc = &dra7xx_mcspi_sysc,
959 .rev = OMAP4_MCSPI_REV,
960};
961
962/* mcspi1 */
963/* mcspi1 dev_attr */
964static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
965 .num_chipselect = 4,
966};
967
968static struct omap_hwmod dra7xx_mcspi1_hwmod = {
969 .name = "mcspi1",
970 .class = &dra7xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi1_dev_attr,
981};
982
983/* mcspi2 */
984/* mcspi2 dev_attr */
985static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
986 .num_chipselect = 2,
987};
988
989static struct omap_hwmod dra7xx_mcspi2_hwmod = {
990 .name = "mcspi2",
991 .class = &dra7xx_mcspi_hwmod_class,
992 .clkdm_name = "l4per_clkdm",
993 .main_clk = "func_48m_fclk",
994 .prcm = {
995 .omap4 = {
996 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
999 },
1000 },
1001 .dev_attr = &mcspi2_dev_attr,
1002};
1003
1004/* mcspi3 */
1005/* mcspi3 dev_attr */
1006static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007 .num_chipselect = 2,
1008};
1009
1010static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1011 .name = "mcspi3",
1012 .class = &dra7xx_mcspi_hwmod_class,
1013 .clkdm_name = "l4per_clkdm",
1014 .main_clk = "func_48m_fclk",
1015 .prcm = {
1016 .omap4 = {
1017 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1020 },
1021 },
1022 .dev_attr = &mcspi3_dev_attr,
1023};
1024
1025/* mcspi4 */
1026/* mcspi4 dev_attr */
1027static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028 .num_chipselect = 1,
1029};
1030
1031static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1032 .name = "mcspi4",
1033 .class = &dra7xx_mcspi_hwmod_class,
1034 .clkdm_name = "l4per_clkdm",
1035 .main_clk = "func_48m_fclk",
1036 .prcm = {
1037 .omap4 = {
1038 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040 .modulemode = MODULEMODE_SWCTRL,
1041 },
1042 },
1043 .dev_attr = &mcspi4_dev_attr,
1044};
1045
1046/*
1047 * 'mmc' class
1048 *
1049 */
1050
1051static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1052 .rev_offs = 0x0000,
1053 .sysc_offs = 0x0010,
1054 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1061};
1062
1063static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1064 .name = "mmc",
1065 .sysc = &dra7xx_mmc_sysc,
1066};
1067
1068/* mmc1 */
1069static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070 { .role = "clk32k", .clk = "mmc1_clk32k" },
1071};
1072
1073/* mmc1 dev_attr */
1074static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1076};
1077
1078static struct omap_hwmod dra7xx_mmc1_hwmod = {
1079 .name = "mmc1",
1080 .class = &dra7xx_mmc_hwmod_class,
1081 .clkdm_name = "l3init_clkdm",
1082 .main_clk = "mmc1_fclk_div",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090 .opt_clks = mmc1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1092 .dev_attr = &mmc1_dev_attr,
1093};
1094
1095/* mmc2 */
1096static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097 { .role = "clk32k", .clk = "mmc2_clk32k" },
1098};
1099
1100static struct omap_hwmod dra7xx_mmc2_hwmod = {
1101 .name = "mmc2",
1102 .class = &dra7xx_mmc_hwmod_class,
1103 .clkdm_name = "l3init_clkdm",
1104 .main_clk = "mmc2_fclk_div",
1105 .prcm = {
1106 .omap4 = {
1107 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1110 },
1111 },
1112 .opt_clks = mmc2_opt_clks,
1113 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1114};
1115
1116/* mmc3 */
1117static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118 { .role = "clk32k", .clk = "mmc3_clk32k" },
1119};
1120
1121static struct omap_hwmod dra7xx_mmc3_hwmod = {
1122 .name = "mmc3",
1123 .class = &dra7xx_mmc_hwmod_class,
1124 .clkdm_name = "l4per_clkdm",
1125 .main_clk = "mmc3_gfclk_div",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1131 },
1132 },
1133 .opt_clks = mmc3_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1135};
1136
1137/* mmc4 */
1138static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139 { .role = "clk32k", .clk = "mmc4_clk32k" },
1140};
1141
1142static struct omap_hwmod dra7xx_mmc4_hwmod = {
1143 .name = "mmc4",
1144 .class = &dra7xx_mmc_hwmod_class,
1145 .clkdm_name = "l4per_clkdm",
1146 .main_clk = "mmc4_gfclk_div",
1147 .prcm = {
1148 .omap4 = {
1149 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1152 },
1153 },
1154 .opt_clks = mmc4_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1156};
1157
1158/*
1159 * 'mpu' class
1160 *
1161 */
1162
1163static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1164 .name = "mpu",
1165};
1166
1167/* mpu */
1168static struct omap_hwmod dra7xx_mpu_hwmod = {
1169 .name = "mpu",
1170 .class = &dra7xx_mpu_hwmod_class,
1171 .clkdm_name = "mpu_clkdm",
1172 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173 .main_clk = "dpll_mpu_m2_ck",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1178 },
1179 },
1180};
1181
1182/*
1183 * 'ocp2scp' class
1184 *
1185 */
1186
1187static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1188 .rev_offs = 0x0000,
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0014,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1194 SIDLE_SMART_WKUP),
1195 .sysc_fields = &omap_hwmod_sysc_type1,
1196};
1197
1198static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1199 .name = "ocp2scp",
1200 .sysc = &dra7xx_ocp2scp_sysc,
1201};
1202
1203/* ocp2scp1 */
1204static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1205 .name = "ocp2scp1",
1206 .class = &dra7xx_ocp2scp_hwmod_class,
1207 .clkdm_name = "l3init_clkdm",
1208 .main_clk = "l4_root_clk_div",
1209 .prcm = {
1210 .omap4 = {
1211 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213 .modulemode = MODULEMODE_HWCTRL,
1214 },
1215 },
1216};
1217
1218/*
1219 * 'qspi' class
1220 *
1221 */
1222
1223static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1224 .sysc_offs = 0x0010,
1225 .sysc_flags = SYSC_HAS_SIDLEMODE,
1226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1227 SIDLE_SMART_WKUP),
1228 .sysc_fields = &omap_hwmod_sysc_type2,
1229};
1230
1231static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1232 .name = "qspi",
1233 .sysc = &dra7xx_qspi_sysc,
1234};
1235
1236/* qspi */
1237static struct omap_hwmod dra7xx_qspi_hwmod = {
1238 .name = "qspi",
1239 .class = &dra7xx_qspi_hwmod_class,
1240 .clkdm_name = "l4per2_clkdm",
1241 .main_clk = "qspi_gfclk_div",
1242 .prcm = {
1243 .omap4 = {
1244 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1245 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1246 .modulemode = MODULEMODE_SWCTRL,
1247 },
1248 },
1249};
1250
1251/*
1252 * 'sata' class
1253 *
1254 */
1255
1256static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1257 .sysc_offs = 0x0000,
1258 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1260 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1261 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1262 .sysc_fields = &omap_hwmod_sysc_type2,
1263};
1264
1265static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1266 .name = "sata",
1267 .sysc = &dra7xx_sata_sysc,
1268};
1269
1270/* sata */
1271static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1272 { .role = "ref_clk", .clk = "sata_ref_clk" },
1273};
1274
1275static struct omap_hwmod dra7xx_sata_hwmod = {
1276 .name = "sata",
1277 .class = &dra7xx_sata_hwmod_class,
1278 .clkdm_name = "l3init_clkdm",
1279 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1280 .main_clk = "func_48m_fclk",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1284 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288 .opt_clks = sata_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1290};
1291
1292/*
1293 * 'smartreflex' class
1294 *
1295 */
1296
1297/* The IP is not compliant to type1 / type2 scheme */
1298static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1299 .sidle_shift = 24,
1300 .enwkup_shift = 26,
1301};
1302
1303static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1304 .sysc_offs = 0x0038,
1305 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307 SIDLE_SMART_WKUP),
1308 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1309};
1310
1311static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1312 .name = "smartreflex",
1313 .sysc = &dra7xx_smartreflex_sysc,
1314 .rev = 2,
1315};
1316
1317/* smartreflex_core */
1318/* smartreflex_core dev_attr */
1319static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1320 .sensor_voltdm_name = "core",
1321};
1322
1323static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1324 .name = "smartreflex_core",
1325 .class = &dra7xx_smartreflex_hwmod_class,
1326 .clkdm_name = "coreaon_clkdm",
1327 .main_clk = "wkupaon_iclk_mux",
1328 .prcm = {
1329 .omap4 = {
1330 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1331 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1333 },
1334 },
1335 .dev_attr = &smartreflex_core_dev_attr,
1336};
1337
1338/* smartreflex_mpu */
1339/* smartreflex_mpu dev_attr */
1340static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1341 .sensor_voltdm_name = "mpu",
1342};
1343
1344static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1345 .name = "smartreflex_mpu",
1346 .class = &dra7xx_smartreflex_hwmod_class,
1347 .clkdm_name = "coreaon_clkdm",
1348 .main_clk = "wkupaon_iclk_mux",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1352 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356 .dev_attr = &smartreflex_mpu_dev_attr,
1357};
1358
1359/*
1360 * 'spinlock' class
1361 *
1362 */
1363
1364static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010,
1367 .syss_offs = 0x0014,
1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1369 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1370 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1372 SIDLE_SMART_WKUP),
1373 .sysc_fields = &omap_hwmod_sysc_type1,
1374};
1375
1376static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1377 .name = "spinlock",
1378 .sysc = &dra7xx_spinlock_sysc,
1379};
1380
1381/* spinlock */
1382static struct omap_hwmod dra7xx_spinlock_hwmod = {
1383 .name = "spinlock",
1384 .class = &dra7xx_spinlock_hwmod_class,
1385 .clkdm_name = "l4cfg_clkdm",
1386 .main_clk = "l3_iclk_div",
1387 .prcm = {
1388 .omap4 = {
1389 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1390 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1391 },
1392 },
1393};
1394
1395/*
1396 * 'timer' class
1397 *
1398 * This class contains several variants: ['timer_1ms', 'timer_secure',
1399 * 'timer']
1400 */
1401
1402static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1403 .rev_offs = 0x0000,
1404 .sysc_offs = 0x0010,
1405 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1406 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1407 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1408 SIDLE_SMART_WKUP),
1409 .sysc_fields = &omap_hwmod_sysc_type2,
1410};
1411
1412static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1413 .name = "timer",
1414 .sysc = &dra7xx_timer_1ms_sysc,
1415};
1416
1417static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1418 .rev_offs = 0x0000,
1419 .sysc_offs = 0x0010,
1420 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1421 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1422 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1423 SIDLE_SMART_WKUP),
1424 .sysc_fields = &omap_hwmod_sysc_type2,
1425};
1426
1427static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1428 .name = "timer",
1429 .sysc = &dra7xx_timer_secure_sysc,
1430};
1431
1432static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1433 .rev_offs = 0x0000,
1434 .sysc_offs = 0x0010,
1435 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1436 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1437 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1438 SIDLE_SMART_WKUP),
1439 .sysc_fields = &omap_hwmod_sysc_type2,
1440};
1441
1442static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1443 .name = "timer",
1444 .sysc = &dra7xx_timer_sysc,
1445};
1446
1447/* timer1 */
1448static struct omap_hwmod dra7xx_timer1_hwmod = {
1449 .name = "timer1",
1450 .class = &dra7xx_timer_1ms_hwmod_class,
1451 .clkdm_name = "wkupaon_clkdm",
1452 .main_clk = "timer1_gfclk_mux",
1453 .prcm = {
1454 .omap4 = {
1455 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1456 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1457 .modulemode = MODULEMODE_SWCTRL,
1458 },
1459 },
1460};
1461
1462/* timer2 */
1463static struct omap_hwmod dra7xx_timer2_hwmod = {
1464 .name = "timer2",
1465 .class = &dra7xx_timer_1ms_hwmod_class,
1466 .clkdm_name = "l4per_clkdm",
1467 .main_clk = "timer2_gfclk_mux",
1468 .prcm = {
1469 .omap4 = {
1470 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1471 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1472 .modulemode = MODULEMODE_SWCTRL,
1473 },
1474 },
1475};
1476
1477/* timer3 */
1478static struct omap_hwmod dra7xx_timer3_hwmod = {
1479 .name = "timer3",
1480 .class = &dra7xx_timer_hwmod_class,
1481 .clkdm_name = "l4per_clkdm",
1482 .main_clk = "timer3_gfclk_mux",
1483 .prcm = {
1484 .omap4 = {
1485 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1486 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1487 .modulemode = MODULEMODE_SWCTRL,
1488 },
1489 },
1490};
1491
1492/* timer4 */
1493static struct omap_hwmod dra7xx_timer4_hwmod = {
1494 .name = "timer4",
1495 .class = &dra7xx_timer_secure_hwmod_class,
1496 .clkdm_name = "l4per_clkdm",
1497 .main_clk = "timer4_gfclk_mux",
1498 .prcm = {
1499 .omap4 = {
1500 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1501 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1502 .modulemode = MODULEMODE_SWCTRL,
1503 },
1504 },
1505};
1506
1507/* timer5 */
1508static struct omap_hwmod dra7xx_timer5_hwmod = {
1509 .name = "timer5",
1510 .class = &dra7xx_timer_hwmod_class,
1511 .clkdm_name = "ipu_clkdm",
1512 .main_clk = "timer5_gfclk_mux",
1513 .prcm = {
1514 .omap4 = {
1515 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1516 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1517 .modulemode = MODULEMODE_SWCTRL,
1518 },
1519 },
1520};
1521
1522/* timer6 */
1523static struct omap_hwmod dra7xx_timer6_hwmod = {
1524 .name = "timer6",
1525 .class = &dra7xx_timer_hwmod_class,
1526 .clkdm_name = "ipu_clkdm",
1527 .main_clk = "timer6_gfclk_mux",
1528 .prcm = {
1529 .omap4 = {
1530 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1531 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1532 .modulemode = MODULEMODE_SWCTRL,
1533 },
1534 },
1535};
1536
1537/* timer7 */
1538static struct omap_hwmod dra7xx_timer7_hwmod = {
1539 .name = "timer7",
1540 .class = &dra7xx_timer_hwmod_class,
1541 .clkdm_name = "ipu_clkdm",
1542 .main_clk = "timer7_gfclk_mux",
1543 .prcm = {
1544 .omap4 = {
1545 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1546 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1547 .modulemode = MODULEMODE_SWCTRL,
1548 },
1549 },
1550};
1551
1552/* timer8 */
1553static struct omap_hwmod dra7xx_timer8_hwmod = {
1554 .name = "timer8",
1555 .class = &dra7xx_timer_hwmod_class,
1556 .clkdm_name = "ipu_clkdm",
1557 .main_clk = "timer8_gfclk_mux",
1558 .prcm = {
1559 .omap4 = {
1560 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1561 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1562 .modulemode = MODULEMODE_SWCTRL,
1563 },
1564 },
1565};
1566
1567/* timer9 */
1568static struct omap_hwmod dra7xx_timer9_hwmod = {
1569 .name = "timer9",
1570 .class = &dra7xx_timer_hwmod_class,
1571 .clkdm_name = "l4per_clkdm",
1572 .main_clk = "timer9_gfclk_mux",
1573 .prcm = {
1574 .omap4 = {
1575 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1576 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1577 .modulemode = MODULEMODE_SWCTRL,
1578 },
1579 },
1580};
1581
1582/* timer10 */
1583static struct omap_hwmod dra7xx_timer10_hwmod = {
1584 .name = "timer10",
1585 .class = &dra7xx_timer_1ms_hwmod_class,
1586 .clkdm_name = "l4per_clkdm",
1587 .main_clk = "timer10_gfclk_mux",
1588 .prcm = {
1589 .omap4 = {
1590 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1591 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1592 .modulemode = MODULEMODE_SWCTRL,
1593 },
1594 },
1595};
1596
1597/* timer11 */
1598static struct omap_hwmod dra7xx_timer11_hwmod = {
1599 .name = "timer11",
1600 .class = &dra7xx_timer_hwmod_class,
1601 .clkdm_name = "l4per_clkdm",
1602 .main_clk = "timer11_gfclk_mux",
1603 .prcm = {
1604 .omap4 = {
1605 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1606 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1607 .modulemode = MODULEMODE_SWCTRL,
1608 },
1609 },
1610};
1611
1612/*
1613 * 'uart' class
1614 *
1615 */
1616
1617static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1618 .rev_offs = 0x0050,
1619 .sysc_offs = 0x0054,
1620 .syss_offs = 0x0058,
1621 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1622 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1623 SYSS_HAS_RESET_STATUS),
1624 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1625 SIDLE_SMART_WKUP),
1626 .sysc_fields = &omap_hwmod_sysc_type1,
1627};
1628
1629static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1630 .name = "uart",
1631 .sysc = &dra7xx_uart_sysc,
1632};
1633
1634/* uart1 */
1635static struct omap_hwmod dra7xx_uart1_hwmod = {
1636 .name = "uart1",
1637 .class = &dra7xx_uart_hwmod_class,
1638 .clkdm_name = "l4per_clkdm",
1639 .main_clk = "uart1_gfclk_mux",
1640 .flags = HWMOD_SWSUP_SIDLE_ACT,
1641 .prcm = {
1642 .omap4 = {
1643 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1644 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1645 .modulemode = MODULEMODE_SWCTRL,
1646 },
1647 },
1648};
1649
1650/* uart2 */
1651static struct omap_hwmod dra7xx_uart2_hwmod = {
1652 .name = "uart2",
1653 .class = &dra7xx_uart_hwmod_class,
1654 .clkdm_name = "l4per_clkdm",
1655 .main_clk = "uart2_gfclk_mux",
1656 .flags = HWMOD_SWSUP_SIDLE_ACT,
1657 .prcm = {
1658 .omap4 = {
1659 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1660 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1661 .modulemode = MODULEMODE_SWCTRL,
1662 },
1663 },
1664};
1665
1666/* uart3 */
1667static struct omap_hwmod dra7xx_uart3_hwmod = {
1668 .name = "uart3",
1669 .class = &dra7xx_uart_hwmod_class,
1670 .clkdm_name = "l4per_clkdm",
1671 .main_clk = "uart3_gfclk_mux",
1672 .flags = HWMOD_SWSUP_SIDLE_ACT,
1673 .prcm = {
1674 .omap4 = {
1675 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1676 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1677 .modulemode = MODULEMODE_SWCTRL,
1678 },
1679 },
1680};
1681
1682/* uart4 */
1683static struct omap_hwmod dra7xx_uart4_hwmod = {
1684 .name = "uart4",
1685 .class = &dra7xx_uart_hwmod_class,
1686 .clkdm_name = "l4per_clkdm",
1687 .main_clk = "uart4_gfclk_mux",
1688 .flags = HWMOD_SWSUP_SIDLE_ACT,
1689 .prcm = {
1690 .omap4 = {
1691 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1692 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1693 .modulemode = MODULEMODE_SWCTRL,
1694 },
1695 },
1696};
1697
1698/* uart5 */
1699static struct omap_hwmod dra7xx_uart5_hwmod = {
1700 .name = "uart5",
1701 .class = &dra7xx_uart_hwmod_class,
1702 .clkdm_name = "l4per_clkdm",
1703 .main_clk = "uart5_gfclk_mux",
1704 .flags = HWMOD_SWSUP_SIDLE_ACT,
1705 .prcm = {
1706 .omap4 = {
1707 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1708 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1709 .modulemode = MODULEMODE_SWCTRL,
1710 },
1711 },
1712};
1713
1714/* uart6 */
1715static struct omap_hwmod dra7xx_uart6_hwmod = {
1716 .name = "uart6",
1717 .class = &dra7xx_uart_hwmod_class,
1718 .clkdm_name = "ipu_clkdm",
1719 .main_clk = "uart6_gfclk_mux",
1720 .flags = HWMOD_SWSUP_SIDLE_ACT,
1721 .prcm = {
1722 .omap4 = {
1723 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1724 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1725 .modulemode = MODULEMODE_SWCTRL,
1726 },
1727 },
1728};
1729
1730/*
1731 * 'usb_otg_ss' class
1732 *
1733 */
1734
1735static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1736 .name = "usb_otg_ss",
1737};
1738
1739/* usb_otg_ss1 */
1740static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1741 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1742};
1743
1744static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1745 .name = "usb_otg_ss1",
1746 .class = &dra7xx_usb_otg_ss_hwmod_class,
1747 .clkdm_name = "l3init_clkdm",
1748 .main_clk = "dpll_core_h13x2_ck",
1749 .prcm = {
1750 .omap4 = {
1751 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1752 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1753 .modulemode = MODULEMODE_HWCTRL,
1754 },
1755 },
1756 .opt_clks = usb_otg_ss1_opt_clks,
1757 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1758};
1759
1760/* usb_otg_ss2 */
1761static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1762 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1763};
1764
1765static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1766 .name = "usb_otg_ss2",
1767 .class = &dra7xx_usb_otg_ss_hwmod_class,
1768 .clkdm_name = "l3init_clkdm",
1769 .main_clk = "dpll_core_h13x2_ck",
1770 .prcm = {
1771 .omap4 = {
1772 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1773 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1774 .modulemode = MODULEMODE_HWCTRL,
1775 },
1776 },
1777 .opt_clks = usb_otg_ss2_opt_clks,
1778 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1779};
1780
1781/* usb_otg_ss3 */
1782static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1783 .name = "usb_otg_ss3",
1784 .class = &dra7xx_usb_otg_ss_hwmod_class,
1785 .clkdm_name = "l3init_clkdm",
1786 .main_clk = "dpll_core_h13x2_ck",
1787 .prcm = {
1788 .omap4 = {
1789 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1790 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1791 .modulemode = MODULEMODE_HWCTRL,
1792 },
1793 },
1794};
1795
1796/* usb_otg_ss4 */
1797static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1798 .name = "usb_otg_ss4",
1799 .class = &dra7xx_usb_otg_ss_hwmod_class,
1800 .clkdm_name = "l3init_clkdm",
1801 .main_clk = "dpll_core_h13x2_ck",
1802 .prcm = {
1803 .omap4 = {
1804 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1805 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1806 .modulemode = MODULEMODE_HWCTRL,
1807 },
1808 },
1809};
1810
1811/*
1812 * 'vcp' class
1813 *
1814 */
1815
1816static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1817 .name = "vcp",
1818};
1819
1820/* vcp1 */
1821static struct omap_hwmod dra7xx_vcp1_hwmod = {
1822 .name = "vcp1",
1823 .class = &dra7xx_vcp_hwmod_class,
1824 .clkdm_name = "l3main1_clkdm",
1825 .main_clk = "l3_iclk_div",
1826 .prcm = {
1827 .omap4 = {
1828 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1829 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1830 },
1831 },
1832};
1833
1834/* vcp2 */
1835static struct omap_hwmod dra7xx_vcp2_hwmod = {
1836 .name = "vcp2",
1837 .class = &dra7xx_vcp_hwmod_class,
1838 .clkdm_name = "l3main1_clkdm",
1839 .main_clk = "l3_iclk_div",
1840 .prcm = {
1841 .omap4 = {
1842 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1843 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1844 },
1845 },
1846};
1847
1848/*
1849 * 'wd_timer' class
1850 *
1851 */
1852
1853static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1854 .rev_offs = 0x0000,
1855 .sysc_offs = 0x0010,
1856 .syss_offs = 0x0014,
1857 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1858 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1859 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860 SIDLE_SMART_WKUP),
1861 .sysc_fields = &omap_hwmod_sysc_type1,
1862};
1863
1864static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1865 .name = "wd_timer",
1866 .sysc = &dra7xx_wd_timer_sysc,
1867 .pre_shutdown = &omap2_wd_timer_disable,
1868 .reset = &omap2_wd_timer_reset,
1869};
1870
1871/* wd_timer2 */
1872static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1873 .name = "wd_timer2",
1874 .class = &dra7xx_wd_timer_hwmod_class,
1875 .clkdm_name = "wkupaon_clkdm",
1876 .main_clk = "sys_32k_ck",
1877 .prcm = {
1878 .omap4 = {
1879 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1880 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1881 .modulemode = MODULEMODE_SWCTRL,
1882 },
1883 },
1884};
1885
1886
1887/*
1888 * Interfaces
1889 */
1890
1891/* l3_main_2 -> l3_instr */
1892static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1893 .master = &dra7xx_l3_main_2_hwmod,
1894 .slave = &dra7xx_l3_instr_hwmod,
1895 .clk = "l3_iclk_div",
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897};
1898
1899/* l4_cfg -> l3_main_1 */
1900static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1901 .master = &dra7xx_l4_cfg_hwmod,
1902 .slave = &dra7xx_l3_main_1_hwmod,
1903 .clk = "l3_iclk_div",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905};
1906
1907/* mpu -> l3_main_1 */
1908static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1909 .master = &dra7xx_mpu_hwmod,
1910 .slave = &dra7xx_l3_main_1_hwmod,
1911 .clk = "l3_iclk_div",
1912 .user = OCP_USER_MPU,
1913};
1914
1915/* l3_main_1 -> l3_main_2 */
1916static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1917 .master = &dra7xx_l3_main_1_hwmod,
1918 .slave = &dra7xx_l3_main_2_hwmod,
1919 .clk = "l3_iclk_div",
1920 .user = OCP_USER_MPU,
1921};
1922
1923/* l4_cfg -> l3_main_2 */
1924static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1925 .master = &dra7xx_l4_cfg_hwmod,
1926 .slave = &dra7xx_l3_main_2_hwmod,
1927 .clk = "l3_iclk_div",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929};
1930
1931/* l3_main_1 -> l4_cfg */
1932static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1933 .master = &dra7xx_l3_main_1_hwmod,
1934 .slave = &dra7xx_l4_cfg_hwmod,
1935 .clk = "l3_iclk_div",
1936 .user = OCP_USER_MPU | OCP_USER_SDMA,
1937};
1938
1939/* l3_main_1 -> l4_per1 */
1940static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1941 .master = &dra7xx_l3_main_1_hwmod,
1942 .slave = &dra7xx_l4_per1_hwmod,
1943 .clk = "l3_iclk_div",
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945};
1946
1947/* l3_main_1 -> l4_per2 */
1948static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1949 .master = &dra7xx_l3_main_1_hwmod,
1950 .slave = &dra7xx_l4_per2_hwmod,
1951 .clk = "l3_iclk_div",
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1953};
1954
1955/* l3_main_1 -> l4_per3 */
1956static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1957 .master = &dra7xx_l3_main_1_hwmod,
1958 .slave = &dra7xx_l4_per3_hwmod,
1959 .clk = "l3_iclk_div",
1960 .user = OCP_USER_MPU | OCP_USER_SDMA,
1961};
1962
1963/* l3_main_1 -> l4_wkup */
1964static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1965 .master = &dra7xx_l3_main_1_hwmod,
1966 .slave = &dra7xx_l4_wkup_hwmod,
1967 .clk = "wkupaon_iclk_mux",
1968 .user = OCP_USER_MPU | OCP_USER_SDMA,
1969};
1970
1971/* l4_per2 -> atl */
1972static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1973 .master = &dra7xx_l4_per2_hwmod,
1974 .slave = &dra7xx_atl_hwmod,
1975 .clk = "l3_iclk_div",
1976 .user = OCP_USER_MPU | OCP_USER_SDMA,
1977};
1978
1979/* l3_main_1 -> bb2d */
1980static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1981 .master = &dra7xx_l3_main_1_hwmod,
1982 .slave = &dra7xx_bb2d_hwmod,
1983 .clk = "l3_iclk_div",
1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
1985};
1986
1987/* l4_wkup -> counter_32k */
1988static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1989 .master = &dra7xx_l4_wkup_hwmod,
1990 .slave = &dra7xx_counter_32k_hwmod,
1991 .clk = "wkupaon_iclk_mux",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993};
1994
1995/* l4_wkup -> ctrl_module_wkup */
1996static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1997 .master = &dra7xx_l4_wkup_hwmod,
1998 .slave = &dra7xx_ctrl_module_wkup_hwmod,
1999 .clk = "wkupaon_iclk_mux",
2000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001};
2002
2003/* l4_wkup -> dcan1 */
2004static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2005 .master = &dra7xx_l4_wkup_hwmod,
2006 .slave = &dra7xx_dcan1_hwmod,
2007 .clk = "wkupaon_iclk_mux",
2008 .user = OCP_USER_MPU | OCP_USER_SDMA,
2009};
2010
2011/* l4_per2 -> dcan2 */
2012static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2013 .master = &dra7xx_l4_per2_hwmod,
2014 .slave = &dra7xx_dcan2_hwmod,
2015 .clk = "l3_iclk_div",
2016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2017};
2018
2019static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2020 {
2021 .pa_start = 0x4a056000,
2022 .pa_end = 0x4a056fff,
2023 .flags = ADDR_TYPE_RT
2024 },
2025 { }
2026};
2027
2028/* l4_cfg -> dma_system */
2029static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2030 .master = &dra7xx_l4_cfg_hwmod,
2031 .slave = &dra7xx_dma_system_hwmod,
2032 .clk = "l3_iclk_div",
2033 .addr = dra7xx_dma_system_addrs,
2034 .user = OCP_USER_MPU | OCP_USER_SDMA,
2035};
2036
2037static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2038 {
2039 .name = "family",
2040 .pa_start = 0x58000000,
2041 .pa_end = 0x5800007f,
2042 .flags = ADDR_TYPE_RT
2043 },
2044};
2045
2046/* l3_main_1 -> dss */
2047static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2048 .master = &dra7xx_l3_main_1_hwmod,
2049 .slave = &dra7xx_dss_hwmod,
2050 .clk = "l3_iclk_div",
2051 .addr = dra7xx_dss_addrs,
2052 .user = OCP_USER_MPU | OCP_USER_SDMA,
2053};
2054
2055static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2056 {
2057 .name = "dispc",
2058 .pa_start = 0x58001000,
2059 .pa_end = 0x58001fff,
2060 .flags = ADDR_TYPE_RT
2061 },
2062};
2063
2064/* l3_main_1 -> dispc */
2065static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2066 .master = &dra7xx_l3_main_1_hwmod,
2067 .slave = &dra7xx_dss_dispc_hwmod,
2068 .clk = "l3_iclk_div",
2069 .addr = dra7xx_dss_dispc_addrs,
2070 .user = OCP_USER_MPU | OCP_USER_SDMA,
2071};
2072
2073static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2074 {
2075 .name = "hdmi_wp",
2076 .pa_start = 0x58040000,
2077 .pa_end = 0x580400ff,
2078 .flags = ADDR_TYPE_RT
2079 },
2080 { }
2081};
2082
2083/* l3_main_1 -> dispc */
2084static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2085 .master = &dra7xx_l3_main_1_hwmod,
2086 .slave = &dra7xx_dss_hdmi_hwmod,
2087 .clk = "l3_iclk_div",
2088 .addr = dra7xx_dss_hdmi_addrs,
2089 .user = OCP_USER_MPU | OCP_USER_SDMA,
2090};
2091
2092static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2093 {
2094 .pa_start = 0x48078000,
2095 .pa_end = 0x48078fff,
2096 .flags = ADDR_TYPE_RT
2097 },
2098 { }
2099};
2100
2101/* l4_per1 -> elm */
2102static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2103 .master = &dra7xx_l4_per1_hwmod,
2104 .slave = &dra7xx_elm_hwmod,
2105 .clk = "l3_iclk_div",
2106 .addr = dra7xx_elm_addrs,
2107 .user = OCP_USER_MPU | OCP_USER_SDMA,
2108};
2109
2110/* l4_wkup -> gpio1 */
2111static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2112 .master = &dra7xx_l4_wkup_hwmod,
2113 .slave = &dra7xx_gpio1_hwmod,
2114 .clk = "wkupaon_iclk_mux",
2115 .user = OCP_USER_MPU | OCP_USER_SDMA,
2116};
2117
2118/* l4_per1 -> gpio2 */
2119static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2120 .master = &dra7xx_l4_per1_hwmod,
2121 .slave = &dra7xx_gpio2_hwmod,
2122 .clk = "l3_iclk_div",
2123 .user = OCP_USER_MPU | OCP_USER_SDMA,
2124};
2125
2126/* l4_per1 -> gpio3 */
2127static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2128 .master = &dra7xx_l4_per1_hwmod,
2129 .slave = &dra7xx_gpio3_hwmod,
2130 .clk = "l3_iclk_div",
2131 .user = OCP_USER_MPU | OCP_USER_SDMA,
2132};
2133
2134/* l4_per1 -> gpio4 */
2135static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2136 .master = &dra7xx_l4_per1_hwmod,
2137 .slave = &dra7xx_gpio4_hwmod,
2138 .clk = "l3_iclk_div",
2139 .user = OCP_USER_MPU | OCP_USER_SDMA,
2140};
2141
2142/* l4_per1 -> gpio5 */
2143static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2144 .master = &dra7xx_l4_per1_hwmod,
2145 .slave = &dra7xx_gpio5_hwmod,
2146 .clk = "l3_iclk_div",
2147 .user = OCP_USER_MPU | OCP_USER_SDMA,
2148};
2149
2150/* l4_per1 -> gpio6 */
2151static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2152 .master = &dra7xx_l4_per1_hwmod,
2153 .slave = &dra7xx_gpio6_hwmod,
2154 .clk = "l3_iclk_div",
2155 .user = OCP_USER_MPU | OCP_USER_SDMA,
2156};
2157
2158/* l4_per1 -> gpio7 */
2159static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2160 .master = &dra7xx_l4_per1_hwmod,
2161 .slave = &dra7xx_gpio7_hwmod,
2162 .clk = "l3_iclk_div",
2163 .user = OCP_USER_MPU | OCP_USER_SDMA,
2164};
2165
2166/* l4_per1 -> gpio8 */
2167static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2168 .master = &dra7xx_l4_per1_hwmod,
2169 .slave = &dra7xx_gpio8_hwmod,
2170 .clk = "l3_iclk_div",
2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2172};
2173
2174static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2175 {
2176 .pa_start = 0x50000000,
2177 .pa_end = 0x500003ff,
2178 .flags = ADDR_TYPE_RT
2179 },
2180 { }
2181};
2182
2183/* l3_main_1 -> gpmc */
2184static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2185 .master = &dra7xx_l3_main_1_hwmod,
2186 .slave = &dra7xx_gpmc_hwmod,
2187 .clk = "l3_iclk_div",
2188 .addr = dra7xx_gpmc_addrs,
2189 .user = OCP_USER_MPU | OCP_USER_SDMA,
2190};
2191
2192static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2193 {
2194 .pa_start = 0x480b2000,
2195 .pa_end = 0x480b201f,
2196 .flags = ADDR_TYPE_RT
2197 },
2198 { }
2199};
2200
2201/* l4_per1 -> hdq1w */
2202static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2203 .master = &dra7xx_l4_per1_hwmod,
2204 .slave = &dra7xx_hdq1w_hwmod,
2205 .clk = "l3_iclk_div",
2206 .addr = dra7xx_hdq1w_addrs,
2207 .user = OCP_USER_MPU | OCP_USER_SDMA,
2208};
2209
2210/* l4_per1 -> i2c1 */
2211static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2212 .master = &dra7xx_l4_per1_hwmod,
2213 .slave = &dra7xx_i2c1_hwmod,
2214 .clk = "l3_iclk_div",
2215 .user = OCP_USER_MPU | OCP_USER_SDMA,
2216};
2217
2218/* l4_per1 -> i2c2 */
2219static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2220 .master = &dra7xx_l4_per1_hwmod,
2221 .slave = &dra7xx_i2c2_hwmod,
2222 .clk = "l3_iclk_div",
2223 .user = OCP_USER_MPU | OCP_USER_SDMA,
2224};
2225
2226/* l4_per1 -> i2c3 */
2227static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2228 .master = &dra7xx_l4_per1_hwmod,
2229 .slave = &dra7xx_i2c3_hwmod,
2230 .clk = "l3_iclk_div",
2231 .user = OCP_USER_MPU | OCP_USER_SDMA,
2232};
2233
2234/* l4_per1 -> i2c4 */
2235static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2236 .master = &dra7xx_l4_per1_hwmod,
2237 .slave = &dra7xx_i2c4_hwmod,
2238 .clk = "l3_iclk_div",
2239 .user = OCP_USER_MPU | OCP_USER_SDMA,
2240};
2241
2242/* l4_per1 -> i2c5 */
2243static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2244 .master = &dra7xx_l4_per1_hwmod,
2245 .slave = &dra7xx_i2c5_hwmod,
2246 .clk = "l3_iclk_div",
2247 .user = OCP_USER_MPU | OCP_USER_SDMA,
2248};
2249
2250/* l4_per1 -> mcspi1 */
2251static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2252 .master = &dra7xx_l4_per1_hwmod,
2253 .slave = &dra7xx_mcspi1_hwmod,
2254 .clk = "l3_iclk_div",
2255 .user = OCP_USER_MPU | OCP_USER_SDMA,
2256};
2257
2258/* l4_per1 -> mcspi2 */
2259static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2260 .master = &dra7xx_l4_per1_hwmod,
2261 .slave = &dra7xx_mcspi2_hwmod,
2262 .clk = "l3_iclk_div",
2263 .user = OCP_USER_MPU | OCP_USER_SDMA,
2264};
2265
2266/* l4_per1 -> mcspi3 */
2267static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2268 .master = &dra7xx_l4_per1_hwmod,
2269 .slave = &dra7xx_mcspi3_hwmod,
2270 .clk = "l3_iclk_div",
2271 .user = OCP_USER_MPU | OCP_USER_SDMA,
2272};
2273
2274/* l4_per1 -> mcspi4 */
2275static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2276 .master = &dra7xx_l4_per1_hwmod,
2277 .slave = &dra7xx_mcspi4_hwmod,
2278 .clk = "l3_iclk_div",
2279 .user = OCP_USER_MPU | OCP_USER_SDMA,
2280};
2281
2282/* l4_per1 -> mmc1 */
2283static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2284 .master = &dra7xx_l4_per1_hwmod,
2285 .slave = &dra7xx_mmc1_hwmod,
2286 .clk = "l3_iclk_div",
2287 .user = OCP_USER_MPU | OCP_USER_SDMA,
2288};
2289
2290/* l4_per1 -> mmc2 */
2291static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2292 .master = &dra7xx_l4_per1_hwmod,
2293 .slave = &dra7xx_mmc2_hwmod,
2294 .clk = "l3_iclk_div",
2295 .user = OCP_USER_MPU | OCP_USER_SDMA,
2296};
2297
2298/* l4_per1 -> mmc3 */
2299static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2300 .master = &dra7xx_l4_per1_hwmod,
2301 .slave = &dra7xx_mmc3_hwmod,
2302 .clk = "l3_iclk_div",
2303 .user = OCP_USER_MPU | OCP_USER_SDMA,
2304};
2305
2306/* l4_per1 -> mmc4 */
2307static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2308 .master = &dra7xx_l4_per1_hwmod,
2309 .slave = &dra7xx_mmc4_hwmod,
2310 .clk = "l3_iclk_div",
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312};
2313
2314/* l4_cfg -> mpu */
2315static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2316 .master = &dra7xx_l4_cfg_hwmod,
2317 .slave = &dra7xx_mpu_hwmod,
2318 .clk = "l3_iclk_div",
2319 .user = OCP_USER_MPU | OCP_USER_SDMA,
2320};
2321
2322static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
2323 {
2324 .pa_start = 0x4a080000,
2325 .pa_end = 0x4a08001f,
2326 .flags = ADDR_TYPE_RT
2327 },
2328 { }
2329};
2330
2331/* l4_cfg -> ocp2scp1 */
2332static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2333 .master = &dra7xx_l4_cfg_hwmod,
2334 .slave = &dra7xx_ocp2scp1_hwmod,
2335 .clk = "l4_root_clk_div",
2336 .addr = dra7xx_ocp2scp1_addrs,
2337 .user = OCP_USER_MPU | OCP_USER_SDMA,
2338};
2339
2340static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2341 {
2342 .pa_start = 0x4b300000,
2343 .pa_end = 0x4b30007f,
2344 .flags = ADDR_TYPE_RT
2345 },
2346 { }
2347};
2348
2349/* l3_main_1 -> qspi */
2350static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2351 .master = &dra7xx_l3_main_1_hwmod,
2352 .slave = &dra7xx_qspi_hwmod,
2353 .clk = "l3_iclk_div",
2354 .addr = dra7xx_qspi_addrs,
2355 .user = OCP_USER_MPU | OCP_USER_SDMA,
2356};
2357
2358static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2359 {
2360 .name = "sysc",
2361 .pa_start = 0x4a141100,
2362 .pa_end = 0x4a141107,
2363 .flags = ADDR_TYPE_RT
2364 },
2365 { }
2366};
2367
2368/* l4_cfg -> sata */
2369static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2370 .master = &dra7xx_l4_cfg_hwmod,
2371 .slave = &dra7xx_sata_hwmod,
2372 .clk = "l3_iclk_div",
2373 .addr = dra7xx_sata_addrs,
2374 .user = OCP_USER_MPU | OCP_USER_SDMA,
2375};
2376
2377static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2378 {
2379 .pa_start = 0x4a0dd000,
2380 .pa_end = 0x4a0dd07f,
2381 .flags = ADDR_TYPE_RT
2382 },
2383 { }
2384};
2385
2386/* l4_cfg -> smartreflex_core */
2387static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2388 .master = &dra7xx_l4_cfg_hwmod,
2389 .slave = &dra7xx_smartreflex_core_hwmod,
2390 .clk = "l4_root_clk_div",
2391 .addr = dra7xx_smartreflex_core_addrs,
2392 .user = OCP_USER_MPU | OCP_USER_SDMA,
2393};
2394
2395static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2396 {
2397 .pa_start = 0x4a0d9000,
2398 .pa_end = 0x4a0d907f,
2399 .flags = ADDR_TYPE_RT
2400 },
2401 { }
2402};
2403
2404/* l4_cfg -> smartreflex_mpu */
2405static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2406 .master = &dra7xx_l4_cfg_hwmod,
2407 .slave = &dra7xx_smartreflex_mpu_hwmod,
2408 .clk = "l4_root_clk_div",
2409 .addr = dra7xx_smartreflex_mpu_addrs,
2410 .user = OCP_USER_MPU | OCP_USER_SDMA,
2411};
2412
2413static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2414 {
2415 .pa_start = 0x4a0f6000,
2416 .pa_end = 0x4a0f6fff,
2417 .flags = ADDR_TYPE_RT
2418 },
2419 { }
2420};
2421
2422/* l4_cfg -> spinlock */
2423static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2424 .master = &dra7xx_l4_cfg_hwmod,
2425 .slave = &dra7xx_spinlock_hwmod,
2426 .clk = "l3_iclk_div",
2427 .addr = dra7xx_spinlock_addrs,
2428 .user = OCP_USER_MPU | OCP_USER_SDMA,
2429};
2430
2431/* l4_wkup -> timer1 */
2432static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2433 .master = &dra7xx_l4_wkup_hwmod,
2434 .slave = &dra7xx_timer1_hwmod,
2435 .clk = "wkupaon_iclk_mux",
2436 .user = OCP_USER_MPU | OCP_USER_SDMA,
2437};
2438
2439/* l4_per1 -> timer2 */
2440static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2441 .master = &dra7xx_l4_per1_hwmod,
2442 .slave = &dra7xx_timer2_hwmod,
2443 .clk = "l3_iclk_div",
2444 .user = OCP_USER_MPU | OCP_USER_SDMA,
2445};
2446
2447/* l4_per1 -> timer3 */
2448static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2449 .master = &dra7xx_l4_per1_hwmod,
2450 .slave = &dra7xx_timer3_hwmod,
2451 .clk = "l3_iclk_div",
2452 .user = OCP_USER_MPU | OCP_USER_SDMA,
2453};
2454
2455/* l4_per1 -> timer4 */
2456static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2457 .master = &dra7xx_l4_per1_hwmod,
2458 .slave = &dra7xx_timer4_hwmod,
2459 .clk = "l3_iclk_div",
2460 .user = OCP_USER_MPU | OCP_USER_SDMA,
2461};
2462
2463/* l4_per3 -> timer5 */
2464static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2465 .master = &dra7xx_l4_per3_hwmod,
2466 .slave = &dra7xx_timer5_hwmod,
2467 .clk = "l3_iclk_div",
2468 .user = OCP_USER_MPU | OCP_USER_SDMA,
2469};
2470
2471/* l4_per3 -> timer6 */
2472static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2473 .master = &dra7xx_l4_per3_hwmod,
2474 .slave = &dra7xx_timer6_hwmod,
2475 .clk = "l3_iclk_div",
2476 .user = OCP_USER_MPU | OCP_USER_SDMA,
2477};
2478
2479/* l4_per3 -> timer7 */
2480static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2481 .master = &dra7xx_l4_per3_hwmod,
2482 .slave = &dra7xx_timer7_hwmod,
2483 .clk = "l3_iclk_div",
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2485};
2486
2487/* l4_per3 -> timer8 */
2488static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2489 .master = &dra7xx_l4_per3_hwmod,
2490 .slave = &dra7xx_timer8_hwmod,
2491 .clk = "l3_iclk_div",
2492 .user = OCP_USER_MPU | OCP_USER_SDMA,
2493};
2494
2495/* l4_per1 -> timer9 */
2496static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2497 .master = &dra7xx_l4_per1_hwmod,
2498 .slave = &dra7xx_timer9_hwmod,
2499 .clk = "l3_iclk_div",
2500 .user = OCP_USER_MPU | OCP_USER_SDMA,
2501};
2502
2503/* l4_per1 -> timer10 */
2504static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2505 .master = &dra7xx_l4_per1_hwmod,
2506 .slave = &dra7xx_timer10_hwmod,
2507 .clk = "l3_iclk_div",
2508 .user = OCP_USER_MPU | OCP_USER_SDMA,
2509};
2510
2511/* l4_per1 -> timer11 */
2512static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2513 .master = &dra7xx_l4_per1_hwmod,
2514 .slave = &dra7xx_timer11_hwmod,
2515 .clk = "l3_iclk_div",
2516 .user = OCP_USER_MPU | OCP_USER_SDMA,
2517};
2518
2519/* l4_per1 -> uart1 */
2520static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2521 .master = &dra7xx_l4_per1_hwmod,
2522 .slave = &dra7xx_uart1_hwmod,
2523 .clk = "l3_iclk_div",
2524 .user = OCP_USER_MPU | OCP_USER_SDMA,
2525};
2526
2527/* l4_per1 -> uart2 */
2528static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2529 .master = &dra7xx_l4_per1_hwmod,
2530 .slave = &dra7xx_uart2_hwmod,
2531 .clk = "l3_iclk_div",
2532 .user = OCP_USER_MPU | OCP_USER_SDMA,
2533};
2534
2535/* l4_per1 -> uart3 */
2536static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2537 .master = &dra7xx_l4_per1_hwmod,
2538 .slave = &dra7xx_uart3_hwmod,
2539 .clk = "l3_iclk_div",
2540 .user = OCP_USER_MPU | OCP_USER_SDMA,
2541};
2542
2543/* l4_per1 -> uart4 */
2544static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2545 .master = &dra7xx_l4_per1_hwmod,
2546 .slave = &dra7xx_uart4_hwmod,
2547 .clk = "l3_iclk_div",
2548 .user = OCP_USER_MPU | OCP_USER_SDMA,
2549};
2550
2551/* l4_per1 -> uart5 */
2552static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2553 .master = &dra7xx_l4_per1_hwmod,
2554 .slave = &dra7xx_uart5_hwmod,
2555 .clk = "l3_iclk_div",
2556 .user = OCP_USER_MPU | OCP_USER_SDMA,
2557};
2558
2559/* l4_per1 -> uart6 */
2560static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2561 .master = &dra7xx_l4_per1_hwmod,
2562 .slave = &dra7xx_uart6_hwmod,
2563 .clk = "l3_iclk_div",
2564 .user = OCP_USER_MPU | OCP_USER_SDMA,
2565};
2566
2567/* l4_per3 -> usb_otg_ss1 */
2568static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2569 .master = &dra7xx_l4_per3_hwmod,
2570 .slave = &dra7xx_usb_otg_ss1_hwmod,
2571 .clk = "dpll_core_h13x2_ck",
2572 .user = OCP_USER_MPU | OCP_USER_SDMA,
2573};
2574
2575/* l4_per3 -> usb_otg_ss2 */
2576static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2577 .master = &dra7xx_l4_per3_hwmod,
2578 .slave = &dra7xx_usb_otg_ss2_hwmod,
2579 .clk = "dpll_core_h13x2_ck",
2580 .user = OCP_USER_MPU | OCP_USER_SDMA,
2581};
2582
2583/* l4_per3 -> usb_otg_ss3 */
2584static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2585 .master = &dra7xx_l4_per3_hwmod,
2586 .slave = &dra7xx_usb_otg_ss3_hwmod,
2587 .clk = "dpll_core_h13x2_ck",
2588 .user = OCP_USER_MPU | OCP_USER_SDMA,
2589};
2590
2591/* l4_per3 -> usb_otg_ss4 */
2592static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2593 .master = &dra7xx_l4_per3_hwmod,
2594 .slave = &dra7xx_usb_otg_ss4_hwmod,
2595 .clk = "dpll_core_h13x2_ck",
2596 .user = OCP_USER_MPU | OCP_USER_SDMA,
2597};
2598
2599/* l3_main_1 -> vcp1 */
2600static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2601 .master = &dra7xx_l3_main_1_hwmod,
2602 .slave = &dra7xx_vcp1_hwmod,
2603 .clk = "l3_iclk_div",
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2605};
2606
2607/* l4_per2 -> vcp1 */
2608static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2609 .master = &dra7xx_l4_per2_hwmod,
2610 .slave = &dra7xx_vcp1_hwmod,
2611 .clk = "l3_iclk_div",
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613};
2614
2615/* l3_main_1 -> vcp2 */
2616static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2617 .master = &dra7xx_l3_main_1_hwmod,
2618 .slave = &dra7xx_vcp2_hwmod,
2619 .clk = "l3_iclk_div",
2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
2621};
2622
2623/* l4_per2 -> vcp2 */
2624static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2625 .master = &dra7xx_l4_per2_hwmod,
2626 .slave = &dra7xx_vcp2_hwmod,
2627 .clk = "l3_iclk_div",
2628 .user = OCP_USER_MPU | OCP_USER_SDMA,
2629};
2630
2631/* l4_wkup -> wd_timer2 */
2632static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2633 .master = &dra7xx_l4_wkup_hwmod,
2634 .slave = &dra7xx_wd_timer2_hwmod,
2635 .clk = "wkupaon_iclk_mux",
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2637};
2638
2639static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2640 &dra7xx_l3_main_2__l3_instr,
2641 &dra7xx_l4_cfg__l3_main_1,
2642 &dra7xx_mpu__l3_main_1,
2643 &dra7xx_l3_main_1__l3_main_2,
2644 &dra7xx_l4_cfg__l3_main_2,
2645 &dra7xx_l3_main_1__l4_cfg,
2646 &dra7xx_l3_main_1__l4_per1,
2647 &dra7xx_l3_main_1__l4_per2,
2648 &dra7xx_l3_main_1__l4_per3,
2649 &dra7xx_l3_main_1__l4_wkup,
2650 &dra7xx_l4_per2__atl,
2651 &dra7xx_l3_main_1__bb2d,
2652 &dra7xx_l4_wkup__counter_32k,
2653 &dra7xx_l4_wkup__ctrl_module_wkup,
2654 &dra7xx_l4_wkup__dcan1,
2655 &dra7xx_l4_per2__dcan2,
2656 &dra7xx_l4_cfg__dma_system,
2657 &dra7xx_l3_main_1__dss,
2658 &dra7xx_l3_main_1__dispc,
2659 &dra7xx_l3_main_1__hdmi,
2660 &dra7xx_l4_per1__elm,
2661 &dra7xx_l4_wkup__gpio1,
2662 &dra7xx_l4_per1__gpio2,
2663 &dra7xx_l4_per1__gpio3,
2664 &dra7xx_l4_per1__gpio4,
2665 &dra7xx_l4_per1__gpio5,
2666 &dra7xx_l4_per1__gpio6,
2667 &dra7xx_l4_per1__gpio7,
2668 &dra7xx_l4_per1__gpio8,
2669 &dra7xx_l3_main_1__gpmc,
2670 &dra7xx_l4_per1__hdq1w,
2671 &dra7xx_l4_per1__i2c1,
2672 &dra7xx_l4_per1__i2c2,
2673 &dra7xx_l4_per1__i2c3,
2674 &dra7xx_l4_per1__i2c4,
2675 &dra7xx_l4_per1__i2c5,
2676 &dra7xx_l4_per1__mcspi1,
2677 &dra7xx_l4_per1__mcspi2,
2678 &dra7xx_l4_per1__mcspi3,
2679 &dra7xx_l4_per1__mcspi4,
2680 &dra7xx_l4_per1__mmc1,
2681 &dra7xx_l4_per1__mmc2,
2682 &dra7xx_l4_per1__mmc3,
2683 &dra7xx_l4_per1__mmc4,
2684 &dra7xx_l4_cfg__mpu,
2685 &dra7xx_l4_cfg__ocp2scp1,
2686 &dra7xx_l3_main_1__qspi,
2687 &dra7xx_l4_cfg__sata,
2688 &dra7xx_l4_cfg__smartreflex_core,
2689 &dra7xx_l4_cfg__smartreflex_mpu,
2690 &dra7xx_l4_cfg__spinlock,
2691 &dra7xx_l4_wkup__timer1,
2692 &dra7xx_l4_per1__timer2,
2693 &dra7xx_l4_per1__timer3,
2694 &dra7xx_l4_per1__timer4,
2695 &dra7xx_l4_per3__timer5,
2696 &dra7xx_l4_per3__timer6,
2697 &dra7xx_l4_per3__timer7,
2698 &dra7xx_l4_per3__timer8,
2699 &dra7xx_l4_per1__timer9,
2700 &dra7xx_l4_per1__timer10,
2701 &dra7xx_l4_per1__timer11,
2702 &dra7xx_l4_per1__uart1,
2703 &dra7xx_l4_per1__uart2,
2704 &dra7xx_l4_per1__uart3,
2705 &dra7xx_l4_per1__uart4,
2706 &dra7xx_l4_per1__uart5,
2707 &dra7xx_l4_per1__uart6,
2708 &dra7xx_l4_per3__usb_otg_ss1,
2709 &dra7xx_l4_per3__usb_otg_ss2,
2710 &dra7xx_l4_per3__usb_otg_ss3,
2711 &dra7xx_l4_per3__usb_otg_ss4,
2712 &dra7xx_l3_main_1__vcp1,
2713 &dra7xx_l4_per2__vcp1,
2714 &dra7xx_l3_main_1__vcp2,
2715 &dra7xx_l4_per2__vcp2,
2716 &dra7xx_l4_wkup__wd_timer2,
2717 NULL,
2718};
2719
2720int __init dra7xx_hwmod_init(void)
2721{
2722 omap_hwmod_init();
2723 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
2724}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index e4d7bd6f94b8..baf3d8bf6bea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -256,6 +256,7 @@ extern void omap3xxx_powerdomains_init(void);
256extern void am33xx_powerdomains_init(void); 256extern void am33xx_powerdomains_init(void);
257extern void omap44xx_powerdomains_init(void); 257extern void omap44xx_powerdomains_init(void);
258extern void omap54xx_powerdomains_init(void); 258extern void omap54xx_powerdomains_init(void);
259extern void dra7xx_powerdomains_init(void);
259 260
260extern struct pwrdm_ops omap2_pwrdm_operations; 261extern struct pwrdm_ops omap2_pwrdm_operations;
261extern struct pwrdm_ops omap3_pwrdm_operations; 262extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
new file mode 100644
index 000000000000..48151d1cfde0
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -0,0 +1,454 @@
1/*
2 * DRA7xx Power domains framework
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Generated by code originally written by:
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25
26#include "powerdomain.h"
27
28#include "prcm-common.h"
29#include "prcm44xx.h"
30#include "prm7xx.h"
31#include "prcm_mpu7xx.h"
32
33/* iva_7xx_pwrdm: IVA-HD power domain */
34static struct powerdomain iva_7xx_pwrdm = {
35 .name = "iva_pwrdm",
36 .prcm_offs = DRA7XX_PRM_IVA_INST,
37 .prcm_partition = DRA7XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_OFF_RET_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF,
40 .banks = 4,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* hwa_mem */
43 [1] = PWRSTS_OFF_RET, /* sl2_mem */
44 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
46 },
47 .pwrsts_mem_on = {
48 [0] = PWRSTS_OFF_RET, /* hwa_mem */
49 [1] = PWRSTS_OFF_RET, /* sl2_mem */
50 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
51 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
52 },
53 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
54};
55
56/* rtc_7xx_pwrdm: */
57static struct powerdomain rtc_7xx_pwrdm = {
58 .name = "rtc_pwrdm",
59 .prcm_offs = DRA7XX_PRM_RTC_INST,
60 .prcm_partition = DRA7XX_PRM_PARTITION,
61 .pwrsts = PWRSTS_ON,
62};
63
64/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
65static struct powerdomain custefuse_7xx_pwrdm = {
66 .name = "custefuse_pwrdm",
67 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
68 .prcm_partition = DRA7XX_PRM_PARTITION,
69 .pwrsts = PWRSTS_OFF_ON,
70 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
71};
72
73/* ipu_7xx_pwrdm: Audio back end power domain */
74static struct powerdomain ipu_7xx_pwrdm = {
75 .name = "ipu_pwrdm",
76 .prcm_offs = DRA7XX_PRM_IPU_INST,
77 .prcm_partition = DRA7XX_PRM_PARTITION,
78 .pwrsts = PWRSTS_OFF_RET_ON,
79 .pwrsts_logic_ret = PWRSTS_OFF,
80 .banks = 2,
81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_OFF_RET, /* aessmem */
83 [1] = PWRSTS_OFF_RET, /* periphmem */
84 },
85 .pwrsts_mem_on = {
86 [0] = PWRSTS_OFF_RET, /* aessmem */
87 [1] = PWRSTS_OFF_RET, /* periphmem */
88 },
89 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
90};
91
92/* dss_7xx_pwrdm: Display subsystem power domain */
93static struct powerdomain dss_7xx_pwrdm = {
94 .name = "dss_pwrdm",
95 .prcm_offs = DRA7XX_PRM_DSS_INST,
96 .prcm_partition = DRA7XX_PRM_PARTITION,
97 .pwrsts = PWRSTS_OFF_RET_ON,
98 .pwrsts_logic_ret = PWRSTS_OFF,
99 .banks = 1,
100 .pwrsts_mem_ret = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */
102 },
103 .pwrsts_mem_on = {
104 [0] = PWRSTS_OFF_RET, /* dss_mem */
105 },
106 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
107};
108
109/* l4per_7xx_pwrdm: Target peripherals power domain */
110static struct powerdomain l4per_7xx_pwrdm = {
111 .name = "l4per_pwrdm",
112 .prcm_offs = DRA7XX_PRM_L4PER_INST,
113 .prcm_partition = DRA7XX_PRM_PARTITION,
114 .pwrsts = PWRSTS_RET_ON,
115 .pwrsts_logic_ret = PWRSTS_OFF_RET,
116 .banks = 2,
117 .pwrsts_mem_ret = {
118 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
119 [1] = PWRSTS_OFF_RET, /* retained_bank */
120 },
121 .pwrsts_mem_on = {
122 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
123 [1] = PWRSTS_OFF_RET, /* retained_bank */
124 },
125 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
126};
127
128/* gpu_7xx_pwrdm: 3D accelerator power domain */
129static struct powerdomain gpu_7xx_pwrdm = {
130 .name = "gpu_pwrdm",
131 .prcm_offs = DRA7XX_PRM_GPU_INST,
132 .prcm_partition = DRA7XX_PRM_PARTITION,
133 .pwrsts = PWRSTS_OFF_ON,
134 .banks = 1,
135 .pwrsts_mem_ret = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */
137 },
138 .pwrsts_mem_on = {
139 [0] = PWRSTS_OFF_RET, /* gpu_mem */
140 },
141 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
142};
143
144/* wkupaon_7xx_pwrdm: Wake-up power domain */
145static struct powerdomain wkupaon_7xx_pwrdm = {
146 .name = "wkupaon_pwrdm",
147 .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
148 .prcm_partition = DRA7XX_PRM_PARTITION,
149 .pwrsts = PWRSTS_ON,
150 .banks = 1,
151 .pwrsts_mem_ret = {
152 },
153 .pwrsts_mem_on = {
154 [0] = PWRSTS_ON, /* wkup_bank */
155 },
156};
157
158/* core_7xx_pwrdm: CORE power domain */
159static struct powerdomain core_7xx_pwrdm = {
160 .name = "core_pwrdm",
161 .prcm_offs = DRA7XX_PRM_CORE_INST,
162 .prcm_partition = DRA7XX_PRM_PARTITION,
163 .pwrsts = PWRSTS_RET_ON,
164 .pwrsts_logic_ret = PWRSTS_OFF_RET,
165 .banks = 5,
166 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
168 [1] = PWRSTS_OFF_RET, /* core_ocmram */
169 [2] = PWRSTS_OFF_RET, /* core_other_bank */
170 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
172 },
173 .pwrsts_mem_on = {
174 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
175 [1] = PWRSTS_OFF_RET, /* core_ocmram */
176 [2] = PWRSTS_OFF_RET, /* core_other_bank */
177 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
178 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
179 },
180 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
181};
182
183/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
184static struct powerdomain coreaon_7xx_pwrdm = {
185 .name = "coreaon_pwrdm",
186 .prcm_offs = DRA7XX_PRM_COREAON_INST,
187 .prcm_partition = DRA7XX_PRM_PARTITION,
188 .pwrsts = PWRSTS_ON,
189};
190
191/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
192static struct powerdomain cpu0_7xx_pwrdm = {
193 .name = "cpu0_pwrdm",
194 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
195 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
196 .pwrsts = PWRSTS_OFF_RET_ON,
197 .pwrsts_logic_ret = PWRSTS_OFF_RET,
198 .banks = 1,
199 .pwrsts_mem_ret = {
200 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
201 },
202 .pwrsts_mem_on = {
203 [0] = PWRSTS_ON, /* cpu0_l1 */
204 },
205};
206
207/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
208static struct powerdomain cpu1_7xx_pwrdm = {
209 .name = "cpu1_pwrdm",
210 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
211 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
212 .pwrsts = PWRSTS_OFF_RET_ON,
213 .pwrsts_logic_ret = PWRSTS_OFF_RET,
214 .banks = 1,
215 .pwrsts_mem_ret = {
216 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
217 },
218 .pwrsts_mem_on = {
219 [0] = PWRSTS_ON, /* cpu1_l1 */
220 },
221};
222
223/* vpe_7xx_pwrdm: */
224static struct powerdomain vpe_7xx_pwrdm = {
225 .name = "vpe_pwrdm",
226 .prcm_offs = DRA7XX_PRM_VPE_INST,
227 .prcm_partition = DRA7XX_PRM_PARTITION,
228 .pwrsts = PWRSTS_OFF_RET_ON,
229 .pwrsts_logic_ret = PWRSTS_OFF_RET,
230 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */
233 },
234 .pwrsts_mem_on = {
235 [0] = PWRSTS_OFF_RET, /* vpe_bank */
236 },
237 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
238};
239
240/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
241static struct powerdomain mpu_7xx_pwrdm = {
242 .name = "mpu_pwrdm",
243 .prcm_offs = DRA7XX_PRM_MPU_INST,
244 .prcm_partition = DRA7XX_PRM_PARTITION,
245 .pwrsts = PWRSTS_RET_ON,
246 .pwrsts_logic_ret = PWRSTS_OFF_RET,
247 .banks = 2,
248 .pwrsts_mem_ret = {
249 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
250 [1] = PWRSTS_RET, /* mpu_ram */
251 },
252 .pwrsts_mem_on = {
253 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
254 [1] = PWRSTS_OFF_RET, /* mpu_ram */
255 },
256};
257
258/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
259static struct powerdomain l3init_7xx_pwrdm = {
260 .name = "l3init_pwrdm",
261 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
262 .prcm_partition = DRA7XX_PRM_PARTITION,
263 .pwrsts = PWRSTS_RET_ON,
264 .pwrsts_logic_ret = PWRSTS_OFF_RET,
265 .banks = 3,
266 .pwrsts_mem_ret = {
267 [0] = PWRSTS_OFF_RET, /* gmac_bank */
268 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
270 },
271 .pwrsts_mem_on = {
272 [0] = PWRSTS_OFF_RET, /* gmac_bank */
273 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
274 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
275 },
276 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
277};
278
279/* eve3_7xx_pwrdm: */
280static struct powerdomain eve3_7xx_pwrdm = {
281 .name = "eve3_pwrdm",
282 .prcm_offs = DRA7XX_PRM_EVE3_INST,
283 .prcm_partition = DRA7XX_PRM_PARTITION,
284 .pwrsts = PWRSTS_OFF_ON,
285 .banks = 1,
286 .pwrsts_mem_ret = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */
288 },
289 .pwrsts_mem_on = {
290 [0] = PWRSTS_OFF_RET, /* eve3_bank */
291 },
292 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
293};
294
295/* emu_7xx_pwrdm: Emulation power domain */
296static struct powerdomain emu_7xx_pwrdm = {
297 .name = "emu_pwrdm",
298 .prcm_offs = DRA7XX_PRM_EMU_INST,
299 .prcm_partition = DRA7XX_PRM_PARTITION,
300 .pwrsts = PWRSTS_OFF_ON,
301 .banks = 1,
302 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */
304 },
305 .pwrsts_mem_on = {
306 [0] = PWRSTS_OFF_RET, /* emu_bank */
307 },
308};
309
310/* dsp2_7xx_pwrdm: */
311static struct powerdomain dsp2_7xx_pwrdm = {
312 .name = "dsp2_pwrdm",
313 .prcm_offs = DRA7XX_PRM_DSP2_INST,
314 .prcm_partition = DRA7XX_PRM_PARTITION,
315 .pwrsts = PWRSTS_OFF_ON,
316 .banks = 3,
317 .pwrsts_mem_ret = {
318 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
319 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
321 },
322 .pwrsts_mem_on = {
323 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
324 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
325 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
326 },
327 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
328};
329
330/* dsp1_7xx_pwrdm: Tesla processor power domain */
331static struct powerdomain dsp1_7xx_pwrdm = {
332 .name = "dsp1_pwrdm",
333 .prcm_offs = DRA7XX_PRM_DSP1_INST,
334 .prcm_partition = DRA7XX_PRM_PARTITION,
335 .pwrsts = PWRSTS_OFF_ON,
336 .banks = 3,
337 .pwrsts_mem_ret = {
338 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
339 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
341 },
342 .pwrsts_mem_on = {
343 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
344 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
345 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
346 },
347 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
348};
349
350/* cam_7xx_pwrdm: Camera subsystem power domain */
351static struct powerdomain cam_7xx_pwrdm = {
352 .name = "cam_pwrdm",
353 .prcm_offs = DRA7XX_PRM_CAM_INST,
354 .prcm_partition = DRA7XX_PRM_PARTITION,
355 .pwrsts = PWRSTS_OFF_ON,
356 .banks = 1,
357 .pwrsts_mem_ret = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */
359 },
360 .pwrsts_mem_on = {
361 [0] = PWRSTS_OFF_RET, /* vip_bank */
362 },
363 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
364};
365
366/* eve4_7xx_pwrdm: */
367static struct powerdomain eve4_7xx_pwrdm = {
368 .name = "eve4_pwrdm",
369 .prcm_offs = DRA7XX_PRM_EVE4_INST,
370 .prcm_partition = DRA7XX_PRM_PARTITION,
371 .pwrsts = PWRSTS_OFF_ON,
372 .banks = 1,
373 .pwrsts_mem_ret = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */
375 },
376 .pwrsts_mem_on = {
377 [0] = PWRSTS_OFF_RET, /* eve4_bank */
378 },
379 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
380};
381
382/* eve2_7xx_pwrdm: */
383static struct powerdomain eve2_7xx_pwrdm = {
384 .name = "eve2_pwrdm",
385 .prcm_offs = DRA7XX_PRM_EVE2_INST,
386 .prcm_partition = DRA7XX_PRM_PARTITION,
387 .pwrsts = PWRSTS_OFF_ON,
388 .banks = 1,
389 .pwrsts_mem_ret = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */
391 },
392 .pwrsts_mem_on = {
393 [0] = PWRSTS_OFF_RET, /* eve2_bank */
394 },
395 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
396};
397
398/* eve1_7xx_pwrdm: */
399static struct powerdomain eve1_7xx_pwrdm = {
400 .name = "eve1_pwrdm",
401 .prcm_offs = DRA7XX_PRM_EVE1_INST,
402 .prcm_partition = DRA7XX_PRM_PARTITION,
403 .pwrsts = PWRSTS_OFF_ON,
404 .banks = 1,
405 .pwrsts_mem_ret = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */
407 },
408 .pwrsts_mem_on = {
409 [0] = PWRSTS_OFF_RET, /* eve1_bank */
410 },
411 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
412};
413
414/*
415 * The following power domains are not under SW control
416 *
417 * mpuaon
418 * mmaon
419 */
420
421/* As powerdomains are added or removed above, this list must also be changed */
422static struct powerdomain *powerdomains_dra7xx[] __initdata = {
423 &iva_7xx_pwrdm,
424 &rtc_7xx_pwrdm,
425 &custefuse_7xx_pwrdm,
426 &ipu_7xx_pwrdm,
427 &dss_7xx_pwrdm,
428 &l4per_7xx_pwrdm,
429 &gpu_7xx_pwrdm,
430 &wkupaon_7xx_pwrdm,
431 &core_7xx_pwrdm,
432 &coreaon_7xx_pwrdm,
433 &cpu0_7xx_pwrdm,
434 &cpu1_7xx_pwrdm,
435 &vpe_7xx_pwrdm,
436 &mpu_7xx_pwrdm,
437 &l3init_7xx_pwrdm,
438 &eve3_7xx_pwrdm,
439 &emu_7xx_pwrdm,
440 &dsp2_7xx_pwrdm,
441 &dsp1_7xx_pwrdm,
442 &cam_7xx_pwrdm,
443 &eve4_7xx_pwrdm,
444 &eve2_7xx_pwrdm,
445 &eve1_7xx_pwrdm,
446 NULL
447};
448
449void __init dra7xx_powerdomains_init(void)
450{
451 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
452 pwrdm_register_pwrdms(powerdomains_dra7xx);
453 pwrdm_complete_init();
454}
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index f429cdd5a118..4fea2cfdf2c3 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -38,6 +38,11 @@
38#define OMAP54XX_SCRM_PARTITION 4 38#define OMAP54XX_SCRM_PARTITION 4
39#define OMAP54XX_PRCM_MPU_PARTITION 5 39#define OMAP54XX_PRCM_MPU_PARTITION 5
40 40
41#define DRA7XX_PRM_PARTITION 1
42#define DRA7XX_CM_CORE_AON_PARTITION 2
43#define DRA7XX_CM_CORE_PARTITION 3
44#define DRA7XX_MPU_PRCM_PARTITION 5
45
41/* 46/*
42 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition 47 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
43 * IDs, plus one 48 * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h
new file mode 100644
index 000000000000..9ebb5ce0878f
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu7xx.h
@@ -0,0 +1,78 @@
1/*
2 * DRA7xx PRCM MPU instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
24
25#include "prcm_mpu_44xx_54xx.h"
26
27#define DRA7XX_PRCM_MPU_BASE 0x48243000
28
29#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
31
32/* MPU_PRCM instances */
33#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
34#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
35#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
36#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
37#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
38#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
39
40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
42#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
43
44
45/* MPU_PRCM */
46
47/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
48#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
49
50/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
51#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
52#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
53
54/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
55#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
56#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
57#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
58#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
59#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
60
61/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
62#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
63#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
64#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
65
66/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
67#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
68#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
69#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
70#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
71#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
72
73/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
74#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
75#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
76#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
77
78#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 415c7e0c9393..03a603476cfc 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -620,6 +620,15 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
620 return 0; 620 return 0;
621} 621}
622 622
623static int omap4_check_vcvp(void)
624{
625 /* No VC/VP on dra7xx devices */
626 if (soc_is_dra7xx())
627 return 0;
628
629 return 1;
630}
631
623struct pwrdm_ops omap4_pwrdm_operations = { 632struct pwrdm_ops omap4_pwrdm_operations = {
624 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, 633 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
625 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, 634 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
@@ -637,6 +646,7 @@ struct pwrdm_ops omap4_pwrdm_operations = {
637 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, 646 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
638 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, 647 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
639 .pwrdm_wait_transition = omap4_pwrdm_wait_transition, 648 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
649 .pwrdm_has_voltdm = omap4_check_vcvp,
640}; 650};
641 651
642/* 652/*
@@ -650,7 +660,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
650 660
651int __init omap44xx_prm_init(void) 661int __init omap44xx_prm_init(void)
652{ 662{
653 if (!cpu_is_omap44xx() && !soc_is_omap54xx()) 663 if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
654 return 0; 664 return 0;
655 665
656 return prm_register(&omap44xx_prm_ll_data); 666 return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
new file mode 100644
index 000000000000..d92a8404edc7
--- /dev/null
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -0,0 +1,678 @@
1/*
2 * DRA7xx PRM instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
24
25#include "prm44xx_54xx.h"
26#include "prcm-common.h"
27#include "prm.h"
28
29#define DRA7XX_PRM_BASE 0x4ae06000
30
31#define DRA7XX_PRM_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
33
34
35/* PRM instances */
36#define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
37#define DRA7XX_PRM_CKGEN_INST 0x0100
38#define DRA7XX_PRM_MPU_INST 0x0300
39#define DRA7XX_PRM_DSP1_INST 0x0400
40#define DRA7XX_PRM_IPU_INST 0x0500
41#define DRA7XX_PRM_COREAON_INST 0x0628
42#define DRA7XX_PRM_CORE_INST 0x0700
43#define DRA7XX_PRM_IVA_INST 0x0f00
44#define DRA7XX_PRM_CAM_INST 0x1000
45#define DRA7XX_PRM_DSS_INST 0x1100
46#define DRA7XX_PRM_GPU_INST 0x1200
47#define DRA7XX_PRM_L3INIT_INST 0x1300
48#define DRA7XX_PRM_L4PER_INST 0x1400
49#define DRA7XX_PRM_CUSTEFUSE_INST 0x1600
50#define DRA7XX_PRM_WKUPAON_INST 0x1724
51#define DRA7XX_PRM_WKUPAON_CM_INST 0x1800
52#define DRA7XX_PRM_EMU_INST 0x1900
53#define DRA7XX_PRM_EMU_CM_INST 0x1a00
54#define DRA7XX_PRM_DSP2_INST 0x1b00
55#define DRA7XX_PRM_EVE1_INST 0x1b40
56#define DRA7XX_PRM_EVE2_INST 0x1b80
57#define DRA7XX_PRM_EVE3_INST 0x1bc0
58#define DRA7XX_PRM_EVE4_INST 0x1c00
59#define DRA7XX_PRM_RTC_INST 0x1c60
60#define DRA7XX_PRM_VPE_INST 0x1c80
61#define DRA7XX_PRM_DEVICE_INST 0x1d00
62#define DRA7XX_PRM_INSTR_INST 0x1f00
63
64/* PRM clockdomain register offsets (from instance start) */
65#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
66#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
67
68/* PRM */
69
70/* PRM.OCP_SOCKET_PRM register offsets */
71#define DRA7XX_REVISION_PRM_OFFSET 0x0000
72#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
73#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
74#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
75#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
76#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020
77#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028
78#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030
79#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038
80#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
81#define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
82#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044
83#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048
84#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c
85#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050
86#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054
87#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058
88#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c
89#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060
90#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064
91#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068
92#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c
93#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070
94#define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4
95#define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8
96#define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec
97#define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4
98
99/* PRM.CKGEN_PRM register offsets */
100#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000
101#define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
102#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
103#define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
104#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
105#define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
106#define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010
107#define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
108#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014
109#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
110#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018
111#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
112#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c
113#define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
114#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020
115#define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
116#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024
117#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
118#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028
119#define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
120#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c
121#define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
122#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030
123#define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
124#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034
125#define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
126#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038
127#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
128#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040
129#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
130#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044
131#define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
132#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048
133#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
134#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c
135#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
136#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050
137#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
138#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054
139#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
140#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058
141#define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
142#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c
143#define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
144#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060
145#define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
146#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064
147#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
148#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068
149#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
150#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c
151#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
152#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070
153#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
154#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074
155#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
156#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078
157#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
158#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080
159#define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
160#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084
161#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
162#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088
163#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
164#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c
165#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
166#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090
167#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
168#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094
169#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
170#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098
171#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
172#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c
173#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
174#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0
175#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
176#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4
177#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
178#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8
179#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
180#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac
181#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
182#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0
183#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
184#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4
185#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
186#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8
187#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
188#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc
189#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
190#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0
191#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
192#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4
193#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
194#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8
195#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
196#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc
197#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
198#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0
199#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
200#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4
201#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
202#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8
203#define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
204#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc
205#define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
206#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0
207#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
208
209/* PRM.MPU_PRM register offsets */
210#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
211#define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004
212#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
213
214/* PRM.DSP1_PRM register offsets */
215#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000
216#define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004
217#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010
218#define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014
219#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024
220
221/* PRM.IPU_PRM register offsets */
222#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000
223#define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004
224#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010
225#define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014
226#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024
227#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050
228#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054
229#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058
230#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c
231#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060
232#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064
233#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068
234#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c
235#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070
236#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074
237#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078
238#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c
239#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080
240#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084
241
242/* PRM.COREAON_PRM register offsets */
243#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000
244#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004
245#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010
246#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014
247#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030
248#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034
249#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040
250#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044
251#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050
252#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054
253#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084
254#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094
255#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4
256#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4
257
258/* PRM.CORE_PRM register offsets */
259#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
260#define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004
261#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
262#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c
263#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034
264#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050
265#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054
266#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058
267#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c
268#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060
269#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064
270#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c
271#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070
272#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074
273#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078
274#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c
275#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080
276#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084
277#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c
278#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094
279#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c
280#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4
281#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac
282#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4
283#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc
284#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4
285#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc
286#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4
287#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc
288#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4
289#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc
290#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210
291#define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214
292#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224
293#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
294#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
295#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
296#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
297#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
298#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
299#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524
300#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
301#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
302#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634
303#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
304#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
305#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c
306#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654
307#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c
308#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664
309#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c
310#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674
311#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c
312#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684
313#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c
314#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694
315#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c
316#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4
317#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac
318#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4
319#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc
320#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4
321#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724
322#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
323#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
324
325/* PRM.IVA_PRM register offsets */
326#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
327#define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004
328#define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010
329#define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014
330#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
331#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
332
333/* PRM.CAM_PRM register offsets */
334#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
335#define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004
336#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020
337#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024
338#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028
339#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c
340#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030
341#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034
342#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c
343#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044
344#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c
345
346/* PRM.DSS_PRM register offsets */
347#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
348#define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004
349#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
350#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
351#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028
352#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
353#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c
354
355/* PRM.GPU_PRM register offsets */
356#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
357#define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004
358#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
359
360/* PRM.L3INIT_PRM register offsets */
361#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
362#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
363#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
364#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
365#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
366#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
367#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040
368#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044
369#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048
370#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c
371#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050
372#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054
373#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c
374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
377#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
378#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
379#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
380#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0
381#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4
382
383/* PRM.L4PER_PRM register offsets */
384#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
385#define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004
386#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c
387#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014
388#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c
389#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024
390#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028
391#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c
392#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030
393#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034
394#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038
395#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c
396#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040
397#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044
398#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048
399#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c
400#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050
401#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054
402#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
403#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
404#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
405#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
406#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
407#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
408#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
409#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
410#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
411#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
412#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
413#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
414#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094
415#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c
416#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
417#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
418#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
419#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
420#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
421#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
422#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
423#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
424#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0
425#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4
426#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8
427#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc
428#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0
429#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4
430#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8
431#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc
432#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
433#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
434#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
435#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
436#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
437#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
438#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
439#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
440#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110
441#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114
442#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118
443#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c
444#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120
445#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124
446#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128
447#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c
448#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130
449#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134
450#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138
451#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c
452#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
453#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
454#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
455#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
456#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
457#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
458#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
459#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
460#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160
461#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164
462#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168
463#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c
464#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170
465#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174
466#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178
467#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c
468#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180
469#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184
470#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188
471#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c
472#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190
473#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194
474#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198
475#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c
476#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
477#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
478#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
479#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc
480#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
481#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
482#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0
483#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4
484#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc
485#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0
486#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4
487#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8
488#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec
489#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0
490#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4
491#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc
492
493/* PRM.CUSTEFUSE_PRM register offsets */
494#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
495#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
496#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
497
498/* PRM.WKUPAON_PRM register offsets */
499#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000
500#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004
501#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008
502#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c
503#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010
504#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014
505#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018
506#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c
507#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020
508#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024
509#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028
510#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030
511#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040
512#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054
513#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058
514#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c
515#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060
516#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064
517#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068
518#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c
519#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080
520#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090
521#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098
522#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0
523#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8
524#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0
525#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8
526
527/* PRM.WKUPAON_CM register offsets */
528#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
529#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
530#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
531#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
532#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
533#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
534#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
535#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
536#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
537#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
538#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
539#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
540#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
541#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
542#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
543#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
544#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
545#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
546#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
547#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080
548#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
549#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088
550#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
551#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
552#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
553#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
554#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
555#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0
556#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
557#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0
558#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
559#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8
560#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
561#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0
562#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
563#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8
564#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
565#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0
566#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
567#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8
568#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
569
570/* PRM.EMU_PRM register offsets */
571#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
572#define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004
573#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
574
575/* PRM.EMU_CM register offsets */
576#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
577#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004
578#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
579#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
580#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c
581#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
582
583/* PRM.DSP2_PRM register offsets */
584#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000
585#define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004
586#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010
587#define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014
588#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024
589
590/* PRM.EVE1_PRM register offsets */
591#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000
592#define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004
593#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010
594#define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014
595#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020
596#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024
597
598/* PRM.EVE2_PRM register offsets */
599#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000
600#define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004
601#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010
602#define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014
603#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020
604#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024
605
606/* PRM.EVE3_PRM register offsets */
607#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000
608#define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004
609#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010
610#define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014
611#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020
612#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024
613
614/* PRM.EVE4_PRM register offsets */
615#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000
616#define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004
617#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010
618#define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014
619#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020
620#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024
621
622/* PRM.RTC_PRM register offsets */
623#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000
624#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004
625
626/* PRM.VPE_PRM register offsets */
627#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000
628#define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004
629#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020
630#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024
631
632/* PRM.DEVICE_PRM register offsets */
633#define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000
634#define DRA7XX_PRM_RSTST_OFFSET 0x0004
635#define DRA7XX_PRM_RSTTIME_OFFSET 0x0008
636#define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c
637#define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010
638#define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014
639#define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018
640#define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c
641#define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020
642#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
643#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
644#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
645#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
646#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
647#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
648#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
649#define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc
650#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
651#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
652#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
653#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
654#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
655#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4
656#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8
657#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
658#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
659#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4
660#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8
661#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
662#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
663#define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
664#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
665#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
666#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
667#define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110
668#define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114
669#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118
670#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c
671#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120
672#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124
673#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128
674#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c
675#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130
676#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134
677
678#endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index c12320c0ae95..6334b96b4097 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -20,10 +20,13 @@
20#include "common.h" 20#include "common.h"
21#include "prcm-common.h" 21#include "prcm-common.h"
22#include "prm44xx.h" 22#include "prm44xx.h"
23#include "prm54xx.h"
24#include "prm7xx.h"
23#include "prminst44xx.h" 25#include "prminst44xx.h"
24#include "prm-regbits-44xx.h" 26#include "prm-regbits-44xx.h"
25#include "prcm44xx.h" 27#include "prcm44xx.h"
26#include "prcm_mpu44xx.h" 28#include "prcm_mpu44xx.h"
29#include "soc.h"
27 30
28static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 31static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
29 32
@@ -165,10 +168,19 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
165void omap4_prminst_global_warm_sw_reset(void) 168void omap4_prminst_global_warm_sw_reset(void)
166{ 169{
167 u32 v; 170 u32 v;
168 171 s16 dev_inst;
169 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 172
170 OMAP4430_PRM_DEVICE_INST, 173 if (cpu_is_omap44xx())
171 OMAP4_PRM_RSTCTRL_OFFSET); 174 dev_inst = OMAP4430_PRM_DEVICE_INST;
175 else if (soc_is_omap54xx())
176 dev_inst = OMAP54XX_PRM_DEVICE_INST;
177 else if (soc_is_dra7xx())
178 dev_inst = DRA7XX_PRM_DEVICE_INST;
179 else
180 return;
181
182 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
183 OMAP4_PRM_RSTCTRL_OFFSET);
172 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; 184 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
173 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, 185 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
174 OMAP4430_PRM_DEVICE_INST, 186 OMAP4430_PRM_DEVICE_INST,
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 8c616e436bc7..4588df1447ed 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -8,6 +8,7 @@
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
10 * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> 10 * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
11 * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
11 * 12 *
12 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 14 * it under the terms of the GNU General Public License as published by
@@ -35,6 +36,7 @@
35#ifndef __ASSEMBLY__ 36#ifndef __ASSEMBLY__
36 37
37#include <linux/bitops.h> 38#include <linux/bitops.h>
39#include <linux/of.h>
38 40
39/* 41/*
40 * Test if multicore OMAP support is needed 42 * Test if multicore OMAP support is needed
@@ -105,6 +107,15 @@
105# endif 107# endif
106#endif 108#endif
107 109
110#ifdef CONFIG_SOC_DRA7XX
111# ifdef OMAP_NAME
112# undef MULTI_OMAP2
113# define MULTI_OMAP2
114# else
115# define OMAP_NAME DRA7XX
116# endif
117#endif
118
108/* 119/*
109 * Omap device type i.e. EMU/HS/TST/GP/BAD 120 * Omap device type i.e. EMU/HS/TST/GP/BAD
110 */ 121 */
@@ -233,6 +244,7 @@ IS_AM_SUBCLASS(437x, 0x437)
233#define cpu_is_omap447x() 0 244#define cpu_is_omap447x() 0
234#define soc_is_omap54xx() 0 245#define soc_is_omap54xx() 0
235#define soc_is_omap543x() 0 246#define soc_is_omap543x() 0
247#define soc_is_dra7xx() 0
236 248
237#if defined(MULTI_OMAP2) 249#if defined(MULTI_OMAP2)
238# if defined(CONFIG_ARCH_OMAP2) 250# if defined(CONFIG_ARCH_OMAP2)
@@ -379,6 +391,11 @@ IS_OMAP_TYPE(3430, 0x3430)
379# define soc_is_omap543x() is_omap543x() 391# define soc_is_omap543x() is_omap543x()
380#endif 392#endif
381 393
394#if defined(CONFIG_SOC_DRA7XX)
395#undef soc_is_dra7xx
396#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
397#endif
398
382/* Various silicon revisions for omap2 */ 399/* Various silicon revisions for omap2 */
383#define OMAP242X_CLASS 0x24200024 400#define OMAP242X_CLASS 0x24200024
384#define OMAP2420_REV_ES1_0 OMAP242X_CLASS 401#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index b37e1fcbad56..1e77f11c5f51 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -594,7 +594,8 @@ OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
594 1, "timer_sys_ck", "ti,timer-alwon"); 594 1, "timer_sys_ck", "ti,timer-alwon");
595#endif 595#endif
596 596
597#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) 597#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
598 defined(CONFIG_SOC_DRA7XX)
598static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", 599static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
599 2, "sys_clkin_ck", NULL); 600 2, "sys_clkin_ck", NULL);
600#endif 601#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 02:32:24 -0500