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-rw-r--r--arch/arm/mach-omap2/Kconfig1
-rw-r--r--arch/arm/mach-omap2/Makefile13
-rw-r--r--arch/arm/mach-omap2/am35xx-emac.c37
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c38
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c91
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c2
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c25
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c35
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c30
-rw-r--r--arch/arm/mach-omap2/board-flash.c4
-rw-r--r--arch/arm/mach-omap2/board-flash.h11
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c118
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c44
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c37
-rw-r--r--arch/arm/mach-omap2/board-omap3logic.c26
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c29
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c119
-rw-r--r--arch/arm/mach-omap2/board-overo.c25
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c92
-rw-r--r--arch/arm/mach-omap2/board-rx51.c38
-rw-r--r--arch/arm/mach-omap2/board-zoom-display.c1
-rw-r--r--arch/arm/mach-omap2/clock.c2
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c25
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c11
-rw-r--r--arch/arm/mach-omap2/clockdomain.c7
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c6
-rw-r--r--arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c10
-rw-r--r--arch/arm/mach-omap2/clockdomains3xxx_data.c6
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains_common_data.c24
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h4
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c28
-rw-r--r--arch/arm/mach-omap2/common.c1
-rw-r--r--arch/arm/mach-omap2/common.h6
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c298
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c126
-rw-r--r--arch/arm/mach-omap2/devices.c45
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c23
-rw-r--r--arch/arm/mach-omap2/dsp.c5
-rw-r--r--arch/arm/mach-omap2/gpio.c5
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c3
-rw-r--r--arch/arm/mach-omap2/gpmc.c3
-rw-r--r--arch/arm/mach-omap2/hdq1w.c72
-rw-r--r--arch/arm/mach-omap2/hwspinlock.c2
-rw-r--r--arch/arm/mach-omap2/id.c5
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h8
-rw-r--r--arch/arm/mach-omap2/io.c19
-rw-r--r--arch/arm/mach-omap2/irq.c6
-rw-r--r--arch/arm/mach-omap2/mailbox.c6
-rw-r--r--arch/arm/mach-omap2/msdi.c88
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/omap-secure.c1
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c2
-rw-r--r--arch/arm/mach-omap2/omap4-common.c58
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c1143
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c1580
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c1968
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c22
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c266
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c585
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c3087
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c6323
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h76
-rw-r--r--arch/arm/mach-omap2/pm.h21
-rw-r--r--arch/arm/mach-omap2/pm24xx.c3
-rw-r--r--arch/arm/mach-omap2/pm34xx.c10
-rw-r--r--arch/arm/mach-omap2/powerdomain.c10
-rw-r--r--arch/arm/mach-omap2/powerdomain.h1
-rw-r--r--arch/arm/mach-omap2/prcm-common.h17
-rw-r--r--arch/arm/mach-omap2/prcm.c8
-rw-r--r--arch/arm/mach-omap2/prm_common.c4
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c27
-rw-r--r--arch/arm/mach-omap2/serial.c10
-rw-r--r--arch/arm/mach-omap2/timer.c22
-rw-r--r--arch/arm/mach-omap2/twl-common.c190
-rw-r--r--arch/arm/mach-omap2/twl-common.h2
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c2
-rw-r--r--arch/arm/mach-omap2/vc3xxx_data.c1
-rw-r--r--arch/arm/mach-omap2/voltage.c21
-rw-r--r--arch/arm/mach-omap2/wd_timer.c45
-rw-r--r--arch/arm/mach-omap2/wd_timer.h1
82 files changed, 8435 insertions, 8744 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8141b76283a6..964ee67a3b77 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -17,6 +17,7 @@ config ARCH_OMAP2PLUS_TYPICAL
17 select MENELAUS if ARCH_OMAP2 17 select MENELAUS if ARCH_OMAP2
18 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 18 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
19 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 19 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
20 select HIGHMEM
20 help 21 help
21 Compile a kernel suitable for booting most boards 22 Compile a kernel suitable for booting most boards
22 23
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 49f92bc1c311..385c083d24b2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o display.o i2c.o 7 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
8 8
9omap-2-3-common = irq.o sdrc.o 9omap-2-3-common = irq.o sdrc.o
10hwmod-common = omap_hwmod.o \ 10hwmod-common = omap_hwmod.o \
@@ -118,16 +118,18 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
118 powerdomains44xx_data.o 118 powerdomains44xx_data.o
119 119
120# PRCM clockdomain control 120# PRCM clockdomain control
121obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ 121clockdomain-common += clockdomain.o \
122 clockdomains_common_data.o
123obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) \
122 clockdomain2xxx_3xxx.o \ 124 clockdomain2xxx_3xxx.o \
123 clockdomains2xxx_3xxx_data.o 125 clockdomains2xxx_3xxx_data.o
124obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o 126obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
125obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o 127obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
126obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ 128obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) \
127 clockdomain2xxx_3xxx.o \ 129 clockdomain2xxx_3xxx.o \
128 clockdomains2xxx_3xxx_data.o \ 130 clockdomains2xxx_3xxx_data.o \
129 clockdomains3xxx_data.o 131 clockdomains3xxx_data.o
130obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ 132obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) \
131 clockdomain44xx.o \ 133 clockdomain44xx.o \
132 clockdomains44xx_data.o 134 clockdomains44xx_data.o
133 135
@@ -187,6 +189,9 @@ ifneq ($(CONFIG_TIDSPBRIDGE),)
187obj-y += dsp.o 189obj-y += dsp.o
188endif 190endif
189 191
192# OMAP2420 MSDI controller integration support ("MMC")
193obj-$(CONFIG_SOC_OMAP2420) += msdi.o
194
190# Specific board support 195# Specific board support
191obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 196obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
192obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 197obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 1f97e7475206..447682c4e11c 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -39,26 +39,23 @@ static struct platform_device am35xx_emac_mdio_device = {
39 39
40static void am35xx_enable_emac_int(void) 40static void am35xx_enable_emac_int(void)
41{ 41{
42 u32 regval; 42 u32 v;
43 43
44 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); 44 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
45 regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | 45 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
46 AM35XX_CPGMAC_C0_TX_PULSE_CLR | 46 AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
47 AM35XX_CPGMAC_C0_MISC_PULSE_CLR | 47 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
48 AM35XX_CPGMAC_C0_RX_THRESH_CLR); 48 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
49 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
50 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
51} 49}
52 50
53static void am35xx_disable_emac_int(void) 51static void am35xx_disable_emac_int(void)
54{ 52{
55 u32 regval; 53 u32 v;
56 54
57 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); 55 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
58 regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR | 56 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
59 AM35XX_CPGMAC_C0_TX_PULSE_CLR); 57 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
60 omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); 58 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
61 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
62} 59}
63 60
64static struct emac_platform_data am35xx_emac_pdata = { 61static struct emac_platform_data am35xx_emac_pdata = {
@@ -92,7 +89,7 @@ static struct platform_device am35xx_emac_device = {
92 89
93void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) 90void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
94{ 91{
95 unsigned int regval; 92 u32 v;
96 int err; 93 int err;
97 94
98 am35xx_emac_pdata.rmii_en = rmii_en; 95 am35xx_emac_pdata.rmii_en = rmii_en;
@@ -110,8 +107,8 @@ void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
110 return; 107 return;
111 } 108 }
112 109
113 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); 110 v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
114 regval = regval & (~(AM35XX_CPGMACSS_SW_RST)); 111 v &= ~AM35XX_CPGMACSS_SW_RST;
115 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); 112 omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
116 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); 113 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
117} 114}
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index da75f239873e..37abb0d49b51 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -37,7 +37,7 @@
37#include <plat/dma.h> 37#include <plat/dma.h>
38#include <plat/gpmc.h> 38#include <plat/gpmc.h>
39#include <video/omapdss.h> 39#include <video/omapdss.h>
40#include <video/omap-panel-dvi.h> 40#include <video/omap-panel-tfp410.h>
41 41
42#include <plat/gpmc-smc91x.h> 42#include <plat/gpmc-smc91x.h>
43 43
@@ -113,9 +113,6 @@ static struct gpio sdp3430_dss_gpios[] __initdata = {
113 {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"}, 113 {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
114}; 114};
115 115
116static int lcd_enabled;
117static int dvi_enabled;
118
119static void __init sdp3430_display_init(void) 116static void __init sdp3430_display_init(void)
120{ 117{
121 int r; 118 int r;
@@ -129,44 +126,18 @@ static void __init sdp3430_display_init(void)
129 126
130static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) 127static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
131{ 128{
132 if (dvi_enabled) {
133 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
134 return -EINVAL;
135 }
136
137 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1); 129 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
138 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1); 130 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
139 131
140 lcd_enabled = 1;
141
142 return 0; 132 return 0;
143} 133}
144 134
145static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) 135static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
146{ 136{
147 lcd_enabled = 0;
148
149 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0); 137 gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
150 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0); 138 gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
151} 139}
152 140
153static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
154{
155 if (lcd_enabled) {
156 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
157 return -EINVAL;
158 }
159
160 dvi_enabled = 1;
161
162 return 0;
163}
164
165static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
166{
167 dvi_enabled = 0;
168}
169
170static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) 141static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
171{ 142{
172 return 0; 143 return 0;
@@ -186,15 +157,14 @@ static struct omap_dss_device sdp3430_lcd_device = {
186 .platform_disable = sdp3430_panel_disable_lcd, 157 .platform_disable = sdp3430_panel_disable_lcd,
187}; 158};
188 159
189static struct panel_dvi_platform_data dvi_panel = { 160static struct tfp410_platform_data dvi_panel = {
190 .platform_enable = sdp3430_panel_enable_dvi, 161 .power_down_gpio = -1,
191 .platform_disable = sdp3430_panel_disable_dvi,
192}; 162};
193 163
194static struct omap_dss_device sdp3430_dvi_device = { 164static struct omap_dss_device sdp3430_dvi_device = {
195 .name = "dvi", 165 .name = "dvi",
196 .type = OMAP_DISPLAY_TYPE_DPI, 166 .type = OMAP_DISPLAY_TYPE_DPI,
197 .driver_name = "dvi", 167 .driver_name = "tfp410",
198 .data = &dvi_panel, 168 .data = &dvi_panel,
199 .phy.dpi.data_lines = 24, 169 .phy.dpi.data_lines = 24,
200}; 170};
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 130ab00c09a2..94af6cde2e36 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -384,6 +384,11 @@ static struct platform_device sdp4430_dmic_codec = {
384 .id = -1, 384 .id = -1,
385}; 385};
386 386
387static struct platform_device sdp4430_hdmi_audio_codec = {
388 .name = "hdmi-audio-codec",
389 .id = -1,
390};
391
387static struct omap_abe_twl6040_data sdp4430_abe_audio_data = { 392static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
388 .card_name = "SDP4430", 393 .card_name = "SDP4430",
389 .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, 394 .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
@@ -418,6 +423,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
418 &sdp4430_vbat, 423 &sdp4430_vbat,
419 &sdp4430_dmic_codec, 424 &sdp4430_dmic_codec,
420 &sdp4430_abe_audio, 425 &sdp4430_abe_audio,
426 &sdp4430_hdmi_audio_codec,
421}; 427};
422 428
423static struct omap_musb_board_data musb_board_data = { 429static struct omap_musb_board_data musb_board_data = {
@@ -489,50 +495,6 @@ static struct platform_device omap_vwlan_device = {
489 }, 495 },
490}; 496};
491 497
492static int omap4_twl6030_hsmmc_late_init(struct device *dev)
493{
494 int irq = 0;
495 struct platform_device *pdev = container_of(dev,
496 struct platform_device, dev);
497 struct omap_mmc_platform_data *pdata = dev->platform_data;
498
499 /* Setting MMC1 Card detect Irq */
500 if (pdev->id == 0) {
501 irq = twl6030_mmc_card_detect_config();
502 if (irq < 0) {
503 pr_err("Failed configuring MMC1 card detect\n");
504 return irq;
505 }
506 pdata->slots[0].card_detect_irq = irq;
507 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
508 }
509 return 0;
510}
511
512static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
513{
514 struct omap_mmc_platform_data *pdata;
515
516 /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
517 if (!dev) {
518 pr_err("Failed %s\n", __func__);
519 return;
520 }
521 pdata = dev->platform_data;
522 pdata->init = omap4_twl6030_hsmmc_late_init;
523}
524
525static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
526{
527 struct omap2_hsmmc_info *c;
528
529 omap_hsmmc_init(controllers);
530 for (c = controllers; c->mmc; c++)
531 omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
532
533 return 0;
534}
535
536static struct regulator_init_data sdp4430_vaux1 = { 498static struct regulator_init_data sdp4430_vaux1 = {
537 .constraints = { 499 .constraints = {
538 .min_uV = 1000000, 500 .min_uV = 1000000,
@@ -615,7 +577,9 @@ static int __init omap4_i2c_init(void)
615 TWL_COMMON_REGULATOR_VANA | 577 TWL_COMMON_REGULATOR_VANA |
616 TWL_COMMON_REGULATOR_VCXIO | 578 TWL_COMMON_REGULATOR_VCXIO |
617 TWL_COMMON_REGULATOR_VUSB | 579 TWL_COMMON_REGULATOR_VUSB |
618 TWL_COMMON_REGULATOR_CLK32KG); 580 TWL_COMMON_REGULATOR_CLK32KG |
581 TWL_COMMON_REGULATOR_V1V8 |
582 TWL_COMMON_REGULATOR_V2V1);
619 omap4_pmic_init("twl6030", &sdp4430_twldata, 583 omap4_pmic_init("twl6030", &sdp4430_twldata,
620 &twl6040_data, OMAP44XX_IRQ_SYS_2N); 584 &twl6040_data, OMAP44XX_IRQ_SYS_2N);
621 omap_register_i2c_bus(2, 400, NULL, 0); 585 omap_register_i2c_bus(2, 400, NULL, 0);
@@ -666,6 +630,10 @@ static struct nokia_dsi_panel_data dsi1_panel = {
666 .use_ext_te = false, 630 .use_ext_te = false,
667 .ext_te_gpio = 101, 631 .ext_te_gpio = 101,
668 .esd_interval = 0, 632 .esd_interval = 0,
633 .pin_config = {
634 .num_pins = 6,
635 .pins = { 0, 1, 2, 3, 4, 5 },
636 },
669}; 637};
670 638
671static struct omap_dss_device sdp4430_lcd_device = { 639static struct omap_dss_device sdp4430_lcd_device = {
@@ -674,13 +642,6 @@ static struct omap_dss_device sdp4430_lcd_device = {
674 .type = OMAP_DISPLAY_TYPE_DSI, 642 .type = OMAP_DISPLAY_TYPE_DSI,
675 .data = &dsi1_panel, 643 .data = &dsi1_panel,
676 .phy.dsi = { 644 .phy.dsi = {
677 .clk_lane = 1,
678 .clk_pol = 0,
679 .data1_lane = 2,
680 .data1_pol = 0,
681 .data2_lane = 3,
682 .data2_pol = 0,
683
684 .module = 0, 645 .module = 0,
685 }, 646 },
686 647
@@ -715,6 +676,10 @@ static struct nokia_dsi_panel_data dsi2_panel = {
715 .use_ext_te = false, 676 .use_ext_te = false,
716 .ext_te_gpio = 103, 677 .ext_te_gpio = 103,
717 .esd_interval = 0, 678 .esd_interval = 0,
679 .pin_config = {
680 .num_pins = 6,
681 .pins = { 0, 1, 2, 3, 4, 5 },
682 },
718}; 683};
719 684
720static struct omap_dss_device sdp4430_lcd2_device = { 685static struct omap_dss_device sdp4430_lcd2_device = {
@@ -723,12 +688,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
723 .type = OMAP_DISPLAY_TYPE_DSI, 688 .type = OMAP_DISPLAY_TYPE_DSI,
724 .data = &dsi2_panel, 689 .data = &dsi2_panel,
725 .phy.dsi = { 690 .phy.dsi = {
726 .clk_lane = 1,
727 .clk_pol = 0,
728 .data1_lane = 2,
729 .data1_pol = 0,
730 .data2_lane = 3,
731 .data2_pol = 0,
732 691
733 .module = 1, 692 .module = 1,
734 }, 693 },
@@ -758,21 +717,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
758 .channel = OMAP_DSS_CHANNEL_LCD2, 717 .channel = OMAP_DSS_CHANNEL_LCD2,
759}; 718};
760 719
761static void sdp4430_lcd_init(void)
762{
763 int r;
764
765 r = gpio_request_one(dsi1_panel.reset_gpio, GPIOF_DIR_OUT,
766 "lcd1_reset_gpio");
767 if (r)
768 pr_err("%s: Could not get lcd1_reset_gpio\n", __func__);
769
770 r = gpio_request_one(dsi2_panel.reset_gpio, GPIOF_DIR_OUT,
771 "lcd2_reset_gpio");
772 if (r)
773 pr_err("%s: Could not get lcd2_reset_gpio\n", __func__);
774}
775
776static struct omap_dss_hdmi_data sdp4430_hdmi_data = { 720static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
777 .hpd_gpio = HDMI_GPIO_HPD, 721 .hpd_gpio = HDMI_GPIO_HPD,
778}; 722};
@@ -858,7 +802,6 @@ static void __init omap_4430sdp_display_init(void)
858 if (r) 802 if (r)
859 pr_err("%s: Could not get display_sel GPIO\n", __func__); 803 pr_err("%s: Could not get display_sel GPIO\n", __func__);
860 804
861 sdp4430_lcd_init();
862 sdp4430_picodlp_init(); 805 sdp4430_picodlp_init();
863 omap_display_init(&sdp4430_dss_data); 806 omap_display_init(&sdp4430_dss_data);
864 /* 807 /*
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index c3851e8de28b..3b8a53c1f2a8 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -30,6 +30,7 @@
30#include "common.h" 30#include "common.h"
31#include <plat/usb.h> 31#include <plat/usb.h>
32 32
33#include "am35xx-emac.h"
33#include "mux.h" 34#include "mux.h"
34#include "control.h" 35#include "control.h"
35 36
@@ -90,6 +91,7 @@ static void __init am3517_crane_init(void)
90 } 91 }
91 92
92 usbhs_init(&usbhs_bdata); 93 usbhs_init(&usbhs_bdata);
94 am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
93} 95}
94 96
95MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") 97MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 3645285a3e2b..99790eb646e8 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -37,7 +37,7 @@
37#include <plat/usb.h> 37#include <plat/usb.h>
38#include <video/omapdss.h> 38#include <video/omapdss.h>
39#include <video/omap-panel-generic-dpi.h> 39#include <video/omap-panel-generic-dpi.h>
40#include <video/omap-panel-dvi.h> 40#include <video/omap-panel-tfp410.h>
41 41
42#include "am35xx-emac.h" 42#include "am35xx-emac.h"
43#include "mux.h" 43#include "mux.h"
@@ -207,31 +207,14 @@ static struct omap_dss_device am3517_evm_tv_device = {
207 .platform_disable = am3517_evm_panel_disable_tv, 207 .platform_disable = am3517_evm_panel_disable_tv,
208}; 208};
209 209
210static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev) 210static struct tfp410_platform_data dvi_panel = {
211{ 211 .power_down_gpio = -1,
212 if (lcd_enabled) {
213 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
214 return -EINVAL;
215 }
216 dvi_enabled = 1;
217
218 return 0;
219}
220
221static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev)
222{
223 dvi_enabled = 0;
224}
225
226static struct panel_dvi_platform_data dvi_panel = {
227 .platform_enable = am3517_evm_panel_enable_dvi,
228 .platform_disable = am3517_evm_panel_disable_dvi,
229}; 212};
230 213
231static struct omap_dss_device am3517_evm_dvi_device = { 214static struct omap_dss_device am3517_evm_dvi_device = {
232 .type = OMAP_DISPLAY_TYPE_DPI, 215 .type = OMAP_DISPLAY_TYPE_DPI,
233 .name = "dvi", 216 .name = "dvi",
234 .driver_name = "dvi", 217 .driver_name = "tfp410",
235 .data = &dvi_panel, 218 .data = &dvi_panel,
236 .phy.dpi.data_lines = 24, 219 .phy.dpi.data_lines = 24,
237}; 220};
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 909a8b91b564..c03df142ea67 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -44,7 +44,7 @@
44#include <plat/usb.h> 44#include <plat/usb.h>
45#include <video/omapdss.h> 45#include <video/omapdss.h>
46#include <video/omap-panel-generic-dpi.h> 46#include <video/omap-panel-generic-dpi.h>
47#include <video/omap-panel-dvi.h> 47#include <video/omap-panel-tfp410.h>
48#include <plat/mcspi.h> 48#include <plat/mcspi.h>
49 49
50#include <mach/hardware.h> 50#include <mach/hardware.h>
@@ -218,25 +218,6 @@ static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
218 gpio_set_value(CM_T35_LCD_EN_GPIO, 0); 218 gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
219} 219}
220 220
221static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
222{
223 if (lcd_enabled) {
224 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
225 return -EINVAL;
226 }
227
228 gpio_set_value(CM_T35_DVI_EN_GPIO, 0);
229 dvi_enabled = 1;
230
231 return 0;
232}
233
234static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev)
235{
236 gpio_set_value(CM_T35_DVI_EN_GPIO, 1);
237 dvi_enabled = 0;
238}
239
240static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) 221static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
241{ 222{
242 return 0; 223 return 0;
@@ -260,15 +241,14 @@ static struct omap_dss_device cm_t35_lcd_device = {
260 .phy.dpi.data_lines = 18, 241 .phy.dpi.data_lines = 18,
261}; 242};
262 243
263static struct panel_dvi_platform_data dvi_panel = { 244static struct tfp410_platform_data dvi_panel = {
264 .platform_enable = cm_t35_panel_enable_dvi, 245 .power_down_gpio = CM_T35_DVI_EN_GPIO,
265 .platform_disable = cm_t35_panel_disable_dvi,
266}; 246};
267 247
268static struct omap_dss_device cm_t35_dvi_device = { 248static struct omap_dss_device cm_t35_dvi_device = {
269 .name = "dvi", 249 .name = "dvi",
270 .type = OMAP_DISPLAY_TYPE_DPI, 250 .type = OMAP_DISPLAY_TYPE_DPI,
271 .driver_name = "dvi", 251 .driver_name = "tfp410",
272 .data = &dvi_panel, 252 .data = &dvi_panel,
273 .phy.dpi.data_lines = 24, 253 .phy.dpi.data_lines = 24,
274}; 254};
@@ -316,7 +296,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
316static struct gpio cm_t35_dss_gpios[] __initdata = { 296static struct gpio cm_t35_dss_gpios[] __initdata = {
317 { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" }, 297 { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" },
318 { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" }, 298 { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" },
319 { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable" },
320}; 299};
321 300
322static void __init cm_t35_init_display(void) 301static void __init cm_t35_init_display(void)
@@ -335,7 +314,6 @@ static void __init cm_t35_init_display(void)
335 314
336 gpio_export(CM_T35_LCD_EN_GPIO, 0); 315 gpio_export(CM_T35_LCD_EN_GPIO, 0);
337 gpio_export(CM_T35_LCD_BL_GPIO, 0); 316 gpio_export(CM_T35_LCD_BL_GPIO, 0);
338 gpio_export(CM_T35_DVI_EN_GPIO, 0);
339 317
340 msleep(50); 318 msleep(50);
341 gpio_set_value(CM_T35_LCD_EN_GPIO, 1); 319 gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
@@ -498,6 +476,10 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
498 .setup = cm_t35_twl_gpio_setup, 476 .setup = cm_t35_twl_gpio_setup,
499}; 477};
500 478
479static struct twl4030_power_data cm_t35_power_data = {
480 .use_poweroff = true,
481};
482
501static struct twl4030_platform_data cm_t35_twldata = { 483static struct twl4030_platform_data cm_t35_twldata = {
502 /* platform_data for children goes here */ 484 /* platform_data for children goes here */
503 .keypad = &cm_t35_kp_data, 485 .keypad = &cm_t35_kp_data,
@@ -505,6 +487,7 @@ static struct twl4030_platform_data cm_t35_twldata = {
505 .vmmc1 = &cm_t35_vmmc1, 487 .vmmc1 = &cm_t35_vmmc1,
506 .vsim = &cm_t35_vsim, 488 .vsim = &cm_t35_vsim,
507 .vio = &cm_t35_vio, 489 .vio = &cm_t35_vio,
490 .power = &cm_t35_power_data,
508}; 491};
509 492
510static void __init cm_t35_init_i2c(void) 493static void __init cm_t35_init_i2c(void)
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a2010f07de31..b063f0d2faa6 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -47,7 +47,7 @@
47#include <plat/usb.h> 47#include <plat/usb.h>
48#include <video/omapdss.h> 48#include <video/omapdss.h>
49#include <video/omap-panel-generic-dpi.h> 49#include <video/omap-panel-generic-dpi.h>
50#include <video/omap-panel-dvi.h> 50#include <video/omap-panel-tfp410.h>
51 51
52#include <plat/mcspi.h> 52#include <plat/mcspi.h>
53#include <linux/input/matrix_keypad.h> 53#include <linux/input/matrix_keypad.h>
@@ -118,19 +118,6 @@ static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
118 gpio_set_value_cansleep(dssdev->reset_gpio, 0); 118 gpio_set_value_cansleep(dssdev->reset_gpio, 0);
119} 119}
120 120
121static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
122{
123 if (gpio_is_valid(dssdev->reset_gpio))
124 gpio_set_value_cansleep(dssdev->reset_gpio, 1);
125 return 0;
126}
127
128static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
129{
130 if (gpio_is_valid(dssdev->reset_gpio))
131 gpio_set_value_cansleep(dssdev->reset_gpio, 0);
132}
133
134static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = { 121static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
135 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), 122 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
136}; 123};
@@ -154,15 +141,14 @@ static struct omap_dss_device devkit8000_lcd_device = {
154 .phy.dpi.data_lines = 24, 141 .phy.dpi.data_lines = 24,
155}; 142};
156 143
157static struct panel_dvi_platform_data dvi_panel = { 144static struct tfp410_platform_data dvi_panel = {
158 .platform_enable = devkit8000_panel_enable_dvi, 145 .power_down_gpio = -1,
159 .platform_disable = devkit8000_panel_disable_dvi,
160}; 146};
161 147
162static struct omap_dss_device devkit8000_dvi_device = { 148static struct omap_dss_device devkit8000_dvi_device = {
163 .name = "dvi", 149 .name = "dvi",
164 .type = OMAP_DISPLAY_TYPE_DPI, 150 .type = OMAP_DISPLAY_TYPE_DPI,
165 .driver_name = "dvi", 151 .driver_name = "tfp410",
166 .data = &dvi_panel, 152 .data = &dvi_panel,
167 .phy.dpi.data_lines = 24, 153 .phy.dpi.data_lines = 24,
168}; 154};
@@ -244,13 +230,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
244 } 230 }
245 231
246 /* gpio + 7 is "DVI_PD" (out, active low) */ 232 /* gpio + 7 is "DVI_PD" (out, active low) */
247 devkit8000_dvi_device.reset_gpio = gpio + 7; 233 dvi_panel.power_down_gpio = gpio + 7;
248 ret = gpio_request_one(devkit8000_dvi_device.reset_gpio,
249 GPIOF_OUT_INIT_LOW, "DVI PowerDown");
250 if (ret < 0) {
251 devkit8000_dvi_device.reset_gpio = -EINVAL;
252 printk(KERN_ERR "Failed to request GPIO for DVI PowerDown\n");
253 }
254 234
255 return 0; 235 return 0;
256} 236}
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 0349fd2b68d8..70a81f900bb5 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -87,7 +87,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
87 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ 87 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
88}; 88};
89 89
90static void 90void
91__init board_onenand_init(struct mtd_partition *onenand_parts, 91__init board_onenand_init(struct mtd_partition *onenand_parts,
92 u8 nr_parts, u8 cs) 92 u8 nr_parts, u8 cs)
93{ 93{
@@ -98,7 +98,7 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
98 gpmc_onenand_init(&board_onenand_data); 98 gpmc_onenand_init(&board_onenand_data);
99} 99}
100#else 100#else
101static void 101void
102__init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) 102__init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
103{ 103{
104} 104}
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index d25503a98417..c44b70d52021 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -47,3 +47,14 @@ static inline void board_nand_init(struct mtd_partition *nand_parts,
47{ 47{
48} 48}
49#endif 49#endif
50
51#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
52 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
53extern void board_onenand_init(struct mtd_partition *nand_parts,
54 u8 nr_parts, u8 cs);
55#else
56static inline void board_onenand_init(struct mtd_partition *nand_parts,
57 u8 nr_parts, u8 cs)
58{
59}
60#endif
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 930c0d380435..7a274098f67b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -24,6 +24,8 @@
24#include <linux/i2c/twl.h> 24#include <linux/i2c/twl.h>
25#include <linux/mmc/host.h> 25#include <linux/mmc/host.h>
26 26
27#include <linux/mtd/nand.h>
28
27#include <asm/mach-types.h> 29#include <asm/mach-types.h>
28#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
29 31
@@ -32,13 +34,15 @@
32#include <plat/gpmc.h> 34#include <plat/gpmc.h>
33#include <plat/usb.h> 35#include <plat/usb.h>
34#include <video/omapdss.h> 36#include <video/omapdss.h>
35#include <video/omap-panel-dvi.h> 37#include <video/omap-panel-tfp410.h>
36#include <plat/onenand.h> 38#include <plat/onenand.h>
37 39
38#include "mux.h" 40#include "mux.h"
39#include "hsmmc.h" 41#include "hsmmc.h"
40#include "sdram-numonyx-m65kxxxxam.h" 42#include "sdram-numonyx-m65kxxxxam.h"
41#include "common-board-devices.h" 43#include "common-board-devices.h"
44#include "board-flash.h"
45#include "control.h"
42 46
43#define IGEP2_SMSC911X_CS 5 47#define IGEP2_SMSC911X_CS 5
44#define IGEP2_SMSC911X_GPIO 176 48#define IGEP2_SMSC911X_GPIO 176
@@ -60,6 +64,10 @@
60#define IGEP3_GPIO_LED1_RED 16 64#define IGEP3_GPIO_LED1_RED 16
61#define IGEP3_GPIO_USBH_NRESET 183 65#define IGEP3_GPIO_USBH_NRESET 183
62 66
67#define IGEP_SYSBOOT_MASK 0x1f
68#define IGEP_SYSBOOT_NAND 0x0f
69#define IGEP_SYSBOOT_ONENAND 0x10
70
63/* 71/*
64 * IGEP2 Hardware Revision Table 72 * IGEP2 Hardware Revision Table
65 * 73 *
@@ -110,8 +118,10 @@ static void __init igep2_get_revision(void)
110 gpio_free(IGEP2_GPIO_LED1_RED); 118 gpio_free(IGEP2_GPIO_LED1_RED);
111} 119}
112 120
113#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ 121#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
114 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) 122 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) || \
123 defined(CONFIG_MTD_NAND_OMAP2) || \
124 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
115 125
116#define ONENAND_MAP 0x20000000 126#define ONENAND_MAP 0x20000000
117 127
@@ -123,7 +133,7 @@ static void __init igep2_get_revision(void)
123 * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048) 133 * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
124 */ 134 */
125 135
126static struct mtd_partition igep_onenand_partitions[] = { 136static struct mtd_partition igep_flash_partitions[] = {
127 { 137 {
128 .name = "X-Loader", 138 .name = "X-Loader",
129 .offset = 0, 139 .offset = 0,
@@ -151,50 +161,28 @@ static struct mtd_partition igep_onenand_partitions[] = {
151 }, 161 },
152}; 162};
153 163
154static struct omap_onenand_platform_data igep_onenand_data = { 164static inline u32 igep_get_sysboot_value(void)
155 .parts = igep_onenand_partitions, 165{
156 .nr_parts = ARRAY_SIZE(igep_onenand_partitions), 166 return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK;
157 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ 167}
158};
159
160static struct platform_device igep_onenand_device = {
161 .name = "omap2-onenand",
162 .id = -1,
163 .dev = {
164 .platform_data = &igep_onenand_data,
165 },
166};
167 168
168static void __init igep_flash_init(void) 169static void __init igep_flash_init(void)
169{ 170{
170 u8 cs = 0; 171 u32 mux;
171 u8 onenandcs = GPMC_CS_NUM + 1; 172 mux = igep_get_sysboot_value();
172 173
173 for (cs = 0; cs < GPMC_CS_NUM; cs++) { 174 if (mux == IGEP_SYSBOOT_NAND) {
174 u32 ret; 175 pr_info("IGEP: initializing NAND memory device\n");
175 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 176 board_nand_init(igep_flash_partitions,
176 177 ARRAY_SIZE(igep_flash_partitions),
177 /* Check if NAND/oneNAND is configured */ 178 0, NAND_BUSWIDTH_16);
178 if ((ret & 0xC00) == 0x800) 179 } else if (mux == IGEP_SYSBOOT_ONENAND) {
179 /* NAND found */ 180 pr_info("IGEP: initializing OneNAND memory device\n");
180 pr_err("IGEP: Unsupported NAND found\n"); 181 board_onenand_init(igep_flash_partitions,
181 else { 182 ARRAY_SIZE(igep_flash_partitions), 0);
182 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 183 } else {
183 if ((ret & 0x3F) == (ONENAND_MAP >> 24)) 184 pr_err("IGEP: Flash: unsupported sysboot sequence found\n");
184 /* ONENAND found */
185 onenandcs = cs;
186 }
187 }
188
189 if (onenandcs > GPMC_CS_NUM) {
190 pr_err("IGEP: Unable to find configuration in GPMC\n");
191 return;
192 } 185 }
193
194 igep_onenand_data.cs = onenandcs;
195
196 if (platform_device_register(&igep_onenand_device) < 0)
197 pr_err("IGEP: Unable to register OneNAND device\n");
198} 186}
199 187
200#else 188#else
@@ -444,28 +432,15 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
444 .setup = igep_twl_gpio_setup, 432 .setup = igep_twl_gpio_setup,
445}; 433};
446 434
447static int igep2_enable_dvi(struct omap_dss_device *dssdev) 435static struct tfp410_platform_data dvi_panel = {
448{ 436 .i2c_bus_num = 3,
449 gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1); 437 .power_down_gpio = IGEP2_GPIO_DVI_PUP,
450
451 return 0;
452}
453
454static void igep2_disable_dvi(struct omap_dss_device *dssdev)
455{
456 gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0);
457}
458
459static struct panel_dvi_platform_data dvi_panel = {
460 .platform_enable = igep2_enable_dvi,
461 .platform_disable = igep2_disable_dvi,
462 .i2c_bus_num = 3,
463}; 438};
464 439
465static struct omap_dss_device igep2_dvi_device = { 440static struct omap_dss_device igep2_dvi_device = {
466 .type = OMAP_DISPLAY_TYPE_DPI, 441 .type = OMAP_DISPLAY_TYPE_DPI,
467 .name = "dvi", 442 .name = "dvi",
468 .driver_name = "dvi", 443 .driver_name = "tfp410",
469 .data = &dvi_panel, 444 .data = &dvi_panel,
470 .phy.dpi.data_lines = 24, 445 .phy.dpi.data_lines = 24,
471}; 446};
@@ -480,14 +455,6 @@ static struct omap_dss_board_info igep2_dss_data = {
480 .default_device = &igep2_dvi_device, 455 .default_device = &igep2_dvi_device,
481}; 456};
482 457
483static void __init igep2_display_init(void)
484{
485 int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
486 "GPIO_DVI_PUP");
487 if (err)
488 pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
489}
490
491static struct platform_device *igep_devices[] __initdata = { 458static struct platform_device *igep_devices[] __initdata = {
492 &igep_vwlan_device, 459 &igep_vwlan_device,
493}; 460};
@@ -540,7 +507,10 @@ static void __init igep_i2c_init(void)
540{ 507{
541 int ret; 508 int ret;
542 509
543 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0); 510 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB,
511 TWL_COMMON_REGULATOR_VPLL2);
512 igep_twldata.vpll2->constraints.apply_uV = true;
513 igep_twldata.vpll2->constraints.name = "VDVI";
544 514
545 if (machine_is_igep0020()) { 515 if (machine_is_igep0020()) {
546 /* 516 /*
@@ -554,10 +524,7 @@ static void __init igep_i2c_init(void)
554 524
555 igep_twldata.keypad = &igep2_keypad_pdata; 525 igep_twldata.keypad = &igep2_keypad_pdata;
556 /* Get common pmic data */ 526 /* Get common pmic data */
557 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 527 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0);
558 TWL_COMMON_REGULATOR_VPLL2);
559 igep_twldata.vpll2->constraints.apply_uV = true;
560 igep_twldata.vpll2->constraints.name = "VDVI";
561 } 528 }
562 529
563 omap3_pmic_init("twl4030", &igep_twldata); 530 omap3_pmic_init("twl4030", &igep_twldata);
@@ -641,7 +608,7 @@ static struct regulator_consumer_supply dummy_supplies[] = {
641 608
642static void __init igep_init(void) 609static void __init igep_init(void)
643{ 610{
644 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 611 regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
645 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 612 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
646 613
647 /* Get IGEP2 hardware revision */ 614 /* Get IGEP2 hardware revision */
@@ -668,7 +635,6 @@ static void __init igep_init(void)
668 635
669 if (machine_is_igep0020()) { 636 if (machine_is_igep0020()) {
670 omap_display_init(&igep2_dss_data); 637 omap_display_init(&igep2_dss_data);
671 igep2_display_init();
672 igep2_init_smsc911x(); 638 igep2_init_smsc911x();
673 usbhs_init(&igep2_usbhs_bdata); 639 usbhs_init(&igep2_usbhs_bdata);
674 } else { 640 } else {
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7be8d659d91d..2a7b9a9da1db 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -42,7 +42,7 @@
42#include <plat/board.h> 42#include <plat/board.h>
43#include "common.h" 43#include "common.h"
44#include <video/omapdss.h> 44#include <video/omapdss.h>
45#include <video/omap-panel-dvi.h> 45#include <video/omap-panel-tfp410.h>
46#include <plat/gpmc.h> 46#include <plat/gpmc.h>
47#include <plat/nand.h> 47#include <plat/nand.h>
48#include <plat/usb.h> 48#include <plat/usb.h>
@@ -83,11 +83,13 @@ static struct {
83 int usb_pwr_level; 83 int usb_pwr_level;
84 int reset_gpio; 84 int reset_gpio;
85 int usr_button_gpio; 85 int usr_button_gpio;
86 int mmc_caps;
86} beagle_config = { 87} beagle_config = {
87 .mmc1_gpio_wp = -EINVAL, 88 .mmc1_gpio_wp = -EINVAL,
88 .usb_pwr_level = GPIOF_OUT_INIT_LOW, 89 .usb_pwr_level = GPIOF_OUT_INIT_LOW,
89 .reset_gpio = 129, 90 .reset_gpio = 129,
90 .usr_button_gpio = 4, 91 .usr_button_gpio = 4,
92 .mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
91}; 93};
92 94
93static struct gpio omap3_beagle_rev_gpios[] __initdata = { 95static struct gpio omap3_beagle_rev_gpios[] __initdata = {
@@ -145,10 +147,12 @@ static void __init omap3_beagle_init_rev(void)
145 printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n"); 147 printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n");
146 omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; 148 omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
147 beagle_config.usb_pwr_level = GPIOF_OUT_INIT_HIGH; 149 beagle_config.usb_pwr_level = GPIOF_OUT_INIT_HIGH;
150 beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
148 break; 151 break;
149 case 2: 152 case 2:
150 printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n"); 153 printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n");
151 omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC; 154 omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC;
155 beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
152 break; 156 break;
153 default: 157 default:
154 printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev); 158 printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
@@ -189,33 +193,17 @@ static struct mtd_partition omap3beagle_nand_partitions[] = {
189 193
190/* DSS */ 194/* DSS */
191 195
192static int beagle_enable_dvi(struct omap_dss_device *dssdev) 196static struct tfp410_platform_data dvi_panel = {
193{
194 if (gpio_is_valid(dssdev->reset_gpio))
195 gpio_set_value(dssdev->reset_gpio, 1);
196
197 return 0;
198}
199
200static void beagle_disable_dvi(struct omap_dss_device *dssdev)
201{
202 if (gpio_is_valid(dssdev->reset_gpio))
203 gpio_set_value(dssdev->reset_gpio, 0);
204}
205
206static struct panel_dvi_platform_data dvi_panel = {
207 .platform_enable = beagle_enable_dvi,
208 .platform_disable = beagle_disable_dvi,
209 .i2c_bus_num = 3, 197 .i2c_bus_num = 3,
198 .power_down_gpio = -1,
210}; 199};
211 200
212static struct omap_dss_device beagle_dvi_device = { 201static struct omap_dss_device beagle_dvi_device = {
213 .type = OMAP_DISPLAY_TYPE_DPI, 202 .type = OMAP_DISPLAY_TYPE_DPI,
214 .name = "dvi", 203 .name = "dvi",
215 .driver_name = "dvi", 204 .driver_name = "tfp410",
216 .data = &dvi_panel, 205 .data = &dvi_panel,
217 .phy.dpi.data_lines = 24, 206 .phy.dpi.data_lines = 24,
218 .reset_gpio = -EINVAL,
219}; 207};
220 208
221static struct omap_dss_device beagle_tv_device = { 209static struct omap_dss_device beagle_tv_device = {
@@ -236,22 +224,12 @@ static struct omap_dss_board_info beagle_dss_data = {
236 .default_device = &beagle_dvi_device, 224 .default_device = &beagle_dvi_device,
237}; 225};
238 226
239static void __init beagle_display_init(void)
240{
241 int r;
242
243 r = gpio_request_one(beagle_dvi_device.reset_gpio, GPIOF_OUT_INIT_LOW,
244 "DVI reset");
245 if (r < 0)
246 printk(KERN_ERR "Unable to get DVI reset GPIO\n");
247}
248
249#include "sdram-micron-mt46h32m32lf-6.h" 227#include "sdram-micron-mt46h32m32lf-6.h"
250 228
251static struct omap2_hsmmc_info mmc[] = { 229static struct omap2_hsmmc_info mmc[] = {
252 { 230 {
253 .mmc = 1, 231 .mmc = 1,
254 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 232 .caps = MMC_CAP_4_BIT_DATA,
255 .gpio_wp = -EINVAL, 233 .gpio_wp = -EINVAL,
256 .deferred = true, 234 .deferred = true,
257 }, 235 },
@@ -309,7 +287,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
309 if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC")) 287 if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
310 pr_err("%s: unable to configure EHCI_nOC\n", __func__); 288 pr_err("%s: unable to configure EHCI_nOC\n", __func__);
311 } 289 }
312 beagle_dvi_device.reset_gpio = beagle_config.reset_gpio; 290 dvi_panel.power_down_gpio = beagle_config.reset_gpio;
313 291
314 gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level, 292 gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
315 "nEN_USB_PWR"); 293 "nEN_USB_PWR");
@@ -523,6 +501,7 @@ static void __init omap3_beagle_init(void)
523 501
524 if (beagle_config.mmc1_gpio_wp != -EINVAL) 502 if (beagle_config.mmc1_gpio_wp != -EINVAL)
525 omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT); 503 omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
504 mmc[0].caps = beagle_config.mmc_caps;
526 omap_hsmmc_init(mmc); 505 omap_hsmmc_init(mmc);
527 506
528 omap3_beagle_i2c_init(); 507 omap3_beagle_i2c_init();
@@ -552,7 +531,6 @@ static void __init omap3_beagle_init(void)
552 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); 531 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
553 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); 532 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
554 533
555 beagle_display_init();
556 beagle_opp_init(); 534 beagle_opp_init();
557} 535}
558 536
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 49df12735b41..ace3c675e9c2 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -46,7 +46,7 @@
46#include "common.h" 46#include "common.h"
47#include <plat/mcspi.h> 47#include <plat/mcspi.h>
48#include <video/omapdss.h> 48#include <video/omapdss.h>
49#include <video/omap-panel-dvi.h> 49#include <video/omap-panel-tfp410.h>
50 50
51#include "mux.h" 51#include "mux.h"
52#include "sdram-micron-mt46h32m32lf-6.h" 52#include "sdram-micron-mt46h32m32lf-6.h"
@@ -219,35 +219,14 @@ static struct omap_dss_device omap3_evm_tv_device = {
219 .platform_disable = omap3_evm_disable_tv, 219 .platform_disable = omap3_evm_disable_tv,
220}; 220};
221 221
222static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev) 222static struct tfp410_platform_data dvi_panel = {
223{ 223 .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO,
224 if (lcd_enabled) {
225 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
226 return -EINVAL;
227 }
228
229 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
230
231 dvi_enabled = 1;
232 return 0;
233}
234
235static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
236{
237 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
238
239 dvi_enabled = 0;
240}
241
242static struct panel_dvi_platform_data dvi_panel = {
243 .platform_enable = omap3_evm_enable_dvi,
244 .platform_disable = omap3_evm_disable_dvi,
245}; 224};
246 225
247static struct omap_dss_device omap3_evm_dvi_device = { 226static struct omap_dss_device omap3_evm_dvi_device = {
248 .name = "dvi", 227 .name = "dvi",
249 .type = OMAP_DISPLAY_TYPE_DPI, 228 .type = OMAP_DISPLAY_TYPE_DPI,
250 .driver_name = "dvi", 229 .driver_name = "tfp410",
251 .data = &dvi_panel, 230 .data = &dvi_panel,
252 .phy.dpi.data_lines = 24, 231 .phy.dpi.data_lines = 24,
253}; 232};
@@ -630,13 +609,13 @@ static struct regulator_consumer_supply dummy_supplies[] = {
630 609
631static void __init omap3_evm_init(void) 610static void __init omap3_evm_init(void)
632{ 611{
612 struct omap_board_mux *obm;
613
633 omap3_evm_get_revision(); 614 omap3_evm_get_revision();
634 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 615 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
635 616
636 if (cpu_is_omap3630()) 617 obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
637 omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB); 618 omap3_mux_init(obm, OMAP_PACKAGE_CBB);
638 else
639 omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
640 619
641 omap_board_config = omap3_evm_config; 620 omap_board_config = omap3_evm_config;
642 omap_board_config_size = ARRAY_SIZE(omap3_evm_config); 621 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 9b3c141ff51b..c008bf8e1c36 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -4,8 +4,9 @@
4 * Copyright (C) 2010 Li-Pro.Net 4 * Copyright (C) 2010 Li-Pro.Net
5 * Stephan Linz <linz@li-pro.net> 5 * Stephan Linz <linz@li-pro.net>
6 * 6 *
7 * Copyright (C) 2010 Logic Product Development, Inc. 7 * Copyright (C) 2010-2012 Logic Product Development, Inc.
8 * Peter Barada <peter.barada@logicpd.com> 8 * Peter Barada <peter.barada@logicpd.com>
9 * Ashwin BIhari <ashwin.bihari@logicpd.com>
9 * 10 *
10 * Modified from Beagle, EVM, and RX51 11 * Modified from Beagle, EVM, and RX51
11 * 12 *
@@ -45,6 +46,7 @@
45#include <plat/gpmc-smsc911x.h> 46#include <plat/gpmc-smsc911x.h>
46#include <plat/gpmc.h> 47#include <plat/gpmc.h>
47#include <plat/sdrc.h> 48#include <plat/sdrc.h>
49#include <plat/usb.h>
48 50
49#define OMAP3LOGIC_SMSC911X_CS 1 51#define OMAP3LOGIC_SMSC911X_CS 1
50 52
@@ -85,6 +87,11 @@ static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
85 | BIT(13) | BIT(15) | BIT(16) | BIT(17), 87 | BIT(13) | BIT(15) | BIT(16) | BIT(17),
86}; 88};
87 89
90static struct twl4030_usb_data omap3logic_usb_data = {
91 .usb_mode = T2_USB_MODE_ULPI,
92};
93
94
88static struct twl4030_platform_data omap3logic_twldata = { 95static struct twl4030_platform_data omap3logic_twldata = {
89 .irq_base = TWL4030_IRQ_BASE, 96 .irq_base = TWL4030_IRQ_BASE,
90 .irq_end = TWL4030_IRQ_END, 97 .irq_end = TWL4030_IRQ_END,
@@ -92,6 +99,7 @@ static struct twl4030_platform_data omap3logic_twldata = {
92 /* platform_data for children goes here */ 99 /* platform_data for children goes here */
93 .gpio = &omap3logic_gpio_data, 100 .gpio = &omap3logic_gpio_data,
94 .vmmc1 = &omap3logic_vmmc1, 101 .vmmc1 = &omap3logic_vmmc1,
102 .usb = &omap3logic_usb_data,
95}; 103};
96 104
97static int __init omap3logic_i2c_init(void) 105static int __init omap3logic_i2c_init(void)
@@ -185,6 +193,20 @@ static inline void __init board_smsc911x_init(void)
185 193
186#ifdef CONFIG_OMAP_MUX 194#ifdef CONFIG_OMAP_MUX
187static struct omap_board_mux board_mux[] __initdata = { 195static struct omap_board_mux board_mux[] __initdata = {
196 /* mUSB */
197 OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
198 OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
199 OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
200 OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
201 OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
202 OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
203 OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
204 OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
205 OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
206 OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
207 OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
208 OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
209
188 { .reg_offset = OMAP_MUX_TERMINATOR }, 210 { .reg_offset = OMAP_MUX_TERMINATOR },
189}; 211};
190#endif 212#endif
@@ -205,6 +227,8 @@ static void __init omap3logic_init(void)
205 board_mmc_init(); 227 board_mmc_init();
206 board_smsc911x_init(); 228 board_smsc911x_init();
207 229
230 usb_musb_init(NULL);
231
208 /* Ensure SDRC pins are mux'd for self-refresh */ 232 /* Ensure SDRC pins are mux'd for self-refresh */
209 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); 233 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
210 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); 234 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 4dffc95bddd2..4396bae91677 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -42,7 +42,7 @@
42#include <plat/usb.h> 42#include <plat/usb.h>
43#include <video/omapdss.h> 43#include <video/omapdss.h>
44#include <video/omap-panel-generic-dpi.h> 44#include <video/omap-panel-generic-dpi.h>
45#include <video/omap-panel-dvi.h> 45#include <video/omap-panel-tfp410.h>
46 46
47#include <plat/mcspi.h> 47#include <plat/mcspi.h>
48#include <linux/input/matrix_keypad.h> 48#include <linux/input/matrix_keypad.h>
@@ -92,9 +92,6 @@ static inline void __init omap3stalker_init_eth(void)
92#define LCD_PANEL_BKLIGHT_GPIO 210 92#define LCD_PANEL_BKLIGHT_GPIO 210
93#define ENABLE_VPLL2_DEV_GRP 0xE0 93#define ENABLE_VPLL2_DEV_GRP 0xE0
94 94
95static int lcd_enabled;
96static int dvi_enabled;
97
98static void __init omap3_stalker_display_init(void) 95static void __init omap3_stalker_display_init(void)
99{ 96{
100 return; 97 return;
@@ -122,32 +119,14 @@ static struct omap_dss_device omap3_stalker_tv_device = {
122 .platform_disable = omap3_stalker_disable_tv, 119 .platform_disable = omap3_stalker_disable_tv,
123}; 120};
124 121
125static int omap3_stalker_enable_dvi(struct omap_dss_device *dssdev) 122static struct tfp410_platform_data dvi_panel = {
126{ 123 .power_down_gpio = DSS_ENABLE_GPIO,
127 if (lcd_enabled) {
128 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
129 return -EINVAL;
130 }
131 gpio_set_value(DSS_ENABLE_GPIO, 1);
132 dvi_enabled = 1;
133 return 0;
134}
135
136static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev)
137{
138 gpio_set_value(DSS_ENABLE_GPIO, 0);
139 dvi_enabled = 0;
140}
141
142static struct panel_dvi_platform_data dvi_panel = {
143 .platform_enable = omap3_stalker_enable_dvi,
144 .platform_disable = omap3_stalker_disable_dvi,
145}; 124};
146 125
147static struct omap_dss_device omap3_stalker_dvi_device = { 126static struct omap_dss_device omap3_stalker_dvi_device = {
148 .name = "dvi", 127 .name = "dvi",
149 .type = OMAP_DISPLAY_TYPE_DPI, 128 .type = OMAP_DISPLAY_TYPE_DPI,
150 .driver_name = "dvi", 129 .driver_name = "tfp410",
151 .data = &dvi_panel, 130 .data = &dvi_panel,
152 .phy.dpi.data_lines = 24, 131 .phy.dpi.data_lines = 24,
153}; 132};
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 1b782ba53433..68b8fc9ff010 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -28,6 +28,7 @@
28#include <linux/mfd/twl6040.h> 28#include <linux/mfd/twl6040.h>
29#include <linux/regulator/machine.h> 29#include <linux/regulator/machine.h>
30#include <linux/regulator/fixed.h> 30#include <linux/regulator/fixed.h>
31#include <linux/ti_wilink_st.h>
31#include <linux/wl12xx.h> 32#include <linux/wl12xx.h>
32#include <linux/platform_data/omap-abe-twl6040.h> 33#include <linux/platform_data/omap-abe-twl6040.h>
33 34
@@ -42,7 +43,7 @@
42#include "common.h" 43#include "common.h"
43#include <plat/usb.h> 44#include <plat/usb.h>
44#include <plat/mmc.h> 45#include <plat/mmc.h>
45#include <video/omap-panel-dvi.h> 46#include <video/omap-panel-tfp410.h>
46 47
47#include "hsmmc.h" 48#include "hsmmc.h"
48#include "control.h" 49#include "control.h"
@@ -58,12 +59,21 @@
58#define HDMI_GPIO_HPD 63 /* Hotplug detect */ 59#define HDMI_GPIO_HPD 63 /* Hotplug detect */
59 60
60/* wl127x BT, FM, GPS connectivity chip */ 61/* wl127x BT, FM, GPS connectivity chip */
61static int wl1271_gpios[] = {46, -1, -1}; 62static struct ti_st_plat_data wilink_platform_data = {
63 .nshutdown_gpio = 46,
64 .dev_name = "/dev/ttyO1",
65 .flow_cntrl = 1,
66 .baud_rate = 3000000,
67 .chip_enable = NULL,
68 .suspend = NULL,
69 .resume = NULL,
70};
71
62static struct platform_device wl1271_device = { 72static struct platform_device wl1271_device = {
63 .name = "kim", 73 .name = "kim",
64 .id = -1, 74 .id = -1,
65 .dev = { 75 .dev = {
66 .platform_data = &wl1271_gpios, 76 .platform_data = &wilink_platform_data,
67 }, 77 },
68}; 78};
69 79
@@ -117,6 +127,11 @@ static struct platform_device panda_abe_audio = {
117 }, 127 },
118}; 128};
119 129
130static struct platform_device panda_hdmi_audio_codec = {
131 .name = "hdmi-audio-codec",
132 .id = -1,
133};
134
120static struct platform_device btwilink_device = { 135static struct platform_device btwilink_device = {
121 .name = "btwilink", 136 .name = "btwilink",
122 .id = -1, 137 .id = -1,
@@ -126,6 +141,7 @@ static struct platform_device *panda_devices[] __initdata = {
126 &leds_gpio, 141 &leds_gpio,
127 &wl1271_device, 142 &wl1271_device,
128 &panda_abe_audio, 143 &panda_abe_audio,
144 &panda_hdmi_audio_codec,
129 &btwilink_device, 145 &btwilink_device,
130}; 146};
131 147
@@ -231,60 +247,11 @@ static struct platform_device omap_vwlan_device = {
231 }, 247 },
232}; 248};
233 249
234struct wl12xx_platform_data omap_panda_wlan_data __initdata = { 250static struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
235 /* PANDA ref clock is 38.4 MHz */ 251 /* PANDA ref clock is 38.4 MHz */
236 .board_ref_clock = 2, 252 .board_ref_clock = 2,
237}; 253};
238 254
239static int omap4_twl6030_hsmmc_late_init(struct device *dev)
240{
241 int irq = 0;
242 struct platform_device *pdev = container_of(dev,
243 struct platform_device, dev);
244 struct omap_mmc_platform_data *pdata = dev->platform_data;
245
246 if (!pdata) {
247 dev_err(dev, "%s: NULL platform data\n", __func__);
248 return -EINVAL;
249 }
250 /* Setting MMC1 Card detect Irq */
251 if (pdev->id == 0) {
252 irq = twl6030_mmc_card_detect_config();
253 if (irq < 0) {
254 dev_err(dev, "%s: Error card detect config(%d)\n",
255 __func__, irq);
256 return irq;
257 }
258 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
259 }
260 return 0;
261}
262
263static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
264{
265 struct omap_mmc_platform_data *pdata;
266
267 /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
268 if (!dev) {
269 pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
270 return;
271 }
272 pdata = dev->platform_data;
273
274 pdata->init = omap4_twl6030_hsmmc_late_init;
275}
276
277static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
278{
279 struct omap2_hsmmc_info *c;
280
281 omap_hsmmc_init(controllers);
282 for (c = controllers; c->mmc; c++)
283 omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
284
285 return 0;
286}
287
288static struct twl6040_codec_data twl6040_codec = { 255static struct twl6040_codec_data twl6040_codec = {
289 /* single-step ramp for headset and handsfree */ 256 /* single-step ramp for headset and handsfree */
290 .hs_left_step = 0x0f, 257 .hs_left_step = 0x0f,
@@ -323,7 +290,9 @@ static int __init omap4_panda_i2c_init(void)
323 TWL_COMMON_REGULATOR_VANA | 290 TWL_COMMON_REGULATOR_VANA |
324 TWL_COMMON_REGULATOR_VCXIO | 291 TWL_COMMON_REGULATOR_VCXIO |
325 TWL_COMMON_REGULATOR_VUSB | 292 TWL_COMMON_REGULATOR_VUSB |
326 TWL_COMMON_REGULATOR_CLK32KG); 293 TWL_COMMON_REGULATOR_CLK32KG |
294 TWL_COMMON_REGULATOR_V1V8 |
295 TWL_COMMON_REGULATOR_V2V1);
327 omap4_pmic_init("twl6030", &omap4_panda_twldata, 296 omap4_pmic_init("twl6030", &omap4_panda_twldata,
328 &twl6040_data, OMAP44XX_IRQ_SYS_2N); 297 &twl6040_data, OMAP44XX_IRQ_SYS_2N);
329 omap_register_i2c_bus(2, 400, NULL, 0); 298 omap_register_i2c_bus(2, 400, NULL, 0);
@@ -420,47 +389,22 @@ static struct omap_board_mux board_mux[] __initdata = {
420/* Display DVI */ 389/* Display DVI */
421#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0 390#define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0
422 391
423static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev)
424{
425 gpio_set_value(dssdev->reset_gpio, 1);
426 return 0;
427}
428
429static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev)
430{
431 gpio_set_value(dssdev->reset_gpio, 0);
432}
433
434/* Using generic display panel */ 392/* Using generic display panel */
435static struct panel_dvi_platform_data omap4_dvi_panel = { 393static struct tfp410_platform_data omap4_dvi_panel = {
436 .platform_enable = omap4_panda_enable_dvi, 394 .i2c_bus_num = 3,
437 .platform_disable = omap4_panda_disable_dvi, 395 .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
438 .i2c_bus_num = 3,
439}; 396};
440 397
441struct omap_dss_device omap4_panda_dvi_device = { 398static struct omap_dss_device omap4_panda_dvi_device = {
442 .type = OMAP_DISPLAY_TYPE_DPI, 399 .type = OMAP_DISPLAY_TYPE_DPI,
443 .name = "dvi", 400 .name = "dvi",
444 .driver_name = "dvi", 401 .driver_name = "tfp410",
445 .data = &omap4_dvi_panel, 402 .data = &omap4_dvi_panel,
446 .phy.dpi.data_lines = 24, 403 .phy.dpi.data_lines = 24,
447 .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, 404 .reset_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
448 .channel = OMAP_DSS_CHANNEL_LCD2, 405 .channel = OMAP_DSS_CHANNEL_LCD2,
449}; 406};
450 407
451int __init omap4_panda_dvi_init(void)
452{
453 int r;
454
455 /* Requesting TFP410 DVI GPIO and disabling it, at bootup */
456 r = gpio_request_one(omap4_panda_dvi_device.reset_gpio,
457 GPIOF_OUT_INIT_LOW, "DVI PD");
458 if (r)
459 pr_err("Failed to get DVI powerdown GPIO\n");
460
461 return r;
462}
463
464static struct gpio panda_hdmi_gpios[] = { 408static struct gpio panda_hdmi_gpios[] = {
465 { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" }, 409 { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
466 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" }, 410 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
@@ -509,13 +453,8 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
509 .default_device = &omap4_panda_dvi_device, 453 .default_device = &omap4_panda_dvi_device,
510}; 454};
511 455
512void __init omap4_panda_display_init(void) 456static void __init omap4_panda_display_init(void)
513{ 457{
514 int r;
515
516 r = omap4_panda_dvi_init();
517 if (r)
518 pr_err("error initializing panda DVI\n");
519 458
520 omap_display_init(&omap4_panda_dss_data); 459 omap_display_init(&omap4_panda_dss_data);
521 460
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 33aa3910b09e..5527c1979a16 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -46,7 +46,7 @@
46#include "common.h" 46#include "common.h"
47#include <video/omapdss.h> 47#include <video/omapdss.h>
48#include <video/omap-panel-generic-dpi.h> 48#include <video/omap-panel-generic-dpi.h>
49#include <video/omap-panel-dvi.h> 49#include <video/omap-panel-tfp410.h>
50#include <plat/gpmc.h> 50#include <plat/gpmc.h>
51#include <mach/hardware.h> 51#include <mach/hardware.h>
52#include <plat/nand.h> 52#include <plat/nand.h>
@@ -167,32 +167,15 @@ static void __init overo_display_init(void)
167 gpio_export(OVERO_GPIO_LCD_BL, 0); 167 gpio_export(OVERO_GPIO_LCD_BL, 0);
168} 168}
169 169
170static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) 170static struct tfp410_platform_data dvi_panel = {
171{
172 if (lcd_enabled) {
173 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
174 return -EINVAL;
175 }
176 dvi_enabled = 1;
177
178 return 0;
179}
180
181static void overo_panel_disable_dvi(struct omap_dss_device *dssdev)
182{
183 dvi_enabled = 0;
184}
185
186static struct panel_dvi_platform_data dvi_panel = {
187 .platform_enable = overo_panel_enable_dvi,
188 .platform_disable = overo_panel_disable_dvi,
189 .i2c_bus_num = 3, 171 .i2c_bus_num = 3,
172 .power_down_gpio = -1,
190}; 173};
191 174
192static struct omap_dss_device overo_dvi_device = { 175static struct omap_dss_device overo_dvi_device = {
193 .name = "dvi", 176 .name = "dvi",
194 .type = OMAP_DISPLAY_TYPE_DPI, 177 .type = OMAP_DISPLAY_TYPE_DPI,
195 .driver_name = "dvi", 178 .driver_name = "tfp410",
196 .data = &dvi_panel, 179 .data = &dvi_panel,
197 .phy.dpi.data_lines = 24, 180 .phy.dpi.data_lines = 24,
198}; 181};
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index d87ee0612098..ff53deccecab 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -44,6 +44,7 @@
44#include <linux/leds-lp5523.h> 44#include <linux/leds-lp5523.h>
45 45
46#include <../drivers/staging/iio/light/tsl2563.h> 46#include <../drivers/staging/iio/light/tsl2563.h>
47#include <linux/lis3lv02d.h>
47 48
48#include "mux.h" 49#include "mux.h"
49#include "hsmmc.h" 50#include "hsmmc.h"
@@ -63,6 +64,9 @@
63#define RX51_TSC2005_RESET_GPIO 104 64#define RX51_TSC2005_RESET_GPIO 104
64#define RX51_TSC2005_IRQ_GPIO 100 65#define RX51_TSC2005_IRQ_GPIO 100
65 66
67#define LIS302_IRQ1_GPIO 181
68#define LIS302_IRQ2_GPIO 180 /* Not yet in use */
69
66/* list all spi devices here */ 70/* list all spi devices here */
67enum { 71enum {
68 RX51_SPI_WL1251, 72 RX51_SPI_WL1251,
@@ -73,6 +77,77 @@ enum {
73static struct wl12xx_platform_data wl1251_pdata; 77static struct wl12xx_platform_data wl1251_pdata;
74static struct tsc2005_platform_data tsc2005_pdata; 78static struct tsc2005_platform_data tsc2005_pdata;
75 79
80#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
81static int lis302_setup(void)
82{
83 int err;
84 int irq1 = LIS302_IRQ1_GPIO;
85 int irq2 = LIS302_IRQ2_GPIO;
86
87 /* gpio for interrupt pin 1 */
88 err = gpio_request(irq1, "lis3lv02dl_irq1");
89 if (err) {
90 printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
91 goto out;
92 }
93
94 /* gpio for interrupt pin 2 */
95 err = gpio_request(irq2, "lis3lv02dl_irq2");
96 if (err) {
97 gpio_free(irq1);
98 printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
99 goto out;
100 }
101
102 gpio_direction_input(irq1);
103 gpio_direction_input(irq2);
104
105out:
106 return err;
107}
108
109static int lis302_release(void)
110{
111 gpio_free(LIS302_IRQ1_GPIO);
112 gpio_free(LIS302_IRQ2_GPIO);
113
114 return 0;
115}
116
117static struct lis3lv02d_platform_data rx51_lis3lv02d_data = {
118 .click_flags = LIS3_CLICK_SINGLE_X | LIS3_CLICK_SINGLE_Y |
119 LIS3_CLICK_SINGLE_Z,
120 /* Limits are 0.5g * value */
121 .click_thresh_x = 8,
122 .click_thresh_y = 8,
123 .click_thresh_z = 10,
124 /* Click must be longer than time limit */
125 .click_time_limit = 9,
126 /* Kind of debounce filter */
127 .click_latency = 50,
128
129 /* Limits for all axis. millig-value / 18 to get HW values */
130 .wakeup_flags = LIS3_WAKEUP_X_HI | LIS3_WAKEUP_Y_HI,
131 .wakeup_thresh = 800 / 18,
132 .wakeup_flags2 = LIS3_WAKEUP_Z_HI ,
133 .wakeup_thresh2 = 900 / 18,
134
135 .hipass_ctrl = LIS3_HIPASS1_DISABLE | LIS3_HIPASS2_DISABLE,
136
137 /* Interrupt line 2 for click detection, line 1 for thresholds */
138 .irq_cfg = LIS3_IRQ2_CLICK | LIS3_IRQ1_FF_WU_12,
139
140 .axis_x = LIS3_DEV_X,
141 .axis_y = LIS3_INV_DEV_Y,
142 .axis_z = LIS3_INV_DEV_Z,
143 .setup_resources = lis302_setup,
144 .release_resources = lis302_release,
145 .st_min_limits = {-32, 3, 3},
146 .st_max_limits = {-3, 32, 32},
147 .irq2 = OMAP_GPIO_IRQ(LIS302_IRQ2_GPIO),
148};
149#endif
150
76#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) 151#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
77static struct tsl2563_platform_data rx51_tsl2563_platform_data = { 152static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
78 .cover_comp_gain = 16, 153 .cover_comp_gain = 16,
@@ -872,11 +947,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
872 .resource_config = twl4030_rconfig, 947 .resource_config = twl4030_rconfig,
873}; 948};
874 949
875struct twl4030_vibra_data rx51_vibra_data __initdata = { 950static struct twl4030_vibra_data rx51_vibra_data __initdata = {
876 .coexist = 0, 951 .coexist = 0,
877}; 952};
878 953
879struct twl4030_audio_data rx51_audio_data __initdata = { 954static struct twl4030_audio_data rx51_audio_data __initdata = {
880 .audio_mclk = 26000000, 955 .audio_mclk = 26000000,
881 .vibra = &rx51_vibra_data, 956 .vibra = &rx51_vibra_data,
882}; 957};
@@ -950,6 +1025,16 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
950 } 1025 }
951}; 1026};
952 1027
1028static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
1029#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
1030 {
1031 I2C_BOARD_INFO("lis3lv02d", 0x1d),
1032 .platform_data = &rx51_lis3lv02d_data,
1033 .irq = OMAP_GPIO_IRQ(LIS302_IRQ1_GPIO),
1034 },
1035#endif
1036};
1037
953static int __init rx51_i2c_init(void) 1038static int __init rx51_i2c_init(void)
954{ 1039{
955 if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) || 1040 if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
@@ -971,7 +1056,8 @@ static int __init rx51_i2c_init(void)
971 omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata); 1056 omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
972 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2, 1057 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
973 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2)); 1058 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
974 omap_register_i2c_bus(3, 400, NULL, 0); 1059 omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3,
1060 ARRAY_SIZE(rx51_peripherals_i2c_board_info_3));
975 return 0; 1061 return 0;
976} 1062}
977 1063
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 27f01f051dff..2da92a6ba40a 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -59,25 +59,24 @@ static struct platform_device leds_gpio = {
59}; 59};
60 60
61/* 61/*
62 * cpuidle C-states definition override from the default values. 62 * cpuidle C-states definition for rx51.
63 * The 'exit_latency' field is the sum of sleep and wake-up latencies. 63 *
64 */ 64 * The 'exit_latency' field is the sum of sleep
65static struct cpuidle_params rx51_cpuidle_params[] = { 65 * and wake-up latencies.
66 /* C1 */ 66
67 {110 + 162, 5 , 1}, 67 ---------------------------------------------
68 /* C2 */ 68 | state | exit_latency | target_residency |
69 {106 + 180, 309, 1}, 69 ---------------------------------------------
70 /* C3 */ 70 | C1 | 110 + 162 | 5 |
71 {107 + 410, 46057, 0}, 71 | C2 | 106 + 180 | 309 |
72 /* C4 */ 72 | C3 | 107 + 410 | 46057 |
73 {121 + 3374, 46057, 0}, 73 | C4 | 121 + 3374 | 46057 |
74 /* C5 */ 74 | C5 | 855 + 1146 | 46057 |
75 {855 + 1146, 46057, 1}, 75 | C6 | 7580 + 4134 | 484329 |
76 /* C6 */ 76 | C7 | 7505 + 15274 | 484329 |
77 {7580 + 4134, 484329, 0}, 77 ---------------------------------------------
78 /* C7 */ 78
79 {7505 + 15274, 484329, 1}, 79*/
80};
81 80
82extern void __init rx51_peripherals_init(void); 81extern void __init rx51_peripherals_init(void);
83 82
@@ -98,7 +97,6 @@ static void __init rx51_init(void)
98 struct omap_sdrc_params *sdrc_params; 97 struct omap_sdrc_params *sdrc_params;
99 98
100 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 99 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
101 omap3_pm_init_cpuidle(rx51_cpuidle_params);
102 omap_serial_init(); 100 omap_serial_init();
103 101
104 sdrc_params = nokia_get_sdram_timings(); 102 sdrc_params = nokia_get_sdram_timings();
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index a43a765dd092..28187f134fff 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -16,6 +16,7 @@
16#include <linux/spi/spi.h> 16#include <linux/spi/spi.h>
17#include <plat/mcspi.h> 17#include <plat/mcspi.h>
18#include <video/omapdss.h> 18#include <video/omapdss.h>
19#include <mach/board-zoom.h>
19 20
20#define LCD_PANEL_RESET_GPIO_PROD 96 21#define LCD_PANEL_RESET_GPIO_PROD 96
21#define LCD_PANEL_RESET_GPIO_PILOT 55 22#define LCD_PANEL_RESET_GPIO_PILOT 55
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d9f4931513f9..5c4e66542169 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk)
439 clk->ops->disable(clk); 439 clk->ops->disable(clk);
440 } 440 }
441 if (clk->clkdm != NULL) 441 if (clk->clkdm != NULL)
442 pwrdm_clkdm_state_switch(clk->clkdm); 442 pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
443} 443}
444#endif 444#endif
445 445
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index f4a626f7c79e..4e1a3b0e8cc8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP3 clock data 2 * OMAP3 clock data
3 * 3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc. 4 * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
@@ -1640,6 +1640,7 @@ static struct clk hdq_fck = {
1640 .name = "hdq_fck", 1640 .name = "hdq_fck",
1641 .ops = &clkops_omap2_dflt_wait, 1641 .ops = &clkops_omap2_dflt_wait,
1642 .parent = &core_12m_fck, 1642 .parent = &core_12m_fck,
1643 .clkdm_name = "core_l4_clkdm",
1643 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1644 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1645 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1645 .recalc = &followparent_recalc, 1646 .recalc = &followparent_recalc,
@@ -3294,8 +3295,8 @@ static struct omap_clk omap3xxx_clks[] = {
3294 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), 3295 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3295 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), 3296 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3296 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), 3297 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3297 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX), 3298 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3298 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX), 3299 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3299 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), 3300 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3300 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), 3301 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3301 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), 3302 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
@@ -3419,7 +3420,7 @@ static struct omap_clk omap3xxx_clks[] = {
3419 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), 3420 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3420 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), 3421 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3421 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), 3422 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3422 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517), 3423 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
3423 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), 3424 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3424 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), 3425 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3425 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), 3426 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
@@ -3513,21 +3514,9 @@ int __init omap3xxx_clk_init(void)
3513 struct omap_clk *c; 3514 struct omap_clk *c;
3514 u32 cpu_clkflg = 0; 3515 u32 cpu_clkflg = 0;
3515 3516
3516 /* 3517 if (cpu_is_omap3517()) {
3517 * 3505 must be tested before 3517, since 3517 returns true
3518 * for both AM3517 chips and AM3517 family chips, which
3519 * includes 3505. Unfortunately there's no obvious family
3520 * test for 3517/3505 :-(
3521 */
3522 if (cpu_is_omap3505()) {
3523 cpu_mask = RATE_IN_34XX;
3524 cpu_clkflg = CK_3505;
3525 } else if (cpu_is_omap3517()) {
3526 cpu_mask = RATE_IN_34XX;
3527 cpu_clkflg = CK_3517;
3528 } else if (cpu_is_omap3505()) {
3529 cpu_mask = RATE_IN_34XX; 3518 cpu_mask = RATE_IN_34XX;
3530 cpu_clkflg = CK_3505; 3519 cpu_clkflg = CK_AM35XX;
3531 } else if (cpu_is_omap3630()) { 3520 } else if (cpu_is_omap3630()) {
3532 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); 3521 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3533 cpu_clkflg = CK_36XX; 3522 cpu_clkflg = CK_36XX;
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index fa6ea65ad44b..2172f6603848 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3355,17 +3355,6 @@ static struct omap_clk omap44xx_clks[] = {
3355 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), 3355 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3356 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), 3356 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3357 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 3357 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3358 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
3359 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
3360 CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
3361 CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
3362 CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
3363 CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
3364 CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
3365 CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
3366 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
3367 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
3368 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
3369 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), 3358 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
3370 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 3359 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3371 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 3360 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ad07689e1563..8664f5a8bfb6 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
840 spin_lock_irqsave(&clkdm->lock, flags); 840 spin_lock_irqsave(&clkdm->lock, flags);
841 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED; 841 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
842 arch_clkdm->clkdm_allow_idle(clkdm); 842 arch_clkdm->clkdm_allow_idle(clkdm);
843 pwrdm_clkdm_state_switch(clkdm); 843 pwrdm_state_switch(clkdm->pwrdm.ptr);
844 spin_unlock_irqrestore(&clkdm->lock, flags); 844 spin_unlock_irqrestore(&clkdm->lock, flags);
845} 845}
846 846
@@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
924 924
925 spin_lock_irqsave(&clkdm->lock, flags); 925 spin_lock_irqsave(&clkdm->lock, flags);
926 arch_clkdm->clkdm_clk_enable(clkdm); 926 arch_clkdm->clkdm_clk_enable(clkdm);
927 pwrdm_wait_transition(clkdm->pwrdm.ptr); 927 pwrdm_state_switch(clkdm->pwrdm.ptr);
928 pwrdm_clkdm_state_switch(clkdm);
929 spin_unlock_irqrestore(&clkdm->lock, flags); 928 spin_unlock_irqrestore(&clkdm->lock, flags);
930 929
931 pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name); 930 pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
@@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
950 949
951 spin_lock_irqsave(&clkdm->lock, flags); 950 spin_lock_irqsave(&clkdm->lock, flags);
952 arch_clkdm->clkdm_clk_disable(clkdm); 951 arch_clkdm->clkdm_clk_disable(clkdm);
953 pwrdm_clkdm_state_switch(clkdm); 952 pwrdm_state_switch(clkdm->pwrdm.ptr);
954 spin_unlock_irqrestore(&clkdm->lock, flags); 953 spin_unlock_irqrestore(&clkdm->lock, flags);
955 954
956 pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name); 955 pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 935c7f03dab9..4f04dd11d655 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -51,6 +51,9 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
51 struct clkdm_dep *cd; 51 struct clkdm_dep *cd;
52 u32 mask = 0; 52 u32 mask = 0;
53 53
54 if (!clkdm->prcm_partition)
55 return 0;
56
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { 57 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!cd->clkdm) 58 if (!cd->clkdm)
56 continue; /* only happens if data is erroneous */ 59 continue; /* only happens if data is erroneous */
@@ -103,6 +106,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
103{ 106{
104 bool hwsup = false; 107 bool hwsup = false;
105 108
109 if (!clkdm->prcm_partition)
110 return 0;
111
106 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, 112 hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
107 clkdm->cm_inst, clkdm->clkdm_offs); 113 clkdm->cm_inst, clkdm->clkdm_offs);
108 114
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 0a6a04897d89..839145e1cfbe 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -89,13 +89,3 @@ struct clockdomain wkup_common_clkdm = {
89 .pwrdm = { .name = "wkup_pwrdm" }, 89 .pwrdm = { .name = "wkup_pwrdm" },
90 .dep_bit = OMAP_EN_WKUP_SHIFT, 90 .dep_bit = OMAP_EN_WKUP_SHIFT,
91}; 91};
92
93struct clockdomain prm_common_clkdm = {
94 .name = "prm_clkdm",
95 .pwrdm = { .name = "wkup_pwrdm" },
96};
97
98struct clockdomain cm_common_clkdm = {
99 .name = "cm_clkdm",
100 .pwrdm = { .name = "core_pwrdm" },
101};
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index b84e138d99c8..6038adb97710 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -53,9 +53,9 @@
53 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE 53 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
54 */ 54 */
55static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = { 55static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
56 { .clkdm_name = "iva2_clkdm", }, 56 { .clkdm_name = "iva2_clkdm" },
57 { .clkdm_name = "mpu_clkdm", }, 57 { .clkdm_name = "mpu_clkdm" },
58 { .clkdm_name = "wkup_clkdm", }, 58 { .clkdm_name = "wkup_clkdm" },
59 { NULL }, 59 { NULL },
60}; 60};
61 61
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index bd7ed13515cc..c53425847493 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -430,6 +430,8 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
430 &l4_wkup_44xx_clkdm, 430 &l4_wkup_44xx_clkdm,
431 &emu_sys_44xx_clkdm, 431 &emu_sys_44xx_clkdm,
432 &l3_dma_44xx_clkdm, 432 &l3_dma_44xx_clkdm,
433 &prm_common_clkdm,
434 &cm_common_clkdm,
433 NULL 435 NULL
434}; 436};
435 437
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
new file mode 100644
index 000000000000..615b1f04967d
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains_common_data.c
@@ -0,0 +1,24 @@
1/*
2 * OMAP2+-common clockdomain data
3 *
4 * Copyright (C) 2008-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Paul Walmsley, Jouni Högander
8 */
9
10#include <linux/kernel.h>
11#include <linux/io.h>
12
13#include "clockdomain.h"
14
15/* These are implicit clockdomains - they are never defined as such in TRM */
16struct clockdomain prm_common_clkdm = {
17 .name = "prm_clkdm",
18 .pwrdm = { .name = "wkup_pwrdm" },
19};
20
21struct clockdomain cm_common_clkdm = {
22 .name = "cm_clkdm",
23 .pwrdm = { .name = "core_pwrdm" },
24};
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index b91275908f33..8083a8cdc55f 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -79,7 +79,7 @@
79 79
80/* CM_CLKSEL1_PLL_IVA2 */ 80/* CM_CLKSEL1_PLL_IVA2 */
81#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 81#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
82#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 82#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
83#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 83#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
84#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 84#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
85#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 85#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
@@ -124,7 +124,7 @@
124 124
125/* CM_CLKSEL1_PLL_MPU */ 125/* CM_CLKSEL1_PLL_MPU */
126#define OMAP3430_MPU_CLK_SRC_SHIFT 19 126#define OMAP3430_MPU_CLK_SRC_SHIFT 19
127#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 127#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
128#define OMAP3430_MPU_DPLL_MULT_SHIFT 8 128#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
129#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 129#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
130#define OMAP3430_MPU_DPLL_DIV_SHIFT 0 130#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index bd8810c3753f..8c86d294b1a3 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -32,6 +32,7 @@
32#include "prcm44xx.h" 32#include "prcm44xx.h"
33#include "prm44xx.h" 33#include "prm44xx.h"
34#include "prcm_mpu44xx.h" 34#include "prcm_mpu44xx.h"
35#include "prcm-common.h"
35 36
36/* 37/*
37 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 38 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
@@ -49,14 +50,21 @@
49#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 50#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
50#define CLKCTRL_IDLEST_DISABLED 0x3 51#define CLKCTRL_IDLEST_DISABLED 0x3
51 52
52static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { 53static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
53 [OMAP4430_INVALID_PRCM_PARTITION] = 0, 54
54 [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, 55/**
55 [OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE, 56 * omap_cm_base_init - Populates the cm partitions
56 [OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE, 57 *
57 [OMAP4430_SCRM_PARTITION] = 0, 58 * Populates the base addresses of the _cm_bases
58 [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, 59 * array used for read/write of cm module registers.
59}; 60 */
61void omap_cm_base_init(void)
62{
63 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
64 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
65 _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
66 _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
67}
60 68
61/* Private functions */ 69/* Private functions */
62 70
@@ -106,7 +114,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
106 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 114 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
107 part == OMAP4430_INVALID_PRCM_PARTITION || 115 part == OMAP4430_INVALID_PRCM_PARTITION ||
108 !_cm_bases[part]); 116 !_cm_bases[part]);
109 return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); 117 return __raw_readl(_cm_bases[part] + inst + idx);
110} 118}
111 119
112/* Write into a register in a CM instance */ 120/* Write into a register in a CM instance */
@@ -115,7 +123,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
115 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 123 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
116 part == OMAP4430_INVALID_PRCM_PARTITION || 124 part == OMAP4430_INVALID_PRCM_PARTITION ||
117 !_cm_bases[part]); 125 !_cm_bases[part]);
118 __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); 126 __raw_writel(val, _cm_bases[part] + inst + idx);
119} 127}
120 128
121/* Read-modify-write a register in CM1. Caller must lock */ 129/* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 1549c11000d3..8a6953a34fe2 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -166,6 +166,7 @@ static struct omap_globals omap4_globals = {
166 .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), 166 .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
167 .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), 167 .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
168 .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), 168 .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
169 .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
169}; 170};
170 171
171void __init omap2_set_globals_443x(void) 172void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 57da7f406e28..d6c9e6180318 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -27,6 +27,7 @@
27#ifndef __ASSEMBLER__ 27#ifndef __ASSEMBLER__
28 28
29#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/i2c/twl.h>
30#include <plat/common.h> 31#include <plat/common.h>
31#include <asm/proc-fns.h> 32#include <asm/proc-fns.h>
32 33
@@ -111,6 +112,7 @@ struct omap_globals {
111 void __iomem *prm; /* Power and Reset Management */ 112 void __iomem *prm; /* Power and Reset Management */
112 void __iomem *cm; /* Clock Management */ 113 void __iomem *cm; /* Clock Management */
113 void __iomem *cm2; 114 void __iomem *cm2;
115 void __iomem *prcm_mpu;
114}; 116};
115 117
116void omap2_set_globals_242x(void); 118void omap2_set_globals_242x(void);
@@ -134,8 +136,6 @@ void omap4_map_io(void);
134void ti81xx_map_io(void); 136void ti81xx_map_io(void);
135void omap_barriers_init(void); 137void omap_barriers_init(void);
136 138
137extern void __init omap_init_consistent_dma_size(void);
138
139/** 139/**
140 * omap_test_timeout - busy-loop, testing a condition 140 * omap_test_timeout - busy-loop, testing a condition
141 * @cond: condition to test until it evaluates to true 141 * @cond: condition to test until it evaluates to true
@@ -254,6 +254,8 @@ static inline u32 omap4_mpuss_read_prev_context_state(void)
254struct omap_sdrc_params; 254struct omap_sdrc_params;
255extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 255extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
256 struct omap_sdrc_params *sdrc_cs1); 256 struct omap_sdrc_params *sdrc_cs1);
257struct omap2_hsmmc_info;
258extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
257 259
258#endif /* __ASSEMBLER__ */ 260#endif /* __ASSEMBLER__ */
259#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ 261#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 535866489ce3..207bc1c7759f 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -38,40 +38,44 @@
38 38
39#ifdef CONFIG_CPU_IDLE 39#ifdef CONFIG_CPU_IDLE
40 40
41/*
42 * The latencies/thresholds for various C states have
43 * to be configured from the respective board files.
44 * These are some default values (which might not provide
45 * the best power savings) used on boards which do not
46 * pass these details from the board file.
47 */
48static struct cpuidle_params cpuidle_params_table[] = {
49 /* C1 */
50 {2 + 2, 5, 1},
51 /* C2 */
52 {10 + 10, 30, 1},
53 /* C3 */
54 {50 + 50, 300, 1},
55 /* C4 */
56 {1500 + 1800, 4000, 1},
57 /* C5 */
58 {2500 + 7500, 12000, 1},
59 /* C6 */
60 {3000 + 8500, 15000, 1},
61 /* C7 */
62 {10000 + 30000, 300000, 1},
63};
64#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
65
66/* Mach specific information to be recorded in the C-state driver_data */ 41/* Mach specific information to be recorded in the C-state driver_data */
67struct omap3_idle_statedata { 42struct omap3_idle_statedata {
68 u32 mpu_state; 43 u32 mpu_state;
69 u32 core_state; 44 u32 core_state;
70 u8 valid;
71}; 45};
72struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
73 46
74struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; 47static struct omap3_idle_statedata omap3_idle_data[] = {
48 {
49 .mpu_state = PWRDM_POWER_ON,
50 .core_state = PWRDM_POWER_ON,
51 },
52 {
53 .mpu_state = PWRDM_POWER_ON,
54 .core_state = PWRDM_POWER_ON,
55 },
56 {
57 .mpu_state = PWRDM_POWER_RET,
58 .core_state = PWRDM_POWER_ON,
59 },
60 {
61 .mpu_state = PWRDM_POWER_OFF,
62 .core_state = PWRDM_POWER_ON,
63 },
64 {
65 .mpu_state = PWRDM_POWER_RET,
66 .core_state = PWRDM_POWER_RET,
67 },
68 {
69 .mpu_state = PWRDM_POWER_OFF,
70 .core_state = PWRDM_POWER_RET,
71 },
72 {
73 .mpu_state = PWRDM_POWER_OFF,
74 .core_state = PWRDM_POWER_OFF,
75 },
76};
77
78static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
75 79
76static int _cpuidle_allow_idle(struct powerdomain *pwrdm, 80static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
77 struct clockdomain *clkdm) 81 struct clockdomain *clkdm)
@@ -91,8 +95,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
91 struct cpuidle_driver *drv, 95 struct cpuidle_driver *drv,
92 int index) 96 int index)
93{ 97{
94 struct omap3_idle_statedata *cx = 98 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
95 cpuidle_get_statedata(&dev->states_usage[index]);
96 u32 mpu_state = cx->mpu_state, core_state = cx->core_state; 99 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
97 100
98 local_fiq_disable(); 101 local_fiq_disable();
@@ -169,14 +172,12 @@ static inline int omap3_enter_idle(struct cpuidle_device *dev,
169 * if it satisfies the enable_off_mode condition. 172 * if it satisfies the enable_off_mode condition.
170 */ 173 */
171static int next_valid_state(struct cpuidle_device *dev, 174static int next_valid_state(struct cpuidle_device *dev,
172 struct cpuidle_driver *drv, 175 struct cpuidle_driver *drv, int index)
173 int index)
174{ 176{
175 struct cpuidle_state_usage *curr_usage = &dev->states_usage[index]; 177 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
176 struct cpuidle_state *curr = &drv->states[index];
177 struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
178 u32 mpu_deepest_state = PWRDM_POWER_RET; 178 u32 mpu_deepest_state = PWRDM_POWER_RET;
179 u32 core_deepest_state = PWRDM_POWER_RET; 179 u32 core_deepest_state = PWRDM_POWER_RET;
180 int idx;
180 int next_index = -1; 181 int next_index = -1;
181 182
182 if (enable_off_mode) { 183 if (enable_off_mode) {
@@ -191,45 +192,29 @@ static int next_valid_state(struct cpuidle_device *dev,
191 } 192 }
192 193
193 /* Check if current state is valid */ 194 /* Check if current state is valid */
194 if ((cx->valid) && 195 if ((cx->mpu_state >= mpu_deepest_state) &&
195 (cx->mpu_state >= mpu_deepest_state) && 196 (cx->core_state >= core_deepest_state))
196 (cx->core_state >= core_deepest_state)) {
197 return index; 197 return index;
198 } else {
199 int idx = OMAP3_NUM_STATES - 1;
200
201 /* Reach the current state starting at highest C-state */
202 for (; idx >= 0; idx--) {
203 if (&drv->states[idx] == curr) {
204 next_index = idx;
205 break;
206 }
207 }
208
209 /* Should never hit this condition */
210 WARN_ON(next_index == -1);
211 198
212 /* 199 /*
213 * Drop to next valid state. 200 * Drop to next valid state.
214 * Start search from the next (lower) state. 201 * Start search from the next (lower) state.
215 */ 202 */
216 idx--; 203 for (idx = index - 1; idx >= 0; idx--) {
217 for (; idx >= 0; idx--) { 204 cx = &omap3_idle_data[idx];
218 cx = cpuidle_get_statedata(&dev->states_usage[idx]); 205 if ((cx->mpu_state >= mpu_deepest_state) &&
219 if ((cx->valid) && 206 (cx->core_state >= core_deepest_state)) {
220 (cx->mpu_state >= mpu_deepest_state) && 207 next_index = idx;
221 (cx->core_state >= core_deepest_state)) { 208 break;
222 next_index = idx;
223 break;
224 }
225 } 209 }
226 /*
227 * C1 is always valid.
228 * So, no need to check for 'next_index == -1' outside
229 * this loop.
230 */
231 } 210 }
232 211
212 /*
213 * C1 is always valid.
214 * So, no need to check for 'next_index == -1' outside
215 * this loop.
216 */
217
233 return next_index; 218 return next_index;
234} 219}
235 220
@@ -273,7 +258,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
273 * Prevent PER off if CORE is not in retention or off as this 258 * Prevent PER off if CORE is not in retention or off as this
274 * would disable PER wakeups completely. 259 * would disable PER wakeups completely.
275 */ 260 */
276 cx = cpuidle_get_statedata(&dev->states_usage[index]); 261 cx = &omap3_idle_data[index];
277 core_next_state = cx->core_state; 262 core_next_state = cx->core_state;
278 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); 263 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
279 if ((per_next_state == PWRDM_POWER_OFF) && 264 if ((per_next_state == PWRDM_POWER_OFF) &&
@@ -298,57 +283,71 @@ select_state:
298 283
299DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); 284DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
300 285
301void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
302{
303 int i;
304
305 if (!cpuidle_board_params)
306 return;
307
308 for (i = 0; i < OMAP3_NUM_STATES; i++) {
309 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
310 cpuidle_params_table[i].exit_latency =
311 cpuidle_board_params[i].exit_latency;
312 cpuidle_params_table[i].target_residency =
313 cpuidle_board_params[i].target_residency;
314 }
315 return;
316}
317
318struct cpuidle_driver omap3_idle_driver = { 286struct cpuidle_driver omap3_idle_driver = {
319 .name = "omap3_idle", 287 .name = "omap3_idle",
320 .owner = THIS_MODULE, 288 .owner = THIS_MODULE,
289 .states = {
290 {
291 .enter = omap3_enter_idle,
292 .exit_latency = 2 + 2,
293 .target_residency = 5,
294 .flags = CPUIDLE_FLAG_TIME_VALID,
295 .name = "C1",
296 .desc = "MPU ON + CORE ON",
297 },
298 {
299 .enter = omap3_enter_idle_bm,
300 .exit_latency = 10 + 10,
301 .target_residency = 30,
302 .flags = CPUIDLE_FLAG_TIME_VALID,
303 .name = "C2",
304 .desc = "MPU ON + CORE ON",
305 },
306 {
307 .enter = omap3_enter_idle_bm,
308 .exit_latency = 50 + 50,
309 .target_residency = 300,
310 .flags = CPUIDLE_FLAG_TIME_VALID,
311 .name = "C3",
312 .desc = "MPU RET + CORE ON",
313 },
314 {
315 .enter = omap3_enter_idle_bm,
316 .exit_latency = 1500 + 1800,
317 .target_residency = 4000,
318 .flags = CPUIDLE_FLAG_TIME_VALID,
319 .name = "C4",
320 .desc = "MPU OFF + CORE ON",
321 },
322 {
323 .enter = omap3_enter_idle_bm,
324 .exit_latency = 2500 + 7500,
325 .target_residency = 12000,
326 .flags = CPUIDLE_FLAG_TIME_VALID,
327 .name = "C5",
328 .desc = "MPU RET + CORE RET",
329 },
330 {
331 .enter = omap3_enter_idle_bm,
332 .exit_latency = 3000 + 8500,
333 .target_residency = 15000,
334 .flags = CPUIDLE_FLAG_TIME_VALID,
335 .name = "C6",
336 .desc = "MPU OFF + CORE RET",
337 },
338 {
339 .enter = omap3_enter_idle_bm,
340 .exit_latency = 10000 + 30000,
341 .target_residency = 30000,
342 .flags = CPUIDLE_FLAG_TIME_VALID,
343 .name = "C7",
344 .desc = "MPU OFF + CORE OFF",
345 },
346 },
347 .state_count = ARRAY_SIZE(omap3_idle_data),
348 .safe_state_index = 0,
321}; 349};
322 350
323/* Helper to fill the C-state common data*/
324static inline void _fill_cstate(struct cpuidle_driver *drv,
325 int idx, const char *descr)
326{
327 struct cpuidle_state *state = &drv->states[idx];
328
329 state->exit_latency = cpuidle_params_table[idx].exit_latency;
330 state->target_residency = cpuidle_params_table[idx].target_residency;
331 state->flags = CPUIDLE_FLAG_TIME_VALID;
332 state->enter = omap3_enter_idle_bm;
333 sprintf(state->name, "C%d", idx + 1);
334 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
335
336}
337
338/* Helper to register the driver_data */
339static inline struct omap3_idle_statedata *_fill_cstate_usage(
340 struct cpuidle_device *dev,
341 int idx)
342{
343 struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
344 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
345
346 cx->valid = cpuidle_params_table[idx].valid;
347 cpuidle_set_statedata(state_usage, cx);
348
349 return cx;
350}
351
352/** 351/**
353 * omap3_idle_init - Init routine for OMAP3 idle 352 * omap3_idle_init - Init routine for OMAP3 idle
354 * 353 *
@@ -358,77 +357,20 @@ static inline struct omap3_idle_statedata *_fill_cstate_usage(
358int __init omap3_idle_init(void) 357int __init omap3_idle_init(void)
359{ 358{
360 struct cpuidle_device *dev; 359 struct cpuidle_device *dev;
361 struct cpuidle_driver *drv = &omap3_idle_driver;
362 struct omap3_idle_statedata *cx;
363 360
364 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 361 mpu_pd = pwrdm_lookup("mpu_pwrdm");
365 core_pd = pwrdm_lookup("core_pwrdm"); 362 core_pd = pwrdm_lookup("core_pwrdm");
366 per_pd = pwrdm_lookup("per_pwrdm"); 363 per_pd = pwrdm_lookup("per_pwrdm");
367 cam_pd = pwrdm_lookup("cam_pwrdm"); 364 cam_pd = pwrdm_lookup("cam_pwrdm");
368 365
366 if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
367 return -ENODEV;
369 368
370 drv->safe_state_index = -1;
371 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
372
373 /* C1 . MPU WFI + Core active */
374 _fill_cstate(drv, 0, "MPU ON + CORE ON");
375 (&drv->states[0])->enter = omap3_enter_idle;
376 drv->safe_state_index = 0;
377 cx = _fill_cstate_usage(dev, 0);
378 cx->valid = 1; /* C1 is always valid */
379 cx->mpu_state = PWRDM_POWER_ON;
380 cx->core_state = PWRDM_POWER_ON;
381
382 /* C2 . MPU WFI + Core inactive */
383 _fill_cstate(drv, 1, "MPU ON + CORE ON");
384 cx = _fill_cstate_usage(dev, 1);
385 cx->mpu_state = PWRDM_POWER_ON;
386 cx->core_state = PWRDM_POWER_ON;
387
388 /* C3 . MPU CSWR + Core inactive */
389 _fill_cstate(drv, 2, "MPU RET + CORE ON");
390 cx = _fill_cstate_usage(dev, 2);
391 cx->mpu_state = PWRDM_POWER_RET;
392 cx->core_state = PWRDM_POWER_ON;
393
394 /* C4 . MPU OFF + Core inactive */
395 _fill_cstate(drv, 3, "MPU OFF + CORE ON");
396 cx = _fill_cstate_usage(dev, 3);
397 cx->mpu_state = PWRDM_POWER_OFF;
398 cx->core_state = PWRDM_POWER_ON;
399
400 /* C5 . MPU RET + Core RET */
401 _fill_cstate(drv, 4, "MPU RET + CORE RET");
402 cx = _fill_cstate_usage(dev, 4);
403 cx->mpu_state = PWRDM_POWER_RET;
404 cx->core_state = PWRDM_POWER_RET;
405
406 /* C6 . MPU OFF + Core RET */
407 _fill_cstate(drv, 5, "MPU OFF + CORE RET");
408 cx = _fill_cstate_usage(dev, 5);
409 cx->mpu_state = PWRDM_POWER_OFF;
410 cx->core_state = PWRDM_POWER_RET;
411
412 /* C7 . MPU OFF + Core OFF */
413 _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
414 cx = _fill_cstate_usage(dev, 6);
415 /*
416 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
417 * enable OFF mode in a stable form for previous revisions.
418 * We disable C7 state as a result.
419 */
420 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
421 cx->valid = 0;
422 pr_warn("%s: core off state C7 disabled due to i583\n",
423 __func__);
424 }
425 cx->mpu_state = PWRDM_POWER_OFF;
426 cx->core_state = PWRDM_POWER_OFF;
427
428 drv->state_count = OMAP3_NUM_STATES;
429 cpuidle_register_driver(&omap3_idle_driver); 369 cpuidle_register_driver(&omap3_idle_driver);
430 370
431 dev->state_count = OMAP3_NUM_STATES; 371 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
372 dev->cpu = 0;
373
432 if (cpuidle_register_device(dev)) { 374 if (cpuidle_register_device(dev)) {
433 printk(KERN_ERR "%s: CPUidle register device failed\n", 375 printk(KERN_ERR "%s: CPUidle register device failed\n",
434 __func__); 376 __func__);
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index f386cbe9c889..be1617ca84bd 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -24,26 +24,31 @@
24 24
25#ifdef CONFIG_CPU_IDLE 25#ifdef CONFIG_CPU_IDLE
26 26
27/* Machine specific information to be recorded in the C-state driver_data */ 27/* Machine specific information */
28struct omap4_idle_statedata { 28struct omap4_idle_statedata {
29 u32 cpu_state; 29 u32 cpu_state;
30 u32 mpu_logic_state; 30 u32 mpu_logic_state;
31 u32 mpu_state; 31 u32 mpu_state;
32 u8 valid;
33}; 32};
34 33
35static struct cpuidle_params cpuidle_params_table[] = { 34static struct omap4_idle_statedata omap4_idle_data[] = {
36 /* C1 - CPU0 ON + CPU1 ON + MPU ON */ 35 {
37 {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1}, 36 .cpu_state = PWRDM_POWER_ON,
38 /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */ 37 .mpu_state = PWRDM_POWER_ON,
39 {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1}, 38 .mpu_logic_state = PWRDM_POWER_RET,
40 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ 39 },
41 {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1}, 40 {
41 .cpu_state = PWRDM_POWER_OFF,
42 .mpu_state = PWRDM_POWER_RET,
43 .mpu_logic_state = PWRDM_POWER_RET,
44 },
45 {
46 .cpu_state = PWRDM_POWER_OFF,
47 .mpu_state = PWRDM_POWER_RET,
48 .mpu_logic_state = PWRDM_POWER_OFF,
49 },
42}; 50};
43 51
44#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
45
46struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
47static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd; 52static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
48 53
49/** 54/**
@@ -60,8 +65,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
60 struct cpuidle_driver *drv, 65 struct cpuidle_driver *drv,
61 int index) 66 int index)
62{ 67{
63 struct omap4_idle_statedata *cx = 68 struct omap4_idle_statedata *cx = &omap4_idle_data[index];
64 cpuidle_get_statedata(&dev->states_usage[index]);
65 u32 cpu1_state; 69 u32 cpu1_state;
66 int cpu_id = smp_processor_id(); 70 int cpu_id = smp_processor_id();
67 71
@@ -78,7 +82,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
78 cpu1_state = pwrdm_read_pwrst(cpu1_pd); 82 cpu1_state = pwrdm_read_pwrst(cpu1_pd);
79 if (cpu1_state != PWRDM_POWER_OFF) { 83 if (cpu1_state != PWRDM_POWER_OFF) {
80 index = drv->safe_state_index; 84 index = drv->safe_state_index;
81 cx = cpuidle_get_statedata(&dev->states_usage[index]); 85 cx = &omap4_idle_data[index];
82 } 86 }
83 87
84 if (index > 0) 88 if (index > 0)
@@ -133,36 +137,39 @@ struct cpuidle_driver omap4_idle_driver = {
133 .name = "omap4_idle", 137 .name = "omap4_idle",
134 .owner = THIS_MODULE, 138 .owner = THIS_MODULE,
135 .en_core_tk_irqen = 1, 139 .en_core_tk_irqen = 1,
140 .states = {
141 {
142 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
143 .exit_latency = 2 + 2,
144 .target_residency = 5,
145 .flags = CPUIDLE_FLAG_TIME_VALID,
146 .enter = omap4_enter_idle,
147 .name = "C1",
148 .desc = "MPUSS ON"
149 },
150 {
151 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
152 .exit_latency = 328 + 440,
153 .target_residency = 960,
154 .flags = CPUIDLE_FLAG_TIME_VALID,
155 .enter = omap4_enter_idle,
156 .name = "C2",
157 .desc = "MPUSS CSWR",
158 },
159 {
160 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
161 .exit_latency = 460 + 518,
162 .target_residency = 1100,
163 .flags = CPUIDLE_FLAG_TIME_VALID,
164 .enter = omap4_enter_idle,
165 .name = "C3",
166 .desc = "MPUSS OSWR",
167 },
168 },
169 .state_count = ARRAY_SIZE(omap4_idle_data),
170 .safe_state_index = 0,
136}; 171};
137 172
138static inline void _fill_cstate(struct cpuidle_driver *drv,
139 int idx, const char *descr)
140{
141 struct cpuidle_state *state = &drv->states[idx];
142
143 state->exit_latency = cpuidle_params_table[idx].exit_latency;
144 state->target_residency = cpuidle_params_table[idx].target_residency;
145 state->flags = CPUIDLE_FLAG_TIME_VALID;
146 state->enter = omap4_enter_idle;
147 sprintf(state->name, "C%d", idx + 1);
148 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
149}
150
151static inline struct omap4_idle_statedata *_fill_cstate_usage(
152 struct cpuidle_device *dev,
153 int idx)
154{
155 struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
156 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
157
158 cx->valid = cpuidle_params_table[idx].valid;
159 cpuidle_set_statedata(state_usage, cx);
160
161 return cx;
162}
163
164
165
166/** 173/**
167 * omap4_idle_init - Init routine for OMAP4 idle 174 * omap4_idle_init - Init routine for OMAP4 idle
168 * 175 *
@@ -171,9 +178,7 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
171 */ 178 */
172int __init omap4_idle_init(void) 179int __init omap4_idle_init(void)
173{ 180{
174 struct omap4_idle_statedata *cx;
175 struct cpuidle_device *dev; 181 struct cpuidle_device *dev;
176 struct cpuidle_driver *drv = &omap4_idle_driver;
177 unsigned int cpu_id = 0; 182 unsigned int cpu_id = 0;
178 183
179 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 184 mpu_pd = pwrdm_lookup("mpu_pwrdm");
@@ -182,42 +187,15 @@ int __init omap4_idle_init(void)
182 if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd)) 187 if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
183 return -ENODEV; 188 return -ENODEV;
184 189
185
186 drv->safe_state_index = -1;
187 dev = &per_cpu(omap4_idle_dev, cpu_id); 190 dev = &per_cpu(omap4_idle_dev, cpu_id);
188 dev->cpu = cpu_id; 191 dev->cpu = cpu_id;
189 192
190 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
191 _fill_cstate(drv, 0, "MPUSS ON");
192 drv->safe_state_index = 0;
193 cx = _fill_cstate_usage(dev, 0);
194 cx->valid = 1; /* C1 is always valid */
195 cx->cpu_state = PWRDM_POWER_ON;
196 cx->mpu_state = PWRDM_POWER_ON;
197 cx->mpu_logic_state = PWRDM_POWER_RET;
198
199 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
200 _fill_cstate(drv, 1, "MPUSS CSWR");
201 cx = _fill_cstate_usage(dev, 1);
202 cx->cpu_state = PWRDM_POWER_OFF;
203 cx->mpu_state = PWRDM_POWER_RET;
204 cx->mpu_logic_state = PWRDM_POWER_RET;
205
206 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
207 _fill_cstate(drv, 2, "MPUSS OSWR");
208 cx = _fill_cstate_usage(dev, 2);
209 cx->cpu_state = PWRDM_POWER_OFF;
210 cx->mpu_state = PWRDM_POWER_RET;
211 cx->mpu_logic_state = PWRDM_POWER_OFF;
212
213 drv->state_count = OMAP4_NUM_STATES;
214 cpuidle_register_driver(&omap4_idle_driver); 193 cpuidle_register_driver(&omap4_idle_driver);
215 194
216 dev->state_count = OMAP4_NUM_STATES;
217 if (cpuidle_register_device(dev)) { 195 if (cpuidle_register_device(dev)) {
218 pr_err("%s: CPUidle register device failed\n", __func__); 196 pr_err("%s: CPUidle register device failed\n", __func__);
219 return -EIO; 197 return -EIO;
220 } 198 }
221 199
222 return 0; 200 return 0;
223} 201}
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 98cab3a204b9..ae62ece04ef9 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -42,7 +42,6 @@
42 42
43static int __init omap3_l3_init(void) 43static int __init omap3_l3_init(void)
44{ 44{
45 int l;
46 struct omap_hwmod *oh; 45 struct omap_hwmod *oh;
47 struct platform_device *pdev; 46 struct platform_device *pdev;
48 char oh_name[L3_MODULES_MAX_LEN]; 47 char oh_name[L3_MODULES_MAX_LEN];
@@ -54,7 +53,7 @@ static int __init omap3_l3_init(void)
54 if (!(cpu_is_omap34xx())) 53 if (!(cpu_is_omap34xx()))
55 return -ENODEV; 54 return -ENODEV;
56 55
57 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); 56 snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
58 57
59 oh = omap_hwmod_lookup(oh_name); 58 oh = omap_hwmod_lookup(oh_name);
60 59
@@ -72,7 +71,7 @@ postcore_initcall(omap3_l3_init);
72 71
73static int __init omap4_l3_init(void) 72static int __init omap4_l3_init(void)
74{ 73{
75 int l, i; 74 int i;
76 struct omap_hwmod *oh[3]; 75 struct omap_hwmod *oh[3];
77 struct platform_device *pdev; 76 struct platform_device *pdev;
78 char oh_name[L3_MODULES_MAX_LEN]; 77 char oh_name[L3_MODULES_MAX_LEN];
@@ -89,7 +88,7 @@ static int __init omap4_l3_init(void)
89 return -ENODEV; 88 return -ENODEV;
90 89
91 for (i = 0; i < L3_MODULES; i++) { 90 for (i = 0; i < L3_MODULES; i++) {
92 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); 91 snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
93 92
94 oh[i] = omap_hwmod_lookup(oh_name); 93 oh[i] = omap_hwmod_lookup(oh_name);
95 if (!(oh[i])) 94 if (!(oh[i]))
@@ -355,6 +354,36 @@ static void __init omap_init_dmic(void)
355static inline void omap_init_dmic(void) {} 354static inline void omap_init_dmic(void) {}
356#endif 355#endif
357 356
357#if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \
358 defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE)
359
360static struct platform_device omap_hdmi_audio = {
361 .name = "omap-hdmi-audio",
362 .id = -1,
363};
364
365static void __init omap_init_hdmi_audio(void)
366{
367 struct omap_hwmod *oh;
368 struct platform_device *pdev;
369
370 oh = omap_hwmod_lookup("dss_hdmi");
371 if (!oh) {
372 printk(KERN_ERR "Could not look up dss_hdmi hw_mod\n");
373 return;
374 }
375
376 pdev = omap_device_build("omap-hdmi-audio-dai",
377 -1, oh, NULL, 0, NULL, 0, 0);
378 WARN(IS_ERR(pdev),
379 "Can't build omap_device for omap-hdmi-audio-dai.\n");
380
381 platform_device_register(&omap_hdmi_audio);
382}
383#else
384static inline void omap_init_hdmi_audio(void) {}
385#endif
386
358#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) 387#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
359 388
360#include <plat/mcspi.h> 389#include <plat/mcspi.h>
@@ -701,13 +730,15 @@ static int __init omap2_init_devices(void)
701 * in alphabetical order so they're easier to sort through. 730 * in alphabetical order so they're easier to sort through.
702 */ 731 */
703 omap_init_audio(); 732 omap_init_audio();
704 omap_init_mcpdm();
705 omap_init_dmic();
706 omap_init_camera(); 733 omap_init_camera();
734 omap_init_hdmi_audio();
707 omap_init_mbox(); 735 omap_init_mbox();
708 /* If dtb is there, the devices will be created dynamically */ 736 /* If dtb is there, the devices will be created dynamically */
709 if (!of_have_populated_dt()) 737 if (!of_have_populated_dt()) {
738 omap_init_dmic();
739 omap_init_mcpdm();
710 omap_init_mcspi(); 740 omap_init_mcspi();
741 }
711 omap_init_pmu(); 742 omap_init_pmu();
712 omap_hdq_init(); 743 omap_hdq_init();
713 omap_init_sti(); 744 omap_init_sti();
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fc56745676fa..f0f10beeffe8 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -142,7 +142,8 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
142 142
143 ai = omap3_dpll_autoidle_read(clk); 143 ai = omap3_dpll_autoidle_read(clk);
144 144
145 omap3_dpll_deny_idle(clk); 145 if (ai)
146 omap3_dpll_deny_idle(clk);
146 147
147 _omap3_dpll_write_clken(clk, DPLL_LOCKED); 148 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
148 149
@@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
186 187
187 if (ai) 188 if (ai)
188 omap3_dpll_allow_idle(clk); 189 omap3_dpll_allow_idle(clk);
189 else
190 omap3_dpll_deny_idle(clk);
191 190
192 return r; 191 return r;
193} 192}
@@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
216 215
217 if (ai) 216 if (ai)
218 omap3_dpll_allow_idle(clk); 217 omap3_dpll_allow_idle(clk);
219 else
220 omap3_dpll_deny_idle(clk);
221 218
222 return 0; 219 return 0;
223} 220}
@@ -519,6 +516,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
519 516
520 dd = clk->dpll_data; 517 dd = clk->dpll_data;
521 518
519 if (!dd->autoidle_reg)
520 return -EINVAL;
521
522 v = __raw_readl(dd->autoidle_reg); 522 v = __raw_readl(dd->autoidle_reg);
523 v &= dd->autoidle_mask; 523 v &= dd->autoidle_mask;
524 v >>= __ffs(dd->autoidle_mask); 524 v >>= __ffs(dd->autoidle_mask);
@@ -545,6 +545,12 @@ void omap3_dpll_allow_idle(struct clk *clk)
545 545
546 dd = clk->dpll_data; 546 dd = clk->dpll_data;
547 547
548 if (!dd->autoidle_reg) {
549 pr_debug("clock: DPLL %s: autoidle not supported\n",
550 clk->name);
551 return;
552 }
553
548 /* 554 /*
549 * REVISIT: CORE DPLL can optionally enter low-power bypass 555 * REVISIT: CORE DPLL can optionally enter low-power bypass
550 * by writing 0x5 instead of 0x1. Add some mechanism to 556 * by writing 0x5 instead of 0x1. Add some mechanism to
@@ -554,6 +560,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
554 v &= ~dd->autoidle_mask; 560 v &= ~dd->autoidle_mask;
555 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); 561 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
556 __raw_writel(v, dd->autoidle_reg); 562 __raw_writel(v, dd->autoidle_reg);
563
557} 564}
558 565
559/** 566/**
@@ -572,6 +579,12 @@ void omap3_dpll_deny_idle(struct clk *clk)
572 579
573 dd = clk->dpll_data; 580 dd = clk->dpll_data;
574 581
582 if (!dd->autoidle_reg) {
583 pr_debug("clock: DPLL %s: autoidle not supported\n",
584 clk->name);
585 return;
586 }
587
575 v = __raw_readl(dd->autoidle_reg); 588 v = __raw_readl(dd->autoidle_reg);
576 v &= ~dd->autoidle_mask; 589 v &= ~dd->autoidle_mask;
577 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); 590 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 74f18f2952df..3376388b317a 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -57,8 +57,9 @@ static int __init omap_dsp_init(void)
57 57
58 if (pdata->phys_mempool_base) { 58 if (pdata->phys_mempool_base) {
59 pdata->phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE; 59 pdata->phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
60 pr_info("%s: %x bytes @ %x\n", __func__, 60 pr_info("%s: %llx bytes @ %llx\n", __func__,
61 pdata->phys_mempool_size, pdata->phys_mempool_base); 61 (unsigned long long)pdata->phys_mempool_size,
62 (unsigned long long)pdata->phys_mempool_base);
62 } 63 }
63 64
64 pdev = platform_device_alloc("omap-dsp", -1); 65 pdev = platform_device_alloc("omap-dsp", -1);
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 18f9c7bd7200..9ad7d489b0de 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -56,10 +56,9 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
56 dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr; 56 dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
57 pdata->bank_width = dev_attr->bank_width; 57 pdata->bank_width = dev_attr->bank_width;
58 pdata->dbck_flag = dev_attr->dbck_flag; 58 pdata->dbck_flag = dev_attr->dbck_flag;
59 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
60 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 59 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
61 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); 60 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
62 if (!pdata) { 61 if (!pdata->regs) {
63 pr_err("gpio%d: Memory allocation failed\n", id); 62 pr_err("gpio%d: Memory allocation failed\n", id);
64 return -ENOMEM; 63 return -ENOMEM;
65 } 64 }
@@ -103,6 +102,8 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
103 pdata->regs->dataout = OMAP4_GPIO_DATAOUT; 102 pdata->regs->dataout = OMAP4_GPIO_DATAOUT;
104 pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT; 103 pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT;
105 pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT; 104 pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT;
105 pdata->regs->irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0;
106 pdata->regs->irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1;
106 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0; 107 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
107 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1; 108 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
108 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0; 109 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 385b3e02c4a6..a0fa9bb2bda5 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -176,7 +176,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
176 const int t_wpl = 40; 176 const int t_wpl = 40;
177 const int t_wph = 30; 177 const int t_wph = 30;
178 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 178 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
179 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; 179 int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
180 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; 180 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
181 int err, ticks_cez; 181 int err, ticks_cez;
182 int cs = cfg->cs, freq = *freq_ptr; 182 int cs = cfg->cs, freq = *freq_ptr;
@@ -240,7 +240,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
240 break; 240 break;
241 } 241 }
242 242
243 tick_ns = gpmc_ticks_to_ns(1);
244 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period); 243 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
245 gpmc_clk_ns = gpmc_ticks_to_ns(div); 244 gpmc_clk_ns = gpmc_ticks_to_ns(div);
246 if (gpmc_clk_ns < 15) /* >66Mhz */ 245 if (gpmc_clk_ns < 15) /* >66Mhz */
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d510858e28..580e684e8825 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -755,8 +755,7 @@ static int __init gpmc_init(void)
755 irq++; 755 irq++;
756 } 756 }
757 757
758 ret = request_irq(gpmc_irq, 758 ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
759 gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
760 if (ret) 759 if (ret)
761 pr_err("gpmc: irq-%d could not claim: err %d\n", 760 pr_err("gpmc: irq-%d could not claim: err %d\n",
762 gpmc_irq, ret); 761 gpmc_irq, ret);
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
new file mode 100644
index 000000000000..297ebe03f09c
--- /dev/null
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -0,0 +1,72 @@
1/*
2 * IP block integration code for the HDQ1W/1-wire IP block
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
8 * Avinash.H.M <avinashhm@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
23 */
24
25#include <plat/omap_hwmod.h>
26#include <plat/hdq1w.h>
27
28#include "common.h"
29
30/* Maximum microseconds to wait for OMAP module to softreset */
31#define MAX_MODULE_SOFTRESET_WAIT 10000
32
33/**
34 * omap_hdq1w_reset - reset the OMAP HDQ1W module
35 * @oh: struct omap_hwmod *
36 *
37 * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
38 * Software Reset" of the OMAP34xx Technical Reference Manual Revision
39 * ZR (SWPU223R) does not include the rather important fact that, for
40 * the reset to succeed, the HDQ1W module's internal clock gate must be
41 * programmed to allow the clock to propagate to the rest of the
42 * module. In this sense, it's rather similar to the I2C custom reset
43 * function. Returns 0.
44 */
45int omap_hdq1w_reset(struct omap_hwmod *oh)
46{
47 u32 v;
48 int c = 0;
49
50 /* Write to the SOFTRESET bit */
51 omap_hwmod_softreset(oh);
52
53 /* Enable the module's internal clocks */
54 v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
55 v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
56 omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
57
58 /* Poll on RESETDONE bit */
59 omap_test_timeout((omap_hwmod_read(oh,
60 oh->class->sysc->syss_offs)
61 & SYSS_RESETDONE_MASK),
62 MAX_MODULE_SOFTRESET_WAIT, c);
63
64 if (c == MAX_MODULE_SOFTRESET_WAIT)
65 pr_warning("%s: %s: softreset failed (waited %d usec)\n",
66 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
67 else
68 pr_debug("%s: %s: softreset in %d usec\n", __func__,
69 oh->name, c);
70
71 return 0;
72}
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 454dfce125ca..8763c8520dc2 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -28,7 +28,7 @@ static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
28 .base_id = 0, 28 .base_id = 0,
29}; 29};
30 30
31int __init hwspinlocks_init(void) 31static int __init hwspinlocks_init(void)
32{ 32{
33 int retval = 0; 33 int retval = 0;
34 struct omap_hwmod *oh; 34 struct omap_hwmod *oh;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0e79b7bc6aa4..f1398171d8a2 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -478,9 +478,12 @@ void __init omap4xxx_check_revision(void)
478 case 0xb94e: 478 case 0xb94e:
479 switch (rev) { 479 switch (rev) {
480 case 0: 480 case 0:
481 default:
482 omap_revision = OMAP4460_REV_ES1_0; 481 omap_revision = OMAP4460_REV_ES1_0;
483 break; 482 break;
483 case 2:
484 default:
485 omap_revision = OMAP4460_REV_ES1_1;
486 break;
484 } 487 }
485 break; 488 break;
486 case 0xb975: 489 case 0xb975:
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
index 1e2d3322f33e..c88420de1151 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -941,10 +941,10 @@
941#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) 941#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
942#define OMAP4_DSI1_LANEENABLE_SHIFT 24 942#define OMAP4_DSI1_LANEENABLE_SHIFT 24
943#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) 943#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
944#define OMAP4_DSI2_PIPD_SHIFT 19 944#define OMAP4_DSI1_PIPD_SHIFT 19
945#define OMAP4_DSI2_PIPD_MASK (0x1f << 19) 945#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
946#define OMAP4_DSI1_PIPD_SHIFT 14 946#define OMAP4_DSI2_PIPD_SHIFT 14
947#define OMAP4_DSI1_PIPD_MASK (0x1f << 14) 947#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
948 948
949/* CONTROL_MCBSPLP */ 949/* CONTROL_MCBSPLP */
950#define OMAP4_ALBCTRLRX_FSX_SHIFT 31 950#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 065bd768987c..4b9491aa36fa 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -31,6 +31,7 @@
31#include <plat/omap-pm.h> 31#include <plat/omap-pm.h>
32#include <plat/omap_hwmod.h> 32#include <plat/omap_hwmod.h>
33#include <plat/multi.h> 33#include <plat/multi.h>
34#include <plat/dma.h>
34 35
35#include "iomap.h" 36#include "iomap.h"
36#include "voltage.h" 37#include "voltage.h"
@@ -363,24 +364,6 @@ static void __init omap_hwmod_init_postsetup(void)
363#endif 364#endif
364 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 365 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
365 366
366 /*
367 * Set the default postsetup state for unusual modules (like
368 * MPU WDT).
369 *
370 * The postsetup_state is not actually used until
371 * omap_hwmod_late_init(), so boards that desire full watchdog
372 * coverage of kernel initialization can reprogram the
373 * postsetup_state between the calls to
374 * omap2_init_common_infra() and omap_sdrc_init().
375 *
376 * XXX ideally we could detect whether the MPU WDT was currently
377 * enabled here and make this conditional
378 */
379 postsetup_state = _HWMOD_STATE_DISABLED;
380 omap_hwmod_for_each_by_class("wd_timer",
381 _set_hwmod_postsetup_state,
382 &postsetup_state);
383
384 omap_pm_if_early_init(); 367 omap_pm_if_early_init();
385} 368}
386 369
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f0d2571c9a..1ecf54565fe2 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -25,6 +25,7 @@
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27#include "iomap.h" 27#include "iomap.h"
28#include "common.h"
28 29
29/* selected INTC register offsets */ 30/* selected INTC register offsets */
30 31
@@ -149,7 +150,6 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
149 ct->chip.irq_mask = irq_gc_mask_disable_reg; 150 ct->chip.irq_mask = irq_gc_mask_disable_reg;
150 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 151 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
151 152
152 ct->regs.ack = INTC_CONTROL;
153 ct->regs.enable = INTC_MIR_CLEAR0; 153 ct->regs.enable = INTC_MIR_CLEAR0;
154 ct->regs.disable = INTC_MIR_SET0; 154 ct->regs.disable = INTC_MIR_SET0;
155 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 155 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
@@ -231,7 +231,7 @@ static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs
231 goto out; 231 goto out;
232 232
233 irqnr = readl_relaxed(base_addr + 0xd8); 233 irqnr = readl_relaxed(base_addr + 0xd8);
234#ifdef CONFIG_SOC_OMAPTI816X 234#ifdef CONFIG_SOC_OMAPTI81XX
235 if (irqnr) 235 if (irqnr)
236 goto out; 236 goto out;
237 irqnr = readl_relaxed(base_addr + 0xf8); 237 irqnr = readl_relaxed(base_addr + 0xf8);
@@ -334,7 +334,7 @@ void omap_intc_restore_context(void)
334void omap3_intc_suspend(void) 334void omap3_intc_suspend(void)
335{ 335{
336 /* A pending interrupt would prevent OMAP from entering suspend */ 336 /* A pending interrupt would prevent OMAP from entering suspend */
337 omap_ack_irq(0); 337 omap_ack_irq(NULL);
338} 338}
339 339
340void omap3_intc_prepare_idle(void) 340void omap3_intc_prepare_idle(void)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 415a6f1cf419..19b8b6774862 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -26,9 +26,9 @@
26#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) 26#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
27#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) 27#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
28 28
29#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u)) 29#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
30#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u)) 30#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
31#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u)) 31#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
32 32
33#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) 33#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
34#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) 34#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
new file mode 100644
index 000000000000..ef2a6924731a
--- /dev/null
+++ b/arch/arm/mach-omap2/msdi.c
@@ -0,0 +1,88 @@
1/*
2 * MSDI IP block reset
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * XXX What about pad muxing?
22 */
23
24#include <linux/kernel.h>
25
26#include <plat/omap_hwmod.h>
27#include <plat/mmc.h>
28
29#include "common.h"
30
31/*
32 * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
33 * from the IP block's base address
34 */
35#define MSDI_CON_OFFSET 0x0c
36
37/* Register bitfields in the CON register */
38#define MSDI_CON_POW_MASK BIT(11)
39#define MSDI_CON_CLKD_MASK (0x3f << 0)
40#define MSDI_CON_CLKD_SHIFT 0
41
42/* Maximum microseconds to wait for OMAP module to softreset */
43#define MAX_MODULE_SOFTRESET_WAIT 10000
44
45/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
46#define MSDI_TARGET_RESET_CLKD 0x3ff
47
48/**
49 * omap_msdi_reset - reset the MSDI IP block
50 * @oh: struct omap_hwmod *
51 *
52 * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
53 * fields set inside its CON register for a reset to complete
54 * successfully. This is not documented in the TRM. For CLKD, we use
55 * the value that results in the lowest possible clock rate, to attempt
56 * to avoid disturbing any cards.
57 */
58int omap_msdi_reset(struct omap_hwmod *oh)
59{
60 u16 v = 0;
61 int c = 0;
62
63 /* Write to the SOFTRESET bit */
64 omap_hwmod_softreset(oh);
65
66 /* Enable the MSDI core and internal clock */
67 v |= MSDI_CON_POW_MASK;
68 v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
69 omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
70
71 /* Poll on RESETDONE bit */
72 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
73 & SYSS_RESETDONE_MASK),
74 MAX_MODULE_SOFTRESET_WAIT, c);
75
76 if (c == MAX_MODULE_SOFTRESET_WAIT)
77 pr_warning("%s: %s: softreset failed (waited %d usec)\n",
78 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
79 else
80 pr_debug("%s: %s: softreset in %d usec\n", __func__,
81 oh->name, c);
82
83 /* Disable the MSDI internal clock */
84 v &= ~MSDI_CON_CLKD_MASK;
85 omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
86
87 return 0;
88}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 65c33911341f..3268ee24eada 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -247,7 +247,7 @@ int __init omap_mux_init_signal(const char *muxname, int val)
247 int mux_mode; 247 int mux_mode;
248 248
249 mux_mode = omap_mux_get_by_name(muxname, &partition, &mux); 249 mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
250 if (mux_mode < 0) 250 if (mux_mode < 0 || !mux)
251 return mux_mode; 251 return mux_mode;
252 252
253 old_mode = omap_mux_read(partition, mux->reg_offset); 253 old_mode = omap_mux_read(partition, mux->reg_offset);
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index d8f8ef40290f..d9ae4a53d818 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -18,6 +18,7 @@
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/memblock.h> 19#include <asm/memblock.h>
20 20
21#include <plat/omap-secure.h>
21#include <mach/omap-secure.h> 22#include <mach/omap-secure.h>
22 23
23static phys_addr_t omap_secure_memblock_base; 24static phys_addr_t omap_secure_memblock_base;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 42cd7fb52414..d811c7790350 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -259,7 +259,7 @@ static void irq_save_context(void)
259/* 259/*
260 * Clear WakeupGen SAR backup status. 260 * Clear WakeupGen SAR backup status.
261 */ 261 */
262void irq_sar_clear(void) 262static void irq_sar_clear(void)
263{ 263{
264 u32 val; 264 u32 val;
265 val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); 265 val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 70de277f5c15..a8161e5f3204 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -25,11 +25,13 @@
25#include <plat/irqs.h> 25#include <plat/irqs.h>
26#include <plat/sram.h> 26#include <plat/sram.h>
27#include <plat/omap-secure.h> 27#include <plat/omap-secure.h>
28#include <plat/mmc.h>
28 29
29#include <mach/hardware.h> 30#include <mach/hardware.h>
30#include <mach/omap-wakeupgen.h> 31#include <mach/omap-wakeupgen.h>
31 32
32#include "common.h" 33#include "common.h"
34#include "hsmmc.h"
33#include "omap4-sar-layout.h" 35#include "omap4-sar-layout.h"
34#include <linux/export.h> 36#include <linux/export.h>
35 37
@@ -207,3 +209,59 @@ static int __init omap4_sar_ram_init(void)
207 return 0; 209 return 0;
208} 210}
209early_initcall(omap4_sar_ram_init); 211early_initcall(omap4_sar_ram_init);
212
213#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
214static int omap4_twl6030_hsmmc_late_init(struct device *dev)
215{
216 int irq = 0;
217 struct platform_device *pdev = container_of(dev,
218 struct platform_device, dev);
219 struct omap_mmc_platform_data *pdata = dev->platform_data;
220
221 /* Setting MMC1 Card detect Irq */
222 if (pdev->id == 0) {
223 irq = twl6030_mmc_card_detect_config();
224 if (irq < 0) {
225 dev_err(dev, "%s: Error card detect config(%d)\n",
226 __func__, irq);
227 return irq;
228 }
229 pdata->slots[0].card_detect_irq = irq;
230 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
231 }
232 return 0;
233}
234
235static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
236{
237 struct omap_mmc_platform_data *pdata;
238
239 /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
240 if (!dev) {
241 pr_err("Failed %s\n", __func__);
242 return;
243 }
244 pdata = dev->platform_data;
245 pdata->init = omap4_twl6030_hsmmc_late_init;
246}
247
248int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
249{
250 struct omap2_hsmmc_info *c;
251
252 omap_hsmmc_init(controllers);
253 for (c = controllers; c->mmc; c++) {
254 /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
255 if (!c->pdev)
256 continue;
257 omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
258 }
259
260 return 0;
261}
262#else
263int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
264{
265 return 0;
266}
267#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7144ae651d3d..bf86f7e8f91f 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,7 +2,7 @@
2 * omap_hwmod implementation for OMAP2/3/4 2 * omap_hwmod implementation for OMAP2/3/4
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc. 5 * Copyright (C) 2011-2012 Texas Instruments, Inc.
6 * 6 *
7 * Paul Walmsley, Benoît Cousson, Kevin Hilman 7 * Paul Walmsley, Benoît Cousson, Kevin Hilman
8 * 8 *
@@ -137,6 +137,7 @@
137#include <linux/mutex.h> 137#include <linux/mutex.h>
138#include <linux/spinlock.h> 138#include <linux/spinlock.h>
139#include <linux/slab.h> 139#include <linux/slab.h>
140#include <linux/bootmem.h>
140 141
141#include "common.h" 142#include "common.h"
142#include <plat/cpu.h> 143#include <plat/cpu.h>
@@ -159,16 +160,58 @@
159/* Name of the OMAP hwmod for the MPU */ 160/* Name of the OMAP hwmod for the MPU */
160#define MPU_INITIATOR_NAME "mpu" 161#define MPU_INITIATOR_NAME "mpu"
161 162
163/*
164 * Number of struct omap_hwmod_link records per struct
165 * omap_hwmod_ocp_if record (master->slave and slave->master)
166 */
167#define LINKS_PER_OCP_IF 2
168
162/* omap_hwmod_list contains all registered struct omap_hwmods */ 169/* omap_hwmod_list contains all registered struct omap_hwmods */
163static LIST_HEAD(omap_hwmod_list); 170static LIST_HEAD(omap_hwmod_list);
164 171
165/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ 172/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
166static struct omap_hwmod *mpu_oh; 173static struct omap_hwmod *mpu_oh;
167 174
175/*
176 * linkspace: ptr to a buffer that struct omap_hwmod_link records are
177 * allocated from - used to reduce the number of small memory
178 * allocations, which has a significant impact on performance
179 */
180static struct omap_hwmod_link *linkspace;
181
182/*
183 * free_ls, max_ls: array indexes into linkspace; representing the
184 * next free struct omap_hwmod_link index, and the maximum number of
185 * struct omap_hwmod_link records allocated (respectively)
186 */
187static unsigned short free_ls, max_ls, ls_supp;
168 188
169/* Private functions */ 189/* Private functions */
170 190
171/** 191/**
192 * _fetch_next_ocp_if - return the next OCP interface in a list
193 * @p: ptr to a ptr to the list_head inside the ocp_if to return
194 * @i: pointer to the index of the element pointed to by @p in the list
195 *
196 * Return a pointer to the struct omap_hwmod_ocp_if record
197 * containing the struct list_head pointed to by @p, and increment
198 * @p such that a future call to this routine will return the next
199 * record.
200 */
201static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
202 int *i)
203{
204 struct omap_hwmod_ocp_if *oi;
205
206 oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
207 *p = (*p)->next;
208
209 *i = *i + 1;
210
211 return oi;
212}
213
214/**
172 * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy 215 * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
173 * @oh: struct omap_hwmod * 216 * @oh: struct omap_hwmod *
174 * 217 *
@@ -582,16 +625,16 @@ static int _init_main_clk(struct omap_hwmod *oh)
582 */ 625 */
583static int _init_interface_clks(struct omap_hwmod *oh) 626static int _init_interface_clks(struct omap_hwmod *oh)
584{ 627{
628 struct omap_hwmod_ocp_if *os;
629 struct list_head *p;
585 struct clk *c; 630 struct clk *c;
586 int i; 631 int i = 0;
587 int ret = 0; 632 int ret = 0;
588 633
589 if (oh->slaves_cnt == 0) 634 p = oh->slave_ports.next;
590 return 0;
591
592 for (i = 0; i < oh->slaves_cnt; i++) {
593 struct omap_hwmod_ocp_if *os = oh->slaves[i];
594 635
636 while (i < oh->slaves_cnt) {
637 os = _fetch_next_ocp_if(&p, &i);
595 if (!os->clk) 638 if (!os->clk)
596 continue; 639 continue;
597 640
@@ -643,21 +686,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
643 */ 686 */
644static int _enable_clocks(struct omap_hwmod *oh) 687static int _enable_clocks(struct omap_hwmod *oh)
645{ 688{
646 int i; 689 struct omap_hwmod_ocp_if *os;
690 struct list_head *p;
691 int i = 0;
647 692
648 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); 693 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
649 694
650 if (oh->_clk) 695 if (oh->_clk)
651 clk_enable(oh->_clk); 696 clk_enable(oh->_clk);
652 697
653 if (oh->slaves_cnt > 0) { 698 p = oh->slave_ports.next;
654 for (i = 0; i < oh->slaves_cnt; i++) {
655 struct omap_hwmod_ocp_if *os = oh->slaves[i];
656 struct clk *c = os->_clk;
657 699
658 if (c && (os->flags & OCPIF_SWSUP_IDLE)) 700 while (i < oh->slaves_cnt) {
659 clk_enable(c); 701 os = _fetch_next_ocp_if(&p, &i);
660 } 702
703 if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
704 clk_enable(os->_clk);
661 } 705 }
662 706
663 /* The opt clocks are controlled by the device driver. */ 707 /* The opt clocks are controlled by the device driver. */
@@ -673,21 +717,22 @@ static int _enable_clocks(struct omap_hwmod *oh)
673 */ 717 */
674static int _disable_clocks(struct omap_hwmod *oh) 718static int _disable_clocks(struct omap_hwmod *oh)
675{ 719{
676 int i; 720 struct omap_hwmod_ocp_if *os;
721 struct list_head *p;
722 int i = 0;
677 723
678 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); 724 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
679 725
680 if (oh->_clk) 726 if (oh->_clk)
681 clk_disable(oh->_clk); 727 clk_disable(oh->_clk);
682 728
683 if (oh->slaves_cnt > 0) { 729 p = oh->slave_ports.next;
684 for (i = 0; i < oh->slaves_cnt; i++) {
685 struct omap_hwmod_ocp_if *os = oh->slaves[i];
686 struct clk *c = os->_clk;
687 730
688 if (c && (os->flags & OCPIF_SWSUP_IDLE)) 731 while (i < oh->slaves_cnt) {
689 clk_disable(c); 732 os = _fetch_next_ocp_if(&p, &i);
690 } 733
734 if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
735 clk_disable(os->_clk);
691 } 736 }
692 737
693 /* The opt clocks are controlled by the device driver. */ 738 /* The opt clocks are controlled by the device driver. */
@@ -781,39 +826,6 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
781} 826}
782 827
783/** 828/**
784 * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
785 * @oh: struct omap_hwmod *
786 *
787 * Disable the PRCM module mode related to the hwmod @oh.
788 * Return EINVAL if the modulemode is not supported and 0 in case of success.
789 */
790static int _omap4_disable_module(struct omap_hwmod *oh)
791{
792 int v;
793
794 /* The module mode does not exist prior OMAP4 */
795 if (!cpu_is_omap44xx())
796 return -EINVAL;
797
798 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
799 return -EINVAL;
800
801 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
802
803 omap4_cminst_module_disable(oh->clkdm->prcm_partition,
804 oh->clkdm->cm_inst,
805 oh->clkdm->clkdm_offs,
806 oh->prcm.omap4.clkctrl_offs);
807
808 v = _omap4_wait_target_disable(oh);
809 if (v)
810 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
811 oh->name);
812
813 return 0;
814}
815
816/**
817 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh 829 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
818 * @oh: struct omap_hwmod *oh 830 * @oh: struct omap_hwmod *oh
819 * 831 *
@@ -883,59 +895,220 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
883} 895}
884 896
885/** 897/**
886 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use 898 * _get_mpu_irq_by_name - fetch MPU interrupt line number by name
887 * @oh: struct omap_hwmod * 899 * @oh: struct omap_hwmod * to operate on
900 * @name: pointer to the name of the MPU interrupt number to fetch (optional)
901 * @irq: pointer to an unsigned int to store the MPU IRQ number to
888 * 902 *
889 * Returns the array index of the OCP slave port that the MPU 903 * Retrieve a MPU hardware IRQ line number named by @name associated
890 * addresses the device on, or -EINVAL upon error or not found. 904 * with the IP block pointed to by @oh. The IRQ number will be filled
905 * into the address pointed to by @dma. When @name is non-null, the
906 * IRQ line number associated with the named entry will be returned.
907 * If @name is null, the first matching entry will be returned. Data
908 * order is not meaningful in hwmod data, so callers are strongly
909 * encouraged to use a non-null @name whenever possible to avoid
910 * unpredictable effects if hwmod data is later added that causes data
911 * ordering to change. Returns 0 upon success or a negative error
912 * code upon error.
891 */ 913 */
892static int __init _find_mpu_port_index(struct omap_hwmod *oh) 914static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name,
915 unsigned int *irq)
893{ 916{
894 int i; 917 int i;
895 int found = 0; 918 bool found = false;
896 919
897 if (!oh || oh->slaves_cnt == 0) 920 if (!oh->mpu_irqs)
898 return -EINVAL; 921 return -ENOENT;
899 922
900 for (i = 0; i < oh->slaves_cnt; i++) { 923 i = 0;
901 struct omap_hwmod_ocp_if *os = oh->slaves[i]; 924 while (oh->mpu_irqs[i].irq != -1) {
925 if (name == oh->mpu_irqs[i].name ||
926 !strcmp(name, oh->mpu_irqs[i].name)) {
927 found = true;
928 break;
929 }
930 i++;
931 }
902 932
903 if (os->user & OCP_USER_MPU) { 933 if (!found)
904 found = 1; 934 return -ENOENT;
935
936 *irq = oh->mpu_irqs[i].irq;
937
938 return 0;
939}
940
941/**
942 * _get_sdma_req_by_name - fetch SDMA request line ID by name
943 * @oh: struct omap_hwmod * to operate on
944 * @name: pointer to the name of the SDMA request line to fetch (optional)
945 * @dma: pointer to an unsigned int to store the request line ID to
946 *
947 * Retrieve an SDMA request line ID named by @name on the IP block
948 * pointed to by @oh. The ID will be filled into the address pointed
949 * to by @dma. When @name is non-null, the request line ID associated
950 * with the named entry will be returned. If @name is null, the first
951 * matching entry will be returned. Data order is not meaningful in
952 * hwmod data, so callers are strongly encouraged to use a non-null
953 * @name whenever possible to avoid unpredictable effects if hwmod
954 * data is later added that causes data ordering to change. Returns 0
955 * upon success or a negative error code upon error.
956 */
957static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name,
958 unsigned int *dma)
959{
960 int i;
961 bool found = false;
962
963 if (!oh->sdma_reqs)
964 return -ENOENT;
965
966 i = 0;
967 while (oh->sdma_reqs[i].dma_req != -1) {
968 if (name == oh->sdma_reqs[i].name ||
969 !strcmp(name, oh->sdma_reqs[i].name)) {
970 found = true;
905 break; 971 break;
906 } 972 }
973 i++;
907 } 974 }
908 975
909 if (found) 976 if (!found)
910 pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", 977 return -ENOENT;
911 oh->name, i); 978
912 else 979 *dma = oh->sdma_reqs[i].dma_req;
913 pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
914 oh->name);
915 980
916 return (found) ? i : -EINVAL; 981 return 0;
917} 982}
918 983
919/** 984/**
920 * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU 985 * _get_addr_space_by_name - fetch address space start & end by name
921 * @oh: struct omap_hwmod * 986 * @oh: struct omap_hwmod * to operate on
987 * @name: pointer to the name of the address space to fetch (optional)
988 * @pa_start: pointer to a u32 to store the starting address to
989 * @pa_end: pointer to a u32 to store the ending address to
922 * 990 *
923 * Return the virtual address of the base of the register target of 991 * Retrieve address space start and end addresses for the IP block
924 * device @oh, or NULL on error. 992 * pointed to by @oh. The data will be filled into the addresses
993 * pointed to by @pa_start and @pa_end. When @name is non-null, the
994 * address space data associated with the named entry will be
995 * returned. If @name is null, the first matching entry will be
996 * returned. Data order is not meaningful in hwmod data, so callers
997 * are strongly encouraged to use a non-null @name whenever possible
998 * to avoid unpredictable effects if hwmod data is later added that
999 * causes data ordering to change. Returns 0 upon success or a
1000 * negative error code upon error.
925 */ 1001 */
926static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) 1002static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
1003 u32 *pa_start, u32 *pa_end)
927{ 1004{
1005 int i, j;
928 struct omap_hwmod_ocp_if *os; 1006 struct omap_hwmod_ocp_if *os;
929 struct omap_hwmod_addr_space *mem; 1007 struct list_head *p = NULL;
930 int i = 0, found = 0; 1008 bool found = false;
931 void __iomem *va_start; 1009
1010 p = oh->slave_ports.next;
1011
1012 i = 0;
1013 while (i < oh->slaves_cnt) {
1014 os = _fetch_next_ocp_if(&p, &i);
1015
1016 if (!os->addr)
1017 return -ENOENT;
1018
1019 j = 0;
1020 while (os->addr[j].pa_start != os->addr[j].pa_end) {
1021 if (name == os->addr[j].name ||
1022 !strcmp(name, os->addr[j].name)) {
1023 found = true;
1024 break;
1025 }
1026 j++;
1027 }
1028
1029 if (found)
1030 break;
1031 }
1032
1033 if (!found)
1034 return -ENOENT;
1035
1036 *pa_start = os->addr[j].pa_start;
1037 *pa_end = os->addr[j].pa_end;
1038
1039 return 0;
1040}
1041
1042/**
1043 * _save_mpu_port_index - find and save the index to @oh's MPU port
1044 * @oh: struct omap_hwmod *
1045 *
1046 * Determines the array index of the OCP slave port that the MPU uses
1047 * to address the device, and saves it into the struct omap_hwmod.
1048 * Intended to be called during hwmod registration only. No return
1049 * value.
1050 */
1051static void __init _save_mpu_port_index(struct omap_hwmod *oh)
1052{
1053 struct omap_hwmod_ocp_if *os = NULL;
1054 struct list_head *p;
1055 int i = 0;
1056
1057 if (!oh)
1058 return;
932 1059
933 if (!oh || oh->slaves_cnt == 0) 1060 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
1061
1062 p = oh->slave_ports.next;
1063
1064 while (i < oh->slaves_cnt) {
1065 os = _fetch_next_ocp_if(&p, &i);
1066 if (os->user & OCP_USER_MPU) {
1067 oh->_mpu_port = os;
1068 oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
1069 break;
1070 }
1071 }
1072
1073 return;
1074}
1075
1076/**
1077 * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU
1078 * @oh: struct omap_hwmod *
1079 *
1080 * Given a pointer to a struct omap_hwmod record @oh, return a pointer
1081 * to the struct omap_hwmod_ocp_if record that is used by the MPU to
1082 * communicate with the IP block. This interface need not be directly
1083 * connected to the MPU (and almost certainly is not), but is directly
1084 * connected to the IP block represented by @oh. Returns a pointer
1085 * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon
1086 * error or if there does not appear to be a path from the MPU to this
1087 * IP block.
1088 */
1089static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
1090{
1091 if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
934 return NULL; 1092 return NULL;
935 1093
936 os = oh->slaves[index]; 1094 return oh->_mpu_port;
1095};
1096
1097/**
1098 * _find_mpu_rt_addr_space - return MPU register target address space for @oh
1099 * @oh: struct omap_hwmod *
1100 *
1101 * Returns a pointer to the struct omap_hwmod_addr_space record representing
1102 * the register target MPU address space; or returns NULL upon error.
1103 */
1104static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh)
1105{
1106 struct omap_hwmod_ocp_if *os;
1107 struct omap_hwmod_addr_space *mem;
1108 int found = 0, i = 0;
937 1109
938 if (!os->addr) 1110 os = _find_mpu_rt_port(oh);
1111 if (!os || !os->addr)
939 return NULL; 1112 return NULL;
940 1113
941 do { 1114 do {
@@ -944,20 +1117,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
944 found = 1; 1117 found = 1;
945 } while (!found && mem->pa_start != mem->pa_end); 1118 } while (!found && mem->pa_start != mem->pa_end);
946 1119
947 if (found) { 1120 return (found) ? mem : NULL;
948 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
949 if (!va_start) {
950 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
951 return NULL;
952 }
953 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
954 oh->name, va_start);
955 } else {
956 pr_debug("omap_hwmod: %s: no MPU register target found\n",
957 oh->name);
958 }
959
960 return (found) ? va_start : NULL;
961} 1121}
962 1122
963/** 1123/**
@@ -1205,12 +1365,11 @@ static int _wait_target_ready(struct omap_hwmod *oh)
1205 if (!oh) 1365 if (!oh)
1206 return -EINVAL; 1366 return -EINVAL;
1207 1367
1208 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 1368 if (oh->flags & HWMOD_NO_IDLEST)
1209 return 0; 1369 return 0;
1210 1370
1211 os = oh->slaves[oh->_mpu_port_index]; 1371 os = _find_mpu_rt_port(oh);
1212 1372 if (!os)
1213 if (oh->flags & HWMOD_NO_IDLEST)
1214 return 0; 1373 return 0;
1215 1374
1216 /* XXX check module SIDLEMODE */ 1375 /* XXX check module SIDLEMODE */
@@ -1378,13 +1537,73 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1378} 1537}
1379 1538
1380/** 1539/**
1540 * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
1541 * @oh: struct omap_hwmod *
1542 *
1543 * If any hardreset line associated with @oh is asserted, then return true.
1544 * Otherwise, if @oh has no hardreset lines associated with it, or if
1545 * no hardreset lines associated with @oh are asserted, then return false.
1546 * This function is used to avoid executing some parts of the IP block
1547 * enable/disable sequence if a hardreset line is set.
1548 */
1549static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
1550{
1551 int i;
1552
1553 if (oh->rst_lines_cnt == 0)
1554 return false;
1555
1556 for (i = 0; i < oh->rst_lines_cnt; i++)
1557 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
1558 return true;
1559
1560 return false;
1561}
1562
1563/**
1564 * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
1565 * @oh: struct omap_hwmod *
1566 *
1567 * Disable the PRCM module mode related to the hwmod @oh.
1568 * Return EINVAL if the modulemode is not supported and 0 in case of success.
1569 */
1570static int _omap4_disable_module(struct omap_hwmod *oh)
1571{
1572 int v;
1573
1574 /* The module mode does not exist prior OMAP4 */
1575 if (!cpu_is_omap44xx())
1576 return -EINVAL;
1577
1578 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
1579 return -EINVAL;
1580
1581 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
1582
1583 omap4_cminst_module_disable(oh->clkdm->prcm_partition,
1584 oh->clkdm->cm_inst,
1585 oh->clkdm->clkdm_offs,
1586 oh->prcm.omap4.clkctrl_offs);
1587
1588 if (_are_any_hardreset_lines_asserted(oh))
1589 return 0;
1590
1591 v = _omap4_wait_target_disable(oh);
1592 if (v)
1593 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
1594 oh->name);
1595
1596 return 0;
1597}
1598
1599/**
1381 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit 1600 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
1382 * @oh: struct omap_hwmod * 1601 * @oh: struct omap_hwmod *
1383 * 1602 *
1384 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be 1603 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be
1385 * enabled for this to work. Returns -EINVAL if the hwmod cannot be 1604 * enabled for this to work. Returns -ENOENT if the hwmod cannot be
1386 * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if 1605 * reset this way, -EINVAL if the hwmod is in the wrong state,
1387 * the module did not reset in time, or 0 upon success. 1606 * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
1388 * 1607 *
1389 * In OMAP3 a specific SYSSTATUS register is used to get the reset status. 1608 * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
1390 * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead 1609 * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
@@ -1401,7 +1620,7 @@ static int _ocp_softreset(struct omap_hwmod *oh)
1401 1620
1402 if (!oh->class->sysc || 1621 if (!oh->class->sysc ||
1403 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) 1622 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
1404 return -EINVAL; 1623 return -ENOENT;
1405 1624
1406 /* clocks must be on for this operation */ 1625 /* clocks must be on for this operation */
1407 if (oh->_state != _HWMOD_STATE_ENABLED) { 1626 if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -1462,32 +1681,60 @@ dis_opt_clks:
1462 * _reset - reset an omap_hwmod 1681 * _reset - reset an omap_hwmod
1463 * @oh: struct omap_hwmod * 1682 * @oh: struct omap_hwmod *
1464 * 1683 *
1465 * Resets an omap_hwmod @oh. The default software reset mechanism for 1684 * Resets an omap_hwmod @oh. If the module has a custom reset
1466 * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET 1685 * function pointer defined, then call it to reset the IP block, and
1467 * bit. However, some hwmods cannot be reset via this method: some 1686 * pass along its return value to the caller. Otherwise, if the IP
1468 * are not targets and therefore have no OCP header registers to 1687 * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield
1469 * access; others (like the IVA) have idiosyncratic reset sequences. 1688 * associated with it, call a function to reset the IP block via that
1470 * So for these relatively rare cases, custom reset code can be 1689 * method, and pass along the return value to the caller. Finally, if
1471 * supplied in the struct omap_hwmod_class .reset function pointer. 1690 * the IP block has some hardreset lines associated with it, assert
1472 * Passes along the return value from either _reset() or the custom 1691 * all of those, but do _not_ deassert them. (This is because driver
1473 * reset function - these must return -EINVAL if the hwmod cannot be 1692 * authors have expressed an apparent requirement to control the
1474 * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if 1693 * deassertion of the hardreset lines themselves.)
1475 * the module did not reset in time, or 0 upon success. 1694 *
1695 * The default software reset mechanism for most OMAP IP blocks is
1696 * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some
1697 * hwmods cannot be reset via this method. Some are not targets and
1698 * therefore have no OCP header registers to access. Others (like the
1699 * IVA) have idiosyncratic reset sequences. So for these relatively
1700 * rare cases, custom reset code can be supplied in the struct
1701 * omap_hwmod_class .reset function pointer. Passes along the return
1702 * value from either _ocp_softreset() or the custom reset function -
1703 * these must return -EINVAL if the hwmod cannot be reset this way or
1704 * if the hwmod is in the wrong state, -ETIMEDOUT if the module did
1705 * not reset in time, or 0 upon success.
1476 */ 1706 */
1477static int _reset(struct omap_hwmod *oh) 1707static int _reset(struct omap_hwmod *oh)
1478{ 1708{
1479 int ret; 1709 int i, r;
1480 1710
1481 pr_debug("omap_hwmod: %s: resetting\n", oh->name); 1711 pr_debug("omap_hwmod: %s: resetting\n", oh->name);
1482 1712
1483 ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); 1713 if (oh->class->reset) {
1714 r = oh->class->reset(oh);
1715 } else {
1716 if (oh->rst_lines_cnt > 0) {
1717 for (i = 0; i < oh->rst_lines_cnt; i++)
1718 _assert_hardreset(oh, oh->rst_lines[i].name);
1719 return 0;
1720 } else {
1721 r = _ocp_softreset(oh);
1722 if (r == -ENOENT)
1723 r = 0;
1724 }
1725 }
1484 1726
1727 /*
1728 * OCP_SYSCONFIG bits need to be reprogrammed after a
1729 * softreset. The _enable() function should be split to avoid
1730 * the rewrite of the OCP_SYSCONFIG register.
1731 */
1485 if (oh->class->sysc) { 1732 if (oh->class->sysc) {
1486 _update_sysc_cache(oh); 1733 _update_sysc_cache(oh);
1487 _enable_sysc(oh); 1734 _enable_sysc(oh);
1488 } 1735 }
1489 1736
1490 return ret; 1737 return r;
1491} 1738}
1492 1739
1493/** 1740/**
@@ -1506,10 +1753,9 @@ static int _enable(struct omap_hwmod *oh)
1506 pr_debug("omap_hwmod: %s: enabling\n", oh->name); 1753 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1507 1754
1508 /* 1755 /*
1509 * hwmods with HWMOD_INIT_NO_IDLE flag set are left 1756 * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
1510 * in enabled state at init. 1757 * state at init. Now that someone is really trying to enable
1511 * Now that someone is really trying to enable them, 1758 * them, just ensure that the hwmod mux is set.
1512 * just ensure that the hwmod mux is set.
1513 */ 1759 */
1514 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { 1760 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
1515 /* 1761 /*
@@ -1532,15 +1778,17 @@ static int _enable(struct omap_hwmod *oh)
1532 return -EINVAL; 1778 return -EINVAL;
1533 } 1779 }
1534 1780
1535
1536 /* 1781 /*
1537 * If an IP contains only one HW reset line, then de-assert it in order 1782 * If an IP block contains HW reset lines and any of them are
1538 * to allow the module state transition. Otherwise the PRCM will return 1783 * asserted, we let integration code associated with that
1539 * Intransition status, and the init will failed. 1784 * block handle the enable. We've received very little
1785 * information on what those driver authors need, and until
1786 * detailed information is provided and the driver code is
1787 * posted to the public lists, this is probably the best we
1788 * can do.
1540 */ 1789 */
1541 if ((oh->_state == _HWMOD_STATE_INITIALIZED || 1790 if (_are_any_hardreset_lines_asserted(oh))
1542 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) 1791 return 0;
1543 _deassert_hardreset(oh, oh->rst_lines[0].name);
1544 1792
1545 /* Mux pins for device runtime if populated */ 1793 /* Mux pins for device runtime if populated */
1546 if (oh->mux && (!oh->mux->enabled || 1794 if (oh->mux && (!oh->mux->enabled ||
@@ -1615,6 +1863,9 @@ static int _idle(struct omap_hwmod *oh)
1615 return -EINVAL; 1863 return -EINVAL;
1616 } 1864 }
1617 1865
1866 if (_are_any_hardreset_lines_asserted(oh))
1867 return 0;
1868
1618 if (oh->class->sysc) 1869 if (oh->class->sysc)
1619 _idle_sysc(oh); 1870 _idle_sysc(oh);
1620 _del_initiator_dep(oh, mpu_oh); 1871 _del_initiator_dep(oh, mpu_oh);
@@ -1687,7 +1938,7 @@ int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
1687 */ 1938 */
1688static int _shutdown(struct omap_hwmod *oh) 1939static int _shutdown(struct omap_hwmod *oh)
1689{ 1940{
1690 int ret; 1941 int ret, i;
1691 u8 prev_state; 1942 u8 prev_state;
1692 1943
1693 if (oh->_state != _HWMOD_STATE_IDLE && 1944 if (oh->_state != _HWMOD_STATE_IDLE &&
@@ -1697,6 +1948,9 @@ static int _shutdown(struct omap_hwmod *oh)
1697 return -EINVAL; 1948 return -EINVAL;
1698 } 1949 }
1699 1950
1951 if (_are_any_hardreset_lines_asserted(oh))
1952 return 0;
1953
1700 pr_debug("omap_hwmod: %s: disabling\n", oh->name); 1954 pr_debug("omap_hwmod: %s: disabling\n", oh->name);
1701 1955
1702 if (oh->class->pre_shutdown) { 1956 if (oh->class->pre_shutdown) {
@@ -1728,12 +1982,8 @@ static int _shutdown(struct omap_hwmod *oh)
1728 } 1982 }
1729 /* XXX Should this code also force-disable the optional clocks? */ 1983 /* XXX Should this code also force-disable the optional clocks? */
1730 1984
1731 /* 1985 for (i = 0; i < oh->rst_lines_cnt; i++)
1732 * If an IP contains only one HW reset line, then assert it 1986 _assert_hardreset(oh, oh->rst_lines[i].name);
1733 * after disabling the clocks and before shutting down the IP.
1734 */
1735 if (oh->rst_lines_cnt == 1)
1736 _assert_hardreset(oh, oh->rst_lines[0].name);
1737 1987
1738 /* Mux pins to safe mode or use populated off mode values */ 1988 /* Mux pins to safe mode or use populated off mode values */
1739 if (oh->mux) 1989 if (oh->mux)
@@ -1745,59 +1995,186 @@ static int _shutdown(struct omap_hwmod *oh)
1745} 1995}
1746 1996
1747/** 1997/**
1748 * _setup - do initial configuration of omap_hwmod 1998 * _init_mpu_rt_base - populate the virtual address for a hwmod
1749 * @oh: struct omap_hwmod * 1999 * @oh: struct omap_hwmod * to locate the virtual address
1750 * 2000 *
1751 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh 2001 * Cache the virtual address used by the MPU to access this IP block's
1752 * OCP_SYSCONFIG register. Returns 0. 2002 * registers. This address is needed early so the OCP registers that
2003 * are part of the device's address space can be ioremapped properly.
2004 * No return value.
1753 */ 2005 */
1754static int _setup(struct omap_hwmod *oh, void *data) 2006static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
1755{ 2007{
1756 int i, r; 2008 struct omap_hwmod_addr_space *mem;
1757 u8 postsetup_state; 2009 void __iomem *va_start;
2010
2011 if (!oh)
2012 return;
2013
2014 _save_mpu_port_index(oh);
1758 2015
1759 if (oh->_state != _HWMOD_STATE_CLKS_INITED) 2016 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
2017 return;
2018
2019 mem = _find_mpu_rt_addr_space(oh);
2020 if (!mem) {
2021 pr_debug("omap_hwmod: %s: no MPU register target found\n",
2022 oh->name);
2023 return;
2024 }
2025
2026 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
2027 if (!va_start) {
2028 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
2029 return;
2030 }
2031
2032 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
2033 oh->name, va_start);
2034
2035 oh->_mpu_rt_va = va_start;
2036}
2037
2038/**
2039 * _init - initialize internal data for the hwmod @oh
2040 * @oh: struct omap_hwmod *
2041 * @n: (unused)
2042 *
2043 * Look up the clocks and the address space used by the MPU to access
2044 * registers belonging to the hwmod @oh. @oh must already be
2045 * registered at this point. This is the first of two phases for
2046 * hwmod initialization. Code called here does not touch any hardware
2047 * registers, it simply prepares internal data structures. Returns 0
2048 * upon success or if the hwmod isn't registered, or -EINVAL upon
2049 * failure.
2050 */
2051static int __init _init(struct omap_hwmod *oh, void *data)
2052{
2053 int r;
2054
2055 if (oh->_state != _HWMOD_STATE_REGISTERED)
1760 return 0; 2056 return 0;
1761 2057
1762 /* Set iclk autoidle mode */ 2058 _init_mpu_rt_base(oh, NULL);
1763 if (oh->slaves_cnt > 0) {
1764 for (i = 0; i < oh->slaves_cnt; i++) {
1765 struct omap_hwmod_ocp_if *os = oh->slaves[i];
1766 struct clk *c = os->_clk;
1767 2059
1768 if (!c) 2060 r = _init_clocks(oh, NULL);
1769 continue; 2061 if (IS_ERR_VALUE(r)) {
2062 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
2063 return -EINVAL;
2064 }
1770 2065
1771 if (os->flags & OCPIF_SWSUP_IDLE) { 2066 oh->_state = _HWMOD_STATE_INITIALIZED;
1772 /* XXX omap_iclk_deny_idle(c); */ 2067
1773 } else { 2068 return 0;
1774 /* XXX omap_iclk_allow_idle(c); */ 2069}
1775 clk_enable(c); 2070
1776 } 2071/**
2072 * _setup_iclk_autoidle - configure an IP block's interface clocks
2073 * @oh: struct omap_hwmod *
2074 *
2075 * Set up the module's interface clocks. XXX This function is still mostly
2076 * a stub; implementing this properly requires iclk autoidle usecounting in
2077 * the clock code. No return value.
2078 */
2079static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
2080{
2081 struct omap_hwmod_ocp_if *os;
2082 struct list_head *p;
2083 int i = 0;
2084 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2085 return;
2086
2087 p = oh->slave_ports.next;
2088
2089 while (i < oh->slaves_cnt) {
2090 os = _fetch_next_ocp_if(&p, &i);
2091 if (!os->_clk)
2092 continue;
2093
2094 if (os->flags & OCPIF_SWSUP_IDLE) {
2095 /* XXX omap_iclk_deny_idle(c); */
2096 } else {
2097 /* XXX omap_iclk_allow_idle(c); */
2098 clk_enable(os->_clk);
1777 } 2099 }
1778 } 2100 }
1779 2101
1780 oh->_state = _HWMOD_STATE_INITIALIZED; 2102 return;
2103}
1781 2104
1782 /* 2105/**
1783 * In the case of hwmod with hardreset that should not be 2106 * _setup_reset - reset an IP block during the setup process
1784 * de-assert at boot time, we have to keep the module 2107 * @oh: struct omap_hwmod *
1785 * initialized, because we cannot enable it properly with the 2108 *
1786 * reset asserted. Exit without warning because that behavior is 2109 * Reset the IP block corresponding to the hwmod @oh during the setup
1787 * expected. 2110 * process. The IP block is first enabled so it can be successfully
1788 */ 2111 * reset. Returns 0 upon success or a negative error code upon
1789 if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) 2112 * failure.
1790 return 0; 2113 */
2114static int __init _setup_reset(struct omap_hwmod *oh)
2115{
2116 int r;
1791 2117
1792 r = _enable(oh); 2118 if (oh->_state != _HWMOD_STATE_INITIALIZED)
1793 if (r) { 2119 return -EINVAL;
1794 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", 2120
1795 oh->name, oh->_state); 2121 if (oh->rst_lines_cnt == 0) {
1796 return 0; 2122 r = _enable(oh);
2123 if (r) {
2124 pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
2125 oh->name, oh->_state);
2126 return -EINVAL;
2127 }
1797 } 2128 }
1798 2129
1799 if (!(oh->flags & HWMOD_INIT_NO_RESET)) 2130 if (!(oh->flags & HWMOD_INIT_NO_RESET))
1800 _reset(oh); 2131 r = _reset(oh);
2132
2133 return r;
2134}
2135
2136/**
2137 * _setup_postsetup - transition to the appropriate state after _setup
2138 * @oh: struct omap_hwmod *
2139 *
2140 * Place an IP block represented by @oh into a "post-setup" state --
2141 * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that
2142 * this function is called at the end of _setup().) The postsetup
2143 * state for an IP block can be changed by calling
2144 * omap_hwmod_enter_postsetup_state() early in the boot process,
2145 * before one of the omap_hwmod_setup*() functions are called for the
2146 * IP block.
2147 *
2148 * The IP block stays in this state until a PM runtime-based driver is
2149 * loaded for that IP block. A post-setup state of IDLE is
2150 * appropriate for almost all IP blocks with runtime PM-enabled
2151 * drivers, since those drivers are able to enable the IP block. A
2152 * post-setup state of ENABLED is appropriate for kernels with PM
2153 * runtime disabled. The DISABLED state is appropriate for unusual IP
2154 * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers
2155 * included, since the WDTIMER starts running on reset and will reset
2156 * the MPU if left active.
2157 *
2158 * This post-setup mechanism is deprecated. Once all of the OMAP
2159 * drivers have been converted to use PM runtime, and all of the IP
2160 * block data and interconnect data is available to the hwmod code, it
2161 * should be possible to replace this mechanism with a "lazy reset"
2162 * arrangement. In a "lazy reset" setup, each IP block is enabled
2163 * when the driver first probes, then all remaining IP blocks without
2164 * drivers are either shut down or enabled after the drivers have
2165 * loaded. However, this cannot take place until the above
2166 * preconditions have been met, since otherwise the late reset code
2167 * has no way of knowing which IP blocks are in use by drivers, and
2168 * which ones are unused.
2169 *
2170 * No return value.
2171 */
2172static void __init _setup_postsetup(struct omap_hwmod *oh)
2173{
2174 u8 postsetup_state;
2175
2176 if (oh->rst_lines_cnt > 0)
2177 return;
1801 2178
1802 postsetup_state = oh->_postsetup_state; 2179 postsetup_state = oh->_postsetup_state;
1803 if (postsetup_state == _HWMOD_STATE_UNKNOWN) 2180 if (postsetup_state == _HWMOD_STATE_UNKNOWN)
@@ -1821,6 +2198,35 @@ static int _setup(struct omap_hwmod *oh, void *data)
1821 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", 2198 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
1822 oh->name, postsetup_state); 2199 oh->name, postsetup_state);
1823 2200
2201 return;
2202}
2203
2204/**
2205 * _setup - prepare IP block hardware for use
2206 * @oh: struct omap_hwmod *
2207 * @n: (unused, pass NULL)
2208 *
2209 * Configure the IP block represented by @oh. This may include
2210 * enabling the IP block, resetting it, and placing it into a
2211 * post-setup state, depending on the type of IP block and applicable
2212 * flags. IP blocks are reset to prevent any previous configuration
2213 * by the bootloader or previous operating system from interfering
2214 * with power management or other parts of the system. The reset can
2215 * be avoided; see omap_hwmod_no_setup_reset(). This is the second of
2216 * two phases for hwmod initialization. Code called here generally
2217 * affects the IP block hardware, or system integration hardware
2218 * associated with the IP block. Returns 0.
2219 */
2220static int __init _setup(struct omap_hwmod *oh, void *data)
2221{
2222 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2223 return 0;
2224
2225 _setup_iclk_autoidle(oh);
2226
2227 if (!_setup_reset(oh))
2228 _setup_postsetup(oh);
2229
1824 return 0; 2230 return 0;
1825} 2231}
1826 2232
@@ -1843,8 +2249,6 @@ static int _setup(struct omap_hwmod *oh, void *data)
1843 */ 2249 */
1844static int __init _register(struct omap_hwmod *oh) 2250static int __init _register(struct omap_hwmod *oh)
1845{ 2251{
1846 int ms_id;
1847
1848 if (!oh || !oh->name || !oh->class || !oh->class->name || 2252 if (!oh || !oh->name || !oh->class || !oh->class->name ||
1849 (oh->_state != _HWMOD_STATE_UNKNOWN)) 2253 (oh->_state != _HWMOD_STATE_UNKNOWN))
1850 return -EINVAL; 2254 return -EINVAL;
@@ -1854,14 +2258,10 @@ static int __init _register(struct omap_hwmod *oh)
1854 if (_lookup(oh->name)) 2258 if (_lookup(oh->name))
1855 return -EEXIST; 2259 return -EEXIST;
1856 2260
1857 ms_id = _find_mpu_port_index(oh);
1858 if (!IS_ERR_VALUE(ms_id))
1859 oh->_mpu_port_index = ms_id;
1860 else
1861 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
1862
1863 list_add_tail(&oh->node, &omap_hwmod_list); 2261 list_add_tail(&oh->node, &omap_hwmod_list);
1864 2262
2263 INIT_LIST_HEAD(&oh->master_ports);
2264 INIT_LIST_HEAD(&oh->slave_ports);
1865 spin_lock_init(&oh->_lock); 2265 spin_lock_init(&oh->_lock);
1866 2266
1867 oh->_state = _HWMOD_STATE_REGISTERED; 2267 oh->_state = _HWMOD_STATE_REGISTERED;
@@ -1876,6 +2276,160 @@ static int __init _register(struct omap_hwmod *oh)
1876 return 0; 2276 return 0;
1877} 2277}
1878 2278
2279/**
2280 * _alloc_links - return allocated memory for hwmod links
2281 * @ml: pointer to a struct omap_hwmod_link * for the master link
2282 * @sl: pointer to a struct omap_hwmod_link * for the slave link
2283 *
2284 * Return pointers to two struct omap_hwmod_link records, via the
2285 * addresses pointed to by @ml and @sl. Will first attempt to return
2286 * memory allocated as part of a large initial block, but if that has
2287 * been exhausted, will allocate memory itself. Since ideally this
2288 * second allocation path will never occur, the number of these
2289 * 'supplemental' allocations will be logged when debugging is
2290 * enabled. Returns 0.
2291 */
2292static int __init _alloc_links(struct omap_hwmod_link **ml,
2293 struct omap_hwmod_link **sl)
2294{
2295 unsigned int sz;
2296
2297 if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) {
2298 *ml = &linkspace[free_ls++];
2299 *sl = &linkspace[free_ls++];
2300 return 0;
2301 }
2302
2303 sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
2304
2305 *sl = NULL;
2306 *ml = alloc_bootmem(sz);
2307
2308 memset(*ml, 0, sz);
2309
2310 *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
2311
2312 ls_supp++;
2313 pr_debug("omap_hwmod: supplemental link allocations needed: %d\n",
2314 ls_supp * LINKS_PER_OCP_IF);
2315
2316 return 0;
2317};
2318
2319/**
2320 * _add_link - add an interconnect between two IP blocks
2321 * @oi: pointer to a struct omap_hwmod_ocp_if record
2322 *
2323 * Add struct omap_hwmod_link records connecting the master IP block
2324 * specified in @oi->master to @oi, and connecting the slave IP block
2325 * specified in @oi->slave to @oi. This code is assumed to run before
2326 * preemption or SMP has been enabled, thus avoiding the need for
2327 * locking in this code. Changes to this assumption will require
2328 * additional locking. Returns 0.
2329 */
2330static int __init _add_link(struct omap_hwmod_ocp_if *oi)
2331{
2332 struct omap_hwmod_link *ml, *sl;
2333
2334 pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
2335 oi->slave->name);
2336
2337 _alloc_links(&ml, &sl);
2338
2339 ml->ocp_if = oi;
2340 INIT_LIST_HEAD(&ml->node);
2341 list_add(&ml->node, &oi->master->master_ports);
2342 oi->master->masters_cnt++;
2343
2344 sl->ocp_if = oi;
2345 INIT_LIST_HEAD(&sl->node);
2346 list_add(&sl->node, &oi->slave->slave_ports);
2347 oi->slave->slaves_cnt++;
2348
2349 return 0;
2350}
2351
2352/**
2353 * _register_link - register a struct omap_hwmod_ocp_if
2354 * @oi: struct omap_hwmod_ocp_if *
2355 *
2356 * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it
2357 * has already been registered; -EINVAL if @oi is NULL or if the
2358 * record pointed to by @oi is missing required fields; or 0 upon
2359 * success.
2360 *
2361 * XXX The data should be copied into bootmem, so the original data
2362 * should be marked __initdata and freed after init. This would allow
2363 * unneeded omap_hwmods to be freed on multi-OMAP configurations.
2364 */
2365static int __init _register_link(struct omap_hwmod_ocp_if *oi)
2366{
2367 if (!oi || !oi->master || !oi->slave || !oi->user)
2368 return -EINVAL;
2369
2370 if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
2371 return -EEXIST;
2372
2373 pr_debug("omap_hwmod: registering link from %s to %s\n",
2374 oi->master->name, oi->slave->name);
2375
2376 /*
2377 * Register the connected hwmods, if they haven't been
2378 * registered already
2379 */
2380 if (oi->master->_state != _HWMOD_STATE_REGISTERED)
2381 _register(oi->master);
2382
2383 if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
2384 _register(oi->slave);
2385
2386 _add_link(oi);
2387
2388 oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
2389
2390 return 0;
2391}
2392
2393/**
2394 * _alloc_linkspace - allocate large block of hwmod links
2395 * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count
2396 *
2397 * Allocate a large block of struct omap_hwmod_link records. This
2398 * improves boot time significantly by avoiding the need to allocate
2399 * individual records one by one. If the number of records to
2400 * allocate in the block hasn't been manually specified, this function
2401 * will count the number of struct omap_hwmod_ocp_if records in @ois
2402 * and use that to determine the allocation size. For SoC families
2403 * that require multiple list registrations, such as OMAP3xxx, this
2404 * estimation process isn't optimal, so manual estimation is advised
2405 * in those cases. Returns -EEXIST if the allocation has already occurred
2406 * or 0 upon success.
2407 */
2408static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
2409{
2410 unsigned int i = 0;
2411 unsigned int sz;
2412
2413 if (linkspace) {
2414 WARN(1, "linkspace already allocated\n");
2415 return -EEXIST;
2416 }
2417
2418 if (max_ls == 0)
2419 while (ois[i++])
2420 max_ls += LINKS_PER_OCP_IF;
2421
2422 sz = sizeof(struct omap_hwmod_link) * max_ls;
2423
2424 pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
2425 __func__, sz, max_ls);
2426
2427 linkspace = alloc_bootmem(sz);
2428
2429 memset(linkspace, 0, sz);
2430
2431 return 0;
2432}
1879 2433
1880/* Public functions */ 2434/* Public functions */
1881 2435
@@ -2004,120 +2558,101 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
2004} 2558}
2005 2559
2006/** 2560/**
2007 * omap_hwmod_register - register an array of hwmods 2561 * omap_hwmod_register_links - register an array of hwmod links
2008 * @ohs: pointer to an array of omap_hwmods to register 2562 * @ois: pointer to an array of omap_hwmod_ocp_if to register
2009 * 2563 *
2010 * Intended to be called early in boot before the clock framework is 2564 * Intended to be called early in boot before the clock framework is
2011 * initialized. If @ohs is not null, will register all omap_hwmods 2565 * initialized. If @ois is not null, will register all omap_hwmods
2012 * listed in @ohs that are valid for this chip. Returns 0. 2566 * listed in @ois that are valid for this chip. Returns 0.
2013 */ 2567 */
2014int __init omap_hwmod_register(struct omap_hwmod **ohs) 2568int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
2015{ 2569{
2016 int r, i; 2570 int r, i;
2017 2571
2018 if (!ohs) 2572 if (!ois)
2019 return 0; 2573 return 0;
2020 2574
2575 if (!linkspace) {
2576 if (_alloc_linkspace(ois)) {
2577 pr_err("omap_hwmod: could not allocate link space\n");
2578 return -ENOMEM;
2579 }
2580 }
2581
2021 i = 0; 2582 i = 0;
2022 do { 2583 do {
2023 r = _register(ohs[i]); 2584 r = _register_link(ois[i]);
2024 WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, 2585 WARN(r && r != -EEXIST,
2025 r); 2586 "omap_hwmod: _register_link(%s -> %s) returned %d\n",
2026 } while (ohs[++i]); 2587 ois[i]->master->name, ois[i]->slave->name, r);
2588 } while (ois[++i]);
2027 2589
2028 return 0; 2590 return 0;
2029} 2591}
2030 2592
2031/* 2593/**
2032 * _populate_mpu_rt_base - populate the virtual address for a hwmod 2594 * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
2595 * @oh: pointer to the hwmod currently being set up (usually not the MPU)
2033 * 2596 *
2034 * Must be called only from omap_hwmod_setup_*() so ioremap works properly. 2597 * If the hwmod data corresponding to the MPU subsystem IP block
2035 * Assumes the caller takes care of locking if needed. 2598 * hasn't been initialized and set up yet, do so now. This must be
2599 * done first since sleep dependencies may be added from other hwmods
2600 * to the MPU. Intended to be called only by omap_hwmod_setup*(). No
2601 * return value.
2036 */ 2602 */
2037static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) 2603static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
2038{ 2604{
2039 if (oh->_state != _HWMOD_STATE_REGISTERED) 2605 if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
2040 return 0; 2606 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
2041 2607 __func__, MPU_INITIATOR_NAME);
2042 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 2608 else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
2043 return 0; 2609 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
2044
2045 oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
2046
2047 return 0;
2048} 2610}
2049 2611
2050/** 2612/**
2051 * omap_hwmod_setup_one - set up a single hwmod 2613 * omap_hwmod_setup_one - set up a single hwmod
2052 * @oh_name: const char * name of the already-registered hwmod to set up 2614 * @oh_name: const char * name of the already-registered hwmod to set up
2053 * 2615 *
2054 * Must be called after omap2_clk_init(). Resolves the struct clk 2616 * Initialize and set up a single hwmod. Intended to be used for a
2055 * names to struct clk pointers for each registered omap_hwmod. Also 2617 * small number of early devices, such as the timer IP blocks used for
2056 * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon 2618 * the scheduler clock. Must be called after omap2_clk_init().
2057 * success. 2619 * Resolves the struct clk names to struct clk pointers for each
2620 * registered omap_hwmod. Also calls _setup() on each hwmod. Returns
2621 * -EINVAL upon error or 0 upon success.
2058 */ 2622 */
2059int __init omap_hwmod_setup_one(const char *oh_name) 2623int __init omap_hwmod_setup_one(const char *oh_name)
2060{ 2624{
2061 struct omap_hwmod *oh; 2625 struct omap_hwmod *oh;
2062 int r;
2063 2626
2064 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); 2627 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
2065 2628
2066 if (!mpu_oh) {
2067 pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
2068 oh_name, MPU_INITIATOR_NAME);
2069 return -EINVAL;
2070 }
2071
2072 oh = _lookup(oh_name); 2629 oh = _lookup(oh_name);
2073 if (!oh) { 2630 if (!oh) {
2074 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); 2631 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
2075 return -EINVAL; 2632 return -EINVAL;
2076 } 2633 }
2077 2634
2078 if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) 2635 _ensure_mpu_hwmod_is_setup(oh);
2079 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
2080
2081 r = _populate_mpu_rt_base(oh, NULL);
2082 if (IS_ERR_VALUE(r)) {
2083 WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
2084 return -EINVAL;
2085 }
2086
2087 r = _init_clocks(oh, NULL);
2088 if (IS_ERR_VALUE(r)) {
2089 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
2090 return -EINVAL;
2091 }
2092 2636
2637 _init(oh, NULL);
2093 _setup(oh, NULL); 2638 _setup(oh, NULL);
2094 2639
2095 return 0; 2640 return 0;
2096} 2641}
2097 2642
2098/** 2643/**
2099 * omap_hwmod_setup - do some post-clock framework initialization 2644 * omap_hwmod_setup_all - set up all registered IP blocks
2100 * 2645 *
2101 * Must be called after omap2_clk_init(). Resolves the struct clk names 2646 * Initialize and set up all IP blocks registered with the hwmod code.
2102 * to struct clk pointers for each registered omap_hwmod. Also calls 2647 * Must be called after omap2_clk_init(). Resolves the struct clk
2103 * _setup() on each hwmod. Returns 0 upon success. 2648 * names to struct clk pointers for each registered omap_hwmod. Also
2649 * calls _setup() on each hwmod. Returns 0 upon success.
2104 */ 2650 */
2105static int __init omap_hwmod_setup_all(void) 2651static int __init omap_hwmod_setup_all(void)
2106{ 2652{
2107 int r; 2653 _ensure_mpu_hwmod_is_setup(NULL);
2108
2109 if (!mpu_oh) {
2110 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
2111 __func__, MPU_INITIATOR_NAME);
2112 return -EINVAL;
2113 }
2114
2115 r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
2116
2117 r = omap_hwmod_for_each(_init_clocks, NULL);
2118 WARN(IS_ERR_VALUE(r),
2119 "omap_hwmod: %s: _init_clocks failed\n", __func__);
2120 2654
2655 omap_hwmod_for_each(_init, NULL);
2121 omap_hwmod_for_each(_setup, NULL); 2656 omap_hwmod_for_each(_setup, NULL);
2122 2657
2123 return 0; 2658 return 0;
@@ -2274,6 +2809,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
2274 return r; 2809 return r;
2275} 2810}
2276 2811
2812/*
2813 * IP block data retrieval functions
2814 */
2815
2277/** 2816/**
2278 * omap_hwmod_count_resources - count number of struct resources needed by hwmod 2817 * omap_hwmod_count_resources - count number of struct resources needed by hwmod
2279 * @oh: struct omap_hwmod * 2818 * @oh: struct omap_hwmod *
@@ -2292,12 +2831,19 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
2292 */ 2831 */
2293int omap_hwmod_count_resources(struct omap_hwmod *oh) 2832int omap_hwmod_count_resources(struct omap_hwmod *oh)
2294{ 2833{
2295 int ret, i; 2834 struct omap_hwmod_ocp_if *os;
2835 struct list_head *p;
2836 int ret;
2837 int i = 0;
2296 2838
2297 ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); 2839 ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
2298 2840
2299 for (i = 0; i < oh->slaves_cnt; i++) 2841 p = oh->slave_ports.next;
2300 ret += _count_ocp_if_addr_spaces(oh->slaves[i]); 2842
2843 while (i < oh->slaves_cnt) {
2844 os = _fetch_next_ocp_if(&p, &i);
2845 ret += _count_ocp_if_addr_spaces(os);
2846 }
2301 2847
2302 return ret; 2848 return ret;
2303} 2849}
@@ -2314,7 +2860,9 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
2314 */ 2860 */
2315int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) 2861int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2316{ 2862{
2317 int i, j, mpu_irqs_cnt, sdma_reqs_cnt; 2863 struct omap_hwmod_ocp_if *os;
2864 struct list_head *p;
2865 int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
2318 int r = 0; 2866 int r = 0;
2319 2867
2320 /* For each IRQ, DMA, memory area, fill in array.*/ 2868 /* For each IRQ, DMA, memory area, fill in array.*/
@@ -2337,11 +2885,11 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2337 r++; 2885 r++;
2338 } 2886 }
2339 2887
2340 for (i = 0; i < oh->slaves_cnt; i++) { 2888 p = oh->slave_ports.next;
2341 struct omap_hwmod_ocp_if *os;
2342 int addr_cnt;
2343 2889
2344 os = oh->slaves[i]; 2890 i = 0;
2891 while (i < oh->slaves_cnt) {
2892 os = _fetch_next_ocp_if(&p, &i);
2345 addr_cnt = _count_ocp_if_addr_spaces(os); 2893 addr_cnt = _count_ocp_if_addr_spaces(os);
2346 2894
2347 for (j = 0; j < addr_cnt; j++) { 2895 for (j = 0; j < addr_cnt; j++) {
@@ -2357,6 +2905,69 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2357} 2905}
2358 2906
2359/** 2907/**
2908 * omap_hwmod_get_resource_byname - fetch IP block integration data by name
2909 * @oh: struct omap_hwmod * to operate on
2910 * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
2911 * @name: pointer to the name of the data to fetch (optional)
2912 * @rsrc: pointer to a struct resource, allocated by the caller
2913 *
2914 * Retrieve MPU IRQ, SDMA request line, or address space start/end
2915 * data for the IP block pointed to by @oh. The data will be filled
2916 * into a struct resource record pointed to by @rsrc. The struct
2917 * resource must be allocated by the caller. When @name is non-null,
2918 * the data associated with the matching entry in the IRQ/SDMA/address
2919 * space hwmod data arrays will be returned. If @name is null, the
2920 * first array entry will be returned. Data order is not meaningful
2921 * in hwmod data, so callers are strongly encouraged to use a non-null
2922 * @name whenever possible to avoid unpredictable effects if hwmod
2923 * data is later added that causes data ordering to change. This
2924 * function is only intended for use by OMAP core code. Device
2925 * drivers should not call this function - the appropriate bus-related
2926 * data accessor functions should be used instead. Returns 0 upon
2927 * success or a negative error code upon error.
2928 */
2929int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
2930 const char *name, struct resource *rsrc)
2931{
2932 int r;
2933 unsigned int irq, dma;
2934 u32 pa_start, pa_end;
2935
2936 if (!oh || !rsrc)
2937 return -EINVAL;
2938
2939 if (type == IORESOURCE_IRQ) {
2940 r = _get_mpu_irq_by_name(oh, name, &irq);
2941 if (r)
2942 return r;
2943
2944 rsrc->start = irq;
2945 rsrc->end = irq;
2946 } else if (type == IORESOURCE_DMA) {
2947 r = _get_sdma_req_by_name(oh, name, &dma);
2948 if (r)
2949 return r;
2950
2951 rsrc->start = dma;
2952 rsrc->end = dma;
2953 } else if (type == IORESOURCE_MEM) {
2954 r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end);
2955 if (r)
2956 return r;
2957
2958 rsrc->start = pa_start;
2959 rsrc->end = pa_end;
2960 } else {
2961 return -EINVAL;
2962 }
2963
2964 rsrc->flags = type;
2965 rsrc->name = name;
2966
2967 return 0;
2968}
2969
2970/**
2360 * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain 2971 * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
2361 * @oh: struct omap_hwmod * 2972 * @oh: struct omap_hwmod *
2362 * 2973 *
@@ -2370,6 +2981,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2370struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) 2981struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
2371{ 2982{
2372 struct clk *c; 2983 struct clk *c;
2984 struct omap_hwmod_ocp_if *oi;
2373 2985
2374 if (!oh) 2986 if (!oh)
2375 return NULL; 2987 return NULL;
@@ -2377,9 +2989,10 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
2377 if (oh->_clk) { 2989 if (oh->_clk) {
2378 c = oh->_clk; 2990 c = oh->_clk;
2379 } else { 2991 } else {
2380 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 2992 oi = _find_mpu_rt_port(oh);
2993 if (!oi)
2381 return NULL; 2994 return NULL;
2382 c = oh->slaves[oh->_mpu_port_index]->_clk; 2995 c = oi->_clk;
2383 } 2996 }
2384 2997
2385 if (!c->clkdm) 2998 if (!c->clkdm)
@@ -2653,10 +3266,10 @@ int omap_hwmod_for_each_by_class(const char *classname,
2653 * @state: state that _setup() should leave the hwmod in 3266 * @state: state that _setup() should leave the hwmod in
2654 * 3267 *
2655 * Sets the hwmod state that @oh will enter at the end of _setup() 3268 * Sets the hwmod state that @oh will enter at the end of _setup()
2656 * (called by omap_hwmod_setup_*()). Only valid to call between 3269 * (called by omap_hwmod_setup_*()). See also the documentation
2657 * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns 3270 * for _setup_postsetup(), above. Returns 0 upon success or
2658 * 0 upon success or -EINVAL if there is a problem with the arguments 3271 * -EINVAL if there is a problem with the arguments or if the hwmod is
2659 * or if the hwmod is in the wrong state. 3272 * in the wrong state.
2660 */ 3273 */
2661int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) 3274int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
2662{ 3275{
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a6bde34e443a..a7640d1b215e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -22,6 +23,7 @@
22#include <plat/dmtimer.h> 23#include <plat/dmtimer.h>
23#include <plat/l3_2xxx.h> 24#include <plat/l3_2xxx.h>
24#include <plat/l4_2xxx.h> 25#include <plat/l4_2xxx.h>
26#include <plat/mmc.h>
25 27
26#include "omap_hwmod_common_data.h" 28#include "omap_hwmod_common_data.h"
27 29
@@ -32,707 +34,329 @@
32/* 34/*
33 * OMAP2420 hardware module integration data 35 * OMAP2420 hardware module integration data
34 * 36 *
35 * ALl of the data in this section should be autogeneratable from the 37 * All of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that 38 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs 39 * is driver-specific or driver-kernel integration-specific belongs
38 * elsewhere. 40 * elsewhere.
39 */ 41 */
40 42
41static struct omap_hwmod omap2420_mpu_hwmod;
42static struct omap_hwmod omap2420_iva_hwmod;
43static struct omap_hwmod omap2420_l3_main_hwmod;
44static struct omap_hwmod omap2420_l4_core_hwmod;
45static struct omap_hwmod omap2420_dss_core_hwmod;
46static struct omap_hwmod omap2420_dss_dispc_hwmod;
47static struct omap_hwmod omap2420_dss_rfbi_hwmod;
48static struct omap_hwmod omap2420_dss_venc_hwmod;
49static struct omap_hwmod omap2420_wd_timer2_hwmod;
50static struct omap_hwmod omap2420_gpio1_hwmod;
51static struct omap_hwmod omap2420_gpio2_hwmod;
52static struct omap_hwmod omap2420_gpio3_hwmod;
53static struct omap_hwmod omap2420_gpio4_hwmod;
54static struct omap_hwmod omap2420_dma_system_hwmod;
55static struct omap_hwmod omap2420_mcspi1_hwmod;
56static struct omap_hwmod omap2420_mcspi2_hwmod;
57
58/* L3 -> L4_CORE interface */
59static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
60 .master = &omap2420_l3_main_hwmod,
61 .slave = &omap2420_l4_core_hwmod,
62 .user = OCP_USER_MPU | OCP_USER_SDMA,
63};
64
65/* MPU -> L3 interface */
66static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
67 .master = &omap2420_mpu_hwmod,
68 .slave = &omap2420_l3_main_hwmod,
69 .user = OCP_USER_MPU,
70};
71
72/* Slave interfaces on the L3 interconnect */
73static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
74 &omap2420_mpu__l3_main,
75};
76
77/* DSS -> l3 */
78static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
79 .master = &omap2420_dss_core_hwmod,
80 .slave = &omap2420_l3_main_hwmod,
81 .fw = {
82 .omap2 = {
83 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
84 .flags = OMAP_FIREWALL_L3,
85 }
86 },
87 .user = OCP_USER_MPU | OCP_USER_SDMA,
88};
89
90/* Master interfaces on the L3 interconnect */
91static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
92 &omap2420_l3_main__l4_core,
93};
94
95/* L3 */
96static struct omap_hwmod omap2420_l3_main_hwmod = {
97 .name = "l3_main",
98 .class = &l3_hwmod_class,
99 .masters = omap2420_l3_main_masters,
100 .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
101 .slaves = omap2420_l3_main_slaves,
102 .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
103 .flags = HWMOD_NO_IDLEST,
104};
105
106static struct omap_hwmod omap2420_l4_wkup_hwmod;
107static struct omap_hwmod omap2420_uart1_hwmod;
108static struct omap_hwmod omap2420_uart2_hwmod;
109static struct omap_hwmod omap2420_uart3_hwmod;
110static struct omap_hwmod omap2420_i2c1_hwmod;
111static struct omap_hwmod omap2420_i2c2_hwmod;
112static struct omap_hwmod omap2420_mcbsp1_hwmod;
113static struct omap_hwmod omap2420_mcbsp2_hwmod;
114
115/* l4 core -> mcspi1 interface */
116static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
117 .master = &omap2420_l4_core_hwmod,
118 .slave = &omap2420_mcspi1_hwmod,
119 .clk = "mcspi1_ick",
120 .addr = omap2_mcspi1_addr_space,
121 .user = OCP_USER_MPU | OCP_USER_SDMA,
122};
123
124/* l4 core -> mcspi2 interface */
125static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
126 .master = &omap2420_l4_core_hwmod,
127 .slave = &omap2420_mcspi2_hwmod,
128 .clk = "mcspi2_ick",
129 .addr = omap2_mcspi2_addr_space,
130 .user = OCP_USER_MPU | OCP_USER_SDMA,
131};
132
133/* L4_CORE -> L4_WKUP interface */
134static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
135 .master = &omap2420_l4_core_hwmod,
136 .slave = &omap2420_l4_wkup_hwmod,
137 .user = OCP_USER_MPU | OCP_USER_SDMA,
138};
139
140/* L4 CORE -> UART1 interface */
141static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
142 .master = &omap2420_l4_core_hwmod,
143 .slave = &omap2420_uart1_hwmod,
144 .clk = "uart1_ick",
145 .addr = omap2xxx_uart1_addr_space,
146 .user = OCP_USER_MPU | OCP_USER_SDMA,
147};
148
149/* L4 CORE -> UART2 interface */
150static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
151 .master = &omap2420_l4_core_hwmod,
152 .slave = &omap2420_uart2_hwmod,
153 .clk = "uart2_ick",
154 .addr = omap2xxx_uart2_addr_space,
155 .user = OCP_USER_MPU | OCP_USER_SDMA,
156};
157
158/* L4 PER -> UART3 interface */
159static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
160 .master = &omap2420_l4_core_hwmod,
161 .slave = &omap2420_uart3_hwmod,
162 .clk = "uart3_ick",
163 .addr = omap2xxx_uart3_addr_space,
164 .user = OCP_USER_MPU | OCP_USER_SDMA,
165};
166
167/* L4 CORE -> I2C1 interface */
168static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
169 .master = &omap2420_l4_core_hwmod,
170 .slave = &omap2420_i2c1_hwmod,
171 .clk = "i2c1_ick",
172 .addr = omap2_i2c1_addr_space,
173 .user = OCP_USER_MPU | OCP_USER_SDMA,
174};
175
176/* L4 CORE -> I2C2 interface */
177static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
178 .master = &omap2420_l4_core_hwmod,
179 .slave = &omap2420_i2c2_hwmod,
180 .clk = "i2c2_ick",
181 .addr = omap2_i2c2_addr_space,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
183};
184
185/* Slave interfaces on the L4_CORE interconnect */
186static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
187 &omap2420_l3_main__l4_core,
188};
189
190/* Master interfaces on the L4_CORE interconnect */
191static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
192 &omap2420_l4_core__l4_wkup,
193 &omap2_l4_core__uart1,
194 &omap2_l4_core__uart2,
195 &omap2_l4_core__uart3,
196 &omap2420_l4_core__i2c1,
197 &omap2420_l4_core__i2c2
198};
199
200/* L4 CORE */
201static struct omap_hwmod omap2420_l4_core_hwmod = {
202 .name = "l4_core",
203 .class = &l4_hwmod_class,
204 .masters = omap2420_l4_core_masters,
205 .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
206 .slaves = omap2420_l4_core_slaves,
207 .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
208 .flags = HWMOD_NO_IDLEST,
209};
210
211/* Slave interfaces on the L4_WKUP interconnect */
212static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
213 &omap2420_l4_core__l4_wkup,
214};
215
216/* Master interfaces on the L4_WKUP interconnect */
217static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
218};
219
220/* L4 WKUP */
221static struct omap_hwmod omap2420_l4_wkup_hwmod = {
222 .name = "l4_wkup",
223 .class = &l4_hwmod_class,
224 .masters = omap2420_l4_wkup_masters,
225 .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
226 .slaves = omap2420_l4_wkup_slaves,
227 .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
228 .flags = HWMOD_NO_IDLEST,
229};
230
231/* Master interfaces on the MPU device */
232static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
233 &omap2420_mpu__l3_main,
234};
235
236/* MPU */
237static struct omap_hwmod omap2420_mpu_hwmod = {
238 .name = "mpu",
239 .class = &mpu_hwmod_class,
240 .main_clk = "mpu_ck",
241 .masters = omap2420_mpu_masters,
242 .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
243};
244
245/* 43/*
246 * IVA1 interface data 44 * IP blocks
247 */ 45 */
248 46
249/* IVA <- L3 interface */ 47/* IVA1 (IVA1) */
250static struct omap_hwmod_ocp_if omap2420_l3__iva = { 48static struct omap_hwmod_class iva1_hwmod_class = {
251 .master = &omap2420_l3_main_hwmod, 49 .name = "iva1",
252 .slave = &omap2420_iva_hwmod,
253 .clk = "iva1_ifck",
254 .user = OCP_USER_MPU | OCP_USER_SDMA,
255}; 50};
256 51
257static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { 52static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
258 &omap2420_l3__iva, 53 { .name = "iva", .rst_shift = 8 },
259}; 54};
260 55
261/*
262 * IVA2 (IVA2)
263 */
264
265static struct omap_hwmod omap2420_iva_hwmod = { 56static struct omap_hwmod omap2420_iva_hwmod = {
266 .name = "iva", 57 .name = "iva",
267 .class = &iva_hwmod_class, 58 .class = &iva1_hwmod_class,
268 .masters = omap2420_iva_masters, 59 .clkdm_name = "iva1_clkdm",
269 .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), 60 .rst_lines = omap2420_iva_resets,
270}; 61 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
271 62 .main_clk = "iva1_ifck",
272/* always-on timers dev attribute */
273static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
274 .timer_capability = OMAP_TIMER_ALWON,
275}; 63};
276 64
277/* pwm timers dev attribute */ 65/* DSP */
278static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 66static struct omap_hwmod_class dsp_hwmod_class = {
279 .timer_capability = OMAP_TIMER_HAS_PWM, 67 .name = "dsp",
280};
281
282/* timer1 */
283static struct omap_hwmod omap2420_timer1_hwmod;
284
285static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
286 {
287 .pa_start = 0x48028000,
288 .pa_end = 0x48028000 + SZ_1K - 1,
289 .flags = ADDR_TYPE_RT
290 },
291 { }
292}; 68};
293 69
294/* l4_wkup -> timer1 */ 70static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
295static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 71 { .name = "logic", .rst_shift = 0 },
296 .master = &omap2420_l4_wkup_hwmod, 72 { .name = "mmu", .rst_shift = 1 },
297 .slave = &omap2420_timer1_hwmod,
298 .clk = "gpt1_ick",
299 .addr = omap2420_timer1_addrs,
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
301}; 73};
302 74
303/* timer1 slave port */ 75static struct omap_hwmod omap2420_dsp_hwmod = {
304static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { 76 .name = "dsp",
305 &omap2420_l4_wkup__timer1, 77 .class = &dsp_hwmod_class,
78 .clkdm_name = "dsp_clkdm",
79 .rst_lines = omap2420_dsp_resets,
80 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
81 .main_clk = "dsp_fck",
306}; 82};
307 83
308/* timer1 hwmod */ 84/* I2C common */
309static struct omap_hwmod omap2420_timer1_hwmod = { 85static struct omap_hwmod_class_sysconfig i2c_sysc = {
310 .name = "timer1", 86 .rev_offs = 0x00,
311 .mpu_irqs = omap2_timer1_mpu_irqs, 87 .sysc_offs = 0x20,
312 .main_clk = "gpt1_fck", 88 .syss_offs = 0x10,
313 .prcm = { 89 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
314 .omap2 = { 90 .sysc_fields = &omap_hwmod_sysc_type1,
315 .prcm_reg_id = 1,
316 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
317 .module_offs = WKUP_MOD,
318 .idlest_reg_id = 1,
319 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
320 },
321 },
322 .dev_attr = &capability_alwon_dev_attr,
323 .slaves = omap2420_timer1_slaves,
324 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
325 .class = &omap2xxx_timer_hwmod_class,
326}; 91};
327 92
328/* timer2 */ 93static struct omap_hwmod_class i2c_class = {
329static struct omap_hwmod omap2420_timer2_hwmod; 94 .name = "i2c",
330 95 .sysc = &i2c_sysc,
331/* l4_core -> timer2 */ 96 .rev = OMAP_I2C_IP_VERSION_1,
332static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { 97 .reset = &omap_i2c_reset,
333 .master = &omap2420_l4_core_hwmod,
334 .slave = &omap2420_timer2_hwmod,
335 .clk = "gpt2_ick",
336 .addr = omap2xxx_timer2_addrs,
337 .user = OCP_USER_MPU | OCP_USER_SDMA,
338}; 98};
339 99
340/* timer2 slave port */ 100static struct omap_i2c_dev_attr i2c_dev_attr = {
341static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { 101 .flags = OMAP_I2C_FLAG_NO_FIFO |
342 &omap2420_l4_core__timer2, 102 OMAP_I2C_FLAG_SIMPLE_CLOCK |
103 OMAP_I2C_FLAG_16BIT_DATA_REG |
104 OMAP_I2C_FLAG_BUS_SHIFT_2,
343}; 105};
344 106
345/* timer2 hwmod */ 107/* I2C1 */
346static struct omap_hwmod omap2420_timer2_hwmod = { 108static struct omap_hwmod omap2420_i2c1_hwmod = {
347 .name = "timer2", 109 .name = "i2c1",
348 .mpu_irqs = omap2_timer2_mpu_irqs, 110 .mpu_irqs = omap2_i2c1_mpu_irqs,
349 .main_clk = "gpt2_fck", 111 .sdma_reqs = omap2_i2c1_sdma_reqs,
112 .main_clk = "i2c1_fck",
350 .prcm = { 113 .prcm = {
351 .omap2 = { 114 .omap2 = {
352 .prcm_reg_id = 1,
353 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
354 .module_offs = CORE_MOD, 115 .module_offs = CORE_MOD,
116 .prcm_reg_id = 1,
117 .module_bit = OMAP2420_EN_I2C1_SHIFT,
355 .idlest_reg_id = 1, 118 .idlest_reg_id = 1,
356 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, 119 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
357 }, 120 },
358 }, 121 },
359 .dev_attr = &capability_alwon_dev_attr, 122 .class = &i2c_class,
360 .slaves = omap2420_timer2_slaves, 123 .dev_attr = &i2c_dev_attr,
361 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), 124 .flags = HWMOD_16BIT_REG,
362 .class = &omap2xxx_timer_hwmod_class,
363};
364
365/* timer3 */
366static struct omap_hwmod omap2420_timer3_hwmod;
367
368/* l4_core -> timer3 */
369static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
370 .master = &omap2420_l4_core_hwmod,
371 .slave = &omap2420_timer3_hwmod,
372 .clk = "gpt3_ick",
373 .addr = omap2xxx_timer3_addrs,
374 .user = OCP_USER_MPU | OCP_USER_SDMA,
375};
376
377/* timer3 slave port */
378static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
379 &omap2420_l4_core__timer3,
380}; 125};
381 126
382/* timer3 hwmod */ 127/* I2C2 */
383static struct omap_hwmod omap2420_timer3_hwmod = { 128static struct omap_hwmod omap2420_i2c2_hwmod = {
384 .name = "timer3", 129 .name = "i2c2",
385 .mpu_irqs = omap2_timer3_mpu_irqs, 130 .mpu_irqs = omap2_i2c2_mpu_irqs,
386 .main_clk = "gpt3_fck", 131 .sdma_reqs = omap2_i2c2_sdma_reqs,
132 .main_clk = "i2c2_fck",
387 .prcm = { 133 .prcm = {
388 .omap2 = { 134 .omap2 = {
389 .prcm_reg_id = 1,
390 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
391 .module_offs = CORE_MOD, 135 .module_offs = CORE_MOD,
136 .prcm_reg_id = 1,
137 .module_bit = OMAP2420_EN_I2C2_SHIFT,
392 .idlest_reg_id = 1, 138 .idlest_reg_id = 1,
393 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 139 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
394 }, 140 },
395 }, 141 },
396 .dev_attr = &capability_alwon_dev_attr, 142 .class = &i2c_class,
397 .slaves = omap2420_timer3_slaves, 143 .dev_attr = &i2c_dev_attr,
398 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), 144 .flags = HWMOD_16BIT_REG,
399 .class = &omap2xxx_timer_hwmod_class,
400}; 145};
401 146
402/* timer4 */ 147/* dma attributes */
403static struct omap_hwmod omap2420_timer4_hwmod; 148static struct omap_dma_dev_attr dma_dev_attr = {
149 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
150 IS_CSSA_32 | IS_CDSA_32,
151 .lch_count = 32,
152};
404 153
405/* l4_core -> timer4 */ 154static struct omap_hwmod omap2420_dma_system_hwmod = {
406static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { 155 .name = "dma",
407 .master = &omap2420_l4_core_hwmod, 156 .class = &omap2xxx_dma_hwmod_class,
408 .slave = &omap2420_timer4_hwmod, 157 .mpu_irqs = omap2_dma_system_irqs,
409 .clk = "gpt4_ick", 158 .main_clk = "core_l3_ck",
410 .addr = omap2xxx_timer4_addrs, 159 .dev_attr = &dma_dev_attr,
411 .user = OCP_USER_MPU | OCP_USER_SDMA, 160 .flags = HWMOD_NO_IDLEST,
412}; 161};
413 162
414/* timer4 slave port */ 163/* mailbox */
415static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { 164static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
416 &omap2420_l4_core__timer4, 165 { .name = "dsp", .irq = 26 },
166 { .name = "iva", .irq = 34 },
167 { .irq = -1 }
417}; 168};
418 169
419/* timer4 hwmod */ 170static struct omap_hwmod omap2420_mailbox_hwmod = {
420static struct omap_hwmod omap2420_timer4_hwmod = { 171 .name = "mailbox",
421 .name = "timer4", 172 .class = &omap2xxx_mailbox_hwmod_class,
422 .mpu_irqs = omap2_timer4_mpu_irqs, 173 .mpu_irqs = omap2420_mailbox_irqs,
423 .main_clk = "gpt4_fck", 174 .main_clk = "mailboxes_ick",
424 .prcm = { 175 .prcm = {
425 .omap2 = { 176 .omap2 = {
426 .prcm_reg_id = 1, 177 .prcm_reg_id = 1,
427 .module_bit = OMAP24XX_EN_GPT4_SHIFT, 178 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
428 .module_offs = CORE_MOD, 179 .module_offs = CORE_MOD,
429 .idlest_reg_id = 1, 180 .idlest_reg_id = 1,
430 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, 181 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
431 }, 182 },
432 }, 183 },
433 .dev_attr = &capability_alwon_dev_attr,
434 .slaves = omap2420_timer4_slaves,
435 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
436 .class = &omap2xxx_timer_hwmod_class,
437}; 184};
438 185
439/* timer5 */ 186/*
440static struct omap_hwmod omap2420_timer5_hwmod; 187 * 'mcbsp' class
188 * multi channel buffered serial port controller
189 */
441 190
442/* l4_core -> timer5 */ 191static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
443static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { 192 .name = "mcbsp",
444 .master = &omap2420_l4_core_hwmod,
445 .slave = &omap2420_timer5_hwmod,
446 .clk = "gpt5_ick",
447 .addr = omap2xxx_timer5_addrs,
448 .user = OCP_USER_MPU | OCP_USER_SDMA,
449}; 193};
450 194
451/* timer5 slave port */ 195/* mcbsp1 */
452static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { 196static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
453 &omap2420_l4_core__timer5, 197 { .name = "tx", .irq = 59 },
198 { .name = "rx", .irq = 60 },
199 { .irq = -1 }
454}; 200};
455 201
456/* timer5 hwmod */ 202static struct omap_hwmod omap2420_mcbsp1_hwmod = {
457static struct omap_hwmod omap2420_timer5_hwmod = { 203 .name = "mcbsp1",
458 .name = "timer5", 204 .class = &omap2420_mcbsp_hwmod_class,
459 .mpu_irqs = omap2_timer5_mpu_irqs, 205 .mpu_irqs = omap2420_mcbsp1_irqs,
460 .main_clk = "gpt5_fck", 206 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
207 .main_clk = "mcbsp1_fck",
461 .prcm = { 208 .prcm = {
462 .omap2 = { 209 .omap2 = {
463 .prcm_reg_id = 1, 210 .prcm_reg_id = 1,
464 .module_bit = OMAP24XX_EN_GPT5_SHIFT, 211 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
465 .module_offs = CORE_MOD, 212 .module_offs = CORE_MOD,
466 .idlest_reg_id = 1, 213 .idlest_reg_id = 1,
467 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 214 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
468 }, 215 },
469 }, 216 },
470 .dev_attr = &capability_alwon_dev_attr,
471 .slaves = omap2420_timer5_slaves,
472 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
473 .class = &omap2xxx_timer_hwmod_class,
474}; 217};
475 218
476 219/* mcbsp2 */
477/* timer6 */ 220static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
478static struct omap_hwmod omap2420_timer6_hwmod; 221 { .name = "tx", .irq = 62 },
479 222 { .name = "rx", .irq = 63 },
480/* l4_core -> timer6 */ 223 { .irq = -1 }
481static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
482 .master = &omap2420_l4_core_hwmod,
483 .slave = &omap2420_timer6_hwmod,
484 .clk = "gpt6_ick",
485 .addr = omap2xxx_timer6_addrs,
486 .user = OCP_USER_MPU | OCP_USER_SDMA,
487};
488
489/* timer6 slave port */
490static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
491 &omap2420_l4_core__timer6,
492}; 224};
493 225
494/* timer6 hwmod */ 226static struct omap_hwmod omap2420_mcbsp2_hwmod = {
495static struct omap_hwmod omap2420_timer6_hwmod = { 227 .name = "mcbsp2",
496 .name = "timer6", 228 .class = &omap2420_mcbsp_hwmod_class,
497 .mpu_irqs = omap2_timer6_mpu_irqs, 229 .mpu_irqs = omap2420_mcbsp2_irqs,
498 .main_clk = "gpt6_fck", 230 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
231 .main_clk = "mcbsp2_fck",
499 .prcm = { 232 .prcm = {
500 .omap2 = { 233 .omap2 = {
501 .prcm_reg_id = 1, 234 .prcm_reg_id = 1,
502 .module_bit = OMAP24XX_EN_GPT6_SHIFT, 235 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
503 .module_offs = CORE_MOD, 236 .module_offs = CORE_MOD,
504 .idlest_reg_id = 1, 237 .idlest_reg_id = 1,
505 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 238 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
506 }, 239 },
507 }, 240 },
508 .dev_attr = &capability_alwon_dev_attr,
509 .slaves = omap2420_timer6_slaves,
510 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
511 .class = &omap2xxx_timer_hwmod_class,
512}; 241};
513 242
514/* timer7 */ 243static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
515static struct omap_hwmod omap2420_timer7_hwmod; 244 .rev_offs = 0x3c,
516 245 .sysc_offs = 0x64,
517/* l4_core -> timer7 */ 246 .syss_offs = 0x68,
518static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { 247 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
519 .master = &omap2420_l4_core_hwmod, 248 .sysc_fields = &omap_hwmod_sysc_type1,
520 .slave = &omap2420_timer7_hwmod,
521 .clk = "gpt7_ick",
522 .addr = omap2xxx_timer7_addrs,
523 .user = OCP_USER_MPU | OCP_USER_SDMA,
524};
525
526/* timer7 slave port */
527static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
528 &omap2420_l4_core__timer7,
529}; 249};
530 250
531/* timer7 hwmod */ 251static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
532static struct omap_hwmod omap2420_timer7_hwmod = { 252 .name = "msdi",
533 .name = "timer7", 253 .sysc = &omap2420_msdi_sysc,
534 .mpu_irqs = omap2_timer7_mpu_irqs, 254 .reset = &omap_msdi_reset,
535 .main_clk = "gpt7_fck",
536 .prcm = {
537 .omap2 = {
538 .prcm_reg_id = 1,
539 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
540 .module_offs = CORE_MOD,
541 .idlest_reg_id = 1,
542 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
543 },
544 },
545 .dev_attr = &capability_alwon_dev_attr,
546 .slaves = omap2420_timer7_slaves,
547 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
548 .class = &omap2xxx_timer_hwmod_class,
549}; 255};
550 256
551/* timer8 */ 257/* msdi1 */
552static struct omap_hwmod omap2420_timer8_hwmod; 258static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
553 259 { .irq = 83 },
554/* l4_core -> timer8 */ 260 { .irq = -1 }
555static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
556 .master = &omap2420_l4_core_hwmod,
557 .slave = &omap2420_timer8_hwmod,
558 .clk = "gpt8_ick",
559 .addr = omap2xxx_timer8_addrs,
560 .user = OCP_USER_MPU | OCP_USER_SDMA,
561}; 261};
562 262
563/* timer8 slave port */ 263static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
564static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { 264 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
565 &omap2420_l4_core__timer8, 265 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
266 { .dma_req = -1 }
566}; 267};
567 268
568/* timer8 hwmod */ 269static struct omap_hwmod omap2420_msdi1_hwmod = {
569static struct omap_hwmod omap2420_timer8_hwmod = { 270 .name = "msdi1",
570 .name = "timer8", 271 .class = &omap2420_msdi_hwmod_class,
571 .mpu_irqs = omap2_timer8_mpu_irqs, 272 .mpu_irqs = omap2420_msdi1_irqs,
572 .main_clk = "gpt8_fck", 273 .sdma_reqs = omap2420_msdi1_sdma_reqs,
274 .main_clk = "mmc_fck",
573 .prcm = { 275 .prcm = {
574 .omap2 = { 276 .omap2 = {
575 .prcm_reg_id = 1, 277 .prcm_reg_id = 1,
576 .module_bit = OMAP24XX_EN_GPT8_SHIFT, 278 .module_bit = OMAP2420_EN_MMC_SHIFT,
577 .module_offs = CORE_MOD, 279 .module_offs = CORE_MOD,
578 .idlest_reg_id = 1, 280 .idlest_reg_id = 1,
579 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 281 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
580 }, 282 },
581 }, 283 },
582 .dev_attr = &capability_alwon_dev_attr, 284 .flags = HWMOD_16BIT_REG,
583 .slaves = omap2420_timer8_slaves,
584 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
585 .class = &omap2xxx_timer_hwmod_class,
586};
587
588/* timer9 */
589static struct omap_hwmod omap2420_timer9_hwmod;
590
591/* l4_core -> timer9 */
592static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
593 .master = &omap2420_l4_core_hwmod,
594 .slave = &omap2420_timer9_hwmod,
595 .clk = "gpt9_ick",
596 .addr = omap2xxx_timer9_addrs,
597 .user = OCP_USER_MPU | OCP_USER_SDMA,
598};
599
600/* timer9 slave port */
601static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
602 &omap2420_l4_core__timer9,
603}; 285};
604 286
605/* timer9 hwmod */ 287/* HDQ1W/1-wire */
606static struct omap_hwmod omap2420_timer9_hwmod = { 288static struct omap_hwmod omap2420_hdq1w_hwmod = {
607 .name = "timer9", 289 .name = "hdq1w",
608 .mpu_irqs = omap2_timer9_mpu_irqs, 290 .mpu_irqs = omap2_hdq1w_mpu_irqs,
609 .main_clk = "gpt9_fck", 291 .main_clk = "hdq_fck",
610 .prcm = { 292 .prcm = {
611 .omap2 = { 293 .omap2 = {
612 .prcm_reg_id = 1,
613 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
614 .module_offs = CORE_MOD, 294 .module_offs = CORE_MOD,
295 .prcm_reg_id = 1,
296 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
615 .idlest_reg_id = 1, 297 .idlest_reg_id = 1,
616 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, 298 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
617 }, 299 },
618 }, 300 },
619 .dev_attr = &capability_pwm_dev_attr, 301 .class = &omap2_hdq1w_class,
620 .slaves = omap2420_timer9_slaves,
621 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
622 .class = &omap2xxx_timer_hwmod_class,
623}; 302};
624 303
625/* timer10 */ 304/*
626static struct omap_hwmod omap2420_timer10_hwmod; 305 * interfaces
306 */
627 307
628/* l4_core -> timer10 */ 308/* L4 CORE -> I2C1 interface */
629static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { 309static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
630 .master = &omap2420_l4_core_hwmod, 310 .master = &omap2xxx_l4_core_hwmod,
631 .slave = &omap2420_timer10_hwmod, 311 .slave = &omap2420_i2c1_hwmod,
632 .clk = "gpt10_ick", 312 .clk = "i2c1_ick",
633 .addr = omap2_timer10_addrs, 313 .addr = omap2_i2c1_addr_space,
634 .user = OCP_USER_MPU | OCP_USER_SDMA, 314 .user = OCP_USER_MPU | OCP_USER_SDMA,
635}; 315};
636 316
637/* timer10 slave port */ 317/* L4 CORE -> I2C2 interface */
638static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { 318static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
639 &omap2420_l4_core__timer10, 319 .master = &omap2xxx_l4_core_hwmod,
640}; 320 .slave = &omap2420_i2c2_hwmod,
641 321 .clk = "i2c2_ick",
642/* timer10 hwmod */ 322 .addr = omap2_i2c2_addr_space,
643static struct omap_hwmod omap2420_timer10_hwmod = { 323 .user = OCP_USER_MPU | OCP_USER_SDMA,
644 .name = "timer10",
645 .mpu_irqs = omap2_timer10_mpu_irqs,
646 .main_clk = "gpt10_fck",
647 .prcm = {
648 .omap2 = {
649 .prcm_reg_id = 1,
650 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
651 .module_offs = CORE_MOD,
652 .idlest_reg_id = 1,
653 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
654 },
655 },
656 .dev_attr = &capability_pwm_dev_attr,
657 .slaves = omap2420_timer10_slaves,
658 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
659 .class = &omap2xxx_timer_hwmod_class,
660}; 324};
661 325
662/* timer11 */ 326/* IVA <- L3 interface */
663static struct omap_hwmod omap2420_timer11_hwmod; 327static struct omap_hwmod_ocp_if omap2420_l3__iva = {
664 328 .master = &omap2xxx_l3_main_hwmod,
665/* l4_core -> timer11 */ 329 .slave = &omap2420_iva_hwmod,
666static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { 330 .clk = "core_l3_ck",
667 .master = &omap2420_l4_core_hwmod,
668 .slave = &omap2420_timer11_hwmod,
669 .clk = "gpt11_ick",
670 .addr = omap2_timer11_addrs,
671 .user = OCP_USER_MPU | OCP_USER_SDMA, 331 .user = OCP_USER_MPU | OCP_USER_SDMA,
672}; 332};
673 333
674/* timer11 slave port */ 334/* DSP <- L3 interface */
675static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { 335static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
676 &omap2420_l4_core__timer11, 336 .master = &omap2xxx_l3_main_hwmod,
337 .slave = &omap2420_dsp_hwmod,
338 .clk = "dsp_ick",
339 .user = OCP_USER_MPU | OCP_USER_SDMA,
677}; 340};
678 341
679/* timer11 hwmod */ 342static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
680static struct omap_hwmod omap2420_timer11_hwmod = { 343 {
681 .name = "timer11", 344 .pa_start = 0x48028000,
682 .mpu_irqs = omap2_timer11_mpu_irqs, 345 .pa_end = 0x48028000 + SZ_1K - 1,
683 .main_clk = "gpt11_fck", 346 .flags = ADDR_TYPE_RT
684 .prcm = {
685 .omap2 = {
686 .prcm_reg_id = 1,
687 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
688 .module_offs = CORE_MOD,
689 .idlest_reg_id = 1,
690 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
691 },
692 }, 347 },
693 .dev_attr = &capability_pwm_dev_attr, 348 { }
694 .slaves = omap2420_timer11_slaves,
695 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
696 .class = &omap2xxx_timer_hwmod_class,
697}; 349};
698 350
699/* timer12 */ 351/* l4_wkup -> timer1 */
700static struct omap_hwmod omap2420_timer12_hwmod; 352static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
701 353 .master = &omap2xxx_l4_wkup_hwmod,
702/* l4_core -> timer12 */ 354 .slave = &omap2xxx_timer1_hwmod,
703static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { 355 .clk = "gpt1_ick",
704 .master = &omap2420_l4_core_hwmod, 356 .addr = omap2420_timer1_addrs,
705 .slave = &omap2420_timer12_hwmod,
706 .clk = "gpt12_ick",
707 .addr = omap2xxx_timer12_addrs,
708 .user = OCP_USER_MPU | OCP_USER_SDMA, 357 .user = OCP_USER_MPU | OCP_USER_SDMA,
709}; 358};
710 359
711/* timer12 slave port */
712static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
713 &omap2420_l4_core__timer12,
714};
715
716/* timer12 hwmod */
717static struct omap_hwmod omap2420_timer12_hwmod = {
718 .name = "timer12",
719 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
720 .main_clk = "gpt12_fck",
721 .prcm = {
722 .omap2 = {
723 .prcm_reg_id = 1,
724 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
725 .module_offs = CORE_MOD,
726 .idlest_reg_id = 1,
727 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
728 },
729 },
730 .dev_attr = &capability_pwm_dev_attr,
731 .slaves = omap2420_timer12_slaves,
732 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
733 .class = &omap2xxx_timer_hwmod_class,
734};
735
736/* l4_wkup -> wd_timer2 */ 360/* l4_wkup -> wd_timer2 */
737static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { 361static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
738 { 362 {
@@ -744,363 +368,13 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
744}; 368};
745 369
746static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 370static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
747 .master = &omap2420_l4_wkup_hwmod, 371 .master = &omap2xxx_l4_wkup_hwmod,
748 .slave = &omap2420_wd_timer2_hwmod, 372 .slave = &omap2xxx_wd_timer2_hwmod,
749 .clk = "mpu_wdt_ick", 373 .clk = "mpu_wdt_ick",
750 .addr = omap2420_wd_timer2_addrs, 374 .addr = omap2420_wd_timer2_addrs,
751 .user = OCP_USER_MPU | OCP_USER_SDMA, 375 .user = OCP_USER_MPU | OCP_USER_SDMA,
752}; 376};
753 377
754/* wd_timer2 */
755static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
756 &omap2420_l4_wkup__wd_timer2,
757};
758
759static struct omap_hwmod omap2420_wd_timer2_hwmod = {
760 .name = "wd_timer2",
761 .class = &omap2xxx_wd_timer_hwmod_class,
762 .main_clk = "mpu_wdt_fck",
763 .prcm = {
764 .omap2 = {
765 .prcm_reg_id = 1,
766 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
767 .module_offs = WKUP_MOD,
768 .idlest_reg_id = 1,
769 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
770 },
771 },
772 .slaves = omap2420_wd_timer2_slaves,
773 .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
774};
775
776/* UART1 */
777
778static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
779 &omap2_l4_core__uart1,
780};
781
782static struct omap_hwmod omap2420_uart1_hwmod = {
783 .name = "uart1",
784 .mpu_irqs = omap2_uart1_mpu_irqs,
785 .sdma_reqs = omap2_uart1_sdma_reqs,
786 .main_clk = "uart1_fck",
787 .prcm = {
788 .omap2 = {
789 .module_offs = CORE_MOD,
790 .prcm_reg_id = 1,
791 .module_bit = OMAP24XX_EN_UART1_SHIFT,
792 .idlest_reg_id = 1,
793 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
794 },
795 },
796 .slaves = omap2420_uart1_slaves,
797 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
798 .class = &omap2_uart_class,
799};
800
801/* UART2 */
802
803static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
804 &omap2_l4_core__uart2,
805};
806
807static struct omap_hwmod omap2420_uart2_hwmod = {
808 .name = "uart2",
809 .mpu_irqs = omap2_uart2_mpu_irqs,
810 .sdma_reqs = omap2_uart2_sdma_reqs,
811 .main_clk = "uart2_fck",
812 .prcm = {
813 .omap2 = {
814 .module_offs = CORE_MOD,
815 .prcm_reg_id = 1,
816 .module_bit = OMAP24XX_EN_UART2_SHIFT,
817 .idlest_reg_id = 1,
818 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
819 },
820 },
821 .slaves = omap2420_uart2_slaves,
822 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
823 .class = &omap2_uart_class,
824};
825
826/* UART3 */
827
828static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
829 &omap2_l4_core__uart3,
830};
831
832static struct omap_hwmod omap2420_uart3_hwmod = {
833 .name = "uart3",
834 .mpu_irqs = omap2_uart3_mpu_irqs,
835 .sdma_reqs = omap2_uart3_sdma_reqs,
836 .main_clk = "uart3_fck",
837 .prcm = {
838 .omap2 = {
839 .module_offs = CORE_MOD,
840 .prcm_reg_id = 2,
841 .module_bit = OMAP24XX_EN_UART3_SHIFT,
842 .idlest_reg_id = 2,
843 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
844 },
845 },
846 .slaves = omap2420_uart3_slaves,
847 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
848 .class = &omap2_uart_class,
849};
850
851/* dss */
852/* dss master ports */
853static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
854 &omap2420_dss__l3,
855};
856
857/* l4_core -> dss */
858static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
859 .master = &omap2420_l4_core_hwmod,
860 .slave = &omap2420_dss_core_hwmod,
861 .clk = "dss_ick",
862 .addr = omap2_dss_addrs,
863 .fw = {
864 .omap2 = {
865 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
866 .flags = OMAP_FIREWALL_L4,
867 }
868 },
869 .user = OCP_USER_MPU | OCP_USER_SDMA,
870};
871
872/* dss slave ports */
873static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
874 &omap2420_l4_core__dss,
875};
876
877static struct omap_hwmod_opt_clk dss_opt_clks[] = {
878 /*
879 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
880 * driver does not use these clocks.
881 */
882 { .role = "tv_clk", .clk = "dss_54m_fck" },
883 { .role = "sys_clk", .clk = "dss2_fck" },
884};
885
886static struct omap_hwmod omap2420_dss_core_hwmod = {
887 .name = "dss_core",
888 .class = &omap2_dss_hwmod_class,
889 .main_clk = "dss1_fck", /* instead of dss_fck */
890 .sdma_reqs = omap2xxx_dss_sdma_chs,
891 .prcm = {
892 .omap2 = {
893 .prcm_reg_id = 1,
894 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
895 .module_offs = CORE_MOD,
896 .idlest_reg_id = 1,
897 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
898 },
899 },
900 .opt_clks = dss_opt_clks,
901 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
902 .slaves = omap2420_dss_slaves,
903 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
904 .masters = omap2420_dss_masters,
905 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
906 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
907};
908
909/* l4_core -> dss_dispc */
910static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
911 .master = &omap2420_l4_core_hwmod,
912 .slave = &omap2420_dss_dispc_hwmod,
913 .clk = "dss_ick",
914 .addr = omap2_dss_dispc_addrs,
915 .fw = {
916 .omap2 = {
917 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
918 .flags = OMAP_FIREWALL_L4,
919 }
920 },
921 .user = OCP_USER_MPU | OCP_USER_SDMA,
922};
923
924/* dss_dispc slave ports */
925static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
926 &omap2420_l4_core__dss_dispc,
927};
928
929static struct omap_hwmod omap2420_dss_dispc_hwmod = {
930 .name = "dss_dispc",
931 .class = &omap2_dispc_hwmod_class,
932 .mpu_irqs = omap2_dispc_irqs,
933 .main_clk = "dss1_fck",
934 .prcm = {
935 .omap2 = {
936 .prcm_reg_id = 1,
937 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
938 .module_offs = CORE_MOD,
939 .idlest_reg_id = 1,
940 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
941 },
942 },
943 .slaves = omap2420_dss_dispc_slaves,
944 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
945 .flags = HWMOD_NO_IDLEST,
946 .dev_attr = &omap2_3_dss_dispc_dev_attr
947};
948
949/* l4_core -> dss_rfbi */
950static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
951 .master = &omap2420_l4_core_hwmod,
952 .slave = &omap2420_dss_rfbi_hwmod,
953 .clk = "dss_ick",
954 .addr = omap2_dss_rfbi_addrs,
955 .fw = {
956 .omap2 = {
957 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
958 .flags = OMAP_FIREWALL_L4,
959 }
960 },
961 .user = OCP_USER_MPU | OCP_USER_SDMA,
962};
963
964/* dss_rfbi slave ports */
965static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
966 &omap2420_l4_core__dss_rfbi,
967};
968
969static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
970 { .role = "ick", .clk = "dss_ick" },
971};
972
973static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
974 .name = "dss_rfbi",
975 .class = &omap2_rfbi_hwmod_class,
976 .main_clk = "dss1_fck",
977 .prcm = {
978 .omap2 = {
979 .prcm_reg_id = 1,
980 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
981 .module_offs = CORE_MOD,
982 },
983 },
984 .opt_clks = dss_rfbi_opt_clks,
985 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
986 .slaves = omap2420_dss_rfbi_slaves,
987 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
988 .flags = HWMOD_NO_IDLEST,
989};
990
991/* l4_core -> dss_venc */
992static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
993 .master = &omap2420_l4_core_hwmod,
994 .slave = &omap2420_dss_venc_hwmod,
995 .clk = "dss_ick",
996 .addr = omap2_dss_venc_addrs,
997 .fw = {
998 .omap2 = {
999 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
1000 .flags = OMAP_FIREWALL_L4,
1001 }
1002 },
1003 .user = OCP_USER_MPU | OCP_USER_SDMA,
1004};
1005
1006/* dss_venc slave ports */
1007static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1008 &omap2420_l4_core__dss_venc,
1009};
1010
1011static struct omap_hwmod omap2420_dss_venc_hwmod = {
1012 .name = "dss_venc",
1013 .class = &omap2_venc_hwmod_class,
1014 .main_clk = "dss_54m_fck",
1015 .prcm = {
1016 .omap2 = {
1017 .prcm_reg_id = 1,
1018 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1019 .module_offs = CORE_MOD,
1020 },
1021 },
1022 .slaves = omap2420_dss_venc_slaves,
1023 .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
1024 .flags = HWMOD_NO_IDLEST,
1025};
1026
1027/* I2C common */
1028static struct omap_hwmod_class_sysconfig i2c_sysc = {
1029 .rev_offs = 0x00,
1030 .sysc_offs = 0x20,
1031 .syss_offs = 0x10,
1032 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1033 .sysc_fields = &omap_hwmod_sysc_type1,
1034};
1035
1036static struct omap_hwmod_class i2c_class = {
1037 .name = "i2c",
1038 .sysc = &i2c_sysc,
1039 .rev = OMAP_I2C_IP_VERSION_1,
1040 .reset = &omap_i2c_reset,
1041};
1042
1043static struct omap_i2c_dev_attr i2c_dev_attr = {
1044 .flags = OMAP_I2C_FLAG_NO_FIFO |
1045 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1046 OMAP_I2C_FLAG_16BIT_DATA_REG |
1047 OMAP_I2C_FLAG_BUS_SHIFT_2,
1048};
1049
1050/* I2C1 */
1051
1052static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1053 &omap2420_l4_core__i2c1,
1054};
1055
1056static struct omap_hwmod omap2420_i2c1_hwmod = {
1057 .name = "i2c1",
1058 .mpu_irqs = omap2_i2c1_mpu_irqs,
1059 .sdma_reqs = omap2_i2c1_sdma_reqs,
1060 .main_clk = "i2c1_fck",
1061 .prcm = {
1062 .omap2 = {
1063 .module_offs = CORE_MOD,
1064 .prcm_reg_id = 1,
1065 .module_bit = OMAP2420_EN_I2C1_SHIFT,
1066 .idlest_reg_id = 1,
1067 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1068 },
1069 },
1070 .slaves = omap2420_i2c1_slaves,
1071 .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
1072 .class = &i2c_class,
1073 .dev_attr = &i2c_dev_attr,
1074 .flags = HWMOD_16BIT_REG,
1075};
1076
1077/* I2C2 */
1078
1079static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1080 &omap2420_l4_core__i2c2,
1081};
1082
1083static struct omap_hwmod omap2420_i2c2_hwmod = {
1084 .name = "i2c2",
1085 .mpu_irqs = omap2_i2c2_mpu_irqs,
1086 .sdma_reqs = omap2_i2c2_sdma_reqs,
1087 .main_clk = "i2c2_fck",
1088 .prcm = {
1089 .omap2 = {
1090 .module_offs = CORE_MOD,
1091 .prcm_reg_id = 1,
1092 .module_bit = OMAP2420_EN_I2C2_SHIFT,
1093 .idlest_reg_id = 1,
1094 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1095 },
1096 },
1097 .slaves = omap2420_i2c2_slaves,
1098 .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
1099 .class = &i2c_class,
1100 .dev_attr = &i2c_dev_attr,
1101 .flags = HWMOD_16BIT_REG,
1102};
1103
1104/* l4_wkup -> gpio1 */ 378/* l4_wkup -> gpio1 */
1105static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { 379static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1106 { 380 {
@@ -1112,8 +386,8 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1112}; 386};
1113 387
1114static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 388static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1115 .master = &omap2420_l4_wkup_hwmod, 389 .master = &omap2xxx_l4_wkup_hwmod,
1116 .slave = &omap2420_gpio1_hwmod, 390 .slave = &omap2xxx_gpio1_hwmod,
1117 .clk = "gpios_ick", 391 .clk = "gpios_ick",
1118 .addr = omap2420_gpio1_addr_space, 392 .addr = omap2420_gpio1_addr_space,
1119 .user = OCP_USER_MPU | OCP_USER_SDMA, 393 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1130,8 +404,8 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1130}; 404};
1131 405
1132static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 406static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1133 .master = &omap2420_l4_wkup_hwmod, 407 .master = &omap2xxx_l4_wkup_hwmod,
1134 .slave = &omap2420_gpio2_hwmod, 408 .slave = &omap2xxx_gpio2_hwmod,
1135 .clk = "gpios_ick", 409 .clk = "gpios_ick",
1136 .addr = omap2420_gpio2_addr_space, 410 .addr = omap2420_gpio2_addr_space,
1137 .user = OCP_USER_MPU | OCP_USER_SDMA, 411 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1148,8 +422,8 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1148}; 422};
1149 423
1150static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 424static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1151 .master = &omap2420_l4_wkup_hwmod, 425 .master = &omap2xxx_l4_wkup_hwmod,
1152 .slave = &omap2420_gpio3_hwmod, 426 .slave = &omap2xxx_gpio3_hwmod,
1153 .clk = "gpios_ick", 427 .clk = "gpios_ick",
1154 .addr = omap2420_gpio3_addr_space, 428 .addr = omap2420_gpio3_addr_space,
1155 .user = OCP_USER_MPU | OCP_USER_SDMA, 429 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1166,408 +440,150 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1166}; 440};
1167 441
1168static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 442static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1169 .master = &omap2420_l4_wkup_hwmod, 443 .master = &omap2xxx_l4_wkup_hwmod,
1170 .slave = &omap2420_gpio4_hwmod, 444 .slave = &omap2xxx_gpio4_hwmod,
1171 .clk = "gpios_ick", 445 .clk = "gpios_ick",
1172 .addr = omap2420_gpio4_addr_space, 446 .addr = omap2420_gpio4_addr_space,
1173 .user = OCP_USER_MPU | OCP_USER_SDMA, 447 .user = OCP_USER_MPU | OCP_USER_SDMA,
1174}; 448};
1175 449
1176/* gpio dev_attr */
1177static struct omap_gpio_dev_attr gpio_dev_attr = {
1178 .bank_width = 32,
1179 .dbck_flag = false,
1180};
1181
1182/* gpio1 */
1183static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1184 &omap2420_l4_wkup__gpio1,
1185};
1186
1187static struct omap_hwmod omap2420_gpio1_hwmod = {
1188 .name = "gpio1",
1189 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190 .mpu_irqs = omap2_gpio1_irqs,
1191 .main_clk = "gpios_fck",
1192 .prcm = {
1193 .omap2 = {
1194 .prcm_reg_id = 1,
1195 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1196 .module_offs = WKUP_MOD,
1197 .idlest_reg_id = 1,
1198 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1199 },
1200 },
1201 .slaves = omap2420_gpio1_slaves,
1202 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
1203 .class = &omap2xxx_gpio_hwmod_class,
1204 .dev_attr = &gpio_dev_attr,
1205};
1206
1207/* gpio2 */
1208static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1209 &omap2420_l4_wkup__gpio2,
1210};
1211
1212static struct omap_hwmod omap2420_gpio2_hwmod = {
1213 .name = "gpio2",
1214 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1215 .mpu_irqs = omap2_gpio2_irqs,
1216 .main_clk = "gpios_fck",
1217 .prcm = {
1218 .omap2 = {
1219 .prcm_reg_id = 1,
1220 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1221 .module_offs = WKUP_MOD,
1222 .idlest_reg_id = 1,
1223 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1224 },
1225 },
1226 .slaves = omap2420_gpio2_slaves,
1227 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
1228 .class = &omap2xxx_gpio_hwmod_class,
1229 .dev_attr = &gpio_dev_attr,
1230};
1231
1232/* gpio3 */
1233static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1234 &omap2420_l4_wkup__gpio3,
1235};
1236
1237static struct omap_hwmod omap2420_gpio3_hwmod = {
1238 .name = "gpio3",
1239 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1240 .mpu_irqs = omap2_gpio3_irqs,
1241 .main_clk = "gpios_fck",
1242 .prcm = {
1243 .omap2 = {
1244 .prcm_reg_id = 1,
1245 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1246 .module_offs = WKUP_MOD,
1247 .idlest_reg_id = 1,
1248 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1249 },
1250 },
1251 .slaves = omap2420_gpio3_slaves,
1252 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
1253 .class = &omap2xxx_gpio_hwmod_class,
1254 .dev_attr = &gpio_dev_attr,
1255};
1256
1257/* gpio4 */
1258static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1259 &omap2420_l4_wkup__gpio4,
1260};
1261
1262static struct omap_hwmod omap2420_gpio4_hwmod = {
1263 .name = "gpio4",
1264 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1265 .mpu_irqs = omap2_gpio4_irqs,
1266 .main_clk = "gpios_fck",
1267 .prcm = {
1268 .omap2 = {
1269 .prcm_reg_id = 1,
1270 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1271 .module_offs = WKUP_MOD,
1272 .idlest_reg_id = 1,
1273 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1274 },
1275 },
1276 .slaves = omap2420_gpio4_slaves,
1277 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
1278 .class = &omap2xxx_gpio_hwmod_class,
1279 .dev_attr = &gpio_dev_attr,
1280};
1281
1282/* dma attributes */
1283static struct omap_dma_dev_attr dma_dev_attr = {
1284 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1285 IS_CSSA_32 | IS_CDSA_32,
1286 .lch_count = 32,
1287};
1288
1289/* dma_system -> L3 */ 450/* dma_system -> L3 */
1290static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 451static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1291 .master = &omap2420_dma_system_hwmod, 452 .master = &omap2420_dma_system_hwmod,
1292 .slave = &omap2420_l3_main_hwmod, 453 .slave = &omap2xxx_l3_main_hwmod,
1293 .clk = "core_l3_ck", 454 .clk = "core_l3_ck",
1294 .user = OCP_USER_MPU | OCP_USER_SDMA, 455 .user = OCP_USER_MPU | OCP_USER_SDMA,
1295}; 456};
1296 457
1297/* dma_system master ports */
1298static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1299 &omap2420_dma_system__l3,
1300};
1301
1302/* l4_core -> dma_system */ 458/* l4_core -> dma_system */
1303static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { 459static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1304 .master = &omap2420_l4_core_hwmod, 460 .master = &omap2xxx_l4_core_hwmod,
1305 .slave = &omap2420_dma_system_hwmod, 461 .slave = &omap2420_dma_system_hwmod,
1306 .clk = "sdma_ick", 462 .clk = "sdma_ick",
1307 .addr = omap2_dma_system_addrs, 463 .addr = omap2_dma_system_addrs,
1308 .user = OCP_USER_MPU | OCP_USER_SDMA, 464 .user = OCP_USER_MPU | OCP_USER_SDMA,
1309}; 465};
1310 466
1311/* dma_system slave ports */
1312static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1313 &omap2420_l4_core__dma_system,
1314};
1315
1316static struct omap_hwmod omap2420_dma_system_hwmod = {
1317 .name = "dma",
1318 .class = &omap2xxx_dma_hwmod_class,
1319 .mpu_irqs = omap2_dma_system_irqs,
1320 .main_clk = "core_l3_ck",
1321 .slaves = omap2420_dma_system_slaves,
1322 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
1323 .masters = omap2420_dma_system_masters,
1324 .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
1325 .dev_attr = &dma_dev_attr,
1326 .flags = HWMOD_NO_IDLEST,
1327};
1328
1329/* mailbox */
1330static struct omap_hwmod omap2420_mailbox_hwmod;
1331static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1332 { .name = "dsp", .irq = 26 },
1333 { .name = "iva", .irq = 34 },
1334 { .irq = -1 }
1335};
1336
1337/* l4_core -> mailbox */ 467/* l4_core -> mailbox */
1338static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 468static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1339 .master = &omap2420_l4_core_hwmod, 469 .master = &omap2xxx_l4_core_hwmod,
1340 .slave = &omap2420_mailbox_hwmod, 470 .slave = &omap2420_mailbox_hwmod,
1341 .addr = omap2_mailbox_addrs, 471 .addr = omap2_mailbox_addrs,
1342 .user = OCP_USER_MPU | OCP_USER_SDMA, 472 .user = OCP_USER_MPU | OCP_USER_SDMA,
1343}; 473};
1344 474
1345/* mailbox slave ports */
1346static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1347 &omap2420_l4_core__mailbox,
1348};
1349
1350static struct omap_hwmod omap2420_mailbox_hwmod = {
1351 .name = "mailbox",
1352 .class = &omap2xxx_mailbox_hwmod_class,
1353 .mpu_irqs = omap2420_mailbox_irqs,
1354 .main_clk = "mailboxes_ick",
1355 .prcm = {
1356 .omap2 = {
1357 .prcm_reg_id = 1,
1358 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1359 .module_offs = CORE_MOD,
1360 .idlest_reg_id = 1,
1361 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1362 },
1363 },
1364 .slaves = omap2420_mailbox_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
1366};
1367
1368/* mcspi1 */
1369static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1370 &omap2420_l4_core__mcspi1,
1371};
1372
1373static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1374 .num_chipselect = 4,
1375};
1376
1377static struct omap_hwmod omap2420_mcspi1_hwmod = {
1378 .name = "mcspi1_hwmod",
1379 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1380 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1381 .main_clk = "mcspi1_fck",
1382 .prcm = {
1383 .omap2 = {
1384 .module_offs = CORE_MOD,
1385 .prcm_reg_id = 1,
1386 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1387 .idlest_reg_id = 1,
1388 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1389 },
1390 },
1391 .slaves = omap2420_mcspi1_slaves,
1392 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
1393 .class = &omap2xxx_mcspi_class,
1394 .dev_attr = &omap_mcspi1_dev_attr,
1395};
1396
1397/* mcspi2 */
1398static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1399 &omap2420_l4_core__mcspi2,
1400};
1401
1402static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1403 .num_chipselect = 2,
1404};
1405
1406static struct omap_hwmod omap2420_mcspi2_hwmod = {
1407 .name = "mcspi2_hwmod",
1408 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1409 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1410 .main_clk = "mcspi2_fck",
1411 .prcm = {
1412 .omap2 = {
1413 .module_offs = CORE_MOD,
1414 .prcm_reg_id = 1,
1415 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1416 .idlest_reg_id = 1,
1417 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1418 },
1419 },
1420 .slaves = omap2420_mcspi2_slaves,
1421 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
1422 .class = &omap2xxx_mcspi_class,
1423 .dev_attr = &omap_mcspi2_dev_attr,
1424};
1425
1426/*
1427 * 'mcbsp' class
1428 * multi channel buffered serial port controller
1429 */
1430
1431static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1432 .name = "mcbsp",
1433};
1434
1435/* mcbsp1 */
1436static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1437 { .name = "tx", .irq = 59 },
1438 { .name = "rx", .irq = 60 },
1439 { .irq = -1 }
1440};
1441
1442/* l4_core -> mcbsp1 */ 475/* l4_core -> mcbsp1 */
1443static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { 476static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1444 .master = &omap2420_l4_core_hwmod, 477 .master = &omap2xxx_l4_core_hwmod,
1445 .slave = &omap2420_mcbsp1_hwmod, 478 .slave = &omap2420_mcbsp1_hwmod,
1446 .clk = "mcbsp1_ick", 479 .clk = "mcbsp1_ick",
1447 .addr = omap2_mcbsp1_addrs, 480 .addr = omap2_mcbsp1_addrs,
1448 .user = OCP_USER_MPU | OCP_USER_SDMA, 481 .user = OCP_USER_MPU | OCP_USER_SDMA,
1449}; 482};
1450 483
1451/* mcbsp1 slave ports */
1452static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1453 &omap2420_l4_core__mcbsp1,
1454};
1455
1456static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1457 .name = "mcbsp1",
1458 .class = &omap2420_mcbsp_hwmod_class,
1459 .mpu_irqs = omap2420_mcbsp1_irqs,
1460 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1461 .main_clk = "mcbsp1_fck",
1462 .prcm = {
1463 .omap2 = {
1464 .prcm_reg_id = 1,
1465 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1466 .module_offs = CORE_MOD,
1467 .idlest_reg_id = 1,
1468 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1469 },
1470 },
1471 .slaves = omap2420_mcbsp1_slaves,
1472 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1473};
1474
1475/* mcbsp2 */
1476static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1477 { .name = "tx", .irq = 62 },
1478 { .name = "rx", .irq = 63 },
1479 { .irq = -1 }
1480};
1481
1482/* l4_core -> mcbsp2 */ 484/* l4_core -> mcbsp2 */
1483static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { 485static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1484 .master = &omap2420_l4_core_hwmod, 486 .master = &omap2xxx_l4_core_hwmod,
1485 .slave = &omap2420_mcbsp2_hwmod, 487 .slave = &omap2420_mcbsp2_hwmod,
1486 .clk = "mcbsp2_ick", 488 .clk = "mcbsp2_ick",
1487 .addr = omap2xxx_mcbsp2_addrs, 489 .addr = omap2xxx_mcbsp2_addrs,
1488 .user = OCP_USER_MPU | OCP_USER_SDMA, 490 .user = OCP_USER_MPU | OCP_USER_SDMA,
1489}; 491};
1490 492
1491/* mcbsp2 slave ports */ 493static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
1492static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { 494 {
1493 &omap2420_l4_core__mcbsp2, 495 .pa_start = 0x4809c000,
1494}; 496 .pa_end = 0x4809c000 + SZ_128 - 1,
1495 497 .flags = ADDR_TYPE_RT,
1496static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1497 .name = "mcbsp2",
1498 .class = &omap2420_mcbsp_hwmod_class,
1499 .mpu_irqs = omap2420_mcbsp2_irqs,
1500 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1501 .main_clk = "mcbsp2_fck",
1502 .prcm = {
1503 .omap2 = {
1504 .prcm_reg_id = 1,
1505 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1506 .module_offs = CORE_MOD,
1507 .idlest_reg_id = 1,
1508 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1509 },
1510 }, 498 },
1511 .slaves = omap2420_mcbsp2_slaves, 499 { }
1512 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1513}; 500};
1514 501
1515static __initdata struct omap_hwmod *omap2420_hwmods[] = { 502/* l4_core -> msdi1 */
1516 &omap2420_l3_main_hwmod, 503static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
1517 &omap2420_l4_core_hwmod, 504 .master = &omap2xxx_l4_core_hwmod,
1518 &omap2420_l4_wkup_hwmod, 505 .slave = &omap2420_msdi1_hwmod,
1519 &omap2420_mpu_hwmod, 506 .clk = "mmc_ick",
1520 &omap2420_iva_hwmod, 507 .addr = omap2420_msdi1_addrs,
1521 508 .user = OCP_USER_MPU | OCP_USER_SDMA,
1522 &omap2420_timer1_hwmod, 509};
1523 &omap2420_timer2_hwmod,
1524 &omap2420_timer3_hwmod,
1525 &omap2420_timer4_hwmod,
1526 &omap2420_timer5_hwmod,
1527 &omap2420_timer6_hwmod,
1528 &omap2420_timer7_hwmod,
1529 &omap2420_timer8_hwmod,
1530 &omap2420_timer9_hwmod,
1531 &omap2420_timer10_hwmod,
1532 &omap2420_timer11_hwmod,
1533 &omap2420_timer12_hwmod,
1534
1535 &omap2420_wd_timer2_hwmod,
1536 &omap2420_uart1_hwmod,
1537 &omap2420_uart2_hwmod,
1538 &omap2420_uart3_hwmod,
1539 /* dss class */
1540 &omap2420_dss_core_hwmod,
1541 &omap2420_dss_dispc_hwmod,
1542 &omap2420_dss_rfbi_hwmod,
1543 &omap2420_dss_venc_hwmod,
1544 /* i2c class */
1545 &omap2420_i2c1_hwmod,
1546 &omap2420_i2c2_hwmod,
1547 510
1548 /* gpio class */ 511/* l4_core -> hdq1w interface */
1549 &omap2420_gpio1_hwmod, 512static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
1550 &omap2420_gpio2_hwmod, 513 .master = &omap2xxx_l4_core_hwmod,
1551 &omap2420_gpio3_hwmod, 514 .slave = &omap2420_hdq1w_hwmod,
1552 &omap2420_gpio4_hwmod, 515 .clk = "hdq_ick",
516 .addr = omap2_hdq1w_addr_space,
517 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
519};
1553 520
1554 /* dma_system class*/
1555 &omap2420_dma_system_hwmod,
1556 521
1557 /* mailbox class */ 522/* l4_wkup -> 32ksync_counter */
1558 &omap2420_mailbox_hwmod, 523static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
524 {
525 .pa_start = 0x48004000,
526 .pa_end = 0x4800401f,
527 .flags = ADDR_TYPE_RT
528 },
529 { }
530};
1559 531
1560 /* mcbsp class */ 532static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
1561 &omap2420_mcbsp1_hwmod, 533 .master = &omap2xxx_l4_wkup_hwmod,
1562 &omap2420_mcbsp2_hwmod, 534 .slave = &omap2xxx_counter_32k_hwmod,
535 .clk = "sync_32k_ick",
536 .addr = omap2420_counter_32k_addrs,
537 .user = OCP_USER_MPU | OCP_USER_SDMA,
538};
1563 539
1564 /* mcspi class */ 540static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
1565 &omap2420_mcspi1_hwmod, 541 &omap2xxx_l3_main__l4_core,
1566 &omap2420_mcspi2_hwmod, 542 &omap2xxx_mpu__l3_main,
543 &omap2xxx_dss__l3,
544 &omap2xxx_l4_core__mcspi1,
545 &omap2xxx_l4_core__mcspi2,
546 &omap2xxx_l4_core__l4_wkup,
547 &omap2_l4_core__uart1,
548 &omap2_l4_core__uart2,
549 &omap2_l4_core__uart3,
550 &omap2420_l4_core__i2c1,
551 &omap2420_l4_core__i2c2,
552 &omap2420_l3__iva,
553 &omap2420_l3__dsp,
554 &omap2420_l4_wkup__timer1,
555 &omap2xxx_l4_core__timer2,
556 &omap2xxx_l4_core__timer3,
557 &omap2xxx_l4_core__timer4,
558 &omap2xxx_l4_core__timer5,
559 &omap2xxx_l4_core__timer6,
560 &omap2xxx_l4_core__timer7,
561 &omap2xxx_l4_core__timer8,
562 &omap2xxx_l4_core__timer9,
563 &omap2xxx_l4_core__timer10,
564 &omap2xxx_l4_core__timer11,
565 &omap2xxx_l4_core__timer12,
566 &omap2420_l4_wkup__wd_timer2,
567 &omap2xxx_l4_core__dss,
568 &omap2xxx_l4_core__dss_dispc,
569 &omap2xxx_l4_core__dss_rfbi,
570 &omap2xxx_l4_core__dss_venc,
571 &omap2420_l4_wkup__gpio1,
572 &omap2420_l4_wkup__gpio2,
573 &omap2420_l4_wkup__gpio3,
574 &omap2420_l4_wkup__gpio4,
575 &omap2420_dma_system__l3,
576 &omap2420_l4_core__dma_system,
577 &omap2420_l4_core__mailbox,
578 &omap2420_l4_core__mcbsp1,
579 &omap2420_l4_core__mcbsp2,
580 &omap2420_l4_core__msdi1,
581 &omap2420_l4_core__hdq1w,
582 &omap2420_l4_wkup__counter_32k,
1567 NULL, 583 NULL,
1568}; 584};
1569 585
1570int __init omap2420_hwmod_init(void) 586int __init omap2420_hwmod_init(void)
1571{ 587{
1572 return omap_hwmod_register(omap2420_hwmods); 588 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
1573} 589}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 04a3885f4475..4d7264981230 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -33,1044 +34,29 @@
33/* 34/*
34 * OMAP2430 hardware module integration data 35 * OMAP2430 hardware module integration data
35 * 36 *
36 * ALl of the data in this section should be autogeneratable from the 37 * All of the data in this section should be autogeneratable from the
37 * TI hardware database or other technical documentation. Data that 38 * TI hardware database or other technical documentation. Data that
38 * is driver-specific or driver-kernel integration-specific belongs 39 * is driver-specific or driver-kernel integration-specific belongs
39 * elsewhere. 40 * elsewhere.
40 */ 41 */
41 42
42static struct omap_hwmod omap2430_mpu_hwmod;
43static struct omap_hwmod omap2430_iva_hwmod;
44static struct omap_hwmod omap2430_l3_main_hwmod;
45static struct omap_hwmod omap2430_l4_core_hwmod;
46static struct omap_hwmod omap2430_dss_core_hwmod;
47static struct omap_hwmod omap2430_dss_dispc_hwmod;
48static struct omap_hwmod omap2430_dss_rfbi_hwmod;
49static struct omap_hwmod omap2430_dss_venc_hwmod;
50static struct omap_hwmod omap2430_wd_timer2_hwmod;
51static struct omap_hwmod omap2430_gpio1_hwmod;
52static struct omap_hwmod omap2430_gpio2_hwmod;
53static struct omap_hwmod omap2430_gpio3_hwmod;
54static struct omap_hwmod omap2430_gpio4_hwmod;
55static struct omap_hwmod omap2430_gpio5_hwmod;
56static struct omap_hwmod omap2430_dma_system_hwmod;
57static struct omap_hwmod omap2430_mcbsp1_hwmod;
58static struct omap_hwmod omap2430_mcbsp2_hwmod;
59static struct omap_hwmod omap2430_mcbsp3_hwmod;
60static struct omap_hwmod omap2430_mcbsp4_hwmod;
61static struct omap_hwmod omap2430_mcbsp5_hwmod;
62static struct omap_hwmod omap2430_mcspi1_hwmod;
63static struct omap_hwmod omap2430_mcspi2_hwmod;
64static struct omap_hwmod omap2430_mcspi3_hwmod;
65static struct omap_hwmod omap2430_mmc1_hwmod;
66static struct omap_hwmod omap2430_mmc2_hwmod;
67
68/* L3 -> L4_CORE interface */
69static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
70 .master = &omap2430_l3_main_hwmod,
71 .slave = &omap2430_l4_core_hwmod,
72 .user = OCP_USER_MPU | OCP_USER_SDMA,
73};
74
75/* MPU -> L3 interface */
76static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
77 .master = &omap2430_mpu_hwmod,
78 .slave = &omap2430_l3_main_hwmod,
79 .user = OCP_USER_MPU,
80};
81
82/* Slave interfaces on the L3 interconnect */
83static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
84 &omap2430_mpu__l3_main,
85};
86
87/* DSS -> l3 */
88static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
89 .master = &omap2430_dss_core_hwmod,
90 .slave = &omap2430_l3_main_hwmod,
91 .fw = {
92 .omap2 = {
93 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
94 .flags = OMAP_FIREWALL_L3,
95 }
96 },
97 .user = OCP_USER_MPU | OCP_USER_SDMA,
98};
99
100/* Master interfaces on the L3 interconnect */
101static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
102 &omap2430_l3_main__l4_core,
103};
104
105/* L3 */
106static struct omap_hwmod omap2430_l3_main_hwmod = {
107 .name = "l3_main",
108 .class = &l3_hwmod_class,
109 .masters = omap2430_l3_main_masters,
110 .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
111 .slaves = omap2430_l3_main_slaves,
112 .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
113 .flags = HWMOD_NO_IDLEST,
114};
115
116static struct omap_hwmod omap2430_l4_wkup_hwmod;
117static struct omap_hwmod omap2430_uart1_hwmod;
118static struct omap_hwmod omap2430_uart2_hwmod;
119static struct omap_hwmod omap2430_uart3_hwmod;
120static struct omap_hwmod omap2430_i2c1_hwmod;
121static struct omap_hwmod omap2430_i2c2_hwmod;
122
123static struct omap_hwmod omap2430_usbhsotg_hwmod;
124
125/* l3_core -> usbhsotg interface */
126static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
127 .master = &omap2430_usbhsotg_hwmod,
128 .slave = &omap2430_l3_main_hwmod,
129 .clk = "core_l3_ck",
130 .user = OCP_USER_MPU,
131};
132
133/* L4 CORE -> I2C1 interface */
134static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
135 .master = &omap2430_l4_core_hwmod,
136 .slave = &omap2430_i2c1_hwmod,
137 .clk = "i2c1_ick",
138 .addr = omap2_i2c1_addr_space,
139 .user = OCP_USER_MPU | OCP_USER_SDMA,
140};
141
142/* L4 CORE -> I2C2 interface */
143static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
144 .master = &omap2430_l4_core_hwmod,
145 .slave = &omap2430_i2c2_hwmod,
146 .clk = "i2c2_ick",
147 .addr = omap2_i2c2_addr_space,
148 .user = OCP_USER_MPU | OCP_USER_SDMA,
149};
150
151/* L4_CORE -> L4_WKUP interface */
152static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
153 .master = &omap2430_l4_core_hwmod,
154 .slave = &omap2430_l4_wkup_hwmod,
155 .user = OCP_USER_MPU | OCP_USER_SDMA,
156};
157
158/* L4 CORE -> UART1 interface */
159static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
160 .master = &omap2430_l4_core_hwmod,
161 .slave = &omap2430_uart1_hwmod,
162 .clk = "uart1_ick",
163 .addr = omap2xxx_uart1_addr_space,
164 .user = OCP_USER_MPU | OCP_USER_SDMA,
165};
166
167/* L4 CORE -> UART2 interface */
168static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
169 .master = &omap2430_l4_core_hwmod,
170 .slave = &omap2430_uart2_hwmod,
171 .clk = "uart2_ick",
172 .addr = omap2xxx_uart2_addr_space,
173 .user = OCP_USER_MPU | OCP_USER_SDMA,
174};
175
176/* L4 PER -> UART3 interface */
177static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
178 .master = &omap2430_l4_core_hwmod,
179 .slave = &omap2430_uart3_hwmod,
180 .clk = "uart3_ick",
181 .addr = omap2xxx_uart3_addr_space,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
183};
184
185/*
186* usbhsotg interface data
187*/
188static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
189 {
190 .pa_start = OMAP243X_HS_BASE,
191 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
192 .flags = ADDR_TYPE_RT
193 },
194 { }
195};
196
197/* l4_core ->usbhsotg interface */
198static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
199 .master = &omap2430_l4_core_hwmod,
200 .slave = &omap2430_usbhsotg_hwmod,
201 .clk = "usb_l4_ick",
202 .addr = omap2430_usbhsotg_addrs,
203 .user = OCP_USER_MPU,
204};
205
206static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
207 &omap2430_usbhsotg__l3,
208};
209
210static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
211 &omap2430_l4_core__usbhsotg,
212};
213
214/* L4 CORE -> MMC1 interface */
215static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
216 .master = &omap2430_l4_core_hwmod,
217 .slave = &omap2430_mmc1_hwmod,
218 .clk = "mmchs1_ick",
219 .addr = omap2430_mmc1_addr_space,
220 .user = OCP_USER_MPU | OCP_USER_SDMA,
221};
222
223/* L4 CORE -> MMC2 interface */
224static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
225 .master = &omap2430_l4_core_hwmod,
226 .slave = &omap2430_mmc2_hwmod,
227 .clk = "mmchs2_ick",
228 .addr = omap2430_mmc2_addr_space,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
230};
231
232/* Slave interfaces on the L4_CORE interconnect */
233static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
234 &omap2430_l3_main__l4_core,
235};
236
237/* Master interfaces on the L4_CORE interconnect */
238static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
239 &omap2430_l4_core__l4_wkup,
240 &omap2430_l4_core__mmc1,
241 &omap2430_l4_core__mmc2,
242};
243
244/* L4 CORE */
245static struct omap_hwmod omap2430_l4_core_hwmod = {
246 .name = "l4_core",
247 .class = &l4_hwmod_class,
248 .masters = omap2430_l4_core_masters,
249 .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
250 .slaves = omap2430_l4_core_slaves,
251 .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
252 .flags = HWMOD_NO_IDLEST,
253};
254
255/* Slave interfaces on the L4_WKUP interconnect */
256static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
257 &omap2430_l4_core__l4_wkup,
258 &omap2_l4_core__uart1,
259 &omap2_l4_core__uart2,
260 &omap2_l4_core__uart3,
261};
262
263/* Master interfaces on the L4_WKUP interconnect */
264static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
265};
266
267/* l4 core -> mcspi1 interface */
268static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
269 .master = &omap2430_l4_core_hwmod,
270 .slave = &omap2430_mcspi1_hwmod,
271 .clk = "mcspi1_ick",
272 .addr = omap2_mcspi1_addr_space,
273 .user = OCP_USER_MPU | OCP_USER_SDMA,
274};
275
276/* l4 core -> mcspi2 interface */
277static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
278 .master = &omap2430_l4_core_hwmod,
279 .slave = &omap2430_mcspi2_hwmod,
280 .clk = "mcspi2_ick",
281 .addr = omap2_mcspi2_addr_space,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
283};
284
285/* l4 core -> mcspi3 interface */
286static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
287 .master = &omap2430_l4_core_hwmod,
288 .slave = &omap2430_mcspi3_hwmod,
289 .clk = "mcspi3_ick",
290 .addr = omap2430_mcspi3_addr_space,
291 .user = OCP_USER_MPU | OCP_USER_SDMA,
292};
293
294/* L4 WKUP */
295static struct omap_hwmod omap2430_l4_wkup_hwmod = {
296 .name = "l4_wkup",
297 .class = &l4_hwmod_class,
298 .masters = omap2430_l4_wkup_masters,
299 .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
300 .slaves = omap2430_l4_wkup_slaves,
301 .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
302 .flags = HWMOD_NO_IDLEST,
303};
304
305/* Master interfaces on the MPU device */
306static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
307 &omap2430_mpu__l3_main,
308};
309
310/* MPU */
311static struct omap_hwmod omap2430_mpu_hwmod = {
312 .name = "mpu",
313 .class = &mpu_hwmod_class,
314 .main_clk = "mpu_ck",
315 .masters = omap2430_mpu_masters,
316 .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
317};
318
319/* 43/*
320 * IVA2_1 interface data 44 * IP blocks
321 */ 45 */
322 46
323/* IVA2 <- L3 interface */ 47/* IVA2 (IVA2) */
324static struct omap_hwmod_ocp_if omap2430_l3__iva = { 48static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
325 .master = &omap2430_l3_main_hwmod, 49 { .name = "logic", .rst_shift = 0 },
326 .slave = &omap2430_iva_hwmod, 50 { .name = "mmu", .rst_shift = 1 },
327 .clk = "dsp_fck",
328 .user = OCP_USER_MPU | OCP_USER_SDMA,
329};
330
331static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
332 &omap2430_l3__iva,
333}; 51};
334 52
335/*
336 * IVA2 (IVA2)
337 */
338
339static struct omap_hwmod omap2430_iva_hwmod = { 53static struct omap_hwmod omap2430_iva_hwmod = {
340 .name = "iva", 54 .name = "iva",
341 .class = &iva_hwmod_class, 55 .class = &iva_hwmod_class,
342 .masters = omap2430_iva_masters, 56 .clkdm_name = "dsp_clkdm",
343 .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), 57 .rst_lines = omap2430_iva_resets,
344}; 58 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
345 59 .main_clk = "dsp_fck",
346/* always-on timers dev attribute */
347static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
348 .timer_capability = OMAP_TIMER_ALWON,
349};
350
351/* pwm timers dev attribute */
352static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
353 .timer_capability = OMAP_TIMER_HAS_PWM,
354};
355
356/* timer1 */
357static struct omap_hwmod omap2430_timer1_hwmod;
358
359static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
360 {
361 .pa_start = 0x49018000,
362 .pa_end = 0x49018000 + SZ_1K - 1,
363 .flags = ADDR_TYPE_RT
364 },
365 { }
366};
367
368/* l4_wkup -> timer1 */
369static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
370 .master = &omap2430_l4_wkup_hwmod,
371 .slave = &omap2430_timer1_hwmod,
372 .clk = "gpt1_ick",
373 .addr = omap2430_timer1_addrs,
374 .user = OCP_USER_MPU | OCP_USER_SDMA,
375};
376
377/* timer1 slave port */
378static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
379 &omap2430_l4_wkup__timer1,
380};
381
382/* timer1 hwmod */
383static struct omap_hwmod omap2430_timer1_hwmod = {
384 .name = "timer1",
385 .mpu_irqs = omap2_timer1_mpu_irqs,
386 .main_clk = "gpt1_fck",
387 .prcm = {
388 .omap2 = {
389 .prcm_reg_id = 1,
390 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
391 .module_offs = WKUP_MOD,
392 .idlest_reg_id = 1,
393 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
394 },
395 },
396 .dev_attr = &capability_alwon_dev_attr,
397 .slaves = omap2430_timer1_slaves,
398 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
399 .class = &omap2xxx_timer_hwmod_class,
400};
401
402/* timer2 */
403static struct omap_hwmod omap2430_timer2_hwmod;
404
405/* l4_core -> timer2 */
406static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
407 .master = &omap2430_l4_core_hwmod,
408 .slave = &omap2430_timer2_hwmod,
409 .clk = "gpt2_ick",
410 .addr = omap2xxx_timer2_addrs,
411 .user = OCP_USER_MPU | OCP_USER_SDMA,
412};
413
414/* timer2 slave port */
415static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
416 &omap2430_l4_core__timer2,
417};
418
419/* timer2 hwmod */
420static struct omap_hwmod omap2430_timer2_hwmod = {
421 .name = "timer2",
422 .mpu_irqs = omap2_timer2_mpu_irqs,
423 .main_clk = "gpt2_fck",
424 .prcm = {
425 .omap2 = {
426 .prcm_reg_id = 1,
427 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
428 .module_offs = CORE_MOD,
429 .idlest_reg_id = 1,
430 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
431 },
432 },
433 .dev_attr = &capability_alwon_dev_attr,
434 .slaves = omap2430_timer2_slaves,
435 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
436 .class = &omap2xxx_timer_hwmod_class,
437};
438
439/* timer3 */
440static struct omap_hwmod omap2430_timer3_hwmod;
441
442/* l4_core -> timer3 */
443static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
444 .master = &omap2430_l4_core_hwmod,
445 .slave = &omap2430_timer3_hwmod,
446 .clk = "gpt3_ick",
447 .addr = omap2xxx_timer3_addrs,
448 .user = OCP_USER_MPU | OCP_USER_SDMA,
449};
450
451/* timer3 slave port */
452static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
453 &omap2430_l4_core__timer3,
454};
455
456/* timer3 hwmod */
457static struct omap_hwmod omap2430_timer3_hwmod = {
458 .name = "timer3",
459 .mpu_irqs = omap2_timer3_mpu_irqs,
460 .main_clk = "gpt3_fck",
461 .prcm = {
462 .omap2 = {
463 .prcm_reg_id = 1,
464 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
465 .module_offs = CORE_MOD,
466 .idlest_reg_id = 1,
467 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
468 },
469 },
470 .dev_attr = &capability_alwon_dev_attr,
471 .slaves = omap2430_timer3_slaves,
472 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
473 .class = &omap2xxx_timer_hwmod_class,
474};
475
476/* timer4 */
477static struct omap_hwmod omap2430_timer4_hwmod;
478
479/* l4_core -> timer4 */
480static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
481 .master = &omap2430_l4_core_hwmod,
482 .slave = &omap2430_timer4_hwmod,
483 .clk = "gpt4_ick",
484 .addr = omap2xxx_timer4_addrs,
485 .user = OCP_USER_MPU | OCP_USER_SDMA,
486};
487
488/* timer4 slave port */
489static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
490 &omap2430_l4_core__timer4,
491};
492
493/* timer4 hwmod */
494static struct omap_hwmod omap2430_timer4_hwmod = {
495 .name = "timer4",
496 .mpu_irqs = omap2_timer4_mpu_irqs,
497 .main_clk = "gpt4_fck",
498 .prcm = {
499 .omap2 = {
500 .prcm_reg_id = 1,
501 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
502 .module_offs = CORE_MOD,
503 .idlest_reg_id = 1,
504 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
505 },
506 },
507 .dev_attr = &capability_alwon_dev_attr,
508 .slaves = omap2430_timer4_slaves,
509 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
510 .class = &omap2xxx_timer_hwmod_class,
511};
512
513/* timer5 */
514static struct omap_hwmod omap2430_timer5_hwmod;
515
516/* l4_core -> timer5 */
517static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
518 .master = &omap2430_l4_core_hwmod,
519 .slave = &omap2430_timer5_hwmod,
520 .clk = "gpt5_ick",
521 .addr = omap2xxx_timer5_addrs,
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
523};
524
525/* timer5 slave port */
526static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
527 &omap2430_l4_core__timer5,
528};
529
530/* timer5 hwmod */
531static struct omap_hwmod omap2430_timer5_hwmod = {
532 .name = "timer5",
533 .mpu_irqs = omap2_timer5_mpu_irqs,
534 .main_clk = "gpt5_fck",
535 .prcm = {
536 .omap2 = {
537 .prcm_reg_id = 1,
538 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
539 .module_offs = CORE_MOD,
540 .idlest_reg_id = 1,
541 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
542 },
543 },
544 .dev_attr = &capability_alwon_dev_attr,
545 .slaves = omap2430_timer5_slaves,
546 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
547 .class = &omap2xxx_timer_hwmod_class,
548};
549
550/* timer6 */
551static struct omap_hwmod omap2430_timer6_hwmod;
552
553/* l4_core -> timer6 */
554static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
555 .master = &omap2430_l4_core_hwmod,
556 .slave = &omap2430_timer6_hwmod,
557 .clk = "gpt6_ick",
558 .addr = omap2xxx_timer6_addrs,
559 .user = OCP_USER_MPU | OCP_USER_SDMA,
560};
561
562/* timer6 slave port */
563static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
564 &omap2430_l4_core__timer6,
565};
566
567/* timer6 hwmod */
568static struct omap_hwmod omap2430_timer6_hwmod = {
569 .name = "timer6",
570 .mpu_irqs = omap2_timer6_mpu_irqs,
571 .main_clk = "gpt6_fck",
572 .prcm = {
573 .omap2 = {
574 .prcm_reg_id = 1,
575 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
576 .module_offs = CORE_MOD,
577 .idlest_reg_id = 1,
578 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
579 },
580 },
581 .dev_attr = &capability_alwon_dev_attr,
582 .slaves = omap2430_timer6_slaves,
583 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
584 .class = &omap2xxx_timer_hwmod_class,
585};
586
587/* timer7 */
588static struct omap_hwmod omap2430_timer7_hwmod;
589
590/* l4_core -> timer7 */
591static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
592 .master = &omap2430_l4_core_hwmod,
593 .slave = &omap2430_timer7_hwmod,
594 .clk = "gpt7_ick",
595 .addr = omap2xxx_timer7_addrs,
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
597};
598
599/* timer7 slave port */
600static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
601 &omap2430_l4_core__timer7,
602};
603
604/* timer7 hwmod */
605static struct omap_hwmod omap2430_timer7_hwmod = {
606 .name = "timer7",
607 .mpu_irqs = omap2_timer7_mpu_irqs,
608 .main_clk = "gpt7_fck",
609 .prcm = {
610 .omap2 = {
611 .prcm_reg_id = 1,
612 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
613 .module_offs = CORE_MOD,
614 .idlest_reg_id = 1,
615 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
616 },
617 },
618 .dev_attr = &capability_alwon_dev_attr,
619 .slaves = omap2430_timer7_slaves,
620 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
621 .class = &omap2xxx_timer_hwmod_class,
622};
623
624/* timer8 */
625static struct omap_hwmod omap2430_timer8_hwmod;
626
627/* l4_core -> timer8 */
628static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
629 .master = &omap2430_l4_core_hwmod,
630 .slave = &omap2430_timer8_hwmod,
631 .clk = "gpt8_ick",
632 .addr = omap2xxx_timer8_addrs,
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
634};
635
636/* timer8 slave port */
637static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
638 &omap2430_l4_core__timer8,
639};
640
641/* timer8 hwmod */
642static struct omap_hwmod omap2430_timer8_hwmod = {
643 .name = "timer8",
644 .mpu_irqs = omap2_timer8_mpu_irqs,
645 .main_clk = "gpt8_fck",
646 .prcm = {
647 .omap2 = {
648 .prcm_reg_id = 1,
649 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
650 .module_offs = CORE_MOD,
651 .idlest_reg_id = 1,
652 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
653 },
654 },
655 .dev_attr = &capability_alwon_dev_attr,
656 .slaves = omap2430_timer8_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
658 .class = &omap2xxx_timer_hwmod_class,
659};
660
661/* timer9 */
662static struct omap_hwmod omap2430_timer9_hwmod;
663
664/* l4_core -> timer9 */
665static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
666 .master = &omap2430_l4_core_hwmod,
667 .slave = &omap2430_timer9_hwmod,
668 .clk = "gpt9_ick",
669 .addr = omap2xxx_timer9_addrs,
670 .user = OCP_USER_MPU | OCP_USER_SDMA,
671};
672
673/* timer9 slave port */
674static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
675 &omap2430_l4_core__timer9,
676};
677
678/* timer9 hwmod */
679static struct omap_hwmod omap2430_timer9_hwmod = {
680 .name = "timer9",
681 .mpu_irqs = omap2_timer9_mpu_irqs,
682 .main_clk = "gpt9_fck",
683 .prcm = {
684 .omap2 = {
685 .prcm_reg_id = 1,
686 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
687 .module_offs = CORE_MOD,
688 .idlest_reg_id = 1,
689 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
690 },
691 },
692 .dev_attr = &capability_pwm_dev_attr,
693 .slaves = omap2430_timer9_slaves,
694 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
695 .class = &omap2xxx_timer_hwmod_class,
696};
697
698/* timer10 */
699static struct omap_hwmod omap2430_timer10_hwmod;
700
701/* l4_core -> timer10 */
702static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
703 .master = &omap2430_l4_core_hwmod,
704 .slave = &omap2430_timer10_hwmod,
705 .clk = "gpt10_ick",
706 .addr = omap2_timer10_addrs,
707 .user = OCP_USER_MPU | OCP_USER_SDMA,
708};
709
710/* timer10 slave port */
711static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
712 &omap2430_l4_core__timer10,
713};
714
715/* timer10 hwmod */
716static struct omap_hwmod omap2430_timer10_hwmod = {
717 .name = "timer10",
718 .mpu_irqs = omap2_timer10_mpu_irqs,
719 .main_clk = "gpt10_fck",
720 .prcm = {
721 .omap2 = {
722 .prcm_reg_id = 1,
723 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
724 .module_offs = CORE_MOD,
725 .idlest_reg_id = 1,
726 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
727 },
728 },
729 .dev_attr = &capability_pwm_dev_attr,
730 .slaves = omap2430_timer10_slaves,
731 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
732 .class = &omap2xxx_timer_hwmod_class,
733};
734
735/* timer11 */
736static struct omap_hwmod omap2430_timer11_hwmod;
737
738/* l4_core -> timer11 */
739static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
740 .master = &omap2430_l4_core_hwmod,
741 .slave = &omap2430_timer11_hwmod,
742 .clk = "gpt11_ick",
743 .addr = omap2_timer11_addrs,
744 .user = OCP_USER_MPU | OCP_USER_SDMA,
745};
746
747/* timer11 slave port */
748static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
749 &omap2430_l4_core__timer11,
750};
751
752/* timer11 hwmod */
753static struct omap_hwmod omap2430_timer11_hwmod = {
754 .name = "timer11",
755 .mpu_irqs = omap2_timer11_mpu_irqs,
756 .main_clk = "gpt11_fck",
757 .prcm = {
758 .omap2 = {
759 .prcm_reg_id = 1,
760 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
761 .module_offs = CORE_MOD,
762 .idlest_reg_id = 1,
763 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
764 },
765 },
766 .dev_attr = &capability_pwm_dev_attr,
767 .slaves = omap2430_timer11_slaves,
768 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
769 .class = &omap2xxx_timer_hwmod_class,
770};
771
772/* timer12 */
773static struct omap_hwmod omap2430_timer12_hwmod;
774
775/* l4_core -> timer12 */
776static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
777 .master = &omap2430_l4_core_hwmod,
778 .slave = &omap2430_timer12_hwmod,
779 .clk = "gpt12_ick",
780 .addr = omap2xxx_timer12_addrs,
781 .user = OCP_USER_MPU | OCP_USER_SDMA,
782};
783
784/* timer12 slave port */
785static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
786 &omap2430_l4_core__timer12,
787};
788
789/* timer12 hwmod */
790static struct omap_hwmod omap2430_timer12_hwmod = {
791 .name = "timer12",
792 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
793 .main_clk = "gpt12_fck",
794 .prcm = {
795 .omap2 = {
796 .prcm_reg_id = 1,
797 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
798 .module_offs = CORE_MOD,
799 .idlest_reg_id = 1,
800 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
801 },
802 },
803 .dev_attr = &capability_pwm_dev_attr,
804 .slaves = omap2430_timer12_slaves,
805 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
806 .class = &omap2xxx_timer_hwmod_class,
807};
808
809/* l4_wkup -> wd_timer2 */
810static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
811 {
812 .pa_start = 0x49016000,
813 .pa_end = 0x4901607f,
814 .flags = ADDR_TYPE_RT
815 },
816 { }
817};
818
819static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
820 .master = &omap2430_l4_wkup_hwmod,
821 .slave = &omap2430_wd_timer2_hwmod,
822 .clk = "mpu_wdt_ick",
823 .addr = omap2430_wd_timer2_addrs,
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
825};
826
827/* wd_timer2 */
828static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
829 &omap2430_l4_wkup__wd_timer2,
830};
831
832static struct omap_hwmod omap2430_wd_timer2_hwmod = {
833 .name = "wd_timer2",
834 .class = &omap2xxx_wd_timer_hwmod_class,
835 .main_clk = "mpu_wdt_fck",
836 .prcm = {
837 .omap2 = {
838 .prcm_reg_id = 1,
839 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
840 .module_offs = WKUP_MOD,
841 .idlest_reg_id = 1,
842 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
843 },
844 },
845 .slaves = omap2430_wd_timer2_slaves,
846 .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
847};
848
849/* UART1 */
850
851static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
852 &omap2_l4_core__uart1,
853};
854
855static struct omap_hwmod omap2430_uart1_hwmod = {
856 .name = "uart1",
857 .mpu_irqs = omap2_uart1_mpu_irqs,
858 .sdma_reqs = omap2_uart1_sdma_reqs,
859 .main_clk = "uart1_fck",
860 .prcm = {
861 .omap2 = {
862 .module_offs = CORE_MOD,
863 .prcm_reg_id = 1,
864 .module_bit = OMAP24XX_EN_UART1_SHIFT,
865 .idlest_reg_id = 1,
866 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
867 },
868 },
869 .slaves = omap2430_uart1_slaves,
870 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
871 .class = &omap2_uart_class,
872};
873
874/* UART2 */
875
876static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
877 &omap2_l4_core__uart2,
878};
879
880static struct omap_hwmod omap2430_uart2_hwmod = {
881 .name = "uart2",
882 .mpu_irqs = omap2_uart2_mpu_irqs,
883 .sdma_reqs = omap2_uart2_sdma_reqs,
884 .main_clk = "uart2_fck",
885 .prcm = {
886 .omap2 = {
887 .module_offs = CORE_MOD,
888 .prcm_reg_id = 1,
889 .module_bit = OMAP24XX_EN_UART2_SHIFT,
890 .idlest_reg_id = 1,
891 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
892 },
893 },
894 .slaves = omap2430_uart2_slaves,
895 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
896 .class = &omap2_uart_class,
897};
898
899/* UART3 */
900
901static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
902 &omap2_l4_core__uart3,
903};
904
905static struct omap_hwmod omap2430_uart3_hwmod = {
906 .name = "uart3",
907 .mpu_irqs = omap2_uart3_mpu_irqs,
908 .sdma_reqs = omap2_uart3_sdma_reqs,
909 .main_clk = "uart3_fck",
910 .prcm = {
911 .omap2 = {
912 .module_offs = CORE_MOD,
913 .prcm_reg_id = 2,
914 .module_bit = OMAP24XX_EN_UART3_SHIFT,
915 .idlest_reg_id = 2,
916 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
917 },
918 },
919 .slaves = omap2430_uart3_slaves,
920 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
921 .class = &omap2_uart_class,
922};
923
924/* dss */
925/* dss master ports */
926static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
927 &omap2430_dss__l3,
928};
929
930/* l4_core -> dss */
931static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
932 .master = &omap2430_l4_core_hwmod,
933 .slave = &omap2430_dss_core_hwmod,
934 .clk = "dss_ick",
935 .addr = omap2_dss_addrs,
936 .user = OCP_USER_MPU | OCP_USER_SDMA,
937};
938
939/* dss slave ports */
940static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
941 &omap2430_l4_core__dss,
942};
943
944static struct omap_hwmod_opt_clk dss_opt_clks[] = {
945 /*
946 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
947 * driver does not use these clocks.
948 */
949 { .role = "tv_clk", .clk = "dss_54m_fck" },
950 { .role = "sys_clk", .clk = "dss2_fck" },
951};
952
953static struct omap_hwmod omap2430_dss_core_hwmod = {
954 .name = "dss_core",
955 .class = &omap2_dss_hwmod_class,
956 .main_clk = "dss1_fck", /* instead of dss_fck */
957 .sdma_reqs = omap2xxx_dss_sdma_chs,
958 .prcm = {
959 .omap2 = {
960 .prcm_reg_id = 1,
961 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
962 .module_offs = CORE_MOD,
963 .idlest_reg_id = 1,
964 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
965 },
966 },
967 .opt_clks = dss_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
969 .slaves = omap2430_dss_slaves,
970 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
971 .masters = omap2430_dss_masters,
972 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
973 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
974};
975
976/* l4_core -> dss_dispc */
977static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
978 .master = &omap2430_l4_core_hwmod,
979 .slave = &omap2430_dss_dispc_hwmod,
980 .clk = "dss_ick",
981 .addr = omap2_dss_dispc_addrs,
982 .user = OCP_USER_MPU | OCP_USER_SDMA,
983};
984
985/* dss_dispc slave ports */
986static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
987 &omap2430_l4_core__dss_dispc,
988};
989
990static struct omap_hwmod omap2430_dss_dispc_hwmod = {
991 .name = "dss_dispc",
992 .class = &omap2_dispc_hwmod_class,
993 .mpu_irqs = omap2_dispc_irqs,
994 .main_clk = "dss1_fck",
995 .prcm = {
996 .omap2 = {
997 .prcm_reg_id = 1,
998 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
999 .module_offs = CORE_MOD,
1000 .idlest_reg_id = 1,
1001 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1002 },
1003 },
1004 .slaves = omap2430_dss_dispc_slaves,
1005 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1006 .flags = HWMOD_NO_IDLEST,
1007 .dev_attr = &omap2_3_dss_dispc_dev_attr
1008};
1009
1010/* l4_core -> dss_rfbi */
1011static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1012 .master = &omap2430_l4_core_hwmod,
1013 .slave = &omap2430_dss_rfbi_hwmod,
1014 .clk = "dss_ick",
1015 .addr = omap2_dss_rfbi_addrs,
1016 .user = OCP_USER_MPU | OCP_USER_SDMA,
1017};
1018
1019/* dss_rfbi slave ports */
1020static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1021 &omap2430_l4_core__dss_rfbi,
1022};
1023
1024static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1025 { .role = "ick", .clk = "dss_ick" },
1026};
1027
1028static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1029 .name = "dss_rfbi",
1030 .class = &omap2_rfbi_hwmod_class,
1031 .main_clk = "dss1_fck",
1032 .prcm = {
1033 .omap2 = {
1034 .prcm_reg_id = 1,
1035 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1036 .module_offs = CORE_MOD,
1037 },
1038 },
1039 .opt_clks = dss_rfbi_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1041 .slaves = omap2430_dss_rfbi_slaves,
1042 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1043 .flags = HWMOD_NO_IDLEST,
1044};
1045
1046/* l4_core -> dss_venc */
1047static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1048 .master = &omap2430_l4_core_hwmod,
1049 .slave = &omap2430_dss_venc_hwmod,
1050 .clk = "dss_ick",
1051 .addr = omap2_dss_venc_addrs,
1052 .user = OCP_USER_MPU | OCP_USER_SDMA,
1053};
1054
1055/* dss_venc slave ports */
1056static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1057 &omap2430_l4_core__dss_venc,
1058};
1059
1060static struct omap_hwmod omap2430_dss_venc_hwmod = {
1061 .name = "dss_venc",
1062 .class = &omap2_venc_hwmod_class,
1063 .main_clk = "dss_54m_fck",
1064 .prcm = {
1065 .omap2 = {
1066 .prcm_reg_id = 1,
1067 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1068 .module_offs = CORE_MOD,
1069 },
1070 },
1071 .slaves = omap2430_dss_venc_slaves,
1072 .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
1073 .flags = HWMOD_NO_IDLEST,
1074}; 60};
1075 61
1076/* I2C common */ 62/* I2C common */
@@ -1098,11 +84,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
1098}; 84};
1099 85
1100/* I2C1 */ 86/* I2C1 */
1101
1102static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1103 &omap2430_l4_core__i2c1,
1104};
1105
1106static struct omap_hwmod omap2430_i2c1_hwmod = { 87static struct omap_hwmod omap2430_i2c1_hwmod = {
1107 .name = "i2c1", 88 .name = "i2c1",
1108 .flags = HWMOD_16BIT_REG, 89 .flags = HWMOD_16BIT_REG,
@@ -1126,18 +107,11 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
1126 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, 107 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
1127 }, 108 },
1128 }, 109 },
1129 .slaves = omap2430_i2c1_slaves,
1130 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
1131 .class = &i2c_class, 110 .class = &i2c_class,
1132 .dev_attr = &i2c_dev_attr, 111 .dev_attr = &i2c_dev_attr,
1133}; 112};
1134 113
1135/* I2C2 */ 114/* I2C2 */
1136
1137static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1138 &omap2430_l4_core__i2c2,
1139};
1140
1141static struct omap_hwmod omap2430_i2c2_hwmod = { 115static struct omap_hwmod omap2430_i2c2_hwmod = {
1142 .name = "i2c2", 116 .name = "i2c2",
1143 .flags = HWMOD_16BIT_REG, 117 .flags = HWMOD_16BIT_REG,
@@ -1153,218 +127,16 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
1153 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, 127 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
1154 }, 128 },
1155 }, 129 },
1156 .slaves = omap2430_i2c2_slaves,
1157 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
1158 .class = &i2c_class, 130 .class = &i2c_class,
1159 .dev_attr = &i2c_dev_attr, 131 .dev_attr = &i2c_dev_attr,
1160}; 132};
1161 133
1162/* l4_wkup -> gpio1 */
1163static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1164 {
1165 .pa_start = 0x4900C000,
1166 .pa_end = 0x4900C1ff,
1167 .flags = ADDR_TYPE_RT
1168 },
1169 { }
1170};
1171
1172static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1173 .master = &omap2430_l4_wkup_hwmod,
1174 .slave = &omap2430_gpio1_hwmod,
1175 .clk = "gpios_ick",
1176 .addr = omap2430_gpio1_addr_space,
1177 .user = OCP_USER_MPU | OCP_USER_SDMA,
1178};
1179
1180/* l4_wkup -> gpio2 */
1181static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1182 {
1183 .pa_start = 0x4900E000,
1184 .pa_end = 0x4900E1ff,
1185 .flags = ADDR_TYPE_RT
1186 },
1187 { }
1188};
1189
1190static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1191 .master = &omap2430_l4_wkup_hwmod,
1192 .slave = &omap2430_gpio2_hwmod,
1193 .clk = "gpios_ick",
1194 .addr = omap2430_gpio2_addr_space,
1195 .user = OCP_USER_MPU | OCP_USER_SDMA,
1196};
1197
1198/* l4_wkup -> gpio3 */
1199static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1200 {
1201 .pa_start = 0x49010000,
1202 .pa_end = 0x490101ff,
1203 .flags = ADDR_TYPE_RT
1204 },
1205 { }
1206};
1207
1208static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1209 .master = &omap2430_l4_wkup_hwmod,
1210 .slave = &omap2430_gpio3_hwmod,
1211 .clk = "gpios_ick",
1212 .addr = omap2430_gpio3_addr_space,
1213 .user = OCP_USER_MPU | OCP_USER_SDMA,
1214};
1215
1216/* l4_wkup -> gpio4 */
1217static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1218 {
1219 .pa_start = 0x49012000,
1220 .pa_end = 0x490121ff,
1221 .flags = ADDR_TYPE_RT
1222 },
1223 { }
1224};
1225
1226static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1227 .master = &omap2430_l4_wkup_hwmod,
1228 .slave = &omap2430_gpio4_hwmod,
1229 .clk = "gpios_ick",
1230 .addr = omap2430_gpio4_addr_space,
1231 .user = OCP_USER_MPU | OCP_USER_SDMA,
1232};
1233
1234/* l4_core -> gpio5 */
1235static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1236 {
1237 .pa_start = 0x480B6000,
1238 .pa_end = 0x480B61ff,
1239 .flags = ADDR_TYPE_RT
1240 },
1241 { }
1242};
1243
1244static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1245 .master = &omap2430_l4_core_hwmod,
1246 .slave = &omap2430_gpio5_hwmod,
1247 .clk = "gpio5_ick",
1248 .addr = omap2430_gpio5_addr_space,
1249 .user = OCP_USER_MPU | OCP_USER_SDMA,
1250};
1251
1252/* gpio dev_attr */
1253static struct omap_gpio_dev_attr gpio_dev_attr = {
1254 .bank_width = 32,
1255 .dbck_flag = false,
1256};
1257
1258/* gpio1 */
1259static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1260 &omap2430_l4_wkup__gpio1,
1261};
1262
1263static struct omap_hwmod omap2430_gpio1_hwmod = {
1264 .name = "gpio1",
1265 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1266 .mpu_irqs = omap2_gpio1_irqs,
1267 .main_clk = "gpios_fck",
1268 .prcm = {
1269 .omap2 = {
1270 .prcm_reg_id = 1,
1271 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1272 .module_offs = WKUP_MOD,
1273 .idlest_reg_id = 1,
1274 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
1275 },
1276 },
1277 .slaves = omap2430_gpio1_slaves,
1278 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
1279 .class = &omap2xxx_gpio_hwmod_class,
1280 .dev_attr = &gpio_dev_attr,
1281};
1282
1283/* gpio2 */
1284static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1285 &omap2430_l4_wkup__gpio2,
1286};
1287
1288static struct omap_hwmod omap2430_gpio2_hwmod = {
1289 .name = "gpio2",
1290 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1291 .mpu_irqs = omap2_gpio2_irqs,
1292 .main_clk = "gpios_fck",
1293 .prcm = {
1294 .omap2 = {
1295 .prcm_reg_id = 1,
1296 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1297 .module_offs = WKUP_MOD,
1298 .idlest_reg_id = 1,
1299 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1300 },
1301 },
1302 .slaves = omap2430_gpio2_slaves,
1303 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
1304 .class = &omap2xxx_gpio_hwmod_class,
1305 .dev_attr = &gpio_dev_attr,
1306};
1307
1308/* gpio3 */
1309static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1310 &omap2430_l4_wkup__gpio3,
1311};
1312
1313static struct omap_hwmod omap2430_gpio3_hwmod = {
1314 .name = "gpio3",
1315 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1316 .mpu_irqs = omap2_gpio3_irqs,
1317 .main_clk = "gpios_fck",
1318 .prcm = {
1319 .omap2 = {
1320 .prcm_reg_id = 1,
1321 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1322 .module_offs = WKUP_MOD,
1323 .idlest_reg_id = 1,
1324 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1325 },
1326 },
1327 .slaves = omap2430_gpio3_slaves,
1328 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
1329 .class = &omap2xxx_gpio_hwmod_class,
1330 .dev_attr = &gpio_dev_attr,
1331};
1332
1333/* gpio4 */
1334static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1335 &omap2430_l4_wkup__gpio4,
1336};
1337
1338static struct omap_hwmod omap2430_gpio4_hwmod = {
1339 .name = "gpio4",
1340 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1341 .mpu_irqs = omap2_gpio4_irqs,
1342 .main_clk = "gpios_fck",
1343 .prcm = {
1344 .omap2 = {
1345 .prcm_reg_id = 1,
1346 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1347 .module_offs = WKUP_MOD,
1348 .idlest_reg_id = 1,
1349 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1350 },
1351 },
1352 .slaves = omap2430_gpio4_slaves,
1353 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
1354 .class = &omap2xxx_gpio_hwmod_class,
1355 .dev_attr = &gpio_dev_attr,
1356};
1357
1358/* gpio5 */ 134/* gpio5 */
1359static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { 135static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1360 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ 136 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1361 { .irq = -1 } 137 { .irq = -1 }
1362}; 138};
1363 139
1364static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
1365 &omap2430_l4_core__gpio5,
1366};
1367
1368static struct omap_hwmod omap2430_gpio5_hwmod = { 140static struct omap_hwmod omap2430_gpio5_hwmod = {
1369 .name = "gpio5", 141 .name = "gpio5",
1370 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 142 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1379,10 +151,8 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
1379 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, 151 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
1380 }, 152 },
1381 }, 153 },
1382 .slaves = omap2430_gpio5_slaves,
1383 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
1384 .class = &omap2xxx_gpio_hwmod_class, 154 .class = &omap2xxx_gpio_hwmod_class,
1385 .dev_attr = &gpio_dev_attr, 155 .dev_attr = &omap2xxx_gpio_dev_attr,
1386}; 156};
1387 157
1388/* dma attributes */ 158/* dma attributes */
@@ -1392,66 +162,21 @@ static struct omap_dma_dev_attr dma_dev_attr = {
1392 .lch_count = 32, 162 .lch_count = 32,
1393}; 163};
1394 164
1395/* dma_system -> L3 */
1396static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1397 .master = &omap2430_dma_system_hwmod,
1398 .slave = &omap2430_l3_main_hwmod,
1399 .clk = "core_l3_ck",
1400 .user = OCP_USER_MPU | OCP_USER_SDMA,
1401};
1402
1403/* dma_system master ports */
1404static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
1405 &omap2430_dma_system__l3,
1406};
1407
1408/* l4_core -> dma_system */
1409static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1410 .master = &omap2430_l4_core_hwmod,
1411 .slave = &omap2430_dma_system_hwmod,
1412 .clk = "sdma_ick",
1413 .addr = omap2_dma_system_addrs,
1414 .user = OCP_USER_MPU | OCP_USER_SDMA,
1415};
1416
1417/* dma_system slave ports */
1418static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1419 &omap2430_l4_core__dma_system,
1420};
1421
1422static struct omap_hwmod omap2430_dma_system_hwmod = { 165static struct omap_hwmod omap2430_dma_system_hwmod = {
1423 .name = "dma", 166 .name = "dma",
1424 .class = &omap2xxx_dma_hwmod_class, 167 .class = &omap2xxx_dma_hwmod_class,
1425 .mpu_irqs = omap2_dma_system_irqs, 168 .mpu_irqs = omap2_dma_system_irqs,
1426 .main_clk = "core_l3_ck", 169 .main_clk = "core_l3_ck",
1427 .slaves = omap2430_dma_system_slaves,
1428 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
1429 .masters = omap2430_dma_system_masters,
1430 .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
1431 .dev_attr = &dma_dev_attr, 170 .dev_attr = &dma_dev_attr,
1432 .flags = HWMOD_NO_IDLEST, 171 .flags = HWMOD_NO_IDLEST,
1433}; 172};
1434 173
1435/* mailbox */ 174/* mailbox */
1436static struct omap_hwmod omap2430_mailbox_hwmod;
1437static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 175static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1438 { .irq = 26 }, 176 { .irq = 26 },
1439 { .irq = -1 } 177 { .irq = -1 }
1440}; 178};
1441 179
1442/* l4_core -> mailbox */
1443static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
1444 .master = &omap2430_l4_core_hwmod,
1445 .slave = &omap2430_mailbox_hwmod,
1446 .addr = omap2_mailbox_addrs,
1447 .user = OCP_USER_MPU | OCP_USER_SDMA,
1448};
1449
1450/* mailbox slave ports */
1451static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
1452 &omap2430_l4_core__mailbox,
1453};
1454
1455static struct omap_hwmod omap2430_mailbox_hwmod = { 180static struct omap_hwmod omap2430_mailbox_hwmod = {
1456 .name = "mailbox", 181 .name = "mailbox",
1457 .class = &omap2xxx_mailbox_hwmod_class, 182 .class = &omap2xxx_mailbox_hwmod_class,
@@ -1466,66 +191,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
1466 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 191 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1467 }, 192 },
1468 }, 193 },
1469 .slaves = omap2430_mailbox_slaves,
1470 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
1471};
1472
1473/* mcspi1 */
1474static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
1475 &omap2430_l4_core__mcspi1,
1476};
1477
1478static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1479 .num_chipselect = 4,
1480};
1481
1482static struct omap_hwmod omap2430_mcspi1_hwmod = {
1483 .name = "mcspi1_hwmod",
1484 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1485 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1486 .main_clk = "mcspi1_fck",
1487 .prcm = {
1488 .omap2 = {
1489 .module_offs = CORE_MOD,
1490 .prcm_reg_id = 1,
1491 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1492 .idlest_reg_id = 1,
1493 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1494 },
1495 },
1496 .slaves = omap2430_mcspi1_slaves,
1497 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
1498 .class = &omap2xxx_mcspi_class,
1499 .dev_attr = &omap_mcspi1_dev_attr,
1500};
1501
1502/* mcspi2 */
1503static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
1504 &omap2430_l4_core__mcspi2,
1505};
1506
1507static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1508 .num_chipselect = 2,
1509};
1510
1511static struct omap_hwmod omap2430_mcspi2_hwmod = {
1512 .name = "mcspi2_hwmod",
1513 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1514 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1515 .main_clk = "mcspi2_fck",
1516 .prcm = {
1517 .omap2 = {
1518 .module_offs = CORE_MOD,
1519 .prcm_reg_id = 1,
1520 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1521 .idlest_reg_id = 1,
1522 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1523 },
1524 },
1525 .slaves = omap2430_mcspi2_slaves,
1526 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
1527 .class = &omap2xxx_mcspi_class,
1528 .dev_attr = &omap_mcspi2_dev_attr,
1529}; 194};
1530 195
1531/* mcspi3 */ 196/* mcspi3 */
@@ -1542,16 +207,12 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
1542 { .dma_req = -1 } 207 { .dma_req = -1 }
1543}; 208};
1544 209
1545static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
1546 &omap2430_l4_core__mcspi3,
1547};
1548
1549static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 210static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1550 .num_chipselect = 2, 211 .num_chipselect = 2,
1551}; 212};
1552 213
1553static struct omap_hwmod omap2430_mcspi3_hwmod = { 214static struct omap_hwmod omap2430_mcspi3_hwmod = {
1554 .name = "mcspi3_hwmod", 215 .name = "mcspi3",
1555 .mpu_irqs = omap2430_mcspi3_mpu_irqs, 216 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
1556 .sdma_reqs = omap2430_mcspi3_sdma_reqs, 217 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
1557 .main_clk = "mcspi3_fck", 218 .main_clk = "mcspi3_fck",
@@ -1564,15 +225,11 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
1564 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, 225 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
1565 }, 226 },
1566 }, 227 },
1567 .slaves = omap2430_mcspi3_slaves,
1568 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
1569 .class = &omap2xxx_mcspi_class, 228 .class = &omap2xxx_mcspi_class,
1570 .dev_attr = &omap_mcspi3_dev_attr, 229 .dev_attr = &omap_mcspi3_dev_attr,
1571}; 230};
1572 231
1573/* 232/* usbhsotg */
1574 * usbhsotg
1575 */
1576static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { 233static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
1577 .rev_offs = 0x0400, 234 .rev_offs = 0x0400,
1578 .sysc_offs = 0x0404, 235 .sysc_offs = 0x0404,
@@ -1611,10 +268,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1611 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, 268 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
1612 }, 269 },
1613 }, 270 },
1614 .masters = omap2430_usbhsotg_masters,
1615 .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters),
1616 .slaves = omap2430_usbhsotg_slaves,
1617 .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves),
1618 .class = &usbotg_class, 271 .class = &usbotg_class,
1619 /* 272 /*
1620 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 273 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
@@ -1652,20 +305,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
1652 { .irq = -1 } 305 { .irq = -1 }
1653}; 306};
1654 307
1655/* l4_core -> mcbsp1 */
1656static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
1657 .master = &omap2430_l4_core_hwmod,
1658 .slave = &omap2430_mcbsp1_hwmod,
1659 .clk = "mcbsp1_ick",
1660 .addr = omap2_mcbsp1_addrs,
1661 .user = OCP_USER_MPU | OCP_USER_SDMA,
1662};
1663
1664/* mcbsp1 slave ports */
1665static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
1666 &omap2430_l4_core__mcbsp1,
1667};
1668
1669static struct omap_hwmod omap2430_mcbsp1_hwmod = { 308static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1670 .name = "mcbsp1", 309 .name = "mcbsp1",
1671 .class = &omap2430_mcbsp_hwmod_class, 310 .class = &omap2430_mcbsp_hwmod_class,
@@ -1681,8 +320,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
1681 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 320 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1682 }, 321 },
1683 }, 322 },
1684 .slaves = omap2430_mcbsp1_slaves,
1685 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
1686}; 323};
1687 324
1688/* mcbsp2 */ 325/* mcbsp2 */
@@ -1693,20 +330,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
1693 { .irq = -1 } 330 { .irq = -1 }
1694}; 331};
1695 332
1696/* l4_core -> mcbsp2 */
1697static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
1698 .master = &omap2430_l4_core_hwmod,
1699 .slave = &omap2430_mcbsp2_hwmod,
1700 .clk = "mcbsp2_ick",
1701 .addr = omap2xxx_mcbsp2_addrs,
1702 .user = OCP_USER_MPU | OCP_USER_SDMA,
1703};
1704
1705/* mcbsp2 slave ports */
1706static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
1707 &omap2430_l4_core__mcbsp2,
1708};
1709
1710static struct omap_hwmod omap2430_mcbsp2_hwmod = { 333static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1711 .name = "mcbsp2", 334 .name = "mcbsp2",
1712 .class = &omap2430_mcbsp_hwmod_class, 335 .class = &omap2430_mcbsp_hwmod_class,
@@ -1722,8 +345,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
1722 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 345 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1723 }, 346 },
1724 }, 347 },
1725 .slaves = omap2430_mcbsp2_slaves,
1726 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
1727}; 348};
1728 349
1729/* mcbsp3 */ 350/* mcbsp3 */
@@ -1734,30 +355,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
1734 { .irq = -1 } 355 { .irq = -1 }
1735}; 356};
1736 357
1737static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
1738 {
1739 .name = "mpu",
1740 .pa_start = 0x4808C000,
1741 .pa_end = 0x4808C0ff,
1742 .flags = ADDR_TYPE_RT
1743 },
1744 { }
1745};
1746
1747/* l4_core -> mcbsp3 */
1748static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
1749 .master = &omap2430_l4_core_hwmod,
1750 .slave = &omap2430_mcbsp3_hwmod,
1751 .clk = "mcbsp3_ick",
1752 .addr = omap2430_mcbsp3_addrs,
1753 .user = OCP_USER_MPU | OCP_USER_SDMA,
1754};
1755
1756/* mcbsp3 slave ports */
1757static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
1758 &omap2430_l4_core__mcbsp3,
1759};
1760
1761static struct omap_hwmod omap2430_mcbsp3_hwmod = { 358static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1762 .name = "mcbsp3", 359 .name = "mcbsp3",
1763 .class = &omap2430_mcbsp_hwmod_class, 360 .class = &omap2430_mcbsp_hwmod_class,
@@ -1773,8 +370,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
1773 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 370 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
1774 }, 371 },
1775 }, 372 },
1776 .slaves = omap2430_mcbsp3_slaves,
1777 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
1778}; 373};
1779 374
1780/* mcbsp4 */ 375/* mcbsp4 */
@@ -1791,30 +386,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
1791 { .dma_req = -1 } 386 { .dma_req = -1 }
1792}; 387};
1793 388
1794static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
1795 {
1796 .name = "mpu",
1797 .pa_start = 0x4808E000,
1798 .pa_end = 0x4808E0ff,
1799 .flags = ADDR_TYPE_RT
1800 },
1801 { }
1802};
1803
1804/* l4_core -> mcbsp4 */
1805static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
1806 .master = &omap2430_l4_core_hwmod,
1807 .slave = &omap2430_mcbsp4_hwmod,
1808 .clk = "mcbsp4_ick",
1809 .addr = omap2430_mcbsp4_addrs,
1810 .user = OCP_USER_MPU | OCP_USER_SDMA,
1811};
1812
1813/* mcbsp4 slave ports */
1814static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
1815 &omap2430_l4_core__mcbsp4,
1816};
1817
1818static struct omap_hwmod omap2430_mcbsp4_hwmod = { 389static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1819 .name = "mcbsp4", 390 .name = "mcbsp4",
1820 .class = &omap2430_mcbsp_hwmod_class, 391 .class = &omap2430_mcbsp_hwmod_class,
@@ -1830,8 +401,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
1830 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 401 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
1831 }, 402 },
1832 }, 403 },
1833 .slaves = omap2430_mcbsp4_slaves,
1834 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
1835}; 404};
1836 405
1837/* mcbsp5 */ 406/* mcbsp5 */
@@ -1848,30 +417,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
1848 { .dma_req = -1 } 417 { .dma_req = -1 }
1849}; 418};
1850 419
1851static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
1852 {
1853 .name = "mpu",
1854 .pa_start = 0x48096000,
1855 .pa_end = 0x480960ff,
1856 .flags = ADDR_TYPE_RT
1857 },
1858 { }
1859};
1860
1861/* l4_core -> mcbsp5 */
1862static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
1863 .master = &omap2430_l4_core_hwmod,
1864 .slave = &omap2430_mcbsp5_hwmod,
1865 .clk = "mcbsp5_ick",
1866 .addr = omap2430_mcbsp5_addrs,
1867 .user = OCP_USER_MPU | OCP_USER_SDMA,
1868};
1869
1870/* mcbsp5 slave ports */
1871static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
1872 &omap2430_l4_core__mcbsp5,
1873};
1874
1875static struct omap_hwmod omap2430_mcbsp5_hwmod = { 420static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1876 .name = "mcbsp5", 421 .name = "mcbsp5",
1877 .class = &omap2430_mcbsp_hwmod_class, 422 .class = &omap2430_mcbsp_hwmod_class,
@@ -1887,12 +432,9 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
1887 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 432 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
1888 }, 433 },
1889 }, 434 },
1890 .slaves = omap2430_mcbsp5_slaves,
1891 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
1892}; 435};
1893 436
1894/* MMC/SD/SDIO common */ 437/* MMC/SD/SDIO common */
1895
1896static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { 438static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
1897 .rev_offs = 0x1fc, 439 .rev_offs = 0x1fc,
1898 .sysc_offs = 0x10, 440 .sysc_offs = 0x10,
@@ -1910,7 +452,6 @@ static struct omap_hwmod_class omap2430_mmc_class = {
1910}; 452};
1911 453
1912/* MMC/SD/SDIO1 */ 454/* MMC/SD/SDIO1 */
1913
1914static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { 455static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
1915 { .irq = 83 }, 456 { .irq = 83 },
1916 { .irq = -1 } 457 { .irq = -1 }
@@ -1926,10 +467,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
1926 { .role = "dbck", .clk = "mmchsdb1_fck" }, 467 { .role = "dbck", .clk = "mmchsdb1_fck" },
1927}; 468};
1928 469
1929static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
1930 &omap2430_l4_core__mmc1,
1931};
1932
1933static struct omap_mmc_dev_attr mmc1_dev_attr = { 470static struct omap_mmc_dev_attr mmc1_dev_attr = {
1934 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 471 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1935}; 472};
@@ -1952,13 +489,10 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
1952 }, 489 },
1953 }, 490 },
1954 .dev_attr = &mmc1_dev_attr, 491 .dev_attr = &mmc1_dev_attr,
1955 .slaves = omap2430_mmc1_slaves,
1956 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
1957 .class = &omap2430_mmc_class, 492 .class = &omap2430_mmc_class,
1958}; 493};
1959 494
1960/* MMC/SD/SDIO2 */ 495/* MMC/SD/SDIO2 */
1961
1962static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { 496static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
1963 { .irq = 86 }, 497 { .irq = 86 },
1964 { .irq = -1 } 498 { .irq = -1 }
@@ -1974,10 +508,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
1974 { .role = "dbck", .clk = "mmchsdb2_fck" }, 508 { .role = "dbck", .clk = "mmchsdb2_fck" },
1975}; 509};
1976 510
1977static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
1978 &omap2430_l4_core__mmc2,
1979};
1980
1981static struct omap_hwmod omap2430_mmc2_hwmod = { 511static struct omap_hwmod omap2430_mmc2_hwmod = {
1982 .name = "mmc2", 512 .name = "mmc2",
1983 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 513 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1995,78 +525,418 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
1995 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, 525 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
1996 }, 526 },
1997 }, 527 },
1998 .slaves = omap2430_mmc2_slaves,
1999 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
2000 .class = &omap2430_mmc_class, 528 .class = &omap2430_mmc_class,
2001}; 529};
2002 530
2003static __initdata struct omap_hwmod *omap2430_hwmods[] = { 531/* HDQ1W/1-wire */
2004 &omap2430_l3_main_hwmod, 532static struct omap_hwmod omap2430_hdq1w_hwmod = {
2005 &omap2430_l4_core_hwmod, 533 .name = "hdq1w",
2006 &omap2430_l4_wkup_hwmod, 534 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2007 &omap2430_mpu_hwmod, 535 .main_clk = "hdq_fck",
2008 &omap2430_iva_hwmod, 536 .prcm = {
2009 537 .omap2 = {
2010 &omap2430_timer1_hwmod, 538 .module_offs = CORE_MOD,
2011 &omap2430_timer2_hwmod, 539 .prcm_reg_id = 1,
2012 &omap2430_timer3_hwmod, 540 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
2013 &omap2430_timer4_hwmod, 541 .idlest_reg_id = 1,
2014 &omap2430_timer5_hwmod, 542 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
2015 &omap2430_timer6_hwmod, 543 },
2016 &omap2430_timer7_hwmod, 544 },
2017 &omap2430_timer8_hwmod, 545 .class = &omap2_hdq1w_class,
2018 &omap2430_timer9_hwmod, 546};
2019 &omap2430_timer10_hwmod, 547
2020 &omap2430_timer11_hwmod, 548/*
2021 &omap2430_timer12_hwmod, 549 * interfaces
2022 550 */
2023 &omap2430_wd_timer2_hwmod, 551
2024 &omap2430_uart1_hwmod, 552/* L3 -> L4_CORE interface */
2025 &omap2430_uart2_hwmod, 553/* l3_core -> usbhsotg interface */
2026 &omap2430_uart3_hwmod, 554static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
2027 /* dss class */ 555 .master = &omap2430_usbhsotg_hwmod,
2028 &omap2430_dss_core_hwmod, 556 .slave = &omap2xxx_l3_main_hwmod,
2029 &omap2430_dss_dispc_hwmod, 557 .clk = "core_l3_ck",
2030 &omap2430_dss_rfbi_hwmod, 558 .user = OCP_USER_MPU,
2031 &omap2430_dss_venc_hwmod, 559};
2032 /* i2c class */ 560
2033 &omap2430_i2c1_hwmod, 561/* L4 CORE -> I2C1 interface */
2034 &omap2430_i2c2_hwmod, 562static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
2035 &omap2430_mmc1_hwmod, 563 .master = &omap2xxx_l4_core_hwmod,
2036 &omap2430_mmc2_hwmod, 564 .slave = &omap2430_i2c1_hwmod,
2037 565 .clk = "i2c1_ick",
2038 /* gpio class */ 566 .addr = omap2_i2c1_addr_space,
2039 &omap2430_gpio1_hwmod, 567 .user = OCP_USER_MPU | OCP_USER_SDMA,
2040 &omap2430_gpio2_hwmod, 568};
2041 &omap2430_gpio3_hwmod, 569
2042 &omap2430_gpio4_hwmod, 570/* L4 CORE -> I2C2 interface */
2043 &omap2430_gpio5_hwmod, 571static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
2044 572 .master = &omap2xxx_l4_core_hwmod,
2045 /* dma_system class*/ 573 .slave = &omap2430_i2c2_hwmod,
2046 &omap2430_dma_system_hwmod, 574 .clk = "i2c2_ick",
2047 575 .addr = omap2_i2c2_addr_space,
2048 /* mcbsp class */ 576 .user = OCP_USER_MPU | OCP_USER_SDMA,
2049 &omap2430_mcbsp1_hwmod, 577};
2050 &omap2430_mcbsp2_hwmod, 578
2051 &omap2430_mcbsp3_hwmod, 579static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
2052 &omap2430_mcbsp4_hwmod, 580 {
2053 &omap2430_mcbsp5_hwmod, 581 .pa_start = OMAP243X_HS_BASE,
2054 582 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
2055 /* mailbox class */ 583 .flags = ADDR_TYPE_RT
2056 &omap2430_mailbox_hwmod, 584 },
2057 585 { }
2058 /* mcspi class */ 586};
2059 &omap2430_mcspi1_hwmod, 587
2060 &omap2430_mcspi2_hwmod, 588/* l4_core ->usbhsotg interface */
2061 &omap2430_mcspi3_hwmod, 589static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
2062 590 .master = &omap2xxx_l4_core_hwmod,
2063 /* usbotg class*/ 591 .slave = &omap2430_usbhsotg_hwmod,
2064 &omap2430_usbhsotg_hwmod, 592 .clk = "usb_l4_ick",
593 .addr = omap2430_usbhsotg_addrs,
594 .user = OCP_USER_MPU,
595};
2065 596
597/* L4 CORE -> MMC1 interface */
598static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
599 .master = &omap2xxx_l4_core_hwmod,
600 .slave = &omap2430_mmc1_hwmod,
601 .clk = "mmchs1_ick",
602 .addr = omap2430_mmc1_addr_space,
603 .user = OCP_USER_MPU | OCP_USER_SDMA,
604};
605
606/* L4 CORE -> MMC2 interface */
607static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
608 .master = &omap2xxx_l4_core_hwmod,
609 .slave = &omap2430_mmc2_hwmod,
610 .clk = "mmchs2_ick",
611 .addr = omap2430_mmc2_addr_space,
612 .user = OCP_USER_MPU | OCP_USER_SDMA,
613};
614
615/* l4 core -> mcspi3 interface */
616static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
617 .master = &omap2xxx_l4_core_hwmod,
618 .slave = &omap2430_mcspi3_hwmod,
619 .clk = "mcspi3_ick",
620 .addr = omap2430_mcspi3_addr_space,
621 .user = OCP_USER_MPU | OCP_USER_SDMA,
622};
623
624/* IVA2 <- L3 interface */
625static struct omap_hwmod_ocp_if omap2430_l3__iva = {
626 .master = &omap2xxx_l3_main_hwmod,
627 .slave = &omap2430_iva_hwmod,
628 .clk = "core_l3_ck",
629 .user = OCP_USER_MPU | OCP_USER_SDMA,
630};
631
632static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
633 {
634 .pa_start = 0x49018000,
635 .pa_end = 0x49018000 + SZ_1K - 1,
636 .flags = ADDR_TYPE_RT
637 },
638 { }
639};
640
641/* l4_wkup -> timer1 */
642static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
643 .master = &omap2xxx_l4_wkup_hwmod,
644 .slave = &omap2xxx_timer1_hwmod,
645 .clk = "gpt1_ick",
646 .addr = omap2430_timer1_addrs,
647 .user = OCP_USER_MPU | OCP_USER_SDMA,
648};
649
650/* l4_wkup -> wd_timer2 */
651static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
652 {
653 .pa_start = 0x49016000,
654 .pa_end = 0x4901607f,
655 .flags = ADDR_TYPE_RT
656 },
657 { }
658};
659
660static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
661 .master = &omap2xxx_l4_wkup_hwmod,
662 .slave = &omap2xxx_wd_timer2_hwmod,
663 .clk = "mpu_wdt_ick",
664 .addr = omap2430_wd_timer2_addrs,
665 .user = OCP_USER_MPU | OCP_USER_SDMA,
666};
667
668/* l4_wkup -> gpio1 */
669static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
670 {
671 .pa_start = 0x4900C000,
672 .pa_end = 0x4900C1ff,
673 .flags = ADDR_TYPE_RT
674 },
675 { }
676};
677
678static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
679 .master = &omap2xxx_l4_wkup_hwmod,
680 .slave = &omap2xxx_gpio1_hwmod,
681 .clk = "gpios_ick",
682 .addr = omap2430_gpio1_addr_space,
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
684};
685
686/* l4_wkup -> gpio2 */
687static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
688 {
689 .pa_start = 0x4900E000,
690 .pa_end = 0x4900E1ff,
691 .flags = ADDR_TYPE_RT
692 },
693 { }
694};
695
696static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
697 .master = &omap2xxx_l4_wkup_hwmod,
698 .slave = &omap2xxx_gpio2_hwmod,
699 .clk = "gpios_ick",
700 .addr = omap2430_gpio2_addr_space,
701 .user = OCP_USER_MPU | OCP_USER_SDMA,
702};
703
704/* l4_wkup -> gpio3 */
705static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
706 {
707 .pa_start = 0x49010000,
708 .pa_end = 0x490101ff,
709 .flags = ADDR_TYPE_RT
710 },
711 { }
712};
713
714static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
715 .master = &omap2xxx_l4_wkup_hwmod,
716 .slave = &omap2xxx_gpio3_hwmod,
717 .clk = "gpios_ick",
718 .addr = omap2430_gpio3_addr_space,
719 .user = OCP_USER_MPU | OCP_USER_SDMA,
720};
721
722/* l4_wkup -> gpio4 */
723static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
724 {
725 .pa_start = 0x49012000,
726 .pa_end = 0x490121ff,
727 .flags = ADDR_TYPE_RT
728 },
729 { }
730};
731
732static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
733 .master = &omap2xxx_l4_wkup_hwmod,
734 .slave = &omap2xxx_gpio4_hwmod,
735 .clk = "gpios_ick",
736 .addr = omap2430_gpio4_addr_space,
737 .user = OCP_USER_MPU | OCP_USER_SDMA,
738};
739
740/* l4_core -> gpio5 */
741static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
742 {
743 .pa_start = 0x480B6000,
744 .pa_end = 0x480B61ff,
745 .flags = ADDR_TYPE_RT
746 },
747 { }
748};
749
750static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
751 .master = &omap2xxx_l4_core_hwmod,
752 .slave = &omap2430_gpio5_hwmod,
753 .clk = "gpio5_ick",
754 .addr = omap2430_gpio5_addr_space,
755 .user = OCP_USER_MPU | OCP_USER_SDMA,
756};
757
758/* dma_system -> L3 */
759static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
760 .master = &omap2430_dma_system_hwmod,
761 .slave = &omap2xxx_l3_main_hwmod,
762 .clk = "core_l3_ck",
763 .user = OCP_USER_MPU | OCP_USER_SDMA,
764};
765
766/* l4_core -> dma_system */
767static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
768 .master = &omap2xxx_l4_core_hwmod,
769 .slave = &omap2430_dma_system_hwmod,
770 .clk = "sdma_ick",
771 .addr = omap2_dma_system_addrs,
772 .user = OCP_USER_MPU | OCP_USER_SDMA,
773};
774
775/* l4_core -> mailbox */
776static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
777 .master = &omap2xxx_l4_core_hwmod,
778 .slave = &omap2430_mailbox_hwmod,
779 .addr = omap2_mailbox_addrs,
780 .user = OCP_USER_MPU | OCP_USER_SDMA,
781};
782
783/* l4_core -> mcbsp1 */
784static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
785 .master = &omap2xxx_l4_core_hwmod,
786 .slave = &omap2430_mcbsp1_hwmod,
787 .clk = "mcbsp1_ick",
788 .addr = omap2_mcbsp1_addrs,
789 .user = OCP_USER_MPU | OCP_USER_SDMA,
790};
791
792/* l4_core -> mcbsp2 */
793static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
794 .master = &omap2xxx_l4_core_hwmod,
795 .slave = &omap2430_mcbsp2_hwmod,
796 .clk = "mcbsp2_ick",
797 .addr = omap2xxx_mcbsp2_addrs,
798 .user = OCP_USER_MPU | OCP_USER_SDMA,
799};
800
801static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
802 {
803 .name = "mpu",
804 .pa_start = 0x4808C000,
805 .pa_end = 0x4808C0ff,
806 .flags = ADDR_TYPE_RT
807 },
808 { }
809};
810
811/* l4_core -> mcbsp3 */
812static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
813 .master = &omap2xxx_l4_core_hwmod,
814 .slave = &omap2430_mcbsp3_hwmod,
815 .clk = "mcbsp3_ick",
816 .addr = omap2430_mcbsp3_addrs,
817 .user = OCP_USER_MPU | OCP_USER_SDMA,
818};
819
820static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
821 {
822 .name = "mpu",
823 .pa_start = 0x4808E000,
824 .pa_end = 0x4808E0ff,
825 .flags = ADDR_TYPE_RT
826 },
827 { }
828};
829
830/* l4_core -> mcbsp4 */
831static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
832 .master = &omap2xxx_l4_core_hwmod,
833 .slave = &omap2430_mcbsp4_hwmod,
834 .clk = "mcbsp4_ick",
835 .addr = omap2430_mcbsp4_addrs,
836 .user = OCP_USER_MPU | OCP_USER_SDMA,
837};
838
839static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
840 {
841 .name = "mpu",
842 .pa_start = 0x48096000,
843 .pa_end = 0x480960ff,
844 .flags = ADDR_TYPE_RT
845 },
846 { }
847};
848
849/* l4_core -> mcbsp5 */
850static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
851 .master = &omap2xxx_l4_core_hwmod,
852 .slave = &omap2430_mcbsp5_hwmod,
853 .clk = "mcbsp5_ick",
854 .addr = omap2430_mcbsp5_addrs,
855 .user = OCP_USER_MPU | OCP_USER_SDMA,
856};
857
858/* l4_core -> hdq1w */
859static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
860 .master = &omap2xxx_l4_core_hwmod,
861 .slave = &omap2430_hdq1w_hwmod,
862 .clk = "hdq_ick",
863 .addr = omap2_hdq1w_addr_space,
864 .user = OCP_USER_MPU | OCP_USER_SDMA,
865 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
866};
867
868/* l4_wkup -> 32ksync_counter */
869static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
870 {
871 .pa_start = 0x49020000,
872 .pa_end = 0x4902001f,
873 .flags = ADDR_TYPE_RT
874 },
875 { }
876};
877
878static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
879 .master = &omap2xxx_l4_wkup_hwmod,
880 .slave = &omap2xxx_counter_32k_hwmod,
881 .clk = "sync_32k_ick",
882 .addr = omap2430_counter_32k_addrs,
883 .user = OCP_USER_MPU | OCP_USER_SDMA,
884};
885
886static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
887 &omap2xxx_l3_main__l4_core,
888 &omap2xxx_mpu__l3_main,
889 &omap2xxx_dss__l3,
890 &omap2430_usbhsotg__l3,
891 &omap2430_l4_core__i2c1,
892 &omap2430_l4_core__i2c2,
893 &omap2xxx_l4_core__l4_wkup,
894 &omap2_l4_core__uart1,
895 &omap2_l4_core__uart2,
896 &omap2_l4_core__uart3,
897 &omap2430_l4_core__usbhsotg,
898 &omap2430_l4_core__mmc1,
899 &omap2430_l4_core__mmc2,
900 &omap2xxx_l4_core__mcspi1,
901 &omap2xxx_l4_core__mcspi2,
902 &omap2430_l4_core__mcspi3,
903 &omap2430_l3__iva,
904 &omap2430_l4_wkup__timer1,
905 &omap2xxx_l4_core__timer2,
906 &omap2xxx_l4_core__timer3,
907 &omap2xxx_l4_core__timer4,
908 &omap2xxx_l4_core__timer5,
909 &omap2xxx_l4_core__timer6,
910 &omap2xxx_l4_core__timer7,
911 &omap2xxx_l4_core__timer8,
912 &omap2xxx_l4_core__timer9,
913 &omap2xxx_l4_core__timer10,
914 &omap2xxx_l4_core__timer11,
915 &omap2xxx_l4_core__timer12,
916 &omap2430_l4_wkup__wd_timer2,
917 &omap2xxx_l4_core__dss,
918 &omap2xxx_l4_core__dss_dispc,
919 &omap2xxx_l4_core__dss_rfbi,
920 &omap2xxx_l4_core__dss_venc,
921 &omap2430_l4_wkup__gpio1,
922 &omap2430_l4_wkup__gpio2,
923 &omap2430_l4_wkup__gpio3,
924 &omap2430_l4_wkup__gpio4,
925 &omap2430_l4_core__gpio5,
926 &omap2430_dma_system__l3,
927 &omap2430_l4_core__dma_system,
928 &omap2430_l4_core__mailbox,
929 &omap2430_l4_core__mcbsp1,
930 &omap2430_l4_core__mcbsp2,
931 &omap2430_l4_core__mcbsp3,
932 &omap2430_l4_core__mcbsp4,
933 &omap2430_l4_core__mcbsp5,
934 &omap2430_l4_core__hdq1w,
935 &omap2430_l4_wkup__counter_32k,
2066 NULL, 936 NULL,
2067}; 937};
2068 938
2069int __init omap2430_hwmod_init(void) 939int __init omap2430_hwmod_init(void)
2070{ 940{
2071 return omap_hwmod_register(omap2430_hwmods); 941 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
2072} 942}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index 04637fabadd2..cbb4ef6544ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -171,3 +171,12 @@ struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
171 }, 171 },
172 { } 172 { }
173}; 173};
174
175struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
176 {
177 .pa_start = 0x480b2000,
178 .pa_end = 0x480b2fff,
179 .flags = ADDR_TYPE_RT,
180 },
181 { }
182};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index f08e442af397..102d76e9e9ea 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3 2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
3 * 3 *
4 * Copyright (C) 2011 Nokia Corporation 4 * Copyright (C) 2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -12,6 +13,7 @@
12#include <plat/serial.h> 13#include <plat/serial.h>
13#include <plat/dma.h> 14#include <plat/dma.h>
14#include <plat/common.h> 15#include <plat/common.h>
16#include <plat/hdq1w.h>
15 17
16#include <mach/irqs.h> 18#include <mach/irqs.h>
17 19
@@ -302,3 +304,23 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
302 { .irq = -1 } 304 { .irq = -1 }
303}; 305};
304 306
307struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
308 .rev_offs = 0x0,
309 .sysc_offs = 0x14,
310 .syss_offs = 0x18,
311 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
312 SYSS_HAS_RESET_STATUS),
313 .sysc_fields = &omap_hwmod_sysc_type1,
314};
315
316struct omap_hwmod_class omap2_hdq1w_class = {
317 .name = "hdq1w",
318 .sysc = &omap2_hdq1w_sysc,
319 .reset = &omap_hdq1w_reset,
320};
321
322struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
323 { .irq = 58, },
324 { .irq = -1 }
325};
326
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 4f3547c2a49e..5178e40e84f9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -15,10 +15,12 @@
15 15
16#include <plat/omap_hwmod.h> 16#include <plat/omap_hwmod.h>
17#include <plat/serial.h> 17#include <plat/serial.h>
18#include <plat/l3_2xxx.h>
19#include <plat/l4_2xxx.h>
18 20
19#include "omap_hwmod_common_data.h" 21#include "omap_hwmod_common_data.h"
20 22
21struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = { 23static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
22 { 24 {
23 .pa_start = OMAP2_UART1_BASE, 25 .pa_start = OMAP2_UART1_BASE,
24 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, 26 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
@@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
27 { } 29 { }
28}; 30};
29 31
30struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = { 32static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
31 { 33 {
32 .pa_start = OMAP2_UART2_BASE, 34 .pa_start = OMAP2_UART2_BASE,
33 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, 35 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
@@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
36 { } 38 { }
37}; 39};
38 40
39struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = { 41static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
40 { 42 {
41 .pa_start = OMAP2_UART3_BASE, 43 .pa_start = OMAP2_UART3_BASE,
42 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, 44 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
@@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
45 { } 47 { }
46}; 48};
47 49
48struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = { 50static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
49 { 51 {
50 .pa_start = 0x4802a000, 52 .pa_start = 0x4802a000,
51 .pa_end = 0x4802a000 + SZ_1K - 1, 53 .pa_end = 0x4802a000 + SZ_1K - 1,
@@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
54 { } 56 { }
55}; 57};
56 58
57struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = { 59static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
58 { 60 {
59 .pa_start = 0x48078000, 61 .pa_start = 0x48078000,
60 .pa_end = 0x48078000 + SZ_1K - 1, 62 .pa_end = 0x48078000 + SZ_1K - 1,
@@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
63 { } 65 { }
64}; 66};
65 67
66struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = { 68static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
67 { 69 {
68 .pa_start = 0x4807a000, 70 .pa_start = 0x4807a000,
69 .pa_end = 0x4807a000 + SZ_1K - 1, 71 .pa_end = 0x4807a000 + SZ_1K - 1,
@@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
72 { } 74 { }
73}; 75};
74 76
75struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = { 77static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
76 { 78 {
77 .pa_start = 0x4807c000, 79 .pa_start = 0x4807c000,
78 .pa_end = 0x4807c000 + SZ_1K - 1, 80 .pa_end = 0x4807c000 + SZ_1K - 1,
@@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
81 { } 83 { }
82}; 84};
83 85
84struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = { 86static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
85 { 87 {
86 .pa_start = 0x4807e000, 88 .pa_start = 0x4807e000,
87 .pa_end = 0x4807e000 + SZ_1K - 1, 89 .pa_end = 0x4807e000 + SZ_1K - 1,
@@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
90 { } 92 { }
91}; 93};
92 94
93struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = { 95static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
94 { 96 {
95 .pa_start = 0x48080000, 97 .pa_start = 0x48080000,
96 .pa_end = 0x48080000 + SZ_1K - 1, 98 .pa_end = 0x48080000 + SZ_1K - 1,
@@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
99 { } 101 { }
100}; 102};
101 103
102struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = { 104static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
103 { 105 {
104 .pa_start = 0x48082000, 106 .pa_start = 0x48082000,
105 .pa_end = 0x48082000 + SZ_1K - 1, 107 .pa_end = 0x48082000 + SZ_1K - 1,
@@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
108 { } 110 { }
109}; 111};
110 112
111struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = { 113static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
112 { 114 {
113 .pa_start = 0x48084000, 115 .pa_start = 0x48084000,
114 .pa_end = 0x48084000 + SZ_1K - 1, 116 .pa_end = 0x48084000 + SZ_1K - 1,
@@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
127 { } 129 { }
128}; 130};
129 131
132/*
133 * Common interconnect data
134 */
135
136/* L3 -> L4_CORE interface */
137struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
138 .master = &omap2xxx_l3_main_hwmod,
139 .slave = &omap2xxx_l4_core_hwmod,
140 .user = OCP_USER_MPU | OCP_USER_SDMA,
141};
142
143/* MPU -> L3 interface */
144struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
145 .master = &omap2xxx_mpu_hwmod,
146 .slave = &omap2xxx_l3_main_hwmod,
147 .user = OCP_USER_MPU,
148};
149
150/* DSS -> l3 */
151struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
152 .master = &omap2xxx_dss_core_hwmod,
153 .slave = &omap2xxx_l3_main_hwmod,
154 .fw = {
155 .omap2 = {
156 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
157 .flags = OMAP_FIREWALL_L3,
158 }
159 },
160 .user = OCP_USER_MPU | OCP_USER_SDMA,
161};
162
163/* L4_CORE -> L4_WKUP interface */
164struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
165 .master = &omap2xxx_l4_core_hwmod,
166 .slave = &omap2xxx_l4_wkup_hwmod,
167 .user = OCP_USER_MPU | OCP_USER_SDMA,
168};
169
170/* L4 CORE -> UART1 interface */
171struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
172 .master = &omap2xxx_l4_core_hwmod,
173 .slave = &omap2xxx_uart1_hwmod,
174 .clk = "uart1_ick",
175 .addr = omap2xxx_uart1_addr_space,
176 .user = OCP_USER_MPU | OCP_USER_SDMA,
177};
178
179/* L4 CORE -> UART2 interface */
180struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
181 .master = &omap2xxx_l4_core_hwmod,
182 .slave = &omap2xxx_uart2_hwmod,
183 .clk = "uart2_ick",
184 .addr = omap2xxx_uart2_addr_space,
185 .user = OCP_USER_MPU | OCP_USER_SDMA,
186};
187
188/* L4 PER -> UART3 interface */
189struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
190 .master = &omap2xxx_l4_core_hwmod,
191 .slave = &omap2xxx_uart3_hwmod,
192 .clk = "uart3_ick",
193 .addr = omap2xxx_uart3_addr_space,
194 .user = OCP_USER_MPU | OCP_USER_SDMA,
195};
196
197/* l4 core -> mcspi1 interface */
198struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
199 .master = &omap2xxx_l4_core_hwmod,
200 .slave = &omap2xxx_mcspi1_hwmod,
201 .clk = "mcspi1_ick",
202 .addr = omap2_mcspi1_addr_space,
203 .user = OCP_USER_MPU | OCP_USER_SDMA,
204};
205
206/* l4 core -> mcspi2 interface */
207struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
208 .master = &omap2xxx_l4_core_hwmod,
209 .slave = &omap2xxx_mcspi2_hwmod,
210 .clk = "mcspi2_ick",
211 .addr = omap2_mcspi2_addr_space,
212 .user = OCP_USER_MPU | OCP_USER_SDMA,
213};
214
215/* l4_core -> timer2 */
216struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
217 .master = &omap2xxx_l4_core_hwmod,
218 .slave = &omap2xxx_timer2_hwmod,
219 .clk = "gpt2_ick",
220 .addr = omap2xxx_timer2_addrs,
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
222};
223
224/* l4_core -> timer3 */
225struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
226 .master = &omap2xxx_l4_core_hwmod,
227 .slave = &omap2xxx_timer3_hwmod,
228 .clk = "gpt3_ick",
229 .addr = omap2xxx_timer3_addrs,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231};
232
233/* l4_core -> timer4 */
234struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
235 .master = &omap2xxx_l4_core_hwmod,
236 .slave = &omap2xxx_timer4_hwmod,
237 .clk = "gpt4_ick",
238 .addr = omap2xxx_timer4_addrs,
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
240};
241
242/* l4_core -> timer5 */
243struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
244 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2xxx_timer5_hwmod,
246 .clk = "gpt5_ick",
247 .addr = omap2xxx_timer5_addrs,
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
249};
250
251/* l4_core -> timer6 */
252struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
253 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2xxx_timer6_hwmod,
255 .clk = "gpt6_ick",
256 .addr = omap2xxx_timer6_addrs,
257 .user = OCP_USER_MPU | OCP_USER_SDMA,
258};
259
260/* l4_core -> timer7 */
261struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
262 .master = &omap2xxx_l4_core_hwmod,
263 .slave = &omap2xxx_timer7_hwmod,
264 .clk = "gpt7_ick",
265 .addr = omap2xxx_timer7_addrs,
266 .user = OCP_USER_MPU | OCP_USER_SDMA,
267};
268
269/* l4_core -> timer8 */
270struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
271 .master = &omap2xxx_l4_core_hwmod,
272 .slave = &omap2xxx_timer8_hwmod,
273 .clk = "gpt8_ick",
274 .addr = omap2xxx_timer8_addrs,
275 .user = OCP_USER_MPU | OCP_USER_SDMA,
276};
277
278/* l4_core -> timer9 */
279struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
280 .master = &omap2xxx_l4_core_hwmod,
281 .slave = &omap2xxx_timer9_hwmod,
282 .clk = "gpt9_ick",
283 .addr = omap2xxx_timer9_addrs,
284 .user = OCP_USER_MPU | OCP_USER_SDMA,
285};
286
287/* l4_core -> timer10 */
288struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
289 .master = &omap2xxx_l4_core_hwmod,
290 .slave = &omap2xxx_timer10_hwmod,
291 .clk = "gpt10_ick",
292 .addr = omap2_timer10_addrs,
293 .user = OCP_USER_MPU | OCP_USER_SDMA,
294};
295
296/* l4_core -> timer11 */
297struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
298 .master = &omap2xxx_l4_core_hwmod,
299 .slave = &omap2xxx_timer11_hwmod,
300 .clk = "gpt11_ick",
301 .addr = omap2_timer11_addrs,
302 .user = OCP_USER_MPU | OCP_USER_SDMA,
303};
304
305/* l4_core -> timer12 */
306struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
307 .master = &omap2xxx_l4_core_hwmod,
308 .slave = &omap2xxx_timer12_hwmod,
309 .clk = "gpt12_ick",
310 .addr = omap2xxx_timer12_addrs,
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
312};
313
314/* l4_core -> dss */
315struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
316 .master = &omap2xxx_l4_core_hwmod,
317 .slave = &omap2xxx_dss_core_hwmod,
318 .clk = "dss_ick",
319 .addr = omap2_dss_addrs,
320 .fw = {
321 .omap2 = {
322 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
323 .flags = OMAP_FIREWALL_L4,
324 }
325 },
326 .user = OCP_USER_MPU | OCP_USER_SDMA,
327};
328
329/* l4_core -> dss_dispc */
330struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
331 .master = &omap2xxx_l4_core_hwmod,
332 .slave = &omap2xxx_dss_dispc_hwmod,
333 .clk = "dss_ick",
334 .addr = omap2_dss_dispc_addrs,
335 .fw = {
336 .omap2 = {
337 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
338 .flags = OMAP_FIREWALL_L4,
339 }
340 },
341 .user = OCP_USER_MPU | OCP_USER_SDMA,
342};
343
344/* l4_core -> dss_rfbi */
345struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
346 .master = &omap2xxx_l4_core_hwmod,
347 .slave = &omap2xxx_dss_rfbi_hwmod,
348 .clk = "dss_ick",
349 .addr = omap2_dss_rfbi_addrs,
350 .fw = {
351 .omap2 = {
352 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
353 .flags = OMAP_FIREWALL_L4,
354 }
355 },
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
357};
358
359/* l4_core -> dss_venc */
360struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
361 .master = &omap2xxx_l4_core_hwmod,
362 .slave = &omap2xxx_dss_venc_hwmod,
363 .clk = "dss_ick",
364 .addr = omap2_dss_venc_addrs,
365 .fw = {
366 .omap2 = {
367 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
368 .flags = OMAP_FIREWALL_L4,
369 }
370 },
371 .flags = OCPIF_SWSUP_IDLE,
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
373};
130 374
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 2a6729741b06..83eafd96ecaa 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,6 +10,7 @@
10 */ 10 */
11#include <plat/omap_hwmod.h> 11#include <plat/omap_hwmod.h>
12#include <plat/serial.h> 12#include <plat/serial.h>
13#include <plat/gpio.h>
13#include <plat/dma.h> 14#include <plat/dma.h>
14#include <plat/dmtimer.h> 15#include <plat/dmtimer.h>
15#include <plat/mcspi.h> 16#include <plat/mcspi.h>
@@ -17,6 +18,8 @@
17#include <mach/irqs.h> 18#include <mach/irqs.h>
18 19
19#include "omap_hwmod_common_data.h" 20#include "omap_hwmod_common_data.h"
21#include "cm-regbits-24xx.h"
22#include "prm-regbits-24xx.h"
20#include "wd_timer.h" 23#include "wd_timer.h"
21 24
22struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { 25struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
@@ -86,7 +89,8 @@ static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
86struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = { 89struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
87 .name = "wd_timer", 90 .name = "wd_timer",
88 .sysc = &omap2xxx_wd_timer_sysc, 91 .sysc = &omap2xxx_wd_timer_sysc,
89 .pre_shutdown = &omap2_wd_timer_disable 92 .pre_shutdown = &omap2_wd_timer_disable,
93 .reset = &omap2_wd_timer_reset,
90}; 94};
91 95
92/* 96/*
@@ -170,3 +174,582 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
170 .sysc = &omap2xxx_mcspi_sysc, 174 .sysc = &omap2xxx_mcspi_sysc,
171 .rev = OMAP2_MCSPI_REV, 175 .rev = OMAP2_MCSPI_REV,
172}; 176};
177
178/*
179 * IP blocks
180 */
181
182/* L3 */
183struct omap_hwmod omap2xxx_l3_main_hwmod = {
184 .name = "l3_main",
185 .class = &l3_hwmod_class,
186 .flags = HWMOD_NO_IDLEST,
187};
188
189/* L4 CORE */
190struct omap_hwmod omap2xxx_l4_core_hwmod = {
191 .name = "l4_core",
192 .class = &l4_hwmod_class,
193 .flags = HWMOD_NO_IDLEST,
194};
195
196/* L4 WKUP */
197struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
198 .name = "l4_wkup",
199 .class = &l4_hwmod_class,
200 .flags = HWMOD_NO_IDLEST,
201};
202
203/* MPU */
204struct omap_hwmod omap2xxx_mpu_hwmod = {
205 .name = "mpu",
206 .class = &mpu_hwmod_class,
207 .main_clk = "mpu_ck",
208};
209
210/* IVA2 */
211struct omap_hwmod omap2xxx_iva_hwmod = {
212 .name = "iva",
213 .class = &iva_hwmod_class,
214};
215
216/* always-on timers dev attribute */
217static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
218 .timer_capability = OMAP_TIMER_ALWON,
219};
220
221/* pwm timers dev attribute */
222static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
223 .timer_capability = OMAP_TIMER_HAS_PWM,
224};
225
226/* timer1 */
227
228struct omap_hwmod omap2xxx_timer1_hwmod = {
229 .name = "timer1",
230 .mpu_irqs = omap2_timer1_mpu_irqs,
231 .main_clk = "gpt1_fck",
232 .prcm = {
233 .omap2 = {
234 .prcm_reg_id = 1,
235 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
236 .module_offs = WKUP_MOD,
237 .idlest_reg_id = 1,
238 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
239 },
240 },
241 .dev_attr = &capability_alwon_dev_attr,
242 .class = &omap2xxx_timer_hwmod_class,
243};
244
245/* timer2 */
246
247struct omap_hwmod omap2xxx_timer2_hwmod = {
248 .name = "timer2",
249 .mpu_irqs = omap2_timer2_mpu_irqs,
250 .main_clk = "gpt2_fck",
251 .prcm = {
252 .omap2 = {
253 .prcm_reg_id = 1,
254 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
255 .module_offs = CORE_MOD,
256 .idlest_reg_id = 1,
257 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
258 },
259 },
260 .dev_attr = &capability_alwon_dev_attr,
261 .class = &omap2xxx_timer_hwmod_class,
262};
263
264/* timer3 */
265
266struct omap_hwmod omap2xxx_timer3_hwmod = {
267 .name = "timer3",
268 .mpu_irqs = omap2_timer3_mpu_irqs,
269 .main_clk = "gpt3_fck",
270 .prcm = {
271 .omap2 = {
272 .prcm_reg_id = 1,
273 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
274 .module_offs = CORE_MOD,
275 .idlest_reg_id = 1,
276 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
277 },
278 },
279 .dev_attr = &capability_alwon_dev_attr,
280 .class = &omap2xxx_timer_hwmod_class,
281};
282
283/* timer4 */
284
285struct omap_hwmod omap2xxx_timer4_hwmod = {
286 .name = "timer4",
287 .mpu_irqs = omap2_timer4_mpu_irqs,
288 .main_clk = "gpt4_fck",
289 .prcm = {
290 .omap2 = {
291 .prcm_reg_id = 1,
292 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
293 .module_offs = CORE_MOD,
294 .idlest_reg_id = 1,
295 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
296 },
297 },
298 .dev_attr = &capability_alwon_dev_attr,
299 .class = &omap2xxx_timer_hwmod_class,
300};
301
302/* timer5 */
303
304struct omap_hwmod omap2xxx_timer5_hwmod = {
305 .name = "timer5",
306 .mpu_irqs = omap2_timer5_mpu_irqs,
307 .main_clk = "gpt5_fck",
308 .prcm = {
309 .omap2 = {
310 .prcm_reg_id = 1,
311 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
312 .module_offs = CORE_MOD,
313 .idlest_reg_id = 1,
314 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
315 },
316 },
317 .dev_attr = &capability_alwon_dev_attr,
318 .class = &omap2xxx_timer_hwmod_class,
319};
320
321/* timer6 */
322
323struct omap_hwmod omap2xxx_timer6_hwmod = {
324 .name = "timer6",
325 .mpu_irqs = omap2_timer6_mpu_irqs,
326 .main_clk = "gpt6_fck",
327 .prcm = {
328 .omap2 = {
329 .prcm_reg_id = 1,
330 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
331 .module_offs = CORE_MOD,
332 .idlest_reg_id = 1,
333 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
334 },
335 },
336 .dev_attr = &capability_alwon_dev_attr,
337 .class = &omap2xxx_timer_hwmod_class,
338};
339
340/* timer7 */
341
342struct omap_hwmod omap2xxx_timer7_hwmod = {
343 .name = "timer7",
344 .mpu_irqs = omap2_timer7_mpu_irqs,
345 .main_clk = "gpt7_fck",
346 .prcm = {
347 .omap2 = {
348 .prcm_reg_id = 1,
349 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
350 .module_offs = CORE_MOD,
351 .idlest_reg_id = 1,
352 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
353 },
354 },
355 .dev_attr = &capability_alwon_dev_attr,
356 .class = &omap2xxx_timer_hwmod_class,
357};
358
359/* timer8 */
360
361struct omap_hwmod omap2xxx_timer8_hwmod = {
362 .name = "timer8",
363 .mpu_irqs = omap2_timer8_mpu_irqs,
364 .main_clk = "gpt8_fck",
365 .prcm = {
366 .omap2 = {
367 .prcm_reg_id = 1,
368 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
369 .module_offs = CORE_MOD,
370 .idlest_reg_id = 1,
371 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
372 },
373 },
374 .dev_attr = &capability_alwon_dev_attr,
375 .class = &omap2xxx_timer_hwmod_class,
376};
377
378/* timer9 */
379
380struct omap_hwmod omap2xxx_timer9_hwmod = {
381 .name = "timer9",
382 .mpu_irqs = omap2_timer9_mpu_irqs,
383 .main_clk = "gpt9_fck",
384 .prcm = {
385 .omap2 = {
386 .prcm_reg_id = 1,
387 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
388 .module_offs = CORE_MOD,
389 .idlest_reg_id = 1,
390 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
391 },
392 },
393 .dev_attr = &capability_pwm_dev_attr,
394 .class = &omap2xxx_timer_hwmod_class,
395};
396
397/* timer10 */
398
399struct omap_hwmod omap2xxx_timer10_hwmod = {
400 .name = "timer10",
401 .mpu_irqs = omap2_timer10_mpu_irqs,
402 .main_clk = "gpt10_fck",
403 .prcm = {
404 .omap2 = {
405 .prcm_reg_id = 1,
406 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
407 .module_offs = CORE_MOD,
408 .idlest_reg_id = 1,
409 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
410 },
411 },
412 .dev_attr = &capability_pwm_dev_attr,
413 .class = &omap2xxx_timer_hwmod_class,
414};
415
416/* timer11 */
417
418struct omap_hwmod omap2xxx_timer11_hwmod = {
419 .name = "timer11",
420 .mpu_irqs = omap2_timer11_mpu_irqs,
421 .main_clk = "gpt11_fck",
422 .prcm = {
423 .omap2 = {
424 .prcm_reg_id = 1,
425 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
426 .module_offs = CORE_MOD,
427 .idlest_reg_id = 1,
428 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
429 },
430 },
431 .dev_attr = &capability_pwm_dev_attr,
432 .class = &omap2xxx_timer_hwmod_class,
433};
434
435/* timer12 */
436
437struct omap_hwmod omap2xxx_timer12_hwmod = {
438 .name = "timer12",
439 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
440 .main_clk = "gpt12_fck",
441 .prcm = {
442 .omap2 = {
443 .prcm_reg_id = 1,
444 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
445 .module_offs = CORE_MOD,
446 .idlest_reg_id = 1,
447 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
448 },
449 },
450 .dev_attr = &capability_pwm_dev_attr,
451 .class = &omap2xxx_timer_hwmod_class,
452};
453
454/* wd_timer2 */
455struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
456 .name = "wd_timer2",
457 .class = &omap2xxx_wd_timer_hwmod_class,
458 .main_clk = "mpu_wdt_fck",
459 .prcm = {
460 .omap2 = {
461 .prcm_reg_id = 1,
462 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
463 .module_offs = WKUP_MOD,
464 .idlest_reg_id = 1,
465 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
466 },
467 },
468};
469
470/* UART1 */
471
472struct omap_hwmod omap2xxx_uart1_hwmod = {
473 .name = "uart1",
474 .mpu_irqs = omap2_uart1_mpu_irqs,
475 .sdma_reqs = omap2_uart1_sdma_reqs,
476 .main_clk = "uart1_fck",
477 .prcm = {
478 .omap2 = {
479 .module_offs = CORE_MOD,
480 .prcm_reg_id = 1,
481 .module_bit = OMAP24XX_EN_UART1_SHIFT,
482 .idlest_reg_id = 1,
483 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
484 },
485 },
486 .class = &omap2_uart_class,
487};
488
489/* UART2 */
490
491struct omap_hwmod omap2xxx_uart2_hwmod = {
492 .name = "uart2",
493 .mpu_irqs = omap2_uart2_mpu_irqs,
494 .sdma_reqs = omap2_uart2_sdma_reqs,
495 .main_clk = "uart2_fck",
496 .prcm = {
497 .omap2 = {
498 .module_offs = CORE_MOD,
499 .prcm_reg_id = 1,
500 .module_bit = OMAP24XX_EN_UART2_SHIFT,
501 .idlest_reg_id = 1,
502 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
503 },
504 },
505 .class = &omap2_uart_class,
506};
507
508/* UART3 */
509
510struct omap_hwmod omap2xxx_uart3_hwmod = {
511 .name = "uart3",
512 .mpu_irqs = omap2_uart3_mpu_irqs,
513 .sdma_reqs = omap2_uart3_sdma_reqs,
514 .main_clk = "uart3_fck",
515 .prcm = {
516 .omap2 = {
517 .module_offs = CORE_MOD,
518 .prcm_reg_id = 2,
519 .module_bit = OMAP24XX_EN_UART3_SHIFT,
520 .idlest_reg_id = 2,
521 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
522 },
523 },
524 .class = &omap2_uart_class,
525};
526
527/* dss */
528
529static struct omap_hwmod_opt_clk dss_opt_clks[] = {
530 /*
531 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
532 * driver does not use these clocks.
533 */
534 { .role = "tv_clk", .clk = "dss_54m_fck" },
535 { .role = "sys_clk", .clk = "dss2_fck" },
536};
537
538struct omap_hwmod omap2xxx_dss_core_hwmod = {
539 .name = "dss_core",
540 .class = &omap2_dss_hwmod_class,
541 .main_clk = "dss1_fck", /* instead of dss_fck */
542 .sdma_reqs = omap2xxx_dss_sdma_chs,
543 .prcm = {
544 .omap2 = {
545 .prcm_reg_id = 1,
546 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
547 .module_offs = CORE_MOD,
548 .idlest_reg_id = 1,
549 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
550 },
551 },
552 .opt_clks = dss_opt_clks,
553 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
554 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
555};
556
557struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
558 .name = "dss_dispc",
559 .class = &omap2_dispc_hwmod_class,
560 .mpu_irqs = omap2_dispc_irqs,
561 .main_clk = "dss1_fck",
562 .prcm = {
563 .omap2 = {
564 .prcm_reg_id = 1,
565 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
566 .module_offs = CORE_MOD,
567 .idlest_reg_id = 1,
568 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
569 },
570 },
571 .flags = HWMOD_NO_IDLEST,
572 .dev_attr = &omap2_3_dss_dispc_dev_attr
573};
574
575static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
576 { .role = "ick", .clk = "dss_ick" },
577};
578
579struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
580 .name = "dss_rfbi",
581 .class = &omap2_rfbi_hwmod_class,
582 .main_clk = "dss1_fck",
583 .prcm = {
584 .omap2 = {
585 .prcm_reg_id = 1,
586 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
587 .module_offs = CORE_MOD,
588 },
589 },
590 .opt_clks = dss_rfbi_opt_clks,
591 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
592 .flags = HWMOD_NO_IDLEST,
593};
594
595struct omap_hwmod omap2xxx_dss_venc_hwmod = {
596 .name = "dss_venc",
597 .class = &omap2_venc_hwmod_class,
598 .main_clk = "dss_54m_fck",
599 .prcm = {
600 .omap2 = {
601 .prcm_reg_id = 1,
602 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
603 .module_offs = CORE_MOD,
604 },
605 },
606 .flags = HWMOD_NO_IDLEST,
607};
608
609/* gpio dev_attr */
610struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
611 .bank_width = 32,
612 .dbck_flag = false,
613};
614
615/* gpio1 */
616struct omap_hwmod omap2xxx_gpio1_hwmod = {
617 .name = "gpio1",
618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
619 .mpu_irqs = omap2_gpio1_irqs,
620 .main_clk = "gpios_fck",
621 .prcm = {
622 .omap2 = {
623 .prcm_reg_id = 1,
624 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
625 .module_offs = WKUP_MOD,
626 .idlest_reg_id = 1,
627 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
628 },
629 },
630 .class = &omap2xxx_gpio_hwmod_class,
631 .dev_attr = &omap2xxx_gpio_dev_attr,
632};
633
634/* gpio2 */
635struct omap_hwmod omap2xxx_gpio2_hwmod = {
636 .name = "gpio2",
637 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
638 .mpu_irqs = omap2_gpio2_irqs,
639 .main_clk = "gpios_fck",
640 .prcm = {
641 .omap2 = {
642 .prcm_reg_id = 1,
643 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
644 .module_offs = WKUP_MOD,
645 .idlest_reg_id = 1,
646 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
647 },
648 },
649 .class = &omap2xxx_gpio_hwmod_class,
650 .dev_attr = &omap2xxx_gpio_dev_attr,
651};
652
653/* gpio3 */
654struct omap_hwmod omap2xxx_gpio3_hwmod = {
655 .name = "gpio3",
656 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
657 .mpu_irqs = omap2_gpio3_irqs,
658 .main_clk = "gpios_fck",
659 .prcm = {
660 .omap2 = {
661 .prcm_reg_id = 1,
662 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
663 .module_offs = WKUP_MOD,
664 .idlest_reg_id = 1,
665 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
666 },
667 },
668 .class = &omap2xxx_gpio_hwmod_class,
669 .dev_attr = &omap2xxx_gpio_dev_attr,
670};
671
672/* gpio4 */
673struct omap_hwmod omap2xxx_gpio4_hwmod = {
674 .name = "gpio4",
675 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
676 .mpu_irqs = omap2_gpio4_irqs,
677 .main_clk = "gpios_fck",
678 .prcm = {
679 .omap2 = {
680 .prcm_reg_id = 1,
681 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
682 .module_offs = WKUP_MOD,
683 .idlest_reg_id = 1,
684 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
685 },
686 },
687 .class = &omap2xxx_gpio_hwmod_class,
688 .dev_attr = &omap2xxx_gpio_dev_attr,
689};
690
691/* mcspi1 */
692static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
693 .num_chipselect = 4,
694};
695
696struct omap_hwmod omap2xxx_mcspi1_hwmod = {
697 .name = "mcspi1",
698 .mpu_irqs = omap2_mcspi1_mpu_irqs,
699 .sdma_reqs = omap2_mcspi1_sdma_reqs,
700 .main_clk = "mcspi1_fck",
701 .prcm = {
702 .omap2 = {
703 .module_offs = CORE_MOD,
704 .prcm_reg_id = 1,
705 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
706 .idlest_reg_id = 1,
707 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
708 },
709 },
710 .class = &omap2xxx_mcspi_class,
711 .dev_attr = &omap_mcspi1_dev_attr,
712};
713
714/* mcspi2 */
715static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
716 .num_chipselect = 2,
717};
718
719struct omap_hwmod omap2xxx_mcspi2_hwmod = {
720 .name = "mcspi2",
721 .mpu_irqs = omap2_mcspi2_mpu_irqs,
722 .sdma_reqs = omap2_mcspi2_sdma_reqs,
723 .main_clk = "mcspi2_fck",
724 .prcm = {
725 .omap2 = {
726 .module_offs = CORE_MOD,
727 .prcm_reg_id = 1,
728 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
729 .idlest_reg_id = 1,
730 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
731 },
732 },
733 .class = &omap2xxx_mcspi_class,
734 .dev_attr = &omap_mcspi2_dev_attr,
735};
736
737
738static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
739 .name = "counter",
740};
741
742struct omap_hwmod omap2xxx_counter_32k_hwmod = {
743 .name = "counter_32k",
744 .main_clk = "func_32k_ck",
745 .prcm = {
746 .omap2 = {
747 .module_offs = WKUP_MOD,
748 .prcm_reg_id = 1,
749 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
750 .idlest_reg_id = 1,
751 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
752 },
753 },
754 .class = &omap2xxx_counter_hwmod_class,
755};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index db86ce90c69f..fd48797fa95a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -38,491 +39,56 @@
38/* 39/*
39 * OMAP3xxx hardware module integration data 40 * OMAP3xxx hardware module integration data
40 * 41 *
41 * ALl of the data in this section should be autogeneratable from the 42 * All of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that 43 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs 44 * is driver-specific or driver-kernel integration-specific belongs
44 * elsewhere. 45 * elsewhere.
45 */ 46 */
46 47
47static struct omap_hwmod omap3xxx_mpu_hwmod; 48/*
48static struct omap_hwmod omap3xxx_iva_hwmod; 49 * IP blocks
49static struct omap_hwmod omap3xxx_l3_main_hwmod; 50 */
50static struct omap_hwmod omap3xxx_l4_core_hwmod;
51static struct omap_hwmod omap3xxx_l4_per_hwmod;
52static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53static struct omap_hwmod omap3430es1_dss_core_hwmod;
54static struct omap_hwmod omap3xxx_dss_core_hwmod;
55static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59static struct omap_hwmod omap3xxx_i2c1_hwmod;
60static struct omap_hwmod omap3xxx_i2c2_hwmod;
61static struct omap_hwmod omap3xxx_i2c3_hwmod;
62static struct omap_hwmod omap3xxx_gpio1_hwmod;
63static struct omap_hwmod omap3xxx_gpio2_hwmod;
64static struct omap_hwmod omap3xxx_gpio3_hwmod;
65static struct omap_hwmod omap3xxx_gpio4_hwmod;
66static struct omap_hwmod omap3xxx_gpio5_hwmod;
67static struct omap_hwmod omap3xxx_gpio6_hwmod;
68static struct omap_hwmod omap34xx_sr1_hwmod;
69static struct omap_hwmod omap34xx_sr2_hwmod;
70static struct omap_hwmod omap34xx_mcspi1;
71static struct omap_hwmod omap34xx_mcspi2;
72static struct omap_hwmod omap34xx_mcspi3;
73static struct omap_hwmod omap34xx_mcspi4;
74static struct omap_hwmod omap3xxx_mmc1_hwmod;
75static struct omap_hwmod omap3xxx_mmc2_hwmod;
76static struct omap_hwmod omap3xxx_mmc3_hwmod;
77static struct omap_hwmod am35xx_usbhsotg_hwmod;
78
79static struct omap_hwmod omap3xxx_dma_system_hwmod;
80
81static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
89static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
90
91/* L3 -> L4_CORE interface */
92static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
93 .master = &omap3xxx_l3_main_hwmod,
94 .slave = &omap3xxx_l4_core_hwmod,
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
96};
97
98/* L3 -> L4_PER interface */
99static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100 .master = &omap3xxx_l3_main_hwmod,
101 .slave = &omap3xxx_l4_per_hwmod,
102 .user = OCP_USER_MPU | OCP_USER_SDMA,
103};
104 51
105/* L3 taret configuration and error log registers */ 52/* L3 */
106static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 53static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
107 { .irq = INT_34XX_L3_DBG_IRQ }, 54 { .irq = INT_34XX_L3_DBG_IRQ },
108 { .irq = INT_34XX_L3_APP_IRQ }, 55 { .irq = INT_34XX_L3_APP_IRQ },
109 { .irq = -1 } 56 { .irq = -1 }
110}; 57};
111 58
112static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
113 {
114 .pa_start = 0x68000000,
115 .pa_end = 0x6800ffff,
116 .flags = ADDR_TYPE_RT,
117 },
118 { }
119};
120
121/* MPU -> L3 interface */
122static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
123 .master = &omap3xxx_mpu_hwmod,
124 .slave = &omap3xxx_l3_main_hwmod,
125 .addr = omap3xxx_l3_main_addrs,
126 .user = OCP_USER_MPU,
127};
128
129/* Slave interfaces on the L3 interconnect */
130static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
131 &omap3xxx_mpu__l3_main,
132};
133
134/* DSS -> l3 */
135static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
136 .master = &omap3xxx_dss_core_hwmod,
137 .slave = &omap3xxx_l3_main_hwmod,
138 .fw = {
139 .omap2 = {
140 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
141 .flags = OMAP_FIREWALL_L3,
142 }
143 },
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
145};
146
147/* Master interfaces on the L3 interconnect */
148static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
149 &omap3xxx_l3_main__l4_core,
150 &omap3xxx_l3_main__l4_per,
151};
152
153/* L3 */
154static struct omap_hwmod omap3xxx_l3_main_hwmod = { 59static struct omap_hwmod omap3xxx_l3_main_hwmod = {
155 .name = "l3_main", 60 .name = "l3_main",
156 .class = &l3_hwmod_class, 61 .class = &l3_hwmod_class,
157 .mpu_irqs = omap3xxx_l3_main_irqs, 62 .mpu_irqs = omap3xxx_l3_main_irqs,
158 .masters = omap3xxx_l3_main_masters,
159 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
160 .slaves = omap3xxx_l3_main_slaves,
161 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
162 .flags = HWMOD_NO_IDLEST, 63 .flags = HWMOD_NO_IDLEST,
163}; 64};
164 65
165static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
166static struct omap_hwmod omap3xxx_uart1_hwmod;
167static struct omap_hwmod omap3xxx_uart2_hwmod;
168static struct omap_hwmod omap3xxx_uart3_hwmod;
169static struct omap_hwmod omap3xxx_uart4_hwmod;
170static struct omap_hwmod am35xx_uart4_hwmod;
171static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
172
173/* l3_core -> usbhsotg interface */
174static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
175 .master = &omap3xxx_usbhsotg_hwmod,
176 .slave = &omap3xxx_l3_main_hwmod,
177 .clk = "core_l3_ick",
178 .user = OCP_USER_MPU,
179};
180
181/* l3_core -> am35xx_usbhsotg interface */
182static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
183 .master = &am35xx_usbhsotg_hwmod,
184 .slave = &omap3xxx_l3_main_hwmod,
185 .clk = "core_l3_ick",
186 .user = OCP_USER_MPU,
187};
188/* L4_CORE -> L4_WKUP interface */
189static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
190 .master = &omap3xxx_l4_core_hwmod,
191 .slave = &omap3xxx_l4_wkup_hwmod,
192 .user = OCP_USER_MPU | OCP_USER_SDMA,
193};
194
195/* L4 CORE -> MMC1 interface */
196static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
197 .master = &omap3xxx_l4_core_hwmod,
198 .slave = &omap3xxx_mmc1_hwmod,
199 .clk = "mmchs1_ick",
200 .addr = omap2430_mmc1_addr_space,
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202 .flags = OMAP_FIREWALL_L4
203};
204
205/* L4 CORE -> MMC2 interface */
206static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
207 .master = &omap3xxx_l4_core_hwmod,
208 .slave = &omap3xxx_mmc2_hwmod,
209 .clk = "mmchs2_ick",
210 .addr = omap2430_mmc2_addr_space,
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
212 .flags = OMAP_FIREWALL_L4
213};
214
215/* L4 CORE -> MMC3 interface */
216static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
217 {
218 .pa_start = 0x480ad000,
219 .pa_end = 0x480ad1ff,
220 .flags = ADDR_TYPE_RT,
221 },
222 { }
223};
224
225static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
226 .master = &omap3xxx_l4_core_hwmod,
227 .slave = &omap3xxx_mmc3_hwmod,
228 .clk = "mmchs3_ick",
229 .addr = omap3xxx_mmc3_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231 .flags = OMAP_FIREWALL_L4
232};
233
234/* L4 CORE -> UART1 interface */
235static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
236 {
237 .pa_start = OMAP3_UART1_BASE,
238 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
239 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
240 },
241 { }
242};
243
244static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
245 .master = &omap3xxx_l4_core_hwmod,
246 .slave = &omap3xxx_uart1_hwmod,
247 .clk = "uart1_ick",
248 .addr = omap3xxx_uart1_addr_space,
249 .user = OCP_USER_MPU | OCP_USER_SDMA,
250};
251
252/* L4 CORE -> UART2 interface */
253static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
254 {
255 .pa_start = OMAP3_UART2_BASE,
256 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
257 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
258 },
259 { }
260};
261
262static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
263 .master = &omap3xxx_l4_core_hwmod,
264 .slave = &omap3xxx_uart2_hwmod,
265 .clk = "uart2_ick",
266 .addr = omap3xxx_uart2_addr_space,
267 .user = OCP_USER_MPU | OCP_USER_SDMA,
268};
269
270/* L4 PER -> UART3 interface */
271static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
272 {
273 .pa_start = OMAP3_UART3_BASE,
274 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
275 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
276 },
277 { }
278};
279
280static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
281 .master = &omap3xxx_l4_per_hwmod,
282 .slave = &omap3xxx_uart3_hwmod,
283 .clk = "uart3_ick",
284 .addr = omap3xxx_uart3_addr_space,
285 .user = OCP_USER_MPU | OCP_USER_SDMA,
286};
287
288/* L4 PER -> UART4 interface */
289static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
290 {
291 .pa_start = OMAP3_UART4_BASE,
292 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
293 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
294 },
295 { }
296};
297
298static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
299 .master = &omap3xxx_l4_per_hwmod,
300 .slave = &omap3xxx_uart4_hwmod,
301 .clk = "uart4_ick",
302 .addr = omap3xxx_uart4_addr_space,
303 .user = OCP_USER_MPU | OCP_USER_SDMA,
304};
305
306/* AM35xx: L4 CORE -> UART4 interface */
307static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
308 {
309 .pa_start = OMAP3_UART4_AM35XX_BASE,
310 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
311 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
312 },
313};
314
315static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
316 .master = &omap3xxx_l4_core_hwmod,
317 .slave = &am35xx_uart4_hwmod,
318 .clk = "uart4_ick",
319 .addr = am35xx_uart4_addr_space,
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321};
322
323/* L4 CORE -> I2C1 interface */
324static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
325 .master = &omap3xxx_l4_core_hwmod,
326 .slave = &omap3xxx_i2c1_hwmod,
327 .clk = "i2c1_ick",
328 .addr = omap2_i2c1_addr_space,
329 .fw = {
330 .omap2 = {
331 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
332 .l4_prot_group = 7,
333 .flags = OMAP_FIREWALL_L4,
334 }
335 },
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337};
338
339/* L4 CORE -> I2C2 interface */
340static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
341 .master = &omap3xxx_l4_core_hwmod,
342 .slave = &omap3xxx_i2c2_hwmod,
343 .clk = "i2c2_ick",
344 .addr = omap2_i2c2_addr_space,
345 .fw = {
346 .omap2 = {
347 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
348 .l4_prot_group = 7,
349 .flags = OMAP_FIREWALL_L4,
350 }
351 },
352 .user = OCP_USER_MPU | OCP_USER_SDMA,
353};
354
355/* L4 CORE -> I2C3 interface */
356static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
357 {
358 .pa_start = 0x48060000,
359 .pa_end = 0x48060000 + SZ_128 - 1,
360 .flags = ADDR_TYPE_RT,
361 },
362 { }
363};
364
365static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
366 .master = &omap3xxx_l4_core_hwmod,
367 .slave = &omap3xxx_i2c3_hwmod,
368 .clk = "i2c3_ick",
369 .addr = omap3xxx_i2c3_addr_space,
370 .fw = {
371 .omap2 = {
372 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
373 .l4_prot_group = 7,
374 .flags = OMAP_FIREWALL_L4,
375 }
376 },
377 .user = OCP_USER_MPU | OCP_USER_SDMA,
378};
379
380static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
381 { .irq = 18},
382 { .irq = -1 }
383};
384
385static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
386 { .irq = 19},
387 { .irq = -1 }
388};
389
390/* L4 CORE -> SR1 interface */
391static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
392 {
393 .pa_start = OMAP34XX_SR1_BASE,
394 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
395 .flags = ADDR_TYPE_RT,
396 },
397 { }
398};
399
400static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
401 .master = &omap3xxx_l4_core_hwmod,
402 .slave = &omap34xx_sr1_hwmod,
403 .clk = "sr_l4_ick",
404 .addr = omap3_sr1_addr_space,
405 .user = OCP_USER_MPU,
406};
407
408/* L4 CORE -> SR1 interface */
409static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
410 {
411 .pa_start = OMAP34XX_SR2_BASE,
412 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
413 .flags = ADDR_TYPE_RT,
414 },
415 { }
416};
417
418static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
419 .master = &omap3xxx_l4_core_hwmod,
420 .slave = &omap34xx_sr2_hwmod,
421 .clk = "sr_l4_ick",
422 .addr = omap3_sr2_addr_space,
423 .user = OCP_USER_MPU,
424};
425
426/*
427* usbhsotg interface data
428*/
429
430static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
431 {
432 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
433 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
434 .flags = ADDR_TYPE_RT
435 },
436 { }
437};
438
439/* l4_core -> usbhsotg */
440static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
441 .master = &omap3xxx_l4_core_hwmod,
442 .slave = &omap3xxx_usbhsotg_hwmod,
443 .clk = "l4_ick",
444 .addr = omap3xxx_usbhsotg_addrs,
445 .user = OCP_USER_MPU,
446};
447
448static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
449 &omap3xxx_usbhsotg__l3,
450};
451
452static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
453 &omap3xxx_l4_core__usbhsotg,
454};
455
456static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
457 {
458 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
459 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
460 .flags = ADDR_TYPE_RT
461 },
462 { }
463};
464
465/* l4_core -> usbhsotg */
466static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
467 .master = &omap3xxx_l4_core_hwmod,
468 .slave = &am35xx_usbhsotg_hwmod,
469 .clk = "l4_ick",
470 .addr = am35xx_usbhsotg_addrs,
471 .user = OCP_USER_MPU,
472};
473
474static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
475 &am35xx_usbhsotg__l3,
476};
477
478static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
479 &am35xx_l4_core__usbhsotg,
480};
481/* Slave interfaces on the L4_CORE interconnect */
482static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
483 &omap3xxx_l3_main__l4_core,
484};
485
486/* L4 CORE */ 66/* L4 CORE */
487static struct omap_hwmod omap3xxx_l4_core_hwmod = { 67static struct omap_hwmod omap3xxx_l4_core_hwmod = {
488 .name = "l4_core", 68 .name = "l4_core",
489 .class = &l4_hwmod_class, 69 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_core_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
492 .flags = HWMOD_NO_IDLEST, 70 .flags = HWMOD_NO_IDLEST,
493}; 71};
494 72
495/* Slave interfaces on the L4_PER interconnect */
496static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
497 &omap3xxx_l3_main__l4_per,
498};
499
500/* L4 PER */ 73/* L4 PER */
501static struct omap_hwmod omap3xxx_l4_per_hwmod = { 74static struct omap_hwmod omap3xxx_l4_per_hwmod = {
502 .name = "l4_per", 75 .name = "l4_per",
503 .class = &l4_hwmod_class, 76 .class = &l4_hwmod_class,
504 .slaves = omap3xxx_l4_per_slaves,
505 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
506 .flags = HWMOD_NO_IDLEST, 77 .flags = HWMOD_NO_IDLEST,
507}; 78};
508 79
509/* Slave interfaces on the L4_WKUP interconnect */
510static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
511 &omap3xxx_l4_core__l4_wkup,
512};
513
514/* L4 WKUP */ 80/* L4 WKUP */
515static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 81static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
516 .name = "l4_wkup", 82 .name = "l4_wkup",
517 .class = &l4_hwmod_class, 83 .class = &l4_hwmod_class,
518 .slaves = omap3xxx_l4_wkup_slaves,
519 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
520 .flags = HWMOD_NO_IDLEST, 84 .flags = HWMOD_NO_IDLEST,
521}; 85};
522 86
523/* Master interfaces on the MPU device */ 87/* L4 SEC */
524static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { 88static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
525 &omap3xxx_mpu__l3_main, 89 .name = "l4_sec",
90 .class = &l4_hwmod_class,
91 .flags = HWMOD_NO_IDLEST,
526}; 92};
527 93
528/* MPU */ 94/* MPU */
@@ -530,35 +96,22 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
530 .name = "mpu", 96 .name = "mpu",
531 .class = &mpu_hwmod_class, 97 .class = &mpu_hwmod_class,
532 .main_clk = "arm_fck", 98 .main_clk = "arm_fck",
533 .masters = omap3xxx_mpu_masters,
534 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
535}; 99};
536 100
537/* 101/* IVA2 (IVA2) */
538 * IVA2_2 interface data 102static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
539 */ 103 { .name = "logic", .rst_shift = 0 },
540 104 { .name = "seq0", .rst_shift = 1 },
541/* IVA2 <- L3 interface */ 105 { .name = "seq1", .rst_shift = 2 },
542static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
543 .master = &omap3xxx_l3_main_hwmod,
544 .slave = &omap3xxx_iva_hwmod,
545 .clk = "iva2_ck",
546 .user = OCP_USER_MPU | OCP_USER_SDMA,
547}; 106};
548 107
549static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
550 &omap3xxx_l3__iva,
551};
552
553/*
554 * IVA2 (IVA2)
555 */
556
557static struct omap_hwmod omap3xxx_iva_hwmod = { 108static struct omap_hwmod omap3xxx_iva_hwmod = {
558 .name = "iva", 109 .name = "iva",
559 .class = &iva_hwmod_class, 110 .class = &iva_hwmod_class,
560 .masters = omap3xxx_iva_masters, 111 .clkdm_name = "iva2_clkdm",
561 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), 112 .rst_lines = omap3xxx_iva_resets,
113 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114 .main_clk = "iva2_ck",
562}; 115};
563 116
564/* timer class */ 117/* timer class */
@@ -597,46 +150,20 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
597 150
598/* secure timers dev attribute */ 151/* secure timers dev attribute */
599static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 152static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
600 .timer_capability = OMAP_TIMER_SECURE, 153 .timer_capability = OMAP_TIMER_SECURE,
601}; 154};
602 155
603/* always-on timers dev attribute */ 156/* always-on timers dev attribute */
604static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 157static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
605 .timer_capability = OMAP_TIMER_ALWON, 158 .timer_capability = OMAP_TIMER_ALWON,
606}; 159};
607 160
608/* pwm timers dev attribute */ 161/* pwm timers dev attribute */
609static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 162static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
610 .timer_capability = OMAP_TIMER_HAS_PWM, 163 .timer_capability = OMAP_TIMER_HAS_PWM,
611}; 164};
612 165
613/* timer1 */ 166/* timer1 */
614static struct omap_hwmod omap3xxx_timer1_hwmod;
615
616static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
617 {
618 .pa_start = 0x48318000,
619 .pa_end = 0x48318000 + SZ_1K - 1,
620 .flags = ADDR_TYPE_RT
621 },
622 { }
623};
624
625/* l4_wkup -> timer1 */
626static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
627 .master = &omap3xxx_l4_wkup_hwmod,
628 .slave = &omap3xxx_timer1_hwmod,
629 .clk = "gpt1_ick",
630 .addr = omap3xxx_timer1_addrs,
631 .user = OCP_USER_MPU | OCP_USER_SDMA,
632};
633
634/* timer1 slave port */
635static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
636 &omap3xxx_l4_wkup__timer1,
637};
638
639/* timer1 hwmod */
640static struct omap_hwmod omap3xxx_timer1_hwmod = { 167static struct omap_hwmod omap3xxx_timer1_hwmod = {
641 .name = "timer1", 168 .name = "timer1",
642 .mpu_irqs = omap2_timer1_mpu_irqs, 169 .mpu_irqs = omap2_timer1_mpu_irqs,
@@ -651,38 +178,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
651 }, 178 },
652 }, 179 },
653 .dev_attr = &capability_alwon_dev_attr, 180 .dev_attr = &capability_alwon_dev_attr,
654 .slaves = omap3xxx_timer1_slaves,
655 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
656 .class = &omap3xxx_timer_1ms_hwmod_class, 181 .class = &omap3xxx_timer_1ms_hwmod_class,
657}; 182};
658 183
659/* timer2 */ 184/* timer2 */
660static struct omap_hwmod omap3xxx_timer2_hwmod;
661
662static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
663 {
664 .pa_start = 0x49032000,
665 .pa_end = 0x49032000 + SZ_1K - 1,
666 .flags = ADDR_TYPE_RT
667 },
668 { }
669};
670
671/* l4_per -> timer2 */
672static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
673 .master = &omap3xxx_l4_per_hwmod,
674 .slave = &omap3xxx_timer2_hwmod,
675 .clk = "gpt2_ick",
676 .addr = omap3xxx_timer2_addrs,
677 .user = OCP_USER_MPU | OCP_USER_SDMA,
678};
679
680/* timer2 slave port */
681static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
682 &omap3xxx_l4_per__timer2,
683};
684
685/* timer2 hwmod */
686static struct omap_hwmod omap3xxx_timer2_hwmod = { 185static struct omap_hwmod omap3xxx_timer2_hwmod = {
687 .name = "timer2", 186 .name = "timer2",
688 .mpu_irqs = omap2_timer2_mpu_irqs, 187 .mpu_irqs = omap2_timer2_mpu_irqs,
@@ -697,38 +196,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
697 }, 196 },
698 }, 197 },
699 .dev_attr = &capability_alwon_dev_attr, 198 .dev_attr = &capability_alwon_dev_attr,
700 .slaves = omap3xxx_timer2_slaves,
701 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
702 .class = &omap3xxx_timer_1ms_hwmod_class, 199 .class = &omap3xxx_timer_1ms_hwmod_class,
703}; 200};
704 201
705/* timer3 */ 202/* timer3 */
706static struct omap_hwmod omap3xxx_timer3_hwmod;
707
708static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
709 {
710 .pa_start = 0x49034000,
711 .pa_end = 0x49034000 + SZ_1K - 1,
712 .flags = ADDR_TYPE_RT
713 },
714 { }
715};
716
717/* l4_per -> timer3 */
718static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
719 .master = &omap3xxx_l4_per_hwmod,
720 .slave = &omap3xxx_timer3_hwmod,
721 .clk = "gpt3_ick",
722 .addr = omap3xxx_timer3_addrs,
723 .user = OCP_USER_MPU | OCP_USER_SDMA,
724};
725
726/* timer3 slave port */
727static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
728 &omap3xxx_l4_per__timer3,
729};
730
731/* timer3 hwmod */
732static struct omap_hwmod omap3xxx_timer3_hwmod = { 203static struct omap_hwmod omap3xxx_timer3_hwmod = {
733 .name = "timer3", 204 .name = "timer3",
734 .mpu_irqs = omap2_timer3_mpu_irqs, 205 .mpu_irqs = omap2_timer3_mpu_irqs,
@@ -743,38 +214,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
743 }, 214 },
744 }, 215 },
745 .dev_attr = &capability_alwon_dev_attr, 216 .dev_attr = &capability_alwon_dev_attr,
746 .slaves = omap3xxx_timer3_slaves,
747 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
748 .class = &omap3xxx_timer_hwmod_class, 217 .class = &omap3xxx_timer_hwmod_class,
749}; 218};
750 219
751/* timer4 */ 220/* timer4 */
752static struct omap_hwmod omap3xxx_timer4_hwmod;
753
754static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
755 {
756 .pa_start = 0x49036000,
757 .pa_end = 0x49036000 + SZ_1K - 1,
758 .flags = ADDR_TYPE_RT
759 },
760 { }
761};
762
763/* l4_per -> timer4 */
764static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
765 .master = &omap3xxx_l4_per_hwmod,
766 .slave = &omap3xxx_timer4_hwmod,
767 .clk = "gpt4_ick",
768 .addr = omap3xxx_timer4_addrs,
769 .user = OCP_USER_MPU | OCP_USER_SDMA,
770};
771
772/* timer4 slave port */
773static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
774 &omap3xxx_l4_per__timer4,
775};
776
777/* timer4 hwmod */
778static struct omap_hwmod omap3xxx_timer4_hwmod = { 221static struct omap_hwmod omap3xxx_timer4_hwmod = {
779 .name = "timer4", 222 .name = "timer4",
780 .mpu_irqs = omap2_timer4_mpu_irqs, 223 .mpu_irqs = omap2_timer4_mpu_irqs,
@@ -789,38 +232,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
789 }, 232 },
790 }, 233 },
791 .dev_attr = &capability_alwon_dev_attr, 234 .dev_attr = &capability_alwon_dev_attr,
792 .slaves = omap3xxx_timer4_slaves,
793 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
794 .class = &omap3xxx_timer_hwmod_class, 235 .class = &omap3xxx_timer_hwmod_class,
795}; 236};
796 237
797/* timer5 */ 238/* timer5 */
798static struct omap_hwmod omap3xxx_timer5_hwmod;
799
800static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
801 {
802 .pa_start = 0x49038000,
803 .pa_end = 0x49038000 + SZ_1K - 1,
804 .flags = ADDR_TYPE_RT
805 },
806 { }
807};
808
809/* l4_per -> timer5 */
810static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
811 .master = &omap3xxx_l4_per_hwmod,
812 .slave = &omap3xxx_timer5_hwmod,
813 .clk = "gpt5_ick",
814 .addr = omap3xxx_timer5_addrs,
815 .user = OCP_USER_MPU | OCP_USER_SDMA,
816};
817
818/* timer5 slave port */
819static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
820 &omap3xxx_l4_per__timer5,
821};
822
823/* timer5 hwmod */
824static struct omap_hwmod omap3xxx_timer5_hwmod = { 239static struct omap_hwmod omap3xxx_timer5_hwmod = {
825 .name = "timer5", 240 .name = "timer5",
826 .mpu_irqs = omap2_timer5_mpu_irqs, 241 .mpu_irqs = omap2_timer5_mpu_irqs,
@@ -835,38 +250,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
835 }, 250 },
836 }, 251 },
837 .dev_attr = &capability_alwon_dev_attr, 252 .dev_attr = &capability_alwon_dev_attr,
838 .slaves = omap3xxx_timer5_slaves,
839 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
840 .class = &omap3xxx_timer_hwmod_class, 253 .class = &omap3xxx_timer_hwmod_class,
841}; 254};
842 255
843/* timer6 */ 256/* timer6 */
844static struct omap_hwmod omap3xxx_timer6_hwmod;
845
846static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
847 {
848 .pa_start = 0x4903A000,
849 .pa_end = 0x4903A000 + SZ_1K - 1,
850 .flags = ADDR_TYPE_RT
851 },
852 { }
853};
854
855/* l4_per -> timer6 */
856static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
857 .master = &omap3xxx_l4_per_hwmod,
858 .slave = &omap3xxx_timer6_hwmod,
859 .clk = "gpt6_ick",
860 .addr = omap3xxx_timer6_addrs,
861 .user = OCP_USER_MPU | OCP_USER_SDMA,
862};
863
864/* timer6 slave port */
865static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
866 &omap3xxx_l4_per__timer6,
867};
868
869/* timer6 hwmod */
870static struct omap_hwmod omap3xxx_timer6_hwmod = { 257static struct omap_hwmod omap3xxx_timer6_hwmod = {
871 .name = "timer6", 258 .name = "timer6",
872 .mpu_irqs = omap2_timer6_mpu_irqs, 259 .mpu_irqs = omap2_timer6_mpu_irqs,
@@ -881,38 +268,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
881 }, 268 },
882 }, 269 },
883 .dev_attr = &capability_alwon_dev_attr, 270 .dev_attr = &capability_alwon_dev_attr,
884 .slaves = omap3xxx_timer6_slaves,
885 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
886 .class = &omap3xxx_timer_hwmod_class, 271 .class = &omap3xxx_timer_hwmod_class,
887}; 272};
888 273
889/* timer7 */ 274/* timer7 */
890static struct omap_hwmod omap3xxx_timer7_hwmod;
891
892static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
893 {
894 .pa_start = 0x4903C000,
895 .pa_end = 0x4903C000 + SZ_1K - 1,
896 .flags = ADDR_TYPE_RT
897 },
898 { }
899};
900
901/* l4_per -> timer7 */
902static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
903 .master = &omap3xxx_l4_per_hwmod,
904 .slave = &omap3xxx_timer7_hwmod,
905 .clk = "gpt7_ick",
906 .addr = omap3xxx_timer7_addrs,
907 .user = OCP_USER_MPU | OCP_USER_SDMA,
908};
909
910/* timer7 slave port */
911static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
912 &omap3xxx_l4_per__timer7,
913};
914
915/* timer7 hwmod */
916static struct omap_hwmod omap3xxx_timer7_hwmod = { 275static struct omap_hwmod omap3xxx_timer7_hwmod = {
917 .name = "timer7", 276 .name = "timer7",
918 .mpu_irqs = omap2_timer7_mpu_irqs, 277 .mpu_irqs = omap2_timer7_mpu_irqs,
@@ -927,38 +286,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
927 }, 286 },
928 }, 287 },
929 .dev_attr = &capability_alwon_dev_attr, 288 .dev_attr = &capability_alwon_dev_attr,
930 .slaves = omap3xxx_timer7_slaves,
931 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
932 .class = &omap3xxx_timer_hwmod_class, 289 .class = &omap3xxx_timer_hwmod_class,
933}; 290};
934 291
935/* timer8 */ 292/* timer8 */
936static struct omap_hwmod omap3xxx_timer8_hwmod;
937
938static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
939 {
940 .pa_start = 0x4903E000,
941 .pa_end = 0x4903E000 + SZ_1K - 1,
942 .flags = ADDR_TYPE_RT
943 },
944 { }
945};
946
947/* l4_per -> timer8 */
948static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
949 .master = &omap3xxx_l4_per_hwmod,
950 .slave = &omap3xxx_timer8_hwmod,
951 .clk = "gpt8_ick",
952 .addr = omap3xxx_timer8_addrs,
953 .user = OCP_USER_MPU | OCP_USER_SDMA,
954};
955
956/* timer8 slave port */
957static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
958 &omap3xxx_l4_per__timer8,
959};
960
961/* timer8 hwmod */
962static struct omap_hwmod omap3xxx_timer8_hwmod = { 293static struct omap_hwmod omap3xxx_timer8_hwmod = {
963 .name = "timer8", 294 .name = "timer8",
964 .mpu_irqs = omap2_timer8_mpu_irqs, 295 .mpu_irqs = omap2_timer8_mpu_irqs,
@@ -973,38 +304,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
973 }, 304 },
974 }, 305 },
975 .dev_attr = &capability_pwm_dev_attr, 306 .dev_attr = &capability_pwm_dev_attr,
976 .slaves = omap3xxx_timer8_slaves,
977 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
978 .class = &omap3xxx_timer_hwmod_class, 307 .class = &omap3xxx_timer_hwmod_class,
979}; 308};
980 309
981/* timer9 */ 310/* timer9 */
982static struct omap_hwmod omap3xxx_timer9_hwmod;
983
984static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
985 {
986 .pa_start = 0x49040000,
987 .pa_end = 0x49040000 + SZ_1K - 1,
988 .flags = ADDR_TYPE_RT
989 },
990 { }
991};
992
993/* l4_per -> timer9 */
994static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
995 .master = &omap3xxx_l4_per_hwmod,
996 .slave = &omap3xxx_timer9_hwmod,
997 .clk = "gpt9_ick",
998 .addr = omap3xxx_timer9_addrs,
999 .user = OCP_USER_MPU | OCP_USER_SDMA,
1000};
1001
1002/* timer9 slave port */
1003static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1004 &omap3xxx_l4_per__timer9,
1005};
1006
1007/* timer9 hwmod */
1008static struct omap_hwmod omap3xxx_timer9_hwmod = { 311static struct omap_hwmod omap3xxx_timer9_hwmod = {
1009 .name = "timer9", 312 .name = "timer9",
1010 .mpu_irqs = omap2_timer9_mpu_irqs, 313 .mpu_irqs = omap2_timer9_mpu_irqs,
@@ -1019,29 +322,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
1019 }, 322 },
1020 }, 323 },
1021 .dev_attr = &capability_pwm_dev_attr, 324 .dev_attr = &capability_pwm_dev_attr,
1022 .slaves = omap3xxx_timer9_slaves,
1023 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1024 .class = &omap3xxx_timer_hwmod_class, 325 .class = &omap3xxx_timer_hwmod_class,
1025}; 326};
1026 327
1027/* timer10 */ 328/* timer10 */
1028static struct omap_hwmod omap3xxx_timer10_hwmod;
1029
1030/* l4_core -> timer10 */
1031static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1032 .master = &omap3xxx_l4_core_hwmod,
1033 .slave = &omap3xxx_timer10_hwmod,
1034 .clk = "gpt10_ick",
1035 .addr = omap2_timer10_addrs,
1036 .user = OCP_USER_MPU | OCP_USER_SDMA,
1037};
1038
1039/* timer10 slave port */
1040static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1041 &omap3xxx_l4_core__timer10,
1042};
1043
1044/* timer10 hwmod */
1045static struct omap_hwmod omap3xxx_timer10_hwmod = { 329static struct omap_hwmod omap3xxx_timer10_hwmod = {
1046 .name = "timer10", 330 .name = "timer10",
1047 .mpu_irqs = omap2_timer10_mpu_irqs, 331 .mpu_irqs = omap2_timer10_mpu_irqs,
@@ -1056,29 +340,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
1056 }, 340 },
1057 }, 341 },
1058 .dev_attr = &capability_pwm_dev_attr, 342 .dev_attr = &capability_pwm_dev_attr,
1059 .slaves = omap3xxx_timer10_slaves,
1060 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1061 .class = &omap3xxx_timer_1ms_hwmod_class, 343 .class = &omap3xxx_timer_1ms_hwmod_class,
1062}; 344};
1063 345
1064/* timer11 */ 346/* timer11 */
1065static struct omap_hwmod omap3xxx_timer11_hwmod;
1066
1067/* l4_core -> timer11 */
1068static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1069 .master = &omap3xxx_l4_core_hwmod,
1070 .slave = &omap3xxx_timer11_hwmod,
1071 .clk = "gpt11_ick",
1072 .addr = omap2_timer11_addrs,
1073 .user = OCP_USER_MPU | OCP_USER_SDMA,
1074};
1075
1076/* timer11 slave port */
1077static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1078 &omap3xxx_l4_core__timer11,
1079};
1080
1081/* timer11 hwmod */
1082static struct omap_hwmod omap3xxx_timer11_hwmod = { 347static struct omap_hwmod omap3xxx_timer11_hwmod = {
1083 .name = "timer11", 348 .name = "timer11",
1084 .mpu_irqs = omap2_timer11_mpu_irqs, 349 .mpu_irqs = omap2_timer11_mpu_irqs,
@@ -1093,42 +358,15 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
1093 }, 358 },
1094 }, 359 },
1095 .dev_attr = &capability_pwm_dev_attr, 360 .dev_attr = &capability_pwm_dev_attr,
1096 .slaves = omap3xxx_timer11_slaves,
1097 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1098 .class = &omap3xxx_timer_hwmod_class, 361 .class = &omap3xxx_timer_hwmod_class,
1099}; 362};
1100 363
1101/* timer12*/ 364/* timer12 */
1102static struct omap_hwmod omap3xxx_timer12_hwmod;
1103static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 365static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1104 { .irq = 95, }, 366 { .irq = 95, },
1105 { .irq = -1 } 367 { .irq = -1 }
1106}; 368};
1107 369
1108static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1109 {
1110 .pa_start = 0x48304000,
1111 .pa_end = 0x48304000 + SZ_1K - 1,
1112 .flags = ADDR_TYPE_RT
1113 },
1114 { }
1115};
1116
1117/* l4_core -> timer12 */
1118static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1119 .master = &omap3xxx_l4_core_hwmod,
1120 .slave = &omap3xxx_timer12_hwmod,
1121 .clk = "gpt12_ick",
1122 .addr = omap3xxx_timer12_addrs,
1123 .user = OCP_USER_MPU | OCP_USER_SDMA,
1124};
1125
1126/* timer12 slave port */
1127static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1128 &omap3xxx_l4_core__timer12,
1129};
1130
1131/* timer12 hwmod */
1132static struct omap_hwmod omap3xxx_timer12_hwmod = { 370static struct omap_hwmod omap3xxx_timer12_hwmod = {
1133 .name = "timer12", 371 .name = "timer12",
1134 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 372 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
@@ -1143,29 +381,9 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
1143 }, 381 },
1144 }, 382 },
1145 .dev_attr = &capability_secure_dev_attr, 383 .dev_attr = &capability_secure_dev_attr,
1146 .slaves = omap3xxx_timer12_slaves,
1147 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1148 .class = &omap3xxx_timer_hwmod_class, 384 .class = &omap3xxx_timer_hwmod_class,
1149}; 385};
1150 386
1151/* l4_wkup -> wd_timer2 */
1152static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1153 {
1154 .pa_start = 0x48314000,
1155 .pa_end = 0x4831407f,
1156 .flags = ADDR_TYPE_RT
1157 },
1158 { }
1159};
1160
1161static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1162 .master = &omap3xxx_l4_wkup_hwmod,
1163 .slave = &omap3xxx_wd_timer2_hwmod,
1164 .clk = "wdt2_ick",
1165 .addr = omap3xxx_wd_timer2_addrs,
1166 .user = OCP_USER_MPU | OCP_USER_SDMA,
1167};
1168
1169/* 387/*
1170 * 'wd_timer' class 388 * 'wd_timer' class
1171 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 389 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
@@ -1200,12 +418,8 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
1200static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 418static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1201 .name = "wd_timer", 419 .name = "wd_timer",
1202 .sysc = &omap3xxx_wd_timer_sysc, 420 .sysc = &omap3xxx_wd_timer_sysc,
1203 .pre_shutdown = &omap2_wd_timer_disable 421 .pre_shutdown = &omap2_wd_timer_disable,
1204}; 422 .reset = &omap2_wd_timer_reset,
1205
1206/* wd_timer2 */
1207static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1208 &omap3xxx_l4_wkup__wd_timer2,
1209}; 423};
1210 424
1211static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 425static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
@@ -1221,8 +435,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1221 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 435 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1222 }, 436 },
1223 }, 437 },
1224 .slaves = omap3xxx_wd_timer2_slaves,
1225 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1226 /* 438 /*
1227 * XXX: Use software supervised mode, HW supervised smartidle seems to 439 * XXX: Use software supervised mode, HW supervised smartidle seems to
1228 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 440 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@@ -1231,11 +443,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1231}; 443};
1232 444
1233/* UART1 */ 445/* UART1 */
1234
1235static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1236 &omap3_l4_core__uart1,
1237};
1238
1239static struct omap_hwmod omap3xxx_uart1_hwmod = { 446static struct omap_hwmod omap3xxx_uart1_hwmod = {
1240 .name = "uart1", 447 .name = "uart1",
1241 .mpu_irqs = omap2_uart1_mpu_irqs, 448 .mpu_irqs = omap2_uart1_mpu_irqs,
@@ -1250,17 +457,10 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
1250 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 457 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1251 }, 458 },
1252 }, 459 },
1253 .slaves = omap3xxx_uart1_slaves,
1254 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1255 .class = &omap2_uart_class, 460 .class = &omap2_uart_class,
1256}; 461};
1257 462
1258/* UART2 */ 463/* UART2 */
1259
1260static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1261 &omap3_l4_core__uart2,
1262};
1263
1264static struct omap_hwmod omap3xxx_uart2_hwmod = { 464static struct omap_hwmod omap3xxx_uart2_hwmod = {
1265 .name = "uart2", 465 .name = "uart2",
1266 .mpu_irqs = omap2_uart2_mpu_irqs, 466 .mpu_irqs = omap2_uart2_mpu_irqs,
@@ -1275,17 +475,10 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
1275 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 475 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1276 }, 476 },
1277 }, 477 },
1278 .slaves = omap3xxx_uart2_slaves,
1279 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1280 .class = &omap2_uart_class, 478 .class = &omap2_uart_class,
1281}; 479};
1282 480
1283/* UART3 */ 481/* UART3 */
1284
1285static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1286 &omap3_l4_per__uart3,
1287};
1288
1289static struct omap_hwmod omap3xxx_uart3_hwmod = { 482static struct omap_hwmod omap3xxx_uart3_hwmod = {
1290 .name = "uart3", 483 .name = "uart3",
1291 .mpu_irqs = omap2_uart3_mpu_irqs, 484 .mpu_irqs = omap2_uart3_mpu_irqs,
@@ -1300,13 +493,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1300 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 493 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1301 }, 494 },
1302 }, 495 },
1303 .slaves = omap3xxx_uart3_slaves,
1304 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1305 .class = &omap2_uart_class, 496 .class = &omap2_uart_class,
1306}; 497};
1307 498
1308/* UART4 */ 499/* UART4 */
1309
1310static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 500static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1311 { .irq = INT_36XX_UART4_IRQ, }, 501 { .irq = INT_36XX_UART4_IRQ, },
1312 { .irq = -1 } 502 { .irq = -1 }
@@ -1318,11 +508,7 @@ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1318 { .dma_req = -1 } 508 { .dma_req = -1 }
1319}; 509};
1320 510
1321static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { 511static struct omap_hwmod omap36xx_uart4_hwmod = {
1322 &omap3_l4_per__uart4,
1323};
1324
1325static struct omap_hwmod omap3xxx_uart4_hwmod = {
1326 .name = "uart4", 512 .name = "uart4",
1327 .mpu_irqs = uart4_mpu_irqs, 513 .mpu_irqs = uart4_mpu_irqs,
1328 .sdma_reqs = uart4_sdma_reqs, 514 .sdma_reqs = uart4_sdma_reqs,
@@ -1336,8 +522,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
1336 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 522 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1337 }, 523 },
1338 }, 524 },
1339 .slaves = omap3xxx_uart4_slaves,
1340 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1341 .class = &omap2_uart_class, 525 .class = &omap2_uart_class,
1342}; 526};
1343 527
@@ -1350,16 +534,12 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
1350 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, 534 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
1351}; 535};
1352 536
1353static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
1354 &am35xx_l4_core__uart4,
1355};
1356
1357static struct omap_hwmod am35xx_uart4_hwmod = { 537static struct omap_hwmod am35xx_uart4_hwmod = {
1358 .name = "uart4", 538 .name = "uart4",
1359 .mpu_irqs = am35xx_uart4_mpu_irqs, 539 .mpu_irqs = am35xx_uart4_mpu_irqs,
1360 .sdma_reqs = am35xx_uart4_sdma_reqs, 540 .sdma_reqs = am35xx_uart4_sdma_reqs,
1361 .main_clk = "uart4_fck", 541 .main_clk = "uart4_fck",
1362 .prcm = { 542 .prcm = {
1363 .omap2 = { 543 .omap2 = {
1364 .module_offs = CORE_MOD, 544 .module_offs = CORE_MOD,
1365 .prcm_reg_id = 1, 545 .prcm_reg_id = 1,
@@ -1368,12 +548,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
1368 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, 548 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
1369 }, 549 },
1370 }, 550 },
1371 .slaves = am35xx_uart4_slaves, 551 .class = &omap2_uart_class,
1372 .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves),
1373 .class = &omap2_uart_class,
1374}; 552};
1375 553
1376
1377static struct omap_hwmod_class i2c_class = { 554static struct omap_hwmod_class i2c_class = {
1378 .name = "i2c", 555 .name = "i2c",
1379 .sysc = &i2c_sysc, 556 .sysc = &i2c_sysc,
@@ -1388,51 +565,6 @@ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1388}; 565};
1389 566
1390/* dss */ 567/* dss */
1391/* dss master ports */
1392static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1393 &omap3xxx_dss__l3,
1394};
1395
1396/* l4_core -> dss */
1397static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1398 .master = &omap3xxx_l4_core_hwmod,
1399 .slave = &omap3430es1_dss_core_hwmod,
1400 .clk = "dss_ick",
1401 .addr = omap2_dss_addrs,
1402 .fw = {
1403 .omap2 = {
1404 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1405 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1406 .flags = OMAP_FIREWALL_L4,
1407 }
1408 },
1409 .user = OCP_USER_MPU | OCP_USER_SDMA,
1410};
1411
1412static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1413 .master = &omap3xxx_l4_core_hwmod,
1414 .slave = &omap3xxx_dss_core_hwmod,
1415 .clk = "dss_ick",
1416 .addr = omap2_dss_addrs,
1417 .fw = {
1418 .omap2 = {
1419 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1420 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1421 .flags = OMAP_FIREWALL_L4,
1422 }
1423 },
1424 .user = OCP_USER_MPU | OCP_USER_SDMA,
1425};
1426
1427/* dss slave ports */
1428static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1429 &omap3430es1_l4_core__dss,
1430};
1431
1432static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1433 &omap3xxx_l4_core__dss,
1434};
1435
1436static struct omap_hwmod_opt_clk dss_opt_clks[] = { 568static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1437 /* 569 /*
1438 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 570 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
@@ -1460,10 +592,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1460 }, 592 },
1461 .opt_clks = dss_opt_clks, 593 .opt_clks = dss_opt_clks,
1462 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 594 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1463 .slaves = omap3430es1_dss_slaves,
1464 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1465 .masters = omap3xxx_dss_masters,
1466 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1467 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 595 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1468}; 596};
1469 597
@@ -1485,10 +613,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1485 }, 613 },
1486 .opt_clks = dss_opt_clks, 614 .opt_clks = dss_opt_clks,
1487 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 615 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1488 .slaves = omap3xxx_dss_slaves,
1489 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1490 .masters = omap3xxx_dss_masters,
1491 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1492}; 616};
1493 617
1494/* 618/*
@@ -1513,27 +637,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1513 .sysc = &omap3_dispc_sysc, 637 .sysc = &omap3_dispc_sysc,
1514}; 638};
1515 639
1516/* l4_core -> dss_dispc */
1517static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1518 .master = &omap3xxx_l4_core_hwmod,
1519 .slave = &omap3xxx_dss_dispc_hwmod,
1520 .clk = "dss_ick",
1521 .addr = omap2_dss_dispc_addrs,
1522 .fw = {
1523 .omap2 = {
1524 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1525 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1526 .flags = OMAP_FIREWALL_L4,
1527 }
1528 },
1529 .user = OCP_USER_MPU | OCP_USER_SDMA,
1530};
1531
1532/* dss_dispc slave ports */
1533static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1534 &omap3xxx_l4_core__dss_dispc,
1535};
1536
1537static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 640static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1538 .name = "dss_dispc", 641 .name = "dss_dispc",
1539 .class = &omap3_dispc_hwmod_class, 642 .class = &omap3_dispc_hwmod_class,
@@ -1546,8 +649,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1546 .module_offs = OMAP3430_DSS_MOD, 649 .module_offs = OMAP3430_DSS_MOD,
1547 }, 650 },
1548 }, 651 },
1549 .slaves = omap3xxx_dss_dispc_slaves,
1550 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1551 .flags = HWMOD_NO_IDLEST, 652 .flags = HWMOD_NO_IDLEST,
1552 .dev_attr = &omap2_3_dss_dispc_dev_attr 653 .dev_attr = &omap2_3_dss_dispc_dev_attr
1553}; 654};
@@ -1567,36 +668,6 @@ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1567}; 668};
1568 669
1569/* dss_dsi1 */ 670/* dss_dsi1 */
1570static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1571 {
1572 .pa_start = 0x4804FC00,
1573 .pa_end = 0x4804FFFF,
1574 .flags = ADDR_TYPE_RT
1575 },
1576 { }
1577};
1578
1579/* l4_core -> dss_dsi1 */
1580static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1581 .master = &omap3xxx_l4_core_hwmod,
1582 .slave = &omap3xxx_dss_dsi1_hwmod,
1583 .clk = "dss_ick",
1584 .addr = omap3xxx_dss_dsi1_addrs,
1585 .fw = {
1586 .omap2 = {
1587 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1588 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1589 .flags = OMAP_FIREWALL_L4,
1590 }
1591 },
1592 .user = OCP_USER_MPU | OCP_USER_SDMA,
1593};
1594
1595/* dss_dsi1 slave ports */
1596static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1597 &omap3xxx_l4_core__dss_dsi1,
1598};
1599
1600static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 671static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1601 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 672 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1602}; 673};
@@ -1615,32 +686,9 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1615 }, 686 },
1616 .opt_clks = dss_dsi1_opt_clks, 687 .opt_clks = dss_dsi1_opt_clks,
1617 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 688 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1618 .slaves = omap3xxx_dss_dsi1_slaves,
1619 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1620 .flags = HWMOD_NO_IDLEST, 689 .flags = HWMOD_NO_IDLEST,
1621}; 690};
1622 691
1623/* l4_core -> dss_rfbi */
1624static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1625 .master = &omap3xxx_l4_core_hwmod,
1626 .slave = &omap3xxx_dss_rfbi_hwmod,
1627 .clk = "dss_ick",
1628 .addr = omap2_dss_rfbi_addrs,
1629 .fw = {
1630 .omap2 = {
1631 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1632 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1633 .flags = OMAP_FIREWALL_L4,
1634 }
1635 },
1636 .user = OCP_USER_MPU | OCP_USER_SDMA,
1637};
1638
1639/* dss_rfbi slave ports */
1640static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1641 &omap3xxx_l4_core__dss_rfbi,
1642};
1643
1644static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 692static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1645 { .role = "ick", .clk = "dss_ick" }, 693 { .role = "ick", .clk = "dss_ick" },
1646}; 694};
@@ -1658,32 +706,9 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1658 }, 706 },
1659 .opt_clks = dss_rfbi_opt_clks, 707 .opt_clks = dss_rfbi_opt_clks,
1660 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 708 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1661 .slaves = omap3xxx_dss_rfbi_slaves,
1662 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1663 .flags = HWMOD_NO_IDLEST, 709 .flags = HWMOD_NO_IDLEST,
1664}; 710};
1665 711
1666/* l4_core -> dss_venc */
1667static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1668 .master = &omap3xxx_l4_core_hwmod,
1669 .slave = &omap3xxx_dss_venc_hwmod,
1670 .clk = "dss_ick",
1671 .addr = omap2_dss_venc_addrs,
1672 .fw = {
1673 .omap2 = {
1674 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1675 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1676 .flags = OMAP_FIREWALL_L4,
1677 }
1678 },
1679 .user = OCP_USER_MPU | OCP_USER_SDMA,
1680};
1681
1682/* dss_venc slave ports */
1683static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1684 &omap3xxx_l4_core__dss_venc,
1685};
1686
1687static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 712static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1688 /* required only on OMAP3430 */ 713 /* required only on OMAP3430 */
1689 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 714 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
@@ -1702,13 +727,10 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1702 }, 727 },
1703 .opt_clks = dss_venc_opt_clks, 728 .opt_clks = dss_venc_opt_clks,
1704 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 729 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1705 .slaves = omap3xxx_dss_venc_slaves,
1706 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1707 .flags = HWMOD_NO_IDLEST, 730 .flags = HWMOD_NO_IDLEST,
1708}; 731};
1709 732
1710/* I2C1 */ 733/* I2C1 */
1711
1712static struct omap_i2c_dev_attr i2c1_dev_attr = { 734static struct omap_i2c_dev_attr i2c1_dev_attr = {
1713 .fifo_depth = 8, /* bytes */ 735 .fifo_depth = 8, /* bytes */
1714 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 736 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1716,10 +738,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
1716 OMAP_I2C_FLAG_BUS_SHIFT_2, 738 OMAP_I2C_FLAG_BUS_SHIFT_2,
1717}; 739};
1718 740
1719static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1720 &omap3_l4_core__i2c1,
1721};
1722
1723static struct omap_hwmod omap3xxx_i2c1_hwmod = { 741static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1724 .name = "i2c1", 742 .name = "i2c1",
1725 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 743 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1735,14 +753,11 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1735 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 753 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1736 }, 754 },
1737 }, 755 },
1738 .slaves = omap3xxx_i2c1_slaves,
1739 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1740 .class = &i2c_class, 756 .class = &i2c_class,
1741 .dev_attr = &i2c1_dev_attr, 757 .dev_attr = &i2c1_dev_attr,
1742}; 758};
1743 759
1744/* I2C2 */ 760/* I2C2 */
1745
1746static struct omap_i2c_dev_attr i2c2_dev_attr = { 761static struct omap_i2c_dev_attr i2c2_dev_attr = {
1747 .fifo_depth = 8, /* bytes */ 762 .fifo_depth = 8, /* bytes */
1748 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 763 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1750,10 +765,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
1750 OMAP_I2C_FLAG_BUS_SHIFT_2, 765 OMAP_I2C_FLAG_BUS_SHIFT_2,
1751}; 766};
1752 767
1753static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1754 &omap3_l4_core__i2c2,
1755};
1756
1757static struct omap_hwmod omap3xxx_i2c2_hwmod = { 768static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1758 .name = "i2c2", 769 .name = "i2c2",
1759 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 770 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1769,14 +780,11 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1769 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 780 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1770 }, 781 },
1771 }, 782 },
1772 .slaves = omap3xxx_i2c2_slaves,
1773 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1774 .class = &i2c_class, 783 .class = &i2c_class,
1775 .dev_attr = &i2c2_dev_attr, 784 .dev_attr = &i2c2_dev_attr,
1776}; 785};
1777 786
1778/* I2C3 */ 787/* I2C3 */
1779
1780static struct omap_i2c_dev_attr i2c3_dev_attr = { 788static struct omap_i2c_dev_attr i2c3_dev_attr = {
1781 .fifo_depth = 64, /* bytes */ 789 .fifo_depth = 64, /* bytes */
1782 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 790 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1795,10 +803,6 @@ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1795 { .dma_req = -1 } 803 { .dma_req = -1 }
1796}; 804};
1797 805
1798static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1799 &omap3_l4_core__i2c3,
1800};
1801
1802static struct omap_hwmod omap3xxx_i2c3_hwmod = { 806static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1803 .name = "i2c3", 807 .name = "i2c3",
1804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 808 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1814,114 +818,10 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1814 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 818 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1815 }, 819 },
1816 }, 820 },
1817 .slaves = omap3xxx_i2c3_slaves,
1818 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1819 .class = &i2c_class, 821 .class = &i2c_class,
1820 .dev_attr = &i2c3_dev_attr, 822 .dev_attr = &i2c3_dev_attr,
1821}; 823};
1822 824
1823/* l4_wkup -> gpio1 */
1824static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1825 {
1826 .pa_start = 0x48310000,
1827 .pa_end = 0x483101ff,
1828 .flags = ADDR_TYPE_RT
1829 },
1830 { }
1831};
1832
1833static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1834 .master = &omap3xxx_l4_wkup_hwmod,
1835 .slave = &omap3xxx_gpio1_hwmod,
1836 .addr = omap3xxx_gpio1_addrs,
1837 .user = OCP_USER_MPU | OCP_USER_SDMA,
1838};
1839
1840/* l4_per -> gpio2 */
1841static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1842 {
1843 .pa_start = 0x49050000,
1844 .pa_end = 0x490501ff,
1845 .flags = ADDR_TYPE_RT
1846 },
1847 { }
1848};
1849
1850static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1851 .master = &omap3xxx_l4_per_hwmod,
1852 .slave = &omap3xxx_gpio2_hwmod,
1853 .addr = omap3xxx_gpio2_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855};
1856
1857/* l4_per -> gpio3 */
1858static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1859 {
1860 .pa_start = 0x49052000,
1861 .pa_end = 0x490521ff,
1862 .flags = ADDR_TYPE_RT
1863 },
1864 { }
1865};
1866
1867static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1868 .master = &omap3xxx_l4_per_hwmod,
1869 .slave = &omap3xxx_gpio3_hwmod,
1870 .addr = omap3xxx_gpio3_addrs,
1871 .user = OCP_USER_MPU | OCP_USER_SDMA,
1872};
1873
1874/* l4_per -> gpio4 */
1875static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1876 {
1877 .pa_start = 0x49054000,
1878 .pa_end = 0x490541ff,
1879 .flags = ADDR_TYPE_RT
1880 },
1881 { }
1882};
1883
1884static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1885 .master = &omap3xxx_l4_per_hwmod,
1886 .slave = &omap3xxx_gpio4_hwmod,
1887 .addr = omap3xxx_gpio4_addrs,
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889};
1890
1891/* l4_per -> gpio5 */
1892static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1893 {
1894 .pa_start = 0x49056000,
1895 .pa_end = 0x490561ff,
1896 .flags = ADDR_TYPE_RT
1897 },
1898 { }
1899};
1900
1901static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1902 .master = &omap3xxx_l4_per_hwmod,
1903 .slave = &omap3xxx_gpio5_hwmod,
1904 .addr = omap3xxx_gpio5_addrs,
1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906};
1907
1908/* l4_per -> gpio6 */
1909static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1910 {
1911 .pa_start = 0x49058000,
1912 .pa_end = 0x490581ff,
1913 .flags = ADDR_TYPE_RT
1914 },
1915 { }
1916};
1917
1918static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1919 .master = &omap3xxx_l4_per_hwmod,
1920 .slave = &omap3xxx_gpio6_hwmod,
1921 .addr = omap3xxx_gpio6_addrs,
1922 .user = OCP_USER_MPU | OCP_USER_SDMA,
1923};
1924
1925/* 825/*
1926 * 'gpio' class 826 * 'gpio' class
1927 * general purpose io module 827 * general purpose io module
@@ -1944,7 +844,7 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1944 .rev = 1, 844 .rev = 1,
1945}; 845};
1946 846
1947/* gpio_dev_attr*/ 847/* gpio_dev_attr */
1948static struct omap_gpio_dev_attr gpio_dev_attr = { 848static struct omap_gpio_dev_attr gpio_dev_attr = {
1949 .bank_width = 32, 849 .bank_width = 32,
1950 .dbck_flag = true, 850 .dbck_flag = true,
@@ -1955,10 +855,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1955 { .role = "dbclk", .clk = "gpio1_dbck", }, 855 { .role = "dbclk", .clk = "gpio1_dbck", },
1956}; 856};
1957 857
1958static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1959 &omap3xxx_l4_wkup__gpio1,
1960};
1961
1962static struct omap_hwmod omap3xxx_gpio1_hwmod = { 858static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1963 .name = "gpio1", 859 .name = "gpio1",
1964 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 860 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1975,8 +871,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1975 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 871 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1976 }, 872 },
1977 }, 873 },
1978 .slaves = omap3xxx_gpio1_slaves,
1979 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1980 .class = &omap3xxx_gpio_hwmod_class, 874 .class = &omap3xxx_gpio_hwmod_class,
1981 .dev_attr = &gpio_dev_attr, 875 .dev_attr = &gpio_dev_attr,
1982}; 876};
@@ -1986,10 +880,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1986 { .role = "dbclk", .clk = "gpio2_dbck", }, 880 { .role = "dbclk", .clk = "gpio2_dbck", },
1987}; 881};
1988 882
1989static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1990 &omap3xxx_l4_per__gpio2,
1991};
1992
1993static struct omap_hwmod omap3xxx_gpio2_hwmod = { 883static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1994 .name = "gpio2", 884 .name = "gpio2",
1995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 885 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2006,8 +896,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2006 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 896 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2007 }, 897 },
2008 }, 898 },
2009 .slaves = omap3xxx_gpio2_slaves,
2010 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2011 .class = &omap3xxx_gpio_hwmod_class, 899 .class = &omap3xxx_gpio_hwmod_class,
2012 .dev_attr = &gpio_dev_attr, 900 .dev_attr = &gpio_dev_attr,
2013}; 901};
@@ -2017,10 +905,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2017 { .role = "dbclk", .clk = "gpio3_dbck", }, 905 { .role = "dbclk", .clk = "gpio3_dbck", },
2018}; 906};
2019 907
2020static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2021 &omap3xxx_l4_per__gpio3,
2022};
2023
2024static struct omap_hwmod omap3xxx_gpio3_hwmod = { 908static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2025 .name = "gpio3", 909 .name = "gpio3",
2026 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 910 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2037,8 +921,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2037 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 921 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2038 }, 922 },
2039 }, 923 },
2040 .slaves = omap3xxx_gpio3_slaves,
2041 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2042 .class = &omap3xxx_gpio_hwmod_class, 924 .class = &omap3xxx_gpio_hwmod_class,
2043 .dev_attr = &gpio_dev_attr, 925 .dev_attr = &gpio_dev_attr,
2044}; 926};
@@ -2048,10 +930,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2048 { .role = "dbclk", .clk = "gpio4_dbck", }, 930 { .role = "dbclk", .clk = "gpio4_dbck", },
2049}; 931};
2050 932
2051static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2052 &omap3xxx_l4_per__gpio4,
2053};
2054
2055static struct omap_hwmod omap3xxx_gpio4_hwmod = { 933static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2056 .name = "gpio4", 934 .name = "gpio4",
2057 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 935 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2068,8 +946,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2068 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 946 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2069 }, 947 },
2070 }, 948 },
2071 .slaves = omap3xxx_gpio4_slaves,
2072 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2073 .class = &omap3xxx_gpio_hwmod_class, 949 .class = &omap3xxx_gpio_hwmod_class,
2074 .dev_attr = &gpio_dev_attr, 950 .dev_attr = &gpio_dev_attr,
2075}; 951};
@@ -2084,10 +960,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2084 { .role = "dbclk", .clk = "gpio5_dbck", }, 960 { .role = "dbclk", .clk = "gpio5_dbck", },
2085}; 961};
2086 962
2087static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2088 &omap3xxx_l4_per__gpio5,
2089};
2090
2091static struct omap_hwmod omap3xxx_gpio5_hwmod = { 963static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2092 .name = "gpio5", 964 .name = "gpio5",
2093 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 965 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2104,8 +976,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2104 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 976 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2105 }, 977 },
2106 }, 978 },
2107 .slaves = omap3xxx_gpio5_slaves,
2108 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2109 .class = &omap3xxx_gpio_hwmod_class, 979 .class = &omap3xxx_gpio_hwmod_class,
2110 .dev_attr = &gpio_dev_attr, 980 .dev_attr = &gpio_dev_attr,
2111}; 981};
@@ -2120,10 +990,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2120 { .role = "dbclk", .clk = "gpio6_dbck", }, 990 { .role = "dbclk", .clk = "gpio6_dbck", },
2121}; 991};
2122 992
2123static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2124 &omap3xxx_l4_per__gpio6,
2125};
2126
2127static struct omap_hwmod omap3xxx_gpio6_hwmod = { 993static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2128 .name = "gpio6", 994 .name = "gpio6",
2129 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2140,20 +1006,10 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2140 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 1006 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2141 }, 1007 },
2142 }, 1008 },
2143 .slaves = omap3xxx_gpio6_slaves,
2144 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2145 .class = &omap3xxx_gpio_hwmod_class, 1009 .class = &omap3xxx_gpio_hwmod_class,
2146 .dev_attr = &gpio_dev_attr, 1010 .dev_attr = &gpio_dev_attr,
2147}; 1011};
2148 1012
2149/* dma_system -> L3 */
2150static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2151 .master = &omap3xxx_dma_system_hwmod,
2152 .slave = &omap3xxx_l3_main_hwmod,
2153 .clk = "core_l3_ick",
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2155};
2156
2157/* dma attributes */ 1013/* dma attributes */
2158static struct omap_dma_dev_attr dma_dev_attr = { 1014static struct omap_dma_dev_attr dma_dev_attr = {
2159 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1015 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -2180,34 +1036,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2180}; 1036};
2181 1037
2182/* dma_system */ 1038/* dma_system */
2183static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2184 {
2185 .pa_start = 0x48056000,
2186 .pa_end = 0x48056fff,
2187 .flags = ADDR_TYPE_RT
2188 },
2189 { }
2190};
2191
2192/* dma_system master ports */
2193static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2194 &omap3xxx_dma_system__l3,
2195};
2196
2197/* l4_cfg -> dma_system */
2198static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2199 .master = &omap3xxx_l4_core_hwmod,
2200 .slave = &omap3xxx_dma_system_hwmod,
2201 .clk = "core_l4_ick",
2202 .addr = omap3xxx_dma_system_addrs,
2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2204};
2205
2206/* dma_system slave ports */
2207static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2208 &omap3xxx_l4_core__dma_system,
2209};
2210
2211static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1039static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2212 .name = "dma", 1040 .name = "dma",
2213 .class = &omap3xxx_dma_hwmod_class, 1041 .class = &omap3xxx_dma_hwmod_class,
@@ -2222,10 +1050,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2222 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 1050 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2223 }, 1051 },
2224 }, 1052 },
2225 .slaves = omap3xxx_dma_system_slaves,
2226 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2227 .masters = omap3xxx_dma_system_masters,
2228 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2229 .dev_attr = &dma_dev_attr, 1053 .dev_attr = &dma_dev_attr,
2230 .flags = HWMOD_NO_IDLEST, 1054 .flags = HWMOD_NO_IDLEST,
2231}; 1055};
@@ -2252,36 +1076,12 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2252 1076
2253/* mcbsp1 */ 1077/* mcbsp1 */
2254static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 1078static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2255 { .name = "irq", .irq = 16 }, 1079 { .name = "common", .irq = 16 },
2256 { .name = "tx", .irq = 59 }, 1080 { .name = "tx", .irq = 59 },
2257 { .name = "rx", .irq = 60 }, 1081 { .name = "rx", .irq = 60 },
2258 { .irq = -1 } 1082 { .irq = -1 }
2259}; 1083};
2260 1084
2261static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2262 {
2263 .name = "mpu",
2264 .pa_start = 0x48074000,
2265 .pa_end = 0x480740ff,
2266 .flags = ADDR_TYPE_RT
2267 },
2268 { }
2269};
2270
2271/* l4_core -> mcbsp1 */
2272static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap3xxx_mcbsp1_hwmod,
2275 .clk = "mcbsp1_ick",
2276 .addr = omap3xxx_mcbsp1_addrs,
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2278};
2279
2280/* mcbsp1 slave ports */
2281static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2282 &omap3xxx_l4_core__mcbsp1,
2283};
2284
2285static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1085static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2286 .name = "mcbsp1", 1086 .name = "mcbsp1",
2287 .class = &omap3xxx_mcbsp_hwmod_class, 1087 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2297,42 +1097,16 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2297 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1097 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2298 }, 1098 },
2299 }, 1099 },
2300 .slaves = omap3xxx_mcbsp1_slaves,
2301 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2302}; 1100};
2303 1101
2304/* mcbsp2 */ 1102/* mcbsp2 */
2305static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { 1103static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2306 { .name = "irq", .irq = 17 }, 1104 { .name = "common", .irq = 17 },
2307 { .name = "tx", .irq = 62 }, 1105 { .name = "tx", .irq = 62 },
2308 { .name = "rx", .irq = 63 }, 1106 { .name = "rx", .irq = 63 },
2309 { .irq = -1 } 1107 { .irq = -1 }
2310}; 1108};
2311 1109
2312static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2313 {
2314 .name = "mpu",
2315 .pa_start = 0x49022000,
2316 .pa_end = 0x490220ff,
2317 .flags = ADDR_TYPE_RT
2318 },
2319 { }
2320};
2321
2322/* l4_per -> mcbsp2 */
2323static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2324 .master = &omap3xxx_l4_per_hwmod,
2325 .slave = &omap3xxx_mcbsp2_hwmod,
2326 .clk = "mcbsp2_ick",
2327 .addr = omap3xxx_mcbsp2_addrs,
2328 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329};
2330
2331/* mcbsp2 slave ports */
2332static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2333 &omap3xxx_l4_per__mcbsp2,
2334};
2335
2336static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1110static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2337 .sidetone = "mcbsp2_sidetone", 1111 .sidetone = "mcbsp2_sidetone",
2338}; 1112};
@@ -2352,45 +1126,19 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2352 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1126 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2353 }, 1127 },
2354 }, 1128 },
2355 .slaves = omap3xxx_mcbsp2_slaves,
2356 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2357 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1129 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2358}; 1130};
2359 1131
2360/* mcbsp3 */ 1132/* mcbsp3 */
2361static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { 1133static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2362 { .name = "irq", .irq = 22 }, 1134 { .name = "common", .irq = 22 },
2363 { .name = "tx", .irq = 89 }, 1135 { .name = "tx", .irq = 89 },
2364 { .name = "rx", .irq = 90 }, 1136 { .name = "rx", .irq = 90 },
2365 { .irq = -1 } 1137 { .irq = -1 }
2366}; 1138};
2367 1139
2368static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2369 {
2370 .name = "mpu",
2371 .pa_start = 0x49024000,
2372 .pa_end = 0x490240ff,
2373 .flags = ADDR_TYPE_RT
2374 },
2375 { }
2376};
2377
2378/* l4_per -> mcbsp3 */
2379static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2380 .master = &omap3xxx_l4_per_hwmod,
2381 .slave = &omap3xxx_mcbsp3_hwmod,
2382 .clk = "mcbsp3_ick",
2383 .addr = omap3xxx_mcbsp3_addrs,
2384 .user = OCP_USER_MPU | OCP_USER_SDMA,
2385};
2386
2387/* mcbsp3 slave ports */
2388static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2389 &omap3xxx_l4_per__mcbsp3,
2390};
2391
2392static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1140static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2393 .sidetone = "mcbsp3_sidetone", 1141 .sidetone = "mcbsp3_sidetone",
2394}; 1142};
2395 1143
2396static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1144static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
@@ -2408,14 +1156,12 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2408 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1156 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2409 }, 1157 },
2410 }, 1158 },
2411 .slaves = omap3xxx_mcbsp3_slaves,
2412 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2413 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1159 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2414}; 1160};
2415 1161
2416/* mcbsp4 */ 1162/* mcbsp4 */
2417static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { 1163static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2418 { .name = "irq", .irq = 23 }, 1164 { .name = "common", .irq = 23 },
2419 { .name = "tx", .irq = 54 }, 1165 { .name = "tx", .irq = 54 },
2420 { .name = "rx", .irq = 55 }, 1166 { .name = "rx", .irq = 55 },
2421 { .irq = -1 } 1167 { .irq = -1 }
@@ -2427,30 +1173,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2427 { .dma_req = -1 } 1173 { .dma_req = -1 }
2428}; 1174};
2429 1175
2430static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2431 {
2432 .name = "mpu",
2433 .pa_start = 0x49026000,
2434 .pa_end = 0x490260ff,
2435 .flags = ADDR_TYPE_RT
2436 },
2437 { }
2438};
2439
2440/* l4_per -> mcbsp4 */
2441static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2442 .master = &omap3xxx_l4_per_hwmod,
2443 .slave = &omap3xxx_mcbsp4_hwmod,
2444 .clk = "mcbsp4_ick",
2445 .addr = omap3xxx_mcbsp4_addrs,
2446 .user = OCP_USER_MPU | OCP_USER_SDMA,
2447};
2448
2449/* mcbsp4 slave ports */
2450static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2451 &omap3xxx_l4_per__mcbsp4,
2452};
2453
2454static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1176static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2455 .name = "mcbsp4", 1177 .name = "mcbsp4",
2456 .class = &omap3xxx_mcbsp_hwmod_class, 1178 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2466,13 +1188,11 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2466 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1188 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2467 }, 1189 },
2468 }, 1190 },
2469 .slaves = omap3xxx_mcbsp4_slaves,
2470 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2471}; 1191};
2472 1192
2473/* mcbsp5 */ 1193/* mcbsp5 */
2474static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { 1194static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2475 { .name = "irq", .irq = 27 }, 1195 { .name = "common", .irq = 27 },
2476 { .name = "tx", .irq = 81 }, 1196 { .name = "tx", .irq = 81 },
2477 { .name = "rx", .irq = 82 }, 1197 { .name = "rx", .irq = 82 },
2478 { .irq = -1 } 1198 { .irq = -1 }
@@ -2484,30 +1204,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2484 { .dma_req = -1 } 1204 { .dma_req = -1 }
2485}; 1205};
2486 1206
2487static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2488 {
2489 .name = "mpu",
2490 .pa_start = 0x48096000,
2491 .pa_end = 0x480960ff,
2492 .flags = ADDR_TYPE_RT
2493 },
2494 { }
2495};
2496
2497/* l4_core -> mcbsp5 */
2498static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2499 .master = &omap3xxx_l4_core_hwmod,
2500 .slave = &omap3xxx_mcbsp5_hwmod,
2501 .clk = "mcbsp5_ick",
2502 .addr = omap3xxx_mcbsp5_addrs,
2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2504};
2505
2506/* mcbsp5 slave ports */
2507static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2508 &omap3xxx_l4_core__mcbsp5,
2509};
2510
2511static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1207static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2512 .name = "mcbsp5", 1208 .name = "mcbsp5",
2513 .class = &omap3xxx_mcbsp_hwmod_class, 1209 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2523,11 +1219,9 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2523 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1219 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2524 }, 1220 },
2525 }, 1221 },
2526 .slaves = omap3xxx_mcbsp5_slaves,
2527 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2528}; 1222};
2529/* 'mcbsp sidetone' class */
2530 1223
1224/* 'mcbsp sidetone' class */
2531static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1225static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2532 .sysc_offs = 0x0010, 1226 .sysc_offs = 0x0010,
2533 .sysc_flags = SYSC_HAS_AUTOIDLE, 1227 .sysc_flags = SYSC_HAS_AUTOIDLE,
@@ -2545,30 +1239,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2545 { .irq = -1 } 1239 { .irq = -1 }
2546}; 1240};
2547 1241
2548static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2549 {
2550 .name = "sidetone",
2551 .pa_start = 0x49028000,
2552 .pa_end = 0x490280ff,
2553 .flags = ADDR_TYPE_RT
2554 },
2555 { }
2556};
2557
2558/* l4_per -> mcbsp2_sidetone */
2559static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2560 .master = &omap3xxx_l4_per_hwmod,
2561 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2562 .clk = "mcbsp2_ick",
2563 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2564 .user = OCP_USER_MPU,
2565};
2566
2567/* mcbsp2_sidetone slave ports */
2568static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2569 &omap3xxx_l4_per__mcbsp2_sidetone,
2570};
2571
2572static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1242static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2573 .name = "mcbsp2_sidetone", 1243 .name = "mcbsp2_sidetone",
2574 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1244 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2583,8 +1253,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2583 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1253 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2584 }, 1254 },
2585 }, 1255 },
2586 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2587 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2588}; 1256};
2589 1257
2590/* mcbsp3_sidetone */ 1258/* mcbsp3_sidetone */
@@ -2593,30 +1261,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2593 { .irq = -1 } 1261 { .irq = -1 }
2594}; 1262};
2595 1263
2596static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2597 {
2598 .name = "sidetone",
2599 .pa_start = 0x4902A000,
2600 .pa_end = 0x4902A0ff,
2601 .flags = ADDR_TYPE_RT
2602 },
2603 { }
2604};
2605
2606/* l4_per -> mcbsp3_sidetone */
2607static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2608 .master = &omap3xxx_l4_per_hwmod,
2609 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2610 .clk = "mcbsp3_ick",
2611 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2612 .user = OCP_USER_MPU,
2613};
2614
2615/* mcbsp3_sidetone slave ports */
2616static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2617 &omap3xxx_l4_per__mcbsp3_sidetone,
2618};
2619
2620static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1264static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2621 .name = "mcbsp3_sidetone", 1265 .name = "mcbsp3_sidetone",
2622 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1266 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2631,11 +1275,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2631 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1275 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2632 }, 1276 },
2633 }, 1277 },
2634 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2635 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2636}; 1278};
2637 1279
2638
2639/* SR common */ 1280/* SR common */
2640static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1281static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2641 .clkact_shift = 20, 1282 .clkact_shift = 20,
@@ -2656,7 +1297,7 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2656 1297
2657static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1298static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2658 .sidle_shift = 24, 1299 .sidle_shift = 24,
2659 .enwkup_shift = 26 1300 .enwkup_shift = 26,
2660}; 1301};
2661 1302
2662static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1303static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
@@ -2678,12 +1319,13 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2678 .sensor_voltdm_name = "mpu_iva", 1319 .sensor_voltdm_name = "mpu_iva",
2679}; 1320};
2680 1321
2681static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { 1322static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
2682 &omap3_l4_core__sr1, 1323 { .irq = 18 },
1324 { .irq = -1 }
2683}; 1325};
2684 1326
2685static struct omap_hwmod omap34xx_sr1_hwmod = { 1327static struct omap_hwmod omap34xx_sr1_hwmod = {
2686 .name = "sr1_hwmod", 1328 .name = "sr1",
2687 .class = &omap34xx_smartreflex_hwmod_class, 1329 .class = &omap34xx_smartreflex_hwmod_class,
2688 .main_clk = "sr1_fck", 1330 .main_clk = "sr1_fck",
2689 .prcm = { 1331 .prcm = {
@@ -2695,15 +1337,13 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
2695 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1337 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2696 }, 1338 },
2697 }, 1339 },
2698 .slaves = omap3_sr1_slaves,
2699 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2700 .dev_attr = &sr1_dev_attr, 1340 .dev_attr = &sr1_dev_attr,
2701 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1341 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2702 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1342 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2703}; 1343};
2704 1344
2705static struct omap_hwmod omap36xx_sr1_hwmod = { 1345static struct omap_hwmod omap36xx_sr1_hwmod = {
2706 .name = "sr1_hwmod", 1346 .name = "sr1",
2707 .class = &omap36xx_smartreflex_hwmod_class, 1347 .class = &omap36xx_smartreflex_hwmod_class,
2708 .main_clk = "sr1_fck", 1348 .main_clk = "sr1_fck",
2709 .prcm = { 1349 .prcm = {
@@ -2715,8 +1355,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
2715 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1355 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2716 }, 1356 },
2717 }, 1357 },
2718 .slaves = omap3_sr1_slaves,
2719 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2720 .dev_attr = &sr1_dev_attr, 1358 .dev_attr = &sr1_dev_attr,
2721 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1359 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2722}; 1360};
@@ -2726,12 +1364,13 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2726 .sensor_voltdm_name = "core", 1364 .sensor_voltdm_name = "core",
2727}; 1365};
2728 1366
2729static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { 1367static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
2730 &omap3_l4_core__sr2, 1368 { .irq = 19 },
1369 { .irq = -1 }
2731}; 1370};
2732 1371
2733static struct omap_hwmod omap34xx_sr2_hwmod = { 1372static struct omap_hwmod omap34xx_sr2_hwmod = {
2734 .name = "sr2_hwmod", 1373 .name = "sr2",
2735 .class = &omap34xx_smartreflex_hwmod_class, 1374 .class = &omap34xx_smartreflex_hwmod_class,
2736 .main_clk = "sr2_fck", 1375 .main_clk = "sr2_fck",
2737 .prcm = { 1376 .prcm = {
@@ -2743,15 +1382,13 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
2743 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1382 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2744 }, 1383 },
2745 }, 1384 },
2746 .slaves = omap3_sr2_slaves,
2747 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2748 .dev_attr = &sr2_dev_attr, 1385 .dev_attr = &sr2_dev_attr,
2749 .mpu_irqs = omap3_smartreflex_core_irqs, 1386 .mpu_irqs = omap3_smartreflex_core_irqs,
2750 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1387 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2751}; 1388};
2752 1389
2753static struct omap_hwmod omap36xx_sr2_hwmod = { 1390static struct omap_hwmod omap36xx_sr2_hwmod = {
2754 .name = "sr2_hwmod", 1391 .name = "sr2",
2755 .class = &omap36xx_smartreflex_hwmod_class, 1392 .class = &omap36xx_smartreflex_hwmod_class,
2756 .main_clk = "sr2_fck", 1393 .main_clk = "sr2_fck",
2757 .prcm = { 1394 .prcm = {
@@ -2763,8 +1400,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
2763 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1400 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2764 }, 1401 },
2765 }, 1402 },
2766 .slaves = omap3_sr2_slaves,
2767 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2768 .dev_attr = &sr2_dev_attr, 1403 .dev_attr = &sr2_dev_attr,
2769 .mpu_irqs = omap3_smartreflex_core_irqs, 1404 .mpu_irqs = omap3_smartreflex_core_irqs,
2770}; 1405};
@@ -2790,34 +1425,11 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2790 .sysc = &omap3xxx_mailbox_sysc, 1425 .sysc = &omap3xxx_mailbox_sysc,
2791}; 1426};
2792 1427
2793static struct omap_hwmod omap3xxx_mailbox_hwmod;
2794static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1428static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2795 { .irq = 26 }, 1429 { .irq = 26 },
2796 { .irq = -1 } 1430 { .irq = -1 }
2797}; 1431};
2798 1432
2799static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2800 {
2801 .pa_start = 0x48094000,
2802 .pa_end = 0x480941ff,
2803 .flags = ADDR_TYPE_RT,
2804 },
2805 { }
2806};
2807
2808/* l4_core -> mailbox */
2809static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2810 .master = &omap3xxx_l4_core_hwmod,
2811 .slave = &omap3xxx_mailbox_hwmod,
2812 .addr = omap3xxx_mailbox_addrs,
2813 .user = OCP_USER_MPU | OCP_USER_SDMA,
2814};
2815
2816/* mailbox slave ports */
2817static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2818 &omap3xxx_l4_core__mailbox,
2819};
2820
2821static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1433static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2822 .name = "mailbox", 1434 .name = "mailbox",
2823 .class = &omap3xxx_mailbox_hwmod_class, 1435 .class = &omap3xxx_mailbox_hwmod_class,
@@ -2832,53 +1444,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2832 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1444 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2833 }, 1445 },
2834 }, 1446 },
2835 .slaves = omap3xxx_mailbox_slaves,
2836 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2837};
2838
2839/* l4 core -> mcspi1 interface */
2840static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2841 .master = &omap3xxx_l4_core_hwmod,
2842 .slave = &omap34xx_mcspi1,
2843 .clk = "mcspi1_ick",
2844 .addr = omap2_mcspi1_addr_space,
2845 .user = OCP_USER_MPU | OCP_USER_SDMA,
2846};
2847
2848/* l4 core -> mcspi2 interface */
2849static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2850 .master = &omap3xxx_l4_core_hwmod,
2851 .slave = &omap34xx_mcspi2,
2852 .clk = "mcspi2_ick",
2853 .addr = omap2_mcspi2_addr_space,
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855};
2856
2857/* l4 core -> mcspi3 interface */
2858static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2859 .master = &omap3xxx_l4_core_hwmod,
2860 .slave = &omap34xx_mcspi3,
2861 .clk = "mcspi3_ick",
2862 .addr = omap2430_mcspi3_addr_space,
2863 .user = OCP_USER_MPU | OCP_USER_SDMA,
2864};
2865
2866/* l4 core -> mcspi4 interface */
2867static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2868 {
2869 .pa_start = 0x480ba000,
2870 .pa_end = 0x480ba0ff,
2871 .flags = ADDR_TYPE_RT,
2872 },
2873 { }
2874};
2875
2876static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2877 .master = &omap3xxx_l4_core_hwmod,
2878 .slave = &omap34xx_mcspi4,
2879 .clk = "mcspi4_ick",
2880 .addr = omap34xx_mcspi4_addr_space,
2881 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882}; 1447};
2883 1448
2884/* 1449/*
@@ -2905,10 +1470,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
2905}; 1470};
2906 1471
2907/* mcspi1 */ 1472/* mcspi1 */
2908static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2909 &omap34xx_l4_core__mcspi1,
2910};
2911
2912static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1473static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2913 .num_chipselect = 4, 1474 .num_chipselect = 4,
2914}; 1475};
@@ -2927,17 +1488,11 @@ static struct omap_hwmod omap34xx_mcspi1 = {
2927 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1488 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2928 }, 1489 },
2929 }, 1490 },
2930 .slaves = omap34xx_mcspi1_slaves,
2931 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2932 .class = &omap34xx_mcspi_class, 1491 .class = &omap34xx_mcspi_class,
2933 .dev_attr = &omap_mcspi1_dev_attr, 1492 .dev_attr = &omap_mcspi1_dev_attr,
2934}; 1493};
2935 1494
2936/* mcspi2 */ 1495/* mcspi2 */
2937static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2938 &omap34xx_l4_core__mcspi2,
2939};
2940
2941static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1496static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2942 .num_chipselect = 2, 1497 .num_chipselect = 2,
2943}; 1498};
@@ -2956,8 +1511,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
2956 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1511 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2957 }, 1512 },
2958 }, 1513 },
2959 .slaves = omap34xx_mcspi2_slaves,
2960 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2961 .class = &omap34xx_mcspi_class, 1514 .class = &omap34xx_mcspi_class,
2962 .dev_attr = &omap_mcspi2_dev_attr, 1515 .dev_attr = &omap_mcspi2_dev_attr,
2963}; 1516};
@@ -2976,10 +1529,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2976 { .dma_req = -1 } 1529 { .dma_req = -1 }
2977}; 1530};
2978 1531
2979static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2980 &omap34xx_l4_core__mcspi3,
2981};
2982
2983static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1532static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2984 .num_chipselect = 2, 1533 .num_chipselect = 2,
2985}; 1534};
@@ -2998,13 +1547,11 @@ static struct omap_hwmod omap34xx_mcspi3 = {
2998 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1547 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2999 }, 1548 },
3000 }, 1549 },
3001 .slaves = omap34xx_mcspi3_slaves,
3002 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3003 .class = &omap34xx_mcspi_class, 1550 .class = &omap34xx_mcspi_class,
3004 .dev_attr = &omap_mcspi3_dev_attr, 1551 .dev_attr = &omap_mcspi3_dev_attr,
3005}; 1552};
3006 1553
3007/* SPI4 */ 1554/* mcspi4 */
3008static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 1555static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3009 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ 1556 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3010 { .irq = -1 } 1557 { .irq = -1 }
@@ -3016,10 +1563,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3016 { .dma_req = -1 } 1563 { .dma_req = -1 }
3017}; 1564};
3018 1565
3019static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3020 &omap34xx_l4_core__mcspi4,
3021};
3022
3023static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1566static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3024 .num_chipselect = 1, 1567 .num_chipselect = 1,
3025}; 1568};
@@ -3038,15 +1581,11 @@ static struct omap_hwmod omap34xx_mcspi4 = {
3038 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1581 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3039 }, 1582 },
3040 }, 1583 },
3041 .slaves = omap34xx_mcspi4_slaves,
3042 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3043 .class = &omap34xx_mcspi_class, 1584 .class = &omap34xx_mcspi_class,
3044 .dev_attr = &omap_mcspi4_dev_attr, 1585 .dev_attr = &omap_mcspi4_dev_attr,
3045}; 1586};
3046 1587
3047/* 1588/* usbhsotg */
3048 * usbhsotg
3049 */
3050static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1589static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3051 .rev_offs = 0x0400, 1590 .rev_offs = 0x0400,
3052 .sysc_offs = 0x0404, 1591 .sysc_offs = 0x0404,
@@ -3063,6 +1602,7 @@ static struct omap_hwmod_class usbotg_class = {
3063 .name = "usbotg", 1602 .name = "usbotg",
3064 .sysc = &omap3xxx_usbhsotg_sysc, 1603 .sysc = &omap3xxx_usbhsotg_sysc,
3065}; 1604};
1605
3066/* usb_otg_hs */ 1606/* usb_otg_hs */
3067static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { 1607static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3068 1608
@@ -3085,10 +1625,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3085 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 1625 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3086 }, 1626 },
3087 }, 1627 },
3088 .masters = omap3xxx_usbhsotg_masters,
3089 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3090 .slaves = omap3xxx_usbhsotg_slaves,
3091 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3092 .class = &usbotg_class, 1628 .class = &usbotg_class,
3093 1629
3094 /* 1630 /*
@@ -3120,15 +1656,10 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3120 .omap2 = { 1656 .omap2 = {
3121 }, 1657 },
3122 }, 1658 },
3123 .masters = am35xx_usbhsotg_masters,
3124 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3125 .slaves = am35xx_usbhsotg_slaves,
3126 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3127 .class = &am35xx_usbotg_class, 1659 .class = &am35xx_usbotg_class,
3128}; 1660};
3129 1661
3130/* MMC/SD/SDIO common */ 1662/* MMC/SD/SDIO common */
3131
3132static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1663static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3133 .rev_offs = 0x1fc, 1664 .rev_offs = 0x1fc,
3134 .sysc_offs = 0x10, 1665 .sysc_offs = 0x10,
@@ -3162,10 +1693,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3162 { .role = "dbck", .clk = "omap_32k_fck", }, 1693 { .role = "dbck", .clk = "omap_32k_fck", },
3163}; 1694};
3164 1695
3165static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3166 &omap3xxx_l4_core__mmc1,
3167};
3168
3169static struct omap_mmc_dev_attr mmc1_dev_attr = { 1696static struct omap_mmc_dev_attr mmc1_dev_attr = {
3170 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1697 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3171}; 1698};
@@ -3193,8 +1720,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3193 }, 1720 },
3194 }, 1721 },
3195 .dev_attr = &mmc1_pre_es3_dev_attr, 1722 .dev_attr = &mmc1_pre_es3_dev_attr,
3196 .slaves = omap3xxx_mmc1_slaves,
3197 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3198 .class = &omap34xx_mmc_class, 1723 .class = &omap34xx_mmc_class,
3199}; 1724};
3200 1725
@@ -3215,8 +1740,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3215 }, 1740 },
3216 }, 1741 },
3217 .dev_attr = &mmc1_dev_attr, 1742 .dev_attr = &mmc1_dev_attr,
3218 .slaves = omap3xxx_mmc1_slaves,
3219 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3220 .class = &omap34xx_mmc_class, 1743 .class = &omap34xx_mmc_class,
3221}; 1744};
3222 1745
@@ -3237,10 +1760,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3237 { .role = "dbck", .clk = "omap_32k_fck", }, 1760 { .role = "dbck", .clk = "omap_32k_fck", },
3238}; 1761};
3239 1762
3240static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3241 &omap3xxx_l4_core__mmc2,
3242};
3243
3244/* See 35xx errata 2.1.1.128 in SPRZ278F */ 1763/* See 35xx errata 2.1.1.128 in SPRZ278F */
3245static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { 1764static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3246 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1765 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
@@ -3263,8 +1782,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3263 }, 1782 },
3264 }, 1783 },
3265 .dev_attr = &mmc2_pre_es3_dev_attr, 1784 .dev_attr = &mmc2_pre_es3_dev_attr,
3266 .slaves = omap3xxx_mmc2_slaves,
3267 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3268 .class = &omap34xx_mmc_class, 1785 .class = &omap34xx_mmc_class,
3269}; 1786};
3270 1787
@@ -3284,8 +1801,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3284 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1801 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3285 }, 1802 },
3286 }, 1803 },
3287 .slaves = omap3xxx_mmc2_slaves,
3288 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3289 .class = &omap34xx_mmc_class, 1804 .class = &omap34xx_mmc_class,
3290}; 1805};
3291 1806
@@ -3306,10 +1821,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3306 { .role = "dbck", .clk = "omap_32k_fck", }, 1821 { .role = "dbck", .clk = "omap_32k_fck", },
3307}; 1822};
3308 1823
3309static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3310 &omap3xxx_l4_core__mmc3,
3311};
3312
3313static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1824static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3314 .name = "mmc3", 1825 .name = "mmc3",
3315 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 1826 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
@@ -3325,8 +1836,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3325 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1836 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3326 }, 1837 },
3327 }, 1838 },
3328 .slaves = omap3xxx_mmc3_slaves,
3329 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3330 .class = &omap34xx_mmc_class, 1839 .class = &omap34xx_mmc_class,
3331}; 1840};
3332 1841
@@ -3334,12 +1843,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3334 * 'usb_host_hs' class 1843 * 'usb_host_hs' class
3335 * high-speed multi-port usb host controller 1844 * high-speed multi-port usb host controller
3336 */ 1845 */
3337static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3338 .master = &omap3xxx_usb_host_hs_hwmod,
3339 .slave = &omap3xxx_l3_main_hwmod,
3340 .clk = "core_l3_ick",
3341 .user = OCP_USER_MPU,
3342};
3343 1846
3344static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1847static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
3345 .rev_offs = 0x0000, 1848 .rev_offs = 0x0000,
@@ -3358,42 +1861,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
3358 .sysc = &omap3xxx_usb_host_hs_sysc, 1861 .sysc = &omap3xxx_usb_host_hs_sysc,
3359}; 1862};
3360 1863
3361static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
3362 &omap3xxx_usb_host_hs__l3_main_2,
3363};
3364
3365static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3366 {
3367 .name = "uhh",
3368 .pa_start = 0x48064000,
3369 .pa_end = 0x480643ff,
3370 .flags = ADDR_TYPE_RT
3371 },
3372 {
3373 .name = "ohci",
3374 .pa_start = 0x48064400,
3375 .pa_end = 0x480647ff,
3376 },
3377 {
3378 .name = "ehci",
3379 .pa_start = 0x48064800,
3380 .pa_end = 0x48064cff,
3381 },
3382 {}
3383};
3384
3385static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3386 .master = &omap3xxx_l4_core_hwmod,
3387 .slave = &omap3xxx_usb_host_hs_hwmod,
3388 .clk = "usbhost_ick",
3389 .addr = omap3xxx_usb_host_hs_addrs,
3390 .user = OCP_USER_MPU | OCP_USER_SDMA,
3391};
3392
3393static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
3394 &omap3xxx_l4_core__usb_host_hs,
3395};
3396
3397static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { 1864static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3398 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, 1865 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3399}; 1866};
@@ -3422,10 +1889,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
3422 }, 1889 },
3423 .opt_clks = omap3xxx_usb_host_hs_opt_clks, 1890 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
3424 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), 1891 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
3425 .slaves = omap3xxx_usb_host_hs_slaves,
3426 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
3427 .masters = omap3xxx_usb_host_hs_masters,
3428 .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
3429 1892
3430 /* 1893 /*
3431 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1894 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3501,6 +1964,1134 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3501 { .irq = -1 } 1964 { .irq = -1 }
3502}; 1965};
3503 1966
1967static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1968 .name = "usb_tll_hs",
1969 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1970 .clkdm_name = "l3_init_clkdm",
1971 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
1972 .main_clk = "usbtll_fck",
1973 .prcm = {
1974 .omap2 = {
1975 .module_offs = CORE_MOD,
1976 .prcm_reg_id = 3,
1977 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1978 .idlest_reg_id = 3,
1979 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1980 },
1981 },
1982};
1983
1984static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1985 .name = "hdq1w",
1986 .mpu_irqs = omap2_hdq1w_mpu_irqs,
1987 .main_clk = "hdq_fck",
1988 .prcm = {
1989 .omap2 = {
1990 .module_offs = CORE_MOD,
1991 .prcm_reg_id = 1,
1992 .module_bit = OMAP3430_EN_HDQ_SHIFT,
1993 .idlest_reg_id = 1,
1994 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1995 },
1996 },
1997 .class = &omap2_hdq1w_class,
1998};
1999
2000/*
2001 * '32K sync counter' class
2002 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2003 */
2004static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2005 .rev_offs = 0x0000,
2006 .sysc_offs = 0x0004,
2007 .sysc_flags = SYSC_HAS_SIDLEMODE,
2008 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2009 .sysc_fields = &omap_hwmod_sysc_type1,
2010};
2011
2012static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2013 .name = "counter",
2014 .sysc = &omap3xxx_counter_sysc,
2015};
2016
2017static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2018 .name = "counter_32k",
2019 .class = &omap3xxx_counter_hwmod_class,
2020 .clkdm_name = "wkup_clkdm",
2021 .flags = HWMOD_SWSUP_SIDLE,
2022 .main_clk = "wkup_32k_fck",
2023 .prcm = {
2024 .omap2 = {
2025 .module_offs = WKUP_MOD,
2026 .prcm_reg_id = 1,
2027 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2028 .idlest_reg_id = 1,
2029 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2030 },
2031 },
2032};
2033
2034/*
2035 * interfaces
2036 */
2037
2038/* L3 -> L4_CORE interface */
2039static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2040 .master = &omap3xxx_l3_main_hwmod,
2041 .slave = &omap3xxx_l4_core_hwmod,
2042 .user = OCP_USER_MPU | OCP_USER_SDMA,
2043};
2044
2045/* L3 -> L4_PER interface */
2046static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2047 .master = &omap3xxx_l3_main_hwmod,
2048 .slave = &omap3xxx_l4_per_hwmod,
2049 .user = OCP_USER_MPU | OCP_USER_SDMA,
2050};
2051
2052static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2053 {
2054 .pa_start = 0x68000000,
2055 .pa_end = 0x6800ffff,
2056 .flags = ADDR_TYPE_RT,
2057 },
2058 { }
2059};
2060
2061/* MPU -> L3 interface */
2062static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2063 .master = &omap3xxx_mpu_hwmod,
2064 .slave = &omap3xxx_l3_main_hwmod,
2065 .addr = omap3xxx_l3_main_addrs,
2066 .user = OCP_USER_MPU,
2067};
2068
2069/* DSS -> l3 */
2070static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2071 .master = &omap3430es1_dss_core_hwmod,
2072 .slave = &omap3xxx_l3_main_hwmod,
2073 .user = OCP_USER_MPU | OCP_USER_SDMA,
2074};
2075
2076static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2077 .master = &omap3xxx_dss_core_hwmod,
2078 .slave = &omap3xxx_l3_main_hwmod,
2079 .fw = {
2080 .omap2 = {
2081 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2082 .flags = OMAP_FIREWALL_L3,
2083 }
2084 },
2085 .user = OCP_USER_MPU | OCP_USER_SDMA,
2086};
2087
2088/* l3_core -> usbhsotg interface */
2089static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2090 .master = &omap3xxx_usbhsotg_hwmod,
2091 .slave = &omap3xxx_l3_main_hwmod,
2092 .clk = "core_l3_ick",
2093 .user = OCP_USER_MPU,
2094};
2095
2096/* l3_core -> am35xx_usbhsotg interface */
2097static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2098 .master = &am35xx_usbhsotg_hwmod,
2099 .slave = &omap3xxx_l3_main_hwmod,
2100 .clk = "core_l3_ick",
2101 .user = OCP_USER_MPU,
2102};
2103/* L4_CORE -> L4_WKUP interface */
2104static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2105 .master = &omap3xxx_l4_core_hwmod,
2106 .slave = &omap3xxx_l4_wkup_hwmod,
2107 .user = OCP_USER_MPU | OCP_USER_SDMA,
2108};
2109
2110/* L4 CORE -> MMC1 interface */
2111static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2112 .master = &omap3xxx_l4_core_hwmod,
2113 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2114 .clk = "mmchs1_ick",
2115 .addr = omap2430_mmc1_addr_space,
2116 .user = OCP_USER_MPU | OCP_USER_SDMA,
2117 .flags = OMAP_FIREWALL_L4
2118};
2119
2120static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2121 .master = &omap3xxx_l4_core_hwmod,
2122 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2123 .clk = "mmchs1_ick",
2124 .addr = omap2430_mmc1_addr_space,
2125 .user = OCP_USER_MPU | OCP_USER_SDMA,
2126 .flags = OMAP_FIREWALL_L4
2127};
2128
2129/* L4 CORE -> MMC2 interface */
2130static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2131 .master = &omap3xxx_l4_core_hwmod,
2132 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2133 .clk = "mmchs2_ick",
2134 .addr = omap2430_mmc2_addr_space,
2135 .user = OCP_USER_MPU | OCP_USER_SDMA,
2136 .flags = OMAP_FIREWALL_L4
2137};
2138
2139static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2140 .master = &omap3xxx_l4_core_hwmod,
2141 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2142 .clk = "mmchs2_ick",
2143 .addr = omap2430_mmc2_addr_space,
2144 .user = OCP_USER_MPU | OCP_USER_SDMA,
2145 .flags = OMAP_FIREWALL_L4
2146};
2147
2148/* L4 CORE -> MMC3 interface */
2149static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2150 {
2151 .pa_start = 0x480ad000,
2152 .pa_end = 0x480ad1ff,
2153 .flags = ADDR_TYPE_RT,
2154 },
2155 { }
2156};
2157
2158static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2159 .master = &omap3xxx_l4_core_hwmod,
2160 .slave = &omap3xxx_mmc3_hwmod,
2161 .clk = "mmchs3_ick",
2162 .addr = omap3xxx_mmc3_addr_space,
2163 .user = OCP_USER_MPU | OCP_USER_SDMA,
2164 .flags = OMAP_FIREWALL_L4
2165};
2166
2167/* L4 CORE -> UART1 interface */
2168static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2169 {
2170 .pa_start = OMAP3_UART1_BASE,
2171 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2172 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2173 },
2174 { }
2175};
2176
2177static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2178 .master = &omap3xxx_l4_core_hwmod,
2179 .slave = &omap3xxx_uart1_hwmod,
2180 .clk = "uart1_ick",
2181 .addr = omap3xxx_uart1_addr_space,
2182 .user = OCP_USER_MPU | OCP_USER_SDMA,
2183};
2184
2185/* L4 CORE -> UART2 interface */
2186static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2187 {
2188 .pa_start = OMAP3_UART2_BASE,
2189 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2190 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2191 },
2192 { }
2193};
2194
2195static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2196 .master = &omap3xxx_l4_core_hwmod,
2197 .slave = &omap3xxx_uart2_hwmod,
2198 .clk = "uart2_ick",
2199 .addr = omap3xxx_uart2_addr_space,
2200 .user = OCP_USER_MPU | OCP_USER_SDMA,
2201};
2202
2203/* L4 PER -> UART3 interface */
2204static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2205 {
2206 .pa_start = OMAP3_UART3_BASE,
2207 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2208 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2209 },
2210 { }
2211};
2212
2213static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2214 .master = &omap3xxx_l4_per_hwmod,
2215 .slave = &omap3xxx_uart3_hwmod,
2216 .clk = "uart3_ick",
2217 .addr = omap3xxx_uart3_addr_space,
2218 .user = OCP_USER_MPU | OCP_USER_SDMA,
2219};
2220
2221/* L4 PER -> UART4 interface */
2222static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2223 {
2224 .pa_start = OMAP3_UART4_BASE,
2225 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2226 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2227 },
2228 { }
2229};
2230
2231static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2232 .master = &omap3xxx_l4_per_hwmod,
2233 .slave = &omap36xx_uart4_hwmod,
2234 .clk = "uart4_ick",
2235 .addr = omap36xx_uart4_addr_space,
2236 .user = OCP_USER_MPU | OCP_USER_SDMA,
2237};
2238
2239/* AM35xx: L4 CORE -> UART4 interface */
2240static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2241 {
2242 .pa_start = OMAP3_UART4_AM35XX_BASE,
2243 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2244 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2245 },
2246};
2247
2248static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2249 .master = &omap3xxx_l4_core_hwmod,
2250 .slave = &am35xx_uart4_hwmod,
2251 .clk = "uart4_ick",
2252 .addr = am35xx_uart4_addr_space,
2253 .user = OCP_USER_MPU | OCP_USER_SDMA,
2254};
2255
2256/* L4 CORE -> I2C1 interface */
2257static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2258 .master = &omap3xxx_l4_core_hwmod,
2259 .slave = &omap3xxx_i2c1_hwmod,
2260 .clk = "i2c1_ick",
2261 .addr = omap2_i2c1_addr_space,
2262 .fw = {
2263 .omap2 = {
2264 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2265 .l4_prot_group = 7,
2266 .flags = OMAP_FIREWALL_L4,
2267 }
2268 },
2269 .user = OCP_USER_MPU | OCP_USER_SDMA,
2270};
2271
2272/* L4 CORE -> I2C2 interface */
2273static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2274 .master = &omap3xxx_l4_core_hwmod,
2275 .slave = &omap3xxx_i2c2_hwmod,
2276 .clk = "i2c2_ick",
2277 .addr = omap2_i2c2_addr_space,
2278 .fw = {
2279 .omap2 = {
2280 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2281 .l4_prot_group = 7,
2282 .flags = OMAP_FIREWALL_L4,
2283 }
2284 },
2285 .user = OCP_USER_MPU | OCP_USER_SDMA,
2286};
2287
2288/* L4 CORE -> I2C3 interface */
2289static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2290 {
2291 .pa_start = 0x48060000,
2292 .pa_end = 0x48060000 + SZ_128 - 1,
2293 .flags = ADDR_TYPE_RT,
2294 },
2295 { }
2296};
2297
2298static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2299 .master = &omap3xxx_l4_core_hwmod,
2300 .slave = &omap3xxx_i2c3_hwmod,
2301 .clk = "i2c3_ick",
2302 .addr = omap3xxx_i2c3_addr_space,
2303 .fw = {
2304 .omap2 = {
2305 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2306 .l4_prot_group = 7,
2307 .flags = OMAP_FIREWALL_L4,
2308 }
2309 },
2310 .user = OCP_USER_MPU | OCP_USER_SDMA,
2311};
2312
2313/* L4 CORE -> SR1 interface */
2314static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2315 {
2316 .pa_start = OMAP34XX_SR1_BASE,
2317 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2318 .flags = ADDR_TYPE_RT,
2319 },
2320 { }
2321};
2322
2323static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2324 .master = &omap3xxx_l4_core_hwmod,
2325 .slave = &omap34xx_sr1_hwmod,
2326 .clk = "sr_l4_ick",
2327 .addr = omap3_sr1_addr_space,
2328 .user = OCP_USER_MPU,
2329};
2330
2331static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2332 .master = &omap3xxx_l4_core_hwmod,
2333 .slave = &omap36xx_sr1_hwmod,
2334 .clk = "sr_l4_ick",
2335 .addr = omap3_sr1_addr_space,
2336 .user = OCP_USER_MPU,
2337};
2338
2339/* L4 CORE -> SR1 interface */
2340static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2341 {
2342 .pa_start = OMAP34XX_SR2_BASE,
2343 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2344 .flags = ADDR_TYPE_RT,
2345 },
2346 { }
2347};
2348
2349static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2350 .master = &omap3xxx_l4_core_hwmod,
2351 .slave = &omap34xx_sr2_hwmod,
2352 .clk = "sr_l4_ick",
2353 .addr = omap3_sr2_addr_space,
2354 .user = OCP_USER_MPU,
2355};
2356
2357static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2358 .master = &omap3xxx_l4_core_hwmod,
2359 .slave = &omap36xx_sr2_hwmod,
2360 .clk = "sr_l4_ick",
2361 .addr = omap3_sr2_addr_space,
2362 .user = OCP_USER_MPU,
2363};
2364
2365static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2366 {
2367 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2368 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2369 .flags = ADDR_TYPE_RT
2370 },
2371 { }
2372};
2373
2374/* l4_core -> usbhsotg */
2375static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2376 .master = &omap3xxx_l4_core_hwmod,
2377 .slave = &omap3xxx_usbhsotg_hwmod,
2378 .clk = "l4_ick",
2379 .addr = omap3xxx_usbhsotg_addrs,
2380 .user = OCP_USER_MPU,
2381};
2382
2383static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2384 {
2385 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2386 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2387 .flags = ADDR_TYPE_RT
2388 },
2389 { }
2390};
2391
2392/* l4_core -> usbhsotg */
2393static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2394 .master = &omap3xxx_l4_core_hwmod,
2395 .slave = &am35xx_usbhsotg_hwmod,
2396 .clk = "l4_ick",
2397 .addr = am35xx_usbhsotg_addrs,
2398 .user = OCP_USER_MPU,
2399};
2400
2401/* L4_WKUP -> L4_SEC interface */
2402static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2403 .master = &omap3xxx_l4_wkup_hwmod,
2404 .slave = &omap3xxx_l4_sec_hwmod,
2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406};
2407
2408/* IVA2 <- L3 interface */
2409static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2410 .master = &omap3xxx_l3_main_hwmod,
2411 .slave = &omap3xxx_iva_hwmod,
2412 .clk = "core_l3_ick",
2413 .user = OCP_USER_MPU | OCP_USER_SDMA,
2414};
2415
2416static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2417 {
2418 .pa_start = 0x48318000,
2419 .pa_end = 0x48318000 + SZ_1K - 1,
2420 .flags = ADDR_TYPE_RT
2421 },
2422 { }
2423};
2424
2425/* l4_wkup -> timer1 */
2426static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2427 .master = &omap3xxx_l4_wkup_hwmod,
2428 .slave = &omap3xxx_timer1_hwmod,
2429 .clk = "gpt1_ick",
2430 .addr = omap3xxx_timer1_addrs,
2431 .user = OCP_USER_MPU | OCP_USER_SDMA,
2432};
2433
2434static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2435 {
2436 .pa_start = 0x49032000,
2437 .pa_end = 0x49032000 + SZ_1K - 1,
2438 .flags = ADDR_TYPE_RT
2439 },
2440 { }
2441};
2442
2443/* l4_per -> timer2 */
2444static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2445 .master = &omap3xxx_l4_per_hwmod,
2446 .slave = &omap3xxx_timer2_hwmod,
2447 .clk = "gpt2_ick",
2448 .addr = omap3xxx_timer2_addrs,
2449 .user = OCP_USER_MPU | OCP_USER_SDMA,
2450};
2451
2452static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2453 {
2454 .pa_start = 0x49034000,
2455 .pa_end = 0x49034000 + SZ_1K - 1,
2456 .flags = ADDR_TYPE_RT
2457 },
2458 { }
2459};
2460
2461/* l4_per -> timer3 */
2462static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2463 .master = &omap3xxx_l4_per_hwmod,
2464 .slave = &omap3xxx_timer3_hwmod,
2465 .clk = "gpt3_ick",
2466 .addr = omap3xxx_timer3_addrs,
2467 .user = OCP_USER_MPU | OCP_USER_SDMA,
2468};
2469
2470static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2471 {
2472 .pa_start = 0x49036000,
2473 .pa_end = 0x49036000 + SZ_1K - 1,
2474 .flags = ADDR_TYPE_RT
2475 },
2476 { }
2477};
2478
2479/* l4_per -> timer4 */
2480static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2481 .master = &omap3xxx_l4_per_hwmod,
2482 .slave = &omap3xxx_timer4_hwmod,
2483 .clk = "gpt4_ick",
2484 .addr = omap3xxx_timer4_addrs,
2485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486};
2487
2488static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2489 {
2490 .pa_start = 0x49038000,
2491 .pa_end = 0x49038000 + SZ_1K - 1,
2492 .flags = ADDR_TYPE_RT
2493 },
2494 { }
2495};
2496
2497/* l4_per -> timer5 */
2498static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2499 .master = &omap3xxx_l4_per_hwmod,
2500 .slave = &omap3xxx_timer5_hwmod,
2501 .clk = "gpt5_ick",
2502 .addr = omap3xxx_timer5_addrs,
2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2504};
2505
2506static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2507 {
2508 .pa_start = 0x4903A000,
2509 .pa_end = 0x4903A000 + SZ_1K - 1,
2510 .flags = ADDR_TYPE_RT
2511 },
2512 { }
2513};
2514
2515/* l4_per -> timer6 */
2516static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2517 .master = &omap3xxx_l4_per_hwmod,
2518 .slave = &omap3xxx_timer6_hwmod,
2519 .clk = "gpt6_ick",
2520 .addr = omap3xxx_timer6_addrs,
2521 .user = OCP_USER_MPU | OCP_USER_SDMA,
2522};
2523
2524static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2525 {
2526 .pa_start = 0x4903C000,
2527 .pa_end = 0x4903C000 + SZ_1K - 1,
2528 .flags = ADDR_TYPE_RT
2529 },
2530 { }
2531};
2532
2533/* l4_per -> timer7 */
2534static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2535 .master = &omap3xxx_l4_per_hwmod,
2536 .slave = &omap3xxx_timer7_hwmod,
2537 .clk = "gpt7_ick",
2538 .addr = omap3xxx_timer7_addrs,
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2540};
2541
2542static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2543 {
2544 .pa_start = 0x4903E000,
2545 .pa_end = 0x4903E000 + SZ_1K - 1,
2546 .flags = ADDR_TYPE_RT
2547 },
2548 { }
2549};
2550
2551/* l4_per -> timer8 */
2552static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2553 .master = &omap3xxx_l4_per_hwmod,
2554 .slave = &omap3xxx_timer8_hwmod,
2555 .clk = "gpt8_ick",
2556 .addr = omap3xxx_timer8_addrs,
2557 .user = OCP_USER_MPU | OCP_USER_SDMA,
2558};
2559
2560static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2561 {
2562 .pa_start = 0x49040000,
2563 .pa_end = 0x49040000 + SZ_1K - 1,
2564 .flags = ADDR_TYPE_RT
2565 },
2566 { }
2567};
2568
2569/* l4_per -> timer9 */
2570static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2571 .master = &omap3xxx_l4_per_hwmod,
2572 .slave = &omap3xxx_timer9_hwmod,
2573 .clk = "gpt9_ick",
2574 .addr = omap3xxx_timer9_addrs,
2575 .user = OCP_USER_MPU | OCP_USER_SDMA,
2576};
2577
2578/* l4_core -> timer10 */
2579static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2580 .master = &omap3xxx_l4_core_hwmod,
2581 .slave = &omap3xxx_timer10_hwmod,
2582 .clk = "gpt10_ick",
2583 .addr = omap2_timer10_addrs,
2584 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585};
2586
2587/* l4_core -> timer11 */
2588static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2589 .master = &omap3xxx_l4_core_hwmod,
2590 .slave = &omap3xxx_timer11_hwmod,
2591 .clk = "gpt11_ick",
2592 .addr = omap2_timer11_addrs,
2593 .user = OCP_USER_MPU | OCP_USER_SDMA,
2594};
2595
2596static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2597 {
2598 .pa_start = 0x48304000,
2599 .pa_end = 0x48304000 + SZ_1K - 1,
2600 .flags = ADDR_TYPE_RT
2601 },
2602 { }
2603};
2604
2605/* l4_core -> timer12 */
2606static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2607 .master = &omap3xxx_l4_sec_hwmod,
2608 .slave = &omap3xxx_timer12_hwmod,
2609 .clk = "gpt12_ick",
2610 .addr = omap3xxx_timer12_addrs,
2611 .user = OCP_USER_MPU | OCP_USER_SDMA,
2612};
2613
2614/* l4_wkup -> wd_timer2 */
2615static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2616 {
2617 .pa_start = 0x48314000,
2618 .pa_end = 0x4831407f,
2619 .flags = ADDR_TYPE_RT
2620 },
2621 { }
2622};
2623
2624static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2625 .master = &omap3xxx_l4_wkup_hwmod,
2626 .slave = &omap3xxx_wd_timer2_hwmod,
2627 .clk = "wdt2_ick",
2628 .addr = omap3xxx_wd_timer2_addrs,
2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
2630};
2631
2632/* l4_core -> dss */
2633static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2634 .master = &omap3xxx_l4_core_hwmod,
2635 .slave = &omap3430es1_dss_core_hwmod,
2636 .clk = "dss_ick",
2637 .addr = omap2_dss_addrs,
2638 .fw = {
2639 .omap2 = {
2640 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2641 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2642 .flags = OMAP_FIREWALL_L4,
2643 }
2644 },
2645 .user = OCP_USER_MPU | OCP_USER_SDMA,
2646};
2647
2648static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2649 .master = &omap3xxx_l4_core_hwmod,
2650 .slave = &omap3xxx_dss_core_hwmod,
2651 .clk = "dss_ick",
2652 .addr = omap2_dss_addrs,
2653 .fw = {
2654 .omap2 = {
2655 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2656 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2657 .flags = OMAP_FIREWALL_L4,
2658 }
2659 },
2660 .user = OCP_USER_MPU | OCP_USER_SDMA,
2661};
2662
2663/* l4_core -> dss_dispc */
2664static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2665 .master = &omap3xxx_l4_core_hwmod,
2666 .slave = &omap3xxx_dss_dispc_hwmod,
2667 .clk = "dss_ick",
2668 .addr = omap2_dss_dispc_addrs,
2669 .fw = {
2670 .omap2 = {
2671 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2672 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2673 .flags = OMAP_FIREWALL_L4,
2674 }
2675 },
2676 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677};
2678
2679static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2680 {
2681 .pa_start = 0x4804FC00,
2682 .pa_end = 0x4804FFFF,
2683 .flags = ADDR_TYPE_RT
2684 },
2685 { }
2686};
2687
2688/* l4_core -> dss_dsi1 */
2689static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2690 .master = &omap3xxx_l4_core_hwmod,
2691 .slave = &omap3xxx_dss_dsi1_hwmod,
2692 .clk = "dss_ick",
2693 .addr = omap3xxx_dss_dsi1_addrs,
2694 .fw = {
2695 .omap2 = {
2696 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2697 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2698 .flags = OMAP_FIREWALL_L4,
2699 }
2700 },
2701 .user = OCP_USER_MPU | OCP_USER_SDMA,
2702};
2703
2704/* l4_core -> dss_rfbi */
2705static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2706 .master = &omap3xxx_l4_core_hwmod,
2707 .slave = &omap3xxx_dss_rfbi_hwmod,
2708 .clk = "dss_ick",
2709 .addr = omap2_dss_rfbi_addrs,
2710 .fw = {
2711 .omap2 = {
2712 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2713 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2714 .flags = OMAP_FIREWALL_L4,
2715 }
2716 },
2717 .user = OCP_USER_MPU | OCP_USER_SDMA,
2718};
2719
2720/* l4_core -> dss_venc */
2721static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2722 .master = &omap3xxx_l4_core_hwmod,
2723 .slave = &omap3xxx_dss_venc_hwmod,
2724 .clk = "dss_ick",
2725 .addr = omap2_dss_venc_addrs,
2726 .fw = {
2727 .omap2 = {
2728 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2729 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2730 .flags = OMAP_FIREWALL_L4,
2731 }
2732 },
2733 .flags = OCPIF_SWSUP_IDLE,
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735};
2736
2737/* l4_wkup -> gpio1 */
2738static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2739 {
2740 .pa_start = 0x48310000,
2741 .pa_end = 0x483101ff,
2742 .flags = ADDR_TYPE_RT
2743 },
2744 { }
2745};
2746
2747static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2748 .master = &omap3xxx_l4_wkup_hwmod,
2749 .slave = &omap3xxx_gpio1_hwmod,
2750 .addr = omap3xxx_gpio1_addrs,
2751 .user = OCP_USER_MPU | OCP_USER_SDMA,
2752};
2753
2754/* l4_per -> gpio2 */
2755static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2756 {
2757 .pa_start = 0x49050000,
2758 .pa_end = 0x490501ff,
2759 .flags = ADDR_TYPE_RT
2760 },
2761 { }
2762};
2763
2764static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2765 .master = &omap3xxx_l4_per_hwmod,
2766 .slave = &omap3xxx_gpio2_hwmod,
2767 .addr = omap3xxx_gpio2_addrs,
2768 .user = OCP_USER_MPU | OCP_USER_SDMA,
2769};
2770
2771/* l4_per -> gpio3 */
2772static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2773 {
2774 .pa_start = 0x49052000,
2775 .pa_end = 0x490521ff,
2776 .flags = ADDR_TYPE_RT
2777 },
2778 { }
2779};
2780
2781static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2782 .master = &omap3xxx_l4_per_hwmod,
2783 .slave = &omap3xxx_gpio3_hwmod,
2784 .addr = omap3xxx_gpio3_addrs,
2785 .user = OCP_USER_MPU | OCP_USER_SDMA,
2786};
2787
2788/* l4_per -> gpio4 */
2789static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2790 {
2791 .pa_start = 0x49054000,
2792 .pa_end = 0x490541ff,
2793 .flags = ADDR_TYPE_RT
2794 },
2795 { }
2796};
2797
2798static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2799 .master = &omap3xxx_l4_per_hwmod,
2800 .slave = &omap3xxx_gpio4_hwmod,
2801 .addr = omap3xxx_gpio4_addrs,
2802 .user = OCP_USER_MPU | OCP_USER_SDMA,
2803};
2804
2805/* l4_per -> gpio5 */
2806static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2807 {
2808 .pa_start = 0x49056000,
2809 .pa_end = 0x490561ff,
2810 .flags = ADDR_TYPE_RT
2811 },
2812 { }
2813};
2814
2815static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2816 .master = &omap3xxx_l4_per_hwmod,
2817 .slave = &omap3xxx_gpio5_hwmod,
2818 .addr = omap3xxx_gpio5_addrs,
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2820};
2821
2822/* l4_per -> gpio6 */
2823static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2824 {
2825 .pa_start = 0x49058000,
2826 .pa_end = 0x490581ff,
2827 .flags = ADDR_TYPE_RT
2828 },
2829 { }
2830};
2831
2832static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2833 .master = &omap3xxx_l4_per_hwmod,
2834 .slave = &omap3xxx_gpio6_hwmod,
2835 .addr = omap3xxx_gpio6_addrs,
2836 .user = OCP_USER_MPU | OCP_USER_SDMA,
2837};
2838
2839/* dma_system -> L3 */
2840static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2841 .master = &omap3xxx_dma_system_hwmod,
2842 .slave = &omap3xxx_l3_main_hwmod,
2843 .clk = "core_l3_ick",
2844 .user = OCP_USER_MPU | OCP_USER_SDMA,
2845};
2846
2847static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2848 {
2849 .pa_start = 0x48056000,
2850 .pa_end = 0x48056fff,
2851 .flags = ADDR_TYPE_RT
2852 },
2853 { }
2854};
2855
2856/* l4_cfg -> dma_system */
2857static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2858 .master = &omap3xxx_l4_core_hwmod,
2859 .slave = &omap3xxx_dma_system_hwmod,
2860 .clk = "core_l4_ick",
2861 .addr = omap3xxx_dma_system_addrs,
2862 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863};
2864
2865static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2866 {
2867 .name = "mpu",
2868 .pa_start = 0x48074000,
2869 .pa_end = 0x480740ff,
2870 .flags = ADDR_TYPE_RT
2871 },
2872 { }
2873};
2874
2875/* l4_core -> mcbsp1 */
2876static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2877 .master = &omap3xxx_l4_core_hwmod,
2878 .slave = &omap3xxx_mcbsp1_hwmod,
2879 .clk = "mcbsp1_ick",
2880 .addr = omap3xxx_mcbsp1_addrs,
2881 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882};
2883
2884static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2885 {
2886 .name = "mpu",
2887 .pa_start = 0x49022000,
2888 .pa_end = 0x490220ff,
2889 .flags = ADDR_TYPE_RT
2890 },
2891 { }
2892};
2893
2894/* l4_per -> mcbsp2 */
2895static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2896 .master = &omap3xxx_l4_per_hwmod,
2897 .slave = &omap3xxx_mcbsp2_hwmod,
2898 .clk = "mcbsp2_ick",
2899 .addr = omap3xxx_mcbsp2_addrs,
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901};
2902
2903static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2904 {
2905 .name = "mpu",
2906 .pa_start = 0x49024000,
2907 .pa_end = 0x490240ff,
2908 .flags = ADDR_TYPE_RT
2909 },
2910 { }
2911};
2912
2913/* l4_per -> mcbsp3 */
2914static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2915 .master = &omap3xxx_l4_per_hwmod,
2916 .slave = &omap3xxx_mcbsp3_hwmod,
2917 .clk = "mcbsp3_ick",
2918 .addr = omap3xxx_mcbsp3_addrs,
2919 .user = OCP_USER_MPU | OCP_USER_SDMA,
2920};
2921
2922static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2923 {
2924 .name = "mpu",
2925 .pa_start = 0x49026000,
2926 .pa_end = 0x490260ff,
2927 .flags = ADDR_TYPE_RT
2928 },
2929 { }
2930};
2931
2932/* l4_per -> mcbsp4 */
2933static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2934 .master = &omap3xxx_l4_per_hwmod,
2935 .slave = &omap3xxx_mcbsp4_hwmod,
2936 .clk = "mcbsp4_ick",
2937 .addr = omap3xxx_mcbsp4_addrs,
2938 .user = OCP_USER_MPU | OCP_USER_SDMA,
2939};
2940
2941static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2942 {
2943 .name = "mpu",
2944 .pa_start = 0x48096000,
2945 .pa_end = 0x480960ff,
2946 .flags = ADDR_TYPE_RT
2947 },
2948 { }
2949};
2950
2951/* l4_core -> mcbsp5 */
2952static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2953 .master = &omap3xxx_l4_core_hwmod,
2954 .slave = &omap3xxx_mcbsp5_hwmod,
2955 .clk = "mcbsp5_ick",
2956 .addr = omap3xxx_mcbsp5_addrs,
2957 .user = OCP_USER_MPU | OCP_USER_SDMA,
2958};
2959
2960static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2961 {
2962 .name = "sidetone",
2963 .pa_start = 0x49028000,
2964 .pa_end = 0x490280ff,
2965 .flags = ADDR_TYPE_RT
2966 },
2967 { }
2968};
2969
2970/* l4_per -> mcbsp2_sidetone */
2971static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2972 .master = &omap3xxx_l4_per_hwmod,
2973 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2974 .clk = "mcbsp2_ick",
2975 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2976 .user = OCP_USER_MPU,
2977};
2978
2979static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2980 {
2981 .name = "sidetone",
2982 .pa_start = 0x4902A000,
2983 .pa_end = 0x4902A0ff,
2984 .flags = ADDR_TYPE_RT
2985 },
2986 { }
2987};
2988
2989/* l4_per -> mcbsp3_sidetone */
2990static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2991 .master = &omap3xxx_l4_per_hwmod,
2992 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2993 .clk = "mcbsp3_ick",
2994 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2995 .user = OCP_USER_MPU,
2996};
2997
2998static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2999 {
3000 .pa_start = 0x48094000,
3001 .pa_end = 0x480941ff,
3002 .flags = ADDR_TYPE_RT,
3003 },
3004 { }
3005};
3006
3007/* l4_core -> mailbox */
3008static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3009 .master = &omap3xxx_l4_core_hwmod,
3010 .slave = &omap3xxx_mailbox_hwmod,
3011 .addr = omap3xxx_mailbox_addrs,
3012 .user = OCP_USER_MPU | OCP_USER_SDMA,
3013};
3014
3015/* l4 core -> mcspi1 interface */
3016static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3017 .master = &omap3xxx_l4_core_hwmod,
3018 .slave = &omap34xx_mcspi1,
3019 .clk = "mcspi1_ick",
3020 .addr = omap2_mcspi1_addr_space,
3021 .user = OCP_USER_MPU | OCP_USER_SDMA,
3022};
3023
3024/* l4 core -> mcspi2 interface */
3025static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3026 .master = &omap3xxx_l4_core_hwmod,
3027 .slave = &omap34xx_mcspi2,
3028 .clk = "mcspi2_ick",
3029 .addr = omap2_mcspi2_addr_space,
3030 .user = OCP_USER_MPU | OCP_USER_SDMA,
3031};
3032
3033/* l4 core -> mcspi3 interface */
3034static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3035 .master = &omap3xxx_l4_core_hwmod,
3036 .slave = &omap34xx_mcspi3,
3037 .clk = "mcspi3_ick",
3038 .addr = omap2430_mcspi3_addr_space,
3039 .user = OCP_USER_MPU | OCP_USER_SDMA,
3040};
3041
3042/* l4 core -> mcspi4 interface */
3043static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3044 {
3045 .pa_start = 0x480ba000,
3046 .pa_end = 0x480ba0ff,
3047 .flags = ADDR_TYPE_RT,
3048 },
3049 { }
3050};
3051
3052static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3053 .master = &omap3xxx_l4_core_hwmod,
3054 .slave = &omap34xx_mcspi4,
3055 .clk = "mcspi4_ick",
3056 .addr = omap34xx_mcspi4_addr_space,
3057 .user = OCP_USER_MPU | OCP_USER_SDMA,
3058};
3059
3060static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3061 .master = &omap3xxx_usb_host_hs_hwmod,
3062 .slave = &omap3xxx_l3_main_hwmod,
3063 .clk = "core_l3_ick",
3064 .user = OCP_USER_MPU,
3065};
3066
3067static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3068 {
3069 .name = "uhh",
3070 .pa_start = 0x48064000,
3071 .pa_end = 0x480643ff,
3072 .flags = ADDR_TYPE_RT
3073 },
3074 {
3075 .name = "ohci",
3076 .pa_start = 0x48064400,
3077 .pa_end = 0x480647ff,
3078 },
3079 {
3080 .name = "ehci",
3081 .pa_start = 0x48064800,
3082 .pa_end = 0x48064cff,
3083 },
3084 {}
3085};
3086
3087static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3088 .master = &omap3xxx_l4_core_hwmod,
3089 .slave = &omap3xxx_usb_host_hs_hwmod,
3090 .clk = "usbhost_ick",
3091 .addr = omap3xxx_usb_host_hs_addrs,
3092 .user = OCP_USER_MPU | OCP_USER_SDMA,
3093};
3094
3504static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { 3095static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3505 { 3096 {
3506 .name = "tll", 3097 .name = "tll",
@@ -3519,183 +3110,187 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3519 .user = OCP_USER_MPU | OCP_USER_SDMA, 3110 .user = OCP_USER_MPU | OCP_USER_SDMA,
3520}; 3111};
3521 3112
3522static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { 3113/* l4_core -> hdq1w interface */
3523 &omap3xxx_l4_core__usb_tll_hs, 3114static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3115 .master = &omap3xxx_l4_core_hwmod,
3116 .slave = &omap3xxx_hdq1w_hwmod,
3117 .clk = "hdq_ick",
3118 .addr = omap2_hdq1w_addr_space,
3119 .user = OCP_USER_MPU | OCP_USER_SDMA,
3120 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3524}; 3121};
3525 3122
3526static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 3123/* l4_wkup -> 32ksync_counter */
3527 .name = "usb_tll_hs", 3124static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3528 .class = &omap3xxx_usb_tll_hs_hwmod_class, 3125 {
3529 .clkdm_name = "l3_init_clkdm", 3126 .pa_start = 0x48320000,
3530 .mpu_irqs = omap3xxx_usb_tll_hs_irqs, 3127 .pa_end = 0x4832001f,
3531 .main_clk = "usbtll_fck", 3128 .flags = ADDR_TYPE_RT
3532 .prcm = {
3533 .omap2 = {
3534 .module_offs = CORE_MOD,
3535 .prcm_reg_id = 3,
3536 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3537 .idlest_reg_id = 3,
3538 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
3539 },
3540 }, 3129 },
3541 .slaves = omap3xxx_usb_tll_hs_slaves, 3130 { }
3542 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), 3131};
3543};
3544
3545static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3546 &omap3xxx_l3_main_hwmod,
3547 &omap3xxx_l4_core_hwmod,
3548 &omap3xxx_l4_per_hwmod,
3549 &omap3xxx_l4_wkup_hwmod,
3550 &omap3xxx_mmc3_hwmod,
3551 &omap3xxx_mpu_hwmod,
3552
3553 &omap3xxx_timer1_hwmod,
3554 &omap3xxx_timer2_hwmod,
3555 &omap3xxx_timer3_hwmod,
3556 &omap3xxx_timer4_hwmod,
3557 &omap3xxx_timer5_hwmod,
3558 &omap3xxx_timer6_hwmod,
3559 &omap3xxx_timer7_hwmod,
3560 &omap3xxx_timer8_hwmod,
3561 &omap3xxx_timer9_hwmod,
3562 &omap3xxx_timer10_hwmod,
3563 &omap3xxx_timer11_hwmod,
3564
3565 &omap3xxx_wd_timer2_hwmod,
3566 &omap3xxx_uart1_hwmod,
3567 &omap3xxx_uart2_hwmod,
3568 &omap3xxx_uart3_hwmod,
3569
3570 /* i2c class */
3571 &omap3xxx_i2c1_hwmod,
3572 &omap3xxx_i2c2_hwmod,
3573 &omap3xxx_i2c3_hwmod,
3574
3575 /* gpio class */
3576 &omap3xxx_gpio1_hwmod,
3577 &omap3xxx_gpio2_hwmod,
3578 &omap3xxx_gpio3_hwmod,
3579 &omap3xxx_gpio4_hwmod,
3580 &omap3xxx_gpio5_hwmod,
3581 &omap3xxx_gpio6_hwmod,
3582
3583 /* dma_system class*/
3584 &omap3xxx_dma_system_hwmod,
3585
3586 /* mcbsp class */
3587 &omap3xxx_mcbsp1_hwmod,
3588 &omap3xxx_mcbsp2_hwmod,
3589 &omap3xxx_mcbsp3_hwmod,
3590 &omap3xxx_mcbsp4_hwmod,
3591 &omap3xxx_mcbsp5_hwmod,
3592 &omap3xxx_mcbsp2_sidetone_hwmod,
3593 &omap3xxx_mcbsp3_sidetone_hwmod,
3594
3595
3596 /* mcspi class */
3597 &omap34xx_mcspi1,
3598 &omap34xx_mcspi2,
3599 &omap34xx_mcspi3,
3600 &omap34xx_mcspi4,
3601 3132
3133static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3134 .master = &omap3xxx_l4_wkup_hwmod,
3135 .slave = &omap3xxx_counter_32k_hwmod,
3136 .clk = "omap_32ksync_ick",
3137 .addr = omap3xxx_counter_32k_addrs,
3138 .user = OCP_USER_MPU | OCP_USER_SDMA,
3139};
3140
3141static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3142 &omap3xxx_l3_main__l4_core,
3143 &omap3xxx_l3_main__l4_per,
3144 &omap3xxx_mpu__l3_main,
3145 &omap3xxx_l4_core__l4_wkup,
3146 &omap3xxx_l4_core__mmc3,
3147 &omap3_l4_core__uart1,
3148 &omap3_l4_core__uart2,
3149 &omap3_l4_per__uart3,
3150 &omap3_l4_core__i2c1,
3151 &omap3_l4_core__i2c2,
3152 &omap3_l4_core__i2c3,
3153 &omap3xxx_l4_wkup__l4_sec,
3154 &omap3xxx_l4_wkup__timer1,
3155 &omap3xxx_l4_per__timer2,
3156 &omap3xxx_l4_per__timer3,
3157 &omap3xxx_l4_per__timer4,
3158 &omap3xxx_l4_per__timer5,
3159 &omap3xxx_l4_per__timer6,
3160 &omap3xxx_l4_per__timer7,
3161 &omap3xxx_l4_per__timer8,
3162 &omap3xxx_l4_per__timer9,
3163 &omap3xxx_l4_core__timer10,
3164 &omap3xxx_l4_core__timer11,
3165 &omap3xxx_l4_wkup__wd_timer2,
3166 &omap3xxx_l4_wkup__gpio1,
3167 &omap3xxx_l4_per__gpio2,
3168 &omap3xxx_l4_per__gpio3,
3169 &omap3xxx_l4_per__gpio4,
3170 &omap3xxx_l4_per__gpio5,
3171 &omap3xxx_l4_per__gpio6,
3172 &omap3xxx_dma_system__l3,
3173 &omap3xxx_l4_core__dma_system,
3174 &omap3xxx_l4_core__mcbsp1,
3175 &omap3xxx_l4_per__mcbsp2,
3176 &omap3xxx_l4_per__mcbsp3,
3177 &omap3xxx_l4_per__mcbsp4,
3178 &omap3xxx_l4_core__mcbsp5,
3179 &omap3xxx_l4_per__mcbsp2_sidetone,
3180 &omap3xxx_l4_per__mcbsp3_sidetone,
3181 &omap34xx_l4_core__mcspi1,
3182 &omap34xx_l4_core__mcspi2,
3183 &omap34xx_l4_core__mcspi3,
3184 &omap34xx_l4_core__mcspi4,
3185 &omap3xxx_l4_wkup__counter_32k,
3602 NULL, 3186 NULL,
3603}; 3187};
3604 3188
3605/* GP-only hwmods */ 3189/* GP-only hwmod links */
3606static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { 3190static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3607 &omap3xxx_timer12_hwmod, 3191 &omap3xxx_l4_sec__timer12,
3608 NULL 3192 NULL
3609}; 3193};
3610 3194
3611/* 3430ES1-only hwmods */ 3195/* 3430ES1-only hwmod links */
3612static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { 3196static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3613 &omap3430es1_dss_core_hwmod, 3197 &omap3430es1_dss__l3,
3198 &omap3430es1_l4_core__dss,
3614 NULL 3199 NULL
3615}; 3200};
3616 3201
3617/* 3430ES2+-only hwmods */ 3202/* 3430ES2+-only hwmod links */
3618static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { 3203static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3619 &omap3xxx_dss_core_hwmod, 3204 &omap3xxx_dss__l3,
3620 &omap3xxx_usbhsotg_hwmod, 3205 &omap3xxx_l4_core__dss,
3621 &omap3xxx_usb_host_hs_hwmod, 3206 &omap3xxx_usbhsotg__l3,
3622 &omap3xxx_usb_tll_hs_hwmod, 3207 &omap3xxx_l4_core__usbhsotg,
3208 &omap3xxx_usb_host_hs__l3_main_2,
3209 &omap3xxx_l4_core__usb_host_hs,
3210 &omap3xxx_l4_core__usb_tll_hs,
3623 NULL 3211 NULL
3624}; 3212};
3625 3213
3626/* <= 3430ES3-only hwmods */ 3214/* <= 3430ES3-only hwmod links */
3627static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { 3215static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3628 &omap3xxx_pre_es3_mmc1_hwmod, 3216 &omap3xxx_l4_core__pre_es3_mmc1,
3629 &omap3xxx_pre_es3_mmc2_hwmod, 3217 &omap3xxx_l4_core__pre_es3_mmc2,
3630 NULL 3218 NULL
3631}; 3219};
3632 3220
3633/* 3430ES3+-only hwmods */ 3221/* 3430ES3+-only hwmod links */
3634static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { 3222static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3635 &omap3xxx_es3plus_mmc1_hwmod, 3223 &omap3xxx_l4_core__es3plus_mmc1,
3636 &omap3xxx_es3plus_mmc2_hwmod, 3224 &omap3xxx_l4_core__es3plus_mmc2,
3637 NULL 3225 NULL
3638}; 3226};
3639 3227
3640/* 34xx-only hwmods (all ES revisions) */ 3228/* 34xx-only hwmod links (all ES revisions) */
3641static __initdata struct omap_hwmod *omap34xx_hwmods[] = { 3229static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3642 &omap3xxx_iva_hwmod, 3230 &omap3xxx_l3__iva,
3643 &omap34xx_sr1_hwmod, 3231 &omap34xx_l4_core__sr1,
3644 &omap34xx_sr2_hwmod, 3232 &omap34xx_l4_core__sr2,
3645 &omap3xxx_mailbox_hwmod, 3233 &omap3xxx_l4_core__mailbox,
3234 &omap3xxx_l4_core__hdq1w,
3646 NULL 3235 NULL
3647}; 3236};
3648 3237
3649/* 36xx-only hwmods (all ES revisions) */ 3238/* 36xx-only hwmod links (all ES revisions) */
3650static __initdata struct omap_hwmod *omap36xx_hwmods[] = { 3239static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3651 &omap3xxx_iva_hwmod, 3240 &omap3xxx_l3__iva,
3652 &omap3xxx_uart4_hwmod, 3241 &omap36xx_l4_per__uart4,
3653 &omap3xxx_dss_core_hwmod, 3242 &omap3xxx_dss__l3,
3654 &omap36xx_sr1_hwmod, 3243 &omap3xxx_l4_core__dss,
3655 &omap36xx_sr2_hwmod, 3244 &omap36xx_l4_core__sr1,
3656 &omap3xxx_usbhsotg_hwmod, 3245 &omap36xx_l4_core__sr2,
3657 &omap3xxx_mailbox_hwmod, 3246 &omap3xxx_usbhsotg__l3,
3658 &omap3xxx_usb_host_hs_hwmod, 3247 &omap3xxx_l4_core__usbhsotg,
3659 &omap3xxx_usb_tll_hs_hwmod, 3248 &omap3xxx_l4_core__mailbox,
3660 &omap3xxx_es3plus_mmc1_hwmod, 3249 &omap3xxx_usb_host_hs__l3_main_2,
3661 &omap3xxx_es3plus_mmc2_hwmod, 3250 &omap3xxx_l4_core__usb_host_hs,
3251 &omap3xxx_l4_core__usb_tll_hs,
3252 &omap3xxx_l4_core__es3plus_mmc1,
3253 &omap3xxx_l4_core__es3plus_mmc2,
3254 &omap3xxx_l4_core__hdq1w,
3662 NULL 3255 NULL
3663}; 3256};
3664 3257
3665static __initdata struct omap_hwmod *am35xx_hwmods[] = { 3258static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3666 &omap3xxx_dss_core_hwmod, /* XXX ??? */ 3259 &omap3xxx_dss__l3,
3667 &am35xx_usbhsotg_hwmod, 3260 &omap3xxx_l4_core__dss,
3668 &am35xx_uart4_hwmod, 3261 &am35xx_usbhsotg__l3,
3669 &omap3xxx_usb_host_hs_hwmod, 3262 &am35xx_l4_core__usbhsotg,
3670 &omap3xxx_usb_tll_hs_hwmod, 3263 &am35xx_l4_core__uart4,
3671 &omap3xxx_es3plus_mmc1_hwmod, 3264 &omap3xxx_usb_host_hs__l3_main_2,
3672 &omap3xxx_es3plus_mmc2_hwmod, 3265 &omap3xxx_l4_core__usb_host_hs,
3266 &omap3xxx_l4_core__usb_tll_hs,
3267 &omap3xxx_l4_core__es3plus_mmc1,
3268 &omap3xxx_l4_core__es3plus_mmc2,
3673 NULL 3269 NULL
3674}; 3270};
3675 3271
3676static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { 3272static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3677 /* dss class */ 3273 &omap3xxx_l4_core__dss_dispc,
3678 &omap3xxx_dss_dispc_hwmod, 3274 &omap3xxx_l4_core__dss_dsi1,
3679 &omap3xxx_dss_dsi1_hwmod, 3275 &omap3xxx_l4_core__dss_rfbi,
3680 &omap3xxx_dss_rfbi_hwmod, 3276 &omap3xxx_l4_core__dss_venc,
3681 &omap3xxx_dss_venc_hwmod,
3682 NULL 3277 NULL
3683}; 3278};
3684 3279
3685int __init omap3xxx_hwmod_init(void) 3280int __init omap3xxx_hwmod_init(void)
3686{ 3281{
3687 int r; 3282 int r;
3688 struct omap_hwmod **h = NULL; 3283 struct omap_hwmod_ocp_if **h = NULL;
3689 unsigned int rev; 3284 unsigned int rev;
3690 3285
3691 /* Register hwmods common to all OMAP3 */ 3286 /* Register hwmod links common to all OMAP3 */
3692 r = omap_hwmod_register(omap3xxx_hwmods); 3287 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3693 if (r < 0) 3288 if (r < 0)
3694 return r; 3289 return r;
3695 3290
3696 /* Register GP-only hwmods. */ 3291 /* Register GP-only hwmod links. */
3697 if (omap_type() == OMAP2_DEVICE_TYPE_GP) { 3292 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3698 r = omap_hwmod_register(omap3xxx_gp_hwmods); 3293 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3699 if (r < 0) 3294 if (r < 0)
3700 return r; 3295 return r;
3701 } 3296 }
@@ -3703,43 +3298,43 @@ int __init omap3xxx_hwmod_init(void)
3703 rev = omap_rev(); 3298 rev = omap_rev();
3704 3299
3705 /* 3300 /*
3706 * Register hwmods common to individual OMAP3 families, all 3301 * Register hwmod links common to individual OMAP3 families, all
3707 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3302 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3708 * All possible revisions should be included in this conditional. 3303 * All possible revisions should be included in this conditional.
3709 */ 3304 */
3710 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3305 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3711 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3306 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3712 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3307 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3713 h = omap34xx_hwmods; 3308 h = omap34xx_hwmod_ocp_ifs;
3714 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { 3309 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3715 h = am35xx_hwmods; 3310 h = am35xx_hwmod_ocp_ifs;
3716 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3311 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3717 rev == OMAP3630_REV_ES1_2) { 3312 rev == OMAP3630_REV_ES1_2) {
3718 h = omap36xx_hwmods; 3313 h = omap36xx_hwmod_ocp_ifs;
3719 } else { 3314 } else {
3720 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3315 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3721 return -EINVAL; 3316 return -EINVAL;
3722 }; 3317 };
3723 3318
3724 r = omap_hwmod_register(h); 3319 r = omap_hwmod_register_links(h);
3725 if (r < 0) 3320 if (r < 0)
3726 return r; 3321 return r;
3727 3322
3728 /* 3323 /*
3729 * Register hwmods specific to certain ES levels of a 3324 * Register hwmod links specific to certain ES levels of a
3730 * particular family of silicon (e.g., 34xx ES1.0) 3325 * particular family of silicon (e.g., 34xx ES1.0)
3731 */ 3326 */
3732 h = NULL; 3327 h = NULL;
3733 if (rev == OMAP3430_REV_ES1_0) { 3328 if (rev == OMAP3430_REV_ES1_0) {
3734 h = omap3430es1_hwmods; 3329 h = omap3430es1_hwmod_ocp_ifs;
3735 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3330 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3736 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3331 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3737 rev == OMAP3430_REV_ES3_1_2) { 3332 rev == OMAP3430_REV_ES3_1_2) {
3738 h = omap3430es2plus_hwmods; 3333 h = omap3430es2plus_hwmod_ocp_ifs;
3739 }; 3334 };
3740 3335
3741 if (h) { 3336 if (h) {
3742 r = omap_hwmod_register(h); 3337 r = omap_hwmod_register_links(h);
3743 if (r < 0) 3338 if (r < 0)
3744 return r; 3339 return r;
3745 } 3340 }
@@ -3747,29 +3342,29 @@ int __init omap3xxx_hwmod_init(void)
3747 h = NULL; 3342 h = NULL;
3748 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3343 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3749 rev == OMAP3430_REV_ES2_1) { 3344 rev == OMAP3430_REV_ES2_1) {
3750 h = omap3430_pre_es3_hwmods; 3345 h = omap3430_pre_es3_hwmod_ocp_ifs;
3751 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3346 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3752 rev == OMAP3430_REV_ES3_1_2) { 3347 rev == OMAP3430_REV_ES3_1_2) {
3753 h = omap3430_es3plus_hwmods; 3348 h = omap3430_es3plus_hwmod_ocp_ifs;
3754 }; 3349 };
3755 3350
3756 if (h) 3351 if (h)
3757 r = omap_hwmod_register(h); 3352 r = omap_hwmod_register_links(h);
3758 if (r < 0) 3353 if (r < 0)
3759 return r; 3354 return r;
3760 3355
3761 /* 3356 /*
3762 * DSS code presumes that dss_core hwmod is handled first, 3357 * DSS code presumes that dss_core hwmod is handled first,
3763 * _before_ any other DSS related hwmods so register common 3358 * _before_ any other DSS related hwmods so register common
3764 * DSS hwmods last to ensure that dss_core is already registered. 3359 * DSS hwmod links last to ensure that dss_core is already
3765 * Otherwise some change things may happen, for ex. if dispc 3360 * registered. Otherwise some change things may happen, for
3766 * is handled before dss_core and DSS is enabled in bootloader 3361 * ex. if dispc is handled before dss_core and DSS is enabled
3767 * DIPSC will be reset with outputs enabled which sometimes leads 3362 * in bootloader DISPC will be reset with outputs enabled
3768 * to unrecoverable L3 error. 3363 * which sometimes leads to unrecoverable L3 error. XXX The
3769 * XXX The long-term fix to this is to ensure modules are set up 3364 * long-term fix to this is to ensure hwmods are set up in
3770 * in dependency order in the hwmod core code. 3365 * dependency order in the hwmod core code.
3771 */ 3366 */
3772 r = omap_hwmod_register(omap3xxx_dss_hwmods); 3367 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3773 3368
3774 return r; 3369 return r;
3775} 3370}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 6abc75753e42..950454a3fa31 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Hardware modules present on the OMAP44xx chips 2 * Hardware modules present on the OMAP44xx chips
3 * 3 *
4 * Copyright (C) 2009-2011 Texas Instruments, Inc. 4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley 7 * Paul Walmsley
@@ -44,41 +44,34 @@
44#define OMAP44XX_IRQ_GIC_START 32 44#define OMAP44XX_IRQ_GIC_START 32
45 45
46/* Base offset for all OMAP4 dma requests */ 46/* Base offset for all OMAP4 dma requests */
47#define OMAP44XX_DMA_REQ_START 1 47#define OMAP44XX_DMA_REQ_START 1
48
49/* Backward references (IPs with Bus Master capability) */
50static struct omap_hwmod omap44xx_aess_hwmod;
51static struct omap_hwmod omap44xx_dma_system_hwmod;
52static struct omap_hwmod omap44xx_dmm_hwmod;
53static struct omap_hwmod omap44xx_dsp_hwmod;
54static struct omap_hwmod omap44xx_dss_hwmod;
55static struct omap_hwmod omap44xx_emif_fw_hwmod;
56static struct omap_hwmod omap44xx_hsi_hwmod;
57static struct omap_hwmod omap44xx_ipu_hwmod;
58static struct omap_hwmod omap44xx_iss_hwmod;
59static struct omap_hwmod omap44xx_iva_hwmod;
60static struct omap_hwmod omap44xx_l3_instr_hwmod;
61static struct omap_hwmod omap44xx_l3_main_1_hwmod;
62static struct omap_hwmod omap44xx_l3_main_2_hwmod;
63static struct omap_hwmod omap44xx_l3_main_3_hwmod;
64static struct omap_hwmod omap44xx_l4_abe_hwmod;
65static struct omap_hwmod omap44xx_l4_cfg_hwmod;
66static struct omap_hwmod omap44xx_l4_per_hwmod;
67static struct omap_hwmod omap44xx_l4_wkup_hwmod;
68static struct omap_hwmod omap44xx_mmc1_hwmod;
69static struct omap_hwmod omap44xx_mmc2_hwmod;
70static struct omap_hwmod omap44xx_mpu_hwmod;
71static struct omap_hwmod omap44xx_mpu_private_hwmod;
72static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
73static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
74static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
75 48
76/* 49/*
77 * Interconnects omap_hwmod structures 50 * IP blocks
78 * hwmods that compose the global OMAP interconnect
79 */ 51 */
80 52
81/* 53/*
54 * 'c2c_target_fw' class
55 * instance(s): c2c_target_fw
56 */
57static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
58 .name = "c2c_target_fw",
59};
60
61/* c2c_target_fw */
62static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
63 .name = "c2c_target_fw",
64 .class = &omap44xx_c2c_target_fw_hwmod_class,
65 .clkdm_name = "d2d_clkdm",
66 .prcm = {
67 .omap4 = {
68 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
69 .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
70 },
71 },
72};
73
74/*
82 * 'dmm' class 75 * 'dmm' class
83 * instance(s): dmm 76 * instance(s): dmm
84 */ 77 */
@@ -92,51 +85,17 @@ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
92 { .irq = -1 } 85 { .irq = -1 }
93}; 86};
94 87
95/* l3_main_1 -> dmm */
96static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
97 .master = &omap44xx_l3_main_1_hwmod,
98 .slave = &omap44xx_dmm_hwmod,
99 .clk = "l3_div_ck",
100 .user = OCP_USER_SDMA,
101};
102
103static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
104 {
105 .pa_start = 0x4e000000,
106 .pa_end = 0x4e0007ff,
107 .flags = ADDR_TYPE_RT
108 },
109 { }
110};
111
112/* mpu -> dmm */
113static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
114 .master = &omap44xx_mpu_hwmod,
115 .slave = &omap44xx_dmm_hwmod,
116 .clk = "l3_div_ck",
117 .addr = omap44xx_dmm_addrs,
118 .user = OCP_USER_MPU,
119};
120
121/* dmm slave ports */
122static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
123 &omap44xx_l3_main_1__dmm,
124 &omap44xx_mpu__dmm,
125};
126
127static struct omap_hwmod omap44xx_dmm_hwmod = { 88static struct omap_hwmod omap44xx_dmm_hwmod = {
128 .name = "dmm", 89 .name = "dmm",
129 .class = &omap44xx_dmm_hwmod_class, 90 .class = &omap44xx_dmm_hwmod_class,
130 .clkdm_name = "l3_emif_clkdm", 91 .clkdm_name = "l3_emif_clkdm",
92 .mpu_irqs = omap44xx_dmm_irqs,
131 .prcm = { 93 .prcm = {
132 .omap4 = { 94 .omap4 = {
133 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, 95 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
134 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, 96 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
135 }, 97 },
136 }, 98 },
137 .slaves = omap44xx_dmm_slaves,
138 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
139 .mpu_irqs = omap44xx_dmm_irqs,
140}; 99};
141 100
142/* 101/*
@@ -148,38 +107,6 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
148}; 107};
149 108
150/* emif_fw */ 109/* emif_fw */
151/* dmm -> emif_fw */
152static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
153 .master = &omap44xx_dmm_hwmod,
154 .slave = &omap44xx_emif_fw_hwmod,
155 .clk = "l3_div_ck",
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
157};
158
159static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
160 {
161 .pa_start = 0x4a20c000,
162 .pa_end = 0x4a20c0ff,
163 .flags = ADDR_TYPE_RT
164 },
165 { }
166};
167
168/* l4_cfg -> emif_fw */
169static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
170 .master = &omap44xx_l4_cfg_hwmod,
171 .slave = &omap44xx_emif_fw_hwmod,
172 .clk = "l4_div_ck",
173 .addr = omap44xx_emif_fw_addrs,
174 .user = OCP_USER_MPU,
175};
176
177/* emif_fw slave ports */
178static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
179 &omap44xx_dmm__emif_fw,
180 &omap44xx_l4_cfg__emif_fw,
181};
182
183static struct omap_hwmod omap44xx_emif_fw_hwmod = { 110static struct omap_hwmod omap44xx_emif_fw_hwmod = {
184 .name = "emif_fw", 111 .name = "emif_fw",
185 .class = &omap44xx_emif_fw_hwmod_class, 112 .class = &omap44xx_emif_fw_hwmod_class,
@@ -190,8 +117,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
190 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, 117 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
191 }, 118 },
192 }, 119 },
193 .slaves = omap44xx_emif_fw_slaves,
194 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
195}; 120};
196 121
197/* 122/*
@@ -203,28 +128,6 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
203}; 128};
204 129
205/* l3_instr */ 130/* l3_instr */
206/* iva -> l3_instr */
207static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
208 .master = &omap44xx_iva_hwmod,
209 .slave = &omap44xx_l3_instr_hwmod,
210 .clk = "l3_div_ck",
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
212};
213
214/* l3_main_3 -> l3_instr */
215static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
216 .master = &omap44xx_l3_main_3_hwmod,
217 .slave = &omap44xx_l3_instr_hwmod,
218 .clk = "l3_div_ck",
219 .user = OCP_USER_MPU | OCP_USER_SDMA,
220};
221
222/* l3_instr slave ports */
223static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
224 &omap44xx_iva__l3_instr,
225 &omap44xx_l3_main_3__l3_instr,
226};
227
228static struct omap_hwmod omap44xx_l3_instr_hwmod = { 131static struct omap_hwmod omap44xx_l3_instr_hwmod = {
229 .name = "l3_instr", 132 .name = "l3_instr",
230 .class = &omap44xx_l3_hwmod_class, 133 .class = &omap44xx_l3_hwmod_class,
@@ -236,8 +139,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
236 .modulemode = MODULEMODE_HWCTRL, 139 .modulemode = MODULEMODE_HWCTRL,
237 }, 140 },
238 }, 141 },
239 .slaves = omap44xx_l3_instr_slaves,
240 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
241}; 142};
242 143
243/* l3_main_1 */ 144/* l3_main_1 */
@@ -247,83 +148,6 @@ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
247 { .irq = -1 } 148 { .irq = -1 }
248}; 149};
249 150
250/* dsp -> l3_main_1 */
251static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
252 .master = &omap44xx_dsp_hwmod,
253 .slave = &omap44xx_l3_main_1_hwmod,
254 .clk = "l3_div_ck",
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
256};
257
258/* dss -> l3_main_1 */
259static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
260 .master = &omap44xx_dss_hwmod,
261 .slave = &omap44xx_l3_main_1_hwmod,
262 .clk = "l3_div_ck",
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
264};
265
266/* l3_main_2 -> l3_main_1 */
267static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
268 .master = &omap44xx_l3_main_2_hwmod,
269 .slave = &omap44xx_l3_main_1_hwmod,
270 .clk = "l3_div_ck",
271 .user = OCP_USER_MPU | OCP_USER_SDMA,
272};
273
274/* l4_cfg -> l3_main_1 */
275static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
276 .master = &omap44xx_l4_cfg_hwmod,
277 .slave = &omap44xx_l3_main_1_hwmod,
278 .clk = "l4_div_ck",
279 .user = OCP_USER_MPU | OCP_USER_SDMA,
280};
281
282/* mmc1 -> l3_main_1 */
283static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
284 .master = &omap44xx_mmc1_hwmod,
285 .slave = &omap44xx_l3_main_1_hwmod,
286 .clk = "l3_div_ck",
287 .user = OCP_USER_MPU | OCP_USER_SDMA,
288};
289
290/* mmc2 -> l3_main_1 */
291static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
292 .master = &omap44xx_mmc2_hwmod,
293 .slave = &omap44xx_l3_main_1_hwmod,
294 .clk = "l3_div_ck",
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
296};
297
298static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
299 {
300 .pa_start = 0x44000000,
301 .pa_end = 0x44000fff,
302 .flags = ADDR_TYPE_RT
303 },
304 { }
305};
306
307/* mpu -> l3_main_1 */
308static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
309 .master = &omap44xx_mpu_hwmod,
310 .slave = &omap44xx_l3_main_1_hwmod,
311 .clk = "l3_div_ck",
312 .addr = omap44xx_l3_main_1_addrs,
313 .user = OCP_USER_MPU,
314};
315
316/* l3_main_1 slave ports */
317static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
318 &omap44xx_dsp__l3_main_1,
319 &omap44xx_dss__l3_main_1,
320 &omap44xx_l3_main_2__l3_main_1,
321 &omap44xx_l4_cfg__l3_main_1,
322 &omap44xx_mmc1__l3_main_1,
323 &omap44xx_mmc2__l3_main_1,
324 &omap44xx_mpu__l3_main_1,
325};
326
327static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 151static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
328 .name = "l3_main_1", 152 .name = "l3_main_1",
329 .class = &omap44xx_l3_hwmod_class, 153 .class = &omap44xx_l3_hwmod_class,
@@ -335,97 +159,9 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
335 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, 159 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
336 }, 160 },
337 }, 161 },
338 .slaves = omap44xx_l3_main_1_slaves,
339 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
340}; 162};
341 163
342/* l3_main_2 */ 164/* l3_main_2 */
343/* dma_system -> l3_main_2 */
344static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
345 .master = &omap44xx_dma_system_hwmod,
346 .slave = &omap44xx_l3_main_2_hwmod,
347 .clk = "l3_div_ck",
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
349};
350
351/* hsi -> l3_main_2 */
352static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
353 .master = &omap44xx_hsi_hwmod,
354 .slave = &omap44xx_l3_main_2_hwmod,
355 .clk = "l3_div_ck",
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
357};
358
359/* ipu -> l3_main_2 */
360static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
361 .master = &omap44xx_ipu_hwmod,
362 .slave = &omap44xx_l3_main_2_hwmod,
363 .clk = "l3_div_ck",
364 .user = OCP_USER_MPU | OCP_USER_SDMA,
365};
366
367/* iss -> l3_main_2 */
368static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
369 .master = &omap44xx_iss_hwmod,
370 .slave = &omap44xx_l3_main_2_hwmod,
371 .clk = "l3_div_ck",
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
373};
374
375/* iva -> l3_main_2 */
376static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
377 .master = &omap44xx_iva_hwmod,
378 .slave = &omap44xx_l3_main_2_hwmod,
379 .clk = "l3_div_ck",
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
381};
382
383static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
384 {
385 .pa_start = 0x44800000,
386 .pa_end = 0x44801fff,
387 .flags = ADDR_TYPE_RT
388 },
389 { }
390};
391
392/* l3_main_1 -> l3_main_2 */
393static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
394 .master = &omap44xx_l3_main_1_hwmod,
395 .slave = &omap44xx_l3_main_2_hwmod,
396 .clk = "l3_div_ck",
397 .addr = omap44xx_l3_main_2_addrs,
398 .user = OCP_USER_MPU,
399};
400
401/* l4_cfg -> l3_main_2 */
402static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
403 .master = &omap44xx_l4_cfg_hwmod,
404 .slave = &omap44xx_l3_main_2_hwmod,
405 .clk = "l4_div_ck",
406 .user = OCP_USER_MPU | OCP_USER_SDMA,
407};
408
409/* usb_otg_hs -> l3_main_2 */
410static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
411 .master = &omap44xx_usb_otg_hs_hwmod,
412 .slave = &omap44xx_l3_main_2_hwmod,
413 .clk = "l3_div_ck",
414 .user = OCP_USER_MPU | OCP_USER_SDMA,
415};
416
417/* l3_main_2 slave ports */
418static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
419 &omap44xx_dma_system__l3_main_2,
420 &omap44xx_hsi__l3_main_2,
421 &omap44xx_ipu__l3_main_2,
422 &omap44xx_iss__l3_main_2,
423 &omap44xx_iva__l3_main_2,
424 &omap44xx_l3_main_1__l3_main_2,
425 &omap44xx_l4_cfg__l3_main_2,
426 &omap44xx_usb_otg_hs__l3_main_2,
427};
428
429static struct omap_hwmod omap44xx_l3_main_2_hwmod = { 165static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
430 .name = "l3_main_2", 166 .name = "l3_main_2",
431 .class = &omap44xx_l3_hwmod_class, 167 .class = &omap44xx_l3_hwmod_class,
@@ -436,52 +172,9 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
436 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, 172 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
437 }, 173 },
438 }, 174 },
439 .slaves = omap44xx_l3_main_2_slaves,
440 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
441}; 175};
442 176
443/* l3_main_3 */ 177/* l3_main_3 */
444static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
445 {
446 .pa_start = 0x45000000,
447 .pa_end = 0x45000fff,
448 .flags = ADDR_TYPE_RT
449 },
450 { }
451};
452
453/* l3_main_1 -> l3_main_3 */
454static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
455 .master = &omap44xx_l3_main_1_hwmod,
456 .slave = &omap44xx_l3_main_3_hwmod,
457 .clk = "l3_div_ck",
458 .addr = omap44xx_l3_main_3_addrs,
459 .user = OCP_USER_MPU,
460};
461
462/* l3_main_2 -> l3_main_3 */
463static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
464 .master = &omap44xx_l3_main_2_hwmod,
465 .slave = &omap44xx_l3_main_3_hwmod,
466 .clk = "l3_div_ck",
467 .user = OCP_USER_MPU | OCP_USER_SDMA,
468};
469
470/* l4_cfg -> l3_main_3 */
471static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
472 .master = &omap44xx_l4_cfg_hwmod,
473 .slave = &omap44xx_l3_main_3_hwmod,
474 .clk = "l4_div_ck",
475 .user = OCP_USER_MPU | OCP_USER_SDMA,
476};
477
478/* l3_main_3 slave ports */
479static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
480 &omap44xx_l3_main_1__l3_main_3,
481 &omap44xx_l3_main_2__l3_main_3,
482 &omap44xx_l4_cfg__l3_main_3,
483};
484
485static struct omap_hwmod omap44xx_l3_main_3_hwmod = { 178static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
486 .name = "l3_main_3", 179 .name = "l3_main_3",
487 .class = &omap44xx_l3_hwmod_class, 180 .class = &omap44xx_l3_hwmod_class,
@@ -493,8 +186,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
493 .modulemode = MODULEMODE_HWCTRL, 186 .modulemode = MODULEMODE_HWCTRL,
494 }, 187 },
495 }, 188 },
496 .slaves = omap44xx_l3_main_3_slaves,
497 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
498}; 189};
499 190
500/* 191/*
@@ -506,46 +197,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
506}; 197};
507 198
508/* l4_abe */ 199/* l4_abe */
509/* aess -> l4_abe */
510static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
511 .master = &omap44xx_aess_hwmod,
512 .slave = &omap44xx_l4_abe_hwmod,
513 .clk = "ocp_abe_iclk",
514 .user = OCP_USER_MPU | OCP_USER_SDMA,
515};
516
517/* dsp -> l4_abe */
518static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
519 .master = &omap44xx_dsp_hwmod,
520 .slave = &omap44xx_l4_abe_hwmod,
521 .clk = "ocp_abe_iclk",
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
523};
524
525/* l3_main_1 -> l4_abe */
526static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
527 .master = &omap44xx_l3_main_1_hwmod,
528 .slave = &omap44xx_l4_abe_hwmod,
529 .clk = "l3_div_ck",
530 .user = OCP_USER_MPU | OCP_USER_SDMA,
531};
532
533/* mpu -> l4_abe */
534static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
535 .master = &omap44xx_mpu_hwmod,
536 .slave = &omap44xx_l4_abe_hwmod,
537 .clk = "ocp_abe_iclk",
538 .user = OCP_USER_MPU | OCP_USER_SDMA,
539};
540
541/* l4_abe slave ports */
542static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
543 &omap44xx_aess__l4_abe,
544 &omap44xx_dsp__l4_abe,
545 &omap44xx_l3_main_1__l4_abe,
546 &omap44xx_mpu__l4_abe,
547};
548
549static struct omap_hwmod omap44xx_l4_abe_hwmod = { 200static struct omap_hwmod omap44xx_l4_abe_hwmod = {
550 .name = "l4_abe", 201 .name = "l4_abe",
551 .class = &omap44xx_l4_hwmod_class, 202 .class = &omap44xx_l4_hwmod_class,
@@ -555,24 +206,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
555 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, 206 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
556 }, 207 },
557 }, 208 },
558 .slaves = omap44xx_l4_abe_slaves,
559 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
560}; 209};
561 210
562/* l4_cfg */ 211/* l4_cfg */
563/* l3_main_1 -> l4_cfg */
564static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
565 .master = &omap44xx_l3_main_1_hwmod,
566 .slave = &omap44xx_l4_cfg_hwmod,
567 .clk = "l3_div_ck",
568 .user = OCP_USER_MPU | OCP_USER_SDMA,
569};
570
571/* l4_cfg slave ports */
572static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
573 &omap44xx_l3_main_1__l4_cfg,
574};
575
576static struct omap_hwmod omap44xx_l4_cfg_hwmod = { 212static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
577 .name = "l4_cfg", 213 .name = "l4_cfg",
578 .class = &omap44xx_l4_hwmod_class, 214 .class = &omap44xx_l4_hwmod_class,
@@ -583,24 +219,9 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
583 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, 219 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
584 }, 220 },
585 }, 221 },
586 .slaves = omap44xx_l4_cfg_slaves,
587 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
588}; 222};
589 223
590/* l4_per */ 224/* l4_per */
591/* l3_main_2 -> l4_per */
592static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
593 .master = &omap44xx_l3_main_2_hwmod,
594 .slave = &omap44xx_l4_per_hwmod,
595 .clk = "l3_div_ck",
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
597};
598
599/* l4_per slave ports */
600static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
601 &omap44xx_l3_main_2__l4_per,
602};
603
604static struct omap_hwmod omap44xx_l4_per_hwmod = { 225static struct omap_hwmod omap44xx_l4_per_hwmod = {
605 .name = "l4_per", 226 .name = "l4_per",
606 .class = &omap44xx_l4_hwmod_class, 227 .class = &omap44xx_l4_hwmod_class,
@@ -611,24 +232,9 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
611 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, 232 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
612 }, 233 },
613 }, 234 },
614 .slaves = omap44xx_l4_per_slaves,
615 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
616}; 235};
617 236
618/* l4_wkup */ 237/* l4_wkup */
619/* l4_cfg -> l4_wkup */
620static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
621 .master = &omap44xx_l4_cfg_hwmod,
622 .slave = &omap44xx_l4_wkup_hwmod,
623 .clk = "l4_div_ck",
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
625};
626
627/* l4_wkup slave ports */
628static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
629 &omap44xx_l4_cfg__l4_wkup,
630};
631
632static struct omap_hwmod omap44xx_l4_wkup_hwmod = { 238static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
633 .name = "l4_wkup", 239 .name = "l4_wkup",
634 .class = &omap44xx_l4_hwmod_class, 240 .class = &omap44xx_l4_hwmod_class,
@@ -639,8 +245,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
639 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, 245 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
640 }, 246 },
641 }, 247 },
642 .slaves = omap44xx_l4_wkup_slaves,
643 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
644}; 248};
645 249
646/* 250/*
@@ -652,25 +256,32 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
652}; 256};
653 257
654/* mpu_private */ 258/* mpu_private */
655/* mpu -> mpu_private */
656static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
657 .master = &omap44xx_mpu_hwmod,
658 .slave = &omap44xx_mpu_private_hwmod,
659 .clk = "l3_div_ck",
660 .user = OCP_USER_MPU | OCP_USER_SDMA,
661};
662
663/* mpu_private slave ports */
664static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
665 &omap44xx_mpu__mpu_private,
666};
667
668static struct omap_hwmod omap44xx_mpu_private_hwmod = { 259static struct omap_hwmod omap44xx_mpu_private_hwmod = {
669 .name = "mpu_private", 260 .name = "mpu_private",
670 .class = &omap44xx_mpu_bus_hwmod_class, 261 .class = &omap44xx_mpu_bus_hwmod_class,
671 .clkdm_name = "mpuss_clkdm", 262 .clkdm_name = "mpuss_clkdm",
672 .slaves = omap44xx_mpu_private_slaves, 263};
673 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), 264
265/*
266 * 'ocp_wp_noc' class
267 * instance(s): ocp_wp_noc
268 */
269static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
270 .name = "ocp_wp_noc",
271};
272
273/* ocp_wp_noc */
274static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
275 .name = "ocp_wp_noc",
276 .class = &omap44xx_ocp_wp_noc_hwmod_class,
277 .clkdm_name = "l3_instr_clkdm",
278 .prcm = {
279 .omap4 = {
280 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
281 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
282 .modulemode = MODULEMODE_HWCTRL,
283 },
284 },
674}; 285};
675 286
676/* 287/*
@@ -681,41 +292,7 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
681 * - They still need to be validated with the driver 292 * - They still need to be validated with the driver
682 * properly adapted to omap_hwmod / omap_device 293 * properly adapted to omap_hwmod / omap_device
683 * 294 *
684 * c2c 295 * usim
685 * c2c_target_fw
686 * cm_core
687 * cm_core_aon
688 * ctrl_module_core
689 * ctrl_module_pad_core
690 * ctrl_module_pad_wkup
691 * ctrl_module_wkup
692 * debugss
693 * efuse_ctrl_cust
694 * efuse_ctrl_std
695 * elm
696 * emif1
697 * emif2
698 * fdif
699 * gpmc
700 * gpu
701 * hdq1w
702 * mcasp
703 * mpu_c0
704 * mpu_c1
705 * ocmc_ram
706 * ocp2scp_usb_phy
707 * ocp_wp_noc
708 * prcm_mpu
709 * prm
710 * scrm
711 * sl2if
712 * slimbus1
713 * slimbus2
714 * usb_host_fs
715 * usb_host_hs
716 * usb_phy_cm
717 * usb_tll_hs
718 * usim
719 */ 296 */
720 297
721/* 298/*
@@ -756,53 +333,6 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
756 { .dma_req = -1 } 333 { .dma_req = -1 }
757}; 334};
758 335
759/* aess master ports */
760static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
761 &omap44xx_aess__l4_abe,
762};
763
764static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
765 {
766 .pa_start = 0x401f1000,
767 .pa_end = 0x401f13ff,
768 .flags = ADDR_TYPE_RT
769 },
770 { }
771};
772
773/* l4_abe -> aess */
774static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
775 .master = &omap44xx_l4_abe_hwmod,
776 .slave = &omap44xx_aess_hwmod,
777 .clk = "ocp_abe_iclk",
778 .addr = omap44xx_aess_addrs,
779 .user = OCP_USER_MPU,
780};
781
782static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
783 {
784 .pa_start = 0x490f1000,
785 .pa_end = 0x490f13ff,
786 .flags = ADDR_TYPE_RT
787 },
788 { }
789};
790
791/* l4_abe -> aess (dma) */
792static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
793 .master = &omap44xx_l4_abe_hwmod,
794 .slave = &omap44xx_aess_hwmod,
795 .clk = "ocp_abe_iclk",
796 .addr = omap44xx_aess_dma_addrs,
797 .user = OCP_USER_SDMA,
798};
799
800/* aess slave ports */
801static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
802 &omap44xx_l4_abe__aess,
803 &omap44xx_l4_abe__aess_dma,
804};
805
806static struct omap_hwmod omap44xx_aess_hwmod = { 336static struct omap_hwmod omap44xx_aess_hwmod = {
807 .name = "aess", 337 .name = "aess",
808 .class = &omap44xx_aess_hwmod_class, 338 .class = &omap44xx_aess_hwmod_class,
@@ -817,37 +347,41 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
817 .modulemode = MODULEMODE_SWCTRL, 347 .modulemode = MODULEMODE_SWCTRL,
818 }, 348 },
819 }, 349 },
820 .slaves = omap44xx_aess_slaves,
821 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
822 .masters = omap44xx_aess_masters,
823 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
824}; 350};
825 351
826/* 352/*
827 * 'bandgap' class 353 * 'c2c' class
828 * bangap reference for ldo regulators 354 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
355 * soc
829 */ 356 */
830 357
831static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { 358static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
832 .name = "bandgap", 359 .name = "c2c",
833}; 360};
834 361
835/* bandgap */ 362/* c2c */
836static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { 363static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
837 { .role = "fclk", .clk = "bandgap_fclk" }, 364 { .irq = 88 + OMAP44XX_IRQ_GIC_START },
365 { .irq = -1 }
838}; 366};
839 367
840static struct omap_hwmod omap44xx_bandgap_hwmod = { 368static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
841 .name = "bandgap", 369 { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
842 .class = &omap44xx_bandgap_hwmod_class, 370 { .dma_req = -1 }
843 .clkdm_name = "l4_wkup_clkdm", 371};
372
373static struct omap_hwmod omap44xx_c2c_hwmod = {
374 .name = "c2c",
375 .class = &omap44xx_c2c_hwmod_class,
376 .clkdm_name = "d2d_clkdm",
377 .mpu_irqs = omap44xx_c2c_irqs,
378 .sdma_reqs = omap44xx_c2c_sdma_reqs,
844 .prcm = { 379 .prcm = {
845 .omap4 = { 380 .omap4 = {
846 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET, 381 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
382 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
847 }, 383 },
848 }, 384 },
849 .opt_clks = bandgap_opt_clks,
850 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
851}; 385};
852 386
853/* 387/*
@@ -870,30 +404,6 @@ static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
870}; 404};
871 405
872/* counter_32k */ 406/* counter_32k */
873static struct omap_hwmod omap44xx_counter_32k_hwmod;
874static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
875 {
876 .pa_start = 0x4a304000,
877 .pa_end = 0x4a30401f,
878 .flags = ADDR_TYPE_RT
879 },
880 { }
881};
882
883/* l4_wkup -> counter_32k */
884static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
885 .master = &omap44xx_l4_wkup_hwmod,
886 .slave = &omap44xx_counter_32k_hwmod,
887 .clk = "l4_wkup_clk_mux_ck",
888 .addr = omap44xx_counter_32k_addrs,
889 .user = OCP_USER_MPU | OCP_USER_SDMA,
890};
891
892/* counter_32k slave ports */
893static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
894 &omap44xx_l4_wkup__counter_32k,
895};
896
897static struct omap_hwmod omap44xx_counter_32k_hwmod = { 407static struct omap_hwmod omap44xx_counter_32k_hwmod = {
898 .name = "counter_32k", 408 .name = "counter_32k",
899 .class = &omap44xx_counter_hwmod_class, 409 .class = &omap44xx_counter_hwmod_class,
@@ -906,8 +416,83 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
906 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, 416 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
907 }, 417 },
908 }, 418 },
909 .slaves = omap44xx_counter_32k_slaves, 419};
910 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), 420
421/*
422 * 'ctrl_module' class
423 * attila core control module + core pad control module + wkup pad control
424 * module + attila wkup control module
425 */
426
427static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
428 .rev_offs = 0x0000,
429 .sysc_offs = 0x0010,
430 .sysc_flags = SYSC_HAS_SIDLEMODE,
431 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
432 SIDLE_SMART_WKUP),
433 .sysc_fields = &omap_hwmod_sysc_type2,
434};
435
436static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
437 .name = "ctrl_module",
438 .sysc = &omap44xx_ctrl_module_sysc,
439};
440
441/* ctrl_module_core */
442static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
443 { .irq = 8 + OMAP44XX_IRQ_GIC_START },
444 { .irq = -1 }
445};
446
447static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
448 .name = "ctrl_module_core",
449 .class = &omap44xx_ctrl_module_hwmod_class,
450 .clkdm_name = "l4_cfg_clkdm",
451 .mpu_irqs = omap44xx_ctrl_module_core_irqs,
452};
453
454/* ctrl_module_pad_core */
455static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
456 .name = "ctrl_module_pad_core",
457 .class = &omap44xx_ctrl_module_hwmod_class,
458 .clkdm_name = "l4_cfg_clkdm",
459};
460
461/* ctrl_module_wkup */
462static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
463 .name = "ctrl_module_wkup",
464 .class = &omap44xx_ctrl_module_hwmod_class,
465 .clkdm_name = "l4_wkup_clkdm",
466};
467
468/* ctrl_module_pad_wkup */
469static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
470 .name = "ctrl_module_pad_wkup",
471 .class = &omap44xx_ctrl_module_hwmod_class,
472 .clkdm_name = "l4_wkup_clkdm",
473};
474
475/*
476 * 'debugss' class
477 * debug and emulation sub system
478 */
479
480static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
481 .name = "debugss",
482};
483
484/* debugss */
485static struct omap_hwmod omap44xx_debugss_hwmod = {
486 .name = "debugss",
487 .class = &omap44xx_debugss_hwmod_class,
488 .clkdm_name = "emu_sys_clkdm",
489 .main_clk = "trace_clk_div_ck",
490 .prcm = {
491 .omap4 = {
492 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
493 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
494 },
495 },
911}; 496};
912 497
913/* 498/*
@@ -950,34 +535,6 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
950 { .irq = -1 } 535 { .irq = -1 }
951}; 536};
952 537
953/* dma_system master ports */
954static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
955 &omap44xx_dma_system__l3_main_2,
956};
957
958static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
959 {
960 .pa_start = 0x4a056000,
961 .pa_end = 0x4a056fff,
962 .flags = ADDR_TYPE_RT
963 },
964 { }
965};
966
967/* l4_cfg -> dma_system */
968static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
969 .master = &omap44xx_l4_cfg_hwmod,
970 .slave = &omap44xx_dma_system_hwmod,
971 .clk = "l4_div_ck",
972 .addr = omap44xx_dma_system_addrs,
973 .user = OCP_USER_MPU | OCP_USER_SDMA,
974};
975
976/* dma_system slave ports */
977static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
978 &omap44xx_l4_cfg__dma_system,
979};
980
981static struct omap_hwmod omap44xx_dma_system_hwmod = { 538static struct omap_hwmod omap44xx_dma_system_hwmod = {
982 .name = "dma_system", 539 .name = "dma_system",
983 .class = &omap44xx_dma_hwmod_class, 540 .class = &omap44xx_dma_hwmod_class,
@@ -991,10 +548,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
991 }, 548 },
992 }, 549 },
993 .dev_attr = &dma_dev_attr, 550 .dev_attr = &dma_dev_attr,
994 .slaves = omap44xx_dma_system_slaves,
995 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
996 .masters = omap44xx_dma_system_masters,
997 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
998}; 551};
999 552
1000/* 553/*
@@ -1018,7 +571,6 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1018}; 571};
1019 572
1020/* dmic */ 573/* dmic */
1021static struct omap_hwmod omap44xx_dmic_hwmod;
1022static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { 574static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1023 { .irq = 114 + OMAP44XX_IRQ_GIC_START }, 575 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1024 { .irq = -1 } 576 { .irq = -1 }
@@ -1029,50 +581,6 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1029 { .dma_req = -1 } 581 { .dma_req = -1 }
1030}; 582};
1031 583
1032static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1033 {
1034 .name = "mpu",
1035 .pa_start = 0x4012e000,
1036 .pa_end = 0x4012e07f,
1037 .flags = ADDR_TYPE_RT
1038 },
1039 { }
1040};
1041
1042/* l4_abe -> dmic */
1043static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1044 .master = &omap44xx_l4_abe_hwmod,
1045 .slave = &omap44xx_dmic_hwmod,
1046 .clk = "ocp_abe_iclk",
1047 .addr = omap44xx_dmic_addrs,
1048 .user = OCP_USER_MPU,
1049};
1050
1051static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1052 {
1053 .name = "dma",
1054 .pa_start = 0x4902e000,
1055 .pa_end = 0x4902e07f,
1056 .flags = ADDR_TYPE_RT
1057 },
1058 { }
1059};
1060
1061/* l4_abe -> dmic (dma) */
1062static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1063 .master = &omap44xx_l4_abe_hwmod,
1064 .slave = &omap44xx_dmic_hwmod,
1065 .clk = "ocp_abe_iclk",
1066 .addr = omap44xx_dmic_dma_addrs,
1067 .user = OCP_USER_SDMA,
1068};
1069
1070/* dmic slave ports */
1071static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1072 &omap44xx_l4_abe__dmic,
1073 &omap44xx_l4_abe__dmic_dma,
1074};
1075
1076static struct omap_hwmod omap44xx_dmic_hwmod = { 584static struct omap_hwmod omap44xx_dmic_hwmod = {
1077 .name = "dmic", 585 .name = "dmic",
1078 .class = &omap44xx_dmic_hwmod_class, 586 .class = &omap44xx_dmic_hwmod_class,
@@ -1087,8 +595,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
1087 .modulemode = MODULEMODE_SWCTRL, 595 .modulemode = MODULEMODE_SWCTRL,
1088 }, 596 },
1089 }, 597 },
1090 .slaves = omap44xx_dmic_slaves,
1091 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1092}; 598};
1093 599
1094/* 600/*
@@ -1107,53 +613,8 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1107}; 613};
1108 614
1109static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { 615static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1110 { .name = "mmu_cache", .rst_shift = 1 },
1111};
1112
1113static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1114 { .name = "dsp", .rst_shift = 0 }, 616 { .name = "dsp", .rst_shift = 0 },
1115}; 617 { .name = "mmu_cache", .rst_shift = 1 },
1116
1117/* dsp -> iva */
1118static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1119 .master = &omap44xx_dsp_hwmod,
1120 .slave = &omap44xx_iva_hwmod,
1121 .clk = "dpll_iva_m5x2_ck",
1122};
1123
1124/* dsp master ports */
1125static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1126 &omap44xx_dsp__l3_main_1,
1127 &omap44xx_dsp__l4_abe,
1128 &omap44xx_dsp__iva,
1129};
1130
1131/* l4_cfg -> dsp */
1132static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1133 .master = &omap44xx_l4_cfg_hwmod,
1134 .slave = &omap44xx_dsp_hwmod,
1135 .clk = "l4_div_ck",
1136 .user = OCP_USER_MPU | OCP_USER_SDMA,
1137};
1138
1139/* dsp slave ports */
1140static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1141 &omap44xx_l4_cfg__dsp,
1142};
1143
1144/* Pseudo hwmod for reset control purpose only */
1145static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1146 .name = "dsp_c0",
1147 .class = &omap44xx_dsp_hwmod_class,
1148 .clkdm_name = "tesla_clkdm",
1149 .flags = HWMOD_INIT_NO_RESET,
1150 .rst_lines = omap44xx_dsp_c0_resets,
1151 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1152 .prcm = {
1153 .omap4 = {
1154 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1155 },
1156 },
1157}; 618};
1158 619
1159static struct omap_hwmod omap44xx_dsp_hwmod = { 620static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1172,10 +633,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
1172 .modulemode = MODULEMODE_HWCTRL, 633 .modulemode = MODULEMODE_HWCTRL,
1173 }, 634 },
1174 }, 635 },
1175 .slaves = omap44xx_dsp_slaves,
1176 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1177 .masters = omap44xx_dsp_masters,
1178 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1179}; 636};
1180 637
1181/* 638/*
@@ -1196,53 +653,6 @@ static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1196}; 653};
1197 654
1198/* dss */ 655/* dss */
1199/* dss master ports */
1200static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1201 &omap44xx_dss__l3_main_1,
1202};
1203
1204static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1205 {
1206 .pa_start = 0x58000000,
1207 .pa_end = 0x5800007f,
1208 .flags = ADDR_TYPE_RT
1209 },
1210 { }
1211};
1212
1213/* l3_main_2 -> dss */
1214static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1215 .master = &omap44xx_l3_main_2_hwmod,
1216 .slave = &omap44xx_dss_hwmod,
1217 .clk = "dss_fck",
1218 .addr = omap44xx_dss_dma_addrs,
1219 .user = OCP_USER_SDMA,
1220};
1221
1222static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1223 {
1224 .pa_start = 0x48040000,
1225 .pa_end = 0x4804007f,
1226 .flags = ADDR_TYPE_RT
1227 },
1228 { }
1229};
1230
1231/* l4_per -> dss */
1232static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1233 .master = &omap44xx_l4_per_hwmod,
1234 .slave = &omap44xx_dss_hwmod,
1235 .clk = "l4_div_ck",
1236 .addr = omap44xx_dss_addrs,
1237 .user = OCP_USER_MPU,
1238};
1239
1240/* dss slave ports */
1241static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1242 &omap44xx_l3_main_2__dss,
1243 &omap44xx_l4_per__dss,
1244};
1245
1246static struct omap_hwmod_opt_clk dss_opt_clks[] = { 656static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1247 { .role = "sys_clk", .clk = "dss_sys_clk" }, 657 { .role = "sys_clk", .clk = "dss_sys_clk" },
1248 { .role = "tv_clk", .clk = "dss_tv_clk" }, 658 { .role = "tv_clk", .clk = "dss_tv_clk" },
@@ -1263,10 +673,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
1263 }, 673 },
1264 .opt_clks = dss_opt_clks, 674 .opt_clks = dss_opt_clks,
1265 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 675 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1266 .slaves = omap44xx_dss_slaves,
1267 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1268 .masters = omap44xx_dss_masters,
1269 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1270}; 676};
1271 677
1272/* 678/*
@@ -1293,7 +699,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1293}; 699};
1294 700
1295/* dss_dispc */ 701/* dss_dispc */
1296static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1297static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { 702static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1298 { .irq = 25 + OMAP44XX_IRQ_GIC_START }, 703 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1299 { .irq = -1 } 704 { .irq = -1 }
@@ -1304,53 +709,11 @@ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1304 { .dma_req = -1 } 709 { .dma_req = -1 }
1305}; 710};
1306 711
1307static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1308 {
1309 .pa_start = 0x58001000,
1310 .pa_end = 0x58001fff,
1311 .flags = ADDR_TYPE_RT
1312 },
1313 { }
1314};
1315
1316/* l3_main_2 -> dss_dispc */
1317static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1318 .master = &omap44xx_l3_main_2_hwmod,
1319 .slave = &omap44xx_dss_dispc_hwmod,
1320 .clk = "dss_fck",
1321 .addr = omap44xx_dss_dispc_dma_addrs,
1322 .user = OCP_USER_SDMA,
1323};
1324
1325static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1326 {
1327 .pa_start = 0x48041000,
1328 .pa_end = 0x48041fff,
1329 .flags = ADDR_TYPE_RT
1330 },
1331 { }
1332};
1333
1334static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { 712static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1335 .manager_count = 3, 713 .manager_count = 3,
1336 .has_framedonetv_irq = 1 714 .has_framedonetv_irq = 1
1337}; 715};
1338 716
1339/* l4_per -> dss_dispc */
1340static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1341 .master = &omap44xx_l4_per_hwmod,
1342 .slave = &omap44xx_dss_dispc_hwmod,
1343 .clk = "l4_div_ck",
1344 .addr = omap44xx_dss_dispc_addrs,
1345 .user = OCP_USER_MPU,
1346};
1347
1348/* dss_dispc slave ports */
1349static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1350 &omap44xx_l3_main_2__dss_dispc,
1351 &omap44xx_l4_per__dss_dispc,
1352};
1353
1354static struct omap_hwmod omap44xx_dss_dispc_hwmod = { 717static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1355 .name = "dss_dispc", 718 .name = "dss_dispc",
1356 .class = &omap44xx_dispc_hwmod_class, 719 .class = &omap44xx_dispc_hwmod_class,
@@ -1364,8 +727,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1364 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 727 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1365 }, 728 },
1366 }, 729 },
1367 .slaves = omap44xx_dss_dispc_slaves,
1368 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1369 .dev_attr = &omap44xx_dss_dispc_dev_attr 730 .dev_attr = &omap44xx_dss_dispc_dev_attr
1370}; 731};
1371 732
@@ -1391,7 +752,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1391}; 752};
1392 753
1393/* dss_dsi1 */ 754/* dss_dsi1 */
1394static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1395static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { 755static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1396 { .irq = 53 + OMAP44XX_IRQ_GIC_START }, 756 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1397 { .irq = -1 } 757 { .irq = -1 }
@@ -1402,48 +762,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1402 { .dma_req = -1 } 762 { .dma_req = -1 }
1403}; 763};
1404 764
1405static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1406 {
1407 .pa_start = 0x58004000,
1408 .pa_end = 0x580041ff,
1409 .flags = ADDR_TYPE_RT
1410 },
1411 { }
1412};
1413
1414/* l3_main_2 -> dss_dsi1 */
1415static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1416 .master = &omap44xx_l3_main_2_hwmod,
1417 .slave = &omap44xx_dss_dsi1_hwmod,
1418 .clk = "dss_fck",
1419 .addr = omap44xx_dss_dsi1_dma_addrs,
1420 .user = OCP_USER_SDMA,
1421};
1422
1423static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1424 {
1425 .pa_start = 0x48044000,
1426 .pa_end = 0x480441ff,
1427 .flags = ADDR_TYPE_RT
1428 },
1429 { }
1430};
1431
1432/* l4_per -> dss_dsi1 */
1433static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1434 .master = &omap44xx_l4_per_hwmod,
1435 .slave = &omap44xx_dss_dsi1_hwmod,
1436 .clk = "l4_div_ck",
1437 .addr = omap44xx_dss_dsi1_addrs,
1438 .user = OCP_USER_MPU,
1439};
1440
1441/* dss_dsi1 slave ports */
1442static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1443 &omap44xx_l3_main_2__dss_dsi1,
1444 &omap44xx_l4_per__dss_dsi1,
1445};
1446
1447static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 765static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1448 { .role = "sys_clk", .clk = "dss_sys_clk" }, 766 { .role = "sys_clk", .clk = "dss_sys_clk" },
1449}; 767};
@@ -1463,12 +781,9 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1463 }, 781 },
1464 .opt_clks = dss_dsi1_opt_clks, 782 .opt_clks = dss_dsi1_opt_clks,
1465 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 783 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1466 .slaves = omap44xx_dss_dsi1_slaves,
1467 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1468}; 784};
1469 785
1470/* dss_dsi2 */ 786/* dss_dsi2 */
1471static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1472static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { 787static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1473 { .irq = 84 + OMAP44XX_IRQ_GIC_START }, 788 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1474 { .irq = -1 } 789 { .irq = -1 }
@@ -1479,48 +794,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1479 { .dma_req = -1 } 794 { .dma_req = -1 }
1480}; 795};
1481 796
1482static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1483 {
1484 .pa_start = 0x58005000,
1485 .pa_end = 0x580051ff,
1486 .flags = ADDR_TYPE_RT
1487 },
1488 { }
1489};
1490
1491/* l3_main_2 -> dss_dsi2 */
1492static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1493 .master = &omap44xx_l3_main_2_hwmod,
1494 .slave = &omap44xx_dss_dsi2_hwmod,
1495 .clk = "dss_fck",
1496 .addr = omap44xx_dss_dsi2_dma_addrs,
1497 .user = OCP_USER_SDMA,
1498};
1499
1500static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1501 {
1502 .pa_start = 0x48045000,
1503 .pa_end = 0x480451ff,
1504 .flags = ADDR_TYPE_RT
1505 },
1506 { }
1507};
1508
1509/* l4_per -> dss_dsi2 */
1510static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1511 .master = &omap44xx_l4_per_hwmod,
1512 .slave = &omap44xx_dss_dsi2_hwmod,
1513 .clk = "l4_div_ck",
1514 .addr = omap44xx_dss_dsi2_addrs,
1515 .user = OCP_USER_MPU,
1516};
1517
1518/* dss_dsi2 slave ports */
1519static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1520 &omap44xx_l3_main_2__dss_dsi2,
1521 &omap44xx_l4_per__dss_dsi2,
1522};
1523
1524static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { 797static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1525 { .role = "sys_clk", .clk = "dss_sys_clk" }, 798 { .role = "sys_clk", .clk = "dss_sys_clk" },
1526}; 799};
@@ -1540,8 +813,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1540 }, 813 },
1541 .opt_clks = dss_dsi2_opt_clks, 814 .opt_clks = dss_dsi2_opt_clks,
1542 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), 815 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1543 .slaves = omap44xx_dss_dsi2_slaves,
1544 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1545}; 816};
1546 817
1547/* 818/*
@@ -1565,7 +836,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1565}; 836};
1566 837
1567/* dss_hdmi */ 838/* dss_hdmi */
1568static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1569static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { 839static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1570 { .irq = 101 + OMAP44XX_IRQ_GIC_START }, 840 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1571 { .irq = -1 } 841 { .irq = -1 }
@@ -1576,48 +846,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1576 { .dma_req = -1 } 846 { .dma_req = -1 }
1577}; 847};
1578 848
1579static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1580 {
1581 .pa_start = 0x58006000,
1582 .pa_end = 0x58006fff,
1583 .flags = ADDR_TYPE_RT
1584 },
1585 { }
1586};
1587
1588/* l3_main_2 -> dss_hdmi */
1589static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1590 .master = &omap44xx_l3_main_2_hwmod,
1591 .slave = &omap44xx_dss_hdmi_hwmod,
1592 .clk = "dss_fck",
1593 .addr = omap44xx_dss_hdmi_dma_addrs,
1594 .user = OCP_USER_SDMA,
1595};
1596
1597static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1598 {
1599 .pa_start = 0x48046000,
1600 .pa_end = 0x48046fff,
1601 .flags = ADDR_TYPE_RT
1602 },
1603 { }
1604};
1605
1606/* l4_per -> dss_hdmi */
1607static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1608 .master = &omap44xx_l4_per_hwmod,
1609 .slave = &omap44xx_dss_hdmi_hwmod,
1610 .clk = "l4_div_ck",
1611 .addr = omap44xx_dss_hdmi_addrs,
1612 .user = OCP_USER_MPU,
1613};
1614
1615/* dss_hdmi slave ports */
1616static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1617 &omap44xx_l3_main_2__dss_hdmi,
1618 &omap44xx_l4_per__dss_hdmi,
1619};
1620
1621static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { 849static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1622 { .role = "sys_clk", .clk = "dss_sys_clk" }, 850 { .role = "sys_clk", .clk = "dss_sys_clk" },
1623}; 851};
@@ -1637,8 +865,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1637 }, 865 },
1638 .opt_clks = dss_hdmi_opt_clks, 866 .opt_clks = dss_hdmi_opt_clks,
1639 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), 867 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1640 .slaves = omap44xx_dss_hdmi_slaves,
1641 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1642}; 868};
1643 869
1644/* 870/*
@@ -1662,54 +888,11 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1662}; 888};
1663 889
1664/* dss_rfbi */ 890/* dss_rfbi */
1665static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1666static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { 891static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1667 { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, 892 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1668 { .dma_req = -1 } 893 { .dma_req = -1 }
1669}; 894};
1670 895
1671static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1672 {
1673 .pa_start = 0x58002000,
1674 .pa_end = 0x580020ff,
1675 .flags = ADDR_TYPE_RT
1676 },
1677 { }
1678};
1679
1680/* l3_main_2 -> dss_rfbi */
1681static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1682 .master = &omap44xx_l3_main_2_hwmod,
1683 .slave = &omap44xx_dss_rfbi_hwmod,
1684 .clk = "dss_fck",
1685 .addr = omap44xx_dss_rfbi_dma_addrs,
1686 .user = OCP_USER_SDMA,
1687};
1688
1689static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1690 {
1691 .pa_start = 0x48042000,
1692 .pa_end = 0x480420ff,
1693 .flags = ADDR_TYPE_RT
1694 },
1695 { }
1696};
1697
1698/* l4_per -> dss_rfbi */
1699static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1700 .master = &omap44xx_l4_per_hwmod,
1701 .slave = &omap44xx_dss_rfbi_hwmod,
1702 .clk = "l4_div_ck",
1703 .addr = omap44xx_dss_rfbi_addrs,
1704 .user = OCP_USER_MPU,
1705};
1706
1707/* dss_rfbi slave ports */
1708static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1709 &omap44xx_l3_main_2__dss_rfbi,
1710 &omap44xx_l4_per__dss_rfbi,
1711};
1712
1713static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 896static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1714 { .role = "ick", .clk = "dss_fck" }, 897 { .role = "ick", .clk = "dss_fck" },
1715}; 898};
@@ -1728,8 +911,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1728 }, 911 },
1729 .opt_clks = dss_rfbi_opt_clks, 912 .opt_clks = dss_rfbi_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 913 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1731 .slaves = omap44xx_dss_rfbi_slaves,
1732 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1733}; 914};
1734 915
1735/* 916/*
@@ -1742,62 +923,165 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1742}; 923};
1743 924
1744/* dss_venc */ 925/* dss_venc */
1745static struct omap_hwmod omap44xx_dss_venc_hwmod; 926static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1746static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { 927 .name = "dss_venc",
1747 { 928 .class = &omap44xx_venc_hwmod_class,
1748 .pa_start = 0x58003000, 929 .clkdm_name = "l3_dss_clkdm",
1749 .pa_end = 0x580030ff, 930 .main_clk = "dss_tv_clk",
1750 .flags = ADDR_TYPE_RT 931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
934 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
935 },
1751 }, 936 },
1752 { }
1753}; 937};
1754 938
1755/* l3_main_2 -> dss_venc */ 939/*
1756static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { 940 * 'elm' class
1757 .master = &omap44xx_l3_main_2_hwmod, 941 * bch error location module
1758 .slave = &omap44xx_dss_venc_hwmod, 942 */
1759 .clk = "dss_fck", 943
1760 .addr = omap44xx_dss_venc_dma_addrs, 944static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
1761 .user = OCP_USER_SDMA, 945 .rev_offs = 0x0000,
946 .sysc_offs = 0x0010,
947 .syss_offs = 0x0014,
948 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
949 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
950 SYSS_HAS_RESET_STATUS),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
952 .sysc_fields = &omap_hwmod_sysc_type1,
1762}; 953};
1763 954
1764static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { 955static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
1765 { 956 .name = "elm",
1766 .pa_start = 0x48043000, 957 .sysc = &omap44xx_elm_sysc,
1767 .pa_end = 0x480430ff, 958};
1768 .flags = ADDR_TYPE_RT 959
960/* elm */
961static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
962 { .irq = 4 + OMAP44XX_IRQ_GIC_START },
963 { .irq = -1 }
964};
965
966static struct omap_hwmod omap44xx_elm_hwmod = {
967 .name = "elm",
968 .class = &omap44xx_elm_hwmod_class,
969 .clkdm_name = "l4_per_clkdm",
970 .mpu_irqs = omap44xx_elm_irqs,
971 .prcm = {
972 .omap4 = {
973 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
974 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
975 },
1769 }, 976 },
1770 { }
1771}; 977};
1772 978
1773/* l4_per -> dss_venc */ 979/*
1774static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { 980 * 'emif' class
1775 .master = &omap44xx_l4_per_hwmod, 981 * external memory interface no1
1776 .slave = &omap44xx_dss_venc_hwmod, 982 */
1777 .clk = "l4_div_ck", 983
1778 .addr = omap44xx_dss_venc_addrs, 984static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1779 .user = OCP_USER_MPU, 985 .rev_offs = 0x0000,
1780}; 986};
1781 987
1782/* dss_venc slave ports */ 988static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1783static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { 989 .name = "emif",
1784 &omap44xx_l3_main_2__dss_venc, 990 .sysc = &omap44xx_emif_sysc,
1785 &omap44xx_l4_per__dss_venc,
1786}; 991};
1787 992
1788static struct omap_hwmod omap44xx_dss_venc_hwmod = { 993/* emif1 */
1789 .name = "dss_venc", 994static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1790 .class = &omap44xx_venc_hwmod_class, 995 { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1791 .clkdm_name = "l3_dss_clkdm", 996 { .irq = -1 }
1792 .main_clk = "dss_tv_clk", 997};
998
999static struct omap_hwmod omap44xx_emif1_hwmod = {
1000 .name = "emif1",
1001 .class = &omap44xx_emif_hwmod_class,
1002 .clkdm_name = "l3_emif_clkdm",
1003 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1004 .mpu_irqs = omap44xx_emif1_irqs,
1005 .main_clk = "ddrphy_ck",
1793 .prcm = { 1006 .prcm = {
1794 .omap4 = { 1007 .omap4 = {
1795 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 1008 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1796 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 1009 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1010 .modulemode = MODULEMODE_HWCTRL,
1011 },
1012 },
1013};
1014
1015/* emif2 */
1016static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1017 { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1018 { .irq = -1 }
1019};
1020
1021static struct omap_hwmod omap44xx_emif2_hwmod = {
1022 .name = "emif2",
1023 .class = &omap44xx_emif_hwmod_class,
1024 .clkdm_name = "l3_emif_clkdm",
1025 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1026 .mpu_irqs = omap44xx_emif2_irqs,
1027 .main_clk = "ddrphy_ck",
1028 .prcm = {
1029 .omap4 = {
1030 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1031 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1032 .modulemode = MODULEMODE_HWCTRL,
1033 },
1034 },
1035};
1036
1037/*
1038 * 'fdif' class
1039 * face detection hw accelerator module
1040 */
1041
1042static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1043 .rev_offs = 0x0000,
1044 .sysc_offs = 0x0010,
1045 /*
1046 * FDIF needs 100 OCP clk cycles delay after a softreset before
1047 * accessing sysconfig again.
1048 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1049 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1050 *
1051 * TODO: Indicate errata when available.
1052 */
1053 .srst_udelay = 2,
1054 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1055 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1056 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1057 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1058 .sysc_fields = &omap_hwmod_sysc_type2,
1059};
1060
1061static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1062 .name = "fdif",
1063 .sysc = &omap44xx_fdif_sysc,
1064};
1065
1066/* fdif */
1067static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1068 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1069 { .irq = -1 }
1070};
1071
1072static struct omap_hwmod omap44xx_fdif_hwmod = {
1073 .name = "fdif",
1074 .class = &omap44xx_fdif_hwmod_class,
1075 .clkdm_name = "iss_clkdm",
1076 .mpu_irqs = omap44xx_fdif_irqs,
1077 .main_clk = "fdif_fck",
1078 .prcm = {
1079 .omap4 = {
1080 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1081 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1082 .modulemode = MODULEMODE_SWCTRL,
1797 }, 1083 },
1798 }, 1084 },
1799 .slaves = omap44xx_dss_venc_slaves,
1800 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1801}; 1085};
1802 1086
1803/* 1087/*
@@ -1830,35 +1114,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1830}; 1114};
1831 1115
1832/* gpio1 */ 1116/* gpio1 */
1833static struct omap_hwmod omap44xx_gpio1_hwmod;
1834static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { 1117static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1835 { .irq = 29 + OMAP44XX_IRQ_GIC_START }, 1118 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1836 { .irq = -1 } 1119 { .irq = -1 }
1837}; 1120};
1838 1121
1839static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1840 {
1841 .pa_start = 0x4a310000,
1842 .pa_end = 0x4a3101ff,
1843 .flags = ADDR_TYPE_RT
1844 },
1845 { }
1846};
1847
1848/* l4_wkup -> gpio1 */
1849static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1850 .master = &omap44xx_l4_wkup_hwmod,
1851 .slave = &omap44xx_gpio1_hwmod,
1852 .clk = "l4_wkup_clk_mux_ck",
1853 .addr = omap44xx_gpio1_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855};
1856
1857/* gpio1 slave ports */
1858static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1859 &omap44xx_l4_wkup__gpio1,
1860};
1861
1862static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 1122static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1863 { .role = "dbclk", .clk = "gpio1_dbclk" }, 1123 { .role = "dbclk", .clk = "gpio1_dbclk" },
1864}; 1124};
@@ -1879,40 +1139,14 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1879 .opt_clks = gpio1_opt_clks, 1139 .opt_clks = gpio1_opt_clks,
1880 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 1140 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1881 .dev_attr = &gpio_dev_attr, 1141 .dev_attr = &gpio_dev_attr,
1882 .slaves = omap44xx_gpio1_slaves,
1883 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1884}; 1142};
1885 1143
1886/* gpio2 */ 1144/* gpio2 */
1887static struct omap_hwmod omap44xx_gpio2_hwmod;
1888static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { 1145static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1889 { .irq = 30 + OMAP44XX_IRQ_GIC_START }, 1146 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1890 { .irq = -1 } 1147 { .irq = -1 }
1891}; 1148};
1892 1149
1893static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1894 {
1895 .pa_start = 0x48055000,
1896 .pa_end = 0x480551ff,
1897 .flags = ADDR_TYPE_RT
1898 },
1899 { }
1900};
1901
1902/* l4_per -> gpio2 */
1903static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1904 .master = &omap44xx_l4_per_hwmod,
1905 .slave = &omap44xx_gpio2_hwmod,
1906 .clk = "l4_div_ck",
1907 .addr = omap44xx_gpio2_addrs,
1908 .user = OCP_USER_MPU | OCP_USER_SDMA,
1909};
1910
1911/* gpio2 slave ports */
1912static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1913 &omap44xx_l4_per__gpio2,
1914};
1915
1916static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 1150static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1917 { .role = "dbclk", .clk = "gpio2_dbclk" }, 1151 { .role = "dbclk", .clk = "gpio2_dbclk" },
1918}; 1152};
@@ -1934,40 +1168,14 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1934 .opt_clks = gpio2_opt_clks, 1168 .opt_clks = gpio2_opt_clks,
1935 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 1169 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1936 .dev_attr = &gpio_dev_attr, 1170 .dev_attr = &gpio_dev_attr,
1937 .slaves = omap44xx_gpio2_slaves,
1938 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1939}; 1171};
1940 1172
1941/* gpio3 */ 1173/* gpio3 */
1942static struct omap_hwmod omap44xx_gpio3_hwmod;
1943static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { 1174static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1944 { .irq = 31 + OMAP44XX_IRQ_GIC_START }, 1175 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1945 { .irq = -1 } 1176 { .irq = -1 }
1946}; 1177};
1947 1178
1948static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1949 {
1950 .pa_start = 0x48057000,
1951 .pa_end = 0x480571ff,
1952 .flags = ADDR_TYPE_RT
1953 },
1954 { }
1955};
1956
1957/* l4_per -> gpio3 */
1958static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1959 .master = &omap44xx_l4_per_hwmod,
1960 .slave = &omap44xx_gpio3_hwmod,
1961 .clk = "l4_div_ck",
1962 .addr = omap44xx_gpio3_addrs,
1963 .user = OCP_USER_MPU | OCP_USER_SDMA,
1964};
1965
1966/* gpio3 slave ports */
1967static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1968 &omap44xx_l4_per__gpio3,
1969};
1970
1971static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 1179static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1972 { .role = "dbclk", .clk = "gpio3_dbclk" }, 1180 { .role = "dbclk", .clk = "gpio3_dbclk" },
1973}; 1181};
@@ -1989,40 +1197,14 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1989 .opt_clks = gpio3_opt_clks, 1197 .opt_clks = gpio3_opt_clks,
1990 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 1198 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1991 .dev_attr = &gpio_dev_attr, 1199 .dev_attr = &gpio_dev_attr,
1992 .slaves = omap44xx_gpio3_slaves,
1993 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1994}; 1200};
1995 1201
1996/* gpio4 */ 1202/* gpio4 */
1997static struct omap_hwmod omap44xx_gpio4_hwmod;
1998static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { 1203static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1999 { .irq = 32 + OMAP44XX_IRQ_GIC_START }, 1204 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2000 { .irq = -1 } 1205 { .irq = -1 }
2001}; 1206};
2002 1207
2003static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2004 {
2005 .pa_start = 0x48059000,
2006 .pa_end = 0x480591ff,
2007 .flags = ADDR_TYPE_RT
2008 },
2009 { }
2010};
2011
2012/* l4_per -> gpio4 */
2013static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2014 .master = &omap44xx_l4_per_hwmod,
2015 .slave = &omap44xx_gpio4_hwmod,
2016 .clk = "l4_div_ck",
2017 .addr = omap44xx_gpio4_addrs,
2018 .user = OCP_USER_MPU | OCP_USER_SDMA,
2019};
2020
2021/* gpio4 slave ports */
2022static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2023 &omap44xx_l4_per__gpio4,
2024};
2025
2026static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 1208static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2027 { .role = "dbclk", .clk = "gpio4_dbclk" }, 1209 { .role = "dbclk", .clk = "gpio4_dbclk" },
2028}; 1210};
@@ -2044,40 +1226,14 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
2044 .opt_clks = gpio4_opt_clks, 1226 .opt_clks = gpio4_opt_clks,
2045 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 1227 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2046 .dev_attr = &gpio_dev_attr, 1228 .dev_attr = &gpio_dev_attr,
2047 .slaves = omap44xx_gpio4_slaves,
2048 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
2049}; 1229};
2050 1230
2051/* gpio5 */ 1231/* gpio5 */
2052static struct omap_hwmod omap44xx_gpio5_hwmod;
2053static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { 1232static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2054 { .irq = 33 + OMAP44XX_IRQ_GIC_START }, 1233 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2055 { .irq = -1 } 1234 { .irq = -1 }
2056}; 1235};
2057 1236
2058static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2059 {
2060 .pa_start = 0x4805b000,
2061 .pa_end = 0x4805b1ff,
2062 .flags = ADDR_TYPE_RT
2063 },
2064 { }
2065};
2066
2067/* l4_per -> gpio5 */
2068static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2069 .master = &omap44xx_l4_per_hwmod,
2070 .slave = &omap44xx_gpio5_hwmod,
2071 .clk = "l4_div_ck",
2072 .addr = omap44xx_gpio5_addrs,
2073 .user = OCP_USER_MPU | OCP_USER_SDMA,
2074};
2075
2076/* gpio5 slave ports */
2077static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2078 &omap44xx_l4_per__gpio5,
2079};
2080
2081static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1237static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2082 { .role = "dbclk", .clk = "gpio5_dbclk" }, 1238 { .role = "dbclk", .clk = "gpio5_dbclk" },
2083}; 1239};
@@ -2099,40 +1255,14 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
2099 .opt_clks = gpio5_opt_clks, 1255 .opt_clks = gpio5_opt_clks,
2100 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 1256 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2101 .dev_attr = &gpio_dev_attr, 1257 .dev_attr = &gpio_dev_attr,
2102 .slaves = omap44xx_gpio5_slaves,
2103 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
2104}; 1258};
2105 1259
2106/* gpio6 */ 1260/* gpio6 */
2107static struct omap_hwmod omap44xx_gpio6_hwmod;
2108static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { 1261static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2109 { .irq = 34 + OMAP44XX_IRQ_GIC_START }, 1262 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2110 { .irq = -1 } 1263 { .irq = -1 }
2111}; 1264};
2112 1265
2113static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2114 {
2115 .pa_start = 0x4805d000,
2116 .pa_end = 0x4805d1ff,
2117 .flags = ADDR_TYPE_RT
2118 },
2119 { }
2120};
2121
2122/* l4_per -> gpio6 */
2123static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2124 .master = &omap44xx_l4_per_hwmod,
2125 .slave = &omap44xx_gpio6_hwmod,
2126 .clk = "l4_div_ck",
2127 .addr = omap44xx_gpio6_addrs,
2128 .user = OCP_USER_MPU | OCP_USER_SDMA,
2129};
2130
2131/* gpio6 slave ports */
2132static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2133 &omap44xx_l4_per__gpio6,
2134};
2135
2136static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 1266static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2137 { .role = "dbclk", .clk = "gpio6_dbclk" }, 1267 { .role = "dbclk", .clk = "gpio6_dbclk" },
2138}; 1268};
@@ -2154,8 +1284,135 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
2154 .opt_clks = gpio6_opt_clks, 1284 .opt_clks = gpio6_opt_clks,
2155 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 1285 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2156 .dev_attr = &gpio_dev_attr, 1286 .dev_attr = &gpio_dev_attr,
2157 .slaves = omap44xx_gpio6_slaves, 1287};
2158 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), 1288
1289/*
1290 * 'gpmc' class
1291 * general purpose memory controller
1292 */
1293
1294static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1295 .rev_offs = 0x0000,
1296 .sysc_offs = 0x0010,
1297 .syss_offs = 0x0014,
1298 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1299 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1300 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1301 .sysc_fields = &omap_hwmod_sysc_type1,
1302};
1303
1304static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1305 .name = "gpmc",
1306 .sysc = &omap44xx_gpmc_sysc,
1307};
1308
1309/* gpmc */
1310static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1311 { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1312 { .irq = -1 }
1313};
1314
1315static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1316 { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1317 { .dma_req = -1 }
1318};
1319
1320static struct omap_hwmod omap44xx_gpmc_hwmod = {
1321 .name = "gpmc",
1322 .class = &omap44xx_gpmc_hwmod_class,
1323 .clkdm_name = "l3_2_clkdm",
1324 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1325 .mpu_irqs = omap44xx_gpmc_irqs,
1326 .sdma_reqs = omap44xx_gpmc_sdma_reqs,
1327 .prcm = {
1328 .omap4 = {
1329 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1330 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1331 .modulemode = MODULEMODE_HWCTRL,
1332 },
1333 },
1334};
1335
1336/*
1337 * 'gpu' class
1338 * 2d/3d graphics accelerator
1339 */
1340
1341static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1342 .rev_offs = 0x1fc00,
1343 .sysc_offs = 0x1fc10,
1344 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1345 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1346 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1347 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1348 .sysc_fields = &omap_hwmod_sysc_type2,
1349};
1350
1351static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1352 .name = "gpu",
1353 .sysc = &omap44xx_gpu_sysc,
1354};
1355
1356/* gpu */
1357static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1358 { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1359 { .irq = -1 }
1360};
1361
1362static struct omap_hwmod omap44xx_gpu_hwmod = {
1363 .name = "gpu",
1364 .class = &omap44xx_gpu_hwmod_class,
1365 .clkdm_name = "l3_gfx_clkdm",
1366 .mpu_irqs = omap44xx_gpu_irqs,
1367 .main_clk = "gpu_fck",
1368 .prcm = {
1369 .omap4 = {
1370 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1371 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1372 .modulemode = MODULEMODE_SWCTRL,
1373 },
1374 },
1375};
1376
1377/*
1378 * 'hdq1w' class
1379 * hdq / 1-wire serial interface controller
1380 */
1381
1382static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1383 .rev_offs = 0x0000,
1384 .sysc_offs = 0x0014,
1385 .syss_offs = 0x0018,
1386 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1387 SYSS_HAS_RESET_STATUS),
1388 .sysc_fields = &omap_hwmod_sysc_type1,
1389};
1390
1391static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1392 .name = "hdq1w",
1393 .sysc = &omap44xx_hdq1w_sysc,
1394};
1395
1396/* hdq1w */
1397static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1398 { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1399 { .irq = -1 }
1400};
1401
1402static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1403 .name = "hdq1w",
1404 .class = &omap44xx_hdq1w_hwmod_class,
1405 .clkdm_name = "l4_per_clkdm",
1406 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1407 .mpu_irqs = omap44xx_hdq1w_irqs,
1408 .main_clk = "hdq1w_fck",
1409 .prcm = {
1410 .omap4 = {
1411 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1412 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1413 .modulemode = MODULEMODE_SWCTRL,
1414 },
1415 },
2159}; 1416};
2160 1417
2161/* 1418/*
@@ -2190,34 +1447,6 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2190 { .irq = -1 } 1447 { .irq = -1 }
2191}; 1448};
2192 1449
2193/* hsi master ports */
2194static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2195 &omap44xx_hsi__l3_main_2,
2196};
2197
2198static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2199 {
2200 .pa_start = 0x4a058000,
2201 .pa_end = 0x4a05bfff,
2202 .flags = ADDR_TYPE_RT
2203 },
2204 { }
2205};
2206
2207/* l4_cfg -> hsi */
2208static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2209 .master = &omap44xx_l4_cfg_hwmod,
2210 .slave = &omap44xx_hsi_hwmod,
2211 .clk = "l4_div_ck",
2212 .addr = omap44xx_hsi_addrs,
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2214};
2215
2216/* hsi slave ports */
2217static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2218 &omap44xx_l4_cfg__hsi,
2219};
2220
2221static struct omap_hwmod omap44xx_hsi_hwmod = { 1450static struct omap_hwmod omap44xx_hsi_hwmod = {
2222 .name = "hsi", 1451 .name = "hsi",
2223 .class = &omap44xx_hsi_hwmod_class, 1452 .class = &omap44xx_hsi_hwmod_class,
@@ -2231,10 +1460,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
2231 .modulemode = MODULEMODE_HWCTRL, 1460 .modulemode = MODULEMODE_HWCTRL,
2232 }, 1461 },
2233 }, 1462 },
2234 .slaves = omap44xx_hsi_slaves,
2235 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2236 .masters = omap44xx_hsi_masters,
2237 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2238}; 1463};
2239 1464
2240/* 1465/*
@@ -2262,11 +1487,11 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2262}; 1487};
2263 1488
2264static struct omap_i2c_dev_attr i2c_dev_attr = { 1489static struct omap_i2c_dev_attr i2c_dev_attr = {
2265 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, 1490 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1491 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
2266}; 1492};
2267 1493
2268/* i2c1 */ 1494/* i2c1 */
2269static struct omap_hwmod omap44xx_i2c1_hwmod;
2270static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { 1495static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2271 { .irq = 56 + OMAP44XX_IRQ_GIC_START }, 1496 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2272 { .irq = -1 } 1497 { .irq = -1 }
@@ -2278,29 +1503,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2278 { .dma_req = -1 } 1503 { .dma_req = -1 }
2279}; 1504};
2280 1505
2281static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2282 {
2283 .pa_start = 0x48070000,
2284 .pa_end = 0x480700ff,
2285 .flags = ADDR_TYPE_RT
2286 },
2287 { }
2288};
2289
2290/* l4_per -> i2c1 */
2291static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2292 .master = &omap44xx_l4_per_hwmod,
2293 .slave = &omap44xx_i2c1_hwmod,
2294 .clk = "l4_div_ck",
2295 .addr = omap44xx_i2c1_addrs,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297};
2298
2299/* i2c1 slave ports */
2300static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2301 &omap44xx_l4_per__i2c1,
2302};
2303
2304static struct omap_hwmod omap44xx_i2c1_hwmod = { 1506static struct omap_hwmod omap44xx_i2c1_hwmod = {
2305 .name = "i2c1", 1507 .name = "i2c1",
2306 .class = &omap44xx_i2c_hwmod_class, 1508 .class = &omap44xx_i2c_hwmod_class,
@@ -2316,13 +1518,10 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
2316 .modulemode = MODULEMODE_SWCTRL, 1518 .modulemode = MODULEMODE_SWCTRL,
2317 }, 1519 },
2318 }, 1520 },
2319 .slaves = omap44xx_i2c1_slaves,
2320 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2321 .dev_attr = &i2c_dev_attr, 1521 .dev_attr = &i2c_dev_attr,
2322}; 1522};
2323 1523
2324/* i2c2 */ 1524/* i2c2 */
2325static struct omap_hwmod omap44xx_i2c2_hwmod;
2326static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { 1525static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2327 { .irq = 57 + OMAP44XX_IRQ_GIC_START }, 1526 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2328 { .irq = -1 } 1527 { .irq = -1 }
@@ -2334,29 +1533,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2334 { .dma_req = -1 } 1533 { .dma_req = -1 }
2335}; 1534};
2336 1535
2337static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2338 {
2339 .pa_start = 0x48072000,
2340 .pa_end = 0x480720ff,
2341 .flags = ADDR_TYPE_RT
2342 },
2343 { }
2344};
2345
2346/* l4_per -> i2c2 */
2347static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2348 .master = &omap44xx_l4_per_hwmod,
2349 .slave = &omap44xx_i2c2_hwmod,
2350 .clk = "l4_div_ck",
2351 .addr = omap44xx_i2c2_addrs,
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353};
2354
2355/* i2c2 slave ports */
2356static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2357 &omap44xx_l4_per__i2c2,
2358};
2359
2360static struct omap_hwmod omap44xx_i2c2_hwmod = { 1536static struct omap_hwmod omap44xx_i2c2_hwmod = {
2361 .name = "i2c2", 1537 .name = "i2c2",
2362 .class = &omap44xx_i2c_hwmod_class, 1538 .class = &omap44xx_i2c_hwmod_class,
@@ -2372,13 +1548,10 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
2372 .modulemode = MODULEMODE_SWCTRL, 1548 .modulemode = MODULEMODE_SWCTRL,
2373 }, 1549 },
2374 }, 1550 },
2375 .slaves = omap44xx_i2c2_slaves,
2376 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2377 .dev_attr = &i2c_dev_attr, 1551 .dev_attr = &i2c_dev_attr,
2378}; 1552};
2379 1553
2380/* i2c3 */ 1554/* i2c3 */
2381static struct omap_hwmod omap44xx_i2c3_hwmod;
2382static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { 1555static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2383 { .irq = 61 + OMAP44XX_IRQ_GIC_START }, 1556 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2384 { .irq = -1 } 1557 { .irq = -1 }
@@ -2390,29 +1563,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2390 { .dma_req = -1 } 1563 { .dma_req = -1 }
2391}; 1564};
2392 1565
2393static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2394 {
2395 .pa_start = 0x48060000,
2396 .pa_end = 0x480600ff,
2397 .flags = ADDR_TYPE_RT
2398 },
2399 { }
2400};
2401
2402/* l4_per -> i2c3 */
2403static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2404 .master = &omap44xx_l4_per_hwmod,
2405 .slave = &omap44xx_i2c3_hwmod,
2406 .clk = "l4_div_ck",
2407 .addr = omap44xx_i2c3_addrs,
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409};
2410
2411/* i2c3 slave ports */
2412static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2413 &omap44xx_l4_per__i2c3,
2414};
2415
2416static struct omap_hwmod omap44xx_i2c3_hwmod = { 1566static struct omap_hwmod omap44xx_i2c3_hwmod = {
2417 .name = "i2c3", 1567 .name = "i2c3",
2418 .class = &omap44xx_i2c_hwmod_class, 1568 .class = &omap44xx_i2c_hwmod_class,
@@ -2428,13 +1578,10 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
2428 .modulemode = MODULEMODE_SWCTRL, 1578 .modulemode = MODULEMODE_SWCTRL,
2429 }, 1579 },
2430 }, 1580 },
2431 .slaves = omap44xx_i2c3_slaves,
2432 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2433 .dev_attr = &i2c_dev_attr, 1581 .dev_attr = &i2c_dev_attr,
2434}; 1582};
2435 1583
2436/* i2c4 */ 1584/* i2c4 */
2437static struct omap_hwmod omap44xx_i2c4_hwmod;
2438static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { 1585static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2439 { .irq = 62 + OMAP44XX_IRQ_GIC_START }, 1586 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2440 { .irq = -1 } 1587 { .irq = -1 }
@@ -2446,29 +1593,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2446 { .dma_req = -1 } 1593 { .dma_req = -1 }
2447}; 1594};
2448 1595
2449static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2450 {
2451 .pa_start = 0x48350000,
2452 .pa_end = 0x483500ff,
2453 .flags = ADDR_TYPE_RT
2454 },
2455 { }
2456};
2457
2458/* l4_per -> i2c4 */
2459static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2460 .master = &omap44xx_l4_per_hwmod,
2461 .slave = &omap44xx_i2c4_hwmod,
2462 .clk = "l4_div_ck",
2463 .addr = omap44xx_i2c4_addrs,
2464 .user = OCP_USER_MPU | OCP_USER_SDMA,
2465};
2466
2467/* i2c4 slave ports */
2468static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2469 &omap44xx_l4_per__i2c4,
2470};
2471
2472static struct omap_hwmod omap44xx_i2c4_hwmod = { 1596static struct omap_hwmod omap44xx_i2c4_hwmod = {
2473 .name = "i2c4", 1597 .name = "i2c4",
2474 .class = &omap44xx_i2c_hwmod_class, 1598 .class = &omap44xx_i2c_hwmod_class,
@@ -2484,8 +1608,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
2484 .modulemode = MODULEMODE_SWCTRL, 1608 .modulemode = MODULEMODE_SWCTRL,
2485 }, 1609 },
2486 }, 1610 },
2487 .slaves = omap44xx_i2c4_slaves,
2488 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2489 .dev_attr = &i2c_dev_attr, 1611 .dev_attr = &i2c_dev_attr,
2490}; 1612};
2491 1613
@@ -2504,66 +1626,12 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2504 { .irq = -1 } 1626 { .irq = -1 }
2505}; 1627};
2506 1628
2507static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { 1629static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2508 { .name = "cpu0", .rst_shift = 0 }, 1630 { .name = "cpu0", .rst_shift = 0 },
2509};
2510
2511static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2512 { .name = "cpu1", .rst_shift = 1 }, 1631 { .name = "cpu1", .rst_shift = 1 },
2513};
2514
2515static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2516 { .name = "mmu_cache", .rst_shift = 2 }, 1632 { .name = "mmu_cache", .rst_shift = 2 },
2517}; 1633};
2518 1634
2519/* ipu master ports */
2520static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2521 &omap44xx_ipu__l3_main_2,
2522};
2523
2524/* l3_main_2 -> ipu */
2525static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2526 .master = &omap44xx_l3_main_2_hwmod,
2527 .slave = &omap44xx_ipu_hwmod,
2528 .clk = "l3_div_ck",
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2530};
2531
2532/* ipu slave ports */
2533static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2534 &omap44xx_l3_main_2__ipu,
2535};
2536
2537/* Pseudo hwmod for reset control purpose only */
2538static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2539 .name = "ipu_c0",
2540 .class = &omap44xx_ipu_hwmod_class,
2541 .clkdm_name = "ducati_clkdm",
2542 .flags = HWMOD_INIT_NO_RESET,
2543 .rst_lines = omap44xx_ipu_c0_resets,
2544 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2545 .prcm = {
2546 .omap4 = {
2547 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2548 },
2549 },
2550};
2551
2552/* Pseudo hwmod for reset control purpose only */
2553static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2554 .name = "ipu_c1",
2555 .class = &omap44xx_ipu_hwmod_class,
2556 .clkdm_name = "ducati_clkdm",
2557 .flags = HWMOD_INIT_NO_RESET,
2558 .rst_lines = omap44xx_ipu_c1_resets,
2559 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2560 .prcm = {
2561 .omap4 = {
2562 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2563 },
2564 },
2565};
2566
2567static struct omap_hwmod omap44xx_ipu_hwmod = { 1635static struct omap_hwmod omap44xx_ipu_hwmod = {
2568 .name = "ipu", 1636 .name = "ipu",
2569 .class = &omap44xx_ipu_hwmod_class, 1637 .class = &omap44xx_ipu_hwmod_class,
@@ -2580,10 +1648,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
2580 .modulemode = MODULEMODE_HWCTRL, 1648 .modulemode = MODULEMODE_HWCTRL,
2581 }, 1649 },
2582 }, 1650 },
2583 .slaves = omap44xx_ipu_slaves,
2584 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2585 .masters = omap44xx_ipu_masters,
2586 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2587}; 1651};
2588 1652
2589/* 1653/*
@@ -2630,34 +1694,6 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2630 { .dma_req = -1 } 1694 { .dma_req = -1 }
2631}; 1695};
2632 1696
2633/* iss master ports */
2634static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2635 &omap44xx_iss__l3_main_2,
2636};
2637
2638static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2639 {
2640 .pa_start = 0x52000000,
2641 .pa_end = 0x520000ff,
2642 .flags = ADDR_TYPE_RT
2643 },
2644 { }
2645};
2646
2647/* l3_main_2 -> iss */
2648static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2649 .master = &omap44xx_l3_main_2_hwmod,
2650 .slave = &omap44xx_iss_hwmod,
2651 .clk = "l3_div_ck",
2652 .addr = omap44xx_iss_addrs,
2653 .user = OCP_USER_MPU | OCP_USER_SDMA,
2654};
2655
2656/* iss slave ports */
2657static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2658 &omap44xx_l3_main_2__iss,
2659};
2660
2661static struct omap_hwmod_opt_clk iss_opt_clks[] = { 1697static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2662 { .role = "ctrlclk", .clk = "iss_ctrlclk" }, 1698 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2663}; 1699};
@@ -2678,10 +1714,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
2678 }, 1714 },
2679 .opt_clks = iss_opt_clks, 1715 .opt_clks = iss_opt_clks,
2680 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), 1716 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2681 .slaves = omap44xx_iss_slaves,
2682 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2683 .masters = omap44xx_iss_masters,
2684 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2685}; 1717};
2686 1718
2687/* 1719/*
@@ -2702,75 +1734,9 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2702}; 1734};
2703 1735
2704static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { 1736static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2705 { .name = "logic", .rst_shift = 2 },
2706};
2707
2708static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2709 { .name = "seq0", .rst_shift = 0 }, 1737 { .name = "seq0", .rst_shift = 0 },
2710};
2711
2712static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2713 { .name = "seq1", .rst_shift = 1 }, 1738 { .name = "seq1", .rst_shift = 1 },
2714}; 1739 { .name = "logic", .rst_shift = 2 },
2715
2716/* iva master ports */
2717static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2718 &omap44xx_iva__l3_main_2,
2719 &omap44xx_iva__l3_instr,
2720};
2721
2722static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2723 {
2724 .pa_start = 0x5a000000,
2725 .pa_end = 0x5a07ffff,
2726 .flags = ADDR_TYPE_RT
2727 },
2728 { }
2729};
2730
2731/* l3_main_2 -> iva */
2732static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2733 .master = &omap44xx_l3_main_2_hwmod,
2734 .slave = &omap44xx_iva_hwmod,
2735 .clk = "l3_div_ck",
2736 .addr = omap44xx_iva_addrs,
2737 .user = OCP_USER_MPU,
2738};
2739
2740/* iva slave ports */
2741static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2742 &omap44xx_dsp__iva,
2743 &omap44xx_l3_main_2__iva,
2744};
2745
2746/* Pseudo hwmod for reset control purpose only */
2747static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2748 .name = "iva_seq0",
2749 .class = &omap44xx_iva_hwmod_class,
2750 .clkdm_name = "ivahd_clkdm",
2751 .flags = HWMOD_INIT_NO_RESET,
2752 .rst_lines = omap44xx_iva_seq0_resets,
2753 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2754 .prcm = {
2755 .omap4 = {
2756 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2757 },
2758 },
2759};
2760
2761/* Pseudo hwmod for reset control purpose only */
2762static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2763 .name = "iva_seq1",
2764 .class = &omap44xx_iva_hwmod_class,
2765 .clkdm_name = "ivahd_clkdm",
2766 .flags = HWMOD_INIT_NO_RESET,
2767 .rst_lines = omap44xx_iva_seq1_resets,
2768 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2769 .prcm = {
2770 .omap4 = {
2771 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2772 },
2773 },
2774}; 1740};
2775 1741
2776static struct omap_hwmod omap44xx_iva_hwmod = { 1742static struct omap_hwmod omap44xx_iva_hwmod = {
@@ -2789,10 +1755,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
2789 .modulemode = MODULEMODE_HWCTRL, 1755 .modulemode = MODULEMODE_HWCTRL,
2790 }, 1756 },
2791 }, 1757 },
2792 .slaves = omap44xx_iva_slaves,
2793 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2794 .masters = omap44xx_iva_masters,
2795 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2796}; 1758};
2797 1759
2798/* 1760/*
@@ -2818,35 +1780,11 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2818}; 1780};
2819 1781
2820/* kbd */ 1782/* kbd */
2821static struct omap_hwmod omap44xx_kbd_hwmod;
2822static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { 1783static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2823 { .irq = 120 + OMAP44XX_IRQ_GIC_START }, 1784 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2824 { .irq = -1 } 1785 { .irq = -1 }
2825}; 1786};
2826 1787
2827static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2828 {
2829 .pa_start = 0x4a31c000,
2830 .pa_end = 0x4a31c07f,
2831 .flags = ADDR_TYPE_RT
2832 },
2833 { }
2834};
2835
2836/* l4_wkup -> kbd */
2837static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2838 .master = &omap44xx_l4_wkup_hwmod,
2839 .slave = &omap44xx_kbd_hwmod,
2840 .clk = "l4_wkup_clk_mux_ck",
2841 .addr = omap44xx_kbd_addrs,
2842 .user = OCP_USER_MPU | OCP_USER_SDMA,
2843};
2844
2845/* kbd slave ports */
2846static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2847 &omap44xx_l4_wkup__kbd,
2848};
2849
2850static struct omap_hwmod omap44xx_kbd_hwmod = { 1788static struct omap_hwmod omap44xx_kbd_hwmod = {
2851 .name = "kbd", 1789 .name = "kbd",
2852 .class = &omap44xx_kbd_hwmod_class, 1790 .class = &omap44xx_kbd_hwmod_class,
@@ -2860,8 +1798,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
2860 .modulemode = MODULEMODE_SWCTRL, 1798 .modulemode = MODULEMODE_SWCTRL,
2861 }, 1799 },
2862 }, 1800 },
2863 .slaves = omap44xx_kbd_slaves,
2864 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2865}; 1801};
2866 1802
2867/* 1803/*
@@ -2885,35 +1821,11 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2885}; 1821};
2886 1822
2887/* mailbox */ 1823/* mailbox */
2888static struct omap_hwmod omap44xx_mailbox_hwmod;
2889static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { 1824static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2890 { .irq = 26 + OMAP44XX_IRQ_GIC_START }, 1825 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2891 { .irq = -1 } 1826 { .irq = -1 }
2892}; 1827};
2893 1828
2894static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2895 {
2896 .pa_start = 0x4a0f4000,
2897 .pa_end = 0x4a0f41ff,
2898 .flags = ADDR_TYPE_RT
2899 },
2900 { }
2901};
2902
2903/* l4_cfg -> mailbox */
2904static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2905 .master = &omap44xx_l4_cfg_hwmod,
2906 .slave = &omap44xx_mailbox_hwmod,
2907 .clk = "l4_div_ck",
2908 .addr = omap44xx_mailbox_addrs,
2909 .user = OCP_USER_MPU | OCP_USER_SDMA,
2910};
2911
2912/* mailbox slave ports */
2913static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2914 &omap44xx_l4_cfg__mailbox,
2915};
2916
2917static struct omap_hwmod omap44xx_mailbox_hwmod = { 1829static struct omap_hwmod omap44xx_mailbox_hwmod = {
2918 .name = "mailbox", 1830 .name = "mailbox",
2919 .class = &omap44xx_mailbox_hwmod_class, 1831 .class = &omap44xx_mailbox_hwmod_class,
@@ -2925,8 +1837,58 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
2925 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, 1837 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2926 }, 1838 },
2927 }, 1839 },
2928 .slaves = omap44xx_mailbox_slaves, 1840};
2929 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), 1841
1842/*
1843 * 'mcasp' class
1844 * multi-channel audio serial port controller
1845 */
1846
1847/* The IP is not compliant to type1 / type2 scheme */
1848static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1849 .sidle_shift = 0,
1850};
1851
1852static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1853 .sysc_offs = 0x0004,
1854 .sysc_flags = SYSC_HAS_SIDLEMODE,
1855 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1856 SIDLE_SMART_WKUP),
1857 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1858};
1859
1860static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1861 .name = "mcasp",
1862 .sysc = &omap44xx_mcasp_sysc,
1863};
1864
1865/* mcasp */
1866static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1867 { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1868 { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1869 { .irq = -1 }
1870};
1871
1872static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1873 { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1874 { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1875 { .dma_req = -1 }
1876};
1877
1878static struct omap_hwmod omap44xx_mcasp_hwmod = {
1879 .name = "mcasp",
1880 .class = &omap44xx_mcasp_hwmod_class,
1881 .clkdm_name = "abe_clkdm",
1882 .mpu_irqs = omap44xx_mcasp_irqs,
1883 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1884 .main_clk = "mcasp_fck",
1885 .prcm = {
1886 .omap4 = {
1887 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1888 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1889 .modulemode = MODULEMODE_SWCTRL,
1890 },
1891 },
2930}; 1892};
2931 1893
2932/* 1894/*
@@ -2949,9 +1911,8 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2949}; 1911};
2950 1912
2951/* mcbsp1 */ 1913/* mcbsp1 */
2952static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2953static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { 1914static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2954 { .irq = 17 + OMAP44XX_IRQ_GIC_START }, 1915 { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
2955 { .irq = -1 } 1916 { .irq = -1 }
2956}; 1917};
2957 1918
@@ -2961,50 +1922,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2961 { .dma_req = -1 } 1922 { .dma_req = -1 }
2962}; 1923};
2963 1924
2964static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2965 {
2966 .name = "mpu",
2967 .pa_start = 0x40122000,
2968 .pa_end = 0x401220ff,
2969 .flags = ADDR_TYPE_RT
2970 },
2971 { }
2972};
2973
2974/* l4_abe -> mcbsp1 */
2975static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2976 .master = &omap44xx_l4_abe_hwmod,
2977 .slave = &omap44xx_mcbsp1_hwmod,
2978 .clk = "ocp_abe_iclk",
2979 .addr = omap44xx_mcbsp1_addrs,
2980 .user = OCP_USER_MPU,
2981};
2982
2983static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2984 {
2985 .name = "dma",
2986 .pa_start = 0x49022000,
2987 .pa_end = 0x490220ff,
2988 .flags = ADDR_TYPE_RT
2989 },
2990 { }
2991};
2992
2993/* l4_abe -> mcbsp1 (dma) */
2994static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2995 .master = &omap44xx_l4_abe_hwmod,
2996 .slave = &omap44xx_mcbsp1_hwmod,
2997 .clk = "ocp_abe_iclk",
2998 .addr = omap44xx_mcbsp1_dma_addrs,
2999 .user = OCP_USER_SDMA,
3000};
3001
3002/* mcbsp1 slave ports */
3003static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
3004 &omap44xx_l4_abe__mcbsp1,
3005 &omap44xx_l4_abe__mcbsp1_dma,
3006};
3007
3008static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { 1925static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
3009 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1926 { .role = "pad_fck", .clk = "pad_clks_ck" },
3010 { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, 1927 { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
@@ -3024,16 +1941,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
3024 .modulemode = MODULEMODE_SWCTRL, 1941 .modulemode = MODULEMODE_SWCTRL,
3025 }, 1942 },
3026 }, 1943 },
3027 .slaves = omap44xx_mcbsp1_slaves,
3028 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3029 .opt_clks = mcbsp1_opt_clks, 1944 .opt_clks = mcbsp1_opt_clks,
3030 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), 1945 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
3031}; 1946};
3032 1947
3033/* mcbsp2 */ 1948/* mcbsp2 */
3034static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3035static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { 1949static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3036 { .irq = 22 + OMAP44XX_IRQ_GIC_START }, 1950 { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
3037 { .irq = -1 } 1951 { .irq = -1 }
3038}; 1952};
3039 1953
@@ -3043,50 +1957,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3043 { .dma_req = -1 } 1957 { .dma_req = -1 }
3044}; 1958};
3045 1959
3046static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3047 {
3048 .name = "mpu",
3049 .pa_start = 0x40124000,
3050 .pa_end = 0x401240ff,
3051 .flags = ADDR_TYPE_RT
3052 },
3053 { }
3054};
3055
3056/* l4_abe -> mcbsp2 */
3057static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3058 .master = &omap44xx_l4_abe_hwmod,
3059 .slave = &omap44xx_mcbsp2_hwmod,
3060 .clk = "ocp_abe_iclk",
3061 .addr = omap44xx_mcbsp2_addrs,
3062 .user = OCP_USER_MPU,
3063};
3064
3065static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3066 {
3067 .name = "dma",
3068 .pa_start = 0x49024000,
3069 .pa_end = 0x490240ff,
3070 .flags = ADDR_TYPE_RT
3071 },
3072 { }
3073};
3074
3075/* l4_abe -> mcbsp2 (dma) */
3076static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3077 .master = &omap44xx_l4_abe_hwmod,
3078 .slave = &omap44xx_mcbsp2_hwmod,
3079 .clk = "ocp_abe_iclk",
3080 .addr = omap44xx_mcbsp2_dma_addrs,
3081 .user = OCP_USER_SDMA,
3082};
3083
3084/* mcbsp2 slave ports */
3085static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3086 &omap44xx_l4_abe__mcbsp2,
3087 &omap44xx_l4_abe__mcbsp2_dma,
3088};
3089
3090static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { 1960static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
3091 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1961 { .role = "pad_fck", .clk = "pad_clks_ck" },
3092 { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, 1962 { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
@@ -3106,16 +1976,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3106 .modulemode = MODULEMODE_SWCTRL, 1976 .modulemode = MODULEMODE_SWCTRL,
3107 }, 1977 },
3108 }, 1978 },
3109 .slaves = omap44xx_mcbsp2_slaves,
3110 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3111 .opt_clks = mcbsp2_opt_clks, 1979 .opt_clks = mcbsp2_opt_clks,
3112 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), 1980 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
3113}; 1981};
3114 1982
3115/* mcbsp3 */ 1983/* mcbsp3 */
3116static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3117static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { 1984static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3118 { .irq = 23 + OMAP44XX_IRQ_GIC_START }, 1985 { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
3119 { .irq = -1 } 1986 { .irq = -1 }
3120}; 1987};
3121 1988
@@ -3125,50 +1992,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3125 { .dma_req = -1 } 1992 { .dma_req = -1 }
3126}; 1993};
3127 1994
3128static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3129 {
3130 .name = "mpu",
3131 .pa_start = 0x40126000,
3132 .pa_end = 0x401260ff,
3133 .flags = ADDR_TYPE_RT
3134 },
3135 { }
3136};
3137
3138/* l4_abe -> mcbsp3 */
3139static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3140 .master = &omap44xx_l4_abe_hwmod,
3141 .slave = &omap44xx_mcbsp3_hwmod,
3142 .clk = "ocp_abe_iclk",
3143 .addr = omap44xx_mcbsp3_addrs,
3144 .user = OCP_USER_MPU,
3145};
3146
3147static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3148 {
3149 .name = "dma",
3150 .pa_start = 0x49026000,
3151 .pa_end = 0x490260ff,
3152 .flags = ADDR_TYPE_RT
3153 },
3154 { }
3155};
3156
3157/* l4_abe -> mcbsp3 (dma) */
3158static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3159 .master = &omap44xx_l4_abe_hwmod,
3160 .slave = &omap44xx_mcbsp3_hwmod,
3161 .clk = "ocp_abe_iclk",
3162 .addr = omap44xx_mcbsp3_dma_addrs,
3163 .user = OCP_USER_SDMA,
3164};
3165
3166/* mcbsp3 slave ports */
3167static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3168 &omap44xx_l4_abe__mcbsp3,
3169 &omap44xx_l4_abe__mcbsp3_dma,
3170};
3171
3172static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { 1995static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
3173 { .role = "pad_fck", .clk = "pad_clks_ck" }, 1996 { .role = "pad_fck", .clk = "pad_clks_ck" },
3174 { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, 1997 { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
@@ -3188,16 +2011,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3188 .modulemode = MODULEMODE_SWCTRL, 2011 .modulemode = MODULEMODE_SWCTRL,
3189 }, 2012 },
3190 }, 2013 },
3191 .slaves = omap44xx_mcbsp3_slaves,
3192 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3193 .opt_clks = mcbsp3_opt_clks, 2014 .opt_clks = mcbsp3_opt_clks,
3194 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), 2015 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
3195}; 2016};
3196 2017
3197/* mcbsp4 */ 2018/* mcbsp4 */
3198static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3199static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { 2019static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3200 { .irq = 16 + OMAP44XX_IRQ_GIC_START }, 2020 { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
3201 { .irq = -1 } 2021 { .irq = -1 }
3202}; 2022};
3203 2023
@@ -3207,29 +2027,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3207 { .dma_req = -1 } 2027 { .dma_req = -1 }
3208}; 2028};
3209 2029
3210static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3211 {
3212 .pa_start = 0x48096000,
3213 .pa_end = 0x480960ff,
3214 .flags = ADDR_TYPE_RT
3215 },
3216 { }
3217};
3218
3219/* l4_per -> mcbsp4 */
3220static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3221 .master = &omap44xx_l4_per_hwmod,
3222 .slave = &omap44xx_mcbsp4_hwmod,
3223 .clk = "l4_div_ck",
3224 .addr = omap44xx_mcbsp4_addrs,
3225 .user = OCP_USER_MPU | OCP_USER_SDMA,
3226};
3227
3228/* mcbsp4 slave ports */
3229static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3230 &omap44xx_l4_per__mcbsp4,
3231};
3232
3233static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { 2030static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
3234 { .role = "pad_fck", .clk = "pad_clks_ck" }, 2031 { .role = "pad_fck", .clk = "pad_clks_ck" },
3235 { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, 2032 { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
@@ -3249,8 +2046,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3249 .modulemode = MODULEMODE_SWCTRL, 2046 .modulemode = MODULEMODE_SWCTRL,
3250 }, 2047 },
3251 }, 2048 },
3252 .slaves = omap44xx_mcbsp4_slaves,
3253 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3254 .opt_clks = mcbsp4_opt_clks, 2049 .opt_clks = mcbsp4_opt_clks,
3255 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), 2050 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
3256}; 2051};
@@ -3277,7 +2072,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3277}; 2072};
3278 2073
3279/* mcpdm */ 2074/* mcpdm */
3280static struct omap_hwmod omap44xx_mcpdm_hwmod;
3281static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { 2075static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3282 { .irq = 112 + OMAP44XX_IRQ_GIC_START }, 2076 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3283 { .irq = -1 } 2077 { .irq = -1 }
@@ -3289,48 +2083,6 @@ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3289 { .dma_req = -1 } 2083 { .dma_req = -1 }
3290}; 2084};
3291 2085
3292static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3293 {
3294 .pa_start = 0x40132000,
3295 .pa_end = 0x4013207f,
3296 .flags = ADDR_TYPE_RT
3297 },
3298 { }
3299};
3300
3301/* l4_abe -> mcpdm */
3302static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3303 .master = &omap44xx_l4_abe_hwmod,
3304 .slave = &omap44xx_mcpdm_hwmod,
3305 .clk = "ocp_abe_iclk",
3306 .addr = omap44xx_mcpdm_addrs,
3307 .user = OCP_USER_MPU,
3308};
3309
3310static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3311 {
3312 .pa_start = 0x49032000,
3313 .pa_end = 0x4903207f,
3314 .flags = ADDR_TYPE_RT
3315 },
3316 { }
3317};
3318
3319/* l4_abe -> mcpdm (dma) */
3320static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3321 .master = &omap44xx_l4_abe_hwmod,
3322 .slave = &omap44xx_mcpdm_hwmod,
3323 .clk = "ocp_abe_iclk",
3324 .addr = omap44xx_mcpdm_dma_addrs,
3325 .user = OCP_USER_SDMA,
3326};
3327
3328/* mcpdm slave ports */
3329static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3330 &omap44xx_l4_abe__mcpdm,
3331 &omap44xx_l4_abe__mcpdm_dma,
3332};
3333
3334static struct omap_hwmod omap44xx_mcpdm_hwmod = { 2086static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3335 .name = "mcpdm", 2087 .name = "mcpdm",
3336 .class = &omap44xx_mcpdm_hwmod_class, 2088 .class = &omap44xx_mcpdm_hwmod_class,
@@ -3345,8 +2097,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3345 .modulemode = MODULEMODE_SWCTRL, 2097 .modulemode = MODULEMODE_SWCTRL,
3346 }, 2098 },
3347 }, 2099 },
3348 .slaves = omap44xx_mcpdm_slaves,
3349 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3350}; 2100};
3351 2101
3352/* 2102/*
@@ -3372,7 +2122,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3372}; 2122};
3373 2123
3374/* mcspi1 */ 2124/* mcspi1 */
3375static struct omap_hwmod omap44xx_mcspi1_hwmod;
3376static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { 2125static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3377 { .irq = 65 + OMAP44XX_IRQ_GIC_START }, 2126 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3378 { .irq = -1 } 2127 { .irq = -1 }
@@ -3390,29 +2139,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3390 { .dma_req = -1 } 2139 { .dma_req = -1 }
3391}; 2140};
3392 2141
3393static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3394 {
3395 .pa_start = 0x48098000,
3396 .pa_end = 0x480981ff,
3397 .flags = ADDR_TYPE_RT
3398 },
3399 { }
3400};
3401
3402/* l4_per -> mcspi1 */
3403static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3404 .master = &omap44xx_l4_per_hwmod,
3405 .slave = &omap44xx_mcspi1_hwmod,
3406 .clk = "l4_div_ck",
3407 .addr = omap44xx_mcspi1_addrs,
3408 .user = OCP_USER_MPU | OCP_USER_SDMA,
3409};
3410
3411/* mcspi1 slave ports */
3412static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3413 &omap44xx_l4_per__mcspi1,
3414};
3415
3416/* mcspi1 dev_attr */ 2142/* mcspi1 dev_attr */
3417static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { 2143static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3418 .num_chipselect = 4, 2144 .num_chipselect = 4,
@@ -3433,12 +2159,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3433 }, 2159 },
3434 }, 2160 },
3435 .dev_attr = &mcspi1_dev_attr, 2161 .dev_attr = &mcspi1_dev_attr,
3436 .slaves = omap44xx_mcspi1_slaves,
3437 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3438}; 2162};
3439 2163
3440/* mcspi2 */ 2164/* mcspi2 */
3441static struct omap_hwmod omap44xx_mcspi2_hwmod;
3442static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { 2165static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3443 { .irq = 66 + OMAP44XX_IRQ_GIC_START }, 2166 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3444 { .irq = -1 } 2167 { .irq = -1 }
@@ -3452,29 +2175,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3452 { .dma_req = -1 } 2175 { .dma_req = -1 }
3453}; 2176};
3454 2177
3455static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3456 {
3457 .pa_start = 0x4809a000,
3458 .pa_end = 0x4809a1ff,
3459 .flags = ADDR_TYPE_RT
3460 },
3461 { }
3462};
3463
3464/* l4_per -> mcspi2 */
3465static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3466 .master = &omap44xx_l4_per_hwmod,
3467 .slave = &omap44xx_mcspi2_hwmod,
3468 .clk = "l4_div_ck",
3469 .addr = omap44xx_mcspi2_addrs,
3470 .user = OCP_USER_MPU | OCP_USER_SDMA,
3471};
3472
3473/* mcspi2 slave ports */
3474static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3475 &omap44xx_l4_per__mcspi2,
3476};
3477
3478/* mcspi2 dev_attr */ 2178/* mcspi2 dev_attr */
3479static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { 2179static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3480 .num_chipselect = 2, 2180 .num_chipselect = 2,
@@ -3495,12 +2195,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3495 }, 2195 },
3496 }, 2196 },
3497 .dev_attr = &mcspi2_dev_attr, 2197 .dev_attr = &mcspi2_dev_attr,
3498 .slaves = omap44xx_mcspi2_slaves,
3499 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3500}; 2198};
3501 2199
3502/* mcspi3 */ 2200/* mcspi3 */
3503static struct omap_hwmod omap44xx_mcspi3_hwmod;
3504static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { 2201static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3505 { .irq = 91 + OMAP44XX_IRQ_GIC_START }, 2202 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3506 { .irq = -1 } 2203 { .irq = -1 }
@@ -3514,29 +2211,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3514 { .dma_req = -1 } 2211 { .dma_req = -1 }
3515}; 2212};
3516 2213
3517static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3518 {
3519 .pa_start = 0x480b8000,
3520 .pa_end = 0x480b81ff,
3521 .flags = ADDR_TYPE_RT
3522 },
3523 { }
3524};
3525
3526/* l4_per -> mcspi3 */
3527static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3528 .master = &omap44xx_l4_per_hwmod,
3529 .slave = &omap44xx_mcspi3_hwmod,
3530 .clk = "l4_div_ck",
3531 .addr = omap44xx_mcspi3_addrs,
3532 .user = OCP_USER_MPU | OCP_USER_SDMA,
3533};
3534
3535/* mcspi3 slave ports */
3536static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3537 &omap44xx_l4_per__mcspi3,
3538};
3539
3540/* mcspi3 dev_attr */ 2214/* mcspi3 dev_attr */
3541static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { 2215static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3542 .num_chipselect = 2, 2216 .num_chipselect = 2,
@@ -3557,12 +2231,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3557 }, 2231 },
3558 }, 2232 },
3559 .dev_attr = &mcspi3_dev_attr, 2233 .dev_attr = &mcspi3_dev_attr,
3560 .slaves = omap44xx_mcspi3_slaves,
3561 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3562}; 2234};
3563 2235
3564/* mcspi4 */ 2236/* mcspi4 */
3565static struct omap_hwmod omap44xx_mcspi4_hwmod;
3566static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { 2237static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3567 { .irq = 48 + OMAP44XX_IRQ_GIC_START }, 2238 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3568 { .irq = -1 } 2239 { .irq = -1 }
@@ -3574,29 +2245,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3574 { .dma_req = -1 } 2245 { .dma_req = -1 }
3575}; 2246};
3576 2247
3577static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3578 {
3579 .pa_start = 0x480ba000,
3580 .pa_end = 0x480ba1ff,
3581 .flags = ADDR_TYPE_RT
3582 },
3583 { }
3584};
3585
3586/* l4_per -> mcspi4 */
3587static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3588 .master = &omap44xx_l4_per_hwmod,
3589 .slave = &omap44xx_mcspi4_hwmod,
3590 .clk = "l4_div_ck",
3591 .addr = omap44xx_mcspi4_addrs,
3592 .user = OCP_USER_MPU | OCP_USER_SDMA,
3593};
3594
3595/* mcspi4 slave ports */
3596static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3597 &omap44xx_l4_per__mcspi4,
3598};
3599
3600/* mcspi4 dev_attr */ 2248/* mcspi4 dev_attr */
3601static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { 2249static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3602 .num_chipselect = 1, 2250 .num_chipselect = 1,
@@ -3617,8 +2265,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3617 }, 2265 },
3618 }, 2266 },
3619 .dev_attr = &mcspi4_dev_attr, 2267 .dev_attr = &mcspi4_dev_attr,
3620 .slaves = omap44xx_mcspi4_slaves,
3621 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3622}; 2268};
3623 2269
3624/* 2270/*
@@ -3655,34 +2301,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3655 { .dma_req = -1 } 2301 { .dma_req = -1 }
3656}; 2302};
3657 2303
3658/* mmc1 master ports */
3659static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3660 &omap44xx_mmc1__l3_main_1,
3661};
3662
3663static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3664 {
3665 .pa_start = 0x4809c000,
3666 .pa_end = 0x4809c3ff,
3667 .flags = ADDR_TYPE_RT
3668 },
3669 { }
3670};
3671
3672/* l4_per -> mmc1 */
3673static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3674 .master = &omap44xx_l4_per_hwmod,
3675 .slave = &omap44xx_mmc1_hwmod,
3676 .clk = "l4_div_ck",
3677 .addr = omap44xx_mmc1_addrs,
3678 .user = OCP_USER_MPU | OCP_USER_SDMA,
3679};
3680
3681/* mmc1 slave ports */
3682static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3683 &omap44xx_l4_per__mmc1,
3684};
3685
3686/* mmc1 dev_attr */ 2304/* mmc1 dev_attr */
3687static struct omap_mmc_dev_attr mmc1_dev_attr = { 2305static struct omap_mmc_dev_attr mmc1_dev_attr = {
3688 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 2306 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
@@ -3703,10 +2321,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
3703 }, 2321 },
3704 }, 2322 },
3705 .dev_attr = &mmc1_dev_attr, 2323 .dev_attr = &mmc1_dev_attr,
3706 .slaves = omap44xx_mmc1_slaves,
3707 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3708 .masters = omap44xx_mmc1_masters,
3709 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3710}; 2324};
3711 2325
3712/* mmc2 */ 2326/* mmc2 */
@@ -3721,34 +2335,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3721 { .dma_req = -1 } 2335 { .dma_req = -1 }
3722}; 2336};
3723 2337
3724/* mmc2 master ports */
3725static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3726 &omap44xx_mmc2__l3_main_1,
3727};
3728
3729static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3730 {
3731 .pa_start = 0x480b4000,
3732 .pa_end = 0x480b43ff,
3733 .flags = ADDR_TYPE_RT
3734 },
3735 { }
3736};
3737
3738/* l4_per -> mmc2 */
3739static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3740 .master = &omap44xx_l4_per_hwmod,
3741 .slave = &omap44xx_mmc2_hwmod,
3742 .clk = "l4_div_ck",
3743 .addr = omap44xx_mmc2_addrs,
3744 .user = OCP_USER_MPU | OCP_USER_SDMA,
3745};
3746
3747/* mmc2 slave ports */
3748static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3749 &omap44xx_l4_per__mmc2,
3750};
3751
3752static struct omap_hwmod omap44xx_mmc2_hwmod = { 2338static struct omap_hwmod omap44xx_mmc2_hwmod = {
3753 .name = "mmc2", 2339 .name = "mmc2",
3754 .class = &omap44xx_mmc_hwmod_class, 2340 .class = &omap44xx_mmc_hwmod_class,
@@ -3763,14 +2349,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
3763 .modulemode = MODULEMODE_SWCTRL, 2349 .modulemode = MODULEMODE_SWCTRL,
3764 }, 2350 },
3765 }, 2351 },
3766 .slaves = omap44xx_mmc2_slaves,
3767 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3768 .masters = omap44xx_mmc2_masters,
3769 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3770}; 2352};
3771 2353
3772/* mmc3 */ 2354/* mmc3 */
3773static struct omap_hwmod omap44xx_mmc3_hwmod;
3774static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { 2355static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3775 { .irq = 94 + OMAP44XX_IRQ_GIC_START }, 2356 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3776 { .irq = -1 } 2357 { .irq = -1 }
@@ -3782,29 +2363,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3782 { .dma_req = -1 } 2363 { .dma_req = -1 }
3783}; 2364};
3784 2365
3785static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3786 {
3787 .pa_start = 0x480ad000,
3788 .pa_end = 0x480ad3ff,
3789 .flags = ADDR_TYPE_RT
3790 },
3791 { }
3792};
3793
3794/* l4_per -> mmc3 */
3795static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3796 .master = &omap44xx_l4_per_hwmod,
3797 .slave = &omap44xx_mmc3_hwmod,
3798 .clk = "l4_div_ck",
3799 .addr = omap44xx_mmc3_addrs,
3800 .user = OCP_USER_MPU | OCP_USER_SDMA,
3801};
3802
3803/* mmc3 slave ports */
3804static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3805 &omap44xx_l4_per__mmc3,
3806};
3807
3808static struct omap_hwmod omap44xx_mmc3_hwmod = { 2366static struct omap_hwmod omap44xx_mmc3_hwmod = {
3809 .name = "mmc3", 2367 .name = "mmc3",
3810 .class = &omap44xx_mmc_hwmod_class, 2368 .class = &omap44xx_mmc_hwmod_class,
@@ -3819,12 +2377,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
3819 .modulemode = MODULEMODE_SWCTRL, 2377 .modulemode = MODULEMODE_SWCTRL,
3820 }, 2378 },
3821 }, 2379 },
3822 .slaves = omap44xx_mmc3_slaves,
3823 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3824}; 2380};
3825 2381
3826/* mmc4 */ 2382/* mmc4 */
3827static struct omap_hwmod omap44xx_mmc4_hwmod;
3828static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { 2383static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3829 { .irq = 96 + OMAP44XX_IRQ_GIC_START }, 2384 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3830 { .irq = -1 } 2385 { .irq = -1 }
@@ -3836,35 +2391,11 @@ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3836 { .dma_req = -1 } 2391 { .dma_req = -1 }
3837}; 2392};
3838 2393
3839static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3840 {
3841 .pa_start = 0x480d1000,
3842 .pa_end = 0x480d13ff,
3843 .flags = ADDR_TYPE_RT
3844 },
3845 { }
3846};
3847
3848/* l4_per -> mmc4 */
3849static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3850 .master = &omap44xx_l4_per_hwmod,
3851 .slave = &omap44xx_mmc4_hwmod,
3852 .clk = "l4_div_ck",
3853 .addr = omap44xx_mmc4_addrs,
3854 .user = OCP_USER_MPU | OCP_USER_SDMA,
3855};
3856
3857/* mmc4 slave ports */
3858static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3859 &omap44xx_l4_per__mmc4,
3860};
3861
3862static struct omap_hwmod omap44xx_mmc4_hwmod = { 2394static struct omap_hwmod omap44xx_mmc4_hwmod = {
3863 .name = "mmc4", 2395 .name = "mmc4",
3864 .class = &omap44xx_mmc_hwmod_class, 2396 .class = &omap44xx_mmc_hwmod_class,
3865 .clkdm_name = "l4_per_clkdm", 2397 .clkdm_name = "l4_per_clkdm",
3866 .mpu_irqs = omap44xx_mmc4_irqs, 2398 .mpu_irqs = omap44xx_mmc4_irqs,
3867
3868 .sdma_reqs = omap44xx_mmc4_sdma_reqs, 2399 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3869 .main_clk = "mmc4_fck", 2400 .main_clk = "mmc4_fck",
3870 .prcm = { 2401 .prcm = {
@@ -3874,12 +2405,9 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
3874 .modulemode = MODULEMODE_SWCTRL, 2405 .modulemode = MODULEMODE_SWCTRL,
3875 }, 2406 },
3876 }, 2407 },
3877 .slaves = omap44xx_mmc4_slaves,
3878 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3879}; 2408};
3880 2409
3881/* mmc5 */ 2410/* mmc5 */
3882static struct omap_hwmod omap44xx_mmc5_hwmod;
3883static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { 2411static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3884 { .irq = 59 + OMAP44XX_IRQ_GIC_START }, 2412 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3885 { .irq = -1 } 2413 { .irq = -1 }
@@ -3891,29 +2419,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3891 { .dma_req = -1 } 2419 { .dma_req = -1 }
3892}; 2420};
3893 2421
3894static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3895 {
3896 .pa_start = 0x480d5000,
3897 .pa_end = 0x480d53ff,
3898 .flags = ADDR_TYPE_RT
3899 },
3900 { }
3901};
3902
3903/* l4_per -> mmc5 */
3904static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3905 .master = &omap44xx_l4_per_hwmod,
3906 .slave = &omap44xx_mmc5_hwmod,
3907 .clk = "l4_div_ck",
3908 .addr = omap44xx_mmc5_addrs,
3909 .user = OCP_USER_MPU | OCP_USER_SDMA,
3910};
3911
3912/* mmc5 slave ports */
3913static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3914 &omap44xx_l4_per__mmc5,
3915};
3916
3917static struct omap_hwmod omap44xx_mmc5_hwmod = { 2422static struct omap_hwmod omap44xx_mmc5_hwmod = {
3918 .name = "mmc5", 2423 .name = "mmc5",
3919 .class = &omap44xx_mmc_hwmod_class, 2424 .class = &omap44xx_mmc_hwmod_class,
@@ -3928,8 +2433,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
3928 .modulemode = MODULEMODE_SWCTRL, 2433 .modulemode = MODULEMODE_SWCTRL,
3929 }, 2434 },
3930 }, 2435 },
3931 .slaves = omap44xx_mmc5_slaves,
3932 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3933}; 2436};
3934 2437
3935/* 2438/*
@@ -3949,13 +2452,6 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3949 { .irq = -1 } 2452 { .irq = -1 }
3950}; 2453};
3951 2454
3952/* mpu master ports */
3953static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3954 &omap44xx_mpu__l3_main_1,
3955 &omap44xx_mpu__l4_abe,
3956 &omap44xx_mpu__dmm,
3957};
3958
3959static struct omap_hwmod omap44xx_mpu_hwmod = { 2455static struct omap_hwmod omap44xx_mpu_hwmod = {
3960 .name = "mpu", 2456 .name = "mpu",
3961 .class = &omap44xx_mpu_hwmod_class, 2457 .class = &omap44xx_mpu_hwmod_class,
@@ -3969,8 +2465,252 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
3969 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, 2465 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3970 }, 2466 },
3971 }, 2467 },
3972 .masters = omap44xx_mpu_masters, 2468};
3973 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), 2469
2470/*
2471 * 'ocmc_ram' class
2472 * top-level core on-chip ram
2473 */
2474
2475static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2476 .name = "ocmc_ram",
2477};
2478
2479/* ocmc_ram */
2480static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2481 .name = "ocmc_ram",
2482 .class = &omap44xx_ocmc_ram_hwmod_class,
2483 .clkdm_name = "l3_2_clkdm",
2484 .prcm = {
2485 .omap4 = {
2486 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2487 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2488 },
2489 },
2490};
2491
2492/*
2493 * 'ocp2scp' class
2494 * bridge to transform ocp interface protocol to scp (serial control port)
2495 * protocol
2496 */
2497
2498static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2499 .name = "ocp2scp",
2500};
2501
2502/* ocp2scp_usb_phy */
2503static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2504 { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2505};
2506
2507static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2508 .name = "ocp2scp_usb_phy",
2509 .class = &omap44xx_ocp2scp_hwmod_class,
2510 .clkdm_name = "l3_init_clkdm",
2511 .prcm = {
2512 .omap4 = {
2513 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2514 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2515 .modulemode = MODULEMODE_HWCTRL,
2516 },
2517 },
2518 .opt_clks = ocp2scp_usb_phy_opt_clks,
2519 .opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2520};
2521
2522/*
2523 * 'prcm' class
2524 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2525 * + clock manager 1 (in always on power domain) + local prm in mpu
2526 */
2527
2528static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2529 .name = "prcm",
2530};
2531
2532/* prcm_mpu */
2533static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2534 .name = "prcm_mpu",
2535 .class = &omap44xx_prcm_hwmod_class,
2536 .clkdm_name = "l4_wkup_clkdm",
2537};
2538
2539/* cm_core_aon */
2540static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2541 .name = "cm_core_aon",
2542 .class = &omap44xx_prcm_hwmod_class,
2543 .clkdm_name = "cm_clkdm",
2544};
2545
2546/* cm_core */
2547static struct omap_hwmod omap44xx_cm_core_hwmod = {
2548 .name = "cm_core",
2549 .class = &omap44xx_prcm_hwmod_class,
2550 .clkdm_name = "cm_clkdm",
2551};
2552
2553/* prm */
2554static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2555 { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2556 { .irq = -1 }
2557};
2558
2559static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2560 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2561 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2562};
2563
2564static struct omap_hwmod omap44xx_prm_hwmod = {
2565 .name = "prm",
2566 .class = &omap44xx_prcm_hwmod_class,
2567 .clkdm_name = "prm_clkdm",
2568 .mpu_irqs = omap44xx_prm_irqs,
2569 .rst_lines = omap44xx_prm_resets,
2570 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2571};
2572
2573/*
2574 * 'scrm' class
2575 * system clock and reset manager
2576 */
2577
2578static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2579 .name = "scrm",
2580};
2581
2582/* scrm */
2583static struct omap_hwmod omap44xx_scrm_hwmod = {
2584 .name = "scrm",
2585 .class = &omap44xx_scrm_hwmod_class,
2586 .clkdm_name = "l4_wkup_clkdm",
2587};
2588
2589/*
2590 * 'sl2if' class
2591 * shared level 2 memory interface
2592 */
2593
2594static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2595 .name = "sl2if",
2596};
2597
2598/* sl2if */
2599static struct omap_hwmod omap44xx_sl2if_hwmod = {
2600 .name = "sl2if",
2601 .class = &omap44xx_sl2if_hwmod_class,
2602 .clkdm_name = "ivahd_clkdm",
2603 .prcm = {
2604 .omap4 = {
2605 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2606 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2607 .modulemode = MODULEMODE_HWCTRL,
2608 },
2609 },
2610};
2611
2612/*
2613 * 'slimbus' class
2614 * bidirectional, multi-drop, multi-channel two-line serial interface between
2615 * the device and external components
2616 */
2617
2618static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2619 .rev_offs = 0x0000,
2620 .sysc_offs = 0x0010,
2621 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2622 SYSC_HAS_SOFTRESET),
2623 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2624 SIDLE_SMART_WKUP),
2625 .sysc_fields = &omap_hwmod_sysc_type2,
2626};
2627
2628static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2629 .name = "slimbus",
2630 .sysc = &omap44xx_slimbus_sysc,
2631};
2632
2633/* slimbus1 */
2634static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2635 { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2636 { .irq = -1 }
2637};
2638
2639static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2640 { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2641 { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2642 { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2643 { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2644 { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2645 { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2646 { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2647 { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2648 { .dma_req = -1 }
2649};
2650
2651static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2652 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2653 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2654 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2655 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2656};
2657
2658static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2659 .name = "slimbus1",
2660 .class = &omap44xx_slimbus_hwmod_class,
2661 .clkdm_name = "abe_clkdm",
2662 .mpu_irqs = omap44xx_slimbus1_irqs,
2663 .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
2664 .prcm = {
2665 .omap4 = {
2666 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2667 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2668 .modulemode = MODULEMODE_SWCTRL,
2669 },
2670 },
2671 .opt_clks = slimbus1_opt_clks,
2672 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2673};
2674
2675/* slimbus2 */
2676static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2677 { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2678 { .irq = -1 }
2679};
2680
2681static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2682 { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2683 { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2684 { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2685 { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2686 { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2687 { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2688 { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2689 { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2690 { .dma_req = -1 }
2691};
2692
2693static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2694 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2695 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2696 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2697};
2698
2699static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2700 .name = "slimbus2",
2701 .class = &omap44xx_slimbus_hwmod_class,
2702 .clkdm_name = "l4_per_clkdm",
2703 .mpu_irqs = omap44xx_slimbus2_irqs,
2704 .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
2705 .prcm = {
2706 .omap4 = {
2707 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2708 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2709 .modulemode = MODULEMODE_SWCTRL,
2710 },
2711 },
2712 .opt_clks = slimbus2_opt_clks,
2713 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
3974}; 2714};
3975 2715
3976/* 2716/*
@@ -4004,35 +2744,11 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
4004 .sensor_voltdm_name = "core", 2744 .sensor_voltdm_name = "core",
4005}; 2745};
4006 2746
4007static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
4008static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { 2747static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
4009 { .irq = 19 + OMAP44XX_IRQ_GIC_START }, 2748 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
4010 { .irq = -1 } 2749 { .irq = -1 }
4011}; 2750};
4012 2751
4013static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4014 {
4015 .pa_start = 0x4a0dd000,
4016 .pa_end = 0x4a0dd03f,
4017 .flags = ADDR_TYPE_RT
4018 },
4019 { }
4020};
4021
4022/* l4_cfg -> smartreflex_core */
4023static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4024 .master = &omap44xx_l4_cfg_hwmod,
4025 .slave = &omap44xx_smartreflex_core_hwmod,
4026 .clk = "l4_div_ck",
4027 .addr = omap44xx_smartreflex_core_addrs,
4028 .user = OCP_USER_MPU | OCP_USER_SDMA,
4029};
4030
4031/* smartreflex_core slave ports */
4032static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
4033 &omap44xx_l4_cfg__smartreflex_core,
4034};
4035
4036static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { 2752static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
4037 .name = "smartreflex_core", 2753 .name = "smartreflex_core",
4038 .class = &omap44xx_smartreflex_hwmod_class, 2754 .class = &omap44xx_smartreflex_hwmod_class,
@@ -4047,8 +2763,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
4047 .modulemode = MODULEMODE_SWCTRL, 2763 .modulemode = MODULEMODE_SWCTRL,
4048 }, 2764 },
4049 }, 2765 },
4050 .slaves = omap44xx_smartreflex_core_slaves,
4051 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4052 .dev_attr = &smartreflex_core_dev_attr, 2766 .dev_attr = &smartreflex_core_dev_attr,
4053}; 2767};
4054 2768
@@ -4057,35 +2771,11 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
4057 .sensor_voltdm_name = "iva", 2771 .sensor_voltdm_name = "iva",
4058}; 2772};
4059 2773
4060static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4061static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { 2774static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4062 { .irq = 102 + OMAP44XX_IRQ_GIC_START }, 2775 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4063 { .irq = -1 } 2776 { .irq = -1 }
4064}; 2777};
4065 2778
4066static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4067 {
4068 .pa_start = 0x4a0db000,
4069 .pa_end = 0x4a0db03f,
4070 .flags = ADDR_TYPE_RT
4071 },
4072 { }
4073};
4074
4075/* l4_cfg -> smartreflex_iva */
4076static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4077 .master = &omap44xx_l4_cfg_hwmod,
4078 .slave = &omap44xx_smartreflex_iva_hwmod,
4079 .clk = "l4_div_ck",
4080 .addr = omap44xx_smartreflex_iva_addrs,
4081 .user = OCP_USER_MPU | OCP_USER_SDMA,
4082};
4083
4084/* smartreflex_iva slave ports */
4085static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4086 &omap44xx_l4_cfg__smartreflex_iva,
4087};
4088
4089static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { 2779static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4090 .name = "smartreflex_iva", 2780 .name = "smartreflex_iva",
4091 .class = &omap44xx_smartreflex_hwmod_class, 2781 .class = &omap44xx_smartreflex_hwmod_class,
@@ -4099,8 +2789,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4099 .modulemode = MODULEMODE_SWCTRL, 2789 .modulemode = MODULEMODE_SWCTRL,
4100 }, 2790 },
4101 }, 2791 },
4102 .slaves = omap44xx_smartreflex_iva_slaves,
4103 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4104 .dev_attr = &smartreflex_iva_dev_attr, 2792 .dev_attr = &smartreflex_iva_dev_attr,
4105}; 2793};
4106 2794
@@ -4109,35 +2797,11 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
4109 .sensor_voltdm_name = "mpu", 2797 .sensor_voltdm_name = "mpu",
4110}; 2798};
4111 2799
4112static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4113static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { 2800static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4114 { .irq = 18 + OMAP44XX_IRQ_GIC_START }, 2801 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4115 { .irq = -1 } 2802 { .irq = -1 }
4116}; 2803};
4117 2804
4118static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4119 {
4120 .pa_start = 0x4a0d9000,
4121 .pa_end = 0x4a0d903f,
4122 .flags = ADDR_TYPE_RT
4123 },
4124 { }
4125};
4126
4127/* l4_cfg -> smartreflex_mpu */
4128static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4129 .master = &omap44xx_l4_cfg_hwmod,
4130 .slave = &omap44xx_smartreflex_mpu_hwmod,
4131 .clk = "l4_div_ck",
4132 .addr = omap44xx_smartreflex_mpu_addrs,
4133 .user = OCP_USER_MPU | OCP_USER_SDMA,
4134};
4135
4136/* smartreflex_mpu slave ports */
4137static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4138 &omap44xx_l4_cfg__smartreflex_mpu,
4139};
4140
4141static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { 2805static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4142 .name = "smartreflex_mpu", 2806 .name = "smartreflex_mpu",
4143 .class = &omap44xx_smartreflex_hwmod_class, 2807 .class = &omap44xx_smartreflex_hwmod_class,
@@ -4151,8 +2815,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4151 .modulemode = MODULEMODE_SWCTRL, 2815 .modulemode = MODULEMODE_SWCTRL,
4152 }, 2816 },
4153 }, 2817 },
4154 .slaves = omap44xx_smartreflex_mpu_slaves,
4155 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4156 .dev_attr = &smartreflex_mpu_dev_attr, 2818 .dev_attr = &smartreflex_mpu_dev_attr,
4157}; 2819};
4158 2820
@@ -4180,30 +2842,6 @@ static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4180}; 2842};
4181 2843
4182/* spinlock */ 2844/* spinlock */
4183static struct omap_hwmod omap44xx_spinlock_hwmod;
4184static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4185 {
4186 .pa_start = 0x4a0f6000,
4187 .pa_end = 0x4a0f6fff,
4188 .flags = ADDR_TYPE_RT
4189 },
4190 { }
4191};
4192
4193/* l4_cfg -> spinlock */
4194static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4195 .master = &omap44xx_l4_cfg_hwmod,
4196 .slave = &omap44xx_spinlock_hwmod,
4197 .clk = "l4_div_ck",
4198 .addr = omap44xx_spinlock_addrs,
4199 .user = OCP_USER_MPU | OCP_USER_SDMA,
4200};
4201
4202/* spinlock slave ports */
4203static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4204 &omap44xx_l4_cfg__spinlock,
4205};
4206
4207static struct omap_hwmod omap44xx_spinlock_hwmod = { 2845static struct omap_hwmod omap44xx_spinlock_hwmod = {
4208 .name = "spinlock", 2846 .name = "spinlock",
4209 .class = &omap44xx_spinlock_hwmod_class, 2847 .class = &omap44xx_spinlock_hwmod_class,
@@ -4214,8 +2852,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
4214 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, 2852 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4215 }, 2853 },
4216 }, 2854 },
4217 .slaves = omap44xx_spinlock_slaves,
4218 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4219}; 2855};
4220 2856
4221/* 2857/*
@@ -4267,35 +2903,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4267}; 2903};
4268 2904
4269/* timer1 */ 2905/* timer1 */
4270static struct omap_hwmod omap44xx_timer1_hwmod;
4271static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { 2906static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4272 { .irq = 37 + OMAP44XX_IRQ_GIC_START }, 2907 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4273 { .irq = -1 } 2908 { .irq = -1 }
4274}; 2909};
4275 2910
4276static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4277 {
4278 .pa_start = 0x4a318000,
4279 .pa_end = 0x4a31807f,
4280 .flags = ADDR_TYPE_RT
4281 },
4282 { }
4283};
4284
4285/* l4_wkup -> timer1 */
4286static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4287 .master = &omap44xx_l4_wkup_hwmod,
4288 .slave = &omap44xx_timer1_hwmod,
4289 .clk = "l4_wkup_clk_mux_ck",
4290 .addr = omap44xx_timer1_addrs,
4291 .user = OCP_USER_MPU | OCP_USER_SDMA,
4292};
4293
4294/* timer1 slave ports */
4295static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4296 &omap44xx_l4_wkup__timer1,
4297};
4298
4299static struct omap_hwmod omap44xx_timer1_hwmod = { 2911static struct omap_hwmod omap44xx_timer1_hwmod = {
4300 .name = "timer1", 2912 .name = "timer1",
4301 .class = &omap44xx_timer_1ms_hwmod_class, 2913 .class = &omap44xx_timer_1ms_hwmod_class,
@@ -4310,40 +2922,14 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
4310 }, 2922 },
4311 }, 2923 },
4312 .dev_attr = &capability_alwon_dev_attr, 2924 .dev_attr = &capability_alwon_dev_attr,
4313 .slaves = omap44xx_timer1_slaves,
4314 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4315}; 2925};
4316 2926
4317/* timer2 */ 2927/* timer2 */
4318static struct omap_hwmod omap44xx_timer2_hwmod;
4319static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { 2928static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4320 { .irq = 38 + OMAP44XX_IRQ_GIC_START }, 2929 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4321 { .irq = -1 } 2930 { .irq = -1 }
4322}; 2931};
4323 2932
4324static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4325 {
4326 .pa_start = 0x48032000,
4327 .pa_end = 0x4803207f,
4328 .flags = ADDR_TYPE_RT
4329 },
4330 { }
4331};
4332
4333/* l4_per -> timer2 */
4334static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4335 .master = &omap44xx_l4_per_hwmod,
4336 .slave = &omap44xx_timer2_hwmod,
4337 .clk = "l4_div_ck",
4338 .addr = omap44xx_timer2_addrs,
4339 .user = OCP_USER_MPU | OCP_USER_SDMA,
4340};
4341
4342/* timer2 slave ports */
4343static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4344 &omap44xx_l4_per__timer2,
4345};
4346
4347static struct omap_hwmod omap44xx_timer2_hwmod = { 2933static struct omap_hwmod omap44xx_timer2_hwmod = {
4348 .name = "timer2", 2934 .name = "timer2",
4349 .class = &omap44xx_timer_1ms_hwmod_class, 2935 .class = &omap44xx_timer_1ms_hwmod_class,
@@ -4358,40 +2944,14 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
4358 }, 2944 },
4359 }, 2945 },
4360 .dev_attr = &capability_alwon_dev_attr, 2946 .dev_attr = &capability_alwon_dev_attr,
4361 .slaves = omap44xx_timer2_slaves,
4362 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4363}; 2947};
4364 2948
4365/* timer3 */ 2949/* timer3 */
4366static struct omap_hwmod omap44xx_timer3_hwmod;
4367static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { 2950static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4368 { .irq = 39 + OMAP44XX_IRQ_GIC_START }, 2951 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4369 { .irq = -1 } 2952 { .irq = -1 }
4370}; 2953};
4371 2954
4372static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4373 {
4374 .pa_start = 0x48034000,
4375 .pa_end = 0x4803407f,
4376 .flags = ADDR_TYPE_RT
4377 },
4378 { }
4379};
4380
4381/* l4_per -> timer3 */
4382static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4383 .master = &omap44xx_l4_per_hwmod,
4384 .slave = &omap44xx_timer3_hwmod,
4385 .clk = "l4_div_ck",
4386 .addr = omap44xx_timer3_addrs,
4387 .user = OCP_USER_MPU | OCP_USER_SDMA,
4388};
4389
4390/* timer3 slave ports */
4391static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4392 &omap44xx_l4_per__timer3,
4393};
4394
4395static struct omap_hwmod omap44xx_timer3_hwmod = { 2955static struct omap_hwmod omap44xx_timer3_hwmod = {
4396 .name = "timer3", 2956 .name = "timer3",
4397 .class = &omap44xx_timer_hwmod_class, 2957 .class = &omap44xx_timer_hwmod_class,
@@ -4406,40 +2966,14 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
4406 }, 2966 },
4407 }, 2967 },
4408 .dev_attr = &capability_alwon_dev_attr, 2968 .dev_attr = &capability_alwon_dev_attr,
4409 .slaves = omap44xx_timer3_slaves,
4410 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4411}; 2969};
4412 2970
4413/* timer4 */ 2971/* timer4 */
4414static struct omap_hwmod omap44xx_timer4_hwmod;
4415static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { 2972static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4416 { .irq = 40 + OMAP44XX_IRQ_GIC_START }, 2973 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4417 { .irq = -1 } 2974 { .irq = -1 }
4418}; 2975};
4419 2976
4420static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4421 {
4422 .pa_start = 0x48036000,
4423 .pa_end = 0x4803607f,
4424 .flags = ADDR_TYPE_RT
4425 },
4426 { }
4427};
4428
4429/* l4_per -> timer4 */
4430static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4431 .master = &omap44xx_l4_per_hwmod,
4432 .slave = &omap44xx_timer4_hwmod,
4433 .clk = "l4_div_ck",
4434 .addr = omap44xx_timer4_addrs,
4435 .user = OCP_USER_MPU | OCP_USER_SDMA,
4436};
4437
4438/* timer4 slave ports */
4439static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4440 &omap44xx_l4_per__timer4,
4441};
4442
4443static struct omap_hwmod omap44xx_timer4_hwmod = { 2977static struct omap_hwmod omap44xx_timer4_hwmod = {
4444 .name = "timer4", 2978 .name = "timer4",
4445 .class = &omap44xx_timer_hwmod_class, 2979 .class = &omap44xx_timer_hwmod_class,
@@ -4454,59 +2988,14 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
4454 }, 2988 },
4455 }, 2989 },
4456 .dev_attr = &capability_alwon_dev_attr, 2990 .dev_attr = &capability_alwon_dev_attr,
4457 .slaves = omap44xx_timer4_slaves,
4458 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4459}; 2991};
4460 2992
4461/* timer5 */ 2993/* timer5 */
4462static struct omap_hwmod omap44xx_timer5_hwmod;
4463static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { 2994static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4464 { .irq = 41 + OMAP44XX_IRQ_GIC_START }, 2995 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4465 { .irq = -1 } 2996 { .irq = -1 }
4466}; 2997};
4467 2998
4468static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4469 {
4470 .pa_start = 0x40138000,
4471 .pa_end = 0x4013807f,
4472 .flags = ADDR_TYPE_RT
4473 },
4474 { }
4475};
4476
4477/* l4_abe -> timer5 */
4478static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4479 .master = &omap44xx_l4_abe_hwmod,
4480 .slave = &omap44xx_timer5_hwmod,
4481 .clk = "ocp_abe_iclk",
4482 .addr = omap44xx_timer5_addrs,
4483 .user = OCP_USER_MPU,
4484};
4485
4486static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4487 {
4488 .pa_start = 0x49038000,
4489 .pa_end = 0x4903807f,
4490 .flags = ADDR_TYPE_RT
4491 },
4492 { }
4493};
4494
4495/* l4_abe -> timer5 (dma) */
4496static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4497 .master = &omap44xx_l4_abe_hwmod,
4498 .slave = &omap44xx_timer5_hwmod,
4499 .clk = "ocp_abe_iclk",
4500 .addr = omap44xx_timer5_dma_addrs,
4501 .user = OCP_USER_SDMA,
4502};
4503
4504/* timer5 slave ports */
4505static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4506 &omap44xx_l4_abe__timer5,
4507 &omap44xx_l4_abe__timer5_dma,
4508};
4509
4510static struct omap_hwmod omap44xx_timer5_hwmod = { 2999static struct omap_hwmod omap44xx_timer5_hwmod = {
4511 .name = "timer5", 3000 .name = "timer5",
4512 .class = &omap44xx_timer_hwmod_class, 3001 .class = &omap44xx_timer_hwmod_class,
@@ -4521,59 +3010,14 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
4521 }, 3010 },
4522 }, 3011 },
4523 .dev_attr = &capability_alwon_dev_attr, 3012 .dev_attr = &capability_alwon_dev_attr,
4524 .slaves = omap44xx_timer5_slaves,
4525 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4526}; 3013};
4527 3014
4528/* timer6 */ 3015/* timer6 */
4529static struct omap_hwmod omap44xx_timer6_hwmod;
4530static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { 3016static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4531 { .irq = 42 + OMAP44XX_IRQ_GIC_START }, 3017 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4532 { .irq = -1 } 3018 { .irq = -1 }
4533}; 3019};
4534 3020
4535static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4536 {
4537 .pa_start = 0x4013a000,
4538 .pa_end = 0x4013a07f,
4539 .flags = ADDR_TYPE_RT
4540 },
4541 { }
4542};
4543
4544/* l4_abe -> timer6 */
4545static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4546 .master = &omap44xx_l4_abe_hwmod,
4547 .slave = &omap44xx_timer6_hwmod,
4548 .clk = "ocp_abe_iclk",
4549 .addr = omap44xx_timer6_addrs,
4550 .user = OCP_USER_MPU,
4551};
4552
4553static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4554 {
4555 .pa_start = 0x4903a000,
4556 .pa_end = 0x4903a07f,
4557 .flags = ADDR_TYPE_RT
4558 },
4559 { }
4560};
4561
4562/* l4_abe -> timer6 (dma) */
4563static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4564 .master = &omap44xx_l4_abe_hwmod,
4565 .slave = &omap44xx_timer6_hwmod,
4566 .clk = "ocp_abe_iclk",
4567 .addr = omap44xx_timer6_dma_addrs,
4568 .user = OCP_USER_SDMA,
4569};
4570
4571/* timer6 slave ports */
4572static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4573 &omap44xx_l4_abe__timer6,
4574 &omap44xx_l4_abe__timer6_dma,
4575};
4576
4577static struct omap_hwmod omap44xx_timer6_hwmod = { 3021static struct omap_hwmod omap44xx_timer6_hwmod = {
4578 .name = "timer6", 3022 .name = "timer6",
4579 .class = &omap44xx_timer_hwmod_class, 3023 .class = &omap44xx_timer_hwmod_class,
@@ -4589,59 +3033,14 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
4589 }, 3033 },
4590 }, 3034 },
4591 .dev_attr = &capability_alwon_dev_attr, 3035 .dev_attr = &capability_alwon_dev_attr,
4592 .slaves = omap44xx_timer6_slaves,
4593 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4594}; 3036};
4595 3037
4596/* timer7 */ 3038/* timer7 */
4597static struct omap_hwmod omap44xx_timer7_hwmod;
4598static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { 3039static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4599 { .irq = 43 + OMAP44XX_IRQ_GIC_START }, 3040 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4600 { .irq = -1 } 3041 { .irq = -1 }
4601}; 3042};
4602 3043
4603static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4604 {
4605 .pa_start = 0x4013c000,
4606 .pa_end = 0x4013c07f,
4607 .flags = ADDR_TYPE_RT
4608 },
4609 { }
4610};
4611
4612/* l4_abe -> timer7 */
4613static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4614 .master = &omap44xx_l4_abe_hwmod,
4615 .slave = &omap44xx_timer7_hwmod,
4616 .clk = "ocp_abe_iclk",
4617 .addr = omap44xx_timer7_addrs,
4618 .user = OCP_USER_MPU,
4619};
4620
4621static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4622 {
4623 .pa_start = 0x4903c000,
4624 .pa_end = 0x4903c07f,
4625 .flags = ADDR_TYPE_RT
4626 },
4627 { }
4628};
4629
4630/* l4_abe -> timer7 (dma) */
4631static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4632 .master = &omap44xx_l4_abe_hwmod,
4633 .slave = &omap44xx_timer7_hwmod,
4634 .clk = "ocp_abe_iclk",
4635 .addr = omap44xx_timer7_dma_addrs,
4636 .user = OCP_USER_SDMA,
4637};
4638
4639/* timer7 slave ports */
4640static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4641 &omap44xx_l4_abe__timer7,
4642 &omap44xx_l4_abe__timer7_dma,
4643};
4644
4645static struct omap_hwmod omap44xx_timer7_hwmod = { 3044static struct omap_hwmod omap44xx_timer7_hwmod = {
4646 .name = "timer7", 3045 .name = "timer7",
4647 .class = &omap44xx_timer_hwmod_class, 3046 .class = &omap44xx_timer_hwmod_class,
@@ -4656,59 +3055,14 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
4656 }, 3055 },
4657 }, 3056 },
4658 .dev_attr = &capability_alwon_dev_attr, 3057 .dev_attr = &capability_alwon_dev_attr,
4659 .slaves = omap44xx_timer7_slaves,
4660 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4661}; 3058};
4662 3059
4663/* timer8 */ 3060/* timer8 */
4664static struct omap_hwmod omap44xx_timer8_hwmod;
4665static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { 3061static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4666 { .irq = 44 + OMAP44XX_IRQ_GIC_START }, 3062 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4667 { .irq = -1 } 3063 { .irq = -1 }
4668}; 3064};
4669 3065
4670static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4671 {
4672 .pa_start = 0x4013e000,
4673 .pa_end = 0x4013e07f,
4674 .flags = ADDR_TYPE_RT
4675 },
4676 { }
4677};
4678
4679/* l4_abe -> timer8 */
4680static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4681 .master = &omap44xx_l4_abe_hwmod,
4682 .slave = &omap44xx_timer8_hwmod,
4683 .clk = "ocp_abe_iclk",
4684 .addr = omap44xx_timer8_addrs,
4685 .user = OCP_USER_MPU,
4686};
4687
4688static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4689 {
4690 .pa_start = 0x4903e000,
4691 .pa_end = 0x4903e07f,
4692 .flags = ADDR_TYPE_RT
4693 },
4694 { }
4695};
4696
4697/* l4_abe -> timer8 (dma) */
4698static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4699 .master = &omap44xx_l4_abe_hwmod,
4700 .slave = &omap44xx_timer8_hwmod,
4701 .clk = "ocp_abe_iclk",
4702 .addr = omap44xx_timer8_dma_addrs,
4703 .user = OCP_USER_SDMA,
4704};
4705
4706/* timer8 slave ports */
4707static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4708 &omap44xx_l4_abe__timer8,
4709 &omap44xx_l4_abe__timer8_dma,
4710};
4711
4712static struct omap_hwmod omap44xx_timer8_hwmod = { 3066static struct omap_hwmod omap44xx_timer8_hwmod = {
4713 .name = "timer8", 3067 .name = "timer8",
4714 .class = &omap44xx_timer_hwmod_class, 3068 .class = &omap44xx_timer_hwmod_class,
@@ -4723,40 +3077,14 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
4723 }, 3077 },
4724 }, 3078 },
4725 .dev_attr = &capability_pwm_dev_attr, 3079 .dev_attr = &capability_pwm_dev_attr,
4726 .slaves = omap44xx_timer8_slaves,
4727 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4728}; 3080};
4729 3081
4730/* timer9 */ 3082/* timer9 */
4731static struct omap_hwmod omap44xx_timer9_hwmod;
4732static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { 3083static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4733 { .irq = 45 + OMAP44XX_IRQ_GIC_START }, 3084 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4734 { .irq = -1 } 3085 { .irq = -1 }
4735}; 3086};
4736 3087
4737static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4738 {
4739 .pa_start = 0x4803e000,
4740 .pa_end = 0x4803e07f,
4741 .flags = ADDR_TYPE_RT
4742 },
4743 { }
4744};
4745
4746/* l4_per -> timer9 */
4747static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4748 .master = &omap44xx_l4_per_hwmod,
4749 .slave = &omap44xx_timer9_hwmod,
4750 .clk = "l4_div_ck",
4751 .addr = omap44xx_timer9_addrs,
4752 .user = OCP_USER_MPU | OCP_USER_SDMA,
4753};
4754
4755/* timer9 slave ports */
4756static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4757 &omap44xx_l4_per__timer9,
4758};
4759
4760static struct omap_hwmod omap44xx_timer9_hwmod = { 3088static struct omap_hwmod omap44xx_timer9_hwmod = {
4761 .name = "timer9", 3089 .name = "timer9",
4762 .class = &omap44xx_timer_hwmod_class, 3090 .class = &omap44xx_timer_hwmod_class,
@@ -4771,40 +3099,14 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
4771 }, 3099 },
4772 }, 3100 },
4773 .dev_attr = &capability_pwm_dev_attr, 3101 .dev_attr = &capability_pwm_dev_attr,
4774 .slaves = omap44xx_timer9_slaves,
4775 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4776}; 3102};
4777 3103
4778/* timer10 */ 3104/* timer10 */
4779static struct omap_hwmod omap44xx_timer10_hwmod;
4780static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { 3105static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4781 { .irq = 46 + OMAP44XX_IRQ_GIC_START }, 3106 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4782 { .irq = -1 } 3107 { .irq = -1 }
4783}; 3108};
4784 3109
4785static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4786 {
4787 .pa_start = 0x48086000,
4788 .pa_end = 0x4808607f,
4789 .flags = ADDR_TYPE_RT
4790 },
4791 { }
4792};
4793
4794/* l4_per -> timer10 */
4795static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4796 .master = &omap44xx_l4_per_hwmod,
4797 .slave = &omap44xx_timer10_hwmod,
4798 .clk = "l4_div_ck",
4799 .addr = omap44xx_timer10_addrs,
4800 .user = OCP_USER_MPU | OCP_USER_SDMA,
4801};
4802
4803/* timer10 slave ports */
4804static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4805 &omap44xx_l4_per__timer10,
4806};
4807
4808static struct omap_hwmod omap44xx_timer10_hwmod = { 3110static struct omap_hwmod omap44xx_timer10_hwmod = {
4809 .name = "timer10", 3111 .name = "timer10",
4810 .class = &omap44xx_timer_1ms_hwmod_class, 3112 .class = &omap44xx_timer_1ms_hwmod_class,
@@ -4819,40 +3121,14 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
4819 }, 3121 },
4820 }, 3122 },
4821 .dev_attr = &capability_pwm_dev_attr, 3123 .dev_attr = &capability_pwm_dev_attr,
4822 .slaves = omap44xx_timer10_slaves,
4823 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4824}; 3124};
4825 3125
4826/* timer11 */ 3126/* timer11 */
4827static struct omap_hwmod omap44xx_timer11_hwmod;
4828static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { 3127static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4829 { .irq = 47 + OMAP44XX_IRQ_GIC_START }, 3128 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4830 { .irq = -1 } 3129 { .irq = -1 }
4831}; 3130};
4832 3131
4833static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4834 {
4835 .pa_start = 0x48088000,
4836 .pa_end = 0x4808807f,
4837 .flags = ADDR_TYPE_RT
4838 },
4839 { }
4840};
4841
4842/* l4_per -> timer11 */
4843static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4844 .master = &omap44xx_l4_per_hwmod,
4845 .slave = &omap44xx_timer11_hwmod,
4846 .clk = "l4_div_ck",
4847 .addr = omap44xx_timer11_addrs,
4848 .user = OCP_USER_MPU | OCP_USER_SDMA,
4849};
4850
4851/* timer11 slave ports */
4852static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4853 &omap44xx_l4_per__timer11,
4854};
4855
4856static struct omap_hwmod omap44xx_timer11_hwmod = { 3132static struct omap_hwmod omap44xx_timer11_hwmod = {
4857 .name = "timer11", 3133 .name = "timer11",
4858 .class = &omap44xx_timer_hwmod_class, 3134 .class = &omap44xx_timer_hwmod_class,
@@ -4867,8 +3143,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
4867 }, 3143 },
4868 }, 3144 },
4869 .dev_attr = &capability_pwm_dev_attr, 3145 .dev_attr = &capability_pwm_dev_attr,
4870 .slaves = omap44xx_timer11_slaves,
4871 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4872}; 3146};
4873 3147
4874/* 3148/*
@@ -4894,7 +3168,6 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4894}; 3168};
4895 3169
4896/* uart1 */ 3170/* uart1 */
4897static struct omap_hwmod omap44xx_uart1_hwmod;
4898static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { 3171static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4899 { .irq = 72 + OMAP44XX_IRQ_GIC_START }, 3172 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4900 { .irq = -1 } 3173 { .irq = -1 }
@@ -4906,29 +3179,6 @@ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4906 { .dma_req = -1 } 3179 { .dma_req = -1 }
4907}; 3180};
4908 3181
4909static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4910 {
4911 .pa_start = 0x4806a000,
4912 .pa_end = 0x4806a0ff,
4913 .flags = ADDR_TYPE_RT
4914 },
4915 { }
4916};
4917
4918/* l4_per -> uart1 */
4919static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4920 .master = &omap44xx_l4_per_hwmod,
4921 .slave = &omap44xx_uart1_hwmod,
4922 .clk = "l4_div_ck",
4923 .addr = omap44xx_uart1_addrs,
4924 .user = OCP_USER_MPU | OCP_USER_SDMA,
4925};
4926
4927/* uart1 slave ports */
4928static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4929 &omap44xx_l4_per__uart1,
4930};
4931
4932static struct omap_hwmod omap44xx_uart1_hwmod = { 3182static struct omap_hwmod omap44xx_uart1_hwmod = {
4933 .name = "uart1", 3183 .name = "uart1",
4934 .class = &omap44xx_uart_hwmod_class, 3184 .class = &omap44xx_uart_hwmod_class,
@@ -4943,12 +3193,9 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
4943 .modulemode = MODULEMODE_SWCTRL, 3193 .modulemode = MODULEMODE_SWCTRL,
4944 }, 3194 },
4945 }, 3195 },
4946 .slaves = omap44xx_uart1_slaves,
4947 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4948}; 3196};
4949 3197
4950/* uart2 */ 3198/* uart2 */
4951static struct omap_hwmod omap44xx_uart2_hwmod;
4952static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { 3199static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4953 { .irq = 73 + OMAP44XX_IRQ_GIC_START }, 3200 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4954 { .irq = -1 } 3201 { .irq = -1 }
@@ -4960,29 +3207,6 @@ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4960 { .dma_req = -1 } 3207 { .dma_req = -1 }
4961}; 3208};
4962 3209
4963static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4964 {
4965 .pa_start = 0x4806c000,
4966 .pa_end = 0x4806c0ff,
4967 .flags = ADDR_TYPE_RT
4968 },
4969 { }
4970};
4971
4972/* l4_per -> uart2 */
4973static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4974 .master = &omap44xx_l4_per_hwmod,
4975 .slave = &omap44xx_uart2_hwmod,
4976 .clk = "l4_div_ck",
4977 .addr = omap44xx_uart2_addrs,
4978 .user = OCP_USER_MPU | OCP_USER_SDMA,
4979};
4980
4981/* uart2 slave ports */
4982static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4983 &omap44xx_l4_per__uart2,
4984};
4985
4986static struct omap_hwmod omap44xx_uart2_hwmod = { 3210static struct omap_hwmod omap44xx_uart2_hwmod = {
4987 .name = "uart2", 3211 .name = "uart2",
4988 .class = &omap44xx_uart_hwmod_class, 3212 .class = &omap44xx_uart_hwmod_class,
@@ -4997,12 +3221,9 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
4997 .modulemode = MODULEMODE_SWCTRL, 3221 .modulemode = MODULEMODE_SWCTRL,
4998 }, 3222 },
4999 }, 3223 },
5000 .slaves = omap44xx_uart2_slaves,
5001 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
5002}; 3224};
5003 3225
5004/* uart3 */ 3226/* uart3 */
5005static struct omap_hwmod omap44xx_uart3_hwmod;
5006static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { 3227static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
5007 { .irq = 74 + OMAP44XX_IRQ_GIC_START }, 3228 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
5008 { .irq = -1 } 3229 { .irq = -1 }
@@ -5014,29 +3235,6 @@ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
5014 { .dma_req = -1 } 3235 { .dma_req = -1 }
5015}; 3236};
5016 3237
5017static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5018 {
5019 .pa_start = 0x48020000,
5020 .pa_end = 0x480200ff,
5021 .flags = ADDR_TYPE_RT
5022 },
5023 { }
5024};
5025
5026/* l4_per -> uart3 */
5027static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5028 .master = &omap44xx_l4_per_hwmod,
5029 .slave = &omap44xx_uart3_hwmod,
5030 .clk = "l4_div_ck",
5031 .addr = omap44xx_uart3_addrs,
5032 .user = OCP_USER_MPU | OCP_USER_SDMA,
5033};
5034
5035/* uart3 slave ports */
5036static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
5037 &omap44xx_l4_per__uart3,
5038};
5039
5040static struct omap_hwmod omap44xx_uart3_hwmod = { 3238static struct omap_hwmod omap44xx_uart3_hwmod = {
5041 .name = "uart3", 3239 .name = "uart3",
5042 .class = &omap44xx_uart_hwmod_class, 3240 .class = &omap44xx_uart_hwmod_class,
@@ -5052,12 +3250,9 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
5052 .modulemode = MODULEMODE_SWCTRL, 3250 .modulemode = MODULEMODE_SWCTRL,
5053 }, 3251 },
5054 }, 3252 },
5055 .slaves = omap44xx_uart3_slaves,
5056 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
5057}; 3253};
5058 3254
5059/* uart4 */ 3255/* uart4 */
5060static struct omap_hwmod omap44xx_uart4_hwmod;
5061static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { 3256static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5062 { .irq = 70 + OMAP44XX_IRQ_GIC_START }, 3257 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5063 { .irq = -1 } 3258 { .irq = -1 }
@@ -5069,29 +3264,6 @@ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5069 { .dma_req = -1 } 3264 { .dma_req = -1 }
5070}; 3265};
5071 3266
5072static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5073 {
5074 .pa_start = 0x4806e000,
5075 .pa_end = 0x4806e0ff,
5076 .flags = ADDR_TYPE_RT
5077 },
5078 { }
5079};
5080
5081/* l4_per -> uart4 */
5082static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5083 .master = &omap44xx_l4_per_hwmod,
5084 .slave = &omap44xx_uart4_hwmod,
5085 .clk = "l4_div_ck",
5086 .addr = omap44xx_uart4_addrs,
5087 .user = OCP_USER_MPU | OCP_USER_SDMA,
5088};
5089
5090/* uart4 slave ports */
5091static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5092 &omap44xx_l4_per__uart4,
5093};
5094
5095static struct omap_hwmod omap44xx_uart4_hwmod = { 3267static struct omap_hwmod omap44xx_uart4_hwmod = {
5096 .name = "uart4", 3268 .name = "uart4",
5097 .class = &omap44xx_uart_hwmod_class, 3269 .class = &omap44xx_uart_hwmod_class,
@@ -5106,8 +3278,147 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
5106 .modulemode = MODULEMODE_SWCTRL, 3278 .modulemode = MODULEMODE_SWCTRL,
5107 }, 3279 },
5108 }, 3280 },
5109 .slaves = omap44xx_uart4_slaves, 3281};
5110 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), 3282
3283/*
3284 * 'usb_host_fs' class
3285 * full-speed usb host controller
3286 */
3287
3288/* The IP is not compliant to type1 / type2 scheme */
3289static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3290 .midle_shift = 4,
3291 .sidle_shift = 2,
3292 .srst_shift = 1,
3293};
3294
3295static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3296 .rev_offs = 0x0000,
3297 .sysc_offs = 0x0210,
3298 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3299 SYSC_HAS_SOFTRESET),
3300 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3301 SIDLE_SMART_WKUP),
3302 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
3303};
3304
3305static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3306 .name = "usb_host_fs",
3307 .sysc = &omap44xx_usb_host_fs_sysc,
3308};
3309
3310/* usb_host_fs */
3311static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3312 { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3313 { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3314 { .irq = -1 }
3315};
3316
3317static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3318 .name = "usb_host_fs",
3319 .class = &omap44xx_usb_host_fs_hwmod_class,
3320 .clkdm_name = "l3_init_clkdm",
3321 .mpu_irqs = omap44xx_usb_host_fs_irqs,
3322 .main_clk = "usb_host_fs_fck",
3323 .prcm = {
3324 .omap4 = {
3325 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3326 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3327 .modulemode = MODULEMODE_SWCTRL,
3328 },
3329 },
3330};
3331
3332/*
3333 * 'usb_host_hs' class
3334 * high-speed multi-port usb host controller
3335 */
3336
3337static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3338 .rev_offs = 0x0000,
3339 .sysc_offs = 0x0010,
3340 .syss_offs = 0x0014,
3341 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3342 SYSC_HAS_SOFTRESET),
3343 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3344 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3345 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3346 .sysc_fields = &omap_hwmod_sysc_type2,
3347};
3348
3349static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3350 .name = "usb_host_hs",
3351 .sysc = &omap44xx_usb_host_hs_sysc,
3352};
3353
3354/* usb_host_hs */
3355static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3356 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3357 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3358 { .irq = -1 }
3359};
3360
3361static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3362 .name = "usb_host_hs",
3363 .class = &omap44xx_usb_host_hs_hwmod_class,
3364 .clkdm_name = "l3_init_clkdm",
3365 .main_clk = "usb_host_hs_fck",
3366 .prcm = {
3367 .omap4 = {
3368 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3369 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3370 .modulemode = MODULEMODE_SWCTRL,
3371 },
3372 },
3373 .mpu_irqs = omap44xx_usb_host_hs_irqs,
3374
3375 /*
3376 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3377 * id: i660
3378 *
3379 * Description:
3380 * In the following configuration :
3381 * - USBHOST module is set to smart-idle mode
3382 * - PRCM asserts idle_req to the USBHOST module ( This typically
3383 * happens when the system is going to a low power mode : all ports
3384 * have been suspended, the master part of the USBHOST module has
3385 * entered the standby state, and SW has cut the functional clocks)
3386 * - an USBHOST interrupt occurs before the module is able to answer
3387 * idle_ack, typically a remote wakeup IRQ.
3388 * Then the USB HOST module will enter a deadlock situation where it
3389 * is no more accessible nor functional.
3390 *
3391 * Workaround:
3392 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3393 */
3394
3395 /*
3396 * Errata: USB host EHCI may stall when entering smart-standby mode
3397 * Id: i571
3398 *
3399 * Description:
3400 * When the USBHOST module is set to smart-standby mode, and when it is
3401 * ready to enter the standby state (i.e. all ports are suspended and
3402 * all attached devices are in suspend mode), then it can wrongly assert
3403 * the Mstandby signal too early while there are still some residual OCP
3404 * transactions ongoing. If this condition occurs, the internal state
3405 * machine may go to an undefined state and the USB link may be stuck
3406 * upon the next resume.
3407 *
3408 * Workaround:
3409 * Don't use smart standby; use only force standby,
3410 * hence HWMOD_SWSUP_MSTANDBY
3411 */
3412
3413 /*
3414 * During system boot; If the hwmod framework resets the module
3415 * the module will have smart idle settings; which can lead to deadlock
3416 * (above Errata Id:i660); so, dont reset the module during boot;
3417 * Use HWMOD_INIT_NO_RESET.
3418 */
3419
3420 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3421 HWMOD_INIT_NO_RESET,
5111}; 3422};
5112 3423
5113/* 3424/*
@@ -5140,34 +3451,6 @@ static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5140 { .irq = -1 } 3451 { .irq = -1 }
5141}; 3452};
5142 3453
5143/* usb_otg_hs master ports */
5144static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5145 &omap44xx_usb_otg_hs__l3_main_2,
5146};
5147
5148static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5149 {
5150 .pa_start = 0x4a0ab000,
5151 .pa_end = 0x4a0ab003,
5152 .flags = ADDR_TYPE_RT
5153 },
5154 { }
5155};
5156
5157/* l4_cfg -> usb_otg_hs */
5158static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5159 .master = &omap44xx_l4_cfg_hwmod,
5160 .slave = &omap44xx_usb_otg_hs_hwmod,
5161 .clk = "l4_div_ck",
5162 .addr = omap44xx_usb_otg_hs_addrs,
5163 .user = OCP_USER_MPU | OCP_USER_SDMA,
5164};
5165
5166/* usb_otg_hs slave ports */
5167static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5168 &omap44xx_l4_cfg__usb_otg_hs,
5169};
5170
5171static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { 3454static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5172 { .role = "xclk", .clk = "usb_otg_hs_xclk" }, 3455 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5173}; 3456};
@@ -5188,10 +3471,47 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5188 }, 3471 },
5189 .opt_clks = usb_otg_hs_opt_clks, 3472 .opt_clks = usb_otg_hs_opt_clks,
5190 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), 3473 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5191 .slaves = omap44xx_usb_otg_hs_slaves, 3474};
5192 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), 3475
5193 .masters = omap44xx_usb_otg_hs_masters, 3476/*
5194 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), 3477 * 'usb_tll_hs' class
3478 * usb_tll_hs module is the adapter on the usb_host_hs ports
3479 */
3480
3481static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3482 .rev_offs = 0x0000,
3483 .sysc_offs = 0x0010,
3484 .syss_offs = 0x0014,
3485 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3486 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3487 SYSC_HAS_AUTOIDLE),
3488 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3489 .sysc_fields = &omap_hwmod_sysc_type1,
3490};
3491
3492static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3493 .name = "usb_tll_hs",
3494 .sysc = &omap44xx_usb_tll_hs_sysc,
3495};
3496
3497static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3498 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3499 { .irq = -1 }
3500};
3501
3502static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3503 .name = "usb_tll_hs",
3504 .class = &omap44xx_usb_tll_hs_hwmod_class,
3505 .clkdm_name = "l3_init_clkdm",
3506 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
3507 .main_clk = "usb_tll_hs_ick",
3508 .prcm = {
3509 .omap4 = {
3510 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3511 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3512 .modulemode = MODULEMODE_HWCTRL,
3513 },
3514 },
5195}; 3515};
5196 3516
5197/* 3517/*
@@ -5215,38 +3535,15 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5215 .name = "wd_timer", 3535 .name = "wd_timer",
5216 .sysc = &omap44xx_wd_timer_sysc, 3536 .sysc = &omap44xx_wd_timer_sysc,
5217 .pre_shutdown = &omap2_wd_timer_disable, 3537 .pre_shutdown = &omap2_wd_timer_disable,
3538 .reset = &omap2_wd_timer_reset,
5218}; 3539};
5219 3540
5220/* wd_timer2 */ 3541/* wd_timer2 */
5221static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5222static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { 3542static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5223 { .irq = 80 + OMAP44XX_IRQ_GIC_START }, 3543 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5224 { .irq = -1 } 3544 { .irq = -1 }
5225}; 3545};
5226 3546
5227static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5228 {
5229 .pa_start = 0x4a314000,
5230 .pa_end = 0x4a31407f,
5231 .flags = ADDR_TYPE_RT
5232 },
5233 { }
5234};
5235
5236/* l4_wkup -> wd_timer2 */
5237static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5238 .master = &omap44xx_l4_wkup_hwmod,
5239 .slave = &omap44xx_wd_timer2_hwmod,
5240 .clk = "l4_wkup_clk_mux_ck",
5241 .addr = omap44xx_wd_timer2_addrs,
5242 .user = OCP_USER_MPU | OCP_USER_SDMA,
5243};
5244
5245/* wd_timer2 slave ports */
5246static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5247 &omap44xx_l4_wkup__wd_timer2,
5248};
5249
5250static struct omap_hwmod omap44xx_wd_timer2_hwmod = { 3547static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5251 .name = "wd_timer2", 3548 .name = "wd_timer2",
5252 .class = &omap44xx_wd_timer_hwmod_class, 3549 .class = &omap44xx_wd_timer_hwmod_class,
@@ -5260,106 +3557,2308 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5260 .modulemode = MODULEMODE_SWCTRL, 3557 .modulemode = MODULEMODE_SWCTRL,
5261 }, 3558 },
5262 }, 3559 },
5263 .slaves = omap44xx_wd_timer2_slaves,
5264 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5265}; 3560};
5266 3561
5267/* wd_timer3 */ 3562/* wd_timer3 */
5268static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5269static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { 3563static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5270 { .irq = 36 + OMAP44XX_IRQ_GIC_START }, 3564 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5271 { .irq = -1 } 3565 { .irq = -1 }
5272}; 3566};
5273 3567
5274static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { 3568static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3569 .name = "wd_timer3",
3570 .class = &omap44xx_wd_timer_hwmod_class,
3571 .clkdm_name = "abe_clkdm",
3572 .mpu_irqs = omap44xx_wd_timer3_irqs,
3573 .main_clk = "wd_timer3_fck",
3574 .prcm = {
3575 .omap4 = {
3576 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3577 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3578 .modulemode = MODULEMODE_SWCTRL,
3579 },
3580 },
3581};
3582
3583
3584/*
3585 * interfaces
3586 */
3587
3588static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
5275 { 3589 {
5276 .pa_start = 0x40130000, 3590 .pa_start = 0x4a204000,
5277 .pa_end = 0x4013007f, 3591 .pa_end = 0x4a2040ff,
5278 .flags = ADDR_TYPE_RT 3592 .flags = ADDR_TYPE_RT
5279 }, 3593 },
5280 { } 3594 { }
5281}; 3595};
5282 3596
5283/* l4_abe -> wd_timer3 */ 3597/* c2c -> c2c_target_fw */
5284static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { 3598static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3599 .master = &omap44xx_c2c_hwmod,
3600 .slave = &omap44xx_c2c_target_fw_hwmod,
3601 .clk = "div_core_ck",
3602 .addr = omap44xx_c2c_target_fw_addrs,
3603 .user = OCP_USER_MPU,
3604};
3605
3606/* l4_cfg -> c2c_target_fw */
3607static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3608 .master = &omap44xx_l4_cfg_hwmod,
3609 .slave = &omap44xx_c2c_target_fw_hwmod,
3610 .clk = "l4_div_ck",
3611 .user = OCP_USER_MPU | OCP_USER_SDMA,
3612};
3613
3614/* l3_main_1 -> dmm */
3615static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3616 .master = &omap44xx_l3_main_1_hwmod,
3617 .slave = &omap44xx_dmm_hwmod,
3618 .clk = "l3_div_ck",
3619 .user = OCP_USER_SDMA,
3620};
3621
3622static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3623 {
3624 .pa_start = 0x4e000000,
3625 .pa_end = 0x4e0007ff,
3626 .flags = ADDR_TYPE_RT
3627 },
3628 { }
3629};
3630
3631/* mpu -> dmm */
3632static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3633 .master = &omap44xx_mpu_hwmod,
3634 .slave = &omap44xx_dmm_hwmod,
3635 .clk = "l3_div_ck",
3636 .addr = omap44xx_dmm_addrs,
3637 .user = OCP_USER_MPU,
3638};
3639
3640/* c2c -> emif_fw */
3641static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3642 .master = &omap44xx_c2c_hwmod,
3643 .slave = &omap44xx_emif_fw_hwmod,
3644 .clk = "div_core_ck",
3645 .user = OCP_USER_MPU | OCP_USER_SDMA,
3646};
3647
3648/* dmm -> emif_fw */
3649static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3650 .master = &omap44xx_dmm_hwmod,
3651 .slave = &omap44xx_emif_fw_hwmod,
3652 .clk = "l3_div_ck",
3653 .user = OCP_USER_MPU | OCP_USER_SDMA,
3654};
3655
3656static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3657 {
3658 .pa_start = 0x4a20c000,
3659 .pa_end = 0x4a20c0ff,
3660 .flags = ADDR_TYPE_RT
3661 },
3662 { }
3663};
3664
3665/* l4_cfg -> emif_fw */
3666static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3667 .master = &omap44xx_l4_cfg_hwmod,
3668 .slave = &omap44xx_emif_fw_hwmod,
3669 .clk = "l4_div_ck",
3670 .addr = omap44xx_emif_fw_addrs,
3671 .user = OCP_USER_MPU,
3672};
3673
3674/* iva -> l3_instr */
3675static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3676 .master = &omap44xx_iva_hwmod,
3677 .slave = &omap44xx_l3_instr_hwmod,
3678 .clk = "l3_div_ck",
3679 .user = OCP_USER_MPU | OCP_USER_SDMA,
3680};
3681
3682/* l3_main_3 -> l3_instr */
3683static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3684 .master = &omap44xx_l3_main_3_hwmod,
3685 .slave = &omap44xx_l3_instr_hwmod,
3686 .clk = "l3_div_ck",
3687 .user = OCP_USER_MPU | OCP_USER_SDMA,
3688};
3689
3690/* ocp_wp_noc -> l3_instr */
3691static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3692 .master = &omap44xx_ocp_wp_noc_hwmod,
3693 .slave = &omap44xx_l3_instr_hwmod,
3694 .clk = "l3_div_ck",
3695 .user = OCP_USER_MPU | OCP_USER_SDMA,
3696};
3697
3698/* dsp -> l3_main_1 */
3699static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3700 .master = &omap44xx_dsp_hwmod,
3701 .slave = &omap44xx_l3_main_1_hwmod,
3702 .clk = "l3_div_ck",
3703 .user = OCP_USER_MPU | OCP_USER_SDMA,
3704};
3705
3706/* dss -> l3_main_1 */
3707static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3708 .master = &omap44xx_dss_hwmod,
3709 .slave = &omap44xx_l3_main_1_hwmod,
3710 .clk = "l3_div_ck",
3711 .user = OCP_USER_MPU | OCP_USER_SDMA,
3712};
3713
3714/* l3_main_2 -> l3_main_1 */
3715static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3716 .master = &omap44xx_l3_main_2_hwmod,
3717 .slave = &omap44xx_l3_main_1_hwmod,
3718 .clk = "l3_div_ck",
3719 .user = OCP_USER_MPU | OCP_USER_SDMA,
3720};
3721
3722/* l4_cfg -> l3_main_1 */
3723static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3724 .master = &omap44xx_l4_cfg_hwmod,
3725 .slave = &omap44xx_l3_main_1_hwmod,
3726 .clk = "l4_div_ck",
3727 .user = OCP_USER_MPU | OCP_USER_SDMA,
3728};
3729
3730/* mmc1 -> l3_main_1 */
3731static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3732 .master = &omap44xx_mmc1_hwmod,
3733 .slave = &omap44xx_l3_main_1_hwmod,
3734 .clk = "l3_div_ck",
3735 .user = OCP_USER_MPU | OCP_USER_SDMA,
3736};
3737
3738/* mmc2 -> l3_main_1 */
3739static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3740 .master = &omap44xx_mmc2_hwmod,
3741 .slave = &omap44xx_l3_main_1_hwmod,
3742 .clk = "l3_div_ck",
3743 .user = OCP_USER_MPU | OCP_USER_SDMA,
3744};
3745
3746static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3747 {
3748 .pa_start = 0x44000000,
3749 .pa_end = 0x44000fff,
3750 .flags = ADDR_TYPE_RT
3751 },
3752 { }
3753};
3754
3755/* mpu -> l3_main_1 */
3756static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3757 .master = &omap44xx_mpu_hwmod,
3758 .slave = &omap44xx_l3_main_1_hwmod,
3759 .clk = "l3_div_ck",
3760 .addr = omap44xx_l3_main_1_addrs,
3761 .user = OCP_USER_MPU,
3762};
3763
3764/* c2c_target_fw -> l3_main_2 */
3765static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3766 .master = &omap44xx_c2c_target_fw_hwmod,
3767 .slave = &omap44xx_l3_main_2_hwmod,
3768 .clk = "l3_div_ck",
3769 .user = OCP_USER_MPU | OCP_USER_SDMA,
3770};
3771
3772/* debugss -> l3_main_2 */
3773static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3774 .master = &omap44xx_debugss_hwmod,
3775 .slave = &omap44xx_l3_main_2_hwmod,
3776 .clk = "dbgclk_mux_ck",
3777 .user = OCP_USER_MPU | OCP_USER_SDMA,
3778};
3779
3780/* dma_system -> l3_main_2 */
3781static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3782 .master = &omap44xx_dma_system_hwmod,
3783 .slave = &omap44xx_l3_main_2_hwmod,
3784 .clk = "l3_div_ck",
3785 .user = OCP_USER_MPU | OCP_USER_SDMA,
3786};
3787
3788/* fdif -> l3_main_2 */
3789static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3790 .master = &omap44xx_fdif_hwmod,
3791 .slave = &omap44xx_l3_main_2_hwmod,
3792 .clk = "l3_div_ck",
3793 .user = OCP_USER_MPU | OCP_USER_SDMA,
3794};
3795
3796/* gpu -> l3_main_2 */
3797static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3798 .master = &omap44xx_gpu_hwmod,
3799 .slave = &omap44xx_l3_main_2_hwmod,
3800 .clk = "l3_div_ck",
3801 .user = OCP_USER_MPU | OCP_USER_SDMA,
3802};
3803
3804/* hsi -> l3_main_2 */
3805static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3806 .master = &omap44xx_hsi_hwmod,
3807 .slave = &omap44xx_l3_main_2_hwmod,
3808 .clk = "l3_div_ck",
3809 .user = OCP_USER_MPU | OCP_USER_SDMA,
3810};
3811
3812/* ipu -> l3_main_2 */
3813static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3814 .master = &omap44xx_ipu_hwmod,
3815 .slave = &omap44xx_l3_main_2_hwmod,
3816 .clk = "l3_div_ck",
3817 .user = OCP_USER_MPU | OCP_USER_SDMA,
3818};
3819
3820/* iss -> l3_main_2 */
3821static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3822 .master = &omap44xx_iss_hwmod,
3823 .slave = &omap44xx_l3_main_2_hwmod,
3824 .clk = "l3_div_ck",
3825 .user = OCP_USER_MPU | OCP_USER_SDMA,
3826};
3827
3828/* iva -> l3_main_2 */
3829static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3830 .master = &omap44xx_iva_hwmod,
3831 .slave = &omap44xx_l3_main_2_hwmod,
3832 .clk = "l3_div_ck",
3833 .user = OCP_USER_MPU | OCP_USER_SDMA,
3834};
3835
3836static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3837 {
3838 .pa_start = 0x44800000,
3839 .pa_end = 0x44801fff,
3840 .flags = ADDR_TYPE_RT
3841 },
3842 { }
3843};
3844
3845/* l3_main_1 -> l3_main_2 */
3846static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3847 .master = &omap44xx_l3_main_1_hwmod,
3848 .slave = &omap44xx_l3_main_2_hwmod,
3849 .clk = "l3_div_ck",
3850 .addr = omap44xx_l3_main_2_addrs,
3851 .user = OCP_USER_MPU,
3852};
3853
3854/* l4_cfg -> l3_main_2 */
3855static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3856 .master = &omap44xx_l4_cfg_hwmod,
3857 .slave = &omap44xx_l3_main_2_hwmod,
3858 .clk = "l4_div_ck",
3859 .user = OCP_USER_MPU | OCP_USER_SDMA,
3860};
3861
3862/* usb_host_fs -> l3_main_2 */
3863static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3864 .master = &omap44xx_usb_host_fs_hwmod,
3865 .slave = &omap44xx_l3_main_2_hwmod,
3866 .clk = "l3_div_ck",
3867 .user = OCP_USER_MPU | OCP_USER_SDMA,
3868};
3869
3870/* usb_host_hs -> l3_main_2 */
3871static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3872 .master = &omap44xx_usb_host_hs_hwmod,
3873 .slave = &omap44xx_l3_main_2_hwmod,
3874 .clk = "l3_div_ck",
3875 .user = OCP_USER_MPU | OCP_USER_SDMA,
3876};
3877
3878/* usb_otg_hs -> l3_main_2 */
3879static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3880 .master = &omap44xx_usb_otg_hs_hwmod,
3881 .slave = &omap44xx_l3_main_2_hwmod,
3882 .clk = "l3_div_ck",
3883 .user = OCP_USER_MPU | OCP_USER_SDMA,
3884};
3885
3886static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3887 {
3888 .pa_start = 0x45000000,
3889 .pa_end = 0x45000fff,
3890 .flags = ADDR_TYPE_RT
3891 },
3892 { }
3893};
3894
3895/* l3_main_1 -> l3_main_3 */
3896static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3897 .master = &omap44xx_l3_main_1_hwmod,
3898 .slave = &omap44xx_l3_main_3_hwmod,
3899 .clk = "l3_div_ck",
3900 .addr = omap44xx_l3_main_3_addrs,
3901 .user = OCP_USER_MPU,
3902};
3903
3904/* l3_main_2 -> l3_main_3 */
3905static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3906 .master = &omap44xx_l3_main_2_hwmod,
3907 .slave = &omap44xx_l3_main_3_hwmod,
3908 .clk = "l3_div_ck",
3909 .user = OCP_USER_MPU | OCP_USER_SDMA,
3910};
3911
3912/* l4_cfg -> l3_main_3 */
3913static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3914 .master = &omap44xx_l4_cfg_hwmod,
3915 .slave = &omap44xx_l3_main_3_hwmod,
3916 .clk = "l4_div_ck",
3917 .user = OCP_USER_MPU | OCP_USER_SDMA,
3918};
3919
3920/* aess -> l4_abe */
3921static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3922 .master = &omap44xx_aess_hwmod,
3923 .slave = &omap44xx_l4_abe_hwmod,
3924 .clk = "ocp_abe_iclk",
3925 .user = OCP_USER_MPU | OCP_USER_SDMA,
3926};
3927
3928/* dsp -> l4_abe */
3929static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3930 .master = &omap44xx_dsp_hwmod,
3931 .slave = &omap44xx_l4_abe_hwmod,
3932 .clk = "ocp_abe_iclk",
3933 .user = OCP_USER_MPU | OCP_USER_SDMA,
3934};
3935
3936/* l3_main_1 -> l4_abe */
3937static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3938 .master = &omap44xx_l3_main_1_hwmod,
3939 .slave = &omap44xx_l4_abe_hwmod,
3940 .clk = "l3_div_ck",
3941 .user = OCP_USER_MPU | OCP_USER_SDMA,
3942};
3943
3944/* mpu -> l4_abe */
3945static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3946 .master = &omap44xx_mpu_hwmod,
3947 .slave = &omap44xx_l4_abe_hwmod,
3948 .clk = "ocp_abe_iclk",
3949 .user = OCP_USER_MPU | OCP_USER_SDMA,
3950};
3951
3952/* l3_main_1 -> l4_cfg */
3953static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3954 .master = &omap44xx_l3_main_1_hwmod,
3955 .slave = &omap44xx_l4_cfg_hwmod,
3956 .clk = "l3_div_ck",
3957 .user = OCP_USER_MPU | OCP_USER_SDMA,
3958};
3959
3960/* l3_main_2 -> l4_per */
3961static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3962 .master = &omap44xx_l3_main_2_hwmod,
3963 .slave = &omap44xx_l4_per_hwmod,
3964 .clk = "l3_div_ck",
3965 .user = OCP_USER_MPU | OCP_USER_SDMA,
3966};
3967
3968/* l4_cfg -> l4_wkup */
3969static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3970 .master = &omap44xx_l4_cfg_hwmod,
3971 .slave = &omap44xx_l4_wkup_hwmod,
3972 .clk = "l4_div_ck",
3973 .user = OCP_USER_MPU | OCP_USER_SDMA,
3974};
3975
3976/* mpu -> mpu_private */
3977static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3978 .master = &omap44xx_mpu_hwmod,
3979 .slave = &omap44xx_mpu_private_hwmod,
3980 .clk = "l3_div_ck",
3981 .user = OCP_USER_MPU | OCP_USER_SDMA,
3982};
3983
3984static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3985 {
3986 .pa_start = 0x4a102000,
3987 .pa_end = 0x4a10207f,
3988 .flags = ADDR_TYPE_RT
3989 },
3990 { }
3991};
3992
3993/* l4_cfg -> ocp_wp_noc */
3994static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3995 .master = &omap44xx_l4_cfg_hwmod,
3996 .slave = &omap44xx_ocp_wp_noc_hwmod,
3997 .clk = "l4_div_ck",
3998 .addr = omap44xx_ocp_wp_noc_addrs,
3999 .user = OCP_USER_MPU | OCP_USER_SDMA,
4000};
4001
4002static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4003 {
4004 .pa_start = 0x401f1000,
4005 .pa_end = 0x401f13ff,
4006 .flags = ADDR_TYPE_RT
4007 },
4008 { }
4009};
4010
4011/* l4_abe -> aess */
4012static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
5285 .master = &omap44xx_l4_abe_hwmod, 4013 .master = &omap44xx_l4_abe_hwmod,
5286 .slave = &omap44xx_wd_timer3_hwmod, 4014 .slave = &omap44xx_aess_hwmod,
5287 .clk = "ocp_abe_iclk", 4015 .clk = "ocp_abe_iclk",
5288 .addr = omap44xx_wd_timer3_addrs, 4016 .addr = omap44xx_aess_addrs,
5289 .user = OCP_USER_MPU, 4017 .user = OCP_USER_MPU,
5290}; 4018};
5291 4019
5292static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { 4020static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
5293 { 4021 {
5294 .pa_start = 0x49030000, 4022 .pa_start = 0x490f1000,
5295 .pa_end = 0x4903007f, 4023 .pa_end = 0x490f13ff,
5296 .flags = ADDR_TYPE_RT 4024 .flags = ADDR_TYPE_RT
5297 }, 4025 },
5298 { } 4026 { }
5299}; 4027};
5300 4028
5301/* l4_abe -> wd_timer3 (dma) */ 4029/* l4_abe -> aess (dma) */
5302static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { 4030static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
5303 .master = &omap44xx_l4_abe_hwmod, 4031 .master = &omap44xx_l4_abe_hwmod,
5304 .slave = &omap44xx_wd_timer3_hwmod, 4032 .slave = &omap44xx_aess_hwmod,
5305 .clk = "ocp_abe_iclk", 4033 .clk = "ocp_abe_iclk",
5306 .addr = omap44xx_wd_timer3_dma_addrs, 4034 .addr = omap44xx_aess_dma_addrs,
5307 .user = OCP_USER_SDMA, 4035 .user = OCP_USER_SDMA,
5308}; 4036};
5309 4037
5310/* wd_timer3 slave ports */ 4038/* l3_main_2 -> c2c */
5311static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { 4039static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
5312 &omap44xx_l4_abe__wd_timer3, 4040 .master = &omap44xx_l3_main_2_hwmod,
5313 &omap44xx_l4_abe__wd_timer3_dma, 4041 .slave = &omap44xx_c2c_hwmod,
4042 .clk = "l3_div_ck",
4043 .user = OCP_USER_MPU | OCP_USER_SDMA,
5314}; 4044};
5315 4045
5316static struct omap_hwmod omap44xx_wd_timer3_hwmod = { 4046static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
5317 .name = "wd_timer3", 4047 {
5318 .class = &omap44xx_wd_timer_hwmod_class, 4048 .pa_start = 0x4a304000,
5319 .clkdm_name = "abe_clkdm", 4049 .pa_end = 0x4a30401f,
5320 .mpu_irqs = omap44xx_wd_timer3_irqs, 4050 .flags = ADDR_TYPE_RT
5321 .main_clk = "wd_timer3_fck",
5322 .prcm = {
5323 .omap4 = {
5324 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5325 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5326 .modulemode = MODULEMODE_SWCTRL,
5327 },
5328 }, 4051 },
5329 .slaves = omap44xx_wd_timer3_slaves, 4052 { }
5330 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5331}; 4053};
5332 4054
5333/* 4055/* l4_wkup -> counter_32k */
5334 * 'usb_host_hs' class 4056static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
5335 * high-speed multi-port usb host controller 4057 .master = &omap44xx_l4_wkup_hwmod,
5336 */ 4058 .slave = &omap44xx_counter_32k_hwmod,
5337static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { 4059 .clk = "l4_wkup_clk_mux_ck",
5338 .master = &omap44xx_usb_host_hs_hwmod, 4060 .addr = omap44xx_counter_32k_addrs,
5339 .slave = &omap44xx_l3_main_2_hwmod, 4061 .user = OCP_USER_MPU | OCP_USER_SDMA,
4062};
4063
4064static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4065 {
4066 .pa_start = 0x4a002000,
4067 .pa_end = 0x4a0027ff,
4068 .flags = ADDR_TYPE_RT
4069 },
4070 { }
4071};
4072
4073/* l4_cfg -> ctrl_module_core */
4074static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4075 .master = &omap44xx_l4_cfg_hwmod,
4076 .slave = &omap44xx_ctrl_module_core_hwmod,
4077 .clk = "l4_div_ck",
4078 .addr = omap44xx_ctrl_module_core_addrs,
4079 .user = OCP_USER_MPU | OCP_USER_SDMA,
4080};
4081
4082static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4083 {
4084 .pa_start = 0x4a100000,
4085 .pa_end = 0x4a1007ff,
4086 .flags = ADDR_TYPE_RT
4087 },
4088 { }
4089};
4090
4091/* l4_cfg -> ctrl_module_pad_core */
4092static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4093 .master = &omap44xx_l4_cfg_hwmod,
4094 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
4095 .clk = "l4_div_ck",
4096 .addr = omap44xx_ctrl_module_pad_core_addrs,
4097 .user = OCP_USER_MPU | OCP_USER_SDMA,
4098};
4099
4100static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4101 {
4102 .pa_start = 0x4a30c000,
4103 .pa_end = 0x4a30c7ff,
4104 .flags = ADDR_TYPE_RT
4105 },
4106 { }
4107};
4108
4109/* l4_wkup -> ctrl_module_wkup */
4110static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4111 .master = &omap44xx_l4_wkup_hwmod,
4112 .slave = &omap44xx_ctrl_module_wkup_hwmod,
4113 .clk = "l4_wkup_clk_mux_ck",
4114 .addr = omap44xx_ctrl_module_wkup_addrs,
4115 .user = OCP_USER_MPU | OCP_USER_SDMA,
4116};
4117
4118static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4119 {
4120 .pa_start = 0x4a31e000,
4121 .pa_end = 0x4a31e7ff,
4122 .flags = ADDR_TYPE_RT
4123 },
4124 { }
4125};
4126
4127/* l4_wkup -> ctrl_module_pad_wkup */
4128static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4129 .master = &omap44xx_l4_wkup_hwmod,
4130 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
4131 .clk = "l4_wkup_clk_mux_ck",
4132 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
4133 .user = OCP_USER_MPU | OCP_USER_SDMA,
4134};
4135
4136static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4137 {
4138 .pa_start = 0x54160000,
4139 .pa_end = 0x54167fff,
4140 .flags = ADDR_TYPE_RT
4141 },
4142 { }
4143};
4144
4145/* l3_instr -> debugss */
4146static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4147 .master = &omap44xx_l3_instr_hwmod,
4148 .slave = &omap44xx_debugss_hwmod,
5340 .clk = "l3_div_ck", 4149 .clk = "l3_div_ck",
4150 .addr = omap44xx_debugss_addrs,
5341 .user = OCP_USER_MPU | OCP_USER_SDMA, 4151 .user = OCP_USER_MPU | OCP_USER_SDMA,
5342}; 4152};
5343 4153
5344static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { 4154static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
5345 .rev_offs = 0x0000, 4155 {
5346 .sysc_offs = 0x0010, 4156 .pa_start = 0x4a056000,
5347 .syss_offs = 0x0014, 4157 .pa_end = 0x4a056fff,
5348 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | 4158 .flags = ADDR_TYPE_RT
5349 SYSC_HAS_SOFTRESET), 4159 },
5350 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 4160 { }
5351 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5352 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5353 .sysc_fields = &omap_hwmod_sysc_type2,
5354}; 4161};
5355 4162
5356static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { 4163/* l4_cfg -> dma_system */
5357 .name = "usb_host_hs", 4164static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
5358 .sysc = &omap44xx_usb_host_hs_sysc, 4165 .master = &omap44xx_l4_cfg_hwmod,
4166 .slave = &omap44xx_dma_system_hwmod,
4167 .clk = "l4_div_ck",
4168 .addr = omap44xx_dma_system_addrs,
4169 .user = OCP_USER_MPU | OCP_USER_SDMA,
5359}; 4170};
5360 4171
5361static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = { 4172static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
5362 &omap44xx_usb_host_hs__l3_main_2, 4173 {
4174 .name = "mpu",
4175 .pa_start = 0x4012e000,
4176 .pa_end = 0x4012e07f,
4177 .flags = ADDR_TYPE_RT
4178 },
4179 { }
4180};
4181
4182/* l4_abe -> dmic */
4183static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4184 .master = &omap44xx_l4_abe_hwmod,
4185 .slave = &omap44xx_dmic_hwmod,
4186 .clk = "ocp_abe_iclk",
4187 .addr = omap44xx_dmic_addrs,
4188 .user = OCP_USER_MPU,
4189};
4190
4191static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4192 {
4193 .name = "dma",
4194 .pa_start = 0x4902e000,
4195 .pa_end = 0x4902e07f,
4196 .flags = ADDR_TYPE_RT
4197 },
4198 { }
4199};
4200
4201/* l4_abe -> dmic (dma) */
4202static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4203 .master = &omap44xx_l4_abe_hwmod,
4204 .slave = &omap44xx_dmic_hwmod,
4205 .clk = "ocp_abe_iclk",
4206 .addr = omap44xx_dmic_dma_addrs,
4207 .user = OCP_USER_SDMA,
4208};
4209
4210/* dsp -> iva */
4211static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4212 .master = &omap44xx_dsp_hwmod,
4213 .slave = &omap44xx_iva_hwmod,
4214 .clk = "dpll_iva_m5x2_ck",
4215 .user = OCP_USER_DSP,
4216};
4217
4218/* dsp -> sl2if */
4219static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4220 .master = &omap44xx_dsp_hwmod,
4221 .slave = &omap44xx_sl2if_hwmod,
4222 .clk = "dpll_iva_m5x2_ck",
4223 .user = OCP_USER_DSP,
4224};
4225
4226/* l4_cfg -> dsp */
4227static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4228 .master = &omap44xx_l4_cfg_hwmod,
4229 .slave = &omap44xx_dsp_hwmod,
4230 .clk = "l4_div_ck",
4231 .user = OCP_USER_MPU | OCP_USER_SDMA,
4232};
4233
4234static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4235 {
4236 .pa_start = 0x58000000,
4237 .pa_end = 0x5800007f,
4238 .flags = ADDR_TYPE_RT
4239 },
4240 { }
4241};
4242
4243/* l3_main_2 -> dss */
4244static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4245 .master = &omap44xx_l3_main_2_hwmod,
4246 .slave = &omap44xx_dss_hwmod,
4247 .clk = "dss_fck",
4248 .addr = omap44xx_dss_dma_addrs,
4249 .user = OCP_USER_SDMA,
4250};
4251
4252static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4253 {
4254 .pa_start = 0x48040000,
4255 .pa_end = 0x4804007f,
4256 .flags = ADDR_TYPE_RT
4257 },
4258 { }
4259};
4260
4261/* l4_per -> dss */
4262static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4263 .master = &omap44xx_l4_per_hwmod,
4264 .slave = &omap44xx_dss_hwmod,
4265 .clk = "l4_div_ck",
4266 .addr = omap44xx_dss_addrs,
4267 .user = OCP_USER_MPU,
4268};
4269
4270static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4271 {
4272 .pa_start = 0x58001000,
4273 .pa_end = 0x58001fff,
4274 .flags = ADDR_TYPE_RT
4275 },
4276 { }
4277};
4278
4279/* l3_main_2 -> dss_dispc */
4280static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4281 .master = &omap44xx_l3_main_2_hwmod,
4282 .slave = &omap44xx_dss_dispc_hwmod,
4283 .clk = "dss_fck",
4284 .addr = omap44xx_dss_dispc_dma_addrs,
4285 .user = OCP_USER_SDMA,
4286};
4287
4288static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4289 {
4290 .pa_start = 0x48041000,
4291 .pa_end = 0x48041fff,
4292 .flags = ADDR_TYPE_RT
4293 },
4294 { }
4295};
4296
4297/* l4_per -> dss_dispc */
4298static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4299 .master = &omap44xx_l4_per_hwmod,
4300 .slave = &omap44xx_dss_dispc_hwmod,
4301 .clk = "l4_div_ck",
4302 .addr = omap44xx_dss_dispc_addrs,
4303 .user = OCP_USER_MPU,
4304};
4305
4306static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4307 {
4308 .pa_start = 0x58004000,
4309 .pa_end = 0x580041ff,
4310 .flags = ADDR_TYPE_RT
4311 },
4312 { }
4313};
4314
4315/* l3_main_2 -> dss_dsi1 */
4316static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4317 .master = &omap44xx_l3_main_2_hwmod,
4318 .slave = &omap44xx_dss_dsi1_hwmod,
4319 .clk = "dss_fck",
4320 .addr = omap44xx_dss_dsi1_dma_addrs,
4321 .user = OCP_USER_SDMA,
4322};
4323
4324static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4325 {
4326 .pa_start = 0x48044000,
4327 .pa_end = 0x480441ff,
4328 .flags = ADDR_TYPE_RT
4329 },
4330 { }
4331};
4332
4333/* l4_per -> dss_dsi1 */
4334static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4335 .master = &omap44xx_l4_per_hwmod,
4336 .slave = &omap44xx_dss_dsi1_hwmod,
4337 .clk = "l4_div_ck",
4338 .addr = omap44xx_dss_dsi1_addrs,
4339 .user = OCP_USER_MPU,
4340};
4341
4342static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4343 {
4344 .pa_start = 0x58005000,
4345 .pa_end = 0x580051ff,
4346 .flags = ADDR_TYPE_RT
4347 },
4348 { }
4349};
4350
4351/* l3_main_2 -> dss_dsi2 */
4352static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4353 .master = &omap44xx_l3_main_2_hwmod,
4354 .slave = &omap44xx_dss_dsi2_hwmod,
4355 .clk = "dss_fck",
4356 .addr = omap44xx_dss_dsi2_dma_addrs,
4357 .user = OCP_USER_SDMA,
4358};
4359
4360static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4361 {
4362 .pa_start = 0x48045000,
4363 .pa_end = 0x480451ff,
4364 .flags = ADDR_TYPE_RT
4365 },
4366 { }
4367};
4368
4369/* l4_per -> dss_dsi2 */
4370static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4371 .master = &omap44xx_l4_per_hwmod,
4372 .slave = &omap44xx_dss_dsi2_hwmod,
4373 .clk = "l4_div_ck",
4374 .addr = omap44xx_dss_dsi2_addrs,
4375 .user = OCP_USER_MPU,
4376};
4377
4378static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4379 {
4380 .pa_start = 0x58006000,
4381 .pa_end = 0x58006fff,
4382 .flags = ADDR_TYPE_RT
4383 },
4384 { }
4385};
4386
4387/* l3_main_2 -> dss_hdmi */
4388static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4389 .master = &omap44xx_l3_main_2_hwmod,
4390 .slave = &omap44xx_dss_hdmi_hwmod,
4391 .clk = "dss_fck",
4392 .addr = omap44xx_dss_hdmi_dma_addrs,
4393 .user = OCP_USER_SDMA,
4394};
4395
4396static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4397 {
4398 .pa_start = 0x48046000,
4399 .pa_end = 0x48046fff,
4400 .flags = ADDR_TYPE_RT
4401 },
4402 { }
4403};
4404
4405/* l4_per -> dss_hdmi */
4406static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4407 .master = &omap44xx_l4_per_hwmod,
4408 .slave = &omap44xx_dss_hdmi_hwmod,
4409 .clk = "l4_div_ck",
4410 .addr = omap44xx_dss_hdmi_addrs,
4411 .user = OCP_USER_MPU,
4412};
4413
4414static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4415 {
4416 .pa_start = 0x58002000,
4417 .pa_end = 0x580020ff,
4418 .flags = ADDR_TYPE_RT
4419 },
4420 { }
4421};
4422
4423/* l3_main_2 -> dss_rfbi */
4424static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4425 .master = &omap44xx_l3_main_2_hwmod,
4426 .slave = &omap44xx_dss_rfbi_hwmod,
4427 .clk = "dss_fck",
4428 .addr = omap44xx_dss_rfbi_dma_addrs,
4429 .user = OCP_USER_SDMA,
4430};
4431
4432static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4433 {
4434 .pa_start = 0x48042000,
4435 .pa_end = 0x480420ff,
4436 .flags = ADDR_TYPE_RT
4437 },
4438 { }
4439};
4440
4441/* l4_per -> dss_rfbi */
4442static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4443 .master = &omap44xx_l4_per_hwmod,
4444 .slave = &omap44xx_dss_rfbi_hwmod,
4445 .clk = "l4_div_ck",
4446 .addr = omap44xx_dss_rfbi_addrs,
4447 .user = OCP_USER_MPU,
4448};
4449
4450static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4451 {
4452 .pa_start = 0x58003000,
4453 .pa_end = 0x580030ff,
4454 .flags = ADDR_TYPE_RT
4455 },
4456 { }
4457};
4458
4459/* l3_main_2 -> dss_venc */
4460static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4461 .master = &omap44xx_l3_main_2_hwmod,
4462 .slave = &omap44xx_dss_venc_hwmod,
4463 .clk = "dss_fck",
4464 .addr = omap44xx_dss_venc_dma_addrs,
4465 .user = OCP_USER_SDMA,
4466};
4467
4468static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4469 {
4470 .pa_start = 0x48043000,
4471 .pa_end = 0x480430ff,
4472 .flags = ADDR_TYPE_RT
4473 },
4474 { }
4475};
4476
4477/* l4_per -> dss_venc */
4478static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4479 .master = &omap44xx_l4_per_hwmod,
4480 .slave = &omap44xx_dss_venc_hwmod,
4481 .clk = "l4_div_ck",
4482 .addr = omap44xx_dss_venc_addrs,
4483 .user = OCP_USER_MPU,
4484};
4485
4486static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4487 {
4488 .pa_start = 0x48078000,
4489 .pa_end = 0x48078fff,
4490 .flags = ADDR_TYPE_RT
4491 },
4492 { }
4493};
4494
4495/* l4_per -> elm */
4496static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4497 .master = &omap44xx_l4_per_hwmod,
4498 .slave = &omap44xx_elm_hwmod,
4499 .clk = "l4_div_ck",
4500 .addr = omap44xx_elm_addrs,
4501 .user = OCP_USER_MPU | OCP_USER_SDMA,
4502};
4503
4504static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4505 {
4506 .pa_start = 0x4c000000,
4507 .pa_end = 0x4c0000ff,
4508 .flags = ADDR_TYPE_RT
4509 },
4510 { }
4511};
4512
4513/* emif_fw -> emif1 */
4514static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4515 .master = &omap44xx_emif_fw_hwmod,
4516 .slave = &omap44xx_emif1_hwmod,
4517 .clk = "l3_div_ck",
4518 .addr = omap44xx_emif1_addrs,
4519 .user = OCP_USER_MPU | OCP_USER_SDMA,
4520};
4521
4522static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4523 {
4524 .pa_start = 0x4d000000,
4525 .pa_end = 0x4d0000ff,
4526 .flags = ADDR_TYPE_RT
4527 },
4528 { }
4529};
4530
4531/* emif_fw -> emif2 */
4532static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4533 .master = &omap44xx_emif_fw_hwmod,
4534 .slave = &omap44xx_emif2_hwmod,
4535 .clk = "l3_div_ck",
4536 .addr = omap44xx_emif2_addrs,
4537 .user = OCP_USER_MPU | OCP_USER_SDMA,
4538};
4539
4540static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4541 {
4542 .pa_start = 0x4a10a000,
4543 .pa_end = 0x4a10a1ff,
4544 .flags = ADDR_TYPE_RT
4545 },
4546 { }
4547};
4548
4549/* l4_cfg -> fdif */
4550static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4551 .master = &omap44xx_l4_cfg_hwmod,
4552 .slave = &omap44xx_fdif_hwmod,
4553 .clk = "l4_div_ck",
4554 .addr = omap44xx_fdif_addrs,
4555 .user = OCP_USER_MPU | OCP_USER_SDMA,
4556};
4557
4558static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4559 {
4560 .pa_start = 0x4a310000,
4561 .pa_end = 0x4a3101ff,
4562 .flags = ADDR_TYPE_RT
4563 },
4564 { }
4565};
4566
4567/* l4_wkup -> gpio1 */
4568static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4569 .master = &omap44xx_l4_wkup_hwmod,
4570 .slave = &omap44xx_gpio1_hwmod,
4571 .clk = "l4_wkup_clk_mux_ck",
4572 .addr = omap44xx_gpio1_addrs,
4573 .user = OCP_USER_MPU | OCP_USER_SDMA,
4574};
4575
4576static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4577 {
4578 .pa_start = 0x48055000,
4579 .pa_end = 0x480551ff,
4580 .flags = ADDR_TYPE_RT
4581 },
4582 { }
4583};
4584
4585/* l4_per -> gpio2 */
4586static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4587 .master = &omap44xx_l4_per_hwmod,
4588 .slave = &omap44xx_gpio2_hwmod,
4589 .clk = "l4_div_ck",
4590 .addr = omap44xx_gpio2_addrs,
4591 .user = OCP_USER_MPU | OCP_USER_SDMA,
4592};
4593
4594static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4595 {
4596 .pa_start = 0x48057000,
4597 .pa_end = 0x480571ff,
4598 .flags = ADDR_TYPE_RT
4599 },
4600 { }
4601};
4602
4603/* l4_per -> gpio3 */
4604static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4605 .master = &omap44xx_l4_per_hwmod,
4606 .slave = &omap44xx_gpio3_hwmod,
4607 .clk = "l4_div_ck",
4608 .addr = omap44xx_gpio3_addrs,
4609 .user = OCP_USER_MPU | OCP_USER_SDMA,
4610};
4611
4612static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4613 {
4614 .pa_start = 0x48059000,
4615 .pa_end = 0x480591ff,
4616 .flags = ADDR_TYPE_RT
4617 },
4618 { }
4619};
4620
4621/* l4_per -> gpio4 */
4622static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4623 .master = &omap44xx_l4_per_hwmod,
4624 .slave = &omap44xx_gpio4_hwmod,
4625 .clk = "l4_div_ck",
4626 .addr = omap44xx_gpio4_addrs,
4627 .user = OCP_USER_MPU | OCP_USER_SDMA,
4628};
4629
4630static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4631 {
4632 .pa_start = 0x4805b000,
4633 .pa_end = 0x4805b1ff,
4634 .flags = ADDR_TYPE_RT
4635 },
4636 { }
4637};
4638
4639/* l4_per -> gpio5 */
4640static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4641 .master = &omap44xx_l4_per_hwmod,
4642 .slave = &omap44xx_gpio5_hwmod,
4643 .clk = "l4_div_ck",
4644 .addr = omap44xx_gpio5_addrs,
4645 .user = OCP_USER_MPU | OCP_USER_SDMA,
4646};
4647
4648static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4649 {
4650 .pa_start = 0x4805d000,
4651 .pa_end = 0x4805d1ff,
4652 .flags = ADDR_TYPE_RT
4653 },
4654 { }
4655};
4656
4657/* l4_per -> gpio6 */
4658static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4659 .master = &omap44xx_l4_per_hwmod,
4660 .slave = &omap44xx_gpio6_hwmod,
4661 .clk = "l4_div_ck",
4662 .addr = omap44xx_gpio6_addrs,
4663 .user = OCP_USER_MPU | OCP_USER_SDMA,
4664};
4665
4666static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4667 {
4668 .pa_start = 0x50000000,
4669 .pa_end = 0x500003ff,
4670 .flags = ADDR_TYPE_RT
4671 },
4672 { }
4673};
4674
4675/* l3_main_2 -> gpmc */
4676static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4677 .master = &omap44xx_l3_main_2_hwmod,
4678 .slave = &omap44xx_gpmc_hwmod,
4679 .clk = "l3_div_ck",
4680 .addr = omap44xx_gpmc_addrs,
4681 .user = OCP_USER_MPU | OCP_USER_SDMA,
4682};
4683
4684static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4685 {
4686 .pa_start = 0x56000000,
4687 .pa_end = 0x5600ffff,
4688 .flags = ADDR_TYPE_RT
4689 },
4690 { }
4691};
4692
4693/* l3_main_2 -> gpu */
4694static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4695 .master = &omap44xx_l3_main_2_hwmod,
4696 .slave = &omap44xx_gpu_hwmod,
4697 .clk = "l3_div_ck",
4698 .addr = omap44xx_gpu_addrs,
4699 .user = OCP_USER_MPU | OCP_USER_SDMA,
4700};
4701
4702static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4703 {
4704 .pa_start = 0x480b2000,
4705 .pa_end = 0x480b201f,
4706 .flags = ADDR_TYPE_RT
4707 },
4708 { }
4709};
4710
4711/* l4_per -> hdq1w */
4712static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4713 .master = &omap44xx_l4_per_hwmod,
4714 .slave = &omap44xx_hdq1w_hwmod,
4715 .clk = "l4_div_ck",
4716 .addr = omap44xx_hdq1w_addrs,
4717 .user = OCP_USER_MPU | OCP_USER_SDMA,
4718};
4719
4720static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4721 {
4722 .pa_start = 0x4a058000,
4723 .pa_end = 0x4a05bfff,
4724 .flags = ADDR_TYPE_RT
4725 },
4726 { }
4727};
4728
4729/* l4_cfg -> hsi */
4730static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4731 .master = &omap44xx_l4_cfg_hwmod,
4732 .slave = &omap44xx_hsi_hwmod,
4733 .clk = "l4_div_ck",
4734 .addr = omap44xx_hsi_addrs,
4735 .user = OCP_USER_MPU | OCP_USER_SDMA,
4736};
4737
4738static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4739 {
4740 .pa_start = 0x48070000,
4741 .pa_end = 0x480700ff,
4742 .flags = ADDR_TYPE_RT
4743 },
4744 { }
4745};
4746
4747/* l4_per -> i2c1 */
4748static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4749 .master = &omap44xx_l4_per_hwmod,
4750 .slave = &omap44xx_i2c1_hwmod,
4751 .clk = "l4_div_ck",
4752 .addr = omap44xx_i2c1_addrs,
4753 .user = OCP_USER_MPU | OCP_USER_SDMA,
4754};
4755
4756static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4757 {
4758 .pa_start = 0x48072000,
4759 .pa_end = 0x480720ff,
4760 .flags = ADDR_TYPE_RT
4761 },
4762 { }
4763};
4764
4765/* l4_per -> i2c2 */
4766static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4767 .master = &omap44xx_l4_per_hwmod,
4768 .slave = &omap44xx_i2c2_hwmod,
4769 .clk = "l4_div_ck",
4770 .addr = omap44xx_i2c2_addrs,
4771 .user = OCP_USER_MPU | OCP_USER_SDMA,
4772};
4773
4774static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4775 {
4776 .pa_start = 0x48060000,
4777 .pa_end = 0x480600ff,
4778 .flags = ADDR_TYPE_RT
4779 },
4780 { }
4781};
4782
4783/* l4_per -> i2c3 */
4784static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4785 .master = &omap44xx_l4_per_hwmod,
4786 .slave = &omap44xx_i2c3_hwmod,
4787 .clk = "l4_div_ck",
4788 .addr = omap44xx_i2c3_addrs,
4789 .user = OCP_USER_MPU | OCP_USER_SDMA,
4790};
4791
4792static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4793 {
4794 .pa_start = 0x48350000,
4795 .pa_end = 0x483500ff,
4796 .flags = ADDR_TYPE_RT
4797 },
4798 { }
4799};
4800
4801/* l4_per -> i2c4 */
4802static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4803 .master = &omap44xx_l4_per_hwmod,
4804 .slave = &omap44xx_i2c4_hwmod,
4805 .clk = "l4_div_ck",
4806 .addr = omap44xx_i2c4_addrs,
4807 .user = OCP_USER_MPU | OCP_USER_SDMA,
4808};
4809
4810/* l3_main_2 -> ipu */
4811static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4812 .master = &omap44xx_l3_main_2_hwmod,
4813 .slave = &omap44xx_ipu_hwmod,
4814 .clk = "l3_div_ck",
4815 .user = OCP_USER_MPU | OCP_USER_SDMA,
4816};
4817
4818static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4819 {
4820 .pa_start = 0x52000000,
4821 .pa_end = 0x520000ff,
4822 .flags = ADDR_TYPE_RT
4823 },
4824 { }
4825};
4826
4827/* l3_main_2 -> iss */
4828static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4829 .master = &omap44xx_l3_main_2_hwmod,
4830 .slave = &omap44xx_iss_hwmod,
4831 .clk = "l3_div_ck",
4832 .addr = omap44xx_iss_addrs,
4833 .user = OCP_USER_MPU | OCP_USER_SDMA,
4834};
4835
4836/* iva -> sl2if */
4837static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4838 .master = &omap44xx_iva_hwmod,
4839 .slave = &omap44xx_sl2if_hwmod,
4840 .clk = "dpll_iva_m5x2_ck",
4841 .user = OCP_USER_IVA,
4842};
4843
4844static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4845 {
4846 .pa_start = 0x5a000000,
4847 .pa_end = 0x5a07ffff,
4848 .flags = ADDR_TYPE_RT
4849 },
4850 { }
4851};
4852
4853/* l3_main_2 -> iva */
4854static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4855 .master = &omap44xx_l3_main_2_hwmod,
4856 .slave = &omap44xx_iva_hwmod,
4857 .clk = "l3_div_ck",
4858 .addr = omap44xx_iva_addrs,
4859 .user = OCP_USER_MPU,
4860};
4861
4862static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4863 {
4864 .pa_start = 0x4a31c000,
4865 .pa_end = 0x4a31c07f,
4866 .flags = ADDR_TYPE_RT
4867 },
4868 { }
4869};
4870
4871/* l4_wkup -> kbd */
4872static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4873 .master = &omap44xx_l4_wkup_hwmod,
4874 .slave = &omap44xx_kbd_hwmod,
4875 .clk = "l4_wkup_clk_mux_ck",
4876 .addr = omap44xx_kbd_addrs,
4877 .user = OCP_USER_MPU | OCP_USER_SDMA,
4878};
4879
4880static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4881 {
4882 .pa_start = 0x4a0f4000,
4883 .pa_end = 0x4a0f41ff,
4884 .flags = ADDR_TYPE_RT
4885 },
4886 { }
4887};
4888
4889/* l4_cfg -> mailbox */
4890static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4891 .master = &omap44xx_l4_cfg_hwmod,
4892 .slave = &omap44xx_mailbox_hwmod,
4893 .clk = "l4_div_ck",
4894 .addr = omap44xx_mailbox_addrs,
4895 .user = OCP_USER_MPU | OCP_USER_SDMA,
4896};
4897
4898static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4899 {
4900 .pa_start = 0x40128000,
4901 .pa_end = 0x401283ff,
4902 .flags = ADDR_TYPE_RT
4903 },
4904 { }
4905};
4906
4907/* l4_abe -> mcasp */
4908static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4909 .master = &omap44xx_l4_abe_hwmod,
4910 .slave = &omap44xx_mcasp_hwmod,
4911 .clk = "ocp_abe_iclk",
4912 .addr = omap44xx_mcasp_addrs,
4913 .user = OCP_USER_MPU,
4914};
4915
4916static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4917 {
4918 .pa_start = 0x49028000,
4919 .pa_end = 0x490283ff,
4920 .flags = ADDR_TYPE_RT
4921 },
4922 { }
4923};
4924
4925/* l4_abe -> mcasp (dma) */
4926static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4927 .master = &omap44xx_l4_abe_hwmod,
4928 .slave = &omap44xx_mcasp_hwmod,
4929 .clk = "ocp_abe_iclk",
4930 .addr = omap44xx_mcasp_dma_addrs,
4931 .user = OCP_USER_SDMA,
4932};
4933
4934static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4935 {
4936 .name = "mpu",
4937 .pa_start = 0x40122000,
4938 .pa_end = 0x401220ff,
4939 .flags = ADDR_TYPE_RT
4940 },
4941 { }
4942};
4943
4944/* l4_abe -> mcbsp1 */
4945static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4946 .master = &omap44xx_l4_abe_hwmod,
4947 .slave = &omap44xx_mcbsp1_hwmod,
4948 .clk = "ocp_abe_iclk",
4949 .addr = omap44xx_mcbsp1_addrs,
4950 .user = OCP_USER_MPU,
4951};
4952
4953static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4954 {
4955 .name = "dma",
4956 .pa_start = 0x49022000,
4957 .pa_end = 0x490220ff,
4958 .flags = ADDR_TYPE_RT
4959 },
4960 { }
4961};
4962
4963/* l4_abe -> mcbsp1 (dma) */
4964static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4965 .master = &omap44xx_l4_abe_hwmod,
4966 .slave = &omap44xx_mcbsp1_hwmod,
4967 .clk = "ocp_abe_iclk",
4968 .addr = omap44xx_mcbsp1_dma_addrs,
4969 .user = OCP_USER_SDMA,
4970};
4971
4972static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4973 {
4974 .name = "mpu",
4975 .pa_start = 0x40124000,
4976 .pa_end = 0x401240ff,
4977 .flags = ADDR_TYPE_RT
4978 },
4979 { }
4980};
4981
4982/* l4_abe -> mcbsp2 */
4983static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4984 .master = &omap44xx_l4_abe_hwmod,
4985 .slave = &omap44xx_mcbsp2_hwmod,
4986 .clk = "ocp_abe_iclk",
4987 .addr = omap44xx_mcbsp2_addrs,
4988 .user = OCP_USER_MPU,
4989};
4990
4991static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4992 {
4993 .name = "dma",
4994 .pa_start = 0x49024000,
4995 .pa_end = 0x490240ff,
4996 .flags = ADDR_TYPE_RT
4997 },
4998 { }
4999};
5000
5001/* l4_abe -> mcbsp2 (dma) */
5002static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5003 .master = &omap44xx_l4_abe_hwmod,
5004 .slave = &omap44xx_mcbsp2_hwmod,
5005 .clk = "ocp_abe_iclk",
5006 .addr = omap44xx_mcbsp2_dma_addrs,
5007 .user = OCP_USER_SDMA,
5008};
5009
5010static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5011 {
5012 .name = "mpu",
5013 .pa_start = 0x40126000,
5014 .pa_end = 0x401260ff,
5015 .flags = ADDR_TYPE_RT
5016 },
5017 { }
5018};
5019
5020/* l4_abe -> mcbsp3 */
5021static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5022 .master = &omap44xx_l4_abe_hwmod,
5023 .slave = &omap44xx_mcbsp3_hwmod,
5024 .clk = "ocp_abe_iclk",
5025 .addr = omap44xx_mcbsp3_addrs,
5026 .user = OCP_USER_MPU,
5027};
5028
5029static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5030 {
5031 .name = "dma",
5032 .pa_start = 0x49026000,
5033 .pa_end = 0x490260ff,
5034 .flags = ADDR_TYPE_RT
5035 },
5036 { }
5037};
5038
5039/* l4_abe -> mcbsp3 (dma) */
5040static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5041 .master = &omap44xx_l4_abe_hwmod,
5042 .slave = &omap44xx_mcbsp3_hwmod,
5043 .clk = "ocp_abe_iclk",
5044 .addr = omap44xx_mcbsp3_dma_addrs,
5045 .user = OCP_USER_SDMA,
5046};
5047
5048static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5049 {
5050 .pa_start = 0x48096000,
5051 .pa_end = 0x480960ff,
5052 .flags = ADDR_TYPE_RT
5053 },
5054 { }
5055};
5056
5057/* l4_per -> mcbsp4 */
5058static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5059 .master = &omap44xx_l4_per_hwmod,
5060 .slave = &omap44xx_mcbsp4_hwmod,
5061 .clk = "l4_div_ck",
5062 .addr = omap44xx_mcbsp4_addrs,
5063 .user = OCP_USER_MPU | OCP_USER_SDMA,
5064};
5065
5066static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5067 {
5068 .pa_start = 0x40132000,
5069 .pa_end = 0x4013207f,
5070 .flags = ADDR_TYPE_RT
5071 },
5072 { }
5073};
5074
5075/* l4_abe -> mcpdm */
5076static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5077 .master = &omap44xx_l4_abe_hwmod,
5078 .slave = &omap44xx_mcpdm_hwmod,
5079 .clk = "ocp_abe_iclk",
5080 .addr = omap44xx_mcpdm_addrs,
5081 .user = OCP_USER_MPU,
5082};
5083
5084static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5085 {
5086 .pa_start = 0x49032000,
5087 .pa_end = 0x4903207f,
5088 .flags = ADDR_TYPE_RT
5089 },
5090 { }
5091};
5092
5093/* l4_abe -> mcpdm (dma) */
5094static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5095 .master = &omap44xx_l4_abe_hwmod,
5096 .slave = &omap44xx_mcpdm_hwmod,
5097 .clk = "ocp_abe_iclk",
5098 .addr = omap44xx_mcpdm_dma_addrs,
5099 .user = OCP_USER_SDMA,
5100};
5101
5102static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5103 {
5104 .pa_start = 0x48098000,
5105 .pa_end = 0x480981ff,
5106 .flags = ADDR_TYPE_RT
5107 },
5108 { }
5109};
5110
5111/* l4_per -> mcspi1 */
5112static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5113 .master = &omap44xx_l4_per_hwmod,
5114 .slave = &omap44xx_mcspi1_hwmod,
5115 .clk = "l4_div_ck",
5116 .addr = omap44xx_mcspi1_addrs,
5117 .user = OCP_USER_MPU | OCP_USER_SDMA,
5118};
5119
5120static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5121 {
5122 .pa_start = 0x4809a000,
5123 .pa_end = 0x4809a1ff,
5124 .flags = ADDR_TYPE_RT
5125 },
5126 { }
5127};
5128
5129/* l4_per -> mcspi2 */
5130static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5131 .master = &omap44xx_l4_per_hwmod,
5132 .slave = &omap44xx_mcspi2_hwmod,
5133 .clk = "l4_div_ck",
5134 .addr = omap44xx_mcspi2_addrs,
5135 .user = OCP_USER_MPU | OCP_USER_SDMA,
5136};
5137
5138static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5139 {
5140 .pa_start = 0x480b8000,
5141 .pa_end = 0x480b81ff,
5142 .flags = ADDR_TYPE_RT
5143 },
5144 { }
5145};
5146
5147/* l4_per -> mcspi3 */
5148static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5149 .master = &omap44xx_l4_per_hwmod,
5150 .slave = &omap44xx_mcspi3_hwmod,
5151 .clk = "l4_div_ck",
5152 .addr = omap44xx_mcspi3_addrs,
5153 .user = OCP_USER_MPU | OCP_USER_SDMA,
5154};
5155
5156static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5157 {
5158 .pa_start = 0x480ba000,
5159 .pa_end = 0x480ba1ff,
5160 .flags = ADDR_TYPE_RT
5161 },
5162 { }
5163};
5164
5165/* l4_per -> mcspi4 */
5166static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5167 .master = &omap44xx_l4_per_hwmod,
5168 .slave = &omap44xx_mcspi4_hwmod,
5169 .clk = "l4_div_ck",
5170 .addr = omap44xx_mcspi4_addrs,
5171 .user = OCP_USER_MPU | OCP_USER_SDMA,
5172};
5173
5174static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5175 {
5176 .pa_start = 0x4809c000,
5177 .pa_end = 0x4809c3ff,
5178 .flags = ADDR_TYPE_RT
5179 },
5180 { }
5181};
5182
5183/* l4_per -> mmc1 */
5184static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5185 .master = &omap44xx_l4_per_hwmod,
5186 .slave = &omap44xx_mmc1_hwmod,
5187 .clk = "l4_div_ck",
5188 .addr = omap44xx_mmc1_addrs,
5189 .user = OCP_USER_MPU | OCP_USER_SDMA,
5190};
5191
5192static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5193 {
5194 .pa_start = 0x480b4000,
5195 .pa_end = 0x480b43ff,
5196 .flags = ADDR_TYPE_RT
5197 },
5198 { }
5199};
5200
5201/* l4_per -> mmc2 */
5202static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5203 .master = &omap44xx_l4_per_hwmod,
5204 .slave = &omap44xx_mmc2_hwmod,
5205 .clk = "l4_div_ck",
5206 .addr = omap44xx_mmc2_addrs,
5207 .user = OCP_USER_MPU | OCP_USER_SDMA,
5208};
5209
5210static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5211 {
5212 .pa_start = 0x480ad000,
5213 .pa_end = 0x480ad3ff,
5214 .flags = ADDR_TYPE_RT
5215 },
5216 { }
5217};
5218
5219/* l4_per -> mmc3 */
5220static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5221 .master = &omap44xx_l4_per_hwmod,
5222 .slave = &omap44xx_mmc3_hwmod,
5223 .clk = "l4_div_ck",
5224 .addr = omap44xx_mmc3_addrs,
5225 .user = OCP_USER_MPU | OCP_USER_SDMA,
5226};
5227
5228static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5229 {
5230 .pa_start = 0x480d1000,
5231 .pa_end = 0x480d13ff,
5232 .flags = ADDR_TYPE_RT
5233 },
5234 { }
5235};
5236
5237/* l4_per -> mmc4 */
5238static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5239 .master = &omap44xx_l4_per_hwmod,
5240 .slave = &omap44xx_mmc4_hwmod,
5241 .clk = "l4_div_ck",
5242 .addr = omap44xx_mmc4_addrs,
5243 .user = OCP_USER_MPU | OCP_USER_SDMA,
5244};
5245
5246static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5247 {
5248 .pa_start = 0x480d5000,
5249 .pa_end = 0x480d53ff,
5250 .flags = ADDR_TYPE_RT
5251 },
5252 { }
5253};
5254
5255/* l4_per -> mmc5 */
5256static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5257 .master = &omap44xx_l4_per_hwmod,
5258 .slave = &omap44xx_mmc5_hwmod,
5259 .clk = "l4_div_ck",
5260 .addr = omap44xx_mmc5_addrs,
5261 .user = OCP_USER_MPU | OCP_USER_SDMA,
5262};
5263
5264/* l3_main_2 -> ocmc_ram */
5265static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5266 .master = &omap44xx_l3_main_2_hwmod,
5267 .slave = &omap44xx_ocmc_ram_hwmod,
5268 .clk = "l3_div_ck",
5269 .user = OCP_USER_MPU | OCP_USER_SDMA,
5270};
5271
5272/* l4_cfg -> ocp2scp_usb_phy */
5273static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5274 .master = &omap44xx_l4_cfg_hwmod,
5275 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
5276 .clk = "l4_div_ck",
5277 .user = OCP_USER_MPU | OCP_USER_SDMA,
5278};
5279
5280static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5281 {
5282 .pa_start = 0x48243000,
5283 .pa_end = 0x48243fff,
5284 .flags = ADDR_TYPE_RT
5285 },
5286 { }
5287};
5288
5289/* mpu_private -> prcm_mpu */
5290static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5291 .master = &omap44xx_mpu_private_hwmod,
5292 .slave = &omap44xx_prcm_mpu_hwmod,
5293 .clk = "l3_div_ck",
5294 .addr = omap44xx_prcm_mpu_addrs,
5295 .user = OCP_USER_MPU | OCP_USER_SDMA,
5296};
5297
5298static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5299 {
5300 .pa_start = 0x4a004000,
5301 .pa_end = 0x4a004fff,
5302 .flags = ADDR_TYPE_RT
5303 },
5304 { }
5305};
5306
5307/* l4_wkup -> cm_core_aon */
5308static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5309 .master = &omap44xx_l4_wkup_hwmod,
5310 .slave = &omap44xx_cm_core_aon_hwmod,
5311 .clk = "l4_wkup_clk_mux_ck",
5312 .addr = omap44xx_cm_core_aon_addrs,
5313 .user = OCP_USER_MPU | OCP_USER_SDMA,
5314};
5315
5316static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5317 {
5318 .pa_start = 0x4a008000,
5319 .pa_end = 0x4a009fff,
5320 .flags = ADDR_TYPE_RT
5321 },
5322 { }
5323};
5324
5325/* l4_cfg -> cm_core */
5326static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5327 .master = &omap44xx_l4_cfg_hwmod,
5328 .slave = &omap44xx_cm_core_hwmod,
5329 .clk = "l4_div_ck",
5330 .addr = omap44xx_cm_core_addrs,
5331 .user = OCP_USER_MPU | OCP_USER_SDMA,
5332};
5333
5334static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5335 {
5336 .pa_start = 0x4a306000,
5337 .pa_end = 0x4a307fff,
5338 .flags = ADDR_TYPE_RT
5339 },
5340 { }
5341};
5342
5343/* l4_wkup -> prm */
5344static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5345 .master = &omap44xx_l4_wkup_hwmod,
5346 .slave = &omap44xx_prm_hwmod,
5347 .clk = "l4_wkup_clk_mux_ck",
5348 .addr = omap44xx_prm_addrs,
5349 .user = OCP_USER_MPU | OCP_USER_SDMA,
5350};
5351
5352static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5353 {
5354 .pa_start = 0x4a30a000,
5355 .pa_end = 0x4a30a7ff,
5356 .flags = ADDR_TYPE_RT
5357 },
5358 { }
5359};
5360
5361/* l4_wkup -> scrm */
5362static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5363 .master = &omap44xx_l4_wkup_hwmod,
5364 .slave = &omap44xx_scrm_hwmod,
5365 .clk = "l4_wkup_clk_mux_ck",
5366 .addr = omap44xx_scrm_addrs,
5367 .user = OCP_USER_MPU | OCP_USER_SDMA,
5368};
5369
5370/* l3_main_2 -> sl2if */
5371static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5372 .master = &omap44xx_l3_main_2_hwmod,
5373 .slave = &omap44xx_sl2if_hwmod,
5374 .clk = "l3_div_ck",
5375 .user = OCP_USER_MPU | OCP_USER_SDMA,
5376};
5377
5378static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5379 {
5380 .pa_start = 0x4012c000,
5381 .pa_end = 0x4012c3ff,
5382 .flags = ADDR_TYPE_RT
5383 },
5384 { }
5385};
5386
5387/* l4_abe -> slimbus1 */
5388static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5389 .master = &omap44xx_l4_abe_hwmod,
5390 .slave = &omap44xx_slimbus1_hwmod,
5391 .clk = "ocp_abe_iclk",
5392 .addr = omap44xx_slimbus1_addrs,
5393 .user = OCP_USER_MPU,
5394};
5395
5396static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5397 {
5398 .pa_start = 0x4902c000,
5399 .pa_end = 0x4902c3ff,
5400 .flags = ADDR_TYPE_RT
5401 },
5402 { }
5403};
5404
5405/* l4_abe -> slimbus1 (dma) */
5406static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5407 .master = &omap44xx_l4_abe_hwmod,
5408 .slave = &omap44xx_slimbus1_hwmod,
5409 .clk = "ocp_abe_iclk",
5410 .addr = omap44xx_slimbus1_dma_addrs,
5411 .user = OCP_USER_SDMA,
5412};
5413
5414static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5415 {
5416 .pa_start = 0x48076000,
5417 .pa_end = 0x480763ff,
5418 .flags = ADDR_TYPE_RT
5419 },
5420 { }
5421};
5422
5423/* l4_per -> slimbus2 */
5424static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5425 .master = &omap44xx_l4_per_hwmod,
5426 .slave = &omap44xx_slimbus2_hwmod,
5427 .clk = "l4_div_ck",
5428 .addr = omap44xx_slimbus2_addrs,
5429 .user = OCP_USER_MPU | OCP_USER_SDMA,
5430};
5431
5432static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5433 {
5434 .pa_start = 0x4a0dd000,
5435 .pa_end = 0x4a0dd03f,
5436 .flags = ADDR_TYPE_RT
5437 },
5438 { }
5439};
5440
5441/* l4_cfg -> smartreflex_core */
5442static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5443 .master = &omap44xx_l4_cfg_hwmod,
5444 .slave = &omap44xx_smartreflex_core_hwmod,
5445 .clk = "l4_div_ck",
5446 .addr = omap44xx_smartreflex_core_addrs,
5447 .user = OCP_USER_MPU | OCP_USER_SDMA,
5448};
5449
5450static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5451 {
5452 .pa_start = 0x4a0db000,
5453 .pa_end = 0x4a0db03f,
5454 .flags = ADDR_TYPE_RT
5455 },
5456 { }
5457};
5458
5459/* l4_cfg -> smartreflex_iva */
5460static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5461 .master = &omap44xx_l4_cfg_hwmod,
5462 .slave = &omap44xx_smartreflex_iva_hwmod,
5463 .clk = "l4_div_ck",
5464 .addr = omap44xx_smartreflex_iva_addrs,
5465 .user = OCP_USER_MPU | OCP_USER_SDMA,
5466};
5467
5468static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5469 {
5470 .pa_start = 0x4a0d9000,
5471 .pa_end = 0x4a0d903f,
5472 .flags = ADDR_TYPE_RT
5473 },
5474 { }
5475};
5476
5477/* l4_cfg -> smartreflex_mpu */
5478static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5479 .master = &omap44xx_l4_cfg_hwmod,
5480 .slave = &omap44xx_smartreflex_mpu_hwmod,
5481 .clk = "l4_div_ck",
5482 .addr = omap44xx_smartreflex_mpu_addrs,
5483 .user = OCP_USER_MPU | OCP_USER_SDMA,
5484};
5485
5486static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5487 {
5488 .pa_start = 0x4a0f6000,
5489 .pa_end = 0x4a0f6fff,
5490 .flags = ADDR_TYPE_RT
5491 },
5492 { }
5493};
5494
5495/* l4_cfg -> spinlock */
5496static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5497 .master = &omap44xx_l4_cfg_hwmod,
5498 .slave = &omap44xx_spinlock_hwmod,
5499 .clk = "l4_div_ck",
5500 .addr = omap44xx_spinlock_addrs,
5501 .user = OCP_USER_MPU | OCP_USER_SDMA,
5502};
5503
5504static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5505 {
5506 .pa_start = 0x4a318000,
5507 .pa_end = 0x4a31807f,
5508 .flags = ADDR_TYPE_RT
5509 },
5510 { }
5511};
5512
5513/* l4_wkup -> timer1 */
5514static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5515 .master = &omap44xx_l4_wkup_hwmod,
5516 .slave = &omap44xx_timer1_hwmod,
5517 .clk = "l4_wkup_clk_mux_ck",
5518 .addr = omap44xx_timer1_addrs,
5519 .user = OCP_USER_MPU | OCP_USER_SDMA,
5520};
5521
5522static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5523 {
5524 .pa_start = 0x48032000,
5525 .pa_end = 0x4803207f,
5526 .flags = ADDR_TYPE_RT
5527 },
5528 { }
5529};
5530
5531/* l4_per -> timer2 */
5532static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5533 .master = &omap44xx_l4_per_hwmod,
5534 .slave = &omap44xx_timer2_hwmod,
5535 .clk = "l4_div_ck",
5536 .addr = omap44xx_timer2_addrs,
5537 .user = OCP_USER_MPU | OCP_USER_SDMA,
5538};
5539
5540static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5541 {
5542 .pa_start = 0x48034000,
5543 .pa_end = 0x4803407f,
5544 .flags = ADDR_TYPE_RT
5545 },
5546 { }
5547};
5548
5549/* l4_per -> timer3 */
5550static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5551 .master = &omap44xx_l4_per_hwmod,
5552 .slave = &omap44xx_timer3_hwmod,
5553 .clk = "l4_div_ck",
5554 .addr = omap44xx_timer3_addrs,
5555 .user = OCP_USER_MPU | OCP_USER_SDMA,
5556};
5557
5558static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5559 {
5560 .pa_start = 0x48036000,
5561 .pa_end = 0x4803607f,
5562 .flags = ADDR_TYPE_RT
5563 },
5564 { }
5565};
5566
5567/* l4_per -> timer4 */
5568static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5569 .master = &omap44xx_l4_per_hwmod,
5570 .slave = &omap44xx_timer4_hwmod,
5571 .clk = "l4_div_ck",
5572 .addr = omap44xx_timer4_addrs,
5573 .user = OCP_USER_MPU | OCP_USER_SDMA,
5574};
5575
5576static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5577 {
5578 .pa_start = 0x40138000,
5579 .pa_end = 0x4013807f,
5580 .flags = ADDR_TYPE_RT
5581 },
5582 { }
5583};
5584
5585/* l4_abe -> timer5 */
5586static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5587 .master = &omap44xx_l4_abe_hwmod,
5588 .slave = &omap44xx_timer5_hwmod,
5589 .clk = "ocp_abe_iclk",
5590 .addr = omap44xx_timer5_addrs,
5591 .user = OCP_USER_MPU,
5592};
5593
5594static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5595 {
5596 .pa_start = 0x49038000,
5597 .pa_end = 0x4903807f,
5598 .flags = ADDR_TYPE_RT
5599 },
5600 { }
5601};
5602
5603/* l4_abe -> timer5 (dma) */
5604static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5605 .master = &omap44xx_l4_abe_hwmod,
5606 .slave = &omap44xx_timer5_hwmod,
5607 .clk = "ocp_abe_iclk",
5608 .addr = omap44xx_timer5_dma_addrs,
5609 .user = OCP_USER_SDMA,
5610};
5611
5612static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5613 {
5614 .pa_start = 0x4013a000,
5615 .pa_end = 0x4013a07f,
5616 .flags = ADDR_TYPE_RT
5617 },
5618 { }
5619};
5620
5621/* l4_abe -> timer6 */
5622static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5623 .master = &omap44xx_l4_abe_hwmod,
5624 .slave = &omap44xx_timer6_hwmod,
5625 .clk = "ocp_abe_iclk",
5626 .addr = omap44xx_timer6_addrs,
5627 .user = OCP_USER_MPU,
5628};
5629
5630static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5631 {
5632 .pa_start = 0x4903a000,
5633 .pa_end = 0x4903a07f,
5634 .flags = ADDR_TYPE_RT
5635 },
5636 { }
5637};
5638
5639/* l4_abe -> timer6 (dma) */
5640static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5641 .master = &omap44xx_l4_abe_hwmod,
5642 .slave = &omap44xx_timer6_hwmod,
5643 .clk = "ocp_abe_iclk",
5644 .addr = omap44xx_timer6_dma_addrs,
5645 .user = OCP_USER_SDMA,
5646};
5647
5648static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5649 {
5650 .pa_start = 0x4013c000,
5651 .pa_end = 0x4013c07f,
5652 .flags = ADDR_TYPE_RT
5653 },
5654 { }
5655};
5656
5657/* l4_abe -> timer7 */
5658static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5659 .master = &omap44xx_l4_abe_hwmod,
5660 .slave = &omap44xx_timer7_hwmod,
5661 .clk = "ocp_abe_iclk",
5662 .addr = omap44xx_timer7_addrs,
5663 .user = OCP_USER_MPU,
5664};
5665
5666static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5667 {
5668 .pa_start = 0x4903c000,
5669 .pa_end = 0x4903c07f,
5670 .flags = ADDR_TYPE_RT
5671 },
5672 { }
5673};
5674
5675/* l4_abe -> timer7 (dma) */
5676static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5677 .master = &omap44xx_l4_abe_hwmod,
5678 .slave = &omap44xx_timer7_hwmod,
5679 .clk = "ocp_abe_iclk",
5680 .addr = omap44xx_timer7_dma_addrs,
5681 .user = OCP_USER_SDMA,
5682};
5683
5684static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5685 {
5686 .pa_start = 0x4013e000,
5687 .pa_end = 0x4013e07f,
5688 .flags = ADDR_TYPE_RT
5689 },
5690 { }
5691};
5692
5693/* l4_abe -> timer8 */
5694static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5695 .master = &omap44xx_l4_abe_hwmod,
5696 .slave = &omap44xx_timer8_hwmod,
5697 .clk = "ocp_abe_iclk",
5698 .addr = omap44xx_timer8_addrs,
5699 .user = OCP_USER_MPU,
5700};
5701
5702static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5703 {
5704 .pa_start = 0x4903e000,
5705 .pa_end = 0x4903e07f,
5706 .flags = ADDR_TYPE_RT
5707 },
5708 { }
5709};
5710
5711/* l4_abe -> timer8 (dma) */
5712static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5713 .master = &omap44xx_l4_abe_hwmod,
5714 .slave = &omap44xx_timer8_hwmod,
5715 .clk = "ocp_abe_iclk",
5716 .addr = omap44xx_timer8_dma_addrs,
5717 .user = OCP_USER_SDMA,
5718};
5719
5720static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5721 {
5722 .pa_start = 0x4803e000,
5723 .pa_end = 0x4803e07f,
5724 .flags = ADDR_TYPE_RT
5725 },
5726 { }
5727};
5728
5729/* l4_per -> timer9 */
5730static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5731 .master = &omap44xx_l4_per_hwmod,
5732 .slave = &omap44xx_timer9_hwmod,
5733 .clk = "l4_div_ck",
5734 .addr = omap44xx_timer9_addrs,
5735 .user = OCP_USER_MPU | OCP_USER_SDMA,
5736};
5737
5738static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5739 {
5740 .pa_start = 0x48086000,
5741 .pa_end = 0x4808607f,
5742 .flags = ADDR_TYPE_RT
5743 },
5744 { }
5745};
5746
5747/* l4_per -> timer10 */
5748static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5749 .master = &omap44xx_l4_per_hwmod,
5750 .slave = &omap44xx_timer10_hwmod,
5751 .clk = "l4_div_ck",
5752 .addr = omap44xx_timer10_addrs,
5753 .user = OCP_USER_MPU | OCP_USER_SDMA,
5754};
5755
5756static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5757 {
5758 .pa_start = 0x48088000,
5759 .pa_end = 0x4808807f,
5760 .flags = ADDR_TYPE_RT
5761 },
5762 { }
5763};
5764
5765/* l4_per -> timer11 */
5766static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5767 .master = &omap44xx_l4_per_hwmod,
5768 .slave = &omap44xx_timer11_hwmod,
5769 .clk = "l4_div_ck",
5770 .addr = omap44xx_timer11_addrs,
5771 .user = OCP_USER_MPU | OCP_USER_SDMA,
5772};
5773
5774static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5775 {
5776 .pa_start = 0x4806a000,
5777 .pa_end = 0x4806a0ff,
5778 .flags = ADDR_TYPE_RT
5779 },
5780 { }
5781};
5782
5783/* l4_per -> uart1 */
5784static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5785 .master = &omap44xx_l4_per_hwmod,
5786 .slave = &omap44xx_uart1_hwmod,
5787 .clk = "l4_div_ck",
5788 .addr = omap44xx_uart1_addrs,
5789 .user = OCP_USER_MPU | OCP_USER_SDMA,
5790};
5791
5792static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5793 {
5794 .pa_start = 0x4806c000,
5795 .pa_end = 0x4806c0ff,
5796 .flags = ADDR_TYPE_RT
5797 },
5798 { }
5799};
5800
5801/* l4_per -> uart2 */
5802static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5803 .master = &omap44xx_l4_per_hwmod,
5804 .slave = &omap44xx_uart2_hwmod,
5805 .clk = "l4_div_ck",
5806 .addr = omap44xx_uart2_addrs,
5807 .user = OCP_USER_MPU | OCP_USER_SDMA,
5808};
5809
5810static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5811 {
5812 .pa_start = 0x48020000,
5813 .pa_end = 0x480200ff,
5814 .flags = ADDR_TYPE_RT
5815 },
5816 { }
5817};
5818
5819/* l4_per -> uart3 */
5820static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5821 .master = &omap44xx_l4_per_hwmod,
5822 .slave = &omap44xx_uart3_hwmod,
5823 .clk = "l4_div_ck",
5824 .addr = omap44xx_uart3_addrs,
5825 .user = OCP_USER_MPU | OCP_USER_SDMA,
5826};
5827
5828static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5829 {
5830 .pa_start = 0x4806e000,
5831 .pa_end = 0x4806e0ff,
5832 .flags = ADDR_TYPE_RT
5833 },
5834 { }
5835};
5836
5837/* l4_per -> uart4 */
5838static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5839 .master = &omap44xx_l4_per_hwmod,
5840 .slave = &omap44xx_uart4_hwmod,
5841 .clk = "l4_div_ck",
5842 .addr = omap44xx_uart4_addrs,
5843 .user = OCP_USER_MPU | OCP_USER_SDMA,
5844};
5845
5846static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5847 {
5848 .pa_start = 0x4a0a9000,
5849 .pa_end = 0x4a0a93ff,
5850 .flags = ADDR_TYPE_RT
5851 },
5852 { }
5853};
5854
5855/* l4_cfg -> usb_host_fs */
5856static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5857 .master = &omap44xx_l4_cfg_hwmod,
5858 .slave = &omap44xx_usb_host_fs_hwmod,
5859 .clk = "l4_div_ck",
5860 .addr = omap44xx_usb_host_fs_addrs,
5861 .user = OCP_USER_MPU | OCP_USER_SDMA,
5363}; 5862};
5364 5863
5365static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { 5864static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
@@ -5382,12 +5881,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5382 {} 5881 {}
5383}; 5882};
5384 5883
5385static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { 5884/* l4_cfg -> usb_host_hs */
5386 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5387 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5388 { .irq = -1 }
5389};
5390
5391static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { 5885static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5392 .master = &omap44xx_l4_cfg_hwmod, 5886 .master = &omap44xx_l4_cfg_hwmod,
5393 .slave = &omap44xx_usb_host_hs_hwmod, 5887 .slave = &omap44xx_usb_host_hs_hwmod,
@@ -5396,100 +5890,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5396 .user = OCP_USER_MPU | OCP_USER_SDMA, 5890 .user = OCP_USER_MPU | OCP_USER_SDMA,
5397}; 5891};
5398 5892
5399static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = { 5893static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5400 &omap44xx_l4_cfg__usb_host_hs, 5894 {
5401}; 5895 .pa_start = 0x4a0ab000,
5402 5896 .pa_end = 0x4a0ab003,
5403static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { 5897 .flags = ADDR_TYPE_RT
5404 .name = "usb_host_hs",
5405 .class = &omap44xx_usb_host_hs_hwmod_class,
5406 .clkdm_name = "l3_init_clkdm",
5407 .main_clk = "usb_host_hs_fck",
5408 .prcm = {
5409 .omap4 = {
5410 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5411 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5412 .modulemode = MODULEMODE_SWCTRL,
5413 },
5414 }, 5898 },
5415 .mpu_irqs = omap44xx_usb_host_hs_irqs, 5899 { }
5416 .slaves = omap44xx_usb_host_hs_slaves,
5417 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5418 .masters = omap44xx_usb_host_hs_masters,
5419 .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5420
5421 /*
5422 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5423 * id: i660
5424 *
5425 * Description:
5426 * In the following configuration :
5427 * - USBHOST module is set to smart-idle mode
5428 * - PRCM asserts idle_req to the USBHOST module ( This typically
5429 * happens when the system is going to a low power mode : all ports
5430 * have been suspended, the master part of the USBHOST module has
5431 * entered the standby state, and SW has cut the functional clocks)
5432 * - an USBHOST interrupt occurs before the module is able to answer
5433 * idle_ack, typically a remote wakeup IRQ.
5434 * Then the USB HOST module will enter a deadlock situation where it
5435 * is no more accessible nor functional.
5436 *
5437 * Workaround:
5438 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5439 */
5440
5441 /*
5442 * Errata: USB host EHCI may stall when entering smart-standby mode
5443 * Id: i571
5444 *
5445 * Description:
5446 * When the USBHOST module is set to smart-standby mode, and when it is
5447 * ready to enter the standby state (i.e. all ports are suspended and
5448 * all attached devices are in suspend mode), then it can wrongly assert
5449 * the Mstandby signal too early while there are still some residual OCP
5450 * transactions ongoing. If this condition occurs, the internal state
5451 * machine may go to an undefined state and the USB link may be stuck
5452 * upon the next resume.
5453 *
5454 * Workaround:
5455 * Don't use smart standby; use only force standby,
5456 * hence HWMOD_SWSUP_MSTANDBY
5457 */
5458
5459 /*
5460 * During system boot; If the hwmod framework resets the module
5461 * the module will have smart idle settings; which can lead to deadlock
5462 * (above Errata Id:i660); so, dont reset the module during boot;
5463 * Use HWMOD_INIT_NO_RESET.
5464 */
5465
5466 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5467 HWMOD_INIT_NO_RESET,
5468};
5469
5470/*
5471 * 'usb_tll_hs' class
5472 * usb_tll_hs module is the adapter on the usb_host_hs ports
5473 */
5474static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5475 .rev_offs = 0x0000,
5476 .sysc_offs = 0x0010,
5477 .syss_offs = 0x0014,
5478 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5479 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5480 SYSC_HAS_AUTOIDLE),
5481 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5482 .sysc_fields = &omap_hwmod_sysc_type1,
5483};
5484
5485static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5486 .name = "usb_tll_hs",
5487 .sysc = &omap44xx_usb_tll_hs_sysc,
5488}; 5900};
5489 5901
5490static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { 5902/* l4_cfg -> usb_otg_hs */
5491 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, 5903static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5492 { .irq = -1 } 5904 .master = &omap44xx_l4_cfg_hwmod,
5905 .slave = &omap44xx_usb_otg_hs_hwmod,
5906 .clk = "l4_div_ck",
5907 .addr = omap44xx_usb_otg_hs_addrs,
5908 .user = OCP_USER_MPU | OCP_USER_SDMA,
5493}; 5909};
5494 5910
5495static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { 5911static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
@@ -5502,6 +5918,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5502 {} 5918 {}
5503}; 5919};
5504 5920
5921/* l4_cfg -> usb_tll_hs */
5505static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { 5922static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5506 .master = &omap44xx_l4_cfg_hwmod, 5923 .master = &omap44xx_l4_cfg_hwmod,
5507 .slave = &omap44xx_usb_tll_hs_hwmod, 5924 .slave = &omap44xx_usb_tll_hs_hwmod,
@@ -5510,181 +5927,223 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5510 .user = OCP_USER_MPU | OCP_USER_SDMA, 5927 .user = OCP_USER_MPU | OCP_USER_SDMA,
5511}; 5928};
5512 5929
5513static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = { 5930static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5514 &omap44xx_l4_cfg__usb_tll_hs, 5931 {
5932 .pa_start = 0x4a314000,
5933 .pa_end = 0x4a31407f,
5934 .flags = ADDR_TYPE_RT
5935 },
5936 { }
5515}; 5937};
5516 5938
5517static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { 5939/* l4_wkup -> wd_timer2 */
5518 .name = "usb_tll_hs", 5940static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5519 .class = &omap44xx_usb_tll_hs_hwmod_class, 5941 .master = &omap44xx_l4_wkup_hwmod,
5520 .clkdm_name = "l3_init_clkdm", 5942 .slave = &omap44xx_wd_timer2_hwmod,
5521 .main_clk = "usb_tll_hs_ick", 5943 .clk = "l4_wkup_clk_mux_ck",
5522 .prcm = { 5944 .addr = omap44xx_wd_timer2_addrs,
5523 .omap4 = { 5945 .user = OCP_USER_MPU | OCP_USER_SDMA,
5524 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, 5946};
5525 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, 5947
5526 .modulemode = MODULEMODE_HWCTRL, 5948static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5527 }, 5949 {
5950 .pa_start = 0x40130000,
5951 .pa_end = 0x4013007f,
5952 .flags = ADDR_TYPE_RT
5528 }, 5953 },
5529 .mpu_irqs = omap44xx_usb_tll_hs_irqs, 5954 { }
5530 .slaves = omap44xx_usb_tll_hs_slaves,
5531 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5532}; 5955};
5533 5956
5534static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 5957/* l4_abe -> wd_timer3 */
5535 5958static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5536 /* dmm class */ 5959 .master = &omap44xx_l4_abe_hwmod,
5537 &omap44xx_dmm_hwmod, 5960 .slave = &omap44xx_wd_timer3_hwmod,
5538 5961 .clk = "ocp_abe_iclk",
5539 /* emif_fw class */ 5962 .addr = omap44xx_wd_timer3_addrs,
5540 &omap44xx_emif_fw_hwmod, 5963 .user = OCP_USER_MPU,
5541 5964};
5542 /* l3 class */ 5965
5543 &omap44xx_l3_instr_hwmod, 5966static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5544 &omap44xx_l3_main_1_hwmod, 5967 {
5545 &omap44xx_l3_main_2_hwmod, 5968 .pa_start = 0x49030000,
5546 &omap44xx_l3_main_3_hwmod, 5969 .pa_end = 0x4903007f,
5547 5970 .flags = ADDR_TYPE_RT
5548 /* l4 class */ 5971 },
5549 &omap44xx_l4_abe_hwmod, 5972 { }
5550 &omap44xx_l4_cfg_hwmod, 5973};
5551 &omap44xx_l4_per_hwmod, 5974
5552 &omap44xx_l4_wkup_hwmod, 5975/* l4_abe -> wd_timer3 (dma) */
5553 5976static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5554 /* mpu_bus class */ 5977 .master = &omap44xx_l4_abe_hwmod,
5555 &omap44xx_mpu_private_hwmod, 5978 .slave = &omap44xx_wd_timer3_hwmod,
5556 5979 .clk = "ocp_abe_iclk",
5557 /* aess class */ 5980 .addr = omap44xx_wd_timer3_dma_addrs,
5558/* &omap44xx_aess_hwmod, */ 5981 .user = OCP_USER_SDMA,
5559 5982};
5560 /* bandgap class */ 5983
5561 &omap44xx_bandgap_hwmod, 5984static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5562 5985 &omap44xx_c2c__c2c_target_fw,
5563 /* counter class */ 5986 &omap44xx_l4_cfg__c2c_target_fw,
5564/* &omap44xx_counter_32k_hwmod, */ 5987 &omap44xx_l3_main_1__dmm,
5565 5988 &omap44xx_mpu__dmm,
5566 /* dma class */ 5989 &omap44xx_c2c__emif_fw,
5567 &omap44xx_dma_system_hwmod, 5990 &omap44xx_dmm__emif_fw,
5568 5991 &omap44xx_l4_cfg__emif_fw,
5569 /* dmic class */ 5992 &omap44xx_iva__l3_instr,
5570 &omap44xx_dmic_hwmod, 5993 &omap44xx_l3_main_3__l3_instr,
5571 5994 &omap44xx_ocp_wp_noc__l3_instr,
5572 /* dsp class */ 5995 &omap44xx_dsp__l3_main_1,
5573 &omap44xx_dsp_hwmod, 5996 &omap44xx_dss__l3_main_1,
5574 &omap44xx_dsp_c0_hwmod, 5997 &omap44xx_l3_main_2__l3_main_1,
5575 5998 &omap44xx_l4_cfg__l3_main_1,
5576 /* dss class */ 5999 &omap44xx_mmc1__l3_main_1,
5577 &omap44xx_dss_hwmod, 6000 &omap44xx_mmc2__l3_main_1,
5578 &omap44xx_dss_dispc_hwmod, 6001 &omap44xx_mpu__l3_main_1,
5579 &omap44xx_dss_dsi1_hwmod, 6002 &omap44xx_c2c_target_fw__l3_main_2,
5580 &omap44xx_dss_dsi2_hwmod, 6003 &omap44xx_debugss__l3_main_2,
5581 &omap44xx_dss_hdmi_hwmod, 6004 &omap44xx_dma_system__l3_main_2,
5582 &omap44xx_dss_rfbi_hwmod, 6005 &omap44xx_fdif__l3_main_2,
5583 &omap44xx_dss_venc_hwmod, 6006 &omap44xx_gpu__l3_main_2,
5584 6007 &omap44xx_hsi__l3_main_2,
5585 /* gpio class */ 6008 &omap44xx_ipu__l3_main_2,
5586 &omap44xx_gpio1_hwmod, 6009 &omap44xx_iss__l3_main_2,
5587 &omap44xx_gpio2_hwmod, 6010 &omap44xx_iva__l3_main_2,
5588 &omap44xx_gpio3_hwmod, 6011 &omap44xx_l3_main_1__l3_main_2,
5589 &omap44xx_gpio4_hwmod, 6012 &omap44xx_l4_cfg__l3_main_2,
5590 &omap44xx_gpio5_hwmod, 6013 &omap44xx_usb_host_fs__l3_main_2,
5591 &omap44xx_gpio6_hwmod, 6014 &omap44xx_usb_host_hs__l3_main_2,
5592 6015 &omap44xx_usb_otg_hs__l3_main_2,
5593 /* hsi class */ 6016 &omap44xx_l3_main_1__l3_main_3,
5594/* &omap44xx_hsi_hwmod, */ 6017 &omap44xx_l3_main_2__l3_main_3,
5595 6018 &omap44xx_l4_cfg__l3_main_3,
5596 /* i2c class */ 6019 &omap44xx_aess__l4_abe,
5597 &omap44xx_i2c1_hwmod, 6020 &omap44xx_dsp__l4_abe,
5598 &omap44xx_i2c2_hwmod, 6021 &omap44xx_l3_main_1__l4_abe,
5599 &omap44xx_i2c3_hwmod, 6022 &omap44xx_mpu__l4_abe,
5600 &omap44xx_i2c4_hwmod, 6023 &omap44xx_l3_main_1__l4_cfg,
5601 6024 &omap44xx_l3_main_2__l4_per,
5602 /* ipu class */ 6025 &omap44xx_l4_cfg__l4_wkup,
5603 &omap44xx_ipu_hwmod, 6026 &omap44xx_mpu__mpu_private,
5604 &omap44xx_ipu_c0_hwmod, 6027 &omap44xx_l4_cfg__ocp_wp_noc,
5605 &omap44xx_ipu_c1_hwmod, 6028 &omap44xx_l4_abe__aess,
5606 6029 &omap44xx_l4_abe__aess_dma,
5607 /* iss class */ 6030 &omap44xx_l3_main_2__c2c,
5608/* &omap44xx_iss_hwmod, */ 6031 &omap44xx_l4_wkup__counter_32k,
5609 6032 &omap44xx_l4_cfg__ctrl_module_core,
5610 /* iva class */ 6033 &omap44xx_l4_cfg__ctrl_module_pad_core,
5611 &omap44xx_iva_hwmod, 6034 &omap44xx_l4_wkup__ctrl_module_wkup,
5612 &omap44xx_iva_seq0_hwmod, 6035 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
5613 &omap44xx_iva_seq1_hwmod, 6036 &omap44xx_l3_instr__debugss,
5614 6037 &omap44xx_l4_cfg__dma_system,
5615 /* kbd class */ 6038 &omap44xx_l4_abe__dmic,
5616 &omap44xx_kbd_hwmod, 6039 &omap44xx_l4_abe__dmic_dma,
5617 6040 &omap44xx_dsp__iva,
5618 /* mailbox class */ 6041 &omap44xx_dsp__sl2if,
5619 &omap44xx_mailbox_hwmod, 6042 &omap44xx_l4_cfg__dsp,
5620 6043 &omap44xx_l3_main_2__dss,
5621 /* mcbsp class */ 6044 &omap44xx_l4_per__dss,
5622 &omap44xx_mcbsp1_hwmod, 6045 &omap44xx_l3_main_2__dss_dispc,
5623 &omap44xx_mcbsp2_hwmod, 6046 &omap44xx_l4_per__dss_dispc,
5624 &omap44xx_mcbsp3_hwmod, 6047 &omap44xx_l3_main_2__dss_dsi1,
5625 &omap44xx_mcbsp4_hwmod, 6048 &omap44xx_l4_per__dss_dsi1,
5626 6049 &omap44xx_l3_main_2__dss_dsi2,
5627 /* mcpdm class */ 6050 &omap44xx_l4_per__dss_dsi2,
5628 &omap44xx_mcpdm_hwmod, 6051 &omap44xx_l3_main_2__dss_hdmi,
5629 6052 &omap44xx_l4_per__dss_hdmi,
5630 /* mcspi class */ 6053 &omap44xx_l3_main_2__dss_rfbi,
5631 &omap44xx_mcspi1_hwmod, 6054 &omap44xx_l4_per__dss_rfbi,
5632 &omap44xx_mcspi2_hwmod, 6055 &omap44xx_l3_main_2__dss_venc,
5633 &omap44xx_mcspi3_hwmod, 6056 &omap44xx_l4_per__dss_venc,
5634 &omap44xx_mcspi4_hwmod, 6057 &omap44xx_l4_per__elm,
5635 6058 &omap44xx_emif_fw__emif1,
5636 /* mmc class */ 6059 &omap44xx_emif_fw__emif2,
5637 &omap44xx_mmc1_hwmod, 6060 &omap44xx_l4_cfg__fdif,
5638 &omap44xx_mmc2_hwmod, 6061 &omap44xx_l4_wkup__gpio1,
5639 &omap44xx_mmc3_hwmod, 6062 &omap44xx_l4_per__gpio2,
5640 &omap44xx_mmc4_hwmod, 6063 &omap44xx_l4_per__gpio3,
5641 &omap44xx_mmc5_hwmod, 6064 &omap44xx_l4_per__gpio4,
5642 6065 &omap44xx_l4_per__gpio5,
5643 /* mpu class */ 6066 &omap44xx_l4_per__gpio6,
5644 &omap44xx_mpu_hwmod, 6067 &omap44xx_l3_main_2__gpmc,
5645 6068 &omap44xx_l3_main_2__gpu,
5646 /* smartreflex class */ 6069 &omap44xx_l4_per__hdq1w,
5647 &omap44xx_smartreflex_core_hwmod, 6070 &omap44xx_l4_cfg__hsi,
5648 &omap44xx_smartreflex_iva_hwmod, 6071 &omap44xx_l4_per__i2c1,
5649 &omap44xx_smartreflex_mpu_hwmod, 6072 &omap44xx_l4_per__i2c2,
5650 6073 &omap44xx_l4_per__i2c3,
5651 /* spinlock class */ 6074 &omap44xx_l4_per__i2c4,
5652 &omap44xx_spinlock_hwmod, 6075 &omap44xx_l3_main_2__ipu,
5653 6076 &omap44xx_l3_main_2__iss,
5654 /* timer class */ 6077 &omap44xx_iva__sl2if,
5655 &omap44xx_timer1_hwmod, 6078 &omap44xx_l3_main_2__iva,
5656 &omap44xx_timer2_hwmod, 6079 &omap44xx_l4_wkup__kbd,
5657 &omap44xx_timer3_hwmod, 6080 &omap44xx_l4_cfg__mailbox,
5658 &omap44xx_timer4_hwmod, 6081 &omap44xx_l4_abe__mcasp,
5659 &omap44xx_timer5_hwmod, 6082 &omap44xx_l4_abe__mcasp_dma,
5660 &omap44xx_timer6_hwmod, 6083 &omap44xx_l4_abe__mcbsp1,
5661 &omap44xx_timer7_hwmod, 6084 &omap44xx_l4_abe__mcbsp1_dma,
5662 &omap44xx_timer8_hwmod, 6085 &omap44xx_l4_abe__mcbsp2,
5663 &omap44xx_timer9_hwmod, 6086 &omap44xx_l4_abe__mcbsp2_dma,
5664 &omap44xx_timer10_hwmod, 6087 &omap44xx_l4_abe__mcbsp3,
5665 &omap44xx_timer11_hwmod, 6088 &omap44xx_l4_abe__mcbsp3_dma,
5666 6089 &omap44xx_l4_per__mcbsp4,
5667 /* uart class */ 6090 &omap44xx_l4_abe__mcpdm,
5668 &omap44xx_uart1_hwmod, 6091 &omap44xx_l4_abe__mcpdm_dma,
5669 &omap44xx_uart2_hwmod, 6092 &omap44xx_l4_per__mcspi1,
5670 &omap44xx_uart3_hwmod, 6093 &omap44xx_l4_per__mcspi2,
5671 &omap44xx_uart4_hwmod, 6094 &omap44xx_l4_per__mcspi3,
5672 6095 &omap44xx_l4_per__mcspi4,
5673 /* usb host class */ 6096 &omap44xx_l4_per__mmc1,
5674 &omap44xx_usb_host_hs_hwmod, 6097 &omap44xx_l4_per__mmc2,
5675 &omap44xx_usb_tll_hs_hwmod, 6098 &omap44xx_l4_per__mmc3,
5676 6099 &omap44xx_l4_per__mmc4,
5677 /* usb_otg_hs class */ 6100 &omap44xx_l4_per__mmc5,
5678 &omap44xx_usb_otg_hs_hwmod, 6101 &omap44xx_l3_main_2__ocmc_ram,
5679 6102 &omap44xx_l4_cfg__ocp2scp_usb_phy,
5680 /* wd_timer class */ 6103 &omap44xx_mpu_private__prcm_mpu,
5681 &omap44xx_wd_timer2_hwmod, 6104 &omap44xx_l4_wkup__cm_core_aon,
5682 &omap44xx_wd_timer3_hwmod, 6105 &omap44xx_l4_cfg__cm_core,
6106 &omap44xx_l4_wkup__prm,
6107 &omap44xx_l4_wkup__scrm,
6108 &omap44xx_l3_main_2__sl2if,
6109 &omap44xx_l4_abe__slimbus1,
6110 &omap44xx_l4_abe__slimbus1_dma,
6111 &omap44xx_l4_per__slimbus2,
6112 &omap44xx_l4_cfg__smartreflex_core,
6113 &omap44xx_l4_cfg__smartreflex_iva,
6114 &omap44xx_l4_cfg__smartreflex_mpu,
6115 &omap44xx_l4_cfg__spinlock,
6116 &omap44xx_l4_wkup__timer1,
6117 &omap44xx_l4_per__timer2,
6118 &omap44xx_l4_per__timer3,
6119 &omap44xx_l4_per__timer4,
6120 &omap44xx_l4_abe__timer5,
6121 &omap44xx_l4_abe__timer5_dma,
6122 &omap44xx_l4_abe__timer6,
6123 &omap44xx_l4_abe__timer6_dma,
6124 &omap44xx_l4_abe__timer7,
6125 &omap44xx_l4_abe__timer7_dma,
6126 &omap44xx_l4_abe__timer8,
6127 &omap44xx_l4_abe__timer8_dma,
6128 &omap44xx_l4_per__timer9,
6129 &omap44xx_l4_per__timer10,
6130 &omap44xx_l4_per__timer11,
6131 &omap44xx_l4_per__uart1,
6132 &omap44xx_l4_per__uart2,
6133 &omap44xx_l4_per__uart3,
6134 &omap44xx_l4_per__uart4,
6135 &omap44xx_l4_cfg__usb_host_fs,
6136 &omap44xx_l4_cfg__usb_host_hs,
6137 &omap44xx_l4_cfg__usb_otg_hs,
6138 &omap44xx_l4_cfg__usb_tll_hs,
6139 &omap44xx_l4_wkup__wd_timer2,
6140 &omap44xx_l4_abe__wd_timer3,
6141 &omap44xx_l4_abe__wd_timer3_dma,
5683 NULL, 6142 NULL,
5684}; 6143};
5685 6144
5686int __init omap44xx_hwmod_init(void) 6145int __init omap44xx_hwmod_init(void)
5687{ 6146{
5688 return omap_hwmod_register(omap44xx_hwmods); 6147 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
5689} 6148}
5690 6149
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index ad5d8f04c0b8..e7e8eeae95e5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -19,18 +19,6 @@
19#include "display.h" 19#include "display.h"
20 20
21/* Common address space across OMAP2xxx */ 21/* Common address space across OMAP2xxx */
22extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
23extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
24extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
25extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
26extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
27extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
28extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
29extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
30extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
31extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
32extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
33extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
34extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[]; 22extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
35 23
36/* Common address space across OMAP2xxx/3xxx */ 24/* Common address space across OMAP2xxx/3xxx */
@@ -50,10 +38,70 @@ extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
50extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; 38extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
51extern struct omap_hwmod_addr_space omap2_mailbox_addrs[]; 39extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
52extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; 40extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
41extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
53 42
54/* Common IP block data across OMAP2xxx */ 43/* Common IP block data across OMAP2xxx */
55extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; 44extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
56extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[]; 45extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
46extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
47extern struct omap_hwmod omap2xxx_l3_main_hwmod;
48extern struct omap_hwmod omap2xxx_l4_core_hwmod;
49extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
50extern struct omap_hwmod omap2xxx_mpu_hwmod;
51extern struct omap_hwmod omap2xxx_iva_hwmod;
52extern struct omap_hwmod omap2xxx_timer1_hwmod;
53extern struct omap_hwmod omap2xxx_timer2_hwmod;
54extern struct omap_hwmod omap2xxx_timer3_hwmod;
55extern struct omap_hwmod omap2xxx_timer4_hwmod;
56extern struct omap_hwmod omap2xxx_timer5_hwmod;
57extern struct omap_hwmod omap2xxx_timer6_hwmod;
58extern struct omap_hwmod omap2xxx_timer7_hwmod;
59extern struct omap_hwmod omap2xxx_timer8_hwmod;
60extern struct omap_hwmod omap2xxx_timer9_hwmod;
61extern struct omap_hwmod omap2xxx_timer10_hwmod;
62extern struct omap_hwmod omap2xxx_timer11_hwmod;
63extern struct omap_hwmod omap2xxx_timer12_hwmod;
64extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
65extern struct omap_hwmod omap2xxx_uart1_hwmod;
66extern struct omap_hwmod omap2xxx_uart2_hwmod;
67extern struct omap_hwmod omap2xxx_uart3_hwmod;
68extern struct omap_hwmod omap2xxx_dss_core_hwmod;
69extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
70extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
71extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
72extern struct omap_hwmod omap2xxx_gpio1_hwmod;
73extern struct omap_hwmod omap2xxx_gpio2_hwmod;
74extern struct omap_hwmod omap2xxx_gpio3_hwmod;
75extern struct omap_hwmod omap2xxx_gpio4_hwmod;
76extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
77extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
78extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
79
80/* Common interface data across OMAP2xxx */
81extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
82extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
83extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
84extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
85extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
86extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
87extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
88extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
89extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
90extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
91extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
92extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
93extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
94extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
95extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
96extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
97extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
98extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
99extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
100extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
101extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
102extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
103extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
104extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
57 105
58/* Common IP block data */ 106/* Common IP block data */
59extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[]; 107extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
@@ -94,6 +142,8 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
94extern struct omap_hwmod_irq_info omap2_dma_system_irqs[]; 142extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
95extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[]; 143extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
96extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[]; 144extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
145extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
146extern struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[];
97 147
98/* OMAP hwmod classes - forward declarations */ 148/* OMAP hwmod classes - forward declarations */
99extern struct omap_hwmod_class l3_hwmod_class; 149extern struct omap_hwmod_class l3_hwmod_class;
@@ -105,6 +155,8 @@ extern struct omap_hwmod_class omap2_dss_hwmod_class;
105extern struct omap_hwmod_class omap2_dispc_hwmod_class; 155extern struct omap_hwmod_class omap2_dispc_hwmod_class;
106extern struct omap_hwmod_class omap2_rfbi_hwmod_class; 156extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
107extern struct omap_hwmod_class omap2_venc_hwmod_class; 157extern struct omap_hwmod_class omap2_venc_hwmod_class;
158extern struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc;
159extern struct omap_hwmod_class omap2_hdq1w_class;
108 160
109extern struct omap_hwmod_class omap2xxx_timer_hwmod_class; 161extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
110extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class; 162extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 36fa90b6ece8..78564895e914 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -38,27 +38,6 @@ static inline int omap4_opp_init(void)
38} 38}
39#endif 39#endif
40 40
41/*
42 * cpuidle mach specific parameters
43 *
44 * The board code can override the default C-states definition using
45 * omap3_pm_init_cpuidle
46 */
47struct cpuidle_params {
48 u32 exit_latency; /* exit_latency = sleep + wake-up latencies */
49 u32 target_residency;
50 u8 valid; /* validates the C-state */
51};
52
53#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
54extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
55#else
56static
57inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
58{
59}
60#endif
61
62extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); 41extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
63extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); 42extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
64 43
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 95442b69ae27..facfffca9eac 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -171,8 +171,6 @@ static int omap2_allow_mpu_retention(void)
171 171
172static void omap2_enter_mpu_retention(void) 172static void omap2_enter_mpu_retention(void)
173{ 173{
174 int only_idle = 0;
175
176 /* Putting MPU into the WFI state while a transfer is active 174 /* Putting MPU into the WFI state while a transfer is active
177 * seems to cause the I2C block to timeout. Why? Good question. */ 175 * seems to cause the I2C block to timeout. Why? Good question. */
178 if (omap2_i2c_active()) 176 if (omap2_i2c_active())
@@ -195,7 +193,6 @@ static void omap2_enter_mpu_retention(void)
195 193
196 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, 194 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
197 OMAP2_PM_PWSTCTRL); 195 OMAP2_PM_PWSTCTRL);
198 only_idle = 1;
199 } 196 }
200 197
201 omap2_sram_idle(); 198 omap2_sram_idle();
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 703bd1099259..8b43aefba0ea 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -273,7 +273,7 @@ void omap_sram_idle(void)
273 int per_next_state = PWRDM_POWER_ON; 273 int per_next_state = PWRDM_POWER_ON;
274 int core_next_state = PWRDM_POWER_ON; 274 int core_next_state = PWRDM_POWER_ON;
275 int per_going_off; 275 int per_going_off;
276 int core_prev_state, per_prev_state; 276 int core_prev_state;
277 u32 sdrc_pwr = 0; 277 u32 sdrc_pwr = 0;
278 278
279 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 279 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
@@ -375,10 +375,8 @@ void omap_sram_idle(void)
375 pwrdm_post_transition(); 375 pwrdm_post_transition();
376 376
377 /* PER */ 377 /* PER */
378 if (per_next_state < PWRDM_POWER_ON) { 378 if (per_next_state < PWRDM_POWER_ON)
379 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
380 omap2_gpio_resume_after_idle(); 379 omap2_gpio_resume_after_idle();
381 }
382 380
383 /* Disable IO-PAD and IO-CHAIN wakeup */ 381 /* Disable IO-PAD and IO-CHAIN wakeup */
384 if (omap3_has_io_wakeup() && 382 if (omap3_has_io_wakeup() &&
@@ -702,7 +700,7 @@ static void __init pm_errata_configure(void)
702static int __init omap3_pm_init(void) 700static int __init omap3_pm_init(void)
703{ 701{
704 struct power_state *pwrst, *tmp; 702 struct power_state *pwrst, *tmp;
705 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; 703 struct clockdomain *neon_clkdm, *mpu_clkdm;
706 int ret; 704 int ret;
707 705
708 if (!cpu_is_omap34xx()) 706 if (!cpu_is_omap34xx())
@@ -757,8 +755,6 @@ static int __init omap3_pm_init(void)
757 755
758 neon_clkdm = clkdm_lookup("neon_clkdm"); 756 neon_clkdm = clkdm_lookup("neon_clkdm");
759 mpu_clkdm = clkdm_lookup("mpu_clkdm"); 757 mpu_clkdm = clkdm_lookup("mpu_clkdm");
760 per_clkdm = clkdm_lookup("per_clkdm");
761 core_clkdm = clkdm_lookup("core_clkdm");
762 758
763#ifdef CONFIG_SUSPEND 759#ifdef CONFIG_SUSPEND
764 omap_pm_suspend = omap3_pm_suspend; 760 omap_pm_suspend = omap3_pm_suspend;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96ad3dbeac34..96114901b932 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
981 return ret; 981 return ret;
982} 982}
983 983
984int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
985{
986 if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
987 pwrdm_wait_transition(clkdm->pwrdm.ptr);
988 return pwrdm_state_switch(clkdm->pwrdm.ptr);
989 }
990
991 return -EINVAL;
992}
993
994int pwrdm_pre_transition(void) 984int pwrdm_pre_transition(void)
995{ 985{
996 pwrdm_for_each(_pwrdm_pre_transition_cb, NULL); 986 pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a8ce4d..8f88d65c46ea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
213int pwrdm_wait_transition(struct powerdomain *pwrdm); 213int pwrdm_wait_transition(struct powerdomain *pwrdm);
214 214
215int pwrdm_state_switch(struct powerdomain *pwrdm); 215int pwrdm_state_switch(struct powerdomain *pwrdm);
216int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
217int pwrdm_pre_transition(void); 216int pwrdm_pre_transition(void);
218int pwrdm_post_transition(void); 217int pwrdm_post_transition(void);
219int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); 218int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5aa5435e3ff1..6da3ba483ad1 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -177,6 +177,8 @@
177/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 177/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
178#define OMAP24XX_ST_GPIOS_SHIFT 2 178#define OMAP24XX_ST_GPIOS_SHIFT 2
179#define OMAP24XX_ST_GPIOS_MASK (1 << 2) 179#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
180#define OMAP24XX_ST_32KSYNC_SHIFT 1
181#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
180#define OMAP24XX_ST_GPT1_SHIFT 0 182#define OMAP24XX_ST_GPT1_SHIFT 0
181#define OMAP24XX_ST_GPT1_MASK (1 << 0) 183#define OMAP24XX_ST_GPT1_MASK (1 << 0)
182 184
@@ -307,6 +309,8 @@
307#define OMAP3430_ST_SR1_MASK (1 << 6) 309#define OMAP3430_ST_SR1_MASK (1 << 6)
308#define OMAP3430_ST_GPIO1_SHIFT 3 310#define OMAP3430_ST_GPIO1_SHIFT 3
309#define OMAP3430_ST_GPIO1_MASK (1 << 3) 311#define OMAP3430_ST_GPIO1_MASK (1 << 3)
312#define OMAP3430_ST_32KSYNC_SHIFT 2
313#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
310#define OMAP3430_ST_GPT12_SHIFT 1 314#define OMAP3430_ST_GPT12_SHIFT 1
311#define OMAP3430_ST_GPT12_MASK (1 << 1) 315#define OMAP3430_ST_GPT12_MASK (1 << 1)
312#define OMAP3430_ST_GPT1_SHIFT 0 316#define OMAP3430_ST_GPT1_SHIFT 0
@@ -410,6 +414,19 @@
410extern void __iomem *prm_base; 414extern void __iomem *prm_base;
411extern void __iomem *cm_base; 415extern void __iomem *cm_base;
412extern void __iomem *cm2_base; 416extern void __iomem *cm2_base;
417extern void __iomem *prcm_mpu_base;
418
419#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
420extern void omap_prm_base_init(void);
421extern void omap_cm_base_init(void);
422#else
423static inline void omap_prm_base_init(void)
424{
425}
426static inline void omap_cm_base_init(void)
427{
428}
429#endif
413 430
414/** 431/**
415 * struct omap_prcm_irq - describes a PRCM interrupt bit 432 * struct omap_prcm_irq - describes a PRCM interrupt bit
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 626acfad7190..480f40a5ee42 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -42,6 +42,7 @@
42void __iomem *prm_base; 42void __iomem *prm_base;
43void __iomem *cm_base; 43void __iomem *cm_base;
44void __iomem *cm2_base; 44void __iomem *cm2_base;
45void __iomem *prcm_mpu_base;
45 46
46#define MAX_MODULE_ENABLE_WAIT 100000 47#define MAX_MODULE_ENABLE_WAIT 100000
47 48
@@ -155,4 +156,11 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
155 cm_base = omap2_globals->cm; 156 cm_base = omap2_globals->cm;
156 if (omap2_globals->cm2) 157 if (omap2_globals->cm2)
157 cm2_base = omap2_globals->cm2; 158 cm2_base = omap2_globals->cm2;
159 if (omap2_globals->prcm_mpu)
160 prcm_mpu_base = omap2_globals->prcm_mpu;
161
162 if (cpu_is_omap44xx()) {
163 omap_prm_base_init();
164 omap_cm_base_init();
165 }
158} 166}
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index d28f848897d6..dfe00ddb5c60 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -237,7 +237,7 @@ void omap_prcm_irq_complete(void)
237 */ 237 */
238int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) 238int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
239{ 239{
240 int nr_regs = irq_setup->nr_regs; 240 int nr_regs;
241 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; 241 u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
242 int offset, i; 242 int offset, i;
243 struct irq_chip_generic *gc; 243 struct irq_chip_generic *gc;
@@ -246,6 +246,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
246 if (!irq_setup) 246 if (!irq_setup)
247 return -EINVAL; 247 return -EINVAL;
248 248
249 nr_regs = irq_setup->nr_regs;
250
249 if (prcm_irq_setup) { 251 if (prcm_irq_setup) {
250 pr_err("PRCM: already initialized; won't reinitialize\n"); 252 pr_err("PRCM: already initialized; won't reinitialize\n");
251 return -EINVAL; 253 return -EINVAL;
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 9b3898a3ac9b..c12320c0ae95 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -18,20 +18,26 @@
18 18
19#include "iomap.h" 19#include "iomap.h"
20#include "common.h" 20#include "common.h"
21#include "prcm-common.h"
21#include "prm44xx.h" 22#include "prm44xx.h"
22#include "prminst44xx.h" 23#include "prminst44xx.h"
23#include "prm-regbits-44xx.h" 24#include "prm-regbits-44xx.h"
24#include "prcm44xx.h" 25#include "prcm44xx.h"
25#include "prcm_mpu44xx.h" 26#include "prcm_mpu44xx.h"
26 27
27static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { 28static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
28 [OMAP4430_INVALID_PRCM_PARTITION] = 0, 29
29 [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, 30/**
30 [OMAP4430_CM1_PARTITION] = 0, 31 * omap_prm_base_init - Populates the prm partitions
31 [OMAP4430_CM2_PARTITION] = 0, 32 *
32 [OMAP4430_SCRM_PARTITION] = 0, 33 * Populates the base addresses of the _prm_bases
33 [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, 34 * array used for read/write of prm module registers.
34}; 35 */
36void omap_prm_base_init(void)
37{
38 _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
39 _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
40}
35 41
36/* Read a register in a PRM instance */ 42/* Read a register in a PRM instance */
37u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) 43u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
@@ -39,8 +45,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
39 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 45 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
40 part == OMAP4430_INVALID_PRCM_PARTITION || 46 part == OMAP4430_INVALID_PRCM_PARTITION ||
41 !_prm_bases[part]); 47 !_prm_bases[part]);
42 return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + 48 return __raw_readl(_prm_bases[part] + inst + idx);
43 idx));
44} 49}
45 50
46/* Write into a register in a PRM instance */ 51/* Write into a register in a PRM instance */
@@ -49,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
49 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 54 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
50 part == OMAP4430_INVALID_PRCM_PARTITION || 55 part == OMAP4430_INVALID_PRCM_PARTITION ||
51 !_prm_bases[part]); 56 !_prm_bases[part]);
52 __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx)); 57 __raw_writel(val, _prm_bases[part] + inst + idx);
53} 58}
54 59
55/* Read-modify-write a register in PRM. Caller must lock */ 60/* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 9fc2f44188cb..292d4aaca068 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -133,7 +133,7 @@ static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
133static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} 133static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
134#endif 134#endif
135 135
136char *cmdline_find_option(char *str) 136static char *cmdline_find_option(char *str)
137{ 137{
138 extern char *saved_command_line; 138 extern char *saved_command_line;
139 139
@@ -245,14 +245,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
245 omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate; 245 omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
246 omap_up.autosuspend_timeout = info->autosuspend_timeout; 246 omap_up.autosuspend_timeout = info->autosuspend_timeout;
247 247
248 /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
249 if (!cpu_is_omap2420() && !cpu_is_ti816x())
250 omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
251
252 /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
253 if (cpu_is_omap34xx() || cpu_is_omap3630())
254 omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
255
256 pdata = &omap_up; 248 pdata = &omap_up;
257 pdata_size = sizeof(struct omap_uart_port_info); 249 pdata_size = sizeof(struct omap_uart_port_info);
258 250
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index c512bac69ec5..1b7835865c83 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -145,8 +145,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
145{ 145{
146 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 146 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
147 struct omap_hwmod *oh; 147 struct omap_hwmod *oh;
148 struct resource irq_rsrc, mem_rsrc;
148 size_t size; 149 size_t size;
149 int res = 0; 150 int res = 0;
151 int r;
150 152
151 sprintf(name, "timer%d", gptimer_id); 153 sprintf(name, "timer%d", gptimer_id);
152 omap_hwmod_setup_one(name); 154 omap_hwmod_setup_one(name);
@@ -154,9 +156,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
154 if (!oh) 156 if (!oh)
155 return -ENODEV; 157 return -ENODEV;
156 158
157 timer->irq = oh->mpu_irqs[0].irq; 159 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
158 timer->phys_base = oh->slaves[0]->addr->pa_start; 160 if (r)
159 size = oh->slaves[0]->addr->pa_end - timer->phys_base; 161 return -ENXIO;
162 timer->irq = irq_rsrc.start;
163
164 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
165 if (r)
166 return -ENXIO;
167 timer->phys_base = mem_rsrc.start;
168 size = mem_rsrc.end - mem_rsrc.start;
160 169
161 /* Static mapping, never released */ 170 /* Static mapping, never released */
162 timer->io_base = ioremap(timer->phys_base, size); 171 timer->io_base = ioremap(timer->phys_base, size);
@@ -169,13 +178,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
169 if (IS_ERR(timer->fclk)) 178 if (IS_ERR(timer->fclk))
170 return -ENODEV; 179 return -ENODEV;
171 180
172 sprintf(name, "gpt%d_ick", gptimer_id);
173 timer->iclk = clk_get(NULL, name);
174 if (IS_ERR(timer->iclk)) {
175 clk_put(timer->fclk);
176 return -ENODEV;
177 }
178
179 omap_hwmod_enable(oh); 181 omap_hwmod_enable(oh);
180 182
181 sys_timer_reserved |= (1 << (gptimer_id - 1)); 183 sys_timer_reserved |= (1 << (gptimer_id - 1));
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 7a7b89304c48..119d5a910f3a 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -31,6 +31,7 @@
31 31
32#include "twl-common.h" 32#include "twl-common.h"
33#include "pm.h" 33#include "pm.h"
34#include "voltage.h"
34 35
35static struct i2c_board_info __initdata pmic_i2c_board_info = { 36static struct i2c_board_info __initdata pmic_i2c_board_info = {
36 .addr = 0x48, 37 .addr = 0x48,
@@ -47,6 +48,18 @@ static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
47 }, 48 },
48}; 49};
49 50
51static int twl_set_voltage(void *data, int target_uV)
52{
53 struct voltagedomain *voltdm = (struct voltagedomain *)data;
54 return voltdm_scale(voltdm, target_uV);
55}
56
57static int twl_get_voltage(void *data)
58{
59 struct voltagedomain *voltdm = (struct voltagedomain *)data;
60 return voltdm_get_voltage(voltdm);
61}
62
50void __init omap_pmic_init(int bus, u32 clkrate, 63void __init omap_pmic_init(int bus, u32 clkrate,
51 const char *pmic_type, int pmic_irq, 64 const char *pmic_type, int pmic_irq,
52 struct twl4030_platform_data *pmic_data) 65 struct twl4030_platform_data *pmic_data)
@@ -153,6 +166,48 @@ static struct regulator_init_data omap3_vpll2_idata = {
153 .consumer_supplies = omap3_vpll2_supplies, 166 .consumer_supplies = omap3_vpll2_supplies,
154}; 167};
155 168
169static struct regulator_consumer_supply omap3_vdd1_supply[] = {
170 REGULATOR_SUPPLY("vcc", "mpu.0"),
171};
172
173static struct regulator_consumer_supply omap3_vdd2_supply[] = {
174 REGULATOR_SUPPLY("vcc", "l3_main.0"),
175};
176
177static struct regulator_init_data omap3_vdd1 = {
178 .constraints = {
179 .name = "vdd_mpu_iva",
180 .min_uV = 600000,
181 .max_uV = 1450000,
182 .valid_modes_mask = REGULATOR_MODE_NORMAL,
183 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
184 },
185 .num_consumer_supplies = ARRAY_SIZE(omap3_vdd1_supply),
186 .consumer_supplies = omap3_vdd1_supply,
187};
188
189static struct regulator_init_data omap3_vdd2 = {
190 .constraints = {
191 .name = "vdd_core",
192 .min_uV = 600000,
193 .max_uV = 1450000,
194 .valid_modes_mask = REGULATOR_MODE_NORMAL,
195 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
196 },
197 .num_consumer_supplies = ARRAY_SIZE(omap3_vdd2_supply),
198 .consumer_supplies = omap3_vdd2_supply,
199};
200
201static struct twl_regulator_driver_data omap3_vdd1_drvdata = {
202 .get_voltage = twl_get_voltage,
203 .set_voltage = twl_set_voltage,
204};
205
206static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
207 .get_voltage = twl_get_voltage,
208 .set_voltage = twl_set_voltage,
209};
210
156void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, 211void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
157 u32 pdata_flags, u32 regulators_flags) 212 u32 pdata_flags, u32 regulators_flags)
158{ 213{
@@ -160,6 +215,16 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
160 pmic_data->irq_base = TWL4030_IRQ_BASE; 215 pmic_data->irq_base = TWL4030_IRQ_BASE;
161 if (!pmic_data->irq_end) 216 if (!pmic_data->irq_end)
162 pmic_data->irq_end = TWL4030_IRQ_END; 217 pmic_data->irq_end = TWL4030_IRQ_END;
218 if (!pmic_data->vdd1) {
219 omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
220 omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
221 pmic_data->vdd1 = &omap3_vdd1;
222 }
223 if (!pmic_data->vdd2) {
224 omap3_vdd2.driver_data = &omap3_vdd2_drvdata;
225 omap3_vdd2_drvdata.data = voltdm_lookup("core");
226 pmic_data->vdd2 = &omap3_vdd2;
227 }
163 228
164 /* Common platform data configurations */ 229 /* Common platform data configurations */
165 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb) 230 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
@@ -201,6 +266,7 @@ static struct regulator_init_data omap4_vdac_idata = {
201 .valid_ops_mask = REGULATOR_CHANGE_MODE 266 .valid_ops_mask = REGULATOR_CHANGE_MODE
202 | REGULATOR_CHANGE_STATUS, 267 | REGULATOR_CHANGE_STATUS,
203 }, 268 },
269 .supply_regulator = "V2V1",
204}; 270};
205 271
206static struct regulator_init_data omap4_vaux2_idata = { 272static struct regulator_init_data omap4_vaux2_idata = {
@@ -291,6 +357,7 @@ static struct regulator_init_data omap4_vcxio_idata = {
291 }, 357 },
292 .num_consumer_supplies = ARRAY_SIZE(omap4_vcxio_supply), 358 .num_consumer_supplies = ARRAY_SIZE(omap4_vcxio_supply),
293 .consumer_supplies = omap4_vcxio_supply, 359 .consumer_supplies = omap4_vcxio_supply,
360 .supply_regulator = "V2V1",
294}; 361};
295 362
296static struct regulator_init_data omap4_vusb_idata = { 363static struct regulator_init_data omap4_vusb_idata = {
@@ -310,6 +377,105 @@ static struct regulator_init_data omap4_clk32kg_idata = {
310 }, 377 },
311}; 378};
312 379
380static struct regulator_consumer_supply omap4_vdd1_supply[] = {
381 REGULATOR_SUPPLY("vcc", "mpu.0"),
382};
383
384static struct regulator_consumer_supply omap4_vdd2_supply[] = {
385 REGULATOR_SUPPLY("vcc", "iva.0"),
386};
387
388static struct regulator_consumer_supply omap4_vdd3_supply[] = {
389 REGULATOR_SUPPLY("vcc", "l3_main.0"),
390};
391
392static struct regulator_init_data omap4_vdd1 = {
393 .constraints = {
394 .name = "vdd_mpu",
395 .min_uV = 500000,
396 .max_uV = 1500000,
397 .valid_modes_mask = REGULATOR_MODE_NORMAL,
398 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
399 },
400 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd1_supply),
401 .consumer_supplies = omap4_vdd1_supply,
402};
403
404static struct regulator_init_data omap4_vdd2 = {
405 .constraints = {
406 .name = "vdd_iva",
407 .min_uV = 500000,
408 .max_uV = 1500000,
409 .valid_modes_mask = REGULATOR_MODE_NORMAL,
410 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
411 },
412 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd2_supply),
413 .consumer_supplies = omap4_vdd2_supply,
414};
415
416static struct regulator_init_data omap4_vdd3 = {
417 .constraints = {
418 .name = "vdd_core",
419 .min_uV = 500000,
420 .max_uV = 1500000,
421 .valid_modes_mask = REGULATOR_MODE_NORMAL,
422 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
423 },
424 .num_consumer_supplies = ARRAY_SIZE(omap4_vdd3_supply),
425 .consumer_supplies = omap4_vdd3_supply,
426};
427
428
429static struct twl_regulator_driver_data omap4_vdd1_drvdata = {
430 .get_voltage = twl_get_voltage,
431 .set_voltage = twl_set_voltage,
432};
433
434static struct twl_regulator_driver_data omap4_vdd2_drvdata = {
435 .get_voltage = twl_get_voltage,
436 .set_voltage = twl_set_voltage,
437};
438
439static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
440 .get_voltage = twl_get_voltage,
441 .set_voltage = twl_set_voltage,
442};
443
444static struct regulator_consumer_supply omap4_v1v8_supply[] = {
445 REGULATOR_SUPPLY("vio", "1-004b"),
446};
447
448static struct regulator_init_data omap4_v1v8_idata = {
449 .constraints = {
450 .min_uV = 1800000,
451 .max_uV = 1800000,
452 .valid_modes_mask = REGULATOR_MODE_NORMAL
453 | REGULATOR_MODE_STANDBY,
454 .valid_ops_mask = REGULATOR_CHANGE_MODE
455 | REGULATOR_CHANGE_STATUS,
456 .always_on = true,
457 },
458 .num_consumer_supplies = ARRAY_SIZE(omap4_v1v8_supply),
459 .consumer_supplies = omap4_v1v8_supply,
460};
461
462static struct regulator_consumer_supply omap4_v2v1_supply[] = {
463 REGULATOR_SUPPLY("v2v1", "1-004b"),
464};
465
466static struct regulator_init_data omap4_v2v1_idata = {
467 .constraints = {
468 .min_uV = 2100000,
469 .max_uV = 2100000,
470 .valid_modes_mask = REGULATOR_MODE_NORMAL
471 | REGULATOR_MODE_STANDBY,
472 .valid_ops_mask = REGULATOR_CHANGE_MODE
473 | REGULATOR_CHANGE_STATUS,
474 },
475 .num_consumer_supplies = ARRAY_SIZE(omap4_v2v1_supply),
476 .consumer_supplies = omap4_v2v1_supply,
477};
478
313void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, 479void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
314 u32 pdata_flags, u32 regulators_flags) 480 u32 pdata_flags, u32 regulators_flags)
315{ 481{
@@ -318,6 +484,24 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
318 if (!pmic_data->irq_end) 484 if (!pmic_data->irq_end)
319 pmic_data->irq_end = TWL6030_IRQ_END; 485 pmic_data->irq_end = TWL6030_IRQ_END;
320 486
487 if (!pmic_data->vdd1) {
488 omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
489 omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
490 pmic_data->vdd1 = &omap4_vdd1;
491 }
492
493 if (!pmic_data->vdd2) {
494 omap4_vdd2.driver_data = &omap4_vdd2_drvdata;
495 omap4_vdd2_drvdata.data = voltdm_lookup("iva");
496 pmic_data->vdd2 = &omap4_vdd2;
497 }
498
499 if (!pmic_data->vdd3) {
500 omap4_vdd3.driver_data = &omap4_vdd3_drvdata;
501 omap4_vdd3_drvdata.data = voltdm_lookup("core");
502 pmic_data->vdd3 = &omap4_vdd3;
503 }
504
321 /* Common platform data configurations */ 505 /* Common platform data configurations */
322 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb) 506 if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
323 pmic_data->usb = &omap4_usb_pdata; 507 pmic_data->usb = &omap4_usb_pdata;
@@ -350,5 +534,11 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
350 if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG && 534 if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
351 !pmic_data->clk32kg) 535 !pmic_data->clk32kg)
352 pmic_data->clk32kg = &omap4_clk32kg_idata; 536 pmic_data->clk32kg = &omap4_clk32kg_idata;
537
538 if (regulators_flags & TWL_COMMON_REGULATOR_V1V8 && !pmic_data->v1v8)
539 pmic_data->v1v8 = &omap4_v1v8_idata;
540
541 if (regulators_flags & TWL_COMMON_REGULATOR_V2V1 && !pmic_data->v2v1)
542 pmic_data->v2v1 = &omap4_v2v1_idata;
353} 543}
354#endif /* CONFIG_ARCH_OMAP4 */ 544#endif /* CONFIG_ARCH_OMAP4 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 09627483a57f..8fe71cfd002c 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -22,6 +22,8 @@
22#define TWL_COMMON_REGULATOR_VCXIO (1 << 8) 22#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
23#define TWL_COMMON_REGULATOR_VUSB (1 << 9) 23#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
24#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10) 24#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
25#define TWL_COMMON_REGULATOR_V1V8 (1 << 11)
26#define TWL_COMMON_REGULATOR_V2V1 (1 << 12)
25 27
26/* TWL4030 LDO regulators */ 28/* TWL4030 LDO regulators */
27#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4) 29#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 994d8f591a1d..db84a46ce7fd 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
126 tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps; 126 tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
127 if (tmp > 4) 127 if (tmp > 4)
128 return -ERANGE; 128 return -ERANGE;
129 if (tmp <= 0) 129 if (tmp == 0)
130 tmp = 1; 130 tmp = 1;
131 t.page_burst_access = (fclk_ps * tmp) / 1000; 131 t.page_burst_access = (fclk_ps * tmp) / 1000;
132 132
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index a5ec7f8f2ea8..5d8eaf31569c 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -46,6 +46,7 @@ static struct omap_vc_common omap3_vc_common = {
46}; 46};
47 47
48struct omap_vc_channel omap3_vc_mpu = { 48struct omap_vc_channel omap3_vc_mpu = {
49 .flags = OMAP_VC_CHANNEL_DEFAULT,
49 .common = &omap3_vc_common, 50 .common = &omap3_vc_common,
50 .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET, 51 .smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET,
51 .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET, 52 .smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 8a36342e60d2..4dc60e83e00d 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -73,7 +73,8 @@ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
73int voltdm_scale(struct voltagedomain *voltdm, 73int voltdm_scale(struct voltagedomain *voltdm,
74 unsigned long target_volt) 74 unsigned long target_volt)
75{ 75{
76 int ret; 76 int ret, i;
77 unsigned long volt = 0;
77 78
78 if (!voltdm || IS_ERR(voltdm)) { 79 if (!voltdm || IS_ERR(voltdm)) {
79 pr_warning("%s: VDD specified does not exist!\n", __func__); 80 pr_warning("%s: VDD specified does not exist!\n", __func__);
@@ -86,9 +87,23 @@ int voltdm_scale(struct voltagedomain *voltdm,
86 return -ENODATA; 87 return -ENODATA;
87 } 88 }
88 89
89 ret = voltdm->scale(voltdm, target_volt); 90 /* Adjust voltage to the exact voltage from the OPP table */
91 for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
92 if (voltdm->volt_data[i].volt_nominal >= target_volt) {
93 volt = voltdm->volt_data[i].volt_nominal;
94 break;
95 }
96 }
97
98 if (!volt) {
99 pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n",
100 __func__, target_volt);
101 return -EINVAL;
102 }
103
104 ret = voltdm->scale(voltdm, volt);
90 if (!ret) 105 if (!ret)
91 voltdm->nominal_volt = target_volt; 106 voltdm->nominal_volt = volt;
92 107
93 return ret; 108 return ret;
94} 109}
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 4067669d96c4..b2f1c67043a2 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -14,6 +14,7 @@
14#include <plat/omap_hwmod.h> 14#include <plat/omap_hwmod.h>
15 15
16#include "wd_timer.h" 16#include "wd_timer.h"
17#include "common.h"
17 18
18/* 19/*
19 * In order to avoid any assumptions from bootloader regarding WDT 20 * In order to avoid any assumptions from bootloader regarding WDT
@@ -25,6 +26,8 @@
25#define OMAP_WDT_WPS 0x34 26#define OMAP_WDT_WPS 0x34
26#define OMAP_WDT_SPR 0x48 27#define OMAP_WDT_SPR 0x48
27 28
29/* Maximum microseconds to wait for OMAP module to softreset */
30#define MAX_MODULE_SOFTRESET_WAIT 10000
28 31
29int omap2_wd_timer_disable(struct omap_hwmod *oh) 32int omap2_wd_timer_disable(struct omap_hwmod *oh)
30{ 33{
@@ -54,3 +57,45 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
54 return 0; 57 return 0;
55} 58}
56 59
60/**
61 * omap2_wdtimer_reset - reset and disable the WDTIMER IP block
62 * @oh: struct omap_hwmod *
63 *
64 * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
65 * care to execute the special watchdog disable sequence. This is
66 * because the watchdog is re-armed upon OCP softreset. (On OMAP4,
67 * this behavior was apparently changed and the watchdog is no longer
68 * re-armed after an OCP soft-reset.) Returns -ETIMEDOUT if the reset
69 * did not complete, or 0 upon success.
70 *
71 * XXX Most of this code should be moved to the omap_hwmod.c layer
72 * during a normal merge window. omap_hwmod_softreset() should be
73 * renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
74 * should call the hwmod _ocp_softreset() code.
75 */
76int omap2_wd_timer_reset(struct omap_hwmod *oh)
77{
78 int c = 0;
79
80 /* Write to the SOFTRESET bit */
81 omap_hwmod_softreset(oh);
82
83 /* Poll on RESETDONE bit */
84 omap_test_timeout((omap_hwmod_read(oh,
85 oh->class->sysc->syss_offs)
86 & SYSS_RESETDONE_MASK),
87 MAX_MODULE_SOFTRESET_WAIT, c);
88
89 if (oh->class->sysc->srst_udelay)
90 udelay(oh->class->sysc->srst_udelay);
91
92 if (c == MAX_MODULE_SOFTRESET_WAIT)
93 pr_warning("%s: %s: softreset failed (waited %d usec)\n",
94 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
95 else
96 pr_debug("%s: %s: softreset in %d usec\n", __func__,
97 oh->name, c);
98
99 return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
100 omap2_wd_timer_disable(oh);
101}
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h
index e0054a2d5505..f6bbba73b535 100644
--- a/arch/arm/mach-omap2/wd_timer.h
+++ b/arch/arm/mach-omap2/wd_timer.h
@@ -13,5 +13,6 @@
13#include <plat/omap_hwmod.h> 13#include <plat/omap_hwmod.h>
14 14
15extern int omap2_wd_timer_disable(struct omap_hwmod *oh); 15extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
16extern int omap2_wd_timer_reset(struct omap_hwmod *oh);
16 17
17#endif 18#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 03:21:23 -0500