17 files changed, 150 insertions, 93 deletions

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dd0fbf76ac79..fcd4e85c4ddc 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -62,12 +62,14 @@ config ARCH_OMAP4
         select PM_OPP if PM
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARM_CPU_SUSPEND if PM
+        select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
 
 config SOC_OMAP5
         bool "TI OMAP5"
         select CPU_V7
         select ARM_GIC
         select HAVE_SMP
+        select ARM_CPU_SUSPEND if PM
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 74915295482e..28214483aaba 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -554,6 +554,8 @@ static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
+        OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #endif
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 2c5d0ed75285..677357ff61ac 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -468,7 +468,6 @@ static struct omap_mmc_platform_data mmc1_data = {
         .cleanup                        = n8x0_mmc_cleanup,
         .shutdown                       = n8x0_mmc_shutdown,
         .max_freq                       = 24000000,
-        .dma_mask                       = 0xffffffff,
         .slots[0] = {
                 .wires                  = 4,
                 .set_power              = n8x0_mmc_set_power,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ef230a0eb5eb..0d362e9f9cb9 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -58,6 +58,7 @@
 #include "hsmmc.h"
 #include "common-board-devices.h"
 
+#define OMAP3_EVM_TS_GPIO       175
 #define OMAP3_EVM_EHCI_VBUS     22
 #define OMAP3_EVM_EHCI_SELECT   61
 
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 91b3d5c60bfe..83bed9ad3017 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3376,15 +3376,15 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 14734746457c..c1875862679f 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .turbo_mode     = 0,
 };
 
-/*
- * ADS7846 driver maybe request a gpio according to the value
- * of pdata->get_pendown_state, but we have done this. So set
- * get_pendown_state to avoid twice gpio requesting.
- */
-static int omap3_get_pendown_state(void)
-{
-        return !gpio_get_value(OMAP3_EVM_TS_GPIO);
-}
-
 static struct ads7846_platform_data ads7846_config = {
         .x_max                  = 0x0fff,
         .y_max                  = 0x0fff,
@@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
         .debounce_rep           = 1,
         .gpio_pendown           = -EINVAL,
         .keep_vref_on           = 1,
-        .get_pendown_state      = &omap3_get_pendown_state,
 };
 
 static struct spi_board_info ads7846_spi_board_info __initdata = {
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 4c4ef6a6166b..a0b4a42836ab 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -4,7 +4,6 @@
 #include "twl-common.h"
 
 #define NAND_BLOCK_SIZE SZ_128K
-#define OMAP3_EVM_TS_GPIO       175
 
 struct mtd_partition;
 struct ads7846_platform_data;
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 02d15bbd4e35..288bee6cbb76 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -21,6 +21,7 @@
 #include "common.h"
 #include "pm.h"
 #include "prm.h"
+#include "clockdomain.h"
 
 /* Machine specific information */
 struct omap4_idle_statedata {
@@ -47,10 +48,14 @@ static struct omap4_idle_statedata omap4_idle_data[] = {
         },
 };
 
-static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
+static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
+static struct clockdomain *cpu_clkdm[NR_CPUS];
+
+static atomic_t abort_barrier;
+static bool cpu_done[NR_CPUS];
 
 /**
- * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
  * @dev: cpuidle device
  * @drv: cpuidle driver
  * @index: the index of state to be entered
@@ -59,60 +64,84 @@ static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
  * specified low power state selected by the governor.
  * Returns the amount of time spent in the low power state.
  */
-static int omap4_enter_idle(struct cpuidle_device *dev,
+static int omap4_enter_idle_simple(struct cpuidle_device *dev,
+                        struct cpuidle_driver *drv,
+                        int index)
+{
+        local_fiq_disable();
+        omap_do_wfi();
+        local_fiq_enable();
+
+        return index;
+}
+
+static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                         int index)
 {
         struct omap4_idle_statedata *cx = &omap4_idle_data[index];
-        u32 cpu1_state;
         int cpu_id = smp_processor_id();
 
         local_fiq_disable();
 
         /*
-         * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
+         * CPU0 has to wait and stay ON until CPU1 is OFF state.
          * This is necessary to honour hardware recommondation
          * of triggeing all the possible low power modes once CPU1 is
          * out of coherency and in OFF mode.
-         * Update dev->last_state so that governor stats reflects right
-         * data.
          */
-        cpu1_state = pwrdm_read_pwrst(cpu1_pd);
-        if (cpu1_state != PWRDM_POWER_OFF) {
-                index = drv->safe_state_index;
-                cx = &omap4_idle_data[index];
+        if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
+                while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
+                        cpu_relax();
+
+                        /*
+                         * CPU1 could have already entered & exited idle
+                         * without hitting off because of a wakeup
+                         * or a failed attempt to hit off mode.  Check for
+                         * that here, otherwise we could spin forever
+                         * waiting for CPU1 off.
+                         */
+                        if (cpu_done[1])
+                            goto fail;
+
+                }
         }
 
-        if (index > 0)
-                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
 
         /*
          * Call idle CPU PM enter notifier chain so that
          * VFP and per CPU interrupt context is saved.
          */
-        if (cx->cpu_state == PWRDM_POWER_OFF)
-                cpu_pm_enter();
-
-        pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
-        omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
-
-        /*
-         * Call idle CPU cluster PM enter notifier chain
-         * to save GIC and wakeupgen context.
-         */
-        if ((cx->mpu_state == PWRDM_POWER_RET) &&
-                (cx->mpu_logic_state == PWRDM_POWER_OFF))
-                        cpu_cluster_pm_enter();
+        cpu_pm_enter();
+
+        if (dev->cpu == 0) {
+                pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+                omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+
+                /*
+                 * Call idle CPU cluster PM enter notifier chain
+                 * to save GIC and wakeupgen context.
+                 */
+                if ((cx->mpu_state == PWRDM_POWER_RET) &&
+                        (cx->mpu_logic_state == PWRDM_POWER_OFF))
+                                cpu_cluster_pm_enter();
+        }
 
         omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+        cpu_done[dev->cpu] = true;
+
+        /* Wakeup CPU1 only if it is not offlined */
+        if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
+                clkdm_wakeup(cpu_clkdm[1]);
+                clkdm_allow_idle(cpu_clkdm[1]);
+        }
 
         /*
          * Call idle CPU PM exit notifier chain to restore
-         * VFP and per CPU IRQ context. Only CPU0 state is
-         * considered since CPU1 is managed by CPU hotplug.
+         * VFP and per CPU IRQ context.
          */
-        if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
-                cpu_pm_exit();
+        cpu_pm_exit();
 
         /*
          * Call idle CPU cluster PM exit notifier chain
@@ -121,8 +150,11 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
         if (omap4_mpuss_read_prev_context_state())
                 cpu_cluster_pm_exit();
 
-        if (index > 0)
-                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+
+fail:
+        cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+        cpu_done[dev->cpu] = false;
 
         local_fiq_enable();
 
@@ -141,7 +173,7 @@ struct cpuidle_driver omap4_idle_driver = {
                         .exit_latency = 2 + 2,
                         .target_residency = 5,
                         .flags = CPUIDLE_FLAG_TIME_VALID,
-                        .enter = omap4_enter_idle,
+                        .enter = omap4_enter_idle_simple,
                         .name = "C1",
                         .desc = "MPUSS ON"
                 },
@@ -149,8 +181,8 @@ struct cpuidle_driver omap4_idle_driver = {
                         /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
                         .exit_latency = 328 + 440,
                         .target_residency = 960,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
-                        .enter = omap4_enter_idle,
+                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
+                        .enter = omap4_enter_idle_coupled,
                         .name = "C2",
                         .desc = "MPUSS CSWR",
                 },
@@ -158,8 +190,8 @@ struct cpuidle_driver omap4_idle_driver = {
                         /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
                         .exit_latency = 460 + 518,
                         .target_residency = 1100,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
-                        .enter = omap4_enter_idle,
+                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
+                        .enter = omap4_enter_idle_coupled,
                         .name = "C3",
                         .desc = "MPUSS OSWR",
                 },
@@ -168,6 +200,16 @@ struct cpuidle_driver omap4_idle_driver = {
         .safe_state_index = 0,
 };
 
+/*
+ * For each cpu, setup the broadcast timer because local timers
+ * stops for the states above C1.
+ */
+static void omap_setup_broadcast_timer(void *arg)
+{
+        int cpu = smp_processor_id();
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
+}
+
 /**
  * omap4_idle_init - Init routine for OMAP4 idle
  *
@@ -180,19 +222,31 @@ int __init omap4_idle_init(void)
         unsigned int cpu_id = 0;
 
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
-        cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
-        cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
-        if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
+        cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
+        cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
+        if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
                 return -ENODEV;
 
-        dev = &per_cpu(omap4_idle_dev, cpu_id);
-        dev->cpu = cpu_id;
-
-        cpuidle_register_driver(&omap4_idle_driver);
+        cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
+        cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
+        if (!cpu_clkdm[0] || !cpu_clkdm[1])
+                return -ENODEV;
 
-        if (cpuidle_register_device(dev)) {
-                pr_err("%s: CPUidle register device failed\n", __func__);
-                return -EIO;
+        /* Configure the broadcast timer on each cpu */
+        on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
+
+        for_each_cpu(cpu_id, cpu_online_mask) {
+                dev = &per_cpu(omap4_idle_dev, cpu_id);
+                dev->cpu = cpu_id;
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+                dev->coupled_cpus = *cpu_online_mask;
+#endif
+                cpuidle_register_driver(&omap4_idle_driver);
+
+                if (cpuidle_register_device(dev)) {
+                        pr_err("%s: CPUidle register failed\n", __func__);
+                        return -EIO;
+                }
         }
 
         return 0;
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 5fb47a14f4ba..af1ed7d24a1f 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -37,6 +37,7 @@
 
 #define DISPC_CONTROL           0x0040
 #define DISPC_CONTROL2          0x0238
+#define DISPC_CONTROL3          0x0848
 #define DISPC_IRQSTATUS         0x0018
 
 #define DSS_SYSCONFIG           0x10
@@ -52,6 +53,7 @@
 #define EVSYNC_EVEN_IRQ_SHIFT   2
 #define EVSYNC_ODD_IRQ_SHIFT    3
 #define FRAMEDONE2_IRQ_SHIFT    22
+#define FRAMEDONE3_IRQ_SHIFT    30
 #define FRAMEDONETV_IRQ_SHIFT   24
 
 /*
@@ -376,7 +378,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
 static void dispc_disable_outputs(void)
 {
         u32 v, irq_mask = 0;
-        bool lcd_en, digit_en, lcd2_en = false;
+        bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
         int i;
         struct omap_dss_dispc_dev_attr *da;
         struct omap_hwmod *oh;
@@ -405,7 +407,13 @@ static void dispc_disable_outputs(void)
                 lcd2_en = v & LCD_EN_MASK;
         }
 
-        if (!(lcd_en | digit_en | lcd2_en))
+        /* store value of LCDENABLE for LCD3 */
+        if (da->manager_count > 3) {
+                v = omap_hwmod_read(oh, DISPC_CONTROL3);
+                lcd3_en = v & LCD_EN_MASK;
+        }
+
+        if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
                 return; /* no managers currently enabled */
 
         /*
@@ -426,10 +434,12 @@ static void dispc_disable_outputs(void)
 
         if (lcd2_en)
                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
+        if (lcd3_en)
+                irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
 
         /*
          * clear any previous FRAMEDONE, FRAMEDONETV,
-         * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
+         * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
          */
         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
 
@@ -445,12 +455,19 @@ static void dispc_disable_outputs(void)
                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
         }
 
+        /* disable LCD3 manager */
+        if (da->manager_count > 3) {
+                v = omap_hwmod_read(oh, DISPC_CONTROL3);
+                v &= ~LCD_EN_MASK;
+                omap_hwmod_write(v, oh, DISPC_CONTROL3);
+        }
+
         i = 0;
         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
                irq_mask) {
                 i++;
                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
-                        pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
+                        pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
                         break;
                 }
                 mdelay(1);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index be697d4e0843..a9675d8d1822 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -315,7 +315,6 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
         mmc->slots[0].caps = c->caps;
         mmc->slots[0].pm_caps = c->pm_caps;
         mmc->slots[0].internal_clock = !c->ext_clock;
-        mmc->dma_mask = 0xffffffff;
         mmc->max_freq = c->max_freq;
         if (cpu_is_omap44xx())
                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 471e62a74a16..76f9b3c2f586 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -127,7 +127,6 @@ struct omap_mux_partition {
  * @gpio:       GPIO number
  * @muxnames:   available signal modes for a ball
  * @balls:      available balls on the package
- * @partition:  mux partition
  */
 struct omap_mux {
         u16     reg_offset;
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 7d118b9bdd5f..9a35adf91232 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -125,7 +125,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
                 booted = true;
         }
 
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
 
         /*
          * Now the secondary core is starting up let it run its
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 2293ba27101b..c95415da23c2 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -94,7 +94,7 @@ int __init omap4_opp_init(void)
 {
         int r = -ENODEV;
 
-        if (!cpu_is_omap44xx())
+        if (!cpu_is_omap443x())
                 return r;
 
         r = omap_init_opp_table(omap44xx_opp_def_list,
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e4fc88c65dbd..05bd8f02723f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -272,21 +272,16 @@ void omap_sram_idle(void)
         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 
-        if (mpu_next_state < PWRDM_POWER_ON) {
-                pwrdm_pre_transition(mpu_pwrdm);
-                pwrdm_pre_transition(neon_pwrdm);
-        }
+        pwrdm_pre_transition(NULL);
 
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
-                pwrdm_pre_transition(per_pwrdm);
                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
                 omap2_gpio_prepare_for_idle(per_going_off);
         }
 
         /* CORE */
         if (core_next_state < PWRDM_POWER_ON) {
-                pwrdm_pre_transition(core_pwrdm);
                 if (core_next_state == PWRDM_POWER_OFF) {
                         omap3_core_save_context();
                         omap3_cm_save_context();
@@ -339,20 +334,14 @@ void omap_sram_idle(void)
                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                                OMAP3430_GR_MOD,
                                                OMAP3_PRM_VOLTCTRL_OFFSET);
-                pwrdm_post_transition(core_pwrdm);
         }
         omap3_intc_resume_idle();
 
+        pwrdm_post_transition(NULL);
+
         /* PER */
-        if (per_next_state < PWRDM_POWER_ON) {
+        if (per_next_state < PWRDM_POWER_ON)
                 omap2_gpio_resume_after_idle();
-                pwrdm_post_transition(per_pwrdm);
-        }
-
-        if (mpu_next_state < PWRDM_POWER_ON) {
-                pwrdm_post_transition(mpu_pwrdm);
-                pwrdm_post_transition(neon_pwrdm);
-        }
 }
 
 static void omap3_pm_idle(void)
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 9f6b83d1b193..91e71d8f46f0 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -56,9 +56,13 @@ ppa_por_params:
  * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
  * It returns to the caller for CPU INACTIVE and ON power states or in case
  * CPU failed to transition to targeted OFF/DORMANT state.
+ *
+ * omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
+ * stack frame and it expects the caller to take care of it. Hence the entire
+ * stack frame is saved to avoid possible stack corruption.
  */
 ENTRY(omap4_finish_suspend)
-        stmfd   sp!, {lr}
+        stmfd   sp!, {r4-r12, lr}
         cmp     r0, #0x0
         beq     do_WFI                          @ No lowpower state, jump to WFI
 
@@ -226,7 +230,7 @@ scu_gp_clear:
 skip_scu_gp_clear:
         isb
         dsb
-        ldmfd   sp!, {pc}
+        ldmfd   sp!, {r4-r12, pc}
 ENDPROC(omap4_finish_suspend)
 
 /*
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 13d20c8a283d..2ff6d41ec6c6 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -130,6 +130,7 @@ static struct clock_event_device clockevent_gpt = {
         .name           = "gp_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .shift          = 32,
+        .rating         = 300,
         .set_next_event = omap2_gp_timer_set_next_event,
         .set_mode       = omap2_gp_timer_set_mode,
 };
@@ -223,7 +224,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
                 clockevent_delta2ns(3, &clockevent_gpt);
                 /* Timer internal resynch latency. */
 
-        clockevent_gpt.cpumask = cpumask_of(0);
+        clockevent_gpt.cpumask = cpu_possible_mask;
+        clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
         clockevents_register_device(&clockevent_gpt);
 
         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index de47f170ba50..db5ff6642375 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -67,6 +67,7 @@ void __init omap_pmic_init(int bus, u32 clkrate,
                            const char *pmic_type, int pmic_irq,
                            struct twl4030_platform_data *pmic_data)
 {
+        omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
         strncpy(pmic_i2c_board_info.type, pmic_type,
                 sizeof(pmic_i2c_board_info.type));
         pmic_i2c_board_info.irq = pmic_irq;