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-rw-r--r--arch/arm/mach-omap2/Kconfig8
-rw-r--r--arch/arm/mach-omap2/Makefile12
-rw-r--r--arch/arm/mach-omap2/am33xx.h1
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c30
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c11
-rw-r--r--arch/arm/mach-omap2/clock36xx.c18
-rw-r--r--arch/arm/mach-omap2/clockdomain.h1
-rw-r--r--arch/arm/mach-omap2/clockdomains54xx_data.c464
-rw-r--r--arch/arm/mach-omap2/cm-regbits-54xx.h1737
-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h7
-rw-r--r--arch/arm/mach-omap2/cm1_54xx.h213
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h7
-rw-r--r--arch/arm/mach-omap2/cm2_54xx.h389
-rw-r--r--arch/arm/mach-omap2/cm33xx.h2
-rw-r--r--arch/arm/mach-omap2/cm_44xx_54xx.h36
-rw-r--r--arch/arm/mach-omap2/common.h5
-rw-r--r--arch/arm/mach-omap2/control.h8
-rw-r--r--arch/arm/mach-omap2/id.c8
-rw-r--r--arch/arm/mach-omap2/io.c23
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S8
-rw-r--r--arch/arm/mach-omap2/omap-mpuss-lowpower.c69
-rw-r--r--arch/arm/mach-omap2/omap-smp.c6
-rw-r--r--arch/arm/mach-omap2/omap4-common.c16
-rw-r--r--arch/arm/mach-omap2/omap4-restart.c27
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c12
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c2150
-rw-r--r--arch/arm/mach-omap2/pm34xx.c6
-rw-r--r--arch/arm/mach-omap2/pm44xx.c58
-rw-r--r--arch/arm/mach-omap2/powerdomain.h1
-rw-r--r--arch/arm/mach-omap2/powerdomains54xx_data.c331
-rw-r--r--arch/arm/mach-omap2/prcm44xx.h6
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h14
-rw-r--r--arch/arm/mach-omap2/prcm_mpu54xx.h87
-rw-r--r--arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h36
-rw-r--r--arch/arm/mach-omap2/prm-regbits-54xx.h2701
-rw-r--r--arch/arm/mach-omap2/prm44xx.h33
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h58
-rw-r--r--arch/arm/mach-omap2/prm54xx.h421
-rw-r--r--arch/arm/mach-omap2/scrm54xx.h231
-rw-r--r--arch/arm/mach-omap2/soc.h23
-rw-r--r--arch/arm/mach-omap2/sram.c3
-rw-r--r--arch/arm/mach-omap2/voltage.h1
-rw-r--r--arch/arm/mach-omap2/voltagedomains54xx_data.c102
44 files changed, 9250 insertions, 131 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51e162a..1bfe9ee0331b 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -149,6 +149,14 @@ config SOC_AM33XX
149 select MULTI_IRQ_HANDLER 149 select MULTI_IRQ_HANDLER
150 select COMMON_CLK 150 select COMMON_CLK
151 151
152config SOC_AM43XX
153 bool "TI AM43x"
154 select CPU_V7
155 select MULTI_IRQ_HANDLER
156 select ARM_GIC
157 select COMMON_CLK
158 select MACH_OMAP_GENERIC
159
152config OMAP_PACKAGE_ZAF 160config OMAP_PACKAGE_ZAF
153 bool 161 bool
154 162
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d6777683..f8bc62fd48fb 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
22obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 22obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) 24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
25 26
26ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 27ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
27obj-y += mcbsp.o 28obj-y += mcbsp.o
@@ -38,6 +39,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o \
38 sleep44xx.o 39 sleep44xx.o
39obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) 40obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y)
40obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) 41obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y)
42obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
41 43
42plus_sec := $(call as-instr,.arch_extension sec,+sec) 44plus_sec := $(call as-instr,.arch_extension sec,+sec)
43AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) 45AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,6 +60,8 @@ obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
58obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o 60obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
59obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o 61obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
60obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o 62obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
63obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
64obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
61 65
62# Pin multiplexing 66# Pin multiplexing
63obj-$(CONFIG_SOC_OMAP2420) += mux2420.o 67obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
@@ -110,6 +114,7 @@ obj-$(CONFIG_ARCH_OMAP2) += prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
110obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o 114obj-$(CONFIG_ARCH_OMAP3) += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
111obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o 115obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
112obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o 116obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
117obj-$(CONFIG_SOC_AM43XX) += prm33xx.o cm33xx.o
113omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ 118omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
114 prcm_mpu44xx.o prminst44xx.o \ 119 prcm_mpu44xx.o prminst44xx.o \
115 vc44xx_data.o vp44xx_data.o 120 vc44xx_data.o vp44xx_data.o
@@ -126,7 +131,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
126obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o 131obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
127obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) 132obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
128obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o 133obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
134obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common)
129obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) 135obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
136obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
130 137
131# OMAP powerdomain framework 138# OMAP powerdomain framework
132powerdomain-common += powerdomain.o powerdomain-common.o 139powerdomain-common += powerdomain.o powerdomain-common.o
@@ -140,7 +147,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
140obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o 147obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
141obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) 148obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
142obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o 149obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
150obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
143obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) 151obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
152obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
144 153
145# PRCM clockdomain control 154# PRCM clockdomain control
146clockdomain-common += clockdomain.o 155clockdomain-common += clockdomain.o
@@ -155,7 +164,9 @@ obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
155obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o 164obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
156obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) 165obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
157obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o 166obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
167obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
158obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) 168obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
169obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
159 170
160# Clock framework 171# Clock framework
161obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 172obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -198,6 +209,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
198obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o 209obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
199obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o 210obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
200obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 211obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
212obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
201 213
202# EMU peripherals 214# EMU peripherals
203obj-$(CONFIG_OMAP3_EMU) += emu.o 215obj-$(CONFIG_OMAP3_EMU) += emu.o
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 43296c1af9ee..5eef093e6738 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -21,6 +21,7 @@
21#define AM33XX_SCM_BASE 0x44E10000 21#define AM33XX_SCM_BASE 0x44E10000
22#define AM33XX_CTRL_BASE AM33XX_SCM_BASE 22#define AM33XX_CTRL_BASE AM33XX_SCM_BASE
23#define AM33XX_PRCM_BASE 0x44E00000 23#define AM33XX_PRCM_BASE 0x44E00000
24#define AM43XX_PRCM_BASE 0x44DF0000
24#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC) 25#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC)
25 26
26#endif /* __ASM_ARCH_AM33XX_H */ 27#endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index af3544ce4f02..0346de56436c 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -862,6 +862,33 @@ static struct clk_hw_omap wdt1_fck_hw = {
862 862
863DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops); 863DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
864 864
865static const char *pwmss_clk_parents[] = {
866 "dpll_per_m2_ck",
867};
868
869static const struct clk_ops ehrpwm_tbclk_ops = {
870 .enable = &omap2_dflt_clk_enable,
871 .disable = &omap2_dflt_clk_disable,
872};
873
874DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
875 NULL, NULL, 0,
876 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
877 AM33XX_PWMSS0_TBCLKEN_SHIFT,
878 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
879
880DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
881 NULL, NULL, 0,
882 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
883 AM33XX_PWMSS1_TBCLKEN_SHIFT,
884 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
885
886DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
887 NULL, NULL, 0,
888 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
889 AM33XX_PWMSS2_TBCLKEN_SHIFT,
890 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
891
865/* 892/*
866 * clkdev 893 * clkdev
867 */ 894 */
@@ -942,6 +969,9 @@ static struct omap_clk am33xx_clks[] = {
942 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), 969 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
943 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), 970 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
944 CLK(NULL, "timer_sys_ck", &sys_clkin_ck), 971 CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
972 CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
973 CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
974 CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
945}; 975};
946 976
947 977
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 45cd26430d1f..334b76745900 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3329,11 +3329,7 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3329 CLK(NULL, "cpefuse_fck", &cpefuse_fck), 3329 CLK(NULL, "cpefuse_fck", &cpefuse_fck),
3330 CLK(NULL, "ts_fck", &ts_fck), 3330 CLK(NULL, "ts_fck", &ts_fck),
3331 CLK(NULL, "usbtll_fck", &usbtll_fck), 3331 CLK(NULL, "usbtll_fck", &usbtll_fck),
3332 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck),
3333 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck),
3334 CLK(NULL, "usbtll_ick", &usbtll_ick), 3332 CLK(NULL, "usbtll_ick", &usbtll_ick),
3335 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick),
3336 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick),
3337 CLK("omap_hsmmc.2", "ick", &mmchs3_ick), 3333 CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
3338 CLK(NULL, "mmchs3_ick", &mmchs3_ick), 3334 CLK(NULL, "mmchs3_ick", &mmchs3_ick),
3339 CLK(NULL, "mmchs3_fck", &mmchs3_fck), 3335 CLK(NULL, "mmchs3_fck", &mmchs3_fck),
@@ -3343,7 +3339,6 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
3343 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck), 3339 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
3344 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck), 3340 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
3345 CLK(NULL, "usbhost_ick", &usbhost_ick), 3341 CLK(NULL, "usbhost_ick", &usbhost_ick),
3346 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick),
3347}; 3342};
3348 3343
3349/* 3344/*
@@ -3463,12 +3458,6 @@ static struct omap_clk omap3xxx_clks[] = {
3463 CLK(NULL, "utmi_p2_gfclk", &dummy_ck), 3458 CLK(NULL, "utmi_p2_gfclk", &dummy_ck),
3464 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck), 3459 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck),
3465 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck), 3460 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck),
3466 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck),
3467 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck),
3468 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3469 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3470 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
3471 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
3472 CLK(NULL, "init_60m_fclk", &dummy_ck), 3461 CLK(NULL, "init_60m_fclk", &dummy_ck),
3473 CLK(NULL, "gpt1_fck", &gpt1_fck), 3462 CLK(NULL, "gpt1_fck", &gpt1_fck),
3474 CLK(NULL, "aes2_ick", &aes2_ick), 3463 CLK(NULL, "aes2_ick", &aes2_ick),
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index 8f3bf4e50908..bbd6a3f717e6 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -20,11 +20,12 @@
20 20
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/clk-provider.h>
23#include <linux/io.h> 24#include <linux/io.h>
24 25
25#include "clock.h" 26#include "clock.h"
26#include "clock36xx.h" 27#include "clock36xx.h"
27 28#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
28 29
29/** 30/**
30 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering 31 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@
39 */ 40 */
40int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) 41int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
41{ 42{
42 struct clk_hw_omap *parent; 43 struct clk_divider *parent;
43 struct clk_hw *parent_hw; 44 struct clk_hw *parent_hw;
44 u32 dummy_v, orig_v, clksel_shift; 45 u32 dummy_v, orig_v;
45 int ret; 46 int ret;
46 47
47 /* Clear PWRDN bit of HSDIVIDER */ 48 /* Clear PWRDN bit of HSDIVIDER */
48 ret = omap2_dflt_clk_enable(clk); 49 ret = omap2_dflt_clk_enable(clk);
49 50
50 parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); 51 parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
51 parent = to_clk_hw_omap(parent_hw); 52 parent = to_clk_divider(parent_hw);
52 53
53 /* Restore the dividers */ 54 /* Restore the dividers */
54 if (!ret) { 55 if (!ret) {
55 clksel_shift = __ffs(parent->clksel_mask); 56 orig_v = __raw_readl(parent->reg);
56 orig_v = __raw_readl(parent->clksel_reg);
57 dummy_v = orig_v; 57 dummy_v = orig_v;
58 58
59 /* Write any other value different from the Read value */ 59 /* Write any other value different from the Read value */
60 dummy_v ^= (1 << clksel_shift); 60 dummy_v ^= (1 << parent->shift);
61 __raw_writel(dummy_v, parent->clksel_reg); 61 __raw_writel(dummy_v, parent->reg);
62 62
63 /* Write the original divider */ 63 /* Write the original divider */
64 __raw_writel(orig_v, parent->clksel_reg); 64 __raw_writel(orig_v, parent->reg);
65 } 65 }
66 66
67 return ret; 67 return ret;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2da37656a693..daeecf1b89fa 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
216extern void __init omap3xxx_clockdomains_init(void); 216extern void __init omap3xxx_clockdomains_init(void);
217extern void __init am33xx_clockdomains_init(void); 217extern void __init am33xx_clockdomains_init(void);
218extern void __init omap44xx_clockdomains_init(void); 218extern void __init omap44xx_clockdomains_init(void);
219extern void __init omap54xx_clockdomains_init(void);
219 220
220extern void clkdm_add_autodeps(struct clockdomain *clkdm); 221extern void clkdm_add_autodeps(struct clockdomain *clkdm);
221extern void clkdm_del_autodeps(struct clockdomain *clkdm); 222extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
new file mode 100644
index 000000000000..1a3c69d2e14c
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -0,0 +1,464 @@
1/*
2 * OMAP54XX Clock domains framework
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Abhijit Pagare (abhijitpagare@ti.com)
7 * Benoit Cousson (b-cousson@ti.com)
8 * Paul Walmsley (paul@pwsan.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/kernel.h>
22#include <linux/io.h>
23
24#include "clockdomain.h"
25#include "cm1_54xx.h"
26#include "cm2_54xx.h"
27
28#include "cm-regbits-54xx.h"
29#include "prm54xx.h"
30#include "prcm44xx.h"
31#include "prcm_mpu54xx.h"
32
33/* Static Dependencies for OMAP4 Clock Domains */
34
35static struct clkdm_dep c2c_wkup_sleep_deps[] = {
36 { .clkdm_name = "abe_clkdm" },
37 { .clkdm_name = "emif_clkdm" },
38 { .clkdm_name = "iva_clkdm" },
39 { .clkdm_name = "l3init_clkdm" },
40 { .clkdm_name = "l3main1_clkdm" },
41 { .clkdm_name = "l3main2_clkdm" },
42 { .clkdm_name = "l4cfg_clkdm" },
43 { .clkdm_name = "l4per_clkdm" },
44 { NULL },
45};
46
47static struct clkdm_dep cam_wkup_sleep_deps[] = {
48 { .clkdm_name = "emif_clkdm" },
49 { .clkdm_name = "iva_clkdm" },
50 { .clkdm_name = "l3main1_clkdm" },
51 { NULL },
52};
53
54static struct clkdm_dep dma_wkup_sleep_deps[] = {
55 { .clkdm_name = "abe_clkdm" },
56 { .clkdm_name = "dss_clkdm" },
57 { .clkdm_name = "emif_clkdm" },
58 { .clkdm_name = "ipu_clkdm" },
59 { .clkdm_name = "iva_clkdm" },
60 { .clkdm_name = "l3init_clkdm" },
61 { .clkdm_name = "l3main1_clkdm" },
62 { .clkdm_name = "l4cfg_clkdm" },
63 { .clkdm_name = "l4per_clkdm" },
64 { .clkdm_name = "l4sec_clkdm" },
65 { .clkdm_name = "wkupaon_clkdm" },
66 { NULL },
67};
68
69static struct clkdm_dep dsp_wkup_sleep_deps[] = {
70 { .clkdm_name = "abe_clkdm" },
71 { .clkdm_name = "emif_clkdm" },
72 { .clkdm_name = "iva_clkdm" },
73 { .clkdm_name = "l3init_clkdm" },
74 { .clkdm_name = "l3main1_clkdm" },
75 { .clkdm_name = "l3main2_clkdm" },
76 { .clkdm_name = "l4cfg_clkdm" },
77 { .clkdm_name = "l4per_clkdm" },
78 { .clkdm_name = "wkupaon_clkdm" },
79 { NULL },
80};
81
82static struct clkdm_dep dss_wkup_sleep_deps[] = {
83 { .clkdm_name = "emif_clkdm" },
84 { .clkdm_name = "iva_clkdm" },
85 { .clkdm_name = "l3main2_clkdm" },
86 { NULL },
87};
88
89static struct clkdm_dep gpu_wkup_sleep_deps[] = {
90 { .clkdm_name = "emif_clkdm" },
91 { .clkdm_name = "iva_clkdm" },
92 { .clkdm_name = "l3main1_clkdm" },
93 { NULL },
94};
95
96static struct clkdm_dep ipu_wkup_sleep_deps[] = {
97 { .clkdm_name = "abe_clkdm" },
98 { .clkdm_name = "dsp_clkdm" },
99 { .clkdm_name = "dss_clkdm" },
100 { .clkdm_name = "emif_clkdm" },
101 { .clkdm_name = "gpu_clkdm" },
102 { .clkdm_name = "iva_clkdm" },
103 { .clkdm_name = "l3init_clkdm" },
104 { .clkdm_name = "l3main1_clkdm" },
105 { .clkdm_name = "l3main2_clkdm" },
106 { .clkdm_name = "l4cfg_clkdm" },
107 { .clkdm_name = "l4per_clkdm" },
108 { .clkdm_name = "l4sec_clkdm" },
109 { .clkdm_name = "wkupaon_clkdm" },
110 { NULL },
111};
112
113static struct clkdm_dep iva_wkup_sleep_deps[] = {
114 { .clkdm_name = "emif_clkdm" },
115 { .clkdm_name = "l3main1_clkdm" },
116 { NULL },
117};
118
119static struct clkdm_dep l3init_wkup_sleep_deps[] = {
120 { .clkdm_name = "abe_clkdm" },
121 { .clkdm_name = "emif_clkdm" },
122 { .clkdm_name = "iva_clkdm" },
123 { .clkdm_name = "l4cfg_clkdm" },
124 { .clkdm_name = "l4per_clkdm" },
125 { .clkdm_name = "l4sec_clkdm" },
126 { .clkdm_name = "wkupaon_clkdm" },
127 { NULL },
128};
129
130static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
131 { .clkdm_name = "emif_clkdm" },
132 { .clkdm_name = "l3main1_clkdm" },
133 { .clkdm_name = "l4per_clkdm" },
134 { NULL },
135};
136
137static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
138 { .clkdm_name = "abe_clkdm" },
139 { .clkdm_name = "emif_clkdm" },
140 { .clkdm_name = "iva_clkdm" },
141 { .clkdm_name = "l3init_clkdm" },
142 { .clkdm_name = "l3main1_clkdm" },
143 { .clkdm_name = "l3main2_clkdm" },
144 { .clkdm_name = "l4cfg_clkdm" },
145 { .clkdm_name = "l4per_clkdm" },
146 { NULL },
147};
148
149static struct clkdm_dep mpu_wkup_sleep_deps[] = {
150 { .clkdm_name = "abe_clkdm" },
151 { .clkdm_name = "dsp_clkdm" },
152 { .clkdm_name = "dss_clkdm" },
153 { .clkdm_name = "emif_clkdm" },
154 { .clkdm_name = "gpu_clkdm" },
155 { .clkdm_name = "ipu_clkdm" },
156 { .clkdm_name = "iva_clkdm" },
157 { .clkdm_name = "l3init_clkdm" },
158 { .clkdm_name = "l3main1_clkdm" },
159 { .clkdm_name = "l3main2_clkdm" },
160 { .clkdm_name = "l4cfg_clkdm" },
161 { .clkdm_name = "l4per_clkdm" },
162 { .clkdm_name = "l4sec_clkdm" },
163 { .clkdm_name = "wkupaon_clkdm" },
164 { NULL },
165};
166
167static struct clockdomain l4sec_54xx_clkdm = {
168 .name = "l4sec_clkdm",
169 .pwrdm = { .name = "core_pwrdm" },
170 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
171 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
172 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
173 .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT,
174 .wkdep_srcs = l4sec_wkup_sleep_deps,
175 .sleepdep_srcs = l4sec_wkup_sleep_deps,
176 .flags = CLKDM_CAN_HWSUP_SWSUP,
177};
178
179static struct clockdomain iva_54xx_clkdm = {
180 .name = "iva_clkdm",
181 .pwrdm = { .name = "iva_pwrdm" },
182 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
183 .cm_inst = OMAP54XX_CM_CORE_IVA_INST,
184 .clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
185 .dep_bit = OMAP54XX_IVA_STATDEP_SHIFT,
186 .wkdep_srcs = iva_wkup_sleep_deps,
187 .sleepdep_srcs = iva_wkup_sleep_deps,
188 .flags = CLKDM_CAN_HWSUP_SWSUP,
189};
190
191static struct clockdomain mipiext_54xx_clkdm = {
192 .name = "mipiext_clkdm",
193 .pwrdm = { .name = "core_pwrdm" },
194 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
195 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
196 .clkdm_offs = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
197 .wkdep_srcs = mipiext_wkup_sleep_deps,
198 .sleepdep_srcs = mipiext_wkup_sleep_deps,
199 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
200};
201
202static struct clockdomain l3main2_54xx_clkdm = {
203 .name = "l3main2_clkdm",
204 .pwrdm = { .name = "core_pwrdm" },
205 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
206 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
207 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
208 .dep_bit = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
209 .flags = CLKDM_CAN_HWSUP,
210};
211
212static struct clockdomain l3main1_54xx_clkdm = {
213 .name = "l3main1_clkdm",
214 .pwrdm = { .name = "core_pwrdm" },
215 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
216 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
217 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
218 .dep_bit = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
219 .flags = CLKDM_CAN_HWSUP,
220};
221
222static struct clockdomain custefuse_54xx_clkdm = {
223 .name = "custefuse_clkdm",
224 .pwrdm = { .name = "custefuse_pwrdm" },
225 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
226 .cm_inst = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
227 .clkdm_offs = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
228 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
229};
230
231static struct clockdomain ipu_54xx_clkdm = {
232 .name = "ipu_clkdm",
233 .pwrdm = { .name = "core_pwrdm" },
234 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
235 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
236 .clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
237 .dep_bit = OMAP54XX_IPU_STATDEP_SHIFT,
238 .wkdep_srcs = ipu_wkup_sleep_deps,
239 .sleepdep_srcs = ipu_wkup_sleep_deps,
240 .flags = CLKDM_CAN_HWSUP_SWSUP,
241};
242
243static struct clockdomain l4cfg_54xx_clkdm = {
244 .name = "l4cfg_clkdm",
245 .pwrdm = { .name = "core_pwrdm" },
246 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
247 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
248 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
249 .dep_bit = OMAP54XX_L4CFG_STATDEP_SHIFT,
250 .flags = CLKDM_CAN_HWSUP,
251};
252
253static struct clockdomain abe_54xx_clkdm = {
254 .name = "abe_clkdm",
255 .pwrdm = { .name = "abe_pwrdm" },
256 .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
257 .cm_inst = OMAP54XX_CM_CORE_AON_ABE_INST,
258 .clkdm_offs = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
259 .dep_bit = OMAP54XX_ABE_STATDEP_SHIFT,
260 .flags = CLKDM_CAN_HWSUP_SWSUP,
261};
262
263static struct clockdomain dss_54xx_clkdm = {
264 .name = "dss_clkdm",
265 .pwrdm = { .name = "dss_pwrdm" },
266 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
267 .cm_inst = OMAP54XX_CM_CORE_DSS_INST,
268 .clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
269 .dep_bit = OMAP54XX_DSS_STATDEP_SHIFT,
270 .wkdep_srcs = dss_wkup_sleep_deps,
271 .sleepdep_srcs = dss_wkup_sleep_deps,
272 .flags = CLKDM_CAN_HWSUP_SWSUP,
273};
274
275static struct clockdomain dsp_54xx_clkdm = {
276 .name = "dsp_clkdm",
277 .pwrdm = { .name = "dsp_pwrdm" },
278 .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
279 .cm_inst = OMAP54XX_CM_CORE_AON_DSP_INST,
280 .clkdm_offs = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
281 .dep_bit = OMAP54XX_DSP_STATDEP_SHIFT,
282 .wkdep_srcs = dsp_wkup_sleep_deps,
283 .sleepdep_srcs = dsp_wkup_sleep_deps,
284 .flags = CLKDM_CAN_HWSUP_SWSUP,
285};
286
287static struct clockdomain c2c_54xx_clkdm = {
288 .name = "c2c_clkdm",
289 .pwrdm = { .name = "core_pwrdm" },
290 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
291 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
292 .clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
293 .wkdep_srcs = c2c_wkup_sleep_deps,
294 .sleepdep_srcs = c2c_wkup_sleep_deps,
295 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
296};
297
298static struct clockdomain l4per_54xx_clkdm = {
299 .name = "l4per_clkdm",
300 .pwrdm = { .name = "core_pwrdm" },
301 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
302 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
303 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
304 .dep_bit = OMAP54XX_L4PER_STATDEP_SHIFT,
305 .flags = CLKDM_CAN_HWSUP_SWSUP,
306};
307
308static struct clockdomain gpu_54xx_clkdm = {
309 .name = "gpu_clkdm",
310 .pwrdm = { .name = "gpu_pwrdm" },
311 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
312 .cm_inst = OMAP54XX_CM_CORE_GPU_INST,
313 .clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
314 .dep_bit = OMAP54XX_GPU_STATDEP_SHIFT,
315 .wkdep_srcs = gpu_wkup_sleep_deps,
316 .sleepdep_srcs = gpu_wkup_sleep_deps,
317 .flags = CLKDM_CAN_HWSUP_SWSUP,
318};
319
320static struct clockdomain wkupaon_54xx_clkdm = {
321 .name = "wkupaon_clkdm",
322 .pwrdm = { .name = "wkupaon_pwrdm" },
323 .prcm_partition = OMAP54XX_PRM_PARTITION,
324 .cm_inst = OMAP54XX_PRM_WKUPAON_CM_INST,
325 .clkdm_offs = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
326 .dep_bit = OMAP54XX_WKUPAON_STATDEP_SHIFT,
327 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
328};
329
330static struct clockdomain mpu0_54xx_clkdm = {
331 .name = "mpu0_clkdm",
332 .pwrdm = { .name = "cpu0_pwrdm" },
333 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
334 .cm_inst = OMAP54XX_PRCM_MPU_CM_C0_INST,
335 .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
336 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
337};
338
339static struct clockdomain mpu1_54xx_clkdm = {
340 .name = "mpu1_clkdm",
341 .pwrdm = { .name = "cpu1_pwrdm" },
342 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
343 .cm_inst = OMAP54XX_PRCM_MPU_CM_C1_INST,
344 .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
345 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
346};
347
348static struct clockdomain coreaon_54xx_clkdm = {
349 .name = "coreaon_clkdm",
350 .pwrdm = { .name = "coreaon_pwrdm" },
351 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
352 .cm_inst = OMAP54XX_CM_CORE_COREAON_INST,
353 .clkdm_offs = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
354 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
355};
356
357static struct clockdomain mpu_54xx_clkdm = {
358 .name = "mpu_clkdm",
359 .pwrdm = { .name = "mpu_pwrdm" },
360 .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
361 .cm_inst = OMAP54XX_CM_CORE_AON_MPU_INST,
362 .clkdm_offs = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
363 .wkdep_srcs = mpu_wkup_sleep_deps,
364 .sleepdep_srcs = mpu_wkup_sleep_deps,
365 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
366};
367
368static struct clockdomain l3init_54xx_clkdm = {
369 .name = "l3init_clkdm",
370 .pwrdm = { .name = "l3init_pwrdm" },
371 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
372 .cm_inst = OMAP54XX_CM_CORE_L3INIT_INST,
373 .clkdm_offs = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
374 .dep_bit = OMAP54XX_L3INIT_STATDEP_SHIFT,
375 .wkdep_srcs = l3init_wkup_sleep_deps,
376 .sleepdep_srcs = l3init_wkup_sleep_deps,
377 .flags = CLKDM_CAN_HWSUP_SWSUP,
378};
379
380static struct clockdomain dma_54xx_clkdm = {
381 .name = "dma_clkdm",
382 .pwrdm = { .name = "core_pwrdm" },
383 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
384 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
385 .clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
386 .wkdep_srcs = dma_wkup_sleep_deps,
387 .sleepdep_srcs = dma_wkup_sleep_deps,
388 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
389};
390
391static struct clockdomain l3instr_54xx_clkdm = {
392 .name = "l3instr_clkdm",
393 .pwrdm = { .name = "core_pwrdm" },
394 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
395 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
396 .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
397};
398
399static struct clockdomain emif_54xx_clkdm = {
400 .name = "emif_clkdm",
401 .pwrdm = { .name = "core_pwrdm" },
402 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
403 .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
404 .clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
405 .dep_bit = OMAP54XX_EMIF_STATDEP_SHIFT,
406 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
407};
408
409static struct clockdomain emu_54xx_clkdm = {
410 .name = "emu_clkdm",
411 .pwrdm = { .name = "emu_pwrdm" },
412 .prcm_partition = OMAP54XX_PRM_PARTITION,
413 .cm_inst = OMAP54XX_PRM_EMU_CM_INST,
414 .clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
415 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
416};
417
418static struct clockdomain cam_54xx_clkdm = {
419 .name = "cam_clkdm",
420 .pwrdm = { .name = "cam_pwrdm" },
421 .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
422 .cm_inst = OMAP54XX_CM_CORE_CAM_INST,
423 .clkdm_offs = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
424 .wkdep_srcs = cam_wkup_sleep_deps,
425 .sleepdep_srcs = cam_wkup_sleep_deps,
426 .flags = CLKDM_CAN_HWSUP_SWSUP,
427};
428
429/* As clockdomains are added or removed above, this list must also be changed */
430static struct clockdomain *clockdomains_omap54xx[] __initdata = {
431 &l4sec_54xx_clkdm,
432 &iva_54xx_clkdm,
433 &mipiext_54xx_clkdm,
434 &l3main2_54xx_clkdm,
435 &l3main1_54xx_clkdm,
436 &custefuse_54xx_clkdm,
437 &ipu_54xx_clkdm,
438 &l4cfg_54xx_clkdm,
439 &abe_54xx_clkdm,
440 &dss_54xx_clkdm,
441 &dsp_54xx_clkdm,
442 &c2c_54xx_clkdm,
443 &l4per_54xx_clkdm,
444 &gpu_54xx_clkdm,
445 &wkupaon_54xx_clkdm,
446 &mpu0_54xx_clkdm,
447 &mpu1_54xx_clkdm,
448 &coreaon_54xx_clkdm,
449 &mpu_54xx_clkdm,
450 &l3init_54xx_clkdm,
451 &dma_54xx_clkdm,
452 &l3instr_54xx_clkdm,
453 &emif_54xx_clkdm,
454 &emu_54xx_clkdm,
455 &cam_54xx_clkdm,
456 NULL
457};
458
459void __init omap54xx_clockdomains_init(void)
460{
461 clkdm_register_platform_funcs(&omap4_clkdm_operations);
462 clkdm_register_clkdms(clockdomains_omap54xx);
463 clkdm_complete_init();
464}
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
new file mode 100644
index 000000000000..e83b8e352b6e
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -0,0 +1,1737 @@
1/*
2 * OMAP54xx Clock Management register bits
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
23
24/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
25#define OMAP54XX_ABE_DYNDEP_SHIFT 3
26#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1
27#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3)
28
29/*
30 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
31 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
32 */
33#define OMAP54XX_ABE_STATDEP_SHIFT 3
34#define OMAP54XX_ABE_STATDEP_WIDTH 0x1
35#define OMAP54XX_ABE_STATDEP_MASK (1 << 3)
36
37/*
38 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
39 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
40 * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
41 */
42#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0
43#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3
44#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
45
46/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
47#define OMAP54XX_C2C_DYNDEP_SHIFT 18
48#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1
49#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18)
50
51/* Used by CM_MPU_STATICDEP */
52#define OMAP54XX_C2C_STATDEP_SHIFT 18
53#define OMAP54XX_C2C_STATDEP_WIDTH 0x1
54#define OMAP54XX_C2C_STATDEP_MASK (1 << 18)
55
56/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
57#define OMAP54XX_CAM_DYNDEP_SHIFT 9
58#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1
59#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9)
60
61/*
62 * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
63 * CM_MPU_STATICDEP
64 */
65#define OMAP54XX_CAM_STATDEP_SHIFT 9
66#define OMAP54XX_CAM_STATDEP_WIDTH 0x1
67#define OMAP54XX_CAM_STATDEP_MASK (1 << 9)
68
69/* Used by CM_ABE_CLKSTCTRL */
70#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
71#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
72#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
73
74/* Used by CM_ABE_CLKSTCTRL */
75#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12
76#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1
77#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12)
78
79/* Used by CM_ABE_CLKSTCTRL */
80#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9
81#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1
82#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9)
83
84/* Used by CM_WKUPAON_CLKSTCTRL */
85#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
86#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
87#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
88
89/* Used by CM_ABE_CLKSTCTRL */
90#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11
91#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1
92#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11)
93
94/* Used by CM_ABE_CLKSTCTRL */
95#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
96#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
97#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
98
99/* Used by CM_DSS_CLKSTCTRL */
100#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13
101#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1
102#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13)
103
104/* Used by CM_C2C_CLKSTCTRL */
105#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9
106#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1
107#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9)
108
109/* Used by CM_C2C_CLKSTCTRL */
110#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10
111#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1
112#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10)
113
114/* Used by CM_C2C_CLKSTCTRL */
115#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8
116#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1
117#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8)
118
119/* Used by CM_CAM_CLKSTCTRL */
120#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11
121#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1
122#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11)
123
124/* Used by CM_CAM_CLKSTCTRL */
125#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8
126#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1
127#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8)
128
129/* Used by CM_CAM_CLKSTCTRL */
130#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12
131#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1
132#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12)
133
134/* Used by CM_COREAON_CLKSTCTRL */
135#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12
136#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1
137#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12)
138
139/* Used by CM_COREAON_CLKSTCTRL */
140#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14
141#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1
142#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14)
143
144/* Used by CM_COREAON_CLKSTCTRL */
145#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8
146#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1
147#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8)
148
149/* Used by CM_CAM_CLKSTCTRL */
150#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9
151#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1
152#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9)
153
154/* Used by CM_CUSTEFUSE_CLKSTCTRL */
155#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8
156#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1
157#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8)
158
159/* Used by CM_CUSTEFUSE_CLKSTCTRL */
160#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9
161#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1
162#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9)
163
164/* Used by CM_EMIF_CLKSTCTRL */
165#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9
166#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1
167#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9)
168
169/* Used by CM_DMA_CLKSTCTRL */
170#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8
171#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1
172#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8)
173
174/* Used by CM_DSP_CLKSTCTRL */
175#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8
176#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1
177#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8)
178
179/* Used by CM_DSS_CLKSTCTRL */
180#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9
181#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1
182#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9)
183
184/* Used by CM_DSS_CLKSTCTRL */
185#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8
186#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1
187#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8)
188
189/* Used by CM_DSS_CLKSTCTRL */
190#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10
191#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1
192#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10)
193
194/* Used by CM_EMIF_CLKSTCTRL */
195#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8
196#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1
197#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8)
198
199/* Used by CM_EMIF_CLKSTCTRL */
200#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11
201#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1
202#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11)
203
204/* Used by CM_EMIF_CLKSTCTRL */
205#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10
206#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1
207#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10)
208
209/* Used by CM_EMU_CLKSTCTRL */
210#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8
211#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1
212#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8)
213
214/* Used by CM_CAM_CLKSTCTRL */
215#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10
216#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1
217#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10)
218
219/* Used by CM_ABE_CLKSTCTRL */
220#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
221#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
222#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
223
224/* Used by CM_GPU_CLKSTCTRL */
225#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9
226#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1
227#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9)
228
229/* Used by CM_GPU_CLKSTCTRL */
230#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10
231#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1
232#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10)
233
234/* Used by CM_GPU_CLKSTCTRL */
235#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8
236#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1
237#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8)
238
239/* Used by CM_DSS_CLKSTCTRL */
240#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12
241#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1
242#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12)
243
244/* Used by CM_DSS_CLKSTCTRL */
245#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11
246#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1
247#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11)
248
249/* Used by CM_L3INIT_CLKSTCTRL */
250#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
251#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
252#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
253
254/* Used by CM_L3INIT_CLKSTCTRL */
255#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
256#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
257#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
258
259/* Used by CM_L3INIT_CLKSTCTRL */
260#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
261#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
262#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
263
264/* Used by CM_L3INIT_CLKSTCTRL */
265#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
266#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
267#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
268
269/* Used by CM_L3INIT_CLKSTCTRL */
270#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6
271#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1
272#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6)
273
274/* Used by CM_L3INIT_CLKSTCTRL */
275#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7
276#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1
277#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7)
278
279/* Used by CM_L3INIT_CLKSTCTRL */
280#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16
281#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1
282#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16)
283
284/* Used by CM_IPU_CLKSTCTRL */
285#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8
286#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1
287#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8)
288
289/* Used by CM_IVA_CLKSTCTRL */
290#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8
291#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1
292#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8)
293
294/* Used by CM_L3INIT_CLKSTCTRL */
295#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12
296#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1
297#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12)
298
299/* Used by CM_L3INIT_CLKSTCTRL */
300#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28
301#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1
302#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28)
303
304/* Used by CM_L3INIT_CLKSTCTRL */
305#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29
306#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1
307#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29)
308
309/* Used by CM_L3INIT_CLKSTCTRL */
310#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8
311#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1
312#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8)
313
314/* Used by CM_L3INIT_CLKSTCTRL */
315#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9
316#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1
317#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9)
318
319/* Used by CM_L3INIT_CLKSTCTRL */
320#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11
321#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1
322#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11)
323
324/* Used by CM_L3INSTR_CLKSTCTRL */
325#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9
326#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1
327#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9)
328
329/* Used by CM_L3INSTR_CLKSTCTRL */
330#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8
331#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1
332#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8)
333
334/* Used by CM_L3INSTR_CLKSTCTRL */
335#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10
336#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1
337#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10)
338
339/* Used by CM_L3MAIN1_CLKSTCTRL */
340#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8
341#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1
342#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8)
343
344/* Used by CM_L3MAIN2_CLKSTCTRL */
345#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8
346#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1
347#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8)
348
349/* Used by CM_L4CFG_CLKSTCTRL */
350#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8
351#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1
352#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8)
353
354/* Used by CM_L4PER_CLKSTCTRL */
355#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8
356#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1
357#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8)
358
359/* Used by CM_L4SEC_CLKSTCTRL */
360#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8
361#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1
362#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8)
363
364/* Used by CM_L4SEC_CLKSTCTRL */
365#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9
366#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1
367#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9)
368
369/* Used by CM_MIPIEXT_CLKSTCTRL */
370#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8
371#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1
372#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8)
373
374/* Used by CM_MIPIEXT_CLKSTCTRL */
375#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11
376#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1
377#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11)
378
379/* Used by CM_L3INIT_CLKSTCTRL */
380#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2
381#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1
382#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2)
383
384/* Used by CM_L3INIT_CLKSTCTRL */
385#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17
386#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1
387#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17)
388
389/* Used by CM_L3INIT_CLKSTCTRL */
390#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18
391#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1
392#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18)
393
394/* Used by CM_MPU_CLKSTCTRL */
395#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8
396#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1
397#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8)
398
399/* Used by CM_ABE_CLKSTCTRL */
400#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14
401#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1
402#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14)
403
404/* Used by CM_ABE_CLKSTCTRL */
405#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15
406#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1
407#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15)
408
409/* Used by CM_L3INIT_CLKSTCTRL */
410#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3
411#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1
412#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3)
413
414/* Used by CM_L3INIT_CLKSTCTRL */
415#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4
416#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1
417#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4)
418
419/* Used by CM_L4PER_CLKSTCTRL */
420#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15
421#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1
422#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15)
423
424/* Used by CM_L4PER_CLKSTCTRL */
425#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
426#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
427#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
428
429/* Used by CM_L4PER_CLKSTCTRL */
430#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
431#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
432#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
433
434/* Used by CM_L4PER_CLKSTCTRL */
435#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
436#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
437#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
438
439/* Used by CM_L3INIT_CLKSTCTRL */
440#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19
441#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1
442#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19)
443
444/* Used by CM_COREAON_CLKSTCTRL */
445#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11
446#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1
447#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11)
448
449/* Used by CM_COREAON_CLKSTCTRL */
450#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10
451#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1
452#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10)
453
454/* Used by CM_COREAON_CLKSTCTRL */
455#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9
456#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1
457#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9)
458
459/* Used by CM_WKUPAON_CLKSTCTRL */
460#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8
461#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1
462#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
463
464/* Used by CM_WKUPAON_CLKSTCTRL */
465#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15
466#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1
467#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15)
468
469/* Used by CM_WKUPAON_CLKSTCTRL */
470#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14
471#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1
472#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14)
473
474/* Used by CM_L4PER_CLKSTCTRL */
475#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9
476#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1
477#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9)
478
479/* Used by CM_L4PER_CLKSTCTRL */
480#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10
481#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1
482#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10)
483
484/* Used by CM_L4PER_CLKSTCTRL */
485#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11
486#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1
487#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11)
488
489/* Used by CM_L4PER_CLKSTCTRL */
490#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12
491#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1
492#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12)
493
494/* Used by CM_L4PER_CLKSTCTRL */
495#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13
496#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1
497#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13)
498
499/* Used by CM_L4PER_CLKSTCTRL */
500#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14
501#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1
502#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14)
503
504/* Used by CM_L3INIT_CLKSTCTRL */
505#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
506#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
507#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
508
509/* Used by CM_L3INIT_CLKSTCTRL */
510#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
511#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
512#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
513
514/* Used by CM_L3INIT_CLKSTCTRL */
515#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
516#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
517#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
518
519/* Used by CM_MIPIEXT_CLKSTCTRL */
520#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10
521#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1
522#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10)
523
524/* Used by CM_MIPIEXT_CLKSTCTRL */
525#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13
526#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1
527#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13)
528
529/* Used by CM_MIPIEXT_CLKSTCTRL */
530#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12
531#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1
532#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12)
533
534/* Used by CM_L3INIT_CLKSTCTRL */
535#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10
536#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1
537#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10)
538
539/* Used by CM_L3INIT_CLKSTCTRL */
540#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13
541#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1
542#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13)
543
544/* Used by CM_L3INIT_CLKSTCTRL */
545#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5
546#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1
547#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5)
548
549/* Used by CM_L3INIT_CLKSTCTRL */
550#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
551#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
552#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
553
554/* Used by CM_L3INIT_CLKSTCTRL */
555#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
556#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
557#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
558
559/* Used by CM_L3INIT_CLKSTCTRL */
560#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31
561#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1
562#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31)
563
564/* Used by CM_L3INIT_CLKSTCTRL */
565#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
566#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
567#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
568
569/* Used by CM_L3INIT_CLKSTCTRL */
570#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
571#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
572#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
573
574/* Used by CM_WKUPAON_CLKSTCTRL */
575#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11
576#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1
577#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11)
578
579/* Used by CM_WKUPAON_CLKSTCTRL */
580#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12
581#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1
582#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12)
583
584/* Used by CM_WKUPAON_CLKSTCTRL */
585#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13
586#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1
587#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13)
588
589/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
590#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8
591#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1
592#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8)
593
594/*
595 * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
596 * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
597 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
598 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
599 */
600#define OMAP54XX_CLKSEL_SHIFT 24
601#define OMAP54XX_CLKSEL_WIDTH 0x1
602#define OMAP54XX_CLKSEL_MASK (1 << 24)
603
604/*
605 * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
606 * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
607 */
608#define OMAP54XX_CLKSEL_0_0_SHIFT 0
609#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1
610#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0)
611
612/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
613#define OMAP54XX_CLKSEL_0_1_SHIFT 0
614#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2
615#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0)
616
617/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
618#define OMAP54XX_CLKSEL_24_25_SHIFT 24
619#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2
620#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24)
621
622/* Used by CM_MPU_MPU_CLKCTRL */
623#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26
624#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
625#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
626
627/* Used by CM_ABE_AESS_CLKCTRL */
628#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24
629#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1
630#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24)
631
632/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
633#define OMAP54XX_CLKSEL_DIV_SHIFT 25
634#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1
635#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25)
636
637/* Used by CM_MPU_MPU_CLKCTRL */
638#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24
639#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2
640#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24)
641
642/* Used by CM_CAM_FDIF_CLKCTRL */
643#define OMAP54XX_CLKSEL_FCLK_SHIFT 24
644#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1
645#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24)
646
647/* Used by CM_GPU_GPU_CLKCTRL */
648#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24
649#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1
650#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
651
652/* Used by CM_GPU_GPU_CLKCTRL */
653#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25
654#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1
655#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
656
657/* Used by CM_GPU_GPU_CLKCTRL */
658#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26
659#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1
660#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26)
661
662/*
663 * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
664 * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
665 */
666#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26
667#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2
668#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26)
669
670/* Used by CM_CLKSEL_CORE */
671#define OMAP54XX_CLKSEL_L3_SHIFT 4
672#define OMAP54XX_CLKSEL_L3_WIDTH 0x1
673#define OMAP54XX_CLKSEL_L3_MASK (1 << 4)
674
675/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
676#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1
677#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1
678#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1)
679
680/* Used by CM_CLKSEL_CORE */
681#define OMAP54XX_CLKSEL_L4_SHIFT 8
682#define OMAP54XX_CLKSEL_L4_WIDTH 0x1
683#define OMAP54XX_CLKSEL_L4_MASK (1 << 8)
684
685/* Used by CM_EMIF_EMIF1_CLKCTRL */
686#define OMAP54XX_CLKSEL_LL_SHIFT 24
687#define OMAP54XX_CLKSEL_LL_WIDTH 0x1
688#define OMAP54XX_CLKSEL_LL_MASK (1 << 24)
689
690/* Used by CM_CLKSEL_ABE */
691#define OMAP54XX_CLKSEL_OPP_SHIFT 0
692#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2
693#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0)
694
695/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
696#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24
697#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1
698#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24)
699
700/*
701 * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
702 * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
703 */
704#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24
705#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2
706#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24)
707
708/*
709 * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
710 * CM_L3INIT_MMC2_CLKCTRL
711 */
712#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24
713#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1
714#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24)
715
716/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
717#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24
718#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1
719#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24)
720
721/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
722#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25
723#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1
724#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25)
725
726/*
727 * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
728 * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
729 * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
730 * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
731 * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
732 * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
733 * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
734 * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
735 */
736#define OMAP54XX_CLKST_SHIFT 9
737#define OMAP54XX_CLKST_WIDTH 0x1
738#define OMAP54XX_CLKST_MASK (1 << 9)
739
740/*
741 * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
742 * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
743 * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
744 * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
745 * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
746 * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
747 * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
748 */
749#define OMAP54XX_CLKTRCTRL_SHIFT 0
750#define OMAP54XX_CLKTRCTRL_WIDTH 0x2
751#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0)
752
753/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
754#define OMAP54XX_CLKX2ST_SHIFT 11
755#define OMAP54XX_CLKX2ST_WIDTH 0x1
756#define OMAP54XX_CLKX2ST_MASK (1 << 11)
757
758/* Used by CM_L4CFG_DYNAMICDEP */
759#define OMAP54XX_COREAON_DYNDEP_SHIFT 16
760#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1
761#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16)
762
763/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
764#define OMAP54XX_COREAON_STATDEP_SHIFT 16
765#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1
766#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16)
767
768/* Used by CM_L4CFG_DYNAMICDEP */
769#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17
770#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1
771#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17)
772
773/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
774#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17
775#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1
776#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17)
777
778/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
779#define OMAP54XX_CUSTOM_SHIFT 6
780#define OMAP54XX_CUSTOM_WIDTH 0x2
781#define OMAP54XX_CUSTOM_MASK (0x3 << 6)
782
783/*
784 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
785 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
786 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
787 */
788#define OMAP54XX_DCC_EN_SHIFT 22
789#define OMAP54XX_DCC_EN_WIDTH 0x1
790#define OMAP54XX_DCC_EN_MASK (1 << 22)
791
792/*
793 * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
794 * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
795 * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
796 */
797#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0
798#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd
799#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0)
800
801/*
802 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
803 * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
804 */
805#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
806#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
807#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
808
809/*
810 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
811 * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
812 */
813#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0
814#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9
815#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0)
816
817/*
818 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
819 * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
820 */
821#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0
822#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5
823#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0)
824
825/*
826 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
827 * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
828 */
829#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0
830#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6
831#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0)
832
833/*
834 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
835 * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
836 */
837#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0
838#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb
839#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0)
840
841/*
842 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
843 * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
844 */
845#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
846#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
847#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
848
849/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
850#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0
851#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14
852#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0)
853
854/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
855#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
856#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
857#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
858
859/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
860#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0
861#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b
862#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0)
863
864/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
865#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0
866#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe
867#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0)
868
869/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
870#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0
871#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16
872#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0)
873
874/*
875 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
876 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
877 * CM_SSC_DELTAMSTEP_DPLL_PER
878 */
879#define OMAP54XX_DELTAMSTEP_SHIFT 0
880#define OMAP54XX_DELTAMSTEP_WIDTH 0x14
881#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0)
882
883/*
884 * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
885 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
886 */
887#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0
888#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15
889#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
890
891/*
892 * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
893 * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
894 * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
895 * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
896 * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
897 */
898#define OMAP54XX_DIVHS_SHIFT 0
899#define OMAP54XX_DIVHS_WIDTH 0x6
900#define OMAP54XX_DIVHS_MASK (0x3f << 0)
901
902/*
903 * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
904 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
905 * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
906 */
907#define OMAP54XX_DIVHS_0_4_SHIFT 0
908#define OMAP54XX_DIVHS_0_4_WIDTH 0x5
909#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0)
910
911/*
912 * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
913 * CM_DIV_M2_DPLL_USB
914 */
915#define OMAP54XX_DIVHS_0_6_SHIFT 0
916#define OMAP54XX_DIVHS_0_6_WIDTH 0x7
917#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0)
918
919/* Used by CM_DLL_CTRL */
920#define OMAP54XX_DLL_OVERRIDE_SHIFT 0
921#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1
922#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0)
923
924/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
925#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2
926#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1
927#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2)
928
929/* Used by CM_SHADOW_FREQ_CONFIG1 */
930#define OMAP54XX_DLL_RESET_SHIFT 3
931#define OMAP54XX_DLL_RESET_WIDTH 0x1
932#define OMAP54XX_DLL_RESET_MASK (1 << 3)
933
934/*
935 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
936 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
937 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
938 */
939#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23
940#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1
941#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
942
943/* Used by CM_CLKSEL_DPLL_CORE */
944#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
945#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
946#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
947
948/* Used by CM_SHADOW_FREQ_CONFIG1 */
949#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8
950#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3
951#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
952
953/* Used by CM_SHADOW_FREQ_CONFIG2 */
954#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2
955#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6
956#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2)
957
958/* Used by CM_SHADOW_FREQ_CONFIG1 */
959#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11
960#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5
961#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
962
963/*
964 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
965 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
966 */
967#define OMAP54XX_DPLL_DIV_SHIFT 0
968#define OMAP54XX_DPLL_DIV_WIDTH 0x7
969#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0)
970
971/*
972 * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
973 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
974 */
975#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0
976#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8
977#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0)
978
979/*
980 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
981 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
982 */
983#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8
984#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1
985#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
986
987/*
988 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
989 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
990 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
991 */
992#define OMAP54XX_DPLL_EN_SHIFT 0
993#define OMAP54XX_DPLL_EN_WIDTH 0x3
994#define OMAP54XX_DPLL_EN_MASK (0x7 << 0)
995
996/*
997 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
998 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
999 */
1000#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10
1001#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1
1002#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10)
1003
1004/*
1005 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
1006 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
1007 */
1008#define OMAP54XX_DPLL_MULT_SHIFT 8
1009#define OMAP54XX_DPLL_MULT_WIDTH 0xb
1010#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8)
1011
1012/*
1013 * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
1014 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
1015 */
1016#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8
1017#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc
1018#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8)
1019
1020/*
1021 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1022 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
1023 */
1024#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11
1025#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1
1026#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11)
1027
1028/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
1029#define OMAP54XX_DPLL_SD_DIV_SHIFT 24
1030#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8
1031#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24)
1032
1033/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
1034#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21
1035#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1
1036#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21)
1037
1038/*
1039 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1040 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1041 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1042 */
1043#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13
1044#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1
1045#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13)
1046
1047/*
1048 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1049 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1050 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1051 */
1052#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
1053#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
1054#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
1055
1056/*
1057 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1058 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1059 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1060 */
1061#define OMAP54XX_DPLL_SSC_EN_SHIFT 12
1062#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1
1063#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12)
1064
1065/* Used by CM_L4CFG_DYNAMICDEP */
1066#define OMAP54XX_DSP_DYNDEP_SHIFT 1
1067#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1
1068#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1)
1069
1070/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1071#define OMAP54XX_DSP_STATDEP_SHIFT 1
1072#define OMAP54XX_DSP_STATDEP_WIDTH 0x1
1073#define OMAP54XX_DSP_STATDEP_MASK (1 << 1)
1074
1075/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1076#define OMAP54XX_DSS_DYNDEP_SHIFT 8
1077#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1
1078#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8)
1079
1080/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1081#define OMAP54XX_DSS_STATDEP_SHIFT 8
1082#define OMAP54XX_DSS_STATDEP_WIDTH 0x1
1083#define OMAP54XX_DSS_STATDEP_MASK (1 << 8)
1084
1085/*
1086 * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1087 * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
1088 */
1089#define OMAP54XX_EMIF_DYNDEP_SHIFT 4
1090#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1
1091#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4)
1092
1093/*
1094 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1095 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1096 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1097 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1098 */
1099#define OMAP54XX_EMIF_STATDEP_SHIFT 4
1100#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1
1101#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4)
1102
1103/* Used by CM_SHADOW_FREQ_CONFIG1 */
1104#define OMAP54XX_FREQ_UPDATE_SHIFT 0
1105#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1
1106#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0)
1107
1108/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1109#define OMAP54XX_FUNC_SHIFT 16
1110#define OMAP54XX_FUNC_WIDTH 0xc
1111#define OMAP54XX_FUNC_MASK (0xfff << 16)
1112
1113/* Used by CM_SHADOW_FREQ_CONFIG2 */
1114#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0
1115#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1
1116#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0)
1117
1118/* Used by CM_L3MAIN2_DYNAMICDEP */
1119#define OMAP54XX_GPU_DYNDEP_SHIFT 10
1120#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1
1121#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10)
1122
1123/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1124#define OMAP54XX_GPU_STATDEP_SHIFT 10
1125#define OMAP54XX_GPU_STATDEP_WIDTH 0x1
1126#define OMAP54XX_GPU_STATDEP_MASK (1 << 10)
1127
1128/*
1129 * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
1130 * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
1131 * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
1132 * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
1133 * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
1134 * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
1135 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
1136 * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
1137 * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
1138 * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
1139 * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1140 * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
1141 * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1142 * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
1143 * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
1144 * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1145 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
1146 * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
1147 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
1148 * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
1149 * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
1150 * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1151 * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
1152 * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
1153 * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
1154 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
1155 * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1156 * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1157 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1158 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
1159 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1160 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1161 * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1162 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
1163 * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
1164 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
1165 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1166 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1167 * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1168 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1169 * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1170 * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
1171 * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1172 * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
1173 * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
1174 * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
1175 * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
1176 * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
1177 */
1178#define OMAP54XX_IDLEST_SHIFT 16
1179#define OMAP54XX_IDLEST_WIDTH 0x2
1180#define OMAP54XX_IDLEST_MASK (0x3 << 16)
1181
1182/* Used by CM_L3MAIN2_DYNAMICDEP */
1183#define OMAP54XX_IPU_DYNDEP_SHIFT 0
1184#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1
1185#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0)
1186
1187/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
1188#define OMAP54XX_IPU_STATDEP_SHIFT 0
1189#define OMAP54XX_IPU_STATDEP_WIDTH 0x1
1190#define OMAP54XX_IPU_STATDEP_MASK (1 << 0)
1191
1192/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
1193#define OMAP54XX_IVA_DYNDEP_SHIFT 2
1194#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1
1195#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2)
1196
1197/*
1198 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1199 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1200 * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1201 */
1202#define OMAP54XX_IVA_STATDEP_SHIFT 2
1203#define OMAP54XX_IVA_STATDEP_WIDTH 0x1
1204#define OMAP54XX_IVA_STATDEP_MASK (1 << 2)
1205
1206/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1207#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7
1208#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1
1209#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7)
1210
1211/*
1212 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1213 * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1214 */
1215#define OMAP54XX_L3INIT_STATDEP_SHIFT 7
1216#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1
1217#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7)
1218
1219/*
1220 * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
1221 * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
1222 */
1223#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5
1224#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1
1225#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5)
1226
1227/*
1228 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1229 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1230 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1231 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1232 */
1233#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5
1234#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1
1235#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5)
1236
1237/*
1238 * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
1239 * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
1240 * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
1241 * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
1242 */
1243#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6
1244#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1
1245#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6)
1246
1247/*
1248 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1249 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1250 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1251 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1252 */
1253#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6
1254#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1
1255#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6)
1256
1257/* Used by CM_L3MAIN1_DYNAMICDEP */
1258#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12
1259#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1
1260#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12)
1261
1262/*
1263 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1264 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1265 */
1266#define OMAP54XX_L4CFG_STATDEP_SHIFT 12
1267#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1
1268#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12)
1269
1270/* Used by CM_L3MAIN2_DYNAMICDEP */
1271#define OMAP54XX_L4PER_DYNDEP_SHIFT 13
1272#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1
1273#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13)
1274
1275/*
1276 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1277 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1278 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1279 */
1280#define OMAP54XX_L4PER_STATDEP_SHIFT 13
1281#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1
1282#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13)
1283
1284/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1285#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14
1286#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1
1287#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14)
1288
1289/*
1290 * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
1291 * CM_MPU_STATICDEP
1292 */
1293#define OMAP54XX_L4SEC_STATDEP_SHIFT 14
1294#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1
1295#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14)
1296
1297/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
1298#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21
1299#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1
1300#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21)
1301
1302/* Used by CM_MPU_STATICDEP */
1303#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21
1304#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1
1305#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21)
1306
1307/*
1308 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1309 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1310 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
1311 * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
1312 */
1313#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8
1314#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3
1315#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1316
1317/*
1318 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1319 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1320 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
1321 * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
1322 */
1323#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0
1324#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7
1325#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
1326
1327/*
1328 * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
1329 * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
1330 * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
1331 * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
1332 * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
1333 * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
1334 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
1335 * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
1336 * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
1337 * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
1338 * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1339 * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
1340 * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1341 * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
1342 * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
1343 * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1344 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
1345 * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
1346 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
1347 * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
1348 * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
1349 * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1350 * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
1351 * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
1352 * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
1353 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
1354 * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1355 * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1356 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1357 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
1358 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1359 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1360 * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1361 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
1362 * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
1363 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
1364 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1365 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1366 * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1367 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1368 * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1369 * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
1370 * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1371 * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
1372 * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
1373 * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
1374 * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
1375 * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
1376 */
1377#define OMAP54XX_MODULEMODE_SHIFT 0
1378#define OMAP54XX_MODULEMODE_WIDTH 0x2
1379#define OMAP54XX_MODULEMODE_MASK (0x3 << 0)
1380
1381/* Used by CM_L4CFG_DYNAMICDEP */
1382#define OMAP54XX_MPU_DYNDEP_SHIFT 19
1383#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1
1384#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19)
1385
1386/* Used by CM_DSS_DSS_CLKCTRL */
1387#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
1388#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1
1389#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11)
1390
1391/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
1392#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8
1393#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1
1394#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8)
1395
1396/* Used by CM_DSS_DSS_CLKCTRL */
1397#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1398#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
1399#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
1400
1401/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
1402#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8
1403#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1
1404#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8)
1405
1406/* Used by CM_CAM_ISS_CLKCTRL */
1407#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8
1408#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1
1409#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1410
1411/*
1412 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1413 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1414 * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
1415 */
1416#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8
1417#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1
1418#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8)
1419
1420/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
1421#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8
1422#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1
1423#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
1424
1425/* Used by CM_DSS_DSS_CLKCTRL */
1426#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8
1427#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1
1428#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8)
1429
1430/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1431#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8
1432#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1
1433#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8)
1434
1435/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1436#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9
1437#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1
1438#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9)
1439
1440/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1441#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10
1442#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1
1443#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10)
1444
1445/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1446#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15
1447#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1
1448#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15)
1449
1450/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1451#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1452#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
1453#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1454
1455/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1456#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1457#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
1458#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1459
1460/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1461#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7
1462#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1
1463#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7)
1464
1465/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1466#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1467#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
1468#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1469
1470/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1471#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1472#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
1473#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1474
1475/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1476#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6
1477#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1
1478#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6)
1479
1480/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
1481#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8
1482#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1
1483#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8)
1484
1485/* Used by CM_L3INIT_SATA_CLKCTRL */
1486#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8
1487#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1
1488#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8)
1489
1490/* Used by CM_WKUPAON_SCRM_CLKCTRL */
1491#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8
1492#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1
1493#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
1494
1495/* Used by CM_WKUPAON_SCRM_CLKCTRL */
1496#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9
1497#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1
1498#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9)
1499
1500/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1501#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11
1502#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
1503#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11)
1504
1505/* Used by CM_DSS_DSS_CLKCTRL */
1506#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10
1507#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1
1508#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1509
1510/* Used by CM_MIPIEXT_LLI_CLKCTRL */
1511#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8
1512#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1
1513#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8)
1514
1515/* Used by CM_MIPIEXT_LLI_CLKCTRL */
1516#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9
1517#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1
1518#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9)
1519
1520/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1521#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1522#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
1523#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1524
1525/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1526#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1527#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
1528#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1529
1530/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1531#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1532#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
1533#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1534
1535/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1536#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1537#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
1538#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1539
1540/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1541#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1542#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
1543#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1544
1545/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1546#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1547#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
1548#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1549
1550/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
1551#define OMAP54XX_OUTPUT_SHIFT 0
1552#define OMAP54XX_OUTPUT_WIDTH 0x20
1553#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
1554
1555/* Used by CM_CLKSEL_ABE */
1556#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8
1557#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1
1558#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8)
1559
1560/* Used by CM_RESTORE_ST */
1561#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0
1562#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1
1563#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0)
1564
1565/* Used by CM_RESTORE_ST */
1566#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1
1567#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1
1568#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1)
1569
1570/* Used by CM_RESTORE_ST */
1571#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2
1572#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1
1573#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2)
1574
1575/* Used by CM_DYN_DEP_PRESCAL */
1576#define OMAP54XX_PRESCAL_SHIFT 0
1577#define OMAP54XX_PRESCAL_WIDTH 0x6
1578#define OMAP54XX_PRESCAL_MASK (0x3f << 0)
1579
1580/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1581#define OMAP54XX_R_RTL_SHIFT 11
1582#define OMAP54XX_R_RTL_WIDTH 0x5
1583#define OMAP54XX_R_RTL_MASK (0x1f << 11)
1584
1585/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
1586#define OMAP54XX_SAR_MODE_SHIFT 4
1587#define OMAP54XX_SAR_MODE_WIDTH 0x1
1588#define OMAP54XX_SAR_MODE_MASK (1 << 4)
1589
1590/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1591#define OMAP54XX_SCHEME_SHIFT 30
1592#define OMAP54XX_SCHEME_WIDTH 0x2
1593#define OMAP54XX_SCHEME_MASK (0x3 << 30)
1594
1595/* Used by CM_L4CFG_DYNAMICDEP */
1596#define OMAP54XX_SDMA_DYNDEP_SHIFT 11
1597#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1
1598#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11)
1599
1600/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1601#define OMAP54XX_SDMA_STATDEP_SHIFT 11
1602#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1
1603#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11)
1604
1605/* Used by CM_CORE_AON_DEBUG_CFG */
1606#define OMAP54XX_SEL0_SHIFT 0
1607#define OMAP54XX_SEL0_WIDTH 0x7
1608#define OMAP54XX_SEL0_MASK (0x7f << 0)
1609
1610/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
1611#define OMAP54XX_SEL0_0_7_SHIFT 0
1612#define OMAP54XX_SEL0_0_7_WIDTH 0x8
1613#define OMAP54XX_SEL0_0_7_MASK (0xff << 0)
1614
1615/* Used by CM_CORE_AON_DEBUG_CFG */
1616#define OMAP54XX_SEL1_SHIFT 8
1617#define OMAP54XX_SEL1_WIDTH 0x7
1618#define OMAP54XX_SEL1_MASK (0x7f << 8)
1619
1620/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
1621#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8
1622#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8
1623#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8)
1624
1625/* Used by CM_CORE_AON_DEBUG_CFG */
1626#define OMAP54XX_SEL2_SHIFT 16
1627#define OMAP54XX_SEL2_WIDTH 0x7
1628#define OMAP54XX_SEL2_MASK (0x7f << 16)
1629
1630/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
1631#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16
1632#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8
1633#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16)
1634
1635/* Used by CM_CORE_AON_DEBUG_CFG */
1636#define OMAP54XX_SEL3_SHIFT 24
1637#define OMAP54XX_SEL3_WIDTH 0x7
1638#define OMAP54XX_SEL3_MASK (0x7f << 24)
1639
1640/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
1641#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24
1642#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8
1643#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24)
1644
1645/* Used by CM_CLKSEL_ABE */
1646#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10
1647#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1
1648#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10)
1649
1650/*
1651 * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
1652 * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
1653 * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1654 * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
1655 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
1656 * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
1657 * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
1658 * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
1659 * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
1660 */
1661#define OMAP54XX_STBYST_SHIFT 18
1662#define OMAP54XX_STBYST_WIDTH 0x1
1663#define OMAP54XX_STBYST_MASK (1 << 18)
1664
1665/*
1666 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1667 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1668 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1669 */
1670#define OMAP54XX_ST_DPLL_CLK_SHIFT 0
1671#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1
1672#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0)
1673
1674/*
1675 * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
1676 * CM_CLKDCOLDO_DPLL_USB
1677 */
1678#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9
1679#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1
1680#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1681
1682/*
1683 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1684 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1685 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1686 */
1687#define OMAP54XX_ST_DPLL_INIT_SHIFT 4
1688#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1
1689#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4)
1690
1691/*
1692 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1693 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1694 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1695 */
1696#define OMAP54XX_ST_DPLL_MODE_SHIFT 1
1697#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3
1698#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1)
1699
1700/* Used by CM_CLKSEL_SYS */
1701#define OMAP54XX_SYS_CLKSEL_SHIFT 0
1702#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3
1703#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0)
1704
1705/*
1706 * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1707 * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
1708 * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
1709 * CM_MPU_DYNAMICDEP
1710 */
1711#define OMAP54XX_WINDOWSIZE_SHIFT 24
1712#define OMAP54XX_WINDOWSIZE_WIDTH 0x4
1713#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24)
1714
1715/* Used by CM_L3MAIN1_DYNAMICDEP */
1716#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15
1717#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1
1718#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15)
1719
1720/*
1721 * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
1722 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
1723 */
1724#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15
1725#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1
1726#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15)
1727
1728/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1729#define OMAP54XX_X_MAJOR_SHIFT 8
1730#define OMAP54XX_X_MAJOR_WIDTH 0x3
1731#define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
1732
1733/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1734#define OMAP54XX_Y_MINOR_SHIFT 0
1735#define OMAP54XX_Y_MINOR_WIDTH 0x6
1736#define OMAP54XX_Y_MINOR_MASK (0x3f << 0)
1737#endif
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 1bc00dc4876c..5ae8fe39d6ee 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,6 +25,8 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 26#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
27 27
28#include "cm_44xx_54xx.h"
29
28/* CM1 base address */ 30/* CM1 base address */
29#define OMAP4430_CM1_BASE 0x4a004000 31#define OMAP4430_CM1_BASE 0x4a004000
30 32
@@ -217,9 +219,4 @@
217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 219#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 220#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
219 221
220/* Function prototypes */
221extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
222extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
223extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
224
225#endif 222#endif
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
new file mode 100644
index 000000000000..90b3348e6672
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -0,0 +1,213 @@
1/*
2 * OMAP54xx CM1 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 *
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
24
25#include "cm_44xx_54xx.h"
26
27/* CM1 base address */
28#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
29
30#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
32
33/* CM_CORE_AON instances */
34#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
35#define OMAP54XX_CM_CORE_AON_CKGEN_INST 0x0100
36#define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300
37#define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400
38#define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500
39#define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00
40#define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00
41
42/* CM_CORE_AON clockdomain register offsets (from instance start) */
43#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
44#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000
45#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000
46
47/* CM_CORE_AON */
48
49/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
50#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000
51#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
52#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
53#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080
54#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084
55#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090
56#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094
57#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098
58#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c
59#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0
60#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4
61#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8
62#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac
63#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0
64#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4
65#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8
66#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc
67#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0
68#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4
69#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8
70#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc
71#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0
72#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4
73#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8
74#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc
75#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0
76#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4
77#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8
78#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec
79#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0
80
81/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
82#define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000
83#define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
84#define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008
85#define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
86#define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010
87#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
88#define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
89#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
90#define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
91#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
92#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
93#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
94#define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
95#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
96#define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
97#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
98#define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
99#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
100#define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
101#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
102#define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
103#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
104#define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
105#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
106#define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
107#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
108#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
109#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
110#define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
111#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
112#define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
113#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
114#define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
115#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
116#define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
117#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
118#define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
119#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
120#define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
121#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
122#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
123#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
124#define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
125#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
126#define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
127#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
128#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
129#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
130#define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
131#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
132#define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
133#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
134#define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
135#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
136#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
137#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
138#define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
139#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8
140#define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
141#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc
142#define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
143#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
144#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
145#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
146#define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
147#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
148#define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
149#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
150#define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
151#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
152#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
153#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
154#define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
155#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
156#define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
157#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
158#define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
159#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
160#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
161#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
162#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
163#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
164#define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180
165
166/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
167#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
168#define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004
169#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
170#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
171#define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
172#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
173#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
174
175/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
176#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000
177#define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004
178#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008
179#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020
180#define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
181
182/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
183#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000
184#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020
185#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
186#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028
187#define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
188#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030
189#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
190#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038
191#define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
192#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040
193#define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
194#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
195#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
196#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
197#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
198#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
199#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
200#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060
201#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
202#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
203#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
204#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
205#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
206#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
207#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
208#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
209#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
210#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088
211#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
212
213#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index b9de72da1a8e..ee5136d7cdda 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,6 +25,8 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 26#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
27 27
28#include "cm_44xx_54xx.h"
29
28/* CM2 base address */ 30/* CM2 base address */
29#define OMAP4430_CM2_BASE 0x4a008000 31#define OMAP4430_CM2_BASE 0x4a008000
30 32
@@ -449,9 +451,4 @@
449#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 451#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
450#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 452#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
451 453
452/* Function prototypes */
453extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
454extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
455extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
456
457#endif 454#endif
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
new file mode 100644
index 000000000000..2683231b299b
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -0,0 +1,389 @@
1/*
2 * OMAP54xx CM2 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
23
24#include "cm_44xx_54xx.h"
25
26/* CM2 base address */
27#define OMAP54XX_CM_CORE_BASE 0x4a008000
28
29#define OMAP54XX_CM_CORE_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
31
32/* CM_CORE instances */
33#define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
34#define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
35#define OMAP54XX_CM_CORE_COREAON_INST 0x0600
36#define OMAP54XX_CM_CORE_CORE_INST 0x0700
37#define OMAP54XX_CM_CORE_IVA_INST 0x1200
38#define OMAP54XX_CM_CORE_CAM_INST 0x1300
39#define OMAP54XX_CM_CORE_DSS_INST 0x1400
40#define OMAP54XX_CM_CORE_GPU_INST 0x1500
41#define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
42#define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700
43#define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00
44#define OMAP54XX_CM_CORE_INSTR_INST 0x1f00
45
46/* CM_CORE clockdomain register offsets (from instance start) */
47#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
48#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
49#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100
50#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200
51#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
52#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
53#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500
54#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
55#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
56#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800
57#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900
58#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80
59#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
60#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
61#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
62#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
63#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
64#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
65
66/* CM_CORE */
67
68/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
69#define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000
70#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
71#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
72#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080
73#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084
74
75/* CM_CORE.CKGEN_CM_CORE register offsets */
76#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
77#define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004)
78#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
79#define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040)
80#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044
81#define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044)
82#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
83#define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048)
84#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
85#define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c)
86#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
87#define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050)
88#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
89#define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054)
90#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058
91#define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058)
92#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c
93#define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c)
94#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060
95#define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060)
96#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064
97#define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064)
98#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
99#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
100#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
101#define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080)
102#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084
103#define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084)
104#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
105#define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088)
106#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
107#define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c)
108#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
109#define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090)
110#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
111#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
112#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
113#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4)
114#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0
115#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0)
116#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4
117#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4)
118#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8
119#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8)
120#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc
121#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc)
122#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0
123#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0)
124#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8
125#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec
126#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4
127#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4)
128#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100
129#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100)
130#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104
131#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104)
132#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108
133#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108)
134#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c
135#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c)
136#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110
137#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110)
138#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128
139#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c
140#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134
141#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134)
142
143/* CM_CORE.COREAON_CM_CORE register offsets */
144#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
145#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
146#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028)
147#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030
148#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030)
149#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
150#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038)
151#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040
152#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040)
153#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
154#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050)
155
156/* CM_CORE.CORE_CM_CORE register offsets */
157#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
158#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
159#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
160#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020)
161#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100
162#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108
163#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120
164#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120)
165#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128
166#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128)
167#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
168#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130)
169#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200
170#define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204
171#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208
172#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220
173#define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220)
174#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
175#define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304
176#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
177#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
178#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320)
179#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
180#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
181#define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420)
182#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
183#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428)
184#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
185#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430)
186#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
187#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438)
188#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
189#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440)
190#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500
191#define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504
192#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508
193#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520
194#define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520)
195#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528
196#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528)
197#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530
198#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530)
199#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
200#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
201#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
202#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620)
203#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
204#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628)
205#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
206#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630)
207#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
208#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638)
209#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
210#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640)
211#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
212#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720
213#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720)
214#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
215#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728)
216#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
217#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740)
218#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
219#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748)
220#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
221#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750)
222#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800
223#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804
224#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808
225#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820
226#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820)
227#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828
228#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828)
229#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830
230#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830)
231#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900
232#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908
233#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928
234#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928)
235#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930
236#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930)
237#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938
238#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938)
239#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940
240#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940)
241#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948
242#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948)
243#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950
244#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950)
245#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958
246#define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958)
247#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960
248#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960)
249#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968
250#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968)
251#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970
252#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970)
253#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978
254#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978)
255#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980
256#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980)
257#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988
258#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988)
259#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0
260#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0)
261#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8
262#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8)
263#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0
264#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0)
265#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8
266#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8)
267#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0
268#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0)
269#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0
270#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0)
271#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8
272#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8)
273#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00
274#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00)
275#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08
276#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08)
277#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10
278#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10)
279#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18
280#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18)
281#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20
282#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20)
283#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28
284#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28)
285#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40
286#define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40)
287#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48
288#define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48)
289#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50
290#define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50)
291#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58
292#define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58)
293#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60
294#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60)
295#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68
296#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68)
297#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70
298#define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70)
299#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78
300#define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78)
301#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80
302#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84
303#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88
304#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0
305#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0)
306#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8
307#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8)
308#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0
309#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0)
310#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8
311#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8)
312#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0
313#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0)
314#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8
315#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8)
316#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8
317#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8)
318
319/* CM_CORE.IVA_CM_CORE register offsets */
320#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
321#define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004
322#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
323#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
324#define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020)
325#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
326#define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028)
327
328/* CM_CORE.CAM_CM_CORE register offsets */
329#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
330#define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004
331#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008
332#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
333#define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020)
334#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
335#define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028)
336#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030
337#define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030)
338
339/* CM_CORE.DSS_CM_CORE register offsets */
340#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
341#define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004
342#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
343#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
344#define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020)
345#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
346#define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030)
347
348/* CM_CORE.GPU_CM_CORE register offsets */
349#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
350#define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004
351#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
352#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
353#define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020)
354
355/* CM_CORE.L3INIT_CM_CORE register offsets */
356#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
357#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
358#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
359#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
360#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028)
361#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
362#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030)
363#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
364#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038)
365#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040
366#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040)
367#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048
368#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048)
369#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058
370#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058)
371#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068
372#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068)
373#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
374#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078)
375#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
376#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088)
377#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
378#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0)
379#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
380#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8)
381#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0
382#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0)
383
384/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
385#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
386#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
387#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
388
389#endif
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 64f4bafe7bd9..9d1f4fcdebbb 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
383extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); 383extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
384extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); 384extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
385 385
386#ifdef CONFIG_SOC_AM33XX 386#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
387extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, 387extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
388 u16 clkctrl_offs); 388 u16 clkctrl_offs);
389extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, 389extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
new file mode 100644
index 000000000000..cbb211690321
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_44xx_54xx.h
@@ -0,0 +1,36 @@
1/*
2 * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
25
26/* CM1 Function prototypes */
27extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
28extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
29extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
30
31/* CM2 Function prototypes */
32extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
33extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
34extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
35
36#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2459e1..72cab3f4f16d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -96,6 +96,7 @@ void am33xx_init_early(void);
96void am35xx_init_early(void); 96void am35xx_init_early(void);
97void ti81xx_init_early(void); 97void ti81xx_init_early(void);
98void am33xx_init_early(void); 98void am33xx_init_early(void);
99void am43xx_init_early(void);
99void omap4430_init_early(void); 100void omap4430_init_early(void);
100void omap5_init_early(void); 101void omap5_init_early(void);
101void omap3_init_late(void); /* Do not use this one */ 102void omap3_init_late(void); /* Do not use this one */
@@ -237,8 +238,8 @@ extern void omap_do_wfi(void);
237 238
238#ifdef CONFIG_SMP 239#ifdef CONFIG_SMP
239/* Needed for secondary core boot */ 240/* Needed for secondary core boot */
240extern void omap_secondary_startup(void); 241extern void omap4_secondary_startup(void);
241extern void omap_secondary_startup_4460(void); 242extern void omap4460_secondary_startup(void);
242extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); 243extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
243extern void omap_auxcoreboot_addr(u32 cpu_addr); 244extern void omap_auxcoreboot_addr(u32 cpu_addr);
244extern u32 omap_read_auxcoreboot0(void); 245extern u32 omap_read_auxcoreboot0(void);
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c328128a0a..35d17a6ec06b 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,14 @@
358#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 358#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
359#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) 359#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
360 360
361/* AM33XX PWMSS Control register */
362#define AM33XX_PWMSS_TBCLK_CLKCTRL 0x664
363
364/* AM33XX PWMSS Control bitfields */
365#define AM33XX_PWMSS0_TBCLKEN_SHIFT 0
366#define AM33XX_PWMSS1_TBCLKEN_SHIFT 1
367#define AM33XX_PWMSS2_TBCLKEN_SHIFT 2
368
361/* CONTROL OMAP STATUS register to identify OMAP3 features */ 369/* CONTROL OMAP STATUS register to identify OMAP3 features */
362#define OMAP3_CONTROL_OMAP_STATUS 0x044c 370#define OMAP3_CONTROL_OMAP_STATUS 0x044c
363 371
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41d4749..74f71abcd50e 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,7 +55,7 @@ int omap_type(void)
55 55
56 if (cpu_is_omap24xx()) { 56 if (cpu_is_omap24xx()) {
57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
58 } else if (soc_is_am33xx()) { 58 } else if (soc_is_am33xx() || soc_is_am43xx()) {
59 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 59 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
60 } else if (cpu_is_omap34xx()) { 60 } else if (cpu_is_omap34xx()) {
61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
@@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void)
209 cpu_name = "TI816X"; 209 cpu_name = "TI816X";
210 } else if (soc_is_am335x()) { 210 } else if (soc_is_am335x()) {
211 cpu_name = "AM335X"; 211 cpu_name = "AM335X";
212 } else if (soc_is_am437x()) {
213 cpu_name = "AM437x";
212 } else if (cpu_is_ti814x()) { 214 } else if (cpu_is_ti814x()) {
213 cpu_name = "TI814X"; 215 cpu_name = "TI814X";
214 } else if (omap3_has_iva() && omap3_has_sgx()) { 216 } else if (omap3_has_iva() && omap3_has_sgx()) {
@@ -430,6 +432,10 @@ void __init omap3xxx_check_revision(void)
430 break; 432 break;
431 } 433 }
432 break; 434 break;
435 case 0xb98c:
436 omap_revision = AM437X_REV_ES1_0;
437 cpu_rev = "1.0";
438 break;
433 case 0xb8f2: 439 case 0xb8f2:
434 switch (rev) { 440 switch (rev) {
435 case 0: 441 case 0:
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99e9e57..8dec09a05ce7 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -202,7 +202,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = {
202}; 202};
203#endif 203#endif
204 204
205#ifdef CONFIG_SOC_AM33XX 205#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
206static struct map_desc omapam33xx_io_desc[] __initdata = { 206static struct map_desc omapam33xx_io_desc[] __initdata = {
207 { 207 {
208 .virtual = L4_34XX_VIRT, 208 .virtual = L4_34XX_VIRT,
@@ -318,7 +318,7 @@ void __init ti81xx_map_io(void)
318} 318}
319#endif 319#endif
320 320
321#ifdef CONFIG_SOC_AM33XX 321#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
322void __init am33xx_map_io(void) 322void __init am33xx_map_io(void)
323{ 323{
324 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 324 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
@@ -586,6 +586,19 @@ void __init am33xx_init_early(void)
586} 586}
587#endif 587#endif
588 588
589#ifdef CONFIG_SOC_AM43XX
590void __init am43xx_init_early(void)
591{
592 omap2_set_globals_tap(AM335X_CLASS,
593 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
594 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
595 NULL);
596 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
597 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
598 omap3xxx_check_revision();
599}
600#endif
601
589#ifdef CONFIG_ARCH_OMAP4 602#ifdef CONFIG_ARCH_OMAP4
590void __init omap4430_init_early(void) 603void __init omap4430_init_early(void)
591{ 604{
@@ -631,7 +644,13 @@ void __init omap5_init_early(void)
631 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 644 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
632 omap_prm_base_init(); 645 omap_prm_base_init();
633 omap_cm_base_init(); 646 omap_cm_base_init();
647 omap44xx_prm_init();
634 omap5xxx_check_revision(); 648 omap5xxx_check_revision();
649 omap54xx_voltagedomains_init();
650 omap54xx_powerdomains_init();
651 omap54xx_clockdomains_init();
652 omap54xx_hwmod_init();
653 omap_hwmod_init_postsetup();
635} 654}
636#endif 655#endif
637 656
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 0ea09faf327b..4ea308114165 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -49,7 +49,7 @@ END(omap5_secondary_startup)
49 * The primary core will update this flag using a hardware 49 * The primary core will update this flag using a hardware
50 * register AuxCoreBoot0. 50 * register AuxCoreBoot0.
51 */ 51 */
52ENTRY(omap_secondary_startup) 52ENTRY(omap4_secondary_startup)
53hold: ldr r12,=0x103 53hold: ldr r12,=0x103
54 dsb 54 dsb
55 smc #0 @ read from AuxCoreBoot0 55 smc #0 @ read from AuxCoreBoot0
@@ -64,9 +64,9 @@ hold: ldr r12,=0x103
64 * should now contain the SVC stack for this core 64 * should now contain the SVC stack for this core
65 */ 65 */
66 b secondary_startup 66 b secondary_startup
67ENDPROC(omap_secondary_startup) 67ENDPROC(omap4_secondary_startup)
68 68
69ENTRY(omap_secondary_startup_4460) 69ENTRY(omap4460_secondary_startup)
70hold_2: ldr r12,=0x103 70hold_2: ldr r12,=0x103
71 dsb 71 dsb
72 smc #0 @ read from AuxCoreBoot0 72 smc #0 @ read from AuxCoreBoot0
@@ -101,4 +101,4 @@ hold_2: ldr r12,=0x103
101 * should now contain the SVC stack for this core 101 * should now contain the SVC stack for this core
102 */ 102 */
103 b secondary_startup 103 b secondary_startup
104ENDPROC(omap_secondary_startup_4460) 104ENDPROC(omap4460_secondary_startup)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index e80327b6c81f..f993a4188701 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -71,10 +71,43 @@ struct omap4_cpu_pm_info {
71 void (*secondary_startup)(void); 71 void (*secondary_startup)(void);
72}; 72};
73 73
74/**
75 * struct cpu_pm_ops - CPU pm operations
76 * @finish_suspend: CPU suspend finisher function pointer
77 * @resume: CPU resume function pointer
78 * @scu_prepare: CPU Snoop Control program function pointer
79 *
80 * Structure holds functions pointer for CPU low power operations like
81 * suspend, resume and scu programming.
82 */
83struct cpu_pm_ops {
84 int (*finish_suspend)(unsigned long cpu_state);
85 void (*resume)(void);
86 void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
87};
88
74static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); 89static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
75static struct powerdomain *mpuss_pd; 90static struct powerdomain *mpuss_pd;
76static void __iomem *sar_base; 91static void __iomem *sar_base;
77 92
93static int default_finish_suspend(unsigned long cpu_state)
94{
95 omap_do_wfi();
96 return 0;
97}
98
99static void dummy_cpu_resume(void)
100{}
101
102static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
103{}
104
105struct cpu_pm_ops omap_pm_ops = {
106 .finish_suspend = default_finish_suspend,
107 .resume = dummy_cpu_resume,
108 .scu_prepare = dummy_scu_prepare,
109};
110
78/* 111/*
79 * Program the wakeup routine address for the CPU0 and CPU1 112 * Program the wakeup routine address for the CPU0 and CPU1
80 * used for OFF or DORMANT wakeup. 113 * used for OFF or DORMANT wakeup.
@@ -158,11 +191,12 @@ static void save_l2x0_context(void)
158{ 191{
159 u32 val; 192 u32 val;
160 void __iomem *l2x0_base = omap4_get_l2cache_base(); 193 void __iomem *l2x0_base = omap4_get_l2cache_base();
161 194 if (l2x0_base) {
162 val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); 195 val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
163 __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); 196 __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
164 val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); 197 val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
165 __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); 198 __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
199 }
166} 200}
167#else 201#else
168static void save_l2x0_context(void) 202static void save_l2x0_context(void)
@@ -225,14 +259,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
225 259
226 cpu_clear_prev_logic_pwrst(cpu); 260 cpu_clear_prev_logic_pwrst(cpu);
227 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 261 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
228 set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); 262 set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
229 scu_pwrst_prepare(cpu, power_state); 263 omap_pm_ops.scu_prepare(cpu, power_state);
230 l2x0_pwrst_prepare(cpu, save_state); 264 l2x0_pwrst_prepare(cpu, save_state);
231 265
232 /* 266 /*
233 * Call low level function with targeted low power state. 267 * Call low level function with targeted low power state.
234 */ 268 */
235 cpu_suspend(save_state, omap4_finish_suspend); 269 if (save_state)
270 cpu_suspend(save_state, omap_pm_ops.finish_suspend);
271 else
272 omap_pm_ops.finish_suspend(save_state);
236 273
237 /* 274 /*
238 * Restore the CPUx power state to ON otherwise CPUx 275 * Restore the CPUx power state to ON otherwise CPUx
@@ -268,14 +305,14 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
268 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 305 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
269 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 306 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
270 set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); 307 set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
271 scu_pwrst_prepare(cpu, power_state); 308 omap_pm_ops.scu_prepare(cpu, power_state);
272 309
273 /* 310 /*
274 * CPU never retuns back if targeted power state is OFF mode. 311 * CPU never retuns back if targeted power state is OFF mode.
275 * CPU ONLINE follows normal CPU ONLINE ptah via 312 * CPU ONLINE follows normal CPU ONLINE ptah via
276 * omap_secondary_startup(). 313 * omap4_secondary_startup().
277 */ 314 */
278 omap4_finish_suspend(cpu_state); 315 omap_pm_ops.finish_suspend(cpu_state);
279 316
280 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 317 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
281 return 0; 318 return 0;
@@ -319,9 +356,9 @@ int __init omap4_mpuss_init(void)
319 pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; 356 pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
320 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; 357 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
321 if (cpu_is_omap446x()) 358 if (cpu_is_omap446x())
322 pm_info->secondary_startup = omap_secondary_startup_4460; 359 pm_info->secondary_startup = omap4460_secondary_startup;
323 else 360 else
324 pm_info->secondary_startup = omap_secondary_startup; 361 pm_info->secondary_startup = omap4_secondary_startup;
325 362
326 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); 363 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
327 if (!pm_info->pwrdm) { 364 if (!pm_info->pwrdm) {
@@ -352,6 +389,12 @@ int __init omap4_mpuss_init(void)
352 389
353 save_l2x0_context(); 390 save_l2x0_context();
354 391
392 if (cpu_is_omap44xx()) {
393 omap_pm_ops.finish_suspend = omap4_finish_suspend;
394 omap_pm_ops.resume = omap4_cpu_resume;
395 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
396 }
397
355 return 0; 398 return 0;
356} 399}
357 400
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 2a551f997aea..98a11463a843 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -87,7 +87,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
87 87
88 /* 88 /*
89 * Update the AuxCoreBoot0 with boot state for secondary core. 89 * Update the AuxCoreBoot0 with boot state for secondary core.
90 * omap_secondary_startup() routine will hold the secondary core till 90 * omap4_secondary_startup() routine will hold the secondary core till
91 * the AuxCoreBoot1 register is updated with cpu state 91 * the AuxCoreBoot1 register is updated with cpu state
92 * A barrier is added to ensure that write buffer is drained 92 * A barrier is added to ensure that write buffer is drained
93 */ 93 */
@@ -200,7 +200,7 @@ static void __init omap4_smp_init_cpus(void)
200 200
201static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) 201static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
202{ 202{
203 void *startup_addr = omap_secondary_startup; 203 void *startup_addr = omap4_secondary_startup;
204 void __iomem *base = omap_get_wakeupgen_base(); 204 void __iomem *base = omap_get_wakeupgen_base();
205 205
206 /* 206 /*
@@ -211,7 +211,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
211 scu_enable(scu_base); 211 scu_enable(scu_base);
212 212
213 if (cpu_is_omap446x()) { 213 if (cpu_is_omap446x()) {
214 startup_addr = omap_secondary_startup_4460; 214 startup_addr = omap4460_secondary_startup;
215 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; 215 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
216 } 216 }
217 217
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ffaf45e..38cd3a69cff3 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -339,19 +339,3 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
339 return 0; 339 return 0;
340} 340}
341#endif 341#endif
342
343/**
344 * omap44xx_restart - trigger a software restart of the SoC
345 * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
346 * @cmd: passed from the userspace program rebooting the system (if provided)
347 *
348 * Resets the SoC. For @cmd, see the 'reboot' syscall in
349 * kernel/sys.c. No return value.
350 */
351void omap44xx_restart(char mode, const char *cmd)
352{
353 /* XXX Should save 'cmd' into scratchpad for use after reboot */
354 omap4_prminst_global_warm_sw_reset(); /* never returns */
355 while (1);
356}
357
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
new file mode 100644
index 000000000000..f90e02e11898
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -0,0 +1,27 @@
1/*
2 * omap4-restart.c - Common to OMAP4 and OMAP5
3 *
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/types.h>
11#include "prminst44xx.h"
12
13/**
14 * omap44xx_restart - trigger a software restart of the SoC
15 * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
16 * @cmd: passed from the userspace program rebooting the system (if provided)
17 *
18 * Resets the SoC. For @cmd, see the 'reboot' syscall in
19 * kernel/sys.c. No return value.
20 */
21void omap44xx_restart(char mode, const char *cmd)
22{
23 /* XXX Should save 'cmd' into scratchpad for use after reboot */
24 omap4_prminst_global_warm_sw_reset(); /* never returns */
25 while (1)
26 ;
27}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f58ac9b..aab33fd814c0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void);
699extern int omap2430_hwmod_init(void); 699extern int omap2430_hwmod_init(void);
700extern int omap3xxx_hwmod_init(void); 700extern int omap3xxx_hwmod_init(void);
701extern int omap44xx_hwmod_init(void); 701extern int omap44xx_hwmod_init(void);
702extern int omap54xx_hwmod_init(void);
702extern int am33xx_hwmod_init(void); 703extern int am33xx_hwmod_init(void);
703 704
704extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 705extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 075f7cc51026..0c9a183131e2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -329,7 +329,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
329}; 329};
330 330
331static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { 331static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
332 { .name = "gfx", .rst_shift = 0 }, 332 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
333}; 333};
334 334
335static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = { 335static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
@@ -347,6 +347,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
347 .omap4 = { 347 .omap4 = {
348 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, 348 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
349 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, 349 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
350 .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
350 .modulemode = MODULEMODE_SWCTRL, 351 .modulemode = MODULEMODE_SWCTRL,
351 }, 352 },
352 }, 353 },
@@ -2007,6 +2008,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
2007 }, 2008 },
2008}; 2009};
2009 2010
2011/* uart2 */
2012static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
2013 { .name = "tx", .dma_req = 28, },
2014 { .name = "rx", .dma_req = 29, },
2015 { .dma_req = -1 }
2016};
2017
2010static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { 2018static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2011 { .irq = 73 + OMAP_INTC_START, }, 2019 { .irq = 73 + OMAP_INTC_START, },
2012 { .irq = -1 }, 2020 { .irq = -1 },
@@ -2018,7 +2026,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
2018 .clkdm_name = "l4ls_clkdm", 2026 .clkdm_name = "l4ls_clkdm",
2019 .flags = HWMOD_SWSUP_SIDLE_ACT, 2027 .flags = HWMOD_SWSUP_SIDLE_ACT,
2020 .mpu_irqs = am33xx_uart2_irqs, 2028 .mpu_irqs = am33xx_uart2_irqs,
2021 .sdma_reqs = uart1_edma_reqs, 2029 .sdma_reqs = uart2_edma_reqs,
2022 .main_clk = "dpll_per_m2_div4_ck", 2030 .main_clk = "dpll_per_m2_div4_ck",
2023 .prcm = { 2031 .prcm = {
2024 .omap4 = { 2032 .omap4 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
new file mode 100644
index 000000000000..f37ae96b70a1
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -0,0 +1,2150 @@
1/*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_54xx.h"
33#include "cm2_54xx.h"
34#include "prm54xx.h"
35#include "prm-regbits-54xx.h"
36#include "i2c.h"
37#include "mmc.h"
38#include "wd_timer.h"
39
40/* Base offset for all OMAP5 interrupts external to MPUSS */
41#define OMAP54XX_IRQ_GIC_START 32
42
43/* Base offset for all OMAP5 dma requests */
44#define OMAP54XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
51/*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod omap54xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &omap54xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
72/*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
75 */
76static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod omap54xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &omap54xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &omap54xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &omap54xx_l3_hwmod_class,
111 .clkdm_name = "l3main2_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l3_main_3 */
121static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
122 .name = "l3_main_3",
123 .class = &omap54xx_l3_hwmod_class,
124 .clkdm_name = "l3instr_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
128 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
129 .modulemode = MODULEMODE_HWCTRL,
130 },
131 },
132};
133
134/*
135 * 'l4' class
136 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
137 */
138static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
139 .name = "l4",
140};
141
142/* l4_abe */
143static struct omap_hwmod omap54xx_l4_abe_hwmod = {
144 .name = "l4_abe",
145 .class = &omap54xx_l4_hwmod_class,
146 .clkdm_name = "abe_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_cfg */
156static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
157 .name = "l4_cfg",
158 .class = &omap54xx_l4_hwmod_class,
159 .clkdm_name = "l4cfg_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
163 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
164 },
165 },
166};
167
168/* l4_per */
169static struct omap_hwmod omap54xx_l4_per_hwmod = {
170 .name = "l4_per",
171 .class = &omap54xx_l4_hwmod_class,
172 .clkdm_name = "l4per_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
176 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &omap54xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'mpu_bus' class
196 * instance(s): mpu_private
197 */
198static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
199 .name = "mpu_bus",
200};
201
202/* mpu_private */
203static struct omap_hwmod omap54xx_mpu_private_hwmod = {
204 .name = "mpu_private",
205 .class = &omap54xx_mpu_bus_hwmod_class,
206 .clkdm_name = "mpu_clkdm",
207 .prcm = {
208 .omap4 = {
209 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
210 },
211 },
212};
213
214/*
215 * 'counter' class
216 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
217 */
218
219static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
220 .rev_offs = 0x0000,
221 .sysc_offs = 0x0010,
222 .sysc_flags = SYSC_HAS_SIDLEMODE,
223 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
224 .sysc_fields = &omap_hwmod_sysc_type1,
225};
226
227static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
228 .name = "counter",
229 .sysc = &omap54xx_counter_sysc,
230};
231
232/* counter_32k */
233static struct omap_hwmod omap54xx_counter_32k_hwmod = {
234 .name = "counter_32k",
235 .class = &omap54xx_counter_hwmod_class,
236 .clkdm_name = "wkupaon_clkdm",
237 .flags = HWMOD_SWSUP_SIDLE,
238 .main_clk = "wkupaon_iclk_mux",
239 .prcm = {
240 .omap4 = {
241 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
242 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
243 },
244 },
245};
246
247/*
248 * 'dma' class
249 * dma controller for data exchange between memory to memory (i.e. internal or
250 * external memory) and gp peripherals to memory or memory to gp peripherals
251 */
252
253static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
254 .rev_offs = 0x0000,
255 .sysc_offs = 0x002c,
256 .syss_offs = 0x0028,
257 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
258 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
259 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
260 SYSS_HAS_RESET_STATUS),
261 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
262 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
263 .sysc_fields = &omap_hwmod_sysc_type1,
264};
265
266static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
267 .name = "dma",
268 .sysc = &omap54xx_dma_sysc,
269};
270
271/* dma dev_attr */
272static struct omap_dma_dev_attr dma_dev_attr = {
273 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
274 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
275 .lch_count = 32,
276};
277
278/* dma_system */
279static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
280 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
281 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
282 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
283 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
284 { .irq = -1 }
285};
286
287static struct omap_hwmod omap54xx_dma_system_hwmod = {
288 .name = "dma_system",
289 .class = &omap54xx_dma_hwmod_class,
290 .clkdm_name = "dma_clkdm",
291 .mpu_irqs = omap54xx_dma_system_irqs,
292 .main_clk = "l3_iclk_div",
293 .prcm = {
294 .omap4 = {
295 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
296 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
297 },
298 },
299 .dev_attr = &dma_dev_attr,
300};
301
302/*
303 * 'dmic' class
304 * digital microphone controller
305 */
306
307static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
308 .rev_offs = 0x0000,
309 .sysc_offs = 0x0010,
310 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
311 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
312 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
313 SIDLE_SMART_WKUP),
314 .sysc_fields = &omap_hwmod_sysc_type2,
315};
316
317static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
318 .name = "dmic",
319 .sysc = &omap54xx_dmic_sysc,
320};
321
322/* dmic */
323static struct omap_hwmod omap54xx_dmic_hwmod = {
324 .name = "dmic",
325 .class = &omap54xx_dmic_hwmod_class,
326 .clkdm_name = "abe_clkdm",
327 .main_clk = "dmic_gfclk",
328 .prcm = {
329 .omap4 = {
330 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
331 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
332 .modulemode = MODULEMODE_SWCTRL,
333 },
334 },
335};
336
337/*
338 * 'emif' class
339 * external memory interface no1 (wrapper)
340 */
341
342static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
343 .rev_offs = 0x0000,
344};
345
346static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
347 .name = "emif",
348 .sysc = &omap54xx_emif_sysc,
349};
350
351/* emif1 */
352static struct omap_hwmod omap54xx_emif1_hwmod = {
353 .name = "emif1",
354 .class = &omap54xx_emif_hwmod_class,
355 .clkdm_name = "emif_clkdm",
356 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
357 .main_clk = "dpll_core_h11x2_ck",
358 .prcm = {
359 .omap4 = {
360 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
361 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
362 .modulemode = MODULEMODE_HWCTRL,
363 },
364 },
365};
366
367/* emif2 */
368static struct omap_hwmod omap54xx_emif2_hwmod = {
369 .name = "emif2",
370 .class = &omap54xx_emif_hwmod_class,
371 .clkdm_name = "emif_clkdm",
372 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
373 .main_clk = "dpll_core_h11x2_ck",
374 .prcm = {
375 .omap4 = {
376 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
377 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
378 .modulemode = MODULEMODE_HWCTRL,
379 },
380 },
381};
382
383/*
384 * 'gpio' class
385 * general purpose io module
386 */
387
388static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
389 .rev_offs = 0x0000,
390 .sysc_offs = 0x0010,
391 .syss_offs = 0x0114,
392 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
393 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
394 SYSS_HAS_RESET_STATUS),
395 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
396 SIDLE_SMART_WKUP),
397 .sysc_fields = &omap_hwmod_sysc_type1,
398};
399
400static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
401 .name = "gpio",
402 .sysc = &omap54xx_gpio_sysc,
403 .rev = 2,
404};
405
406/* gpio dev_attr */
407static struct omap_gpio_dev_attr gpio_dev_attr = {
408 .bank_width = 32,
409 .dbck_flag = true,
410};
411
412/* gpio1 */
413static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
414 { .role = "dbclk", .clk = "gpio1_dbclk" },
415};
416
417static struct omap_hwmod omap54xx_gpio1_hwmod = {
418 .name = "gpio1",
419 .class = &omap54xx_gpio_hwmod_class,
420 .clkdm_name = "wkupaon_clkdm",
421 .main_clk = "wkupaon_iclk_mux",
422 .prcm = {
423 .omap4 = {
424 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
425 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
426 .modulemode = MODULEMODE_HWCTRL,
427 },
428 },
429 .opt_clks = gpio1_opt_clks,
430 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
431 .dev_attr = &gpio_dev_attr,
432};
433
434/* gpio2 */
435static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
436 { .role = "dbclk", .clk = "gpio2_dbclk" },
437};
438
439static struct omap_hwmod omap54xx_gpio2_hwmod = {
440 .name = "gpio2",
441 .class = &omap54xx_gpio_hwmod_class,
442 .clkdm_name = "l4per_clkdm",
443 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
444 .main_clk = "l4_root_clk_div",
445 .prcm = {
446 .omap4 = {
447 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
448 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
449 .modulemode = MODULEMODE_HWCTRL,
450 },
451 },
452 .opt_clks = gpio2_opt_clks,
453 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
454 .dev_attr = &gpio_dev_attr,
455};
456
457/* gpio3 */
458static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
459 { .role = "dbclk", .clk = "gpio3_dbclk" },
460};
461
462static struct omap_hwmod omap54xx_gpio3_hwmod = {
463 .name = "gpio3",
464 .class = &omap54xx_gpio_hwmod_class,
465 .clkdm_name = "l4per_clkdm",
466 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
467 .main_clk = "l4_root_clk_div",
468 .prcm = {
469 .omap4 = {
470 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
471 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
472 .modulemode = MODULEMODE_HWCTRL,
473 },
474 },
475 .opt_clks = gpio3_opt_clks,
476 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
477 .dev_attr = &gpio_dev_attr,
478};
479
480/* gpio4 */
481static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
482 { .role = "dbclk", .clk = "gpio4_dbclk" },
483};
484
485static struct omap_hwmod omap54xx_gpio4_hwmod = {
486 .name = "gpio4",
487 .class = &omap54xx_gpio_hwmod_class,
488 .clkdm_name = "l4per_clkdm",
489 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
490 .main_clk = "l4_root_clk_div",
491 .prcm = {
492 .omap4 = {
493 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
494 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
495 .modulemode = MODULEMODE_HWCTRL,
496 },
497 },
498 .opt_clks = gpio4_opt_clks,
499 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
500 .dev_attr = &gpio_dev_attr,
501};
502
503/* gpio5 */
504static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
505 { .role = "dbclk", .clk = "gpio5_dbclk" },
506};
507
508static struct omap_hwmod omap54xx_gpio5_hwmod = {
509 .name = "gpio5",
510 .class = &omap54xx_gpio_hwmod_class,
511 .clkdm_name = "l4per_clkdm",
512 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
513 .main_clk = "l4_root_clk_div",
514 .prcm = {
515 .omap4 = {
516 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
517 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
518 .modulemode = MODULEMODE_HWCTRL,
519 },
520 },
521 .opt_clks = gpio5_opt_clks,
522 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
523 .dev_attr = &gpio_dev_attr,
524};
525
526/* gpio6 */
527static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
528 { .role = "dbclk", .clk = "gpio6_dbclk" },
529};
530
531static struct omap_hwmod omap54xx_gpio6_hwmod = {
532 .name = "gpio6",
533 .class = &omap54xx_gpio_hwmod_class,
534 .clkdm_name = "l4per_clkdm",
535 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
536 .main_clk = "l4_root_clk_div",
537 .prcm = {
538 .omap4 = {
539 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
540 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
541 .modulemode = MODULEMODE_HWCTRL,
542 },
543 },
544 .opt_clks = gpio6_opt_clks,
545 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
546 .dev_attr = &gpio_dev_attr,
547};
548
549/* gpio7 */
550static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
551 { .role = "dbclk", .clk = "gpio7_dbclk" },
552};
553
554static struct omap_hwmod omap54xx_gpio7_hwmod = {
555 .name = "gpio7",
556 .class = &omap54xx_gpio_hwmod_class,
557 .clkdm_name = "l4per_clkdm",
558 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
559 .main_clk = "l4_root_clk_div",
560 .prcm = {
561 .omap4 = {
562 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
563 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
564 .modulemode = MODULEMODE_HWCTRL,
565 },
566 },
567 .opt_clks = gpio7_opt_clks,
568 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
569 .dev_attr = &gpio_dev_attr,
570};
571
572/* gpio8 */
573static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
574 { .role = "dbclk", .clk = "gpio8_dbclk" },
575};
576
577static struct omap_hwmod omap54xx_gpio8_hwmod = {
578 .name = "gpio8",
579 .class = &omap54xx_gpio_hwmod_class,
580 .clkdm_name = "l4per_clkdm",
581 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
582 .main_clk = "l4_root_clk_div",
583 .prcm = {
584 .omap4 = {
585 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
586 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
587 .modulemode = MODULEMODE_HWCTRL,
588 },
589 },
590 .opt_clks = gpio8_opt_clks,
591 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
592 .dev_attr = &gpio_dev_attr,
593};
594
595/*
596 * 'i2c' class
597 * multimaster high-speed i2c controller
598 */
599
600static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
601 .sysc_offs = 0x0010,
602 .syss_offs = 0x0090,
603 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
604 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
605 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
606 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
607 SIDLE_SMART_WKUP),
608 .clockact = CLOCKACT_TEST_ICLK,
609 .sysc_fields = &omap_hwmod_sysc_type1,
610};
611
612static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
613 .name = "i2c",
614 .sysc = &omap54xx_i2c_sysc,
615 .reset = &omap_i2c_reset,
616 .rev = OMAP_I2C_IP_VERSION_2,
617};
618
619/* i2c dev_attr */
620static struct omap_i2c_dev_attr i2c_dev_attr = {
621 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
622};
623
624/* i2c1 */
625static struct omap_hwmod omap54xx_i2c1_hwmod = {
626 .name = "i2c1",
627 .class = &omap54xx_i2c_hwmod_class,
628 .clkdm_name = "l4per_clkdm",
629 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
630 .main_clk = "func_96m_fclk",
631 .prcm = {
632 .omap4 = {
633 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
634 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
635 .modulemode = MODULEMODE_SWCTRL,
636 },
637 },
638 .dev_attr = &i2c_dev_attr,
639};
640
641/* i2c2 */
642static struct omap_hwmod omap54xx_i2c2_hwmod = {
643 .name = "i2c2",
644 .class = &omap54xx_i2c_hwmod_class,
645 .clkdm_name = "l4per_clkdm",
646 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
647 .main_clk = "func_96m_fclk",
648 .prcm = {
649 .omap4 = {
650 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
651 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
652 .modulemode = MODULEMODE_SWCTRL,
653 },
654 },
655 .dev_attr = &i2c_dev_attr,
656};
657
658/* i2c3 */
659static struct omap_hwmod omap54xx_i2c3_hwmod = {
660 .name = "i2c3",
661 .class = &omap54xx_i2c_hwmod_class,
662 .clkdm_name = "l4per_clkdm",
663 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
664 .main_clk = "func_96m_fclk",
665 .prcm = {
666 .omap4 = {
667 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
668 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
669 .modulemode = MODULEMODE_SWCTRL,
670 },
671 },
672 .dev_attr = &i2c_dev_attr,
673};
674
675/* i2c4 */
676static struct omap_hwmod omap54xx_i2c4_hwmod = {
677 .name = "i2c4",
678 .class = &omap54xx_i2c_hwmod_class,
679 .clkdm_name = "l4per_clkdm",
680 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
681 .main_clk = "func_96m_fclk",
682 .prcm = {
683 .omap4 = {
684 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
685 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
686 .modulemode = MODULEMODE_SWCTRL,
687 },
688 },
689 .dev_attr = &i2c_dev_attr,
690};
691
692/* i2c5 */
693static struct omap_hwmod omap54xx_i2c5_hwmod = {
694 .name = "i2c5",
695 .class = &omap54xx_i2c_hwmod_class,
696 .clkdm_name = "l4per_clkdm",
697 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
698 .main_clk = "func_96m_fclk",
699 .prcm = {
700 .omap4 = {
701 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
702 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
703 .modulemode = MODULEMODE_SWCTRL,
704 },
705 },
706 .dev_attr = &i2c_dev_attr,
707};
708
709/*
710 * 'kbd' class
711 * keyboard controller
712 */
713
714static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
715 .rev_offs = 0x0000,
716 .sysc_offs = 0x0010,
717 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
718 SYSC_HAS_SOFTRESET),
719 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
720 .sysc_fields = &omap_hwmod_sysc_type1,
721};
722
723static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
724 .name = "kbd",
725 .sysc = &omap54xx_kbd_sysc,
726};
727
728/* kbd */
729static struct omap_hwmod omap54xx_kbd_hwmod = {
730 .name = "kbd",
731 .class = &omap54xx_kbd_hwmod_class,
732 .clkdm_name = "wkupaon_clkdm",
733 .main_clk = "sys_32k_ck",
734 .prcm = {
735 .omap4 = {
736 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
737 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
738 .modulemode = MODULEMODE_SWCTRL,
739 },
740 },
741};
742
743/*
744 * 'mcbsp' class
745 * multi channel buffered serial port controller
746 */
747
748static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
749 .sysc_offs = 0x008c,
750 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
751 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
752 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
753 .sysc_fields = &omap_hwmod_sysc_type1,
754};
755
756static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
757 .name = "mcbsp",
758 .sysc = &omap54xx_mcbsp_sysc,
759 .rev = MCBSP_CONFIG_TYPE4,
760};
761
762/* mcbsp1 */
763static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
764 { .role = "pad_fck", .clk = "pad_clks_ck" },
765 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
766};
767
768static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
769 .name = "mcbsp1",
770 .class = &omap54xx_mcbsp_hwmod_class,
771 .clkdm_name = "abe_clkdm",
772 .main_clk = "mcbsp1_gfclk",
773 .prcm = {
774 .omap4 = {
775 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
776 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
777 .modulemode = MODULEMODE_SWCTRL,
778 },
779 },
780 .opt_clks = mcbsp1_opt_clks,
781 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
782};
783
784/* mcbsp2 */
785static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
786 { .role = "pad_fck", .clk = "pad_clks_ck" },
787 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
788};
789
790static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
791 .name = "mcbsp2",
792 .class = &omap54xx_mcbsp_hwmod_class,
793 .clkdm_name = "abe_clkdm",
794 .main_clk = "mcbsp2_gfclk",
795 .prcm = {
796 .omap4 = {
797 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
798 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
799 .modulemode = MODULEMODE_SWCTRL,
800 },
801 },
802 .opt_clks = mcbsp2_opt_clks,
803 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
804};
805
806/* mcbsp3 */
807static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
808 { .role = "pad_fck", .clk = "pad_clks_ck" },
809 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
810};
811
812static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
813 .name = "mcbsp3",
814 .class = &omap54xx_mcbsp_hwmod_class,
815 .clkdm_name = "abe_clkdm",
816 .main_clk = "mcbsp3_gfclk",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
820 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
821 .modulemode = MODULEMODE_SWCTRL,
822 },
823 },
824 .opt_clks = mcbsp3_opt_clks,
825 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
826};
827
828/*
829 * 'mcpdm' class
830 * multi channel pdm controller (proprietary interface with phoenix power
831 * ic)
832 */
833
834static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
835 .rev_offs = 0x0000,
836 .sysc_offs = 0x0010,
837 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
838 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
839 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
840 SIDLE_SMART_WKUP),
841 .sysc_fields = &omap_hwmod_sysc_type2,
842};
843
844static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
845 .name = "mcpdm",
846 .sysc = &omap54xx_mcpdm_sysc,
847};
848
849/* mcpdm */
850static struct omap_hwmod omap54xx_mcpdm_hwmod = {
851 .name = "mcpdm",
852 .class = &omap54xx_mcpdm_hwmod_class,
853 .clkdm_name = "abe_clkdm",
854 /*
855 * It's suspected that the McPDM requires an off-chip main
856 * functional clock, controlled via I2C. This IP block is
857 * currently reset very early during boot, before I2C is
858 * available, so it doesn't seem that we have any choice in
859 * the kernel other than to avoid resetting it. XXX This is
860 * really a hardware issue workaround: every IP block should
861 * be able to source its main functional clock from either
862 * on-chip or off-chip sources. McPDM seems to be the only
863 * current exception.
864 */
865
866 .flags = HWMOD_EXT_OPT_MAIN_CLK,
867 .main_clk = "pad_clks_ck",
868 .prcm = {
869 .omap4 = {
870 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
871 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
872 .modulemode = MODULEMODE_SWCTRL,
873 },
874 },
875};
876
877/*
878 * 'mcspi' class
879 * multichannel serial port interface (mcspi) / master/slave synchronous serial
880 * bus
881 */
882
883static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
884 .rev_offs = 0x0000,
885 .sysc_offs = 0x0010,
886 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
887 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
888 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
889 SIDLE_SMART_WKUP),
890 .sysc_fields = &omap_hwmod_sysc_type2,
891};
892
893static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
894 .name = "mcspi",
895 .sysc = &omap54xx_mcspi_sysc,
896 .rev = OMAP4_MCSPI_REV,
897};
898
899/* mcspi1 */
900/* mcspi1 dev_attr */
901static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
902 .num_chipselect = 4,
903};
904
905static struct omap_hwmod omap54xx_mcspi1_hwmod = {
906 .name = "mcspi1",
907 .class = &omap54xx_mcspi_hwmod_class,
908 .clkdm_name = "l4per_clkdm",
909 .main_clk = "func_48m_fclk",
910 .prcm = {
911 .omap4 = {
912 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
913 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
914 .modulemode = MODULEMODE_SWCTRL,
915 },
916 },
917 .dev_attr = &mcspi1_dev_attr,
918};
919
920/* mcspi2 */
921/* mcspi2 dev_attr */
922static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
923 .num_chipselect = 2,
924};
925
926static struct omap_hwmod omap54xx_mcspi2_hwmod = {
927 .name = "mcspi2",
928 .class = &omap54xx_mcspi_hwmod_class,
929 .clkdm_name = "l4per_clkdm",
930 .main_clk = "func_48m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
934 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &mcspi2_dev_attr,
939};
940
941/* mcspi3 */
942/* mcspi3 dev_attr */
943static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
944 .num_chipselect = 2,
945};
946
947static struct omap_hwmod omap54xx_mcspi3_hwmod = {
948 .name = "mcspi3",
949 .class = &omap54xx_mcspi_hwmod_class,
950 .clkdm_name = "l4per_clkdm",
951 .main_clk = "func_48m_fclk",
952 .prcm = {
953 .omap4 = {
954 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
955 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
956 .modulemode = MODULEMODE_SWCTRL,
957 },
958 },
959 .dev_attr = &mcspi3_dev_attr,
960};
961
962/* mcspi4 */
963/* mcspi4 dev_attr */
964static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
965 .num_chipselect = 1,
966};
967
968static struct omap_hwmod omap54xx_mcspi4_hwmod = {
969 .name = "mcspi4",
970 .class = &omap54xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
976 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi4_dev_attr,
981};
982
983/*
984 * 'mmc' class
985 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
986 */
987
988static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
989 .rev_offs = 0x0000,
990 .sysc_offs = 0x0010,
991 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
992 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
993 SYSC_HAS_SOFTRESET),
994 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
995 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
996 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
997 .sysc_fields = &omap_hwmod_sysc_type2,
998};
999
1000static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1001 .name = "mmc",
1002 .sysc = &omap54xx_mmc_sysc,
1003};
1004
1005/* mmc1 */
1006static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1007 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1008};
1009
1010/* mmc1 dev_attr */
1011static struct omap_mmc_dev_attr mmc1_dev_attr = {
1012 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1013};
1014
1015static struct omap_hwmod omap54xx_mmc1_hwmod = {
1016 .name = "mmc1",
1017 .class = &omap54xx_mmc_hwmod_class,
1018 .clkdm_name = "l3init_clkdm",
1019 .main_clk = "mmc1_fclk",
1020 .prcm = {
1021 .omap4 = {
1022 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1023 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1024 .modulemode = MODULEMODE_SWCTRL,
1025 },
1026 },
1027 .opt_clks = mmc1_opt_clks,
1028 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1029 .dev_attr = &mmc1_dev_attr,
1030};
1031
1032/* mmc2 */
1033static struct omap_hwmod omap54xx_mmc2_hwmod = {
1034 .name = "mmc2",
1035 .class = &omap54xx_mmc_hwmod_class,
1036 .clkdm_name = "l3init_clkdm",
1037 .main_clk = "mmc2_fclk",
1038 .prcm = {
1039 .omap4 = {
1040 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1041 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1042 .modulemode = MODULEMODE_SWCTRL,
1043 },
1044 },
1045};
1046
1047/* mmc3 */
1048static struct omap_hwmod omap54xx_mmc3_hwmod = {
1049 .name = "mmc3",
1050 .class = &omap54xx_mmc_hwmod_class,
1051 .clkdm_name = "l4per_clkdm",
1052 .main_clk = "func_48m_fclk",
1053 .prcm = {
1054 .omap4 = {
1055 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1056 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1057 .modulemode = MODULEMODE_SWCTRL,
1058 },
1059 },
1060};
1061
1062/* mmc4 */
1063static struct omap_hwmod omap54xx_mmc4_hwmod = {
1064 .name = "mmc4",
1065 .class = &omap54xx_mmc_hwmod_class,
1066 .clkdm_name = "l4per_clkdm",
1067 .main_clk = "func_48m_fclk",
1068 .prcm = {
1069 .omap4 = {
1070 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1071 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1072 .modulemode = MODULEMODE_SWCTRL,
1073 },
1074 },
1075};
1076
1077/* mmc5 */
1078static struct omap_hwmod omap54xx_mmc5_hwmod = {
1079 .name = "mmc5",
1080 .class = &omap54xx_mmc_hwmod_class,
1081 .clkdm_name = "l4per_clkdm",
1082 .main_clk = "func_96m_fclk",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1086 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090};
1091
1092/*
1093 * 'mpu' class
1094 * mpu sub-system
1095 */
1096
1097static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1098 .name = "mpu",
1099};
1100
1101/* mpu */
1102static struct omap_hwmod omap54xx_mpu_hwmod = {
1103 .name = "mpu",
1104 .class = &omap54xx_mpu_hwmod_class,
1105 .clkdm_name = "mpu_clkdm",
1106 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1107 .main_clk = "dpll_mpu_m2_ck",
1108 .prcm = {
1109 .omap4 = {
1110 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1111 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1112 },
1113 },
1114};
1115
1116/*
1117 * 'timer' class
1118 * general purpose timer module with accurate 1ms tick
1119 * This class contains several variants: ['timer_1ms', 'timer']
1120 */
1121
1122static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1123 .rev_offs = 0x0000,
1124 .sysc_offs = 0x0010,
1125 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1126 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1127 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1128 SIDLE_SMART_WKUP),
1129 .sysc_fields = &omap_hwmod_sysc_type2,
1130 .clockact = CLOCKACT_TEST_ICLK,
1131};
1132
1133static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1134 .name = "timer",
1135 .sysc = &omap54xx_timer_1ms_sysc,
1136};
1137
1138static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1139 .rev_offs = 0x0000,
1140 .sysc_offs = 0x0010,
1141 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1142 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1144 SIDLE_SMART_WKUP),
1145 .sysc_fields = &omap_hwmod_sysc_type2,
1146};
1147
1148static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1149 .name = "timer",
1150 .sysc = &omap54xx_timer_sysc,
1151};
1152
1153/* timer1 */
1154static struct omap_hwmod omap54xx_timer1_hwmod = {
1155 .name = "timer1",
1156 .class = &omap54xx_timer_1ms_hwmod_class,
1157 .clkdm_name = "wkupaon_clkdm",
1158 .main_clk = "timer1_gfclk_mux",
1159 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1160 .prcm = {
1161 .omap4 = {
1162 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1163 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1164 .modulemode = MODULEMODE_SWCTRL,
1165 },
1166 },
1167};
1168
1169/* timer2 */
1170static struct omap_hwmod omap54xx_timer2_hwmod = {
1171 .name = "timer2",
1172 .class = &omap54xx_timer_1ms_hwmod_class,
1173 .clkdm_name = "l4per_clkdm",
1174 .main_clk = "timer2_gfclk_mux",
1175 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1176 .prcm = {
1177 .omap4 = {
1178 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1179 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1180 .modulemode = MODULEMODE_SWCTRL,
1181 },
1182 },
1183};
1184
1185/* timer3 */
1186static struct omap_hwmod omap54xx_timer3_hwmod = {
1187 .name = "timer3",
1188 .class = &omap54xx_timer_hwmod_class,
1189 .clkdm_name = "l4per_clkdm",
1190 .main_clk = "timer3_gfclk_mux",
1191 .prcm = {
1192 .omap4 = {
1193 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1194 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1195 .modulemode = MODULEMODE_SWCTRL,
1196 },
1197 },
1198};
1199
1200/* timer4 */
1201static struct omap_hwmod omap54xx_timer4_hwmod = {
1202 .name = "timer4",
1203 .class = &omap54xx_timer_hwmod_class,
1204 .clkdm_name = "l4per_clkdm",
1205 .main_clk = "timer4_gfclk_mux",
1206 .prcm = {
1207 .omap4 = {
1208 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1209 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1210 .modulemode = MODULEMODE_SWCTRL,
1211 },
1212 },
1213};
1214
1215/* timer5 */
1216static struct omap_hwmod omap54xx_timer5_hwmod = {
1217 .name = "timer5",
1218 .class = &omap54xx_timer_hwmod_class,
1219 .clkdm_name = "abe_clkdm",
1220 .main_clk = "timer5_gfclk_mux",
1221 .prcm = {
1222 .omap4 = {
1223 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1224 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1225 .modulemode = MODULEMODE_SWCTRL,
1226 },
1227 },
1228};
1229
1230/* timer6 */
1231static struct omap_hwmod omap54xx_timer6_hwmod = {
1232 .name = "timer6",
1233 .class = &omap54xx_timer_hwmod_class,
1234 .clkdm_name = "abe_clkdm",
1235 .main_clk = "timer6_gfclk_mux",
1236 .prcm = {
1237 .omap4 = {
1238 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1239 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1240 .modulemode = MODULEMODE_SWCTRL,
1241 },
1242 },
1243};
1244
1245/* timer7 */
1246static struct omap_hwmod omap54xx_timer7_hwmod = {
1247 .name = "timer7",
1248 .class = &omap54xx_timer_hwmod_class,
1249 .clkdm_name = "abe_clkdm",
1250 .main_clk = "timer7_gfclk_mux",
1251 .prcm = {
1252 .omap4 = {
1253 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1254 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1255 .modulemode = MODULEMODE_SWCTRL,
1256 },
1257 },
1258};
1259
1260/* timer8 */
1261static struct omap_hwmod omap54xx_timer8_hwmod = {
1262 .name = "timer8",
1263 .class = &omap54xx_timer_hwmod_class,
1264 .clkdm_name = "abe_clkdm",
1265 .main_clk = "timer8_gfclk_mux",
1266 .prcm = {
1267 .omap4 = {
1268 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1269 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1270 .modulemode = MODULEMODE_SWCTRL,
1271 },
1272 },
1273};
1274
1275/* timer9 */
1276static struct omap_hwmod omap54xx_timer9_hwmod = {
1277 .name = "timer9",
1278 .class = &omap54xx_timer_hwmod_class,
1279 .clkdm_name = "l4per_clkdm",
1280 .main_clk = "timer9_gfclk_mux",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1284 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288};
1289
1290/* timer10 */
1291static struct omap_hwmod omap54xx_timer10_hwmod = {
1292 .name = "timer10",
1293 .class = &omap54xx_timer_1ms_hwmod_class,
1294 .clkdm_name = "l4per_clkdm",
1295 .main_clk = "timer10_gfclk_mux",
1296 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1297 .prcm = {
1298 .omap4 = {
1299 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1300 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1301 .modulemode = MODULEMODE_SWCTRL,
1302 },
1303 },
1304};
1305
1306/* timer11 */
1307static struct omap_hwmod omap54xx_timer11_hwmod = {
1308 .name = "timer11",
1309 .class = &omap54xx_timer_hwmod_class,
1310 .clkdm_name = "l4per_clkdm",
1311 .main_clk = "timer11_gfclk_mux",
1312 .prcm = {
1313 .omap4 = {
1314 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1315 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1316 .modulemode = MODULEMODE_SWCTRL,
1317 },
1318 },
1319};
1320
1321/*
1322 * 'uart' class
1323 * universal asynchronous receiver/transmitter (uart)
1324 */
1325
1326static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1327 .rev_offs = 0x0050,
1328 .sysc_offs = 0x0054,
1329 .syss_offs = 0x0058,
1330 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1331 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1332 SYSS_HAS_RESET_STATUS),
1333 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1334 SIDLE_SMART_WKUP),
1335 .sysc_fields = &omap_hwmod_sysc_type1,
1336};
1337
1338static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1339 .name = "uart",
1340 .sysc = &omap54xx_uart_sysc,
1341};
1342
1343/* uart1 */
1344static struct omap_hwmod omap54xx_uart1_hwmod = {
1345 .name = "uart1",
1346 .class = &omap54xx_uart_hwmod_class,
1347 .clkdm_name = "l4per_clkdm",
1348 .main_clk = "func_48m_fclk",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1352 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356};
1357
1358/* uart2 */
1359static struct omap_hwmod omap54xx_uart2_hwmod = {
1360 .name = "uart2",
1361 .class = &omap54xx_uart_hwmod_class,
1362 .clkdm_name = "l4per_clkdm",
1363 .main_clk = "func_48m_fclk",
1364 .prcm = {
1365 .omap4 = {
1366 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1367 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1368 .modulemode = MODULEMODE_SWCTRL,
1369 },
1370 },
1371};
1372
1373/* uart3 */
1374static struct omap_hwmod omap54xx_uart3_hwmod = {
1375 .name = "uart3",
1376 .class = &omap54xx_uart_hwmod_class,
1377 .clkdm_name = "l4per_clkdm",
1378 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1379 .main_clk = "func_48m_fclk",
1380 .prcm = {
1381 .omap4 = {
1382 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1383 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1384 .modulemode = MODULEMODE_SWCTRL,
1385 },
1386 },
1387};
1388
1389/* uart4 */
1390static struct omap_hwmod omap54xx_uart4_hwmod = {
1391 .name = "uart4",
1392 .class = &omap54xx_uart_hwmod_class,
1393 .clkdm_name = "l4per_clkdm",
1394 .main_clk = "func_48m_fclk",
1395 .prcm = {
1396 .omap4 = {
1397 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1398 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1399 .modulemode = MODULEMODE_SWCTRL,
1400 },
1401 },
1402};
1403
1404/* uart5 */
1405static struct omap_hwmod omap54xx_uart5_hwmod = {
1406 .name = "uart5",
1407 .class = &omap54xx_uart_hwmod_class,
1408 .clkdm_name = "l4per_clkdm",
1409 .main_clk = "func_48m_fclk",
1410 .prcm = {
1411 .omap4 = {
1412 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1413 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1414 .modulemode = MODULEMODE_SWCTRL,
1415 },
1416 },
1417};
1418
1419/* uart6 */
1420static struct omap_hwmod omap54xx_uart6_hwmod = {
1421 .name = "uart6",
1422 .class = &omap54xx_uart_hwmod_class,
1423 .clkdm_name = "l4per_clkdm",
1424 .main_clk = "func_48m_fclk",
1425 .prcm = {
1426 .omap4 = {
1427 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1428 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1429 .modulemode = MODULEMODE_SWCTRL,
1430 },
1431 },
1432};
1433
1434/*
1435 * 'usb_otg_ss' class
1436 * 2.0 super speed (usb_otg_ss) controller
1437 */
1438
1439static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1440 .rev_offs = 0x0000,
1441 .sysc_offs = 0x0010,
1442 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1443 SYSC_HAS_SIDLEMODE),
1444 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1445 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1446 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1447 .sysc_fields = &omap_hwmod_sysc_type2,
1448};
1449
1450static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1451 .name = "usb_otg_ss",
1452 .sysc = &omap54xx_usb_otg_ss_sysc,
1453};
1454
1455/* usb_otg_ss */
1456static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1457 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1458};
1459
1460static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1461 .name = "usb_otg_ss",
1462 .class = &omap54xx_usb_otg_ss_hwmod_class,
1463 .clkdm_name = "l3init_clkdm",
1464 .flags = HWMOD_SWSUP_SIDLE,
1465 .main_clk = "dpll_core_h13x2_ck",
1466 .prcm = {
1467 .omap4 = {
1468 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1469 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1470 .modulemode = MODULEMODE_HWCTRL,
1471 },
1472 },
1473 .opt_clks = usb_otg_ss_opt_clks,
1474 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1475};
1476
1477/*
1478 * 'wd_timer' class
1479 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1480 * overflow condition
1481 */
1482
1483static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1484 .rev_offs = 0x0000,
1485 .sysc_offs = 0x0010,
1486 .syss_offs = 0x0014,
1487 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1488 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1489 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1490 SIDLE_SMART_WKUP),
1491 .sysc_fields = &omap_hwmod_sysc_type1,
1492};
1493
1494static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1495 .name = "wd_timer",
1496 .sysc = &omap54xx_wd_timer_sysc,
1497 .pre_shutdown = &omap2_wd_timer_disable,
1498};
1499
1500/* wd_timer2 */
1501static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1502 .name = "wd_timer2",
1503 .class = &omap54xx_wd_timer_hwmod_class,
1504 .clkdm_name = "wkupaon_clkdm",
1505 .main_clk = "sys_32k_ck",
1506 .prcm = {
1507 .omap4 = {
1508 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1509 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1510 .modulemode = MODULEMODE_SWCTRL,
1511 },
1512 },
1513};
1514
1515
1516/*
1517 * Interfaces
1518 */
1519
1520/* l3_main_1 -> dmm */
1521static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1522 .master = &omap54xx_l3_main_1_hwmod,
1523 .slave = &omap54xx_dmm_hwmod,
1524 .clk = "l3_iclk_div",
1525 .user = OCP_USER_SDMA,
1526};
1527
1528/* l3_main_3 -> l3_instr */
1529static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1530 .master = &omap54xx_l3_main_3_hwmod,
1531 .slave = &omap54xx_l3_instr_hwmod,
1532 .clk = "l3_iclk_div",
1533 .user = OCP_USER_MPU | OCP_USER_SDMA,
1534};
1535
1536/* l3_main_2 -> l3_main_1 */
1537static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1538 .master = &omap54xx_l3_main_2_hwmod,
1539 .slave = &omap54xx_l3_main_1_hwmod,
1540 .clk = "l3_iclk_div",
1541 .user = OCP_USER_MPU | OCP_USER_SDMA,
1542};
1543
1544/* l4_cfg -> l3_main_1 */
1545static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1546 .master = &omap54xx_l4_cfg_hwmod,
1547 .slave = &omap54xx_l3_main_1_hwmod,
1548 .clk = "l3_iclk_div",
1549 .user = OCP_USER_MPU | OCP_USER_SDMA,
1550};
1551
1552/* mpu -> l3_main_1 */
1553static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1554 .master = &omap54xx_mpu_hwmod,
1555 .slave = &omap54xx_l3_main_1_hwmod,
1556 .clk = "l3_iclk_div",
1557 .user = OCP_USER_MPU,
1558};
1559
1560/* l3_main_1 -> l3_main_2 */
1561static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1562 .master = &omap54xx_l3_main_1_hwmod,
1563 .slave = &omap54xx_l3_main_2_hwmod,
1564 .clk = "l3_iclk_div",
1565 .user = OCP_USER_MPU,
1566};
1567
1568/* l4_cfg -> l3_main_2 */
1569static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1570 .master = &omap54xx_l4_cfg_hwmod,
1571 .slave = &omap54xx_l3_main_2_hwmod,
1572 .clk = "l3_iclk_div",
1573 .user = OCP_USER_MPU | OCP_USER_SDMA,
1574};
1575
1576/* l3_main_1 -> l3_main_3 */
1577static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1578 .master = &omap54xx_l3_main_1_hwmod,
1579 .slave = &omap54xx_l3_main_3_hwmod,
1580 .clk = "l3_iclk_div",
1581 .user = OCP_USER_MPU,
1582};
1583
1584/* l3_main_2 -> l3_main_3 */
1585static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1586 .master = &omap54xx_l3_main_2_hwmod,
1587 .slave = &omap54xx_l3_main_3_hwmod,
1588 .clk = "l3_iclk_div",
1589 .user = OCP_USER_MPU | OCP_USER_SDMA,
1590};
1591
1592/* l4_cfg -> l3_main_3 */
1593static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1594 .master = &omap54xx_l4_cfg_hwmod,
1595 .slave = &omap54xx_l3_main_3_hwmod,
1596 .clk = "l3_iclk_div",
1597 .user = OCP_USER_MPU | OCP_USER_SDMA,
1598};
1599
1600/* l3_main_1 -> l4_abe */
1601static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1602 .master = &omap54xx_l3_main_1_hwmod,
1603 .slave = &omap54xx_l4_abe_hwmod,
1604 .clk = "abe_iclk",
1605 .user = OCP_USER_MPU | OCP_USER_SDMA,
1606};
1607
1608/* mpu -> l4_abe */
1609static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1610 .master = &omap54xx_mpu_hwmod,
1611 .slave = &omap54xx_l4_abe_hwmod,
1612 .clk = "abe_iclk",
1613 .user = OCP_USER_MPU | OCP_USER_SDMA,
1614};
1615
1616/* l3_main_1 -> l4_cfg */
1617static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1618 .master = &omap54xx_l3_main_1_hwmod,
1619 .slave = &omap54xx_l4_cfg_hwmod,
1620 .clk = "l4_root_clk_div",
1621 .user = OCP_USER_MPU | OCP_USER_SDMA,
1622};
1623
1624/* l3_main_2 -> l4_per */
1625static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1626 .master = &omap54xx_l3_main_2_hwmod,
1627 .slave = &omap54xx_l4_per_hwmod,
1628 .clk = "l4_root_clk_div",
1629 .user = OCP_USER_MPU | OCP_USER_SDMA,
1630};
1631
1632/* l3_main_1 -> l4_wkup */
1633static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1634 .master = &omap54xx_l3_main_1_hwmod,
1635 .slave = &omap54xx_l4_wkup_hwmod,
1636 .clk = "wkupaon_iclk_mux",
1637 .user = OCP_USER_MPU | OCP_USER_SDMA,
1638};
1639
1640/* mpu -> mpu_private */
1641static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1642 .master = &omap54xx_mpu_hwmod,
1643 .slave = &omap54xx_mpu_private_hwmod,
1644 .clk = "l3_iclk_div",
1645 .user = OCP_USER_MPU | OCP_USER_SDMA,
1646};
1647
1648/* l4_wkup -> counter_32k */
1649static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1650 .master = &omap54xx_l4_wkup_hwmod,
1651 .slave = &omap54xx_counter_32k_hwmod,
1652 .clk = "wkupaon_iclk_mux",
1653 .user = OCP_USER_MPU | OCP_USER_SDMA,
1654};
1655
1656static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1657 {
1658 .pa_start = 0x4a056000,
1659 .pa_end = 0x4a056fff,
1660 .flags = ADDR_TYPE_RT
1661 },
1662 { }
1663};
1664
1665/* l4_cfg -> dma_system */
1666static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1667 .master = &omap54xx_l4_cfg_hwmod,
1668 .slave = &omap54xx_dma_system_hwmod,
1669 .clk = "l4_root_clk_div",
1670 .addr = omap54xx_dma_system_addrs,
1671 .user = OCP_USER_MPU | OCP_USER_SDMA,
1672};
1673
1674/* l4_abe -> dmic */
1675static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1676 .master = &omap54xx_l4_abe_hwmod,
1677 .slave = &omap54xx_dmic_hwmod,
1678 .clk = "abe_iclk",
1679 .user = OCP_USER_MPU,
1680};
1681
1682/* mpu -> emif1 */
1683static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1684 .master = &omap54xx_mpu_hwmod,
1685 .slave = &omap54xx_emif1_hwmod,
1686 .clk = "dpll_core_h11x2_ck",
1687 .user = OCP_USER_MPU | OCP_USER_SDMA,
1688};
1689
1690/* mpu -> emif2 */
1691static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1692 .master = &omap54xx_mpu_hwmod,
1693 .slave = &omap54xx_emif2_hwmod,
1694 .clk = "dpll_core_h11x2_ck",
1695 .user = OCP_USER_MPU | OCP_USER_SDMA,
1696};
1697
1698/* l4_wkup -> gpio1 */
1699static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1700 .master = &omap54xx_l4_wkup_hwmod,
1701 .slave = &omap54xx_gpio1_hwmod,
1702 .clk = "wkupaon_iclk_mux",
1703 .user = OCP_USER_MPU | OCP_USER_SDMA,
1704};
1705
1706/* l4_per -> gpio2 */
1707static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1708 .master = &omap54xx_l4_per_hwmod,
1709 .slave = &omap54xx_gpio2_hwmod,
1710 .clk = "l4_root_clk_div",
1711 .user = OCP_USER_MPU | OCP_USER_SDMA,
1712};
1713
1714/* l4_per -> gpio3 */
1715static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1716 .master = &omap54xx_l4_per_hwmod,
1717 .slave = &omap54xx_gpio3_hwmod,
1718 .clk = "l4_root_clk_div",
1719 .user = OCP_USER_MPU | OCP_USER_SDMA,
1720};
1721
1722/* l4_per -> gpio4 */
1723static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1724 .master = &omap54xx_l4_per_hwmod,
1725 .slave = &omap54xx_gpio4_hwmod,
1726 .clk = "l4_root_clk_div",
1727 .user = OCP_USER_MPU | OCP_USER_SDMA,
1728};
1729
1730/* l4_per -> gpio5 */
1731static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1732 .master = &omap54xx_l4_per_hwmod,
1733 .slave = &omap54xx_gpio5_hwmod,
1734 .clk = "l4_root_clk_div",
1735 .user = OCP_USER_MPU | OCP_USER_SDMA,
1736};
1737
1738/* l4_per -> gpio6 */
1739static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1740 .master = &omap54xx_l4_per_hwmod,
1741 .slave = &omap54xx_gpio6_hwmod,
1742 .clk = "l4_root_clk_div",
1743 .user = OCP_USER_MPU | OCP_USER_SDMA,
1744};
1745
1746/* l4_per -> gpio7 */
1747static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1748 .master = &omap54xx_l4_per_hwmod,
1749 .slave = &omap54xx_gpio7_hwmod,
1750 .clk = "l4_root_clk_div",
1751 .user = OCP_USER_MPU | OCP_USER_SDMA,
1752};
1753
1754/* l4_per -> gpio8 */
1755static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1756 .master = &omap54xx_l4_per_hwmod,
1757 .slave = &omap54xx_gpio8_hwmod,
1758 .clk = "l4_root_clk_div",
1759 .user = OCP_USER_MPU | OCP_USER_SDMA,
1760};
1761
1762/* l4_per -> i2c1 */
1763static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1764 .master = &omap54xx_l4_per_hwmod,
1765 .slave = &omap54xx_i2c1_hwmod,
1766 .clk = "l4_root_clk_div",
1767 .user = OCP_USER_MPU | OCP_USER_SDMA,
1768};
1769
1770/* l4_per -> i2c2 */
1771static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1772 .master = &omap54xx_l4_per_hwmod,
1773 .slave = &omap54xx_i2c2_hwmod,
1774 .clk = "l4_root_clk_div",
1775 .user = OCP_USER_MPU | OCP_USER_SDMA,
1776};
1777
1778/* l4_per -> i2c3 */
1779static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1780 .master = &omap54xx_l4_per_hwmod,
1781 .slave = &omap54xx_i2c3_hwmod,
1782 .clk = "l4_root_clk_div",
1783 .user = OCP_USER_MPU | OCP_USER_SDMA,
1784};
1785
1786/* l4_per -> i2c4 */
1787static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
1788 .master = &omap54xx_l4_per_hwmod,
1789 .slave = &omap54xx_i2c4_hwmod,
1790 .clk = "l4_root_clk_div",
1791 .user = OCP_USER_MPU | OCP_USER_SDMA,
1792};
1793
1794/* l4_per -> i2c5 */
1795static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
1796 .master = &omap54xx_l4_per_hwmod,
1797 .slave = &omap54xx_i2c5_hwmod,
1798 .clk = "l4_root_clk_div",
1799 .user = OCP_USER_MPU | OCP_USER_SDMA,
1800};
1801
1802/* l4_wkup -> kbd */
1803static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1804 .master = &omap54xx_l4_wkup_hwmod,
1805 .slave = &omap54xx_kbd_hwmod,
1806 .clk = "wkupaon_iclk_mux",
1807 .user = OCP_USER_MPU | OCP_USER_SDMA,
1808};
1809
1810/* l4_abe -> mcbsp1 */
1811static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1812 .master = &omap54xx_l4_abe_hwmod,
1813 .slave = &omap54xx_mcbsp1_hwmod,
1814 .clk = "abe_iclk",
1815 .user = OCP_USER_MPU,
1816};
1817
1818/* l4_abe -> mcbsp2 */
1819static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
1820 .master = &omap54xx_l4_abe_hwmod,
1821 .slave = &omap54xx_mcbsp2_hwmod,
1822 .clk = "abe_iclk",
1823 .user = OCP_USER_MPU,
1824};
1825
1826/* l4_abe -> mcbsp3 */
1827static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
1828 .master = &omap54xx_l4_abe_hwmod,
1829 .slave = &omap54xx_mcbsp3_hwmod,
1830 .clk = "abe_iclk",
1831 .user = OCP_USER_MPU,
1832};
1833
1834/* l4_abe -> mcpdm */
1835static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1836 .master = &omap54xx_l4_abe_hwmod,
1837 .slave = &omap54xx_mcpdm_hwmod,
1838 .clk = "abe_iclk",
1839 .user = OCP_USER_MPU,
1840};
1841
1842/* l4_per -> mcspi1 */
1843static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
1844 .master = &omap54xx_l4_per_hwmod,
1845 .slave = &omap54xx_mcspi1_hwmod,
1846 .clk = "l4_root_clk_div",
1847 .user = OCP_USER_MPU | OCP_USER_SDMA,
1848};
1849
1850/* l4_per -> mcspi2 */
1851static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
1852 .master = &omap54xx_l4_per_hwmod,
1853 .slave = &omap54xx_mcspi2_hwmod,
1854 .clk = "l4_root_clk_div",
1855 .user = OCP_USER_MPU | OCP_USER_SDMA,
1856};
1857
1858/* l4_per -> mcspi3 */
1859static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
1860 .master = &omap54xx_l4_per_hwmod,
1861 .slave = &omap54xx_mcspi3_hwmod,
1862 .clk = "l4_root_clk_div",
1863 .user = OCP_USER_MPU | OCP_USER_SDMA,
1864};
1865
1866/* l4_per -> mcspi4 */
1867static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
1868 .master = &omap54xx_l4_per_hwmod,
1869 .slave = &omap54xx_mcspi4_hwmod,
1870 .clk = "l4_root_clk_div",
1871 .user = OCP_USER_MPU | OCP_USER_SDMA,
1872};
1873
1874/* l4_per -> mmc1 */
1875static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
1876 .master = &omap54xx_l4_per_hwmod,
1877 .slave = &omap54xx_mmc1_hwmod,
1878 .clk = "l3_iclk_div",
1879 .user = OCP_USER_MPU | OCP_USER_SDMA,
1880};
1881
1882/* l4_per -> mmc2 */
1883static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
1884 .master = &omap54xx_l4_per_hwmod,
1885 .slave = &omap54xx_mmc2_hwmod,
1886 .clk = "l3_iclk_div",
1887 .user = OCP_USER_MPU | OCP_USER_SDMA,
1888};
1889
1890/* l4_per -> mmc3 */
1891static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
1892 .master = &omap54xx_l4_per_hwmod,
1893 .slave = &omap54xx_mmc3_hwmod,
1894 .clk = "l4_root_clk_div",
1895 .user = OCP_USER_MPU | OCP_USER_SDMA,
1896};
1897
1898/* l4_per -> mmc4 */
1899static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
1900 .master = &omap54xx_l4_per_hwmod,
1901 .slave = &omap54xx_mmc4_hwmod,
1902 .clk = "l4_root_clk_div",
1903 .user = OCP_USER_MPU | OCP_USER_SDMA,
1904};
1905
1906/* l4_per -> mmc5 */
1907static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
1908 .master = &omap54xx_l4_per_hwmod,
1909 .slave = &omap54xx_mmc5_hwmod,
1910 .clk = "l4_root_clk_div",
1911 .user = OCP_USER_MPU | OCP_USER_SDMA,
1912};
1913
1914/* l4_cfg -> mpu */
1915static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1916 .master = &omap54xx_l4_cfg_hwmod,
1917 .slave = &omap54xx_mpu_hwmod,
1918 .clk = "l4_root_clk_div",
1919 .user = OCP_USER_MPU | OCP_USER_SDMA,
1920};
1921
1922/* l4_wkup -> timer1 */
1923static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1924 .master = &omap54xx_l4_wkup_hwmod,
1925 .slave = &omap54xx_timer1_hwmod,
1926 .clk = "wkupaon_iclk_mux",
1927 .user = OCP_USER_MPU | OCP_USER_SDMA,
1928};
1929
1930/* l4_per -> timer2 */
1931static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1932 .master = &omap54xx_l4_per_hwmod,
1933 .slave = &omap54xx_timer2_hwmod,
1934 .clk = "l4_root_clk_div",
1935 .user = OCP_USER_MPU | OCP_USER_SDMA,
1936};
1937
1938/* l4_per -> timer3 */
1939static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1940 .master = &omap54xx_l4_per_hwmod,
1941 .slave = &omap54xx_timer3_hwmod,
1942 .clk = "l4_root_clk_div",
1943 .user = OCP_USER_MPU | OCP_USER_SDMA,
1944};
1945
1946/* l4_per -> timer4 */
1947static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1948 .master = &omap54xx_l4_per_hwmod,
1949 .slave = &omap54xx_timer4_hwmod,
1950 .clk = "l4_root_clk_div",
1951 .user = OCP_USER_MPU | OCP_USER_SDMA,
1952};
1953
1954/* l4_abe -> timer5 */
1955static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1956 .master = &omap54xx_l4_abe_hwmod,
1957 .slave = &omap54xx_timer5_hwmod,
1958 .clk = "abe_iclk",
1959 .user = OCP_USER_MPU,
1960};
1961
1962/* l4_abe -> timer6 */
1963static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
1964 .master = &omap54xx_l4_abe_hwmod,
1965 .slave = &omap54xx_timer6_hwmod,
1966 .clk = "abe_iclk",
1967 .user = OCP_USER_MPU,
1968};
1969
1970/* l4_abe -> timer7 */
1971static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
1972 .master = &omap54xx_l4_abe_hwmod,
1973 .slave = &omap54xx_timer7_hwmod,
1974 .clk = "abe_iclk",
1975 .user = OCP_USER_MPU,
1976};
1977
1978/* l4_abe -> timer8 */
1979static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
1980 .master = &omap54xx_l4_abe_hwmod,
1981 .slave = &omap54xx_timer8_hwmod,
1982 .clk = "abe_iclk",
1983 .user = OCP_USER_MPU,
1984};
1985
1986/* l4_per -> timer9 */
1987static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
1988 .master = &omap54xx_l4_per_hwmod,
1989 .slave = &omap54xx_timer9_hwmod,
1990 .clk = "l4_root_clk_div",
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1992};
1993
1994/* l4_per -> timer10 */
1995static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
1996 .master = &omap54xx_l4_per_hwmod,
1997 .slave = &omap54xx_timer10_hwmod,
1998 .clk = "l4_root_clk_div",
1999 .user = OCP_USER_MPU | OCP_USER_SDMA,
2000};
2001
2002/* l4_per -> timer11 */
2003static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2004 .master = &omap54xx_l4_per_hwmod,
2005 .slave = &omap54xx_timer11_hwmod,
2006 .clk = "l4_root_clk_div",
2007 .user = OCP_USER_MPU | OCP_USER_SDMA,
2008};
2009
2010/* l4_per -> uart1 */
2011static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2012 .master = &omap54xx_l4_per_hwmod,
2013 .slave = &omap54xx_uart1_hwmod,
2014 .clk = "l4_root_clk_div",
2015 .user = OCP_USER_MPU | OCP_USER_SDMA,
2016};
2017
2018/* l4_per -> uart2 */
2019static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2020 .master = &omap54xx_l4_per_hwmod,
2021 .slave = &omap54xx_uart2_hwmod,
2022 .clk = "l4_root_clk_div",
2023 .user = OCP_USER_MPU | OCP_USER_SDMA,
2024};
2025
2026/* l4_per -> uart3 */
2027static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2028 .master = &omap54xx_l4_per_hwmod,
2029 .slave = &omap54xx_uart3_hwmod,
2030 .clk = "l4_root_clk_div",
2031 .user = OCP_USER_MPU | OCP_USER_SDMA,
2032};
2033
2034/* l4_per -> uart4 */
2035static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2036 .master = &omap54xx_l4_per_hwmod,
2037 .slave = &omap54xx_uart4_hwmod,
2038 .clk = "l4_root_clk_div",
2039 .user = OCP_USER_MPU | OCP_USER_SDMA,
2040};
2041
2042/* l4_per -> uart5 */
2043static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2044 .master = &omap54xx_l4_per_hwmod,
2045 .slave = &omap54xx_uart5_hwmod,
2046 .clk = "l4_root_clk_div",
2047 .user = OCP_USER_MPU | OCP_USER_SDMA,
2048};
2049
2050/* l4_per -> uart6 */
2051static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2052 .master = &omap54xx_l4_per_hwmod,
2053 .slave = &omap54xx_uart6_hwmod,
2054 .clk = "l4_root_clk_div",
2055 .user = OCP_USER_MPU | OCP_USER_SDMA,
2056};
2057
2058/* l4_cfg -> usb_otg_ss */
2059static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2060 .master = &omap54xx_l4_cfg_hwmod,
2061 .slave = &omap54xx_usb_otg_ss_hwmod,
2062 .clk = "dpll_core_h13x2_ck",
2063 .user = OCP_USER_MPU | OCP_USER_SDMA,
2064};
2065
2066/* l4_wkup -> wd_timer2 */
2067static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2068 .master = &omap54xx_l4_wkup_hwmod,
2069 .slave = &omap54xx_wd_timer2_hwmod,
2070 .clk = "wkupaon_iclk_mux",
2071 .user = OCP_USER_MPU | OCP_USER_SDMA,
2072};
2073
2074static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2075 &omap54xx_l3_main_1__dmm,
2076 &omap54xx_l3_main_3__l3_instr,
2077 &omap54xx_l3_main_2__l3_main_1,
2078 &omap54xx_l4_cfg__l3_main_1,
2079 &omap54xx_mpu__l3_main_1,
2080 &omap54xx_l3_main_1__l3_main_2,
2081 &omap54xx_l4_cfg__l3_main_2,
2082 &omap54xx_l3_main_1__l3_main_3,
2083 &omap54xx_l3_main_2__l3_main_3,
2084 &omap54xx_l4_cfg__l3_main_3,
2085 &omap54xx_l3_main_1__l4_abe,
2086 &omap54xx_mpu__l4_abe,
2087 &omap54xx_l3_main_1__l4_cfg,
2088 &omap54xx_l3_main_2__l4_per,
2089 &omap54xx_l3_main_1__l4_wkup,
2090 &omap54xx_mpu__mpu_private,
2091 &omap54xx_l4_wkup__counter_32k,
2092 &omap54xx_l4_cfg__dma_system,
2093 &omap54xx_l4_abe__dmic,
2094 &omap54xx_mpu__emif1,
2095 &omap54xx_mpu__emif2,
2096 &omap54xx_l4_wkup__gpio1,
2097 &omap54xx_l4_per__gpio2,
2098 &omap54xx_l4_per__gpio3,
2099 &omap54xx_l4_per__gpio4,
2100 &omap54xx_l4_per__gpio5,
2101 &omap54xx_l4_per__gpio6,
2102 &omap54xx_l4_per__gpio7,
2103 &omap54xx_l4_per__gpio8,
2104 &omap54xx_l4_per__i2c1,
2105 &omap54xx_l4_per__i2c2,
2106 &omap54xx_l4_per__i2c3,
2107 &omap54xx_l4_per__i2c4,
2108 &omap54xx_l4_per__i2c5,
2109 &omap54xx_l4_wkup__kbd,
2110 &omap54xx_l4_abe__mcbsp1,
2111 &omap54xx_l4_abe__mcbsp2,
2112 &omap54xx_l4_abe__mcbsp3,
2113 &omap54xx_l4_abe__mcpdm,
2114 &omap54xx_l4_per__mcspi1,
2115 &omap54xx_l4_per__mcspi2,
2116 &omap54xx_l4_per__mcspi3,
2117 &omap54xx_l4_per__mcspi4,
2118 &omap54xx_l4_per__mmc1,
2119 &omap54xx_l4_per__mmc2,
2120 &omap54xx_l4_per__mmc3,
2121 &omap54xx_l4_per__mmc4,
2122 &omap54xx_l4_per__mmc5,
2123 &omap54xx_l4_cfg__mpu,
2124 &omap54xx_l4_wkup__timer1,
2125 &omap54xx_l4_per__timer2,
2126 &omap54xx_l4_per__timer3,
2127 &omap54xx_l4_per__timer4,
2128 &omap54xx_l4_abe__timer5,
2129 &omap54xx_l4_abe__timer6,
2130 &omap54xx_l4_abe__timer7,
2131 &omap54xx_l4_abe__timer8,
2132 &omap54xx_l4_per__timer9,
2133 &omap54xx_l4_per__timer10,
2134 &omap54xx_l4_per__timer11,
2135 &omap54xx_l4_per__uart1,
2136 &omap54xx_l4_per__uart2,
2137 &omap54xx_l4_per__uart3,
2138 &omap54xx_l4_per__uart4,
2139 &omap54xx_l4_per__uart5,
2140 &omap54xx_l4_per__uart6,
2141 &omap54xx_l4_cfg__usb_otg_ss,
2142 &omap54xx_l4_wkup__wd_timer2,
2143 NULL,
2144};
2145
2146int __init omap54xx_hwmod_init(void)
2147{
2148 omap_hwmod_init();
2149 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2150}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c01859398b54..5a2d8034c8de 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
546 /* Clear any pending PRCM interrupts */ 546 /* Clear any pending PRCM interrupts */
547 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 547 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
548 548
549 if (omap3_has_iva()) 549 /*
550 omap3_iva_idle(); 550 * We need to idle iva2_pwrdm even on am3703 with no iva2.
551 */
552 omap3_iva_idle();
551 553
552 omap3_d2d_idle(); 554 omap3_d2d_idle();
553} 555}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index a251f87fa2a2..82f0698933d8 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP4 Power Management Routines 2 * OMAP4+ Power Management Routines
3 * 3 *
4 * Copyright (C) 2010-2011 Texas Instruments, Inc. 4 * Copyright (C) 2010-2013 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com> 5 * Rajendra Nayak <rnayak@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * 7 *
@@ -135,16 +135,16 @@ static void omap_default_idle(void)
135} 135}
136 136
137/** 137/**
138 * omap4_pm_init - Init routine for OMAP4 PM 138 * omap4_init_static_deps - Add OMAP4 static dependencies
139 * 139 *
140 * Initializes all powerdomain and clockdomain target states 140 * Add needed static clockdomain dependencies on OMAP4 devices.
141 * and all PRCM settings. 141 * Return: 0 on success or 'err' on failures
142 */ 142 */
143int __init omap4_pm_init(void) 143static inline int omap4_init_static_deps(void)
144{ 144{
145 int ret;
146 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; 145 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
147 struct clockdomain *ducati_clkdm, *l3_2_clkdm; 146 struct clockdomain *ducati_clkdm, *l3_2_clkdm;
147 int ret = 0;
148 148
149 if (omap_rev() == OMAP4430_REV_ES1_0) { 149 if (omap_rev() == OMAP4430_REV_ES1_0) {
150 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); 150 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -163,7 +163,7 @@ int __init omap4_pm_init(void)
163 ret = pwrdm_for_each(pwrdms_setup, NULL); 163 ret = pwrdm_for_each(pwrdms_setup, NULL);
164 if (ret) { 164 if (ret) {
165 pr_err("Failed to setup powerdomains\n"); 165 pr_err("Failed to setup powerdomains\n");
166 goto err2; 166 return ret;
167 } 167 }
168 168
169 /* 169 /*
@@ -171,6 +171,10 @@ int __init omap4_pm_init(void)
171 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as 171 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
172 * expected. The hardware recommendation is to enable static 172 * expected. The hardware recommendation is to enable static
173 * dependencies for these to avoid system lock ups or random crashes. 173 * dependencies for these to avoid system lock ups or random crashes.
174 * The L4 wakeup depedency is added to workaround the OCP sync hardware
175 * BUG with 32K synctimer which lead to incorrect timer value read
176 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
177 * are part of L4 wakeup clockdomain.
174 */ 178 */
175 mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); 179 mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
176 emif_clkdm = clkdm_lookup("l3_emif_clkdm"); 180 emif_clkdm = clkdm_lookup("l3_emif_clkdm");
@@ -179,7 +183,7 @@ int __init omap4_pm_init(void)
179 ducati_clkdm = clkdm_lookup("ducati_clkdm"); 183 ducati_clkdm = clkdm_lookup("ducati_clkdm");
180 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || 184 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
181 (!l3_2_clkdm) || (!ducati_clkdm)) 185 (!l3_2_clkdm) || (!ducati_clkdm))
182 goto err2; 186 return -EINVAL;
183 187
184 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); 188 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
185 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); 189 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
@@ -188,9 +192,42 @@ int __init omap4_pm_init(void)
188 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); 192 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
189 if (ret) { 193 if (ret) {
190 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); 194 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
195 return -EINVAL;
196 }
197
198 return ret;
199}
200
201/**
202 * omap4_pm_init - Init routine for OMAP4+ devices
203 *
204 * Initializes all powerdomain and clockdomain target states
205 * and all PRCM settings.
206 * Return: Returns the error code returned by called functions.
207 */
208int __init omap4_pm_init(void)
209{
210 int ret = 0;
211
212 if (omap_rev() == OMAP4430_REV_ES1_0) {
213 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
214 return -ENODEV;
215 }
216
217 pr_info("Power Management for TI OMAP4+ devices.\n");
218
219 ret = pwrdm_for_each(pwrdms_setup, NULL);
220 if (ret) {
221 pr_err("Failed to setup powerdomains.\n");
191 goto err2; 222 goto err2;
192 } 223 }
193 224
225 if (cpu_is_omap44xx()) {
226 ret = omap4_init_static_deps();
227 if (ret)
228 goto err2;
229 }
230
194 ret = omap4_mpuss_init(); 231 ret = omap4_mpuss_init();
195 if (ret) { 232 if (ret) {
196 pr_err("Failed to initialise OMAP4 MPUSS\n"); 233 pr_err("Failed to initialise OMAP4 MPUSS\n");
@@ -206,7 +243,8 @@ int __init omap4_pm_init(void)
206 /* Overwrite the default cpu_do_idle() */ 243 /* Overwrite the default cpu_do_idle() */
207 arm_pm_idle = omap_default_idle; 244 arm_pm_idle = omap_default_idle;
208 245
209 omap4_idle_init(); 246 if (cpu_is_omap44xx())
247 omap4_idle_init();
210 248
211err2: 249err2:
212 return ret; 250 return ret;
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 140c36074fed..3d82f5035aad 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -253,6 +253,7 @@ extern void omap243x_powerdomains_init(void);
253extern void omap3xxx_powerdomains_init(void); 253extern void omap3xxx_powerdomains_init(void);
254extern void am33xx_powerdomains_init(void); 254extern void am33xx_powerdomains_init(void);
255extern void omap44xx_powerdomains_init(void); 255extern void omap44xx_powerdomains_init(void);
256extern void omap54xx_powerdomains_init(void);
256 257
257extern struct pwrdm_ops omap2_pwrdm_operations; 258extern struct pwrdm_ops omap2_pwrdm_operations;
258extern struct pwrdm_ops omap3_pwrdm_operations; 259extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
new file mode 100644
index 000000000000..81f8a7cc26ee
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -0,0 +1,331 @@
1/*
2 * OMAP54XX Power domains framework
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Abhijit Pagare (abhijitpagare@ti.com)
7 * Benoit Cousson (b-cousson@ti.com)
8 * Paul Walmsley (paul@pwsan.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23
24#include "powerdomain.h"
25
26#include "prcm-common.h"
27#include "prcm44xx.h"
28#include "prm-regbits-54xx.h"
29#include "prm54xx.h"
30#include "prcm_mpu54xx.h"
31
32/* core_54xx_pwrdm: CORE power domain */
33static struct powerdomain core_54xx_pwrdm = {
34 .name = "core_pwrdm",
35 .voltdm = { .name = "core" },
36 .prcm_offs = OMAP54XX_PRM_CORE_INST,
37 .prcm_partition = OMAP54XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_RET_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF_RET,
40 .banks = 5,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
43 [1] = PWRSTS_OFF_RET, /* core_ocmram */
44 [2] = PWRSTS_OFF_RET, /* core_other_bank */
45 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
46 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
47 },
48 .pwrsts_mem_on = {
49 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
50 [1] = PWRSTS_OFF_RET, /* core_ocmram */
51 [2] = PWRSTS_OFF_RET, /* core_other_bank */
52 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
53 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
54 },
55 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
56};
57
58/* abe_54xx_pwrdm: Audio back end power domain */
59static struct powerdomain abe_54xx_pwrdm = {
60 .name = "abe_pwrdm",
61 .voltdm = { .name = "core" },
62 .prcm_offs = OMAP54XX_PRM_ABE_INST,
63 .prcm_partition = OMAP54XX_PRM_PARTITION,
64 .pwrsts = PWRSTS_OFF_RET_ON,
65 .pwrsts_logic_ret = PWRSTS_OFF,
66 .banks = 2,
67 .pwrsts_mem_ret = {
68 [0] = PWRSTS_OFF_RET, /* aessmem */
69 [1] = PWRSTS_OFF_RET, /* periphmem */
70 },
71 .pwrsts_mem_on = {
72 [0] = PWRSTS_OFF_RET, /* aessmem */
73 [1] = PWRSTS_OFF_RET, /* periphmem */
74 },
75 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
76};
77
78/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
79static struct powerdomain coreaon_54xx_pwrdm = {
80 .name = "coreaon_pwrdm",
81 .voltdm = { .name = "core" },
82 .prcm_offs = OMAP54XX_PRM_COREAON_INST,
83 .prcm_partition = OMAP54XX_PRM_PARTITION,
84 .pwrsts = PWRSTS_ON,
85};
86
87/* dss_54xx_pwrdm: Display subsystem power domain */
88static struct powerdomain dss_54xx_pwrdm = {
89 .name = "dss_pwrdm",
90 .voltdm = { .name = "core" },
91 .prcm_offs = OMAP54XX_PRM_DSS_INST,
92 .prcm_partition = OMAP54XX_PRM_PARTITION,
93 .pwrsts = PWRSTS_OFF_RET_ON,
94 .pwrsts_logic_ret = PWRSTS_OFF,
95 .banks = 1,
96 .pwrsts_mem_ret = {
97 [0] = PWRSTS_OFF_RET, /* dss_mem */
98 },
99 .pwrsts_mem_on = {
100 [0] = PWRSTS_OFF_RET, /* dss_mem */
101 },
102 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
103};
104
105/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
106static struct powerdomain cpu0_54xx_pwrdm = {
107 .name = "cpu0_pwrdm",
108 .voltdm = { .name = "mpu" },
109 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C0_INST,
110 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
111 .pwrsts = PWRSTS_OFF_RET_ON,
112 .pwrsts_logic_ret = PWRSTS_OFF_RET,
113 .banks = 1,
114 .pwrsts_mem_ret = {
115 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
116 },
117 .pwrsts_mem_on = {
118 [0] = PWRSTS_ON, /* cpu0_l1 */
119 },
120};
121
122/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
123static struct powerdomain cpu1_54xx_pwrdm = {
124 .name = "cpu1_pwrdm",
125 .voltdm = { .name = "mpu" },
126 .prcm_offs = OMAP54XX_PRCM_MPU_PRM_C1_INST,
127 .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
128 .pwrsts = PWRSTS_OFF_RET_ON,
129 .pwrsts_logic_ret = PWRSTS_OFF_RET,
130 .banks = 1,
131 .pwrsts_mem_ret = {
132 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
133 },
134 .pwrsts_mem_on = {
135 [0] = PWRSTS_ON, /* cpu1_l1 */
136 },
137};
138
139/* emu_54xx_pwrdm: Emulation power domain */
140static struct powerdomain emu_54xx_pwrdm = {
141 .name = "emu_pwrdm",
142 .voltdm = { .name = "wkup" },
143 .prcm_offs = OMAP54XX_PRM_EMU_INST,
144 .prcm_partition = OMAP54XX_PRM_PARTITION,
145 .pwrsts = PWRSTS_OFF_ON,
146 .banks = 1,
147 .pwrsts_mem_ret = {
148 [0] = PWRSTS_OFF_RET, /* emu_bank */
149 },
150 .pwrsts_mem_on = {
151 [0] = PWRSTS_OFF_RET, /* emu_bank */
152 },
153};
154
155/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
156static struct powerdomain mpu_54xx_pwrdm = {
157 .name = "mpu_pwrdm",
158 .voltdm = { .name = "mpu" },
159 .prcm_offs = OMAP54XX_PRM_MPU_INST,
160 .prcm_partition = OMAP54XX_PRM_PARTITION,
161 .pwrsts = PWRSTS_RET_ON,
162 .pwrsts_logic_ret = PWRSTS_OFF_RET,
163 .banks = 2,
164 .pwrsts_mem_ret = {
165 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
166 [1] = PWRSTS_RET, /* mpu_ram */
167 },
168 .pwrsts_mem_on = {
169 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
170 [1] = PWRSTS_OFF_RET, /* mpu_ram */
171 },
172};
173
174/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
175static struct powerdomain custefuse_54xx_pwrdm = {
176 .name = "custefuse_pwrdm",
177 .voltdm = { .name = "core" },
178 .prcm_offs = OMAP54XX_PRM_CUSTEFUSE_INST,
179 .prcm_partition = OMAP54XX_PRM_PARTITION,
180 .pwrsts = PWRSTS_OFF_ON,
181 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
182};
183
184/* dsp_54xx_pwrdm: Tesla processor power domain */
185static struct powerdomain dsp_54xx_pwrdm = {
186 .name = "dsp_pwrdm",
187 .voltdm = { .name = "mm" },
188 .prcm_offs = OMAP54XX_PRM_DSP_INST,
189 .prcm_partition = OMAP54XX_PRM_PARTITION,
190 .pwrsts = PWRSTS_OFF_RET_ON,
191 .pwrsts_logic_ret = PWRSTS_OFF_RET,
192 .banks = 3,
193 .pwrsts_mem_ret = {
194 [0] = PWRSTS_OFF_RET, /* dsp_edma */
195 [1] = PWRSTS_OFF_RET, /* dsp_l1 */
196 [2] = PWRSTS_OFF_RET, /* dsp_l2 */
197 },
198 .pwrsts_mem_on = {
199 [0] = PWRSTS_OFF_RET, /* dsp_edma */
200 [1] = PWRSTS_OFF_RET, /* dsp_l1 */
201 [2] = PWRSTS_OFF_RET, /* dsp_l2 */
202 },
203 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
204};
205
206/* cam_54xx_pwrdm: Camera subsystem power domain */
207static struct powerdomain cam_54xx_pwrdm = {
208 .name = "cam_pwrdm",
209 .voltdm = { .name = "core" },
210 .prcm_offs = OMAP54XX_PRM_CAM_INST,
211 .prcm_partition = OMAP54XX_PRM_PARTITION,
212 .pwrsts = PWRSTS_OFF_ON,
213 .banks = 1,
214 .pwrsts_mem_ret = {
215 [0] = PWRSTS_OFF_RET, /* cam_mem */
216 },
217 .pwrsts_mem_on = {
218 [0] = PWRSTS_OFF_RET, /* cam_mem */
219 },
220 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
221};
222
223/* l3init_54xx_pwrdm: L3 initators pheripherals power domain */
224static struct powerdomain l3init_54xx_pwrdm = {
225 .name = "l3init_pwrdm",
226 .voltdm = { .name = "core" },
227 .prcm_offs = OMAP54XX_PRM_L3INIT_INST,
228 .prcm_partition = OMAP54XX_PRM_PARTITION,
229 .pwrsts = PWRSTS_RET_ON,
230 .pwrsts_logic_ret = PWRSTS_OFF_RET,
231 .banks = 2,
232 .pwrsts_mem_ret = {
233 [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
234 [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
235 },
236 .pwrsts_mem_on = {
237 [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
238 [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
239 },
240 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
241};
242
243/* gpu_54xx_pwrdm: 3D accelerator power domain */
244static struct powerdomain gpu_54xx_pwrdm = {
245 .name = "gpu_pwrdm",
246 .voltdm = { .name = "mm" },
247 .prcm_offs = OMAP54XX_PRM_GPU_INST,
248 .prcm_partition = OMAP54XX_PRM_PARTITION,
249 .pwrsts = PWRSTS_OFF_ON,
250 .banks = 1,
251 .pwrsts_mem_ret = {
252 [0] = PWRSTS_OFF_RET, /* gpu_mem */
253 },
254 .pwrsts_mem_on = {
255 [0] = PWRSTS_OFF_RET, /* gpu_mem */
256 },
257 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
258};
259
260/* wkupaon_54xx_pwrdm: Wake-up power domain */
261static struct powerdomain wkupaon_54xx_pwrdm = {
262 .name = "wkupaon_pwrdm",
263 .voltdm = { .name = "wkup" },
264 .prcm_offs = OMAP54XX_PRM_WKUPAON_INST,
265 .prcm_partition = OMAP54XX_PRM_PARTITION,
266 .pwrsts = PWRSTS_ON,
267 .banks = 1,
268 .pwrsts_mem_ret = {
269 },
270 .pwrsts_mem_on = {
271 [0] = PWRSTS_ON, /* wkup_bank */
272 },
273};
274
275/* iva_54xx_pwrdm: IVA-HD power domain */
276static struct powerdomain iva_54xx_pwrdm = {
277 .name = "iva_pwrdm",
278 .voltdm = { .name = "mm" },
279 .prcm_offs = OMAP54XX_PRM_IVA_INST,
280 .prcm_partition = OMAP54XX_PRM_PARTITION,
281 .pwrsts = PWRSTS_OFF_RET_ON,
282 .pwrsts_logic_ret = PWRSTS_OFF,
283 .banks = 4,
284 .pwrsts_mem_ret = {
285 [0] = PWRSTS_OFF_RET, /* hwa_mem */
286 [1] = PWRSTS_OFF_RET, /* sl2_mem */
287 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
288 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
289 },
290 .pwrsts_mem_on = {
291 [0] = PWRSTS_OFF_RET, /* hwa_mem */
292 [1] = PWRSTS_OFF_RET, /* sl2_mem */
293 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
294 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
295 },
296 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
297};
298
299/*
300 * The following power domains are not under SW control
301 *
302 * mpuaon
303 * mmaon
304 */
305
306/* As powerdomains are added or removed above, this list must also be changed */
307static struct powerdomain *powerdomains_omap54xx[] __initdata = {
308 &core_54xx_pwrdm,
309 &abe_54xx_pwrdm,
310 &coreaon_54xx_pwrdm,
311 &dss_54xx_pwrdm,
312 &cpu0_54xx_pwrdm,
313 &cpu1_54xx_pwrdm,
314 &emu_54xx_pwrdm,
315 &mpu_54xx_pwrdm,
316 &custefuse_54xx_pwrdm,
317 &dsp_54xx_pwrdm,
318 &cam_54xx_pwrdm,
319 &l3init_54xx_pwrdm,
320 &gpu_54xx_pwrdm,
321 &wkupaon_54xx_pwrdm,
322 &iva_54xx_pwrdm,
323 NULL
324};
325
326void __init omap54xx_powerdomains_init(void)
327{
328 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
329 pwrdm_register_pwrdms(powerdomains_omap54xx);
330 pwrdm_complete_init();
331}
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index 7334ffb9d2c1..f429cdd5a118 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -32,6 +32,12 @@
32#define OMAP4430_SCRM_PARTITION 4 32#define OMAP4430_SCRM_PARTITION 4
33#define OMAP4430_PRCM_MPU_PARTITION 5 33#define OMAP4430_PRCM_MPU_PARTITION 5
34 34
35#define OMAP54XX_PRM_PARTITION 1
36#define OMAP54XX_CM_CORE_AON_PARTITION 2
37#define OMAP54XX_CM_CORE_PARTITION 3
38#define OMAP54XX_SCRM_PARTITION 4
39#define OMAP54XX_PRCM_MPU_PARTITION 5
40
35/* 41/*
36 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition 42 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
37 * IDs, plus one 43 * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 884af7bb4afd..059bd4f49035 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -25,12 +25,9 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
26#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 26#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
27 27
28#include "prcm_mpu_44xx_54xx.h"
28#include "common.h" 29#include "common.h"
29 30
30# ifndef __ASSEMBLER__
31extern void __iomem *prcm_mpu_base;
32# endif
33
34#define OMAP4430_PRCM_MPU_BASE 0x48243000 31#define OMAP4430_PRCM_MPU_BASE 0x48243000
35 32
36#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ 33#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
98#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 95#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
99#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) 96#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
100 97
101/* Function prototypes */
102# ifndef __ASSEMBLER__
103extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
104extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
105extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
106 s16 idx);
107extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
108# endif
109
110#endif 98#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
new file mode 100644
index 000000000000..bc2ce3288315
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -0,0 +1,87 @@
1/*
2 * OMAP54xx PRCM MPU instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
22#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
23
24#include "prcm_mpu_44xx_54xx.h"
25#include "common.h"
26
27#define OMAP54XX_PRCM_MPU_BASE 0x48243000
28
29#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
31
32/* PRCM_MPU instances */
33#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST 0x0000
34#define OMAP54XX_PRCM_MPU_DEVICE_INST 0x0200
35#define OMAP54XX_PRCM_MPU_PRM_C0_INST 0x0400
36#define OMAP54XX_PRCM_MPU_CM_C0_INST 0x0600
37#define OMAP54XX_PRCM_MPU_PRM_C1_INST 0x0800
38#define OMAP54XX_PRCM_MPU_CM_C1_INST 0x0a00
39
40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS 0x0000
42#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS 0x0000
43
44
45/*
46 * PRCM_MPU
47 *
48 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
49 * point of view the PRCM_MPU is a single entity. It shares the same
50 * programming model as the global PRCM and thus can be assimilate as two new
51 * MOD inside the PRCM
52 */
53
54/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
55#define OMAP54XX_REVISION_PRCM_MPU_OFFSET 0x0000
56
57/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
58#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
59#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
60#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
61#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
62
63/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
64#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
65#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET 0x0004
66#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
67#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
68#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
69
70/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
71#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
72#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
73#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
74
75/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
76#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
77#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET 0x0004
78#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
79#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
80#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
81
82/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
83#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
84#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
85#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
86
87#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
new file mode 100644
index 000000000000..ca149e70bed0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -0,0 +1,36 @@
1/*
2 * OMAP44xx and OMAP54xx PRCM MPU function prototypes
3 *
4 * Copyright (C) 2010, 2013 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
25
26#ifndef __ASSEMBLER__
27extern void __iomem *prcm_mpu_base;
28
29extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
30extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
31extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
32 s16 idx);
33extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
34#endif
35
36#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h
new file mode 100644
index 000000000000..be31b21aa9c6
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-54xx.h
@@ -0,0 +1,2701 @@
1/*
2 * OMAP54xx Power Management register bits
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
23
24/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
25#define OMAP54XX_ABBOFF_ACT_SHIFT 1
26#define OMAP54XX_ABBOFF_ACT_WIDTH 0x1
27#define OMAP54XX_ABBOFF_ACT_MASK (1 << 1)
28
29/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
30#define OMAP54XX_ABBOFF_SLEEP_SHIFT 2
31#define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1
32#define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2)
33
34/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
35#define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31
36#define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1
37#define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31)
38
39/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
40#define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31
41#define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1
42#define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31)
43
44/* Used by PRM_IRQENABLE_MPU_2 */
45#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7
46#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1
47#define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7)
48
49/* Used by PRM_IRQSTATUS_MPU_2 */
50#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7
51#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1
52#define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7)
53
54/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
55#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2
56#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1
57#define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2)
58
59/* Used by PM_ABE_PWRSTCTRL */
60#define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16
61#define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2
62#define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16)
63
64/* Used by PM_ABE_PWRSTCTRL */
65#define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8
66#define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1
67#define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8)
68
69/* Used by PM_ABE_PWRSTST */
70#define OMAP54XX_AESSMEM_STATEST_SHIFT 4
71#define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2
72#define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4)
73
74/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
75#define OMAP54XX_AIPOFF_SHIFT 8
76#define OMAP54XX_AIPOFF_WIDTH 0x1
77#define OMAP54XX_AIPOFF_MASK (1 << 8)
78
79/* Used by PRM_VOLTCTRL */
80#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0
81#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2
82#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
83
84/* Used by PRM_VOLTCTRL */
85#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4
86#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2
87#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4)
88
89/* Used by PRM_VOLTCTRL */
90#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2
91#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2
92#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
93
94/* Used by PRM_VC_BYPASS_ERRST */
95#define OMAP54XX_BYPS_RA_ERR_SHIFT 1
96#define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1
97#define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1)
98
99/* Used by PRM_VC_BYPASS_ERRST */
100#define OMAP54XX_BYPS_SA_ERR_SHIFT 0
101#define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1
102#define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0)
103
104/* Used by PRM_VC_BYPASS_ERRST */
105#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2
106#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1
107#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2)
108
109/* Used by PRM_RSTST */
110#define OMAP54XX_C2C_RST_SHIFT 10
111#define OMAP54XX_C2C_RST_WIDTH 0x1
112#define OMAP54XX_C2C_RST_MASK (1 << 10)
113
114/* Used by PM_CAM_PWRSTCTRL */
115#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16
116#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2
117#define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16)
118
119/* Used by PM_CAM_PWRSTST */
120#define OMAP54XX_CAM_MEM_STATEST_SHIFT 4
121#define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2
122#define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4)
123
124/* Used by PRM_CLKREQCTRL */
125#define OMAP54XX_CLKREQ_COND_SHIFT 0
126#define OMAP54XX_CLKREQ_COND_WIDTH 0x3
127#define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0)
128
129/* Used by PRM_VC_SMPS_CORE_CONFIG */
130#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16
131#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8
132#define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16)
133
134/* Used by PRM_VC_SMPS_MM_CONFIG */
135#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16
136#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8
137#define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16)
138
139/* Used by PRM_VC_SMPS_MPU_CONFIG */
140#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16
141#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8
142#define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16)
143
144/* Used by PRM_VC_SMPS_CORE_CONFIG */
145#define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28
146#define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1
147#define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28)
148
149/* Used by PRM_VC_SMPS_MM_CONFIG */
150#define OMAP54XX_CMD_VDD_MM_L_SHIFT 28
151#define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1
152#define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28)
153
154/* Used by PRM_VC_SMPS_MPU_CONFIG */
155#define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28
156#define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1
157#define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28)
158
159/* Used by PM_CORE_PWRSTCTRL */
160#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18
161#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2
162#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
163
164/* Used by PM_CORE_PWRSTCTRL */
165#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9
166#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1
167#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
168
169/* Used by PM_CORE_PWRSTST */
170#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6
171#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2
172#define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
173
174/* Used by PM_CORE_PWRSTCTRL */
175#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16
176#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2
177#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
178
179/* Used by PM_CORE_PWRSTCTRL */
180#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8
181#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1
182#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
183
184/* Used by PM_CORE_PWRSTST */
185#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4
186#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2
187#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
188
189/* Used by REVISION_PRM */
190#define OMAP54XX_CUSTOM_SHIFT 6
191#define OMAP54XX_CUSTOM_WIDTH 0x2
192#define OMAP54XX_CUSTOM_MASK (0x3 << 6)
193
194/* Used by PRM_VC_VAL_BYPASS */
195#define OMAP54XX_DATA_SHIFT 16
196#define OMAP54XX_DATA_WIDTH 0x8
197#define OMAP54XX_DATA_MASK (0xff << 16)
198
199/* Used by PRM_DEBUG_CORE_RET_TRANS */
200#define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0
201#define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c
202#define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0)
203
204/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */
205#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
206#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
207#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
208
209/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */
210#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
211#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
212#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
213
214/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */
215#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
216#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
217#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
218
219/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */
220#define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0
221#define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc
222#define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0)
223
224/* Used by PRM_DEVICE_OFF_CTRL */
225#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0
226#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1
227#define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0)
228
229/* Used by PRM_VC_CFG_I2C_MODE */
230#define OMAP54XX_DFILTEREN_SHIFT 6
231#define OMAP54XX_DFILTEREN_WIDTH 0x1
232#define OMAP54XX_DFILTEREN_MASK (1 << 6)
233
234/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
235#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4
236#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1
237#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4)
238
239/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
240#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4
241#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1
242#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4)
243
244/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
245#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0
246#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1
247#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0)
248
249/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
250#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0
251#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1
252#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0)
253
254/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
255#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2
256#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1
257#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2)
258
259/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
260#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2
261#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1
262#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2)
263
264/* Used by PRM_IRQENABLE_MPU */
265#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1
266#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1
267#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1)
268
269/* Used by PRM_IRQSTATUS_MPU */
270#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1
271#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1
272#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1)
273
274/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
275#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3
276#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1
277#define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3)
278
279/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
280#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3
281#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1
282#define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3)
283
284/* Used by PM_DSP_PWRSTCTRL */
285#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20
286#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2
287#define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20)
288
289/* Used by PM_DSP_PWRSTCTRL */
290#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10
291#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1
292#define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10)
293
294/* Used by PM_DSP_PWRSTST */
295#define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8
296#define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2
297#define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8)
298
299/* Used by PM_DSP_PWRSTCTRL */
300#define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16
301#define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2
302#define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16)
303
304/* Used by PM_DSP_PWRSTCTRL */
305#define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8
306#define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1
307#define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8)
308
309/* Used by PM_DSP_PWRSTST */
310#define OMAP54XX_DSP_L1_STATEST_SHIFT 4
311#define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2
312#define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4)
313
314/* Used by PM_DSP_PWRSTCTRL */
315#define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18
316#define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2
317#define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18)
318
319/* Used by PM_DSP_PWRSTCTRL */
320#define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9
321#define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1
322#define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9)
323
324/* Used by PM_DSP_PWRSTST */
325#define OMAP54XX_DSP_L2_STATEST_SHIFT 6
326#define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2
327#define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6)
328
329/* Used by PM_DSS_PWRSTCTRL */
330#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16
331#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2
332#define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16)
333
334/* Used by PM_DSS_PWRSTCTRL */
335#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8
336#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1
337#define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8)
338
339/* Used by PM_DSS_PWRSTST */
340#define OMAP54XX_DSS_MEM_STATEST_SHIFT 4
341#define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2
342#define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4)
343
344/* Used by PRM_DEVICE_OFF_CTRL */
345#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8
346#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1
347#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
348
349/* Used by PRM_DEVICE_OFF_CTRL */
350#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9
351#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1
352#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
353
354/* Used by PM_EMU_PWRSTCTRL */
355#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16
356#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2
357#define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16)
358
359/* Used by PM_EMU_PWRSTST */
360#define OMAP54XX_EMU_BANK_STATEST_SHIFT 4
361#define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2
362#define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4)
363
364/*
365 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP,
366 * PRM_SRAM_WKUP_SETUP
367 */
368#define OMAP54XX_ENABLE_RTA_SHIFT 0
369#define OMAP54XX_ENABLE_RTA_WIDTH 0x1
370#define OMAP54XX_ENABLE_RTA_MASK (1 << 0)
371
372/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
373#define OMAP54XX_ENFUNC1_SHIFT 3
374#define OMAP54XX_ENFUNC1_WIDTH 0x1
375#define OMAP54XX_ENFUNC1_MASK (1 << 3)
376
377/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
378#define OMAP54XX_ENFUNC2_SHIFT 4
379#define OMAP54XX_ENFUNC2_WIDTH 0x1
380#define OMAP54XX_ENFUNC2_MASK (1 << 4)
381
382/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
383#define OMAP54XX_ENFUNC3_SHIFT 5
384#define OMAP54XX_ENFUNC3_WIDTH 0x1
385#define OMAP54XX_ENFUNC3_MASK (1 << 5)
386
387/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
388#define OMAP54XX_ENFUNC4_SHIFT 6
389#define OMAP54XX_ENFUNC4_WIDTH 0x1
390#define OMAP54XX_ENFUNC4_MASK (1 << 6)
391
392/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
393#define OMAP54XX_ENFUNC5_SHIFT 7
394#define OMAP54XX_ENFUNC5_WIDTH 0x1
395#define OMAP54XX_ENFUNC5_MASK (1 << 7)
396
397/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
398#define OMAP54XX_ERRORGAIN_SHIFT 16
399#define OMAP54XX_ERRORGAIN_WIDTH 0x8
400#define OMAP54XX_ERRORGAIN_MASK (0xff << 16)
401
402/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
403#define OMAP54XX_ERROROFFSET_SHIFT 24
404#define OMAP54XX_ERROROFFSET_WIDTH 0x8
405#define OMAP54XX_ERROROFFSET_MASK (0xff << 24)
406
407/* Used by PRM_RSTST */
408#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5
409#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1
410#define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5)
411
412/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
413#define OMAP54XX_FORCEUPDATE_SHIFT 1
414#define OMAP54XX_FORCEUPDATE_WIDTH 0x1
415#define OMAP54XX_FORCEUPDATE_MASK (1 << 1)
416
417/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
418#define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8
419#define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18
420#define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8)
421
422/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */
423#define OMAP54XX_FORCEWKUP_EN_SHIFT 10
424#define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1
425#define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10)
426
427/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */
428#define OMAP54XX_FORCEWKUP_ST_SHIFT 10
429#define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1
430#define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10)
431
432/* Used by REVISION_PRM */
433#define OMAP54XX_FUNC_SHIFT 16
434#define OMAP54XX_FUNC_WIDTH 0xc
435#define OMAP54XX_FUNC_MASK (0xfff << 16)
436
437/* Used by PRM_RSTST */
438#define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0
439#define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1
440#define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0)
441
442/* Used by PRM_RSTST */
443#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1
444#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1
445#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
446
447/* Used by PRM_IO_PMCTRL */
448#define OMAP54XX_GLOBAL_WUEN_SHIFT 16
449#define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1
450#define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16)
451
452/* Used by PM_GPU_PWRSTCTRL */
453#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16
454#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2
455#define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16)
456
457/* Used by PM_GPU_PWRSTST */
458#define OMAP54XX_GPU_MEM_STATEST_SHIFT 4
459#define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2
460#define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4)
461
462/* Used by PRM_VC_CFG_I2C_MODE */
463#define OMAP54XX_HSMCODE_SHIFT 0
464#define OMAP54XX_HSMCODE_WIDTH 0x3
465#define OMAP54XX_HSMCODE_MASK (0x7 << 0)
466
467/* Used by PRM_VC_CFG_I2C_MODE */
468#define OMAP54XX_HSMODEEN_SHIFT 3
469#define OMAP54XX_HSMODEEN_WIDTH 0x1
470#define OMAP54XX_HSMODEEN_MASK (1 << 3)
471
472/* Used by PRM_VC_CFG_I2C_CLK */
473#define OMAP54XX_HSSCLH_SHIFT 16
474#define OMAP54XX_HSSCLH_WIDTH 0x8
475#define OMAP54XX_HSSCLH_MASK (0xff << 16)
476
477/* Used by PRM_VC_CFG_I2C_CLK */
478#define OMAP54XX_HSSCLL_SHIFT 24
479#define OMAP54XX_HSSCLL_WIDTH 0x8
480#define OMAP54XX_HSSCLL_MASK (0xff << 24)
481
482/* Used by PM_IVA_PWRSTCTRL */
483#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16
484#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2
485#define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16)
486
487/* Used by PM_IVA_PWRSTCTRL */
488#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8
489#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1
490#define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8)
491
492/* Used by PM_IVA_PWRSTST */
493#define OMAP54XX_HWA_MEM_STATEST_SHIFT 4
494#define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2
495#define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4)
496
497/* Used by PRM_RSTST */
498#define OMAP54XX_ICEPICK_RST_SHIFT 9
499#define OMAP54XX_ICEPICK_RST_WIDTH 0x1
500#define OMAP54XX_ICEPICK_RST_MASK (1 << 9)
501
502/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
503#define OMAP54XX_INITVDD_SHIFT 2
504#define OMAP54XX_INITVDD_WIDTH 0x1
505#define OMAP54XX_INITVDD_MASK (1 << 2)
506
507/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
508#define OMAP54XX_INITVOLTAGE_SHIFT 8
509#define OMAP54XX_INITVOLTAGE_WIDTH 0x8
510#define OMAP54XX_INITVOLTAGE_MASK (0xff << 8)
511
512/*
513 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
514 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
515 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST,
516 * PRM_VOLTST_MM, PRM_VOLTST_MPU
517 */
518#define OMAP54XX_INTRANSITION_SHIFT 20
519#define OMAP54XX_INTRANSITION_WIDTH 0x1
520#define OMAP54XX_INTRANSITION_MASK (1 << 20)
521
522/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
523#define OMAP54XX_IO_EN_SHIFT 9
524#define OMAP54XX_IO_EN_WIDTH 0x1
525#define OMAP54XX_IO_EN_MASK (1 << 9)
526
527/* Used by PRM_IO_PMCTRL */
528#define OMAP54XX_IO_ON_STATUS_SHIFT 5
529#define OMAP54XX_IO_ON_STATUS_WIDTH 0x1
530#define OMAP54XX_IO_ON_STATUS_MASK (1 << 5)
531
532/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
533#define OMAP54XX_IO_ST_SHIFT 9
534#define OMAP54XX_IO_ST_WIDTH 0x1
535#define OMAP54XX_IO_ST_MASK (1 << 9)
536
537/* Used by PM_CORE_PWRSTCTRL */
538#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20
539#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2
540#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20)
541
542/* Used by PM_CORE_PWRSTCTRL */
543#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10
544#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1
545#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10)
546
547/* Used by PM_CORE_PWRSTST */
548#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8
549#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2
550#define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8)
551
552/* Used by PM_CORE_PWRSTCTRL */
553#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22
554#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2
555#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22)
556
557/* Used by PM_CORE_PWRSTCTRL */
558#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11
559#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1
560#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11)
561
562/* Used by PM_CORE_PWRSTST */
563#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10
564#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2
565#define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10)
566
567/* Used by PRM_IO_PMCTRL */
568#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0
569#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1
570#define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0)
571
572/* Used by PRM_IO_PMCTRL */
573#define OMAP54XX_ISOCLK_STATUS_SHIFT 1
574#define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1
575#define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1)
576
577/* Used by PRM_IO_PMCTRL */
578#define OMAP54XX_ISOOVR_EXTEND_SHIFT 4
579#define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1
580#define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4)
581
582/* Used by PRM_IO_COUNT */
583#define OMAP54XX_ISO_2_ON_TIME_SHIFT 0
584#define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8
585#define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0)
586
587/* Used by PM_L3INIT_PWRSTCTRL */
588#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16
589#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2
590#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16)
591
592/* Used by PM_L3INIT_PWRSTCTRL */
593#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8
594#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1
595#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
596
597/* Used by PM_L3INIT_PWRSTST */
598#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4
599#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2
600#define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
601
602/* Used by PM_L3INIT_PWRSTCTRL */
603#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18
604#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2
605#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18)
606
607/* Used by PM_L3INIT_PWRSTCTRL */
608#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9
609#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1
610#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9)
611
612/* Used by PM_L3INIT_PWRSTST */
613#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6
614#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2
615#define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6)
616
617/*
618 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
619 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
620 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
621 */
622#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24
623#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2
624#define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
625
626/* Used by PRM_RSTST */
627#define OMAP54XX_LLI_RST_SHIFT 14
628#define OMAP54XX_LLI_RST_WIDTH 0x1
629#define OMAP54XX_LLI_RST_MASK (1 << 14)
630
631/*
632 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL,
633 * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
634 */
635#define OMAP54XX_LOGICRETSTATE_SHIFT 2
636#define OMAP54XX_LOGICRETSTATE_WIDTH 0x1
637#define OMAP54XX_LOGICRETSTATE_MASK (1 << 2)
638
639/*
640 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
641 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
642 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
643 */
644#define OMAP54XX_LOGICSTATEST_SHIFT 2
645#define OMAP54XX_LOGICSTATEST_WIDTH 0x1
646#define OMAP54XX_LOGICSTATEST_MASK (1 << 2)
647
648/*
649 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
650 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
651 * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT,
652 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
653 * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
654 * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT,
655 * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT,
656 * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,
657 * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
658 * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT,
659 * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
660 * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT,
661 * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT,
662 * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
663 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
664 * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
665 * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
666 * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT,
667 * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT,
668 * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
669 * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
670 * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
671 * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
672 * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
673 * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT,
674 * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT,
675 * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
676 * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT,
677 * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT,
678 * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT,
679 * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT,
680 * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
681 * RM_WKUPAON_WD_TIMER2_CONTEXT
682 */
683#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0
684#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1
685#define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0)
686
687/*
688 * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
689 * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT,
690 * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
691 * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT,
692 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
693 * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT,
694 * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
695 * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
696 * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT,
697 * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT,
698 * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
699 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
700 * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT,
701 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
702 * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
703 * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
704 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
705 * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
706 * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT
707 */
708#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1
709#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1
710#define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1)
711
712/* Used by RM_ABE_AESS_CONTEXT */
713#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8
714#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1
715#define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8)
716
717/* Used by RM_CAM_CAL_CONTEXT */
718#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8
719#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1
720#define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8)
721
722/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
723#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8
724#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1
725#define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8)
726
727/* Used by RM_EMIF_DMM_CONTEXT */
728#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9
729#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1
730#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9)
731
732/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
733#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8
734#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1
735#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8)
736
737/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */
738#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8
739#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1
740#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
741
742/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */
743#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
744#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1
745#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
746
747/* Used by RM_DSP_DSP_CONTEXT */
748#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10
749#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1
750#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10)
751
752/* Used by RM_DSP_DSP_CONTEXT */
753#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8
754#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1
755#define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8)
756
757/* Used by RM_DSP_DSP_CONTEXT */
758#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9
759#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1
760#define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9)
761
762/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
763#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8
764#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1
765#define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8)
766
767/* Used by RM_EMU_DEBUGSS_CONTEXT */
768#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8
769#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1
770#define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8)
771
772/* Used by RM_GPU_GPU_CONTEXT */
773#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8
774#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1
775#define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8)
776
777/* Used by RM_IVA_IVA_CONTEXT */
778#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10
779#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1
780#define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10)
781
782/* Used by RM_IPU_IPU_CONTEXT */
783#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9
784#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1
785#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9)
786
787/* Used by RM_IPU_IPU_CONTEXT */
788#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8
789#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1
790#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8)
791
792/*
793 * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT,
794 * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
795 * RM_L3INIT_USB_OTG_SS_CONTEXT
796 */
797#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8
798#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1
799#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
800
801/* Used by RM_MPU_MPU_CONTEXT */
802#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9
803#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1
804#define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9)
805
806/* Used by RM_MPU_MPU_CONTEXT */
807#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10
808#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1
809#define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10)
810
811/*
812 * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
813 * RM_L4SEC_FPKA_CONTEXT
814 */
815#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8
816#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1
817#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
818
819/*
820 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
821 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT
822 */
823#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8
824#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1
825#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8)
826
827/*
828 * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
829 * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
830 * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT
831 */
832#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8
833#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1
834#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
835
836/* Used by RM_IVA_SL2_CONTEXT */
837#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8
838#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1
839#define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8)
840
841/* Used by RM_IVA_IVA_CONTEXT */
842#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8
843#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1
844#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8)
845
846/* Used by RM_IVA_IVA_CONTEXT */
847#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9
848#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1
849#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9)
850
851/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
852#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8
853#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1
854#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8)
855
856/*
857 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
858 * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
859 * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
860 */
861#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4
862#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1
863#define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
864
865/* Used by PRM_DEBUG_TRANS_CFG */
866#define OMAP54XX_MODE_SHIFT 0
867#define OMAP54XX_MODE_WIDTH 0x2
868#define OMAP54XX_MODE_MASK (0x3 << 0)
869
870/* Used by PRM_MODEM_IF_CTRL */
871#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9
872#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1
873#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
874
875/* Used by PRM_MODEM_IF_CTRL */
876#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8
877#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1
878#define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8)
879
880/* Used by PM_MPU_PWRSTCTRL */
881#define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18
882#define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2
883#define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18)
884
885/* Used by PM_MPU_PWRSTCTRL */
886#define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9
887#define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1
888#define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9)
889
890/* Used by PM_MPU_PWRSTST */
891#define OMAP54XX_MPU_L2_STATEST_SHIFT 6
892#define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2
893#define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6)
894
895/* Used by PM_MPU_PWRSTCTRL */
896#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20
897#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2
898#define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20)
899
900/* Used by PM_MPU_PWRSTCTRL */
901#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10
902#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1
903#define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10)
904
905/* Used by PM_MPU_PWRSTST */
906#define OMAP54XX_MPU_RAM_STATEST_SHIFT 8
907#define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2
908#define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8)
909
910/* Used by PRM_RSTST */
911#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2
912#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1
913#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
914
915/* Used by PRM_RSTST */
916#define OMAP54XX_MPU_WDT_RST_SHIFT 3
917#define OMAP54XX_MPU_WDT_RST_WIDTH 0x1
918#define OMAP54XX_MPU_WDT_RST_MASK (1 << 3)
919
920/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
921#define OMAP54XX_NOCAP_SHIFT 4
922#define OMAP54XX_NOCAP_WIDTH 0x1
923#define OMAP54XX_NOCAP_MASK (1 << 4)
924
925/* Used by PM_CORE_PWRSTCTRL */
926#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24
927#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2
928#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
929
930/* Used by PM_CORE_PWRSTCTRL */
931#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12
932#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1
933#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
934
935/* Used by PM_CORE_PWRSTST */
936#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12
937#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2
938#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
939
940/*
941 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
942 * PRM_VC_VAL_CMD_VDD_MPU_L
943 */
944#define OMAP54XX_OFF_SHIFT 0
945#define OMAP54XX_OFF_WIDTH 0x8
946#define OMAP54XX_OFF_MASK (0xff << 0)
947
948/*
949 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
950 * PRM_VC_VAL_CMD_VDD_MPU_L
951 */
952#define OMAP54XX_ON_SHIFT 24
953#define OMAP54XX_ON_WIDTH 0x8
954#define OMAP54XX_ON_MASK (0xff << 24)
955
956/*
957 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
958 * PRM_VC_VAL_CMD_VDD_MPU_L
959 */
960#define OMAP54XX_ONLP_SHIFT 16
961#define OMAP54XX_ONLP_WIDTH 0x8
962#define OMAP54XX_ONLP_MASK (0xff << 16)
963
964/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
965#define OMAP54XX_OPP_CHANGE_SHIFT 2
966#define OMAP54XX_OPP_CHANGE_WIDTH 0x1
967#define OMAP54XX_OPP_CHANGE_MASK (1 << 2)
968
969/* Used by PRM_VC_VAL_BYPASS */
970#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25
971#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1
972#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25)
973
974/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
975#define OMAP54XX_OPP_SEL_SHIFT 0
976#define OMAP54XX_OPP_SEL_WIDTH 0x2
977#define OMAP54XX_OPP_SEL_MASK (0x3 << 0)
978
979/* Used by PRM_DEBUG_OUT */
980#define OMAP54XX_OUTPUT_SHIFT 0
981#define OMAP54XX_OUTPUT_WIDTH 0x20
982#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
983
984/* Used by PRM_SRAM_COUNT */
985#define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0
986#define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6
987#define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
988
989/* Used by PRM_PSCON_COUNT */
990#define OMAP54XX_PCHARGE_TIME_SHIFT 0
991#define OMAP54XX_PCHARGE_TIME_WIDTH 0x8
992#define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0)
993
994/* Used by PM_ABE_PWRSTCTRL */
995#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20
996#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2
997#define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
998
999/* Used by PM_ABE_PWRSTCTRL */
1000#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10
1001#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1
1002#define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10)
1003
1004/* Used by PM_ABE_PWRSTST */
1005#define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8
1006#define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2
1007#define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8)
1008
1009/* Used by PRM_PHASE1_CNDP */
1010#define OMAP54XX_PHASE1_CNDP_SHIFT 0
1011#define OMAP54XX_PHASE1_CNDP_WIDTH 0x20
1012#define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0)
1013
1014/* Used by PRM_PHASE2A_CNDP */
1015#define OMAP54XX_PHASE2A_CNDP_SHIFT 0
1016#define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20
1017#define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0)
1018
1019/* Used by PRM_PHASE2B_CNDP */
1020#define OMAP54XX_PHASE2B_CNDP_SHIFT 0
1021#define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20
1022#define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0)
1023
1024/* Used by PRM_PSCON_COUNT */
1025#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8
1026#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8
1027#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
1028
1029/*
1030 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
1031 * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
1032 * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
1033 * PM_MPU_PWRSTCTRL
1034 */
1035#define OMAP54XX_POWERSTATE_SHIFT 0
1036#define OMAP54XX_POWERSTATE_WIDTH 0x2
1037#define OMAP54XX_POWERSTATE_MASK (0x3 << 0)
1038
1039/*
1040 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
1041 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
1042 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
1043 */
1044#define OMAP54XX_POWERSTATEST_SHIFT 0
1045#define OMAP54XX_POWERSTATEST_WIDTH 0x2
1046#define OMAP54XX_POWERSTATEST_MASK (0x3 << 0)
1047
1048/* Used by PRM_PWRREQCTRL */
1049#define OMAP54XX_PWRREQ_COND_SHIFT 0
1050#define OMAP54XX_PWRREQ_COND_WIDTH 0x2
1051#define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0)
1052
1053/* Used by PRM_VC_SMPS_CORE_CONFIG */
1054#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27
1055#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1
1056#define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27)
1057
1058/* Used by PRM_VC_SMPS_MM_CONFIG */
1059#define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27
1060#define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1
1061#define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27)
1062
1063/* Used by PRM_VC_SMPS_MPU_CONFIG */
1064#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27
1065#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1
1066#define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27)
1067
1068/* Used by PRM_VC_SMPS_CORE_CONFIG */
1069#define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26
1070#define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1
1071#define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26)
1072
1073/* Used by PRM_VC_SMPS_MM_CONFIG */
1074#define OMAP54XX_RAC_VDD_MM_L_SHIFT 26
1075#define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1
1076#define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26)
1077
1078/* Used by PRM_VC_SMPS_MPU_CONFIG */
1079#define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26
1080#define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1
1081#define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26)
1082
1083/*
1084 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1085 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1086 * PRM_VOLTSETUP_MPU_RET_SLEEP
1087 */
1088#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16
1089#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6
1090#define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16)
1091
1092/*
1093 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1094 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1095 * PRM_VOLTSETUP_MPU_RET_SLEEP
1096 */
1097#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24
1098#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2
1099#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
1100
1101/*
1102 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1103 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1104 * PRM_VOLTSETUP_MPU_RET_SLEEP
1105 */
1106#define OMAP54XX_RAMP_UP_COUNT_SHIFT 0
1107#define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6
1108#define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0)
1109
1110/*
1111 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1112 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1113 * PRM_VOLTSETUP_MPU_RET_SLEEP
1114 */
1115#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8
1116#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2
1117#define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8)
1118
1119/* Used by PRM_VC_SMPS_CORE_CONFIG */
1120#define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25
1121#define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1
1122#define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25)
1123
1124/* Used by PRM_VC_SMPS_MM_CONFIG */
1125#define OMAP54XX_RAV_VDD_MM_L_SHIFT 25
1126#define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1
1127#define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25)
1128
1129/* Used by PRM_VC_SMPS_MPU_CONFIG */
1130#define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25
1131#define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1
1132#define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25)
1133
1134/* Used by PRM_VC_VAL_BYPASS */
1135#define OMAP54XX_REGADDR_SHIFT 8
1136#define OMAP54XX_REGADDR_WIDTH 0x8
1137#define OMAP54XX_REGADDR_MASK (0xff << 8)
1138
1139/*
1140 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
1141 * PRM_VC_VAL_CMD_VDD_MPU_L
1142 */
1143#define OMAP54XX_RET_SHIFT 8
1144#define OMAP54XX_RET_WIDTH 0x8
1145#define OMAP54XX_RET_MASK (0xff << 8)
1146
1147/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1148#define OMAP54XX_RETMODE_ENABLE_SHIFT 0
1149#define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1
1150#define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0)
1151
1152/* Used by PRM_RSTTIME */
1153#define OMAP54XX_RSTTIME1_SHIFT 0
1154#define OMAP54XX_RSTTIME1_WIDTH 0xa
1155#define OMAP54XX_RSTTIME1_MASK (0x3ff << 0)
1156
1157/* Used by PRM_RSTTIME */
1158#define OMAP54XX_RSTTIME2_SHIFT 10
1159#define OMAP54XX_RSTTIME2_WIDTH 0x5
1160#define OMAP54XX_RSTTIME2_MASK (0x1f << 10)
1161
1162/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1163#define OMAP54XX_RST_CPU0_SHIFT 0
1164#define OMAP54XX_RST_CPU0_WIDTH 0x1
1165#define OMAP54XX_RST_CPU0_MASK (1 << 0)
1166
1167/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1168#define OMAP54XX_RST_CPU1_SHIFT 1
1169#define OMAP54XX_RST_CPU1_WIDTH 0x1
1170#define OMAP54XX_RST_CPU1_MASK (1 << 1)
1171
1172/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
1173#define OMAP54XX_RST_DSP_SHIFT 0
1174#define OMAP54XX_RST_DSP_WIDTH 0x1
1175#define OMAP54XX_RST_DSP_MASK (1 << 0)
1176
1177/* Used by RM_DSP_RSTST */
1178#define OMAP54XX_RST_DSP_EMU_SHIFT 2
1179#define OMAP54XX_RST_DSP_EMU_WIDTH 0x1
1180#define OMAP54XX_RST_DSP_EMU_MASK (1 << 2)
1181
1182/* Used by RM_DSP_RSTST */
1183#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3
1184#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1
1185#define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3)
1186
1187/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
1188#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1
1189#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1
1190#define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1)
1191
1192/* Used by RM_IPU_RSTST */
1193#define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3
1194#define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1
1195#define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3)
1196
1197/* Used by RM_IPU_RSTST */
1198#define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4
1199#define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1
1200#define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4)
1201
1202/* Used by RM_IVA_RSTST */
1203#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3
1204#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1
1205#define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3)
1206
1207/* Used by RM_IVA_RSTST */
1208#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4
1209#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1
1210#define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4)
1211
1212/* Used by PRM_RSTCTRL */
1213#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1
1214#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1
1215#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
1216
1217/* Used by PRM_RSTCTRL */
1218#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0
1219#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1
1220#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
1221
1222/* Used by RM_IPU_RSTST */
1223#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5
1224#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1
1225#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5)
1226
1227/* Used by RM_IPU_RSTST */
1228#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6
1229#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1
1230#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6)
1231
1232/* Used by RM_IVA_RSTST */
1233#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5
1234#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1
1235#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5)
1236
1237/* Used by RM_IVA_RSTST */
1238#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6
1239#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1
1240#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6)
1241
1242/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1243#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2
1244#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1
1245#define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2)
1246
1247/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1248#define OMAP54XX_RST_LOGIC_SHIFT 2
1249#define OMAP54XX_RST_LOGIC_WIDTH 0x1
1250#define OMAP54XX_RST_LOGIC_MASK (1 << 2)
1251
1252/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1253#define OMAP54XX_RST_SEQ1_SHIFT 0
1254#define OMAP54XX_RST_SEQ1_WIDTH 0x1
1255#define OMAP54XX_RST_SEQ1_MASK (1 << 0)
1256
1257/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1258#define OMAP54XX_RST_SEQ2_SHIFT 1
1259#define OMAP54XX_RST_SEQ2_WIDTH 0x1
1260#define OMAP54XX_RST_SEQ2_MASK (1 << 1)
1261
1262/* Used by REVISION_PRM */
1263#define OMAP54XX_R_RTL_SHIFT 11
1264#define OMAP54XX_R_RTL_WIDTH 0x5
1265#define OMAP54XX_R_RTL_MASK (0x1f << 11)
1266
1267/* Used by PRM_VC_SMPS_CORE_CONFIG */
1268#define OMAP54XX_SA_VDD_CORE_L_SHIFT 0
1269#define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7
1270#define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0)
1271
1272/* Used by PRM_VC_SMPS_MM_CONFIG */
1273#define OMAP54XX_SA_VDD_MM_L_SHIFT 0
1274#define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7
1275#define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0)
1276
1277/* Used by PRM_VC_SMPS_MPU_CONFIG */
1278#define OMAP54XX_SA_VDD_MPU_L_SHIFT 0
1279#define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7
1280#define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0)
1281
1282/* Used by REVISION_PRM */
1283#define OMAP54XX_SCHEME_SHIFT 30
1284#define OMAP54XX_SCHEME_WIDTH 0x2
1285#define OMAP54XX_SCHEME_MASK (0x3 << 30)
1286
1287/* Used by PRM_VC_CFG_I2C_CLK */
1288#define OMAP54XX_SCLH_SHIFT 0
1289#define OMAP54XX_SCLH_WIDTH 0x8
1290#define OMAP54XX_SCLH_MASK (0xff << 0)
1291
1292/* Used by PRM_VC_CFG_I2C_CLK */
1293#define OMAP54XX_SCLL_SHIFT 8
1294#define OMAP54XX_SCLL_WIDTH 0x8
1295#define OMAP54XX_SCLL_MASK (0xff << 8)
1296
1297/* Used by PRM_RSTST */
1298#define OMAP54XX_SECURE_WDT_RST_SHIFT 4
1299#define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1
1300#define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4)
1301
1302/* Used by PRM_VC_SMPS_CORE_CONFIG */
1303#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24
1304#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1
1305#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24)
1306
1307/* Used by PRM_VC_SMPS_MM_CONFIG */
1308#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24
1309#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1
1310#define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24)
1311
1312/* Used by PRM_VC_SMPS_MPU_CONFIG */
1313#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24
1314#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1
1315#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24)
1316
1317/* Used by PM_IVA_PWRSTCTRL */
1318#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18
1319#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2
1320#define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18)
1321
1322/* Used by PM_IVA_PWRSTCTRL */
1323#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9
1324#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1
1325#define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9)
1326
1327/* Used by PM_IVA_PWRSTST */
1328#define OMAP54XX_SL2_MEM_STATEST_SHIFT 6
1329#define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2
1330#define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6)
1331
1332/* Used by PRM_VC_VAL_BYPASS */
1333#define OMAP54XX_SLAVEADDR_SHIFT 0
1334#define OMAP54XX_SLAVEADDR_WIDTH 0x7
1335#define OMAP54XX_SLAVEADDR_MASK (0x7f << 0)
1336
1337/* Used by PRM_SRAM_COUNT */
1338#define OMAP54XX_SLPCNT_VALUE_SHIFT 16
1339#define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8
1340#define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16)
1341
1342/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1343#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8
1344#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10
1345#define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8)
1346
1347/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1348#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8
1349#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10
1350#define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8)
1351
1352/* Used by PRM_VC_CORE_ERRST */
1353#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1
1354#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1
1355#define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1)
1356
1357/* Used by PRM_VC_MM_ERRST */
1358#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1
1359#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1
1360#define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1)
1361
1362/* Used by PRM_VC_MPU_ERRST */
1363#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1
1364#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1
1365#define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1)
1366
1367/* Used by PRM_VC_CORE_ERRST */
1368#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0
1369#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1
1370#define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0)
1371
1372/* Used by PRM_VC_MM_ERRST */
1373#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0
1374#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1
1375#define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0)
1376
1377/* Used by PRM_VC_MPU_ERRST */
1378#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0
1379#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1
1380#define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0)
1381
1382/* Used by PRM_VC_CORE_ERRST */
1383#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2
1384#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1
1385#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2)
1386
1387/* Used by PRM_VC_MM_ERRST */
1388#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2
1389#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1
1390#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2)
1391
1392/* Used by PRM_VC_MPU_ERRST */
1393#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2
1394#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1
1395#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2)
1396
1397/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
1398#define OMAP54XX_SR2EN_SHIFT 0
1399#define OMAP54XX_SR2EN_WIDTH 0x1
1400#define OMAP54XX_SR2EN_MASK (1 << 0)
1401
1402/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
1403#define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6
1404#define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1
1405#define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6)
1406
1407/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
1408#define OMAP54XX_SR2_STATUS_SHIFT 3
1409#define OMAP54XX_SR2_STATUS_WIDTH 0x2
1410#define OMAP54XX_SR2_STATUS_MASK (0x3 << 3)
1411
1412/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
1413#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8
1414#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8
1415#define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8)
1416
1417/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1418#define OMAP54XX_SRAMLDO_STATUS_SHIFT 8
1419#define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1
1420#define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8)
1421
1422/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1423#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9
1424#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1
1425#define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9)
1426
1427/* Used by PRM_VC_CFG_I2C_MODE */
1428#define OMAP54XX_SRMODEEN_SHIFT 4
1429#define OMAP54XX_SRMODEEN_WIDTH 0x1
1430#define OMAP54XX_SRMODEEN_MASK (1 << 4)
1431
1432/* Used by PRM_VOLTSETUP_WARMRESET */
1433#define OMAP54XX_STABLE_COUNT_SHIFT 0
1434#define OMAP54XX_STABLE_COUNT_WIDTH 0x6
1435#define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0)
1436
1437/* Used by PRM_VOLTSETUP_WARMRESET */
1438#define OMAP54XX_STABLE_PRESCAL_SHIFT 8
1439#define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2
1440#define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8)
1441
1442/* Used by PRM_BANDGAP_SETUP */
1443#define OMAP54XX_STARTUP_COUNT_SHIFT 0
1444#define OMAP54XX_STARTUP_COUNT_WIDTH 0x8
1445#define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0)
1446
1447/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
1448#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24
1449#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8
1450#define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24)
1451
1452/* Used by PM_IVA_PWRSTCTRL */
1453#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20
1454#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2
1455#define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
1456
1457/* Used by PM_IVA_PWRSTCTRL */
1458#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10
1459#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1
1460#define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10)
1461
1462/* Used by PM_IVA_PWRSTST */
1463#define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8
1464#define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2
1465#define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8)
1466
1467/* Used by PM_IVA_PWRSTCTRL */
1468#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22
1469#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2
1470#define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
1471
1472/* Used by PM_IVA_PWRSTCTRL */
1473#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11
1474#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1
1475#define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11)
1476
1477/* Used by PM_IVA_PWRSTST */
1478#define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10
1479#define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2
1480#define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10)
1481
1482/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1483#define OMAP54XX_TIMEOUT_SHIFT 0
1484#define OMAP54XX_TIMEOUT_WIDTH 0x10
1485#define OMAP54XX_TIMEOUT_MASK (0xffff << 0)
1486
1487/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
1488#define OMAP54XX_TIMEOUTEN_SHIFT 3
1489#define OMAP54XX_TIMEOUTEN_WIDTH 0x1
1490#define OMAP54XX_TIMEOUTEN_MASK (1 << 3)
1491
1492/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1493#define OMAP54XX_TRANSITION_EN_SHIFT 8
1494#define OMAP54XX_TRANSITION_EN_WIDTH 0x1
1495#define OMAP54XX_TRANSITION_EN_MASK (1 << 8)
1496
1497/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1498#define OMAP54XX_TRANSITION_ST_SHIFT 8
1499#define OMAP54XX_TRANSITION_ST_WIDTH 0x1
1500#define OMAP54XX_TRANSITION_ST_MASK (1 << 8)
1501
1502/* Used by PRM_DEBUG_TRANS_CFG */
1503#define OMAP54XX_TRIGGER_CLEAR_SHIFT 2
1504#define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1
1505#define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2)
1506
1507/* Used by PRM_RSTST */
1508#define OMAP54XX_TSHUT_CORE_RST_SHIFT 13
1509#define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1
1510#define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13)
1511
1512/* Used by PRM_RSTST */
1513#define OMAP54XX_TSHUT_MM_RST_SHIFT 12
1514#define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1
1515#define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12)
1516
1517/* Used by PRM_RSTST */
1518#define OMAP54XX_TSHUT_MPU_RST_SHIFT 11
1519#define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1
1520#define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11)
1521
1522/* Used by PRM_VC_VAL_BYPASS */
1523#define OMAP54XX_VALID_SHIFT 24
1524#define OMAP54XX_VALID_WIDTH 0x1
1525#define OMAP54XX_VALID_MASK (1 << 24)
1526
1527/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1528#define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14
1529#define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1
1530#define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14)
1531
1532/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1533#define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14
1534#define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1
1535#define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14)
1536
1537/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1538#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22
1539#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1
1540#define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22)
1541
1542/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1543#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22
1544#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1
1545#define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22)
1546
1547/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1548#define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30
1549#define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1
1550#define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30)
1551
1552/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1553#define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30
1554#define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1
1555#define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30)
1556
1557/* Used by PRM_IRQENABLE_MPU_2 */
1558#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6
1559#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1
1560#define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6)
1561
1562/* Used by PRM_IRQSTATUS_MPU_2 */
1563#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6
1564#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1
1565#define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6)
1566
1567/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1568#define OMAP54XX_VC_RAERR_EN_SHIFT 12
1569#define OMAP54XX_VC_RAERR_EN_WIDTH 0x1
1570#define OMAP54XX_VC_RAERR_EN_MASK (1 << 12)
1571
1572/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1573#define OMAP54XX_VC_RAERR_ST_SHIFT 12
1574#define OMAP54XX_VC_RAERR_ST_WIDTH 0x1
1575#define OMAP54XX_VC_RAERR_ST_MASK (1 << 12)
1576
1577/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1578#define OMAP54XX_VC_SAERR_EN_SHIFT 11
1579#define OMAP54XX_VC_SAERR_EN_WIDTH 0x1
1580#define OMAP54XX_VC_SAERR_EN_MASK (1 << 11)
1581
1582/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1583#define OMAP54XX_VC_SAERR_ST_SHIFT 11
1584#define OMAP54XX_VC_SAERR_ST_WIDTH 0x1
1585#define OMAP54XX_VC_SAERR_ST_MASK (1 << 11)
1586
1587/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1588#define OMAP54XX_VC_TOERR_EN_SHIFT 13
1589#define OMAP54XX_VC_TOERR_EN_WIDTH 0x1
1590#define OMAP54XX_VC_TOERR_EN_MASK (1 << 13)
1591
1592/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1593#define OMAP54XX_VC_TOERR_ST_SHIFT 13
1594#define OMAP54XX_VC_TOERR_ST_WIDTH 0x1
1595#define OMAP54XX_VC_TOERR_ST_MASK (1 << 13)
1596
1597/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1598#define OMAP54XX_VDDMAX_SHIFT 24
1599#define OMAP54XX_VDDMAX_WIDTH 0x8
1600#define OMAP54XX_VDDMAX_MASK (0xff << 24)
1601
1602/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1603#define OMAP54XX_VDDMIN_SHIFT 16
1604#define OMAP54XX_VDDMIN_WIDTH 0x8
1605#define OMAP54XX_VDDMIN_MASK (0xff << 16)
1606
1607/* Used by PRM_VOLTCTRL */
1608#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12
1609#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1
1610#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
1611
1612/* Used by PRM_RSTST */
1613#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8
1614#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1
1615#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
1616
1617/* Used by PRM_VOLTCTRL */
1618#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14
1619#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1
1620#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14)
1621
1622/* Used by PRM_VOLTCTRL */
1623#define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9
1624#define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1
1625#define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9)
1626
1627/* Used by PRM_RSTST */
1628#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7
1629#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1
1630#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7)
1631
1632/* Used by PRM_VOLTCTRL */
1633#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13
1634#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1
1635#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
1636
1637/* Used by PRM_VOLTCTRL */
1638#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8
1639#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1
1640#define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8)
1641
1642/* Used by PRM_RSTST */
1643#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6
1644#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1
1645#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
1646
1647/* Used by PRM_VC_CORE_ERRST */
1648#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4
1649#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1
1650#define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4)
1651
1652/* Used by PRM_VC_MM_ERRST */
1653#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4
1654#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1
1655#define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4)
1656
1657/* Used by PRM_VC_MPU_ERRST */
1658#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4
1659#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1
1660#define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4)
1661
1662/* Used by PRM_VC_CORE_ERRST */
1663#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3
1664#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1
1665#define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3)
1666
1667/* Used by PRM_VC_MM_ERRST */
1668#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3
1669#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1
1670#define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3)
1671
1672/* Used by PRM_VC_MPU_ERRST */
1673#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3
1674#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1
1675#define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3)
1676
1677/* Used by PRM_VC_CORE_ERRST */
1678#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5
1679#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1
1680#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5)
1681
1682/* Used by PRM_VC_MM_ERRST */
1683#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5
1684#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1
1685#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5)
1686
1687/* Used by PRM_VC_MPU_ERRST */
1688#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5
1689#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1
1690#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5)
1691
1692/* Used by PRM_VC_SMPS_CORE_CONFIG */
1693#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8
1694#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8
1695#define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8)
1696
1697/* Used by PRM_VC_SMPS_MM_CONFIG */
1698#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8
1699#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8
1700#define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8)
1701
1702/* Used by PRM_VC_SMPS_MPU_CONFIG */
1703#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8
1704#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8
1705#define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8)
1706
1707/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
1708#define OMAP54XX_VOLTSTATEST_SHIFT 0
1709#define OMAP54XX_VOLTSTATEST_WIDTH 0x2
1710#define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0)
1711
1712/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
1713#define OMAP54XX_VPENABLE_SHIFT 0
1714#define OMAP54XX_VPENABLE_WIDTH 0x1
1715#define OMAP54XX_VPENABLE_MASK (1 << 0)
1716
1717/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */
1718#define OMAP54XX_VPINIDLE_SHIFT 0
1719#define OMAP54XX_VPINIDLE_WIDTH 0x1
1720#define OMAP54XX_VPINIDLE_MASK (1 << 0)
1721
1722/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
1723#define OMAP54XX_VPVOLTAGE_SHIFT 0
1724#define OMAP54XX_VPVOLTAGE_WIDTH 0x8
1725#define OMAP54XX_VPVOLTAGE_MASK (0xff << 0)
1726
1727/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1728#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20
1729#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1
1730#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20)
1731
1732/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1733#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20
1734#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1
1735#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20)
1736
1737/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1738#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18
1739#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1
1740#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18)
1741
1742/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1743#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18
1744#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1
1745#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18)
1746
1747/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1748#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17
1749#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1
1750#define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17)
1751
1752/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1753#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17
1754#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1
1755#define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17)
1756
1757/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1758#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19
1759#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1
1760#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19)
1761
1762/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1763#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19
1764#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1
1765#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19)
1766
1767/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1768#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
1769#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1
1770#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16)
1771
1772/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1773#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
1774#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1
1775#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16)
1776
1777/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1778#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21
1779#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1
1780#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21)
1781
1782/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1783#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21
1784#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1
1785#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
1786
1787/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1788#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28
1789#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1
1790#define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28)
1791
1792/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1793#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28
1794#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1
1795#define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28)
1796
1797/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1798#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26
1799#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1
1800#define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26)
1801
1802/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1803#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26
1804#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1
1805#define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26)
1806
1807/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1808#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25
1809#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1
1810#define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25)
1811
1812/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1813#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25
1814#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1
1815#define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25)
1816
1817/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1818#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27
1819#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1
1820#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27)
1821
1822/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1823#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27
1824#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1
1825#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27)
1826
1827/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1828#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24
1829#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1
1830#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24)
1831
1832/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1833#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24
1834#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1
1835#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24)
1836
1837/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1838#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29
1839#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1
1840#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29)
1841
1842/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1843#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29
1844#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1
1845#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29)
1846
1847/* Used by PRM_IRQENABLE_MPU_2 */
1848#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4
1849#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1
1850#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4)
1851
1852/* Used by PRM_IRQSTATUS_MPU_2 */
1853#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4
1854#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1
1855#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4)
1856
1857/* Used by PRM_IRQENABLE_MPU_2 */
1858#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2
1859#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1
1860#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2)
1861
1862/* Used by PRM_IRQSTATUS_MPU_2 */
1863#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2
1864#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1
1865#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2)
1866
1867/* Used by PRM_IRQENABLE_MPU_2 */
1868#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1
1869#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1
1870#define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1)
1871
1872/* Used by PRM_IRQSTATUS_MPU_2 */
1873#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1
1874#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1
1875#define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1)
1876
1877/* Used by PRM_IRQENABLE_MPU_2 */
1878#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3
1879#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1
1880#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3)
1881
1882/* Used by PRM_IRQSTATUS_MPU_2 */
1883#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3
1884#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1
1885#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3)
1886
1887/* Used by PRM_IRQENABLE_MPU_2 */
1888#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
1889#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1
1890#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0)
1891
1892/* Used by PRM_IRQSTATUS_MPU_2 */
1893#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
1894#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1
1895#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0)
1896
1897/* Used by PRM_IRQENABLE_MPU_2 */
1898#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5
1899#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1
1900#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5)
1901
1902/* Used by PRM_IRQSTATUS_MPU_2 */
1903#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5
1904#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1
1905#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
1906
1907/* Used by PRM_SRAM_COUNT */
1908#define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8
1909#define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8
1910#define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8)
1911
1912/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1913#define OMAP54XX_VSTEPMAX_SHIFT 0
1914#define OMAP54XX_VSTEPMAX_WIDTH 0x8
1915#define OMAP54XX_VSTEPMAX_MASK (0xff << 0)
1916
1917/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1918#define OMAP54XX_VSTEPMIN_SHIFT 0
1919#define OMAP54XX_VSTEPMIN_WIDTH 0x8
1920#define OMAP54XX_VSTEPMIN_MASK (0xff << 0)
1921
1922/* Used by PM_DSS_DSS_WKDEP */
1923#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2
1924#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1
1925#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2)
1926
1927/* Used by PM_DSS_DSS_WKDEP */
1928#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1
1929#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1
1930#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1)
1931
1932/* Used by PM_DSS_DSS_WKDEP */
1933#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0
1934#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1
1935#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0)
1936
1937/* Used by PM_DSS_DSS_WKDEP */
1938#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3
1939#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1
1940#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
1941
1942/* Used by PM_ABE_DMIC_WKDEP */
1943#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6
1944#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1
1945#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6)
1946
1947/* Used by PM_ABE_DMIC_WKDEP */
1948#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
1949#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1
1950#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7)
1951
1952/* Used by PM_ABE_DMIC_WKDEP */
1953#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2
1954#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1
1955#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2)
1956
1957/* Used by PM_ABE_DMIC_WKDEP */
1958#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
1959#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1
1960#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0)
1961
1962/* Used by PM_DSS_DSS_WKDEP */
1963#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6
1964#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1
1965#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6)
1966
1967/* Used by PM_DSS_DSS_WKDEP */
1968#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5
1969#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1
1970#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5)
1971
1972/* Used by PM_DSS_DSS_WKDEP */
1973#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4
1974#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1
1975#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4)
1976
1977/* Used by PM_DSS_DSS_WKDEP */
1978#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7
1979#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1
1980#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7)
1981
1982/* Used by PM_DSS_DSS_WKDEP */
1983#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10
1984#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1
1985#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10)
1986
1987/* Used by PM_DSS_DSS_WKDEP */
1988#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9
1989#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1
1990#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9)
1991
1992/* Used by PM_DSS_DSS_WKDEP */
1993#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8
1994#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1
1995#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8)
1996
1997/* Used by PM_DSS_DSS_WKDEP */
1998#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11
1999#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1
2000#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11)
2001
2002/* Used by PM_DSS_DSS_WKDEP */
2003#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17
2004#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1
2005#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17)
2006
2007/* Used by PM_DSS_DSS_WKDEP */
2008#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16
2009#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1
2010#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16)
2011
2012/* Used by PM_DSS_DSS_WKDEP */
2013#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15
2014#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1
2015#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15)
2016
2017/* Used by PM_DSS_DSS_WKDEP */
2018#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18
2019#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1
2020#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18)
2021
2022/* Used by PM_WKUPAON_GPIO1_WKDEP */
2023#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1
2024#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1
2025#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1)
2026
2027/* Used by PM_WKUPAON_GPIO1_WKDEP */
2028#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
2029#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1
2030#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
2031
2032/* Used by PM_WKUPAON_GPIO1_WKDEP */
2033#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6
2034#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1
2035#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6)
2036
2037/* Used by PM_L4PER_GPIO2_WKDEP */
2038#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1
2039#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1
2040#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1)
2041
2042/* Used by PM_L4PER_GPIO2_WKDEP */
2043#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
2044#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1
2045#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
2046
2047/* Used by PM_L4PER_GPIO2_WKDEP */
2048#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6
2049#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1
2050#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6)
2051
2052/* Used by PM_L4PER_GPIO3_WKDEP */
2053#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
2054#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1
2055#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
2056
2057/* Used by PM_L4PER_GPIO3_WKDEP */
2058#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6
2059#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1
2060#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6)
2061
2062/* Used by PM_L4PER_GPIO4_WKDEP */
2063#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
2064#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1
2065#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
2066
2067/* Used by PM_L4PER_GPIO4_WKDEP */
2068#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6
2069#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1
2070#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6)
2071
2072/* Used by PM_L4PER_GPIO5_WKDEP */
2073#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
2074#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1
2075#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
2076
2077/* Used by PM_L4PER_GPIO5_WKDEP */
2078#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6
2079#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1
2080#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6)
2081
2082/* Used by PM_L4PER_GPIO6_WKDEP */
2083#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
2084#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1
2085#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
2086
2087/* Used by PM_L4PER_GPIO6_WKDEP */
2088#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6
2089#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1
2090#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6)
2091
2092/* Used by PM_L4PER_GPIO7_WKDEP */
2093#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0
2094#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1
2095#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0)
2096
2097/* Used by PM_L4PER_GPIO8_WKDEP */
2098#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0
2099#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1
2100#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0)
2101
2102/* Used by PM_DSS_DSS_WKDEP */
2103#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
2104#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1
2105#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19)
2106
2107/* Used by PM_DSS_DSS_WKDEP */
2108#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14
2109#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1
2110#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14)
2111
2112/* Used by PM_DSS_DSS_WKDEP */
2113#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13
2114#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1
2115#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13)
2116
2117/* Used by PM_DSS_DSS_WKDEP */
2118#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
2119#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1
2120#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12)
2121
2122/* Used by PM_L3INIT_HSI_WKDEP */
2123#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6
2124#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1
2125#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6)
2126
2127/* Used by PM_L3INIT_HSI_WKDEP */
2128#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1
2129#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1
2130#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1)
2131
2132/* Used by PM_L3INIT_HSI_WKDEP */
2133#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0
2134#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1
2135#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0)
2136
2137/* Used by PM_L4PER_I2C1_WKDEP */
2138#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
2139#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1
2140#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7)
2141
2142/* Used by PM_L4PER_I2C1_WKDEP */
2143#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1
2144#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1
2145#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1)
2146
2147/* Used by PM_L4PER_I2C1_WKDEP */
2148#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
2149#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1
2150#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
2151
2152/* Used by PM_L4PER_I2C2_WKDEP */
2153#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
2154#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1
2155#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7)
2156
2157/* Used by PM_L4PER_I2C2_WKDEP */
2158#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1
2159#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1
2160#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1)
2161
2162/* Used by PM_L4PER_I2C2_WKDEP */
2163#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
2164#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1
2165#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
2166
2167/* Used by PM_L4PER_I2C3_WKDEP */
2168#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
2169#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1
2170#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7)
2171
2172/* Used by PM_L4PER_I2C3_WKDEP */
2173#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1
2174#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1
2175#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1)
2176
2177/* Used by PM_L4PER_I2C3_WKDEP */
2178#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
2179#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1
2180#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
2181
2182/* Used by PM_L4PER_I2C4_WKDEP */
2183#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
2184#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1
2185#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7)
2186
2187/* Used by PM_L4PER_I2C4_WKDEP */
2188#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1
2189#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1
2190#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1)
2191
2192/* Used by PM_L4PER_I2C4_WKDEP */
2193#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
2194#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1
2195#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
2196
2197/* Used by PM_L4PER_I2C5_WKDEP */
2198#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
2199#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1
2200#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
2201
2202/* Used by PM_WKUPAON_KBD_WKDEP */
2203#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0
2204#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1
2205#define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0)
2206
2207/* Used by PM_ABE_MCASP_WKDEP */
2208#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6
2209#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1
2210#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6)
2211
2212/* Used by PM_ABE_MCASP_WKDEP */
2213#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7
2214#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1
2215#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7)
2216
2217/* Used by PM_ABE_MCASP_WKDEP */
2218#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2
2219#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1
2220#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2)
2221
2222/* Used by PM_ABE_MCASP_WKDEP */
2223#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0
2224#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1
2225#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0)
2226
2227/* Used by PM_ABE_MCBSP1_WKDEP */
2228#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2
2229#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1
2230#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2)
2231
2232/* Used by PM_ABE_MCBSP1_WKDEP */
2233#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0
2234#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1
2235#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0)
2236
2237/* Used by PM_ABE_MCBSP1_WKDEP */
2238#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3
2239#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1
2240#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3)
2241
2242/* Used by PM_ABE_MCBSP2_WKDEP */
2243#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2
2244#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1
2245#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2)
2246
2247/* Used by PM_ABE_MCBSP2_WKDEP */
2248#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0
2249#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1
2250#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0)
2251
2252/* Used by PM_ABE_MCBSP2_WKDEP */
2253#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3
2254#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1
2255#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3)
2256
2257/* Used by PM_ABE_MCBSP3_WKDEP */
2258#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2
2259#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1
2260#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2)
2261
2262/* Used by PM_ABE_MCBSP3_WKDEP */
2263#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0
2264#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1
2265#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0)
2266
2267/* Used by PM_ABE_MCBSP3_WKDEP */
2268#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3
2269#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1
2270#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3)
2271
2272/* Used by PM_ABE_MCPDM_WKDEP */
2273#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6
2274#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1
2275#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6)
2276
2277/* Used by PM_ABE_MCPDM_WKDEP */
2278#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7
2279#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1
2280#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7)
2281
2282/* Used by PM_ABE_MCPDM_WKDEP */
2283#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2
2284#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1
2285#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2)
2286
2287/* Used by PM_ABE_MCPDM_WKDEP */
2288#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0
2289#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1
2290#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0)
2291
2292/* Used by PM_L4PER_MCSPI1_WKDEP */
2293#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2
2294#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1
2295#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2)
2296
2297/* Used by PM_L4PER_MCSPI1_WKDEP */
2298#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1
2299#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1
2300#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1)
2301
2302/* Used by PM_L4PER_MCSPI1_WKDEP */
2303#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0
2304#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1
2305#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
2306
2307/* Used by PM_L4PER_MCSPI1_WKDEP */
2308#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3
2309#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1
2310#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
2311
2312/* Used by PM_L4PER_MCSPI2_WKDEP */
2313#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1
2314#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1
2315#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1)
2316
2317/* Used by PM_L4PER_MCSPI2_WKDEP */
2318#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0
2319#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1
2320#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
2321
2322/* Used by PM_L4PER_MCSPI2_WKDEP */
2323#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3
2324#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1
2325#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
2326
2327/* Used by PM_L4PER_MCSPI3_WKDEP */
2328#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0
2329#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1
2330#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
2331
2332/* Used by PM_L4PER_MCSPI3_WKDEP */
2333#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3
2334#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1
2335#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
2336
2337/* Used by PM_L4PER_MCSPI4_WKDEP */
2338#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0
2339#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1
2340#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
2341
2342/* Used by PM_L4PER_MCSPI4_WKDEP */
2343#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3
2344#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1
2345#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
2346
2347/* Used by PM_L3INIT_MMC1_WKDEP */
2348#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2
2349#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1
2350#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2)
2351
2352/* Used by PM_L3INIT_MMC1_WKDEP */
2353#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1
2354#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1
2355#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1)
2356
2357/* Used by PM_L3INIT_MMC1_WKDEP */
2358#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0
2359#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1
2360#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0)
2361
2362/* Used by PM_L3INIT_MMC1_WKDEP */
2363#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3
2364#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1
2365#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
2366
2367/* Used by PM_L3INIT_MMC2_WKDEP */
2368#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2
2369#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1
2370#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2)
2371
2372/* Used by PM_L3INIT_MMC2_WKDEP */
2373#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1
2374#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1
2375#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1)
2376
2377/* Used by PM_L3INIT_MMC2_WKDEP */
2378#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0
2379#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1
2380#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0)
2381
2382/* Used by PM_L3INIT_MMC2_WKDEP */
2383#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3
2384#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1
2385#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
2386
2387/* Used by PM_L4PER_MMC3_WKDEP */
2388#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1
2389#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1
2390#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1)
2391
2392/* Used by PM_L4PER_MMC3_WKDEP */
2393#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0
2394#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1
2395#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0)
2396
2397/* Used by PM_L4PER_MMC3_WKDEP */
2398#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3
2399#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1
2400#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3)
2401
2402/* Used by PM_L4PER_MMC4_WKDEP */
2403#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0
2404#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1
2405#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0)
2406
2407/* Used by PM_L4PER_MMC4_WKDEP */
2408#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3
2409#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1
2410#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3)
2411
2412/* Used by PM_L4PER_MMC5_WKDEP */
2413#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0
2414#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1
2415#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0)
2416
2417/* Used by PM_L4PER_MMC5_WKDEP */
2418#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3
2419#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1
2420#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3)
2421
2422/* Used by PM_L3INIT_SATA_WKDEP */
2423#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0
2424#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1
2425#define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0)
2426
2427/* Used by PM_ABE_SLIMBUS1_WKDEP */
2428#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6
2429#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1
2430#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6)
2431
2432/* Used by PM_ABE_SLIMBUS1_WKDEP */
2433#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
2434#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1
2435#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7)
2436
2437/* Used by PM_ABE_SLIMBUS1_WKDEP */
2438#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2
2439#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1
2440#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2)
2441
2442/* Used by PM_ABE_SLIMBUS1_WKDEP */
2443#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
2444#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1
2445#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0)
2446
2447/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
2448#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1
2449#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1
2450#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1)
2451
2452/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
2453#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0
2454#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1
2455#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0)
2456
2457/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */
2458#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0
2459#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1
2460#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0)
2461
2462/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
2463#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0
2464#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1
2465#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0)
2466
2467/* Used by PM_L4PER_TIMER10_WKDEP */
2468#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0
2469#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1
2470#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0)
2471
2472/* Used by PM_L4PER_TIMER11_WKDEP */
2473#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1
2474#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1
2475#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1)
2476
2477/* Used by PM_L4PER_TIMER11_WKDEP */
2478#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0
2479#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1
2480#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0)
2481
2482/* Used by PM_WKUPAON_TIMER12_WKDEP */
2483#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0
2484#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1
2485#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
2486
2487/* Used by PM_WKUPAON_TIMER1_WKDEP */
2488#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0
2489#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1
2490#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
2491
2492/* Used by PM_L4PER_TIMER2_WKDEP */
2493#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0
2494#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1
2495#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0)
2496
2497/* Used by PM_L4PER_TIMER3_WKDEP */
2498#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1
2499#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1
2500#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1)
2501
2502/* Used by PM_L4PER_TIMER3_WKDEP */
2503#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0
2504#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1
2505#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0)
2506
2507/* Used by PM_L4PER_TIMER4_WKDEP */
2508#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1
2509#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1
2510#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1)
2511
2512/* Used by PM_L4PER_TIMER4_WKDEP */
2513#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0
2514#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1
2515#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0)
2516
2517/* Used by PM_ABE_TIMER5_WKDEP */
2518#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2
2519#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1
2520#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2)
2521
2522/* Used by PM_ABE_TIMER5_WKDEP */
2523#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0
2524#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1
2525#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
2526
2527/* Used by PM_ABE_TIMER6_WKDEP */
2528#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2
2529#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1
2530#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2)
2531
2532/* Used by PM_ABE_TIMER6_WKDEP */
2533#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0
2534#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1
2535#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
2536
2537/* Used by PM_ABE_TIMER7_WKDEP */
2538#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2
2539#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1
2540#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2)
2541
2542/* Used by PM_ABE_TIMER7_WKDEP */
2543#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0
2544#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1
2545#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
2546
2547/* Used by PM_ABE_TIMER8_WKDEP */
2548#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2
2549#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1
2550#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2)
2551
2552/* Used by PM_ABE_TIMER8_WKDEP */
2553#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0
2554#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1
2555#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
2556
2557/* Used by PM_L4PER_TIMER9_WKDEP */
2558#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1
2559#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1
2560#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1)
2561
2562/* Used by PM_L4PER_TIMER9_WKDEP */
2563#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0
2564#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1
2565#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0)
2566
2567/* Used by PM_L4PER_UART1_WKDEP */
2568#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0
2569#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1
2570#define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0)
2571
2572/* Used by PM_L4PER_UART1_WKDEP */
2573#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3
2574#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1
2575#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3)
2576
2577/* Used by PM_L4PER_UART2_WKDEP */
2578#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0
2579#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1
2580#define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0)
2581
2582/* Used by PM_L4PER_UART2_WKDEP */
2583#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3
2584#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1
2585#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3)
2586
2587/* Used by PM_L4PER_UART3_WKDEP */
2588#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2
2589#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1
2590#define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2)
2591
2592/* Used by PM_L4PER_UART3_WKDEP */
2593#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1
2594#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1
2595#define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1)
2596
2597/* Used by PM_L4PER_UART3_WKDEP */
2598#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0
2599#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1
2600#define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0)
2601
2602/* Used by PM_L4PER_UART3_WKDEP */
2603#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3
2604#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1
2605#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3)
2606
2607/* Used by PM_L4PER_UART4_WKDEP */
2608#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0
2609#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1
2610#define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0)
2611
2612/* Used by PM_L4PER_UART4_WKDEP */
2613#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3
2614#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1
2615#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3)
2616
2617/* Used by PM_L4PER_UART5_WKDEP */
2618#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0
2619#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1
2620#define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0)
2621
2622/* Used by PM_L4PER_UART5_WKDEP */
2623#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3
2624#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1
2625#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3)
2626
2627/* Used by PM_L4PER_UART6_WKDEP */
2628#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0
2629#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1
2630#define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0)
2631
2632/* Used by PM_L4PER_UART6_WKDEP */
2633#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3
2634#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1
2635#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3)
2636
2637/* Used by PM_L3INIT_UNIPRO2_WKDEP */
2638#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0
2639#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1
2640#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0)
2641
2642/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
2643#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1
2644#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1
2645#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1)
2646
2647/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
2648#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0
2649#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1
2650#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0)
2651
2652/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
2653#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1
2654#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1
2655#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1)
2656
2657/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
2658#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0
2659#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1
2660#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0)
2661
2662/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
2663#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1
2664#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1
2665#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1)
2666
2667/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
2668#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0
2669#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1
2670#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0)
2671
2672/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
2673#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0
2674#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1
2675#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0)
2676
2677/* Used by PM_ABE_WD_TIMER3_WKDEP */
2678#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0
2679#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1
2680#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0)
2681
2682/* Used by PRM_IO_PMCTRL */
2683#define OMAP54XX_WUCLK_CTRL_SHIFT 8
2684#define OMAP54XX_WUCLK_CTRL_WIDTH 0x1
2685#define OMAP54XX_WUCLK_CTRL_MASK (1 << 8)
2686
2687/* Used by PRM_IO_PMCTRL */
2688#define OMAP54XX_WUCLK_STATUS_SHIFT 9
2689#define OMAP54XX_WUCLK_STATUS_WIDTH 0x1
2690#define OMAP54XX_WUCLK_STATUS_MASK (1 << 9)
2691
2692/* Used by REVISION_PRM */
2693#define OMAP54XX_X_MAJOR_SHIFT 8
2694#define OMAP54XX_X_MAJOR_WIDTH 0x3
2695#define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
2696
2697/* Used by REVISION_PRM */
2698#define OMAP54XX_Y_MINOR_SHIFT 0
2699#define OMAP54XX_Y_MINOR_WIDTH 0x6
2700#define OMAP54XX_Y_MINOR_MASK (0x3f << 0)
2701#endif
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 8ee1fbdec561..7db2422faa16 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -25,6 +25,7 @@
25#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H 25#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H 26#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
27 27
28#include "prm44xx_54xx.h"
28#include "prcm-common.h" 29#include "prcm-common.h"
29#include "prm.h" 30#include "prm.h"
30 31
@@ -744,36 +745,4 @@
744#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 745#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
745#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) 746#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
746 747
747/* Function prototypes */
748# ifndef __ASSEMBLER__
749
750extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
751extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
752extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
753
754/* OMAP4-specific VP functions */
755u32 omap4_prm_vp_check_txdone(u8 vp_id);
756void omap4_prm_vp_clear_txdone(u8 vp_id);
757
758/*
759 * OMAP4 access functions for voltage controller (VC) and
760 * voltage proccessor (VP) in the PRM.
761 */
762extern u32 omap4_prm_vcvp_read(u8 offset);
763extern void omap4_prm_vcvp_write(u32 val, u8 offset);
764extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
765
766extern void omap44xx_prm_reconfigure_io_chain(void);
767
768/* PRM interrupt-related functions */
769extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
770extern void omap44xx_prm_ocp_barrier(void);
771extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
772extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
773
774extern int __init omap44xx_prm_init(void);
775extern u32 omap44xx_prm_get_reset_sources(void);
776
777# endif
778
779#endif 748#endif
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
new file mode 100644
index 000000000000..7cd22abb8f15
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -0,0 +1,58 @@
1/*
2 * OMAP44xx and 54xx PRM common functions
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
24#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
25
26/* Function prototypes */
27#ifndef __ASSEMBLER__
28
29extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
30extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
31extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
32
33/* OMAP4/OMAP5-specific VP functions */
34u32 omap4_prm_vp_check_txdone(u8 vp_id);
35void omap4_prm_vp_clear_txdone(u8 vp_id);
36
37/*
38 * OMAP4/OMAP5 access functions for voltage controller (VC) and
39 * voltage proccessor (VP) in the PRM.
40 */
41extern u32 omap4_prm_vcvp_read(u8 offset);
42extern void omap4_prm_vcvp_write(u32 val, u8 offset);
43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
44
45extern void omap44xx_prm_reconfigure_io_chain(void);
46
47/* PRM interrupt-related functions */
48extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
49extern void omap44xx_prm_ocp_barrier(void);
50extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
51extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
52
53extern int __init omap44xx_prm_init(void);
54extern u32 omap44xx_prm_get_reset_sources(void);
55
56#endif
57
58#endif
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
new file mode 100644
index 000000000000..e4411010309c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -0,0 +1,421 @@
1/*
2 * OMAP54xx PRM instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
22#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
23
24#include "prm44xx_54xx.h"
25#include "prcm-common.h"
26#include "prm.h"
27
28#define OMAP54XX_PRM_BASE 0x4ae06000
29
30#define OMAP54XX_PRM_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
32
33
34/* PRM instances */
35#define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
36#define OMAP54XX_PRM_CKGEN_INST 0x0100
37#define OMAP54XX_PRM_MPU_INST 0x0300
38#define OMAP54XX_PRM_DSP_INST 0x0400
39#define OMAP54XX_PRM_ABE_INST 0x0500
40#define OMAP54XX_PRM_COREAON_INST 0x0600
41#define OMAP54XX_PRM_CORE_INST 0x0700
42#define OMAP54XX_PRM_IVA_INST 0x1200
43#define OMAP54XX_PRM_CAM_INST 0x1300
44#define OMAP54XX_PRM_DSS_INST 0x1400
45#define OMAP54XX_PRM_GPU_INST 0x1500
46#define OMAP54XX_PRM_L3INIT_INST 0x1600
47#define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700
48#define OMAP54XX_PRM_WKUPAON_INST 0x1800
49#define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900
50#define OMAP54XX_PRM_EMU_INST 0x1a00
51#define OMAP54XX_PRM_EMU_CM_INST 0x1b00
52#define OMAP54XX_PRM_DEVICE_INST 0x1c00
53#define OMAP54XX_PRM_INSTR_INST 0x1f00
54
55/* PRM clockdomain register offsets (from instance start) */
56#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
57#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
58
59/* PRM */
60
61/* PRM.OCP_SOCKET_PRM register offsets */
62#define OMAP54XX_REVISION_PRM_OFFSET 0x0000
63#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
64#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
65#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
66#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
67#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020
68#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028
69#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030
70#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038
71#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
72#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
73#define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084
74#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090
75#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094
76#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098
77#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c
78#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0
79#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4
80
81/* PRM.CKGEN_PRM register offsets */
82#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000
83#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
84#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
85#define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
86#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
87#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
88#define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010
89#define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
90
91/* PRM.MPU_PRM register offsets */
92#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
93#define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004
94#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
95
96/* PRM.DSP_PRM register offsets */
97#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000
98#define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004
99#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010
100#define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014
101#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024
102
103/* PRM.ABE_PRM register offsets */
104#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000
105#define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004
106#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c
107#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030
108#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034
109#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038
110#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c
111#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040
112#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044
113#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048
114#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c
115#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050
116#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054
117#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058
118#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c
119#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060
120#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064
121#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068
122#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c
123#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070
124#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074
125#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078
126#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c
127#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080
128#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084
129#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088
130#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c
131
132/* PRM.COREAON_PRM register offsets */
133#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028
134#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c
135#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030
136#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034
137#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038
138#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c
139
140/* PRM.CORE_PRM register offsets */
141#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
142#define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004
143#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
144#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124
145#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c
146#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134
147#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210
148#define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214
149#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224
150#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
151#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
152#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
153#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
154#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
155#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
156#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524
157#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c
158#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534
159#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
160#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
161#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634
162#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
163#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
164#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724
165#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
166#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
167#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824
168#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c
169#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834
170#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928
171#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c
172#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930
173#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934
174#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938
175#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c
176#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940
177#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944
178#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948
179#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c
180#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950
181#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954
182#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c
183#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960
184#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964
185#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968
186#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c
187#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970
188#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974
189#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978
190#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c
191#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980
192#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984
193#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c
194#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0
195#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4
196#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8
197#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac
198#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0
199#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4
200#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8
201#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc
202#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0
203#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0
204#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4
205#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8
206#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc
207#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00
208#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04
209#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08
210#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c
211#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10
212#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14
213#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18
214#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c
215#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20
216#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24
217#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28
218#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c
219#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40
220#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44
221#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48
222#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c
223#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50
224#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54
225#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58
226#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c
227#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60
228#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64
229#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68
230#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c
231#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70
232#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74
233#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78
234#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c
235#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4
236#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac
237#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4
238#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc
239#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4
240#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc
241#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc
242
243/* PRM.IVA_PRM register offsets */
244#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
245#define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004
246#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010
247#define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014
248#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
249#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
250
251/* PRM.CAM_PRM register offsets */
252#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
253#define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004
254#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024
255#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c
256#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034
257
258/* PRM.DSS_PRM register offsets */
259#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
260#define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004
261#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
262#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
263#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
264
265/* PRM.GPU_PRM register offsets */
266#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
267#define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004
268#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
269
270/* PRM.L3INIT_PRM register offsets */
271#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
272#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
273#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
274#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
275#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
276#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
277#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038
278#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c
279#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040
280#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044
281#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058
282#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c
283#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068
284#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c
285#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
286#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
287#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
288#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
289#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
290#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0
291#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4
292
293/* PRM.CUSTEFUSE_PRM register offsets */
294#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
295#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
296#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
297
298/* PRM.WKUPAON_PRM register offsets */
299#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024
300#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c
301#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030
302#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034
303#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038
304#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c
305#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040
306#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044
307#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048
308#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c
309#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054
310#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064
311#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078
312#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c
313
314/* PRM.WKUPAON_CM register offsets */
315#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
316#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
317#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
318#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
319#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
320#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
321#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
322#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
323#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
324#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
325#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
326#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
327#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
328#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
329#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
330#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
331#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
332#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
333#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
334#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
335#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
336#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
337#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
338
339/* PRM.EMU_PRM register offsets */
340#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
341#define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004
342#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
343
344/* PRM.EMU_CM register offsets */
345#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
346#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
347#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020
348#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
349#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028
350#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
351
352/* PRM.DEVICE_PRM register offsets */
353#define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000
354#define OMAP54XX_PRM_RSTST_OFFSET 0x0004
355#define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008
356#define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c
357#define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010
358#define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014
359#define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018
360#define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c
361#define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020
362#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
363#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
364#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
365#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
366#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
367#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
368#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
369#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040
370#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044
371#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
372#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
373#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
374#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
375#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058
376#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c
377#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
378#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
379#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
380#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
381#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070
382#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074
383#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078
384#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c
385#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080
386#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084
387#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088
388#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c
389#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090
390#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
391#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098
392#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c
393#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
394#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4
395#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8
396#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac
397#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0
398#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4
399#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8
400#define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc
401#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
402#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
403#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
404#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
405#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
406#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4
407#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8
408#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
409#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
410#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4
411#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8
412#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
413#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
414#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
415#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
416#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
417#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
418#define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110
419#define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114
420
421#endif
diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
new file mode 100644
index 000000000000..57e86c8f8239
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -0,0 +1,231 @@
1/*
2 * OMAP54XX SCRM registers and bitfields
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * This file is automatically generated from the OMAP hardware databases.
9 * We respectfully ask that any modifications to this file be coordinated
10 * with the public linux-omap@vger.kernel.org mailing list and the
11 * authors above to ensure that the autogeneration scripts are kept
12 * up-to-date with the file contents.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
20#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
21
22#define OMAP5_SCRM_BASE 0x4ae0a000
23
24#define OMAP54XX_SCRM_REGADDR(reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
26
27/* SCRM */
28
29/* SCRM.SCRM register offsets */
30#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
31#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
32#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
33#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
34#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
35#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
36#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
37#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
38#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
39#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118)
40#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c
41#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c)
42#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200
43#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200)
44#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204
45#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204)
46#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208
47#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208)
48#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210
49#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210)
50#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214
51#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214)
52#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218
53#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218)
54#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c
55#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c)
56#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220
57#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220)
58#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224
59#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224)
60#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234
61#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234)
62#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310
63#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310)
64#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314
65#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314)
66#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318
67#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318)
68#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c
69#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c)
70#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320
71#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320)
72#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324
73#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324)
74#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400
75#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400)
76#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418
77#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418)
78#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c
79#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c)
80#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420
81#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420)
82#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510
83#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510)
84#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514
85#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514)
86#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518
87#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518)
88#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c
89#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c)
90
91/*
92 * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
93 * AUXCLKREQ5, D2DCLKREQ
94 */
95#define OMAP5_ACCURACY_SHIFT 1
96#define OMAP5_ACCURACY_WIDTH 0x1
97#define OMAP5_ACCURACY_MASK (1 << 1)
98
99/* Used by APEWARMRSTST */
100#define OMAP5_APEWARMRSTST_SHIFT 1
101#define OMAP5_APEWARMRSTST_WIDTH 0x1
102#define OMAP5_APEWARMRSTST_MASK (1 << 1)
103
104/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
105#define OMAP5_CLKDIV_SHIFT 16
106#define OMAP5_CLKDIV_WIDTH 0x4
107#define OMAP5_CLKDIV_MASK (0xf << 16)
108
109/* Used by D2DCLKM, MODEMCLKM */
110#define OMAP5_CLK_32KHZ_SHIFT 0
111#define OMAP5_CLK_32KHZ_WIDTH 0x1
112#define OMAP5_CLK_32KHZ_MASK (1 << 0)
113
114/* Used by D2DRSTCTRL, MODEMRSTCTRL */
115#define OMAP5_COLDRST_SHIFT 0
116#define OMAP5_COLDRST_WIDTH 0x1
117#define OMAP5_COLDRST_MASK (1 << 0)
118
119/* Used by D2DWARMRSTST */
120#define OMAP5_D2DWARMRSTST_SHIFT 3
121#define OMAP5_D2DWARMRSTST_WIDTH 0x1
122#define OMAP5_D2DWARMRSTST_MASK (1 << 3)
123
124/* Used by AUXCLK0 */
125#define OMAP5_DISABLECLK_SHIFT 9
126#define OMAP5_DISABLECLK_WIDTH 0x1
127#define OMAP5_DISABLECLK_MASK (1 << 9)
128
129/* Used by CLKSETUPTIME */
130#define OMAP5_DOWNTIME_SHIFT 16
131#define OMAP5_DOWNTIME_WIDTH 0x6
132#define OMAP5_DOWNTIME_MASK (0x3f << 16)
133
134/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
135#define OMAP5_ENABLE_SHIFT 8
136#define OMAP5_ENABLE_WIDTH 0x1
137#define OMAP5_ENABLE_MASK (1 << 8)
138
139/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
140#define OMAP5_ENABLE_0_0_SHIFT 0
141#define OMAP5_ENABLE_0_0_WIDTH 0x1
142#define OMAP5_ENABLE_0_0_MASK (1 << 0)
143
144/* Used by ALTCLKSRC */
145#define OMAP5_ENABLE_EXT_SHIFT 3
146#define OMAP5_ENABLE_EXT_WIDTH 0x1
147#define OMAP5_ENABLE_EXT_MASK (1 << 3)
148
149/* Used by ALTCLKSRC */
150#define OMAP5_ENABLE_INT_SHIFT 2
151#define OMAP5_ENABLE_INT_WIDTH 0x1
152#define OMAP5_ENABLE_INT_MASK (1 << 2)
153
154/* Used by EXTWARMRSTST */
155#define OMAP5_EXTWARMRSTST_SHIFT 0
156#define OMAP5_EXTWARMRSTST_WIDTH 0x1
157#define OMAP5_EXTWARMRSTST_MASK (1 << 0)
158
159/*
160 * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
161 * AUXCLKREQ5
162 */
163#define OMAP5_MAPPING_SHIFT 2
164#define OMAP5_MAPPING_WIDTH 0x3
165#define OMAP5_MAPPING_MASK (0x7 << 2)
166
167/* Used by ALTCLKSRC */
168#define OMAP5_MODE_SHIFT 0
169#define OMAP5_MODE_WIDTH 0x2
170#define OMAP5_MODE_MASK (0x3 << 0)
171
172/* Used by MODEMWARMRSTST */
173#define OMAP5_MODEMWARMRSTST_SHIFT 2
174#define OMAP5_MODEMWARMRSTST_WIDTH 0x1
175#define OMAP5_MODEMWARMRSTST_MASK (1 << 2)
176
177/*
178 * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
179 * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
180 * D2DCLKREQ, EXTCLKREQ, PWRREQ
181 */
182#define OMAP5_POLARITY_SHIFT 0
183#define OMAP5_POLARITY_WIDTH 0x1
184#define OMAP5_POLARITY_MASK (1 << 0)
185
186/* Used by EXTPWRONRSTCTRL */
187#define OMAP5_PWRONRST_SHIFT 1
188#define OMAP5_PWRONRST_WIDTH 0x1
189#define OMAP5_PWRONRST_MASK (1 << 1)
190
191/* Used by REVISION_SCRM */
192#define OMAP5_REV_SHIFT 0
193#define OMAP5_REV_WIDTH 0x8
194#define OMAP5_REV_MASK (0xff << 0)
195
196/* Used by RSTTIME */
197#define OMAP5_RSTTIME_SHIFT 0
198#define OMAP5_RSTTIME_WIDTH 0x4
199#define OMAP5_RSTTIME_MASK (0xf << 0)
200
201/* Used by CLKSETUPTIME */
202#define OMAP5_SETUPTIME_SHIFT 0
203#define OMAP5_SETUPTIME_WIDTH 0xc
204#define OMAP5_SETUPTIME_MASK (0xfff << 0)
205
206/* Used by PMICSETUPTIME */
207#define OMAP5_SLEEPTIME_SHIFT 0
208#define OMAP5_SLEEPTIME_WIDTH 0x6
209#define OMAP5_SLEEPTIME_MASK (0x3f << 0)
210
211/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
212#define OMAP5_SRCSELECT_SHIFT 1
213#define OMAP5_SRCSELECT_WIDTH 0x2
214#define OMAP5_SRCSELECT_MASK (0x3 << 1)
215
216/* Used by D2DCLKM */
217#define OMAP5_SYSCLK_SHIFT 1
218#define OMAP5_SYSCLK_WIDTH 0x1
219#define OMAP5_SYSCLK_MASK (1 << 1)
220
221/* Used by PMICSETUPTIME */
222#define OMAP5_WAKEUPTIME_SHIFT 16
223#define OMAP5_WAKEUPTIME_WIDTH 0x6
224#define OMAP5_WAKEUPTIME_MASK (0x3f << 16)
225
226/* Used by D2DRSTCTRL, MODEMRSTCTRL */
227#define OMAP5_WARMRST_SHIFT 1
228#define OMAP5_WARMRST_WIDTH 0x1
229#define OMAP5_WARMRST_MASK (1 << 1)
230
231#endif
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16870d9..3cefc492b758 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -96,6 +96,15 @@
96# endif 96# endif
97#endif 97#endif
98 98
99#ifdef CONFIG_SOC_AM43XX
100# ifdef OMAP_NAME
101# undef MULTI_OMAP2
102# define MULTI_OMAP2
103# else
104# define OMAP_NAME am43xx
105# endif
106#endif
107
99/* 108/*
100 * Omap device type i.e. EMU/HS/TST/GP/BAD 109 * Omap device type i.e. EMU/HS/TST/GP/BAD
101 */ 110 */
@@ -187,6 +196,7 @@ IS_OMAP_CLASS(44xx, 0x44)
187IS_AM_CLASS(35xx, 0x35) 196IS_AM_CLASS(35xx, 0x35)
188IS_OMAP_CLASS(54xx, 0x54) 197IS_OMAP_CLASS(54xx, 0x54)
189IS_AM_CLASS(33xx, 0x33) 198IS_AM_CLASS(33xx, 0x33)
199IS_AM_CLASS(43xx, 0x43)
190 200
191IS_TI_CLASS(81xx, 0x81) 201IS_TI_CLASS(81xx, 0x81)
192 202
@@ -202,6 +212,7 @@ IS_OMAP_SUBCLASS(543x, 0x543)
202IS_TI_SUBCLASS(816x, 0x816) 212IS_TI_SUBCLASS(816x, 0x816)
203IS_TI_SUBCLASS(814x, 0x814) 213IS_TI_SUBCLASS(814x, 0x814)
204IS_AM_SUBCLASS(335x, 0x335) 214IS_AM_SUBCLASS(335x, 0x335)
215IS_AM_SUBCLASS(437x, 0x437)
205 216
206#define cpu_is_omap24xx() 0 217#define cpu_is_omap24xx() 0
207#define cpu_is_omap242x() 0 218#define cpu_is_omap242x() 0
@@ -214,6 +225,8 @@ IS_AM_SUBCLASS(335x, 0x335)
214#define soc_is_am35xx() 0 225#define soc_is_am35xx() 0
215#define soc_is_am33xx() 0 226#define soc_is_am33xx() 0
216#define soc_is_am335x() 0 227#define soc_is_am335x() 0
228#define soc_is_am43xx() 0
229#define soc_is_am437x() 0
217#define cpu_is_omap44xx() 0 230#define cpu_is_omap44xx() 0
218#define cpu_is_omap443x() 0 231#define cpu_is_omap443x() 0
219#define cpu_is_omap446x() 0 232#define cpu_is_omap446x() 0
@@ -341,6 +354,13 @@ IS_OMAP_TYPE(3430, 0x3430)
341# define soc_is_am335x() is_am335x() 354# define soc_is_am335x() is_am335x()
342#endif 355#endif
343 356
357#ifdef CONFIG_SOC_AM43XX
358# undef soc_is_am43xx
359# undef soc_is_am437x
360# define soc_is_am43xx() is_am43xx()
361# define soc_is_am437x() is_am437x()
362#endif
363
344# if defined(CONFIG_ARCH_OMAP4) 364# if defined(CONFIG_ARCH_OMAP4)
345# undef cpu_is_omap44xx 365# undef cpu_is_omap44xx
346# undef cpu_is_omap443x 366# undef cpu_is_omap443x
@@ -398,6 +418,9 @@ IS_OMAP_TYPE(3430, 0x3430)
398#define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8)) 418#define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8))
399#define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8)) 419#define AM335X_REV_ES2_1 (AM335X_CLASS | (0x2 << 8))
400 420
421#define AM437X_CLASS 0x43700000
422#define AM437X_REV_ES1_0 AM437X_CLASS
423
401#define OMAP443X_CLASS 0x44300044 424#define OMAP443X_CLASS 0x44300044
402#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) 425#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
403#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) 426#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 0ff0f068bea8..4bd096836235 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -119,6 +119,9 @@ static void __init omap_detect_sram(void)
119 if (soc_is_am33xx()) { 119 if (soc_is_am33xx()) {
120 omap_sram_start = AM33XX_SRAM_PA; 120 omap_sram_start = AM33XX_SRAM_PA;
121 omap_sram_size = 0x10000; /* 64K */ 121 omap_sram_size = 0x10000; /* 64K */
122 } else if (soc_is_am43xx()) {
123 omap_sram_start = AM33XX_SRAM_PA;
124 omap_sram_size = SZ_256K;
122 } else if (cpu_is_omap34xx()) { 125 } else if (cpu_is_omap34xx()) {
123 omap_sram_start = OMAP3_SRAM_PA; 126 omap_sram_start = OMAP3_SRAM_PA;
124 omap_sram_size = 0x10000; /* 64K */ 127 omap_sram_size = 0x10000; /* 64K */
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index a0ce4f10ff13..5998eed3a2d2 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -171,6 +171,7 @@ extern void omap2xxx_voltagedomains_init(void);
171extern void omap3xxx_voltagedomains_init(void); 171extern void omap3xxx_voltagedomains_init(void);
172extern void am33xx_voltagedomains_init(void); 172extern void am33xx_voltagedomains_init(void);
173extern void omap44xx_voltagedomains_init(void); 173extern void omap44xx_voltagedomains_init(void);
174extern void omap54xx_voltagedomains_init(void);
174 175
175struct voltagedomain *voltdm_lookup(const char *name); 176struct voltagedomain *voltdm_lookup(const char *name);
176void voltdm_init(struct voltagedomain **voltdm_list); 177void voltdm_init(struct voltagedomain **voltdm_list);
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
new file mode 100644
index 000000000000..72b8971b54c7
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -0,0 +1,102 @@
1/*
2 * OMAP5 Voltage Management Routines
3 *
4 * Based on voltagedomains44xx_data.c
5 *
6 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/init.h>
15
16#include "common.h"
17
18#include "prm54xx.h"
19#include "voltage.h"
20#include "omap_opp_data.h"
21#include "vc.h"
22#include "vp.h"
23
24static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
25 .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
26};
27
28static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
29 .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
30};
31
32static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
33 .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
34};
35
36static struct voltagedomain omap5_voltdm_mpu = {
37 .name = "mpu",
38 .scalable = true,
39 .read = omap4_prm_vcvp_read,
40 .write = omap4_prm_vcvp_write,
41 .rmw = omap4_prm_vcvp_rmw,
42 .vc = &omap4_vc_mpu,
43 .vfsm = &omap5_vdd_mpu_vfsm,
44 .vp = &omap4_vp_mpu,
45};
46
47static struct voltagedomain omap5_voltdm_mm = {
48 .name = "mm",
49 .scalable = true,
50 .read = omap4_prm_vcvp_read,
51 .write = omap4_prm_vcvp_write,
52 .rmw = omap4_prm_vcvp_rmw,
53 .vc = &omap4_vc_iva,
54 .vfsm = &omap5_vdd_mm_vfsm,
55 .vp = &omap4_vp_iva,
56};
57
58static struct voltagedomain omap5_voltdm_core = {
59 .name = "core",
60 .scalable = true,
61 .read = omap4_prm_vcvp_read,
62 .write = omap4_prm_vcvp_write,
63 .rmw = omap4_prm_vcvp_rmw,
64 .vc = &omap4_vc_core,
65 .vfsm = &omap5_vdd_core_vfsm,
66 .vp = &omap4_vp_core,
67};
68
69static struct voltagedomain omap5_voltdm_wkup = {
70 .name = "wkup",
71};
72
73static struct voltagedomain *voltagedomains_omap5[] __initdata = {
74 &omap5_voltdm_mpu,
75 &omap5_voltdm_mm,
76 &omap5_voltdm_core,
77 &omap5_voltdm_wkup,
78 NULL,
79};
80
81static const char *sys_clk_name __initdata = "sys_clkin";
82
83void __init omap54xx_voltagedomains_init(void)
84{
85 struct voltagedomain *voltdm;
86 int i;
87
88 /*
89 * XXX Will depend on the process, validation, and binning
90 * for the currently-running IC. Use OMAP4 data for time being.
91 */
92#ifdef CONFIG_PM_OPP
93 omap5_voltdm_mpu.volt_data = omap446x_vdd_mpu_volt_data;
94 omap5_voltdm_mm.volt_data = omap446x_vdd_iva_volt_data;
95 omap5_voltdm_core.volt_data = omap446x_vdd_core_volt_data;
96#endif
97
98 for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
99 voltdm->sys_clk.name = sys_clk_name;
100
101 voltdm_init(voltagedomains_omap5);
102};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 12:30:17 -0500