30 files changed, 10283 insertions, 4156 deletions

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b05b738d31e6..2feb6870b735 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,13 +3,15 @@
 #
 
 # Common support
-obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
-         serial.o gpmc.o
-
-obj-$(CONFIG_OMAP_MPU_TIMER)            += timer-gp.o
+obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \
+                devices.o serial.o gpmc.o timer-gp.o
 
 # Power Management
-obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
+obj-$(CONFIG_PM) += pm.o sleep.o
+
+# Clock framework
+obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o
 
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 64235dee5614..1c12d7c6c7fc 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -33,7 +33,6 @@
 #include <asm/arch/board.h>
 #include <asm/arch/common.h>
 #include <asm/arch/gpmc.h>
-#include "prcm-regs.h"
 
 #include <asm/io.h>
 
@@ -125,15 +124,18 @@ static inline void __init sdp2430_init_smc91x(void)
         int eth_cs;
         unsigned long cs_mem_base;
         unsigned int rate;
-        struct clk *l3ck;
+        struct clk *gpmc_fck;
 
         eth_cs = SDP2430_SMC91X_CS;
 
-        l3ck = clk_get(NULL, "core_l3_ck");
-        if (IS_ERR(l3ck))
-                rate = 100000000;
-        else
-                rate = clk_get_rate(l3ck);
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
 
         /* Make sure CS1 timings are correct, for 2430 always muxed */
         gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
@@ -160,7 +162,7 @@ static inline void __init sdp2430_init_smc91x(void)
 
         if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
                 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
-                return;
+                goto out;
         }
 
         sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
@@ -171,10 +173,13 @@ static inline void __init sdp2430_init_smc91x(void)
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                         OMAP24XX_ETHR_GPIO_IRQ);
                 gpmc_cs_free(eth_cs);
-                return;
+                goto out;
         }
         omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
 
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
 }
 
 static void __init omap_2430sdp_init_irq(void)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 7846551f0575..a1e1e6765b5b 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -26,6 +26,8 @@
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/leds.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
@@ -39,7 +41,7 @@
 #include <asm/arch/board.h>
 #include <asm/arch/common.h>
 #include <asm/arch/gpmc.h>
-#include "prcm-regs.h"
+#include <asm/arch/control.h>
 
 /* LED & Switch macros */
 #define LED0_GPIO13             13
@@ -187,17 +189,47 @@ static inline void __init apollon_init_smc91x(void)
 {
         unsigned long base;
 
+        unsigned int rate;
+        struct clk *gpmc_fck;
+        int eth_cs;
+
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
+
+        eth_cs = APOLLON_ETH_CS;
+
         /* Make sure CS1 timings are correct */
-        GPMC_CONFIG1_1 = 0x00011203;
-        GPMC_CONFIG2_1 = 0x001f1f01;
-        GPMC_CONFIG3_1 = 0x00080803;
-        GPMC_CONFIG4_1 = 0x1c091c09;
-        GPMC_CONFIG5_1 = 0x041f1f1f;
-        GPMC_CONFIG6_1 = 0x000004c4;
+        gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
+
+        if (rate >= 160000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else if (rate >= 130000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else {/* rate = 100000000 */
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+        }
 
         if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
                 printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
-                return;
+                goto out;
         }
         apollon_smc91x_resources[0].start = base + 0x300;
         apollon_smc91x_resources[0].end   = base + 0x30f;
@@ -208,9 +240,13 @@ static inline void __init apollon_init_smc91x(void)
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                         APOLLON_ETHR_GPIO_IRQ);
                 gpmc_cs_free(APOLLON_ETH_CS);
-                return;
+                goto out;
         }
         omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);
+
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
 }
 
 static void __init omap_apollon_init_irq(void)
@@ -330,6 +366,8 @@ static void __init apollon_usb_init(void)
 
 static void __init omap_apollon_init(void)
 {
+        u32 v;
+
         apollon_led_init();
         apollon_sw_init();
         apollon_flash_init();
@@ -339,7 +377,9 @@ static void __init omap_apollon_init(void)
         omap_cfg_reg(W19_24XX_SYS_NIRQ);
 
         /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
-        CONTROL_DEVCONF |= (1 << 24);
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        v |= (1 << 24);
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 
         /*
          * Make sure the serial ports are muxed on at this point.
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f125f432cc3e..d1915f99a5fa 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -19,6 +19,8 @@
 #include <linux/delay.h>
 #include <linux/workqueue.h>
 #include <linux/input.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
@@ -26,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
+#include <asm/arch/control.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/gpioexpander.h>
 #include <asm/arch/mux.h>
@@ -36,10 +39,13 @@
 #include <asm/arch/keypad.h>
 #include <asm/arch/menelaus.h>
 #include <asm/arch/dma.h>
-#include "prcm-regs.h"
+#include <asm/arch/gpmc.h>
 
 #include <asm/io.h>
 
+#define H4_FLASH_CS     0
+#define H4_SMC91X_CS    1
+
 static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
 static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
 
@@ -116,8 +122,6 @@ static struct flash_platform_data h4_flash_data = {
 };
 
 static struct resource h4_flash_resource = {
-        .start          = H4_CS0_BASE,
-        .end            = H4_CS0_BASE + SZ_64M - 1,
         .flags          = IORESOURCE_MEM,
 };
 
@@ -253,21 +257,107 @@ static struct platform_device *h4_devices[] __initdata = {
         &h4_lcd_device,
 };
 
+/* 2420 Sysboot setup (2430 is different) */
+static u32 get_sysboot_value(void)
+{
+        return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
+                (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
+                 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
+                 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
+}
+
+/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
+ *
+ * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
+ *  correctly.  The macro needs to look at production_id not just hawkeye.
+ */
+static u32 is_gpmc_muxed(void)
+{
+        u32 mux;
+        mux = get_sysboot_value();
+        if ((mux & 0xF) == 0xd)
+                return 1;       /* NAND config (could be either) */
+        if (mux & 0x2)          /* if mux'ed */
+                return 1;
+        else
+                return 0;
+}
+
 static inline void __init h4_init_debug(void)
 {
+        int eth_cs;
+        unsigned long cs_mem_base;
+        unsigned int muxed, rate;
+        struct clk *gpmc_fck;
+
+        eth_cs  = H4_SMC91X_CS;
+
+        gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck)) {
+                WARN_ON(1);
+                return;
+        }
+
+        clk_enable(gpmc_fck);
+        rate = clk_get_rate(gpmc_fck);
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
+
+        if (is_gpmc_muxed())
+                muxed = 0x200;
+        else
+                muxed = 0;
+
         /* Make sure CS1 timings are correct */
-        GPMC_CONFIG1_1 = 0x00011200;
-        GPMC_CONFIG2_1 = 0x001f1f01;
-        GPMC_CONFIG3_1 = 0x00080803;
-        GPMC_CONFIG4_1 = 0x1c091c09;
-        GPMC_CONFIG5_1 = 0x041f1f1f;
-        GPMC_CONFIG6_1 = 0x000004c4;
-        GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);
+        gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
+                          0x00011000 | muxed);
+
+        if (rate >= 160000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else if (rate >= 130000000) {
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
+        } else {/* rate = 100000000 */
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
+                gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
+        }
+
+        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
+                goto out;
+        }
+
         udelay(100);
 
         omap_cfg_reg(M15_24XX_GPIO92);
         if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0)
                 gpmc_cs_free(eth_cs);
+
+out:
+        clk_disable(gpmc_fck);
+        clk_put(gpmc_fck);
+}
+
+static void __init h4_init_flash(void)
+{
+        unsigned long base;
+
+        if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
+                printk("Can't request GPMC CS for flash\n");
+                return;
+        }
+        h4_flash_resource.start = base;
+        h4_flash_resource.end   = base + SZ_64M - 1;
 }
 
 static void __init omap_h4_init_irq(void)
@@ -275,6 +365,7 @@ static void __init omap_h4_init_irq(void)
         omap2_init_common_hw();
         omap_init_irq();
         omap_gpio_init();
+        h4_init_flash();
 }
 
 static struct omap_uart_config h4_uart_config __initdata = {
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e6e85b7b097b..b57ffb5a22a5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1,20 +1,19 @@
 /*
  *  linux/arch/arm/mach-omap2/clock.c
  *
- *  Copyright (C) 2005 Texas Instruments Inc.
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Created for OMAP2.
- *
- *  Cleaned up and modified to use omap shared clock framework by
- *  Tony Lindgren <tony@atomide.com>
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
  *
- *  Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#undef DEBUG
+
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
@@ -22,176 +21,227 @@
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <asm/bitops.h>
 
 #include <asm/io.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
+#include <asm/arch/cpu.h>
 #include <asm/div64.h>
 
-#include "prcm-regs.h"
 #include "memory.h"
+#include "sdrc.h"
 #include "clock.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
 
-#undef DEBUG
-
-//#define DOWN_VARIABLE_DPLL 1                  /* Experimental */
+#define MAX_CLOCK_ENABLE_WAIT           100000
 
-static struct prcm_config *curr_prcm_set;
-static u32 curr_perf_level = PRCM_FULL_SPEED;
-static struct clk *vclk;
-static struct clk *sclk;
+u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
  * Omap2 specific clock functions
  *-------------------------------------------------------------------------*/
 
-/* Recalculate SYST_CLK */
-static void omap2_sys_clk_recalc(struct clk * clk)
+/**
+ * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
+ * @clk: OMAP clock struct ptr to use
+ *
+ * Given a pointer to a source-selectable struct clk, read the hardware
+ * register and determine what its parent is currently set to.  Update the
+ * clk->parent field with the appropriate clk ptr.
+ */
+void omap2_init_clksel_parent(struct clk *clk)
 {
-        u32 div = PRCM_CLKSRC_CTRL;
-        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
-        div >>= clk->rate_offset;
-        clk->rate = (clk->parent->rate / div);
-        propagate_rate(clk);
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+        u32 r, found = 0;
+
+        if (!clk->clksel)
+                return;
+
+        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        r >>= __ffs(clk->clksel_mask);
+
+        for (clks = clk->clksel; clks->parent && !found; clks++) {
+                for (clkr = clks->rates; clkr->div && !found; clkr++) {
+                        if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
+                                if (clk->parent != clks->parent) {
+                                        pr_debug("clock: inited %s parent "
+                                                 "to %s (was %s)\n",
+                                                 clk->name, clks->parent->name,
+                                                 ((clk->parent) ?
+                                                  clk->parent->name : "NULL"));
+                                        clk->parent = clks->parent;
+                                };
+                                found = 1;
+                        }
+                }
+        }
+
+        if (!found)
+                printk(KERN_ERR "clock: init parent: could not find "
+                       "regval %0x for clock %s\n", r,  clk->name);
+
+        return;
 }
 
-static u32 omap2_get_dpll_rate(struct clk * tclk)
+/* Returns the DPLL rate */
+u32 omap2_get_dpll_rate(struct clk *clk)
 {
         long long dpll_clk;
-        int dpll_mult, dpll_div, amult;
+        u32 dpll_mult, dpll_div, dpll;
+        const struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        /* REVISIT: What do we return on error? */
+        if (!dd)
+                return 0;
+
+        dpll = __raw_readl(dd->mult_div1_reg);
+        dpll_mult = dpll & dd->mult_mask;
+        dpll_mult >>= __ffs(dd->mult_mask);
+        dpll_div = dpll & dd->div1_mask;
+        dpll_div >>= __ffs(dd->div1_mask);
 
-        dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff;    /* 10 bits */
-        dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f;        /* 4 bits */
-        dpll_clk = (long long)tclk->parent->rate * dpll_mult;
+        dpll_clk = (long long)clk->parent->rate * dpll_mult;
         do_div(dpll_clk, dpll_div + 1);
-        amult = CM_CLKSEL2_PLL & 0x3;
-        dpll_clk *= amult;
 
         return dpll_clk;
 }
 
-static void omap2_followparent_recalc(struct clk *clk)
-{
-        followparent_recalc(clk);
-}
-
-static void omap2_propagate_rate(struct clk * clk)
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+void omap2_fixed_divisor_recalc(struct clk *clk)
 {
-        if (!(clk->flags & RATE_FIXED))
-                clk->rate = clk->parent->rate;
+        WARN_ON(!clk->fixed_div);
 
-        propagate_rate(clk);
-}
+        clk->rate = clk->parent->rate / clk->fixed_div;
 
-static void omap2_set_osc_ck(int enable)
-{
-        if (enable)
-                PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
-        else
-                PRCM_CLKSRC_CTRL |= 0x3 << 3;
+        if (clk->flags & RATE_PROPAGATES)
+                propagate_rate(clk);
 }
 
-/* Enable an APLL if off */
-static void omap2_clk_fixed_enable(struct clk *clk)
+/**
+ * omap2_wait_clock_ready - wait for clock to enable
+ * @reg: physical address of clock IDLEST register
+ * @mask: value to mask against to determine if the clock is active
+ * @name: name of the clock (for printk)
+ *
+ * Returns 1 if the clock enabled in time, or 0 if it failed to enable
+ * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
+ */
+int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
 {
-        u32 cval, i=0;
+        int i = 0;
+        int ena = 0;
 
-        if (clk->enable_bit == 0xff)                    /* Parent will do it */
-                return;
+        /*
+         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+         * 34xx reverses this, just to keep us on our toes
+         */
+        if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
+                ena = mask;
+        } else if (cpu_mask & RATE_IN_343X) {
+                ena = 0;
+        }
 
-        cval = CM_CLKEN_PLL;
+        /* Wait for lock */
+        while (((__raw_readl(reg) & mask) != ena) &&
+               (i++ < MAX_CLOCK_ENABLE_WAIT)) {
+                udelay(1);
+        }
 
-        if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
-                return;
+        if (i < MAX_CLOCK_ENABLE_WAIT)
+                pr_debug("Clock %s stable after %d loops\n", name, i);
+        else
+                printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
+                       name, MAX_CLOCK_ENABLE_WAIT);
 
-        cval &= ~(0x3 << clk->enable_bit);
-        cval |= (0x3 << clk->enable_bit);
-        CM_CLKEN_PLL = cval;
 
-        if (clk == &apll96_ck)
-                cval = (1 << 8);
-        else if (clk == &apll54_ck)
-                cval = (1 << 6);
+        return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
+};
 
-        while (!(CM_IDLEST_CKGEN & cval)) {             /* Wait for lock */
-                ++i;
-                udelay(1);
-                if (i == 100000) {
-                        printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
-                        break;
-                }
-        }
-}
 
+/*
+ * Note: We don't need special code here for INVERT_ENABLE
+ * for the time being since INVERT_ENABLE only applies to clocks enabled by
+ * CM_CLKEN_PLL
+ */
 static void omap2_clk_wait_ready(struct clk *clk)
 {
-        unsigned long reg, other_reg, st_reg;
+        void __iomem *reg, *other_reg, *st_reg;
         u32 bit;
-        int i;
-
-        reg = (unsigned long) clk->enable_reg;
-        if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
-            reg == (unsigned long) &CM_FCLKEN2_CORE)
-                other_reg = (reg & ~0xf0) | 0x10;
-        else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
-                 reg == (unsigned long) &CM_ICLKEN2_CORE)
-                other_reg = (reg & ~0xf0) | 0x00;
+
+        /*
+         * REVISIT: This code is pretty ugly.  It would be nice to generalize
+         * it and pull it into struct clk itself somehow.
+         */
+        reg = clk->enable_reg;
+        if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
+            (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
+                other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
+        else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
+                 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
+                other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
         else
                 return;
 
+        /* REVISIT: What are the appropriate exclusions for 34XX? */
         /* No check for DSS or cam clocks */
-        if ((reg & 0x0f) == 0) {
-                if (clk->enable_bit <= 1 || clk->enable_bit == 31)
+        if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+                if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
+                    clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
+                    clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
                         return;
         }
 
+        /* REVISIT: What are the appropriate exclusions for 34XX? */
+        /* OMAP3: ignore DSS-mod clocks */
+        if (cpu_is_omap34xx() &&
+            (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0)))
+                return;
+
         /* Check if both functional and interface clocks
          * are running. */
         bit = 1 << clk->enable_bit;
         if (!(__raw_readl(other_reg) & bit))
                 return;
-        st_reg = (other_reg & ~0xf0) | 0x20;
-        i = 0;
-        while (!(__raw_readl(st_reg) & bit)) {
-                i++;
-                if (i == 100000) {
-                        printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
-                        break;
-                }
-        }
-        if (i)
-                pr_debug("Clock %s stable after %d loops\n", clk->name, i);
+        st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+
+        omap2_wait_clock_ready(st_reg, bit, clk->name);
 }
 
 /* Enables clock without considering parent dependencies or use count
  * REVISIT: Maybe change this to use clk->enable like on omap1?
  */
-static int _omap2_clk_enable(struct clk * clk)
+int _omap2_clk_enable(struct clk *clk)
 {
         u32 regval32;
 
-        if (clk->flags & ALWAYS_ENABLED)
+        if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
                 return 0;
 
-        if (unlikely(clk == &osc_ck)) {
-                omap2_set_osc_ck(1);
-                return 0;
-        }
+        if (clk->enable)
+                return clk->enable(clk);
 
         if (unlikely(clk->enable_reg == 0)) {
                 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
                        clk->name);
-                return 0;
-        }
-
-        if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
-                omap2_clk_fixed_enable(clk);
-                return 0;
+                return 0; /* REVISIT: -EINVAL */
         }
 
         regval32 = __raw_readl(clk->enable_reg);
-        regval32 |= (1 << clk->enable_bit);
+        if (clk->flags & INVERT_ENABLE)
+                regval32 &= ~(1 << clk->enable_bit);
+        else
+                regval32 |= (1 << clk->enable_bit);
         __raw_writel(regval32, clk->enable_reg);
         wmb();
 
@@ -200,44 +250,48 @@ static int _omap2_clk_enable(struct clk * clk)
         return 0;
 }
 
-/* Stop APLL */
-static void omap2_clk_fixed_disable(struct clk *clk)
-{
-        u32 cval;
-
-        if(clk->enable_bit == 0xff)             /* let parent off do it */
-                return;
-
-        cval = CM_CLKEN_PLL;
-        cval &= ~(0x3 << clk->enable_bit);
-        CM_CLKEN_PLL = cval;
-}
-
 /* Disables clock without considering parent dependencies or use count */
-static void _omap2_clk_disable(struct clk *clk)
+void _omap2_clk_disable(struct clk *clk)
 {
         u32 regval32;
 
-        if (unlikely(clk == &osc_ck)) {
-                omap2_set_osc_ck(0);
+        if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
                 return;
-        }
 
-        if (clk->enable_reg == 0)
+        if (clk->disable) {
+                clk->disable(clk);
                 return;
+        }
 
-        if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
-                omap2_clk_fixed_disable(clk);
+        if (clk->enable_reg == 0) {
+                /*
+                 * 'Independent' here refers to a clock which is not
+                 * controlled by its parent.
+                 */
+                printk(KERN_ERR "clock: clk_disable called on independent "
+                       "clock %s which has no enable_reg\n", clk->name);
                 return;
         }
 
         regval32 = __raw_readl(clk->enable_reg);
-        regval32 &= ~(1 << clk->enable_bit);
+        if (clk->flags & INVERT_ENABLE)
+                regval32 |= (1 << clk->enable_bit);
+        else
+                regval32 &= ~(1 << clk->enable_bit);
         __raw_writel(regval32, clk->enable_reg);
         wmb();
 }
 
-static int omap2_clk_enable(struct clk *clk)
+void omap2_clk_disable(struct clk *clk)
+{
+        if (clk->usecount > 0 && !(--clk->usecount)) {
+                _omap2_clk_disable(clk);
+                if (likely((u32)clk->parent))
+                        omap2_clk_disable(clk->parent);
+        }
+}
+
+int omap2_clk_enable(struct clk *clk)
 {
         int ret = 0;
 
@@ -261,519 +315,314 @@ static int omap2_clk_enable(struct clk *clk)
         return ret;
 }
 
-static void omap2_clk_disable(struct clk *clk)
-{
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                _omap2_clk_disable(clk);
-                if (likely((u32)clk->parent))
-                        omap2_clk_disable(clk->parent);
-        }
-}
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-static u32 omap2_dpll_round_rate(unsigned long target_rate)
-{
-        u32 high, low;
-
-        if ((CM_CLKSEL2_PLL & 0x3) == 1) {      /* DPLL clockout */
-                high = curr_prcm_set->dpll_speed * 2;
-                low = curr_prcm_set->dpll_speed;
-        } else {                                /* DPLL clockout x 2 */
-                high = curr_prcm_set->dpll_speed;
-                low = curr_prcm_set->dpll_speed / 2;
-        }
-
-#ifdef DOWN_VARIABLE_DPLL
-        if (target_rate > high)
-                return high;
-        else
-                return target_rate;
-#else
-        if (target_rate > low)
-                return high;
-        else
-                return low;
-#endif
-
-}
-
 /*
  * Used for clocks that are part of CLKSEL_xyz governed clocks.
  * REVISIT: Maybe change to use clk->enable() functions like on omap1?
  */
-static void omap2_clksel_recalc(struct clk * clk)
+void omap2_clksel_recalc(struct clk *clk)
 {
-        u32 fixed = 0, div = 0;
+        u32 div = 0;
 
-        if (clk == &dpll_ck) {
-                clk->rate = omap2_get_dpll_rate(clk);
-                fixed = 1;
-                div = 0;
-        }
+        pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
 
-        if (clk == &iva1_mpu_int_ifck) {
-                div = 2;
-                fixed = 1;
-        }
-
-        if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
-                clk->rate = sys_ck.rate;
+        div = omap2_clksel_get_divisor(clk);
+        if (div == 0)
                 return;
-        }
 
-        if (!fixed) {
-                div = omap2_clksel_get_divisor(clk);
-                if (div == 0)
-                        return;
-        }
+        if (unlikely(clk->rate == clk->parent->rate / div))
+                return;
+        clk->rate = clk->parent->rate / div;
 
-        if (div != 0) {
-                if (unlikely(clk->rate == clk->parent->rate / div))
-                        return;
-                clk->rate = clk->parent->rate / div;
-        }
+        pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
 
         if (unlikely(clk->flags & RATE_PROPAGATES))
                 propagate_rate(clk);
 }
 
-/*
- * Finds best divider value in an array based on the source and target
- * rates. The divider array must be sorted with smallest divider first.
+/**
+ * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
+ * @clk: OMAP struct clk ptr to inspect
+ * @src_clk: OMAP struct clk ptr of the parent clk to search for
+ *
+ * Scan the struct clksel array associated with the clock to find
+ * the element associated with the supplied parent clock address.
+ * Returns a pointer to the struct clksel on success or NULL on error.
  */
-static inline u32 omap2_divider_from_table(u32 size, u32 *div_array,
-                                           u32 src_rate, u32 tgt_rate)
+const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
+                                                struct clk *src_clk)
 {
-        int i, test_rate;
+        const struct clksel *clks;
 
-        if (div_array == NULL)
-                return ~1;
+        if (!clk->clksel)
+                return NULL;
 
-        for (i=0; i < size; i++) {
-                test_rate = src_rate / *div_array;
-                if (test_rate <= tgt_rate)
-                        return *div_array;
-                ++div_array;
+        for (clks = clk->clksel; clks->parent; clks++) {
+                if (clks->parent == src_clk)
+                        break; /* Found the requested parent */
         }
 
-        return ~0;      /* No acceptable divider */
+        if (!clks->parent) {
+                printk(KERN_ERR "clock: Could not find parent clock %s in "
+                       "clksel array of clock %s\n", src_clk->name,
+                       clk->name);
+                return NULL;
+        }
+
+        return clks;
 }
 
-/*
- * Find divisor for the given clock and target rate.
+/**
+ * omap2_clksel_round_rate_div - find divisor for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ * @new_div: ptr to where we should store the divisor
  *
+ * Finds 'best' divider value in an array based on the source and target
+ * rates.  The divider array must be sorted with smallest divider first.
  * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
  * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
  */
-static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate,
-        u32 *new_div)
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+                                u32 *new_div)
 {
-        u32 gfx_div[] = {2, 3, 4};
-        u32 sysclkout_div[] = {1, 2, 4, 8, 16};
-        u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16};
-        u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18};
-        u32 best_div = ~0, asize = 0;
-        u32 *div_array = NULL;
-
-        switch (tclk->flags & SRC_RATE_SEL_MASK) {
-        case CM_GFX_SEL1:
-                asize = 3;
-                div_array = gfx_div;
-                break;
-        case CM_PLL_SEL1:
-                return omap2_dpll_round_rate(target_rate);
-        case CM_SYSCLKOUT_SEL1:
-                asize = 5;
-                div_array = sysclkout_div;
-                break;
-        case CM_CORE_SEL1:
-                if(tclk == &dss1_fck){
-                        if(tclk->parent == &core_ck){
-                                asize = 10;
-                                div_array = dss1_div;
-                        } else {
-                                *new_div = 0; /* fixed clk */
-                                return(tclk->parent->rate);
-                        }
-                } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){
-                        if(tclk->parent == &core_ck){
-                                asize = 10;
-                                div_array = vylnq_div;
-                        } else {
-                                *new_div = 0; /* fixed clk */
-                                return(tclk->parent->rate);
-                        }
-                }
-                break;
+        unsigned long test_rate;
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
+        u32 last_div = 0;
+
+        printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
+               clk->name, target_rate);
+
+        *new_div = 1;
+
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
+                return ~0;
+
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (!(clkr->flags & cpu_mask))
+                    continue;
+
+                /* Sanity check */
+                if (clkr->div <= last_div)
+                        printk(KERN_ERR "clock: clksel_rate table not sorted "
+                               "for clock %s", clk->name);
+
+                last_div = clkr->div;
+
+                test_rate = clk->parent->rate / clkr->div;
+
+                if (test_rate <= target_rate)
+                        break; /* found it */
         }
 
-        best_div = omap2_divider_from_table(asize, div_array,
-         tclk->parent->rate, target_rate);
-        if (best_div == ~0){
-                *new_div = 1;
-                return best_div; /* signal error */
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find divisor for target "
+                       "rate %ld for clock %s parent %s\n", target_rate,
+                       clk->name, clk->parent->name);
+                return ~0;
         }
 
-        *new_div = best_div;
-        return (tclk->parent->rate / best_div);
+        *new_div = clkr->div;
+
+        printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
+               (clk->parent->rate / clkr->div));
+
+        return (clk->parent->rate / clkr->div);
 }
 
-/* Given a clock and a rate apply a clock specific rounding function */
-static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+/**
+ * omap2_clksel_round_rate - find rounded rate for the given clock and rate
+ * @clk: OMAP struct clk to use
+ * @target_rate: desired clock rate
+ *
+ * Compatibility wrapper for OMAP clock framework
+ * Finds best target rate based on the source clock and possible dividers.
+ * rates. The divider array must be sorted with smallest divider first.
+ * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
+ * they are only settable as part of virtual_prcm set.
+ *
+ * Returns the rounded clock rate or returns 0xffffffff on error.
+ */
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
 {
-        u32 new_div = 0;
-        int valid_rate;
+        u32 new_div;
 
-        if (clk->flags & RATE_FIXED)
-                return clk->rate;
+        return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
+}
 
-        if (clk->flags & RATE_CKCTL) {
-                valid_rate = omap2_clksel_round_rate(clk, rate, &new_div);
-                return valid_rate;
-        }
 
+/* Given a clock and a rate apply a clock specific rounding function */
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
+{
         if (clk->round_rate != 0)
                 return clk->round_rate(clk, rate);
 
+        if (clk->flags & RATE_FIXED)
+                printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
+                       "on fixed-rate clock %s\n", clk->name);
+
         return clk->rate;
 }
 
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compensate for the shifted DLL value in unlock mode.
+/**
+ * omap2_clksel_to_divisor() - turn clksel field value into integer divider
+ * @clk: OMAP struct clk to use
+ * @field_val: register field value to find
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a register field
+ * value to search for, find the corresponding clock divisor.  The register
+ * field value should be pre-masked and shifted down so the LSB is at bit 0
+ * before calling.  Returns 0 on error
  */
-static u32 omap2_dll_force_needed(void)
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
 {
-        u32 dll_state = SDRC_DLLA_CTRL;         /* dlla and dllb are a set */
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-        if ((dll_state & (1 << 2)) == (1 << 2))
-                return 1;
-        else
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
                 return 0;
-}
 
-static u32 omap2_reprogram_sdrc(u32 level, u32 force)
-{
-        u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
-        u32 prev = curr_perf_level, flags;
-
-        if ((curr_perf_level == level) && !force)
-                return prev;
-
-        m_type = omap2_memory_get_type();
-        slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
-        fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
-
-        if (level == PRCM_HALF_SPEED) {
-                local_irq_save(flags);
-                PRCM_VOLTSETUP = 0xffff;
-                omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
-                                          slow_dll_ctrl, m_type);
-                curr_perf_level = PRCM_HALF_SPEED;
-                local_irq_restore(flags);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
+                        break;
         }
-        if (level == PRCM_FULL_SPEED) {
-                local_irq_save(flags);
-                PRCM_VOLTSETUP = 0xffff;
-                omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
-                                          fast_dll_ctrl, m_type);
-                curr_perf_level = PRCM_FULL_SPEED;
-                local_irq_restore(flags);
+
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find fieldval %d for "
+                       "clock %s parent %s\n", field_val, clk->name,
+                       clk->parent->name);
+                return 0;
         }
 
-        return prev;
+        return clkr->div;
 }
 
-static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
+/**
+ * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
+ * @clk: OMAP struct clk to use
+ * @div: integer divisor to search for
+ *
+ * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
+ * find the corresponding register field value.  The return register value is
+ * the value before left-shifting.  Returns 0xffffffff on error
+ */
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
 {
-        u32 flags, cur_rate, low, mult, div, valid_rate, done_rate;
-        u32 bypass = 0;
-        struct prcm_config tmpset;
-        int ret = -EINVAL;
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-        local_irq_save(flags);
-        cur_rate = omap2_get_dpll_rate(&dpll_ck);
-        mult = CM_CLKSEL2_PLL & 0x3;
-
-        if ((rate == (cur_rate / 2)) && (mult == 2)) {
-                omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
-        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
-        } else if (rate != cur_rate) {
-                valid_rate = omap2_dpll_round_rate(rate);
-                if (valid_rate != rate)
-                        goto dpll_exit;
-
-                if ((CM_CLKSEL2_PLL & 0x3) == 1)
-                        low = curr_prcm_set->dpll_speed;
-                else
-                        low = curr_prcm_set->dpll_speed / 2;
-
-                tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
-                tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
-                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
-                tmpset.cm_clksel2_pll &= ~0x3;
-                if (rate > low) {
-                        tmpset.cm_clksel2_pll |= 0x2;
-                        mult = ((rate / 2) / 1000000);
-                        done_rate = PRCM_FULL_SPEED;
-                } else {
-                        tmpset.cm_clksel2_pll |= 0x1;
-                        mult = (rate / 1000000);
-                        done_rate = PRCM_HALF_SPEED;
-                }
-                tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
-
-                /* Worst case */
-                tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;
-
-                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
-                        bypass = 1;
+        /* should never happen */
+        WARN_ON(div == 0);
 
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */
-
-                /* Force dll lock mode */
-                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
-                               bypass);
+        clks = omap2_get_clksel_by_parent(clk, clk->parent);
+        if (clks == NULL)
+                return 0;
 
-                /* Errata: ret dll entry state */
-                omap2_init_memory_params(omap2_dll_force_needed());
-                omap2_reprogram_sdrc(done_rate, 0);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if ((clkr->flags & cpu_mask) && (clkr->div == div))
+                        break;
         }
-        omap2_clksel_recalc(&dpll_ck);
-        ret = 0;
 
-dpll_exit:
-        local_irq_restore(flags);
-        return(ret);
-}
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find divisor %d for "
+                       "clock %s parent %s\n", div, clk->name,
+                       clk->parent->name);
+                return 0;
+        }
 
-/* Just return the MPU speed */
-static void omap2_mpu_recalc(struct clk * clk)
-{
-        clk->rate = curr_prcm_set->mpu_speed;
+        return clkr->val;
 }
 
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
+/**
+ * omap2_get_clksel - find clksel register addr & field mask for a clk
+ * @clk: struct clk to use
+ * @field_mask: ptr to u32 to store the register field mask
  *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
+ * Returns the address of the clksel register upon success or NULL on error.
  */
-static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate)
+void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
 {
-        struct prcm_config * ptr;
-        long highest_rate;
-
-        if (clk != &virt_prcm_set)
-                return -EINVAL;
-
-        highest_rate = -EINVAL;
-
-        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
-                if (ptr->xtal_speed != sys_ck.rate)
-                        continue;
+        if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0)))
+                return NULL;
 
-                highest_rate = ptr->mpu_speed;
+        *field_mask = clk->clksel_mask;
 
-                /* Can check only after xtal frequency check */
-                if (ptr->mpu_speed <= rate)
-                        break;
-        }
-        return highest_rate;
+        return clk->clksel_reg;
 }
 
-/*
- * omap2_convert_field_to_div() - turn field value into integer divider
+/**
+ * omap2_clksel_get_divisor - get current divider applied to parent clock.
+ * @clk: OMAP struct clk to use.
+ *
+ * Returns the integer divisor upon success or 0 on error.
  */
-static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val)
+u32 omap2_clksel_get_divisor(struct clk *clk)
 {
-        u32 i;
-        u32 clkout_array[] = {1, 2, 4, 8, 16};
+        u32 field_mask, field_val;
+        void __iomem *div_addr;
 
-        if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) {
-                for (i = 0; i < 5; i++) {
-                        if (field_val == i)
-                                return clkout_array[i];
-                }
-                return ~0;
-        } else
-                return field_val;
+        div_addr = omap2_get_clksel(clk, &field_mask);
+        if (div_addr == 0)
+                return 0;
+
+        field_val = __raw_readl(div_addr) & field_mask;
+        field_val >>= __ffs(field_mask);
+
+        return omap2_clksel_to_divisor(clk, field_val);
 }
 
-/*
- * Returns the CLKSEL divider register value
- * REVISIT: This should be cleaned up to work nicely with void __iomem *
- */
-static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
-                            struct clk *clk)
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 {
-        int ret = ~0;
-        u32 reg_val, div_off;
-        u32 div_addr = 0;
-        u32 mask = ~0;
-
-        div_off = clk->rate_offset;
-
-        switch ((*div_sel & SRC_RATE_SEL_MASK)) {
-        case CM_MPU_SEL1:
-                div_addr = (u32)&CM_CLKSEL_MPU;
-                mask = 0x1f;
-                break;
-        case CM_DSP_SEL1:
-                div_addr = (u32)&CM_CLKSEL_DSP;
-                if (cpu_is_omap2420()) {
-                        if ((div_off == 0) || (div_off == 8))
-                                mask = 0x1f;
-                        else if (div_off == 5)
-                                mask = 0x3;
-                } else if (cpu_is_omap2430()) {
-                        if (div_off == 0)
-                                mask = 0x1f;
-                        else if (div_off == 5)
-                                mask = 0x3;
-                }
-                break;
-        case CM_GFX_SEL1:
-                div_addr = (u32)&CM_CLKSEL_GFX;
-                if (div_off == 0)
-                        mask = 0x7;
-                break;
-        case CM_MODEM_SEL1:
-                div_addr = (u32)&CM_CLKSEL_MDM;
-                if (div_off == 0)
-                        mask = 0xf;
-                break;
-        case CM_SYSCLKOUT_SEL1:
-                div_addr = (u32)&PRCM_CLKOUT_CTRL;
-                if ((div_off == 3) || (div_off == 11))
-                        mask= 0x3;
-                break;
-        case CM_CORE_SEL1:
-                div_addr = (u32)&CM_CLKSEL1_CORE;
-                switch (div_off) {
-                case 0:                                 /* l3 */
-                case 8:                                 /* dss1 */
-                case 15:                                /* vylnc-2420 */
-                case 20:                                /* ssi */
-                        mask = 0x1f; break;
-                case 5:                                 /* l4 */
-                        mask = 0x3; break;
-                case 13:                                /* dss2 */
-                        mask = 0x1; break;
-                case 25:                                /* usb */
-                        mask = 0x7; break;
-                }
-        }
+        u32 field_mask, field_val, reg_val, validrate, new_div = 0;
+        void __iomem *div_addr;
 
-        *field_mask = mask;
+        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
+        if (validrate != rate)
+                return -EINVAL;
 
-        if (unlikely(mask == ~0))
-                div_addr = 0;
+        div_addr = omap2_get_clksel(clk, &field_mask);
+        if (div_addr == 0)
+                return -EINVAL;
 
-        *div_sel = div_addr;
+        field_val = omap2_divisor_to_clksel(clk, new_div);
+        if (field_val == ~0)
+                return -EINVAL;
 
-        if (unlikely(div_addr == 0))
-                return ret;
+        reg_val = __raw_readl(div_addr);
+        reg_val &= ~field_mask;
+        reg_val |= (field_val << __ffs(field_mask));
+        __raw_writel(reg_val, div_addr);
+        wmb();
 
-        /* Isolate field */
-        reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
+        clk->rate = clk->parent->rate / new_div;
 
-        /* Normalize back to divider value */
-        reg_val >>= div_off;
+        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
+                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+                wmb();
+        }
 
-        return reg_val;
+        return 0;
 }
 
-/*
- * Return divider to be applied to parent clock.
- * Return 0 on error.
- */
-static u32 omap2_clksel_get_divisor(struct clk *clk)
-{
-        int ret = 0;
-        u32 div, div_sel, div_off, field_mask, field_val;
-
-        /* isolate control register */
-        div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-
-        div_off = clk->rate_offset;
-        field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
-        if (div_sel == 0)
-                return ret;
-
-        div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-        div = omap2_clksel_to_divisor(div_sel, field_val);
-
-        return div;
-}
 
 /* Set the clock rate for a clock source */
-static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
-
+int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         int ret = -EINVAL;
-        void __iomem * reg;
-        u32 div_sel, div_off, field_mask, field_val, reg_val, validrate;
-        u32 new_div = 0;
-
-        if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) {
-                if (clk == &dpll_ck)
-                        return omap2_reprogram_dpll(clk, rate);
-
-                /* Isolate control register */
-                div_sel = (SRC_RATE_SEL_MASK & clk->flags);
-                div_off = clk->rate_offset;
-
-                validrate = omap2_clksel_round_rate(clk, rate, &new_div);
-                if (validrate != rate)
-                        return(ret);
 
-                field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
-                if (div_sel == 0)
-                        return ret;
-
-                if (clk->flags & CM_SYSCLKOUT_SEL1) {
-                        switch (new_div) {
-                        case 16:
-                                field_val = 4;
-                                break;
-                        case 8:
-                                field_val = 3;
-                                break;
-                        case 4:
-                                field_val = 2;
-                                break;
-                        case 2:
-                                field_val = 1;
-                                break;
-                        case 1:
-                                field_val = 0;
-                                break;
-                        }
-                } else
-                        field_val = new_div;
+        pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
 
-                reg = (void __iomem *)div_sel;
-
-                reg_val = __raw_readl(reg);
-                reg_val &= ~(field_mask << div_off);
-                reg_val |= (field_val << div_off);
-                __raw_writel(reg_val, reg);
-                wmb();
-                clk->rate = clk->parent->rate / field_val;
+        /* CONFIG_PARTICIPANT clocks are changed only in sets via the
+           rate table mechanism, driven by mpu_speed  */
+        if (clk->flags & CONFIG_PARTICIPANT)
+                return -EINVAL;
 
-                if (clk->flags & DELAYED_APP) {
-                        __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
-                        wmb();
-                }
-                ret = 0;
-        } else if (clk->set_rate != 0)
+        /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
+        if (clk->set_rate != 0)
                 ret = clk->set_rate(clk, rate);
 
         if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
@@ -782,242 +631,92 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
         return ret;
 }
 
-/* Converts encoded control register address into a full address */
-static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
-                               struct clk *src_clk, u32 *field_mask)
-{
-        u32 val = ~0, src_reg_addr = 0, mask = 0;
-
-        /* Find target control register.*/
-        switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
-        case CM_CORE_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL1_CORE;
-                if (reg_offset == 13) {                 /* DSS2_fclk */
-                        mask = 0x1;
-                        if (src_clk == &sys_ck)
-                                val = 0;
-                        if (src_clk == &func_48m_ck)
-                                val = 1;
-                } else if (reg_offset == 8) {           /* DSS1_fclk */
-                        mask = 0x1f;
-                        if (src_clk == &sys_ck)
-                                val = 0;
-                        else if (src_clk == &core_ck)   /* divided clock */
-                                val = 0x10;             /* rate needs fixing */
-                } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
-                        mask = 0x1F;
-                        if(src_clk == &func_96m_ck)
-                                val = 0;
-                        else if (src_clk == &core_ck)
-                                val = 0x10;
-                }
-                break;
-        case CM_CORE_SEL2:
-                src_reg_addr = (u32)&CM_CLKSEL2_CORE;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &sys_ck)
-                        val = 0x1;
-                if (src_clk == &alt_ck)
-                        val = 0x2;
-                break;
-        case CM_WKUP_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL_WKUP;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &sys_ck)
-                        val = 0x1;
-                if (src_clk == &alt_ck)
-                        val = 0x2;
-                break;
-        case CM_PLL_SEL1:
-                src_reg_addr = (u32)&CM_CLKSEL1_PLL;
-                mask = 0x1;
-                if (reg_offset == 0x3) {
-                        if (src_clk == &apll96_ck)
-                                val = 0;
-                        if (src_clk == &alt_ck)
-                                val = 1;
-                }
-                else if (reg_offset == 0x5) {
-                        if (src_clk == &apll54_ck)
-                                val = 0;
-                        if (src_clk == &alt_ck)
-                                val = 1;
-                }
-                break;
-        case CM_PLL_SEL2:
-                src_reg_addr = (u32)&CM_CLKSEL2_PLL;
-                mask = 0x3;
-                if (src_clk == &func_32k_ck)
-                        val = 0x0;
-                if (src_clk == &dpll_ck)
-                        val = 0x2;
-                break;
-        case CM_SYSCLKOUT_SEL1:
-                src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
-                mask = 0x3;
-                if (src_clk == &dpll_ck)
-                        val = 0;
-                if (src_clk == &sys_ck)
-                        val = 1;
-                if (src_clk == &func_96m_ck)
-                        val = 2;
-                if (src_clk == &func_54m_ck)
-                        val = 3;
-                break;
-        }
-
-        if (val == ~0)                  /* Catch errors in offset */
-                *type_to_addr = 0;
-        else
-                *type_to_addr = src_reg_addr;
-        *field_mask = mask;
-
-        return val;
-}
-
-static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
+/*
+ * Converts encoded control register address into a full address
+ * On error, *src_addr will be returned as 0.
+ */
+static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
+                                      struct clk *src_clk, u32 *field_mask,
+                                      struct clk *clk, u32 *parent_div)
 {
-        void __iomem * reg;
-        u32 src_sel, src_off, field_val, field_mask, reg_val, rate;
-        int ret = -EINVAL;
-
-        if (unlikely(clk->flags & CONFIG_PARTICIPANT))
-                return ret;
-
-        if (clk->flags & SRC_SEL_MASK) {        /* On-chip SEL collection */
-                src_sel = (SRC_RATE_SEL_MASK & clk->flags);
-                src_off = clk->src_offset;
-
-                if (src_sel == 0)
-                        goto set_parent_error;
-
-                field_val = omap2_get_src_field(&src_sel, src_off, new_parent,
-                                                &field_mask);
-
-                reg = (void __iomem *)src_sel;
-
-                if (clk->usecount > 0)
-                        _omap2_clk_disable(clk);
-
-                /* Set new source value (previous dividers if any in effect) */
-                reg_val = __raw_readl(reg) & ~(field_mask << src_off);
-                reg_val |= (field_val << src_off);
-                __raw_writel(reg_val, reg);
-                wmb();
+        const struct clksel *clks;
+        const struct clksel_rate *clkr;
 
-                if (clk->flags & DELAYED_APP) {
-                        __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
-                        wmb();
-                }
-                if (clk->usecount > 0)
-                        _omap2_clk_enable(clk);
-
-                clk->parent = new_parent;
+        *parent_div = 0;
+        *src_addr = 0;
 
-                /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/
-                if ((new_parent == &core_ck) && (clk == &dss1_fck))
-                        clk->rate = new_parent->rate / 0x10;
-                else
-                        clk->rate = new_parent->rate;
+        clks = omap2_get_clksel_by_parent(clk, src_clk);
+        if (clks == NULL)
+                return 0;
 
-                if (unlikely(clk->flags & RATE_PROPAGATES))
-                        propagate_rate(clk);
+        for (clkr = clks->rates; clkr->div; clkr++) {
+                if (clkr->flags & (cpu_mask | DEFAULT_RATE))
+                        break; /* Found the default rate for this platform */
+        }
 
+        if (!clkr->div) {
+                printk(KERN_ERR "clock: Could not find default rate for "
+                       "clock %s parent %s\n", clk->name,
+                       src_clk->parent->name);
                 return 0;
-        } else {
-                clk->parent = new_parent;
-                rate = new_parent->rate;
-                omap2_clk_set_rate(clk, rate);
-                ret = 0;
         }
 
- set_parent_error:
-        return ret;
+        /* Should never happen.  Add a clksel mask to the struct clk. */
+        WARN_ON(clk->clksel_mask == 0);
+
+        *field_mask = clk->clksel_mask;
+        *src_addr = clk->clksel_reg;
+        *parent_div = clkr->div;
+
+        return clkr->val;
 }
 
-/* Sets basic clocks based on the specified rate */
-static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
+int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 {
-        u32 flags, cur_rate, done_rate, bypass = 0;
-        u8 cpu_mask = 0;
-        struct prcm_config *prcm;
-        unsigned long found_speed = 0;
+        void __iomem *src_addr;
+        u32 field_val, field_mask, reg_val, parent_div;
 
-        if (clk != &virt_prcm_set)
+        if (unlikely(clk->flags & CONFIG_PARTICIPANT))
                 return -EINVAL;
 
-        /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */
-        if (cpu_is_omap2420())
-                cpu_mask = RATE_IN_242X;
-        else if (cpu_is_omap2430())
-                cpu_mask = RATE_IN_243X;
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-
-                if (prcm->mpu_speed <= rate) {
-                        found_speed = prcm->mpu_speed;
-                        break;
-                }
-        }
-
-        if (!found_speed) {
-                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
-         rate / 1000000);
+        if (!clk->clksel)
                 return -EINVAL;
-        }
-
-        curr_prcm_set = prcm;
-        cur_rate = omap2_get_dpll_rate(&dpll_ck);
-
-        if (prcm->dpll_speed == cur_rate / 2) {
-                omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);
-        } else if (prcm->dpll_speed == cur_rate * 2) {
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
-        } else if (prcm->dpll_speed != cur_rate) {
-                local_irq_save(flags);
 
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        bypass = 1;
+        field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
+                                               &field_mask, clk, &parent_div);
+        if (src_addr == 0)
+                return -EINVAL;
 
-                if ((prcm->cm_clksel2_pll & 0x3) == 2)
-                        done_rate = PRCM_FULL_SPEED;
-                else
-                        done_rate = PRCM_HALF_SPEED;
+        if (clk->usecount > 0)
+                _omap2_clk_disable(clk);
 
-                /* MPU divider */
-                CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
+        /* Set new source value (previous dividers if any in effect) */
+        reg_val = __raw_readl(src_addr) & ~field_mask;
+        reg_val |= (field_val << __ffs(field_mask));
+        __raw_writel(reg_val, src_addr);
+        wmb();
 
-                /* dsp + iva1 div(2420), iva2.1(2430) */
-                CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
+        if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
+                __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
+                wmb();
+        }
 
-                CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
+        if (clk->usecount > 0)
+                _omap2_clk_enable(clk);
 
-                /* Major subsystem dividers */
-                CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
-                if (cpu_is_omap2430())
-                        CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
+        clk->parent = new_parent;
 
-                /* x2 to enter init_mem */
-                omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);
+        /* CLKSEL clocks follow their parents' rates, divided by a divisor */
+        clk->rate = new_parent->rate;
 
-                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
-                               bypass);
+        if (parent_div > 0)
+                clk->rate /= parent_div;
 
-                omap2_init_memory_params(omap2_dll_force_needed());
-                omap2_reprogram_sdrc(done_rate, 0);
+        pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
+                 clk->name, clk->parent->name, clk->rate);
 
-                local_irq_restore(flags);
-        }
-        omap2_clksel_recalc(&dpll_ck);
+        if (unlikely(clk->flags & RATE_PROPAGATES))
+                propagate_rate(clk);
 
         return 0;
 }
@@ -1027,150 +726,17 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
  *-------------------------------------------------------------------------*/
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
-static void __init omap2_clk_disable_unused(struct clk *clk)
+void omap2_clk_disable_unused(struct clk *clk)
 {
-        u32 regval32;
+        u32 regval32, v;
+
+        v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
 
         regval32 = __raw_readl(clk->enable_reg);
-        if ((regval32 & (1 << clk->enable_bit)) == 0)
+        if ((regval32 & (1 << clk->enable_bit)) == v)
                 return;
 
         printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
         _omap2_clk_disable(clk);
 }
-#else
-#define omap2_clk_disable_unused        NULL
 #endif
-
-static struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-};
-
-static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
-{
-        u32 div, aplls, sclk = 13000000;
-
-        aplls = CM_CLKSEL1_PLL;
-        aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
-        aplls >>= 23;                   /* Isolate field, 0,2,3 */
-
-        if (aplls == 0)
-                sclk = 19200000;
-        else if (aplls == 2)
-                sclk = 13000000;
-        else if (aplls == 3)
-                sclk = 12000000;
-
-        div = PRCM_CLKSRC_CTRL;
-        div &= ((1 << 7) | (1 << 6));
-        div >>= sys->rate_offset;
-
-        osc->rate = sclk * div;
-        sys->rate = sclk;
-}
-
-/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2_clk_prepare_for_reboot(void)
-{
-        u32 rate;
-
-        if (vclk == NULL || sclk == NULL)
-                return;
-
-        rate = clk_get_rate(sclk);
-        clk_set_rate(vclk, rate);
-}
-
-/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
- */
-static int __init omap2_clk_arch_init(void)
-{
-        if (!mpurate)
-                return -EINVAL;
-
-        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
-                printk(KERN_ERR "Could not find matching MPU rate\n");
-
-        propagate_rate(&osc_ck);                /* update main root fast */
-        propagate_rate(&func_32k_ck);           /* update main root slow */
-
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        return 0;
-}
-arch_initcall(omap2_clk_arch_init);
-
-int __init omap2_clk_init(void)
-{
-        struct prcm_config *prcm;
-        struct clk ** clkp;
-        u32 clkrate;
-
-        clk_init(&omap2_clk_functions);
-        omap2_get_crystal_rate(&osc_ck, &sys_ck);
-
-        for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-             clkp++) {
-
-                if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
-                        clk_register(*clkp);
-                        continue;
-                }
-
-                if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
-                        clk_register(*clkp);
-                        continue;
-                }
-        }
-
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2_get_dpll_rate(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                         break;
-        }
-        curr_prcm_set = prcm;
-
-        propagate_rate(&osc_ck);                /* update main root fast */
-        propagate_rate(&func_32k_ck);           /* update main root slow */
-
-        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable(&sync_32k_ick);
-        clk_enable(&omapctrl_ick);
-
-        /* Force the APLLs always active. The clocks are idled
-         * automatically by hardware. */
-        clk_enable(&apll96_ck);
-        clk_enable(&apll54_ck);
-
-        if (cpu_is_omap2430())
-                clk_enable(&sdrc_ick);
-
-        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4f791866b910..d5980a9e09a4 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1,13 +1,12 @@
 /*
- *  linux/arch/arm/mach-omap24xx/clock.h
+ *  linux/arch/arm/mach-omap2/clock.h
  *
- *  Copyright (C) 2005 Texas Instruments Inc.
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Created for OMAP2.
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
  *
- *  Copyright (C) 2004 Nokia corporation
- *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,2095 +16,53 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
 
-static void omap2_sys_clk_recalc(struct clk * clk);
-static void omap2_clksel_recalc(struct clk * clk);
-static void omap2_followparent_recalc(struct clk * clk);
-static void omap2_propagate_rate(struct clk * clk);
-static void omap2_mpu_recalc(struct clk * clk);
-static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
-static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
-static void omap2_clk_disable(struct clk *clk);
-static void omap2_sys_clk_recalc(struct clk * clk);
-static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
-static u32 omap2_clksel_get_divisor(struct clk *clk);
-
-
-#define RATE_IN_242X    (1 << 0)
-#define RATE_IN_243X    (1 << 1)
-
-/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
- * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- */
-struct prcm_config {
-        unsigned long xtal_speed;       /* crystal rate */
-        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
-        unsigned long mpu_speed;        /* speed of MPU */
-        unsigned long cm_clksel_mpu;    /* mpu divider */
-        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
-        unsigned long cm_clksel_gfx;    /* gfx dividers */
-        unsigned long cm_clksel1_core;  /* major subsystem dividers */
-        unsigned long cm_clksel1_pll;   /* m,n */
-        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
-        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
-        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
-};
-
-/* Mask for clksel which support parent settign in set_rate */
-#define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
-                        CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
-
-/* Mask for clksel regs which support rate operations */
-#define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
-                        CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
-                        CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
-                        CM_SYSCLKOUT_SEL1)
-
-/*
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- */
-
-/* Core fields for cm_clksel, not ratio governed */
-#define RX_CLKSEL_DSS1                  (0x10 << 8)
-#define RX_CLKSEL_DSS2                  (0x0 << 13)
-#define RX_CLKSEL_SSI                   (0x5 << 20)
-
-/*-------------------------------------------------------------------------
- * Voltage/DPLL ratios
- *-------------------------------------------------------------------------*/
-
-/* 2430 Ratio's, 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3                    (4 << 0)
-#define R1_CLKSEL_L4                    (2 << 5)
-#define R1_CLKSEL_USB                   (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R1_CLKSEL_L4 | R1_CLKSEL_L3
-#define R1_CLKSEL_MPU                   (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP                   (2 << 0)
-#define R1_CLKSEL_DSP_IF                (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
-#define R1_CLKSEL_GFX                   (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM                   (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3                    (6 << 0)
-#define R2_CLKSEL_L4                    (2 << 5)
-#define R2_CLKSEL_USB                   (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R2_CLKSEL_L4 | R2_CLKSEL_L3
-#define R2_CLKSEL_MPU                   (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP                   (2 << 0)
-#define R2_CLKSEL_DSP_IF                (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
-#define R2_CLKSEL_GFX                   (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM                   (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
-
-/* 2430-Ratio Bootm (BYPASS) */
-#define RB_CLKSEL_L3                    (1 << 0)
-#define RB_CLKSEL_L4                    (1 << 5)
-#define RB_CLKSEL_USB                   (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RB_CLKSEL_L4 | RB_CLKSEL_L3
-#define RB_CLKSEL_MPU                   (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP                   (1 << 0)
-#define RB_CLKSEL_DSP_IF                (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
-#define RB_CLKSEL_GFX                   (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM                   (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
-
-/* 2420 Ratio Equivalents */
-#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
-#define RXX_CLKSEL_SSI                  (0x8 << 20)
-
-/* 2420-PRCM III 532MHz core */
-#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
-#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
-#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
-#define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
-                                        RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
-                                        RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
-                                        RIII_CLKSEL_L3
-#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
-#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
-#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
-#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
-#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
-#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
-#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
-#define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
-                                        RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
-                                        RIII_CLKSEL_DSP
-#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
-#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
-
-/* 2420-PRCM II 600MHz core */
-#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
-#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
-#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
-#define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
-                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RII_CLKSEL_L4 | RII_CLKSEL_L3
-#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
-#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
-#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
-#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
-#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
-#define RII_CLKSEL_IVA                  (6 << 8)        /* iva1 - 200MHz */
-#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
-#define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
-                                        RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
-                                        RII_CLKSEL_DSP
-#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
-#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
-
-/* 2420-PRCM VII (boot) */
-#define RVII_CLKSEL_L3                  (1 << 0)
-#define RVII_CLKSEL_L4                  (1 << 5)
-#define RVII_CLKSEL_DSS1                (1 << 8)
-#define RVII_CLKSEL_DSS2                (0 << 13)
-#define RVII_CLKSEL_VLYNQ               (1 << 15)
-#define RVII_CLKSEL_SSI                 (1 << 20)
-#define RVII_CLKSEL_USB                 (1 << 25)
-
-#define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
-                                        RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
-                                        RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
-
-#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
-#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
+#include <asm/arch/clock.h>
 
-#define RVII_CLKSEL_DSP                 (1 << 0)
-#define RVII_CLKSEL_DSP_IF              (1 << 5)
-#define RVII_SYNC_DSP                   (0 << 7)
-#define RVII_CLKSEL_IVA                 (1 << 8)
-#define RVII_SYNC_IVA                   (0 << 13)
-#define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
-                                        RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
-
-#define RVII_CLKSEL_GFX                 (1 << 0)
-#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
-
-/*-------------------------------------------------------------------------
- * 2430 Target modes: Along with each configuration the CPU has several
- * modes which goes along with them. Modes mainly are the addition of
- * describe DPLL combinations to go along with a ratio.
- *-------------------------------------------------------------------------*/
-
-/* Hardware governed */
-#define MX_48M_SRC                      (0 << 3)
-#define MX_54M_SRC                      (0 << 5)
-#define MX_APLLS_CLIKIN_12              (3 << 23)
-#define MX_APLLS_CLIKIN_13              (2 << 23)
-#define MX_APLLS_CLIKIN_19_2            (0 << 23)
-
-/*
- * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #2   (ratio1) baseport-target
- * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
- */
-#define M5A_DPLL_MULT_12                (133 << 12)
-#define M5A_DPLL_DIV_12                 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13                (266 << 12)
-#define M5A_DPLL_DIV_13                 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19                (180 << 12)
-#define M5A_DPLL_DIV_19                 (12 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
-#define M5B_DPLL_MULT_12                (50 << 12)
-#define M5B_DPLL_DIV_12                 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5B_DPLL_MULT_13                (200 << 12)
-#define M5B_DPLL_DIV_13                 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5B_DPLL_MULT_19                (125 << 12)
-#define M5B_DPLL_DIV_19                 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/*
- * #4   (ratio2)
- * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
- */
-#define M3_DPLL_MULT_12                 (55 << 12)
-#define M3_DPLL_DIV_12                  (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13                 (330 << 12)
-#define M3_DPLL_DIV_13                  (12 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19                 (275 << 12)
-#define M3_DPLL_DIV_19                  (15 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/* boot (boot) */
-#define MB_DPLL_MULT                    (1 << 12)
-#define MB_DPLL_DIV                     (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_12
-
-#define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_13
-
-#define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_19
-
-/*
- * 2430 - chassis (sedna)
- * 165 (ratio1) same as above #2
- * 150 (ratio1)
- * 133 (ratio2) same as above #4
- * 110 (ratio2) same as above #3
- * 104 (ratio2)
- * boot (boot)
- */
-
-/*
- * 2420 Equivalent - mode registers
- * PRCM II , target DPLL = 2*300MHz = 600MHz
- */
-#define MII_DPLL_MULT_12                (50 << 12)
-#define MII_DPLL_DIV_12                 (1 << 8)
-#define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MII_DPLL_MULT_13                (300 << 12)
-#define MII_DPLL_DIV_13                 (12 << 8)
-#define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM III target DPLL = 2*266 = 532MHz*/
-#define MIII_DPLL_MULT_12               (133 << 12)
-#define MIII_DPLL_DIV_12                (5 << 8)
-#define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MIII_DPLL_MULT_13               (266 << 12)
-#define MIII_DPLL_DIV_13                (12 << 8)
-#define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM VII (boot bypass) */
-#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
-#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
-
-/* High and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
-
-/*
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define V24XX_SDRC_RFR_CTRL_133MHz      (0x0003de00 | 1)
-#define V24XX_SDRC_RFR_CTRL_100MHz      (0x0002da01 | 1)
-#define V24XX_SDRC_RFR_CTRL_110MHz      (0x0002da01 | 1) /* Need to calc */
-#define V24XX_SDRC_RFR_CTRL_BYPASS      (0x00005000 | 1) /* Need to calc */
-
-/* MPU speed defines */
-#define S12M    12000000
-#define S13M    13000000
-#define S19M    19200000
-#define S26M    26000000
-#define S100M   100000000
-#define S133M   133000000
-#define S150M   150000000
-#define S165M   165000000
-#define S200M   200000000
-#define S266M   266000000
-#define S300M   300000000
-#define S330M   330000000
-#define S400M   400000000
-#define S532M   532000000
-#define S600M   600000000
-#define S660M   660000000
-
-/*-------------------------------------------------------------------------
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on H4 boards and 2430-SDPs variants available.
- * There are quite a few more rates combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose the
- * fastest one. If a 'fast' value is defined, then automatically, the /2
- * one should be included as it can be used.    Generally having more that
- * one fast set does not make sense, as static timings need to be changed
- * to change the set.    The exception is the bypass setting which is
- * availble for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
-static struct prcm_config rate_table[] = {
-        /* PRCM II - FAST */
-        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - FAST */
-        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM II - SLOW */
-        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - SLOW */
-        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM #3 - ratio2 (ES2) - FAST */
-        {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_110MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - FAST */
-        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - FAST */
-        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM #3 - ratio2 (ES2) - SLOW */
-        {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_110MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - SLOW */
-        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - SLOW*/
-        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                V24XX_SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
-
-/*-------------------------------------------------------------------------
- * 24xx clock tree.
- *
- * NOTE:In many cases here we are assigning a 'default' parent. In many
- *      cases the parent is selectable. The get/set parent calls will also
- *      switch sources.
- *
- *      Many some clocks say always_enabled, but they can be auto idled for
- *      power savings. They will always be available upon clock request.
- *
- *      Several sources are given initial rates which may be wrong, this will
- *      be fixed up in the init func.
- *
- *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most periferals have dependencies on multiple clock
- *      domains. Many get their interface clocks from the L4 domain, but get
- *      functional clocks from fixed sources or other core domain derived
- *      clocks.
- *-------------------------------------------------------------------------*/
-
-/* Base external input clocks */
-static struct clk func_32k_ck = {
-        .name           = "func_32k_ck",
-        .rate           = 32000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED,
-};
-
-/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
-static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
-        .name           = "osc_ck",
-        .rate           = 26000000,             /* fixed up in clock init */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-};
-
-/* With out modem likely 12MHz, with modem likely 13MHz */
-static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
-        .name           = "sys_ck",             /* ~ ref_clk also */
-        .parent         = &osc_ck,
-        .rate           = 13000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-        .rate_offset    = 6, /* sysclkdiv 1 or 2, already handled or no boot */
-        .recalc         = &omap2_sys_clk_recalc,
-};
-
-static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
-        .name           = "alt_ck",
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-};
-
-/*
- * Analog domain root source clocks
- */
-
-/* dpll_ck, is broken out in to special cases through clksel */
-static struct clk dpll_ck = {
-        .name           = "dpll_ck",
-        .parent         = &sys_ck,              /* Can be func_32k also */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk apll96_ck = {
-        .name           = "apll96_ck",
-        .parent         = &sys_ck,
-        .rate           = 96000000,
-        .flags          = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0x2,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk apll54_ck = {
-        .name           = "apll54_ck",
-        .parent         = &sys_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0x6,
-        .recalc         = &omap2_propagate_rate,
-};
+int omap2_clk_enable(struct clk *clk);
+void omap2_clk_disable(struct clk *clk);
+long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
+int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
+int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
 
-/*
- * PRCM digital base sources
- */
-static struct clk func_54m_ck = {
-        .name           = "func_54m_ck",
-        .parent         = &apll54_ck,   /* can also be alt_clk */
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
-        .src_offset     = 5,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk core_ck = {
-        .name           = "core_ck",
-        .parent         = &dpll_ck,             /* can also be 32k */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                ALWAYS_ENABLED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk sleep_ck = {          /* sys_clk or 32k */
-        .name           = "sleep_ck",
-        .parent         = &func_32k_ck,
-        .rate           = 32000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_96m_ck = {
-        .name           = "func_96m_ck",
-        .parent         = &apll96_ck,
-        .rate           = 96000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_48m_ck = {
-        .name           = "func_48m_ck",
-        .parent         = &apll96_ck,    /* 96M or Alt */
-        .rate           = 48000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
-        .src_offset     = 3,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-        .recalc         = &omap2_propagate_rate,
-};
-
-static struct clk func_12m_ck = {
-        .name           = "func_12m_ck",
-        .parent         = &func_48m_ck,
-        .rate           = 12000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .recalc         = &omap2_propagate_rate,
-        .enable_reg     = (void __iomem *)&CM_CLKEN_PLL,
-        .enable_bit     = 0xff,
-};
-
-/* Secure timer, only available in secure mode */
-static struct clk wdt1_osc_ck = {
-        .name           = "ck_wdt1_osc",
-        .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sys_clkout = {
-        .name           = "sys_clkout",
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
-        .src_offset     = 0,
-        .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
-        .enable_bit     = 7,
-        .rate_offset    = 3,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* In 2430, new in 2420 ES2 */
-static struct clk sys_clkout2 = {
-        .name           = "sys_clkout2",
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
-        .src_offset     = 8,
-        .enable_reg     = (void __iomem *)&PRCM_CLKOUT_CTRL,
-        .enable_bit     = 15,
-        .rate_offset    = 11,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk emul_ck = {
-        .name           = "emul_ck",
-        .parent         = &func_54m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&PRCM_CLKEMUL_CTRL,
-        .enable_bit     = 0,
-        .recalc         = &omap2_propagate_rate,
-
-};
-
-/*
- * MPU clock domain
- *      Clocks:
- *              MPU_FCLK, MPU_ICLK
- *              INT_M_FCLK, INT_M_I_CLK
- *
- * - Individual clocks are hardware managed.
- * - Base divider comes from: CM_CLKSEL_MPU
- *
- */
-static struct clk mpu_ck = {    /* Control cpu */
-        .name           = "mpu_ck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
-                                ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
-                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
-        .rate_offset    = 0,    /* bits 0-4 */
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
- * Clocks:
- *      2430: IVA2.1_FCLK, IVA2.1_ICLK
- *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
- */
-static struct clk iva2_1_fck = {
-        .name           = "iva2_1_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | RATE_PROPAGATES |
-                                CONFIG_PARTICIPANT,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk iva2_1_ick = {
-        .name           = "iva2_1_ick",
-        .parent         = &iva2_1_fck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset    = 5,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * Won't be too specific here. The core clock comes into this block
- * it is divided then tee'ed. One branch goes directly to xyz enable
- * controls. The other branch gets further divided by 2 then possibly
- * routed into a synchronizer and out of clocks abc.
- */
-static struct clk dsp_fck = {
-        .name           = "dsp_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
-                        DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dsp_ick = {
-        .name           = "dsp_ick",     /* apparently ipi and isp */
-        .parent         = &dsp_fck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset = 5,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_DSP,
-        .enable_bit     = 1,            /* for ipi */
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk iva1_ifck = {
-        .name           = "iva1_ifck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
-                        CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
-        .rate_offset= 8,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 10,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* IVA1 mpu/int/i/f clocks are /2 of parent */
-static struct clk iva1_mpu_int_ifck = {
-        .name           = "iva1_mpu_int_ifck",
-        .parent         = &iva1_ifck,
-        .flags          = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_DSP,
-        .enable_bit     = 8,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * L3 clock domain
- * L3 clocks are used for both interface and functional clocks to
- * multiple entities. Some of these clocks are completely managed
- * by hardware, and some others allow software control. Hardware
- * managed ones general are based on directly CLK_REQ signals and
- * various auto idle settings. The functional spec sets many of these
- * as 'tie-high' for their enables.
- *
- * I-CLOCKS:
- *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
- *      CAM, HS-USB.
- * F-CLOCK
- *      SSI.
- *
- * GPMC memories and SDRC have timing and clock sensitive registers which
- * may very well need notification when the clock changes. Currently for low
- * operating points, these are taken care of in sleep.S.
- */
-static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
-        .name           = "core_l3_ck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT |
-                                RATE_PROPAGATES,
-        .rate_offset    = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk usb_l4_ick = {        /* FS-USB interface clock */
-        .name           = "usb_l4_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
-                                CONFIG_PARTICIPANT,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 0,
-        .rate_offset = 25,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * SSI is in L3 management domain, its direct parent is core not l3,
- * many core power domain entities are grouped into the L3 clock
- * domain.
- * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
- *
- * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
- */
-static struct clk ssi_ssr_sst_fck = {
-        .name           = "ssi_fck",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,     /* bit 1 */
-        .enable_bit     = 1,
-        .rate_offset = 20,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * GFX clock domain
- *      Clocks:
- * GFX_FCLK, GFX_ICLK
- * GFX_CG1(2d), GFX_CG2(3d)
- *
- * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
- * The 2d and 3d clocks run at a hardware determined
- * divided value of fclk.
- *
- */
-static struct clk gfx_3d_fck = {
-        .name           = "gfx_3d_fck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_GFX_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
-        .enable_bit     = 2,
-        .rate_offset= 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_2d_fck = {
-        .name           = "gfx_2d_fck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_GFX_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_GFX,
-        .enable_bit     = 1,
-        .rate_offset= 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_ick = {
-        .name           = "gfx_ick",            /* From l3 */
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_GFX,       /* bit 0 */
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * Modem clock domain (2430)
- *      CLOCKS:
- *              MDM_OSC_CLK
- *              MDM_ICLK
- */
-static struct clk mdm_ick = {           /* used both as a ick and fck */
-        .name           = "mdm_ick",
-        .parent         = &core_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
-                                DELAYED_APP | CONFIG_PARTICIPANT,
-        .rate_offset    = 0,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_MDM,
-        .enable_bit     = 0,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mdm_osc_ck = {
-        .name           = "mdm_osc_ck",
-        .rate           = 26000000,
-        .parent         = &osc_ck,
-        .flags          = CLOCK_IN_OMAP243X | RATE_FIXED,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_MDM,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * L4 clock management domain
- *
- * This domain contains lots of interface clocks from the L4 interface, some
- * functional clocks.   Fixed APLL functional source clocks are managed in
- * this domain.
- */
-static struct clk l4_ck = {             /* used both as an ick and fck */
-        .name           = "l4_ck",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
-                                DELAYED_APP | RATE_PROPAGATES,
-        .rate_offset    = 5,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk ssi_l4_ick = {
-        .name           = "ssi_l4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,     /* bit 1 */
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-/*
- * DSS clock domain
- * CLOCKs:
- * DSS_L4_ICLK, DSS_L3_ICLK,
- * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
- *
- * DSS is both initiator and target.
- */
-static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
-        .name           = "dss_ick",
-        .parent         = &l4_ck,       /* really both l3 and l4 */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk dss1_fck = {
-        .name           = "dss1_fck",
-        .parent         = &core_ck,             /* Core or sys */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 0,
-        .rate_offset    = 8,
-        .src_offset     = 8,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk dss2_fck = {          /* Alt clk used in power management */
-        .name           = "dss2_fck",
-        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
-                                DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 1,
-        .src_offset     = 13,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk dss_54m_fck = {       /* Alt clk used in power management */
-        .name           = "dss_54m_fck",        /* 54m tv clk */
-        .parent         = &func_54m_ck,
-        .rate           = 54000000,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                RATE_FIXED | RATE_PROPAGATES,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_propagate_rate,
-};
-
-/*
- * CORE power domain ICLK & FCLK defines.
- * Many of the these can have more than one possible parent. Entries
- * here will likely have an L4 interface parent, and may have multiple
- * functional clock parents.
- */
-static struct clk gpt1_ick = {
-        .name           = "gpt1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,      /* Bit0 */
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_WKUP_SEL1,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,      /* Bit0 */
-        .enable_bit     = 0,
-        .src_offset     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt2_ick = {
-        .name           = "gpt2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit4 */
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 4,
-        .src_offset     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt3_ick = {
-        .name           = "gpt3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit5 */
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 5,
-        .src_offset     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt4_ick = {
-        .name           = "gpt4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,     /* Bit6 */
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 6,
-        .src_offset     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt5_ick = {
-        .name           = "gpt5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* Bit7 */
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 7,
-        .src_offset     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt6_ick = {
-        .name           = "gpt6_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 8,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit8 */
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 8,
-        .src_offset     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt7_ick = {
-        .name           = "gpt7_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit9 */
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 9,
-        .src_offset     = 12,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt8_ick = {
-        .name           = "gpt8_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit10 */
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 10,
-        .src_offset     = 14,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt9_ick = {
-        .name           = "gpt9_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 11,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 11,
-        .src_offset     = 16,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt10_ick = {
-        .name           = "gpt10_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 12,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 12,
-        .src_offset     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt11_ick = {
-        .name           = "gpt11_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 13,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 13,
-        .src_offset     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt12_ick = {
-        .name           = "gpt12_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit14 */
-        .enable_bit     = 14,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpt12_fck = {
-        .name           = "gpt12_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                        CM_CORE_SEL2,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 14,
-        .src_offset     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp1_ick = {
-        .name           = "mcbsp1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 15,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,      /* bit16 */
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 15,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp2_ick = {
-        .name           = "mcbsp2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 16,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_bit     = 16,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp3_ick = {
-        .name           = "mcbsp3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp3_fck = {
-        .name           = "mcbsp3_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp4_ick = {
-        .name           = "mcbsp4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp4_fck = {
-        .name           = "mcbsp4_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp5_ick = {
-        .name           = "mcbsp5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcbsp5_fck = {
-        .name           = "mcbsp5_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi1_ick = {
-        .name           = "mcspi_ick",
-        .id             = 1,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi1_fck = {
-        .name           = "mcspi_fck",
-        .id             = 1,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi2_ick = {
-        .name           = "mcspi_ick",
-        .id             = 2,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi2_fck = {
-        .name           = "mcspi_fck",
-        .id             = 2,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 18,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi3_ick = {
-        .name           = "mcspi_ick",
-        .id             = 3,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mcspi3_fck = {
-        .name           = "mcspi_fck",
-        .id             = 3,
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 9,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart1_ick = {
-        .name           = "uart1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 21,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 21,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart2_ick = {
-        .name           = "uart2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 22,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart3_ick = {
-        .name           = "uart3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpios_ick = {
-        .name           = "gpios_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk gpios_fck = {
-        .name           = "gpios_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mpu_wdt_ick = {
-        .name           = "mpu_wdt_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mpu_wdt_fck = {
-        .name           = "mpu_wdt_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN_WKUP,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sync_32k_ick = {
-        .name           = "sync_32k_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk wdt1_ick = {
-        .name           = "wdt1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk omapctrl_ick = {
-        .name           = "omapctrl_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 5,
-        .recalc         = &omap2_followparent_recalc,
-};
-static struct clk icr_ick = {
-        .name           = "icr_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN_WKUP,
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk cam_ick = {
-        .name           = "cam_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 31,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk cam_fck = {
-        .name           = "cam_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 31,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mailboxes_ick = {
-        .name           = "mailboxes_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 30,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt4_ick = {
-        .name           = "wdt4_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 29,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt4_fck = {
-        .name           = "wdt4_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 29,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt3_ick = {
-        .name           = "wdt3_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 28,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 28,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mspro_ick = {
-        .name           = "mspro_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 27,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mspro_fck = {
-        .name           = "mspro_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 27,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmc_ick = {
-        .name           = "mmc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 26,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmc_fck = {
-        .name           = "mmc_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 26,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk fac_ick = {
-        .name           = "fac_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 25,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk fac_fck = {
-        .name           = "fac_fck",
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 25,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk eac_ick = {
-        .name           = "eac_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 24,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk eac_fck = {
-        .name           = "eac_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 24,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk hdq_ick = {
-        .name           = "hdq_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 23,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk hdq_fck = {
-        .name           = "hdq_fck",
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 23,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c2_ick = {
-        .name           = "i2c_ick",
-        .id             = 2,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c2_fck = {
-        .name           = "i2c_fck",
-        .id             = 2,
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2chs2_fck = {
-        .name           = "i2chs2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 20,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c1_ick = {
-        .name           = "i2c_ick",
-        .id             = 1,
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2c1_fck = {
-        .name           = "i2c_fck",
-        .id             = 1,
-        .parent         = &func_12m_ck,
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk i2chs1_fck = {
-        .name           = "i2chs1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 19,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk vlynq_ick = {
-        .name           = "vlynq_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN1_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk vlynq_fck = {
-        .name           = "vlynq_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN1_CORE,
-        .enable_bit     = 3,
-        .src_offset     = 15,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sdrc_ick = {
-        .name           = "sdrc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN3_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk des_ick = {
-        .name           = "des_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk sha_ick = {
-        .name           = "sha_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 1,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 2,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk aes_ick = {
-        .name           = "aes_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 3,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk pka_ick = {
-        .name           = "pka_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN4_CORE,
-        .enable_bit     = 4,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk usb_fck = {
-        .name           = "usb_fck",
-        .parent         = &func_48m_ck,
-        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 0,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk usbhs_ick = {
-        .name           = "usbhs_ick",
-        .parent         = &core_l3_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 6,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs1_ick = {
-        .name           = "mmchs1_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs1_fck = {
-        .name           = "mmchs1_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 7,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs2_ick = {
-        .name           = "mmchs2_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
-
-static struct clk mmchs2_fck = {
-        .name           = "mmchs2_fck",
-        .parent         = &func_96m_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 8,
-        .recalc         = &omap2_followparent_recalc,
-};
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+void omap2_clk_disable_unused(struct clk *clk);
+#else
+#define omap2_clk_disable_unused        NULL
+#endif
 
-static struct clk gpio5_ick = {
-        .name           = "gpio5_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
+void omap2_clksel_recalc(struct clk *clk);
+void omap2_init_clksel_parent(struct clk *clk);
+u32 omap2_clksel_get_divisor(struct clk *clk);
+u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
+                                u32 *new_div);
+u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
+u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
+void omap2_fixed_divisor_recalc(struct clk *clk);
+long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
+int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
+u32 omap2_get_dpll_rate(struct clk *clk);
+int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 
-static struct clk gpio5_fck = {
-        .name           = "gpio5_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 10,
-        .recalc         = &omap2_followparent_recalc,
-};
+extern u8 cpu_mask;
 
-static struct clk mdm_intc_ick = {
-        .name           = "mdm_intc_ick",
-        .parent         = &l4_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_ICLKEN2_CORE,
-        .enable_bit     = 11,
-        .recalc         = &omap2_followparent_recalc,
+/* clksel_rate data common to 24xx/343x */
+static const struct clksel_rate gpt_32k_rates[] = {
+         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
 };
 
-static struct clk mmchsdb1_fck = {
-        .name           = "mmchsdb1_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 16,
-        .recalc         = &omap2_followparent_recalc,
+static const struct clksel_rate gpt_sys_rates[] = {
+         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
 };
 
-static struct clk mmchsdb2_fck = {
-        .name           = "mmchsdb2_fck",
-        .parent         = &func_32k_ck,
-        .flags          = CLOCK_IN_OMAP243X,
-        .enable_reg     = (void __iomem *)&CM_FCLKEN2_CORE,
-        .enable_bit     = 17,
-        .recalc         = &omap2_followparent_recalc,
+static const struct clksel_rate gfx_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 0 }
 };
 
-/*
- * This clock is a composite clock which does entire set changes then
- * forces a rebalance. It keys on the MPU speed, but it really could
- * be any key speed part of a set in the rate table.
- *
- * to really change a set, you need memory table sets which get changed
- * in sram, pre-notifiers & post notifiers, changing the top set, without
- * having low level display recalc's won't work... this is why dpm notifiers
- * work, isr's off, walk a list of clocks already _off_ and not messing with
- * the bus.
- *
- * This clock should have no parent. It embodies the entire upper level
- * active set. A parent will mess up some of the init also.
- */
-static struct clk virt_prcm_set = {
-        .name           = "virt_prcm_set",
-        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
-                                VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
-        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
-        .recalc         = &omap2_mpu_recalc,    /* sets are keyed on mpu rate */
-        .set_rate       = &omap2_select_table_rate,
-        .round_rate     = &omap2_round_to_table_rate,
-};
-
-static struct clk *onchip_clks[] = {
-        /* external root sources */
-        &func_32k_ck,
-        &osc_ck,
-        &sys_ck,
-        &alt_ck,
-        /* internal analog sources */
-        &dpll_ck,
-        &apll96_ck,
-        &apll54_ck,
-        /* internal prcm root sources */
-        &func_54m_ck,
-        &core_ck,
-        &sleep_ck,
-        &func_96m_ck,
-        &func_48m_ck,
-        &func_12m_ck,
-        &wdt1_osc_ck,
-        &sys_clkout,
-        &sys_clkout2,
-        &emul_ck,
-        /* mpu domain clocks */
-        &mpu_ck,
-        /* dsp domain clocks */
-        &iva2_1_fck,            /* 2430 */
-        &iva2_1_ick,
-        &dsp_ick,               /* 2420 */
-        &dsp_fck,
-        &iva1_ifck,
-        &iva1_mpu_int_ifck,
-        /* GFX domain clocks */
-        &gfx_3d_fck,
-        &gfx_2d_fck,
-        &gfx_ick,
-        /* Modem domain clocks */
-        &mdm_ick,
-        &mdm_osc_ck,
-        /* DSS domain clocks */
-        &dss_ick,
-        &dss1_fck,
-        &dss2_fck,
-        &dss_54m_fck,
-        /* L3 domain clocks */
-        &core_l3_ck,
-        &ssi_ssr_sst_fck,
-        &usb_l4_ick,
-        /* L4 domain clocks */
-        &l4_ck,                 /* used as both core_l4 and wu_l4 */
-        &ssi_l4_ick,
-        /* virtual meta-group clock */
-        &virt_prcm_set,
-        /* general l4 interface ck, multi-parent functional clk */
-        &gpt1_ick,
-        &gpt1_fck,
-        &gpt2_ick,
-        &gpt2_fck,
-        &gpt3_ick,
-        &gpt3_fck,
-        &gpt4_ick,
-        &gpt4_fck,
-        &gpt5_ick,
-        &gpt5_fck,
-        &gpt6_ick,
-        &gpt6_fck,
-        &gpt7_ick,
-        &gpt7_fck,
-        &gpt8_ick,
-        &gpt8_fck,
-        &gpt9_ick,
-        &gpt9_fck,
-        &gpt10_ick,
-        &gpt10_fck,
-        &gpt11_ick,
-        &gpt11_fck,
-        &gpt12_ick,
-        &gpt12_fck,
-        &mcbsp1_ick,
-        &mcbsp1_fck,
-        &mcbsp2_ick,
-        &mcbsp2_fck,
-        &mcbsp3_ick,
-        &mcbsp3_fck,
-        &mcbsp4_ick,
-        &mcbsp4_fck,
-        &mcbsp5_ick,
-        &mcbsp5_fck,
-        &mcspi1_ick,
-        &mcspi1_fck,
-        &mcspi2_ick,
-        &mcspi2_fck,
-        &mcspi3_ick,
-        &mcspi3_fck,
-        &uart1_ick,
-        &uart1_fck,
-        &uart2_ick,
-        &uart2_fck,
-        &uart3_ick,
-        &uart3_fck,
-        &gpios_ick,
-        &gpios_fck,
-        &mpu_wdt_ick,
-        &mpu_wdt_fck,
-        &sync_32k_ick,
-        &wdt1_ick,
-        &omapctrl_ick,
-        &icr_ick,
-        &cam_fck,
-        &cam_ick,
-        &mailboxes_ick,
-        &wdt4_ick,
-        &wdt4_fck,
-        &wdt3_ick,
-        &wdt3_fck,
-        &mspro_ick,
-        &mspro_fck,
-        &mmc_ick,
-        &mmc_fck,
-        &fac_ick,
-        &fac_fck,
-        &eac_ick,
-        &eac_fck,
-        &hdq_ick,
-        &hdq_fck,
-        &i2c1_ick,
-        &i2c1_fck,
-        &i2chs1_fck,
-        &i2c2_ick,
-        &i2c2_fck,
-        &i2chs2_fck,
-        &vlynq_ick,
-        &vlynq_fck,
-        &sdrc_ick,
-        &des_ick,
-        &sha_ick,
-        &rng_ick,
-        &aes_ick,
-        &pka_ick,
-        &usb_fck,
-        &usbhs_ick,
-        &mmchs1_ick,
-        &mmchs1_fck,
-        &mmchs2_ick,
-        &mmchs2_fck,
-        &gpio5_ick,
-        &gpio5_fck,
-        &mdm_intc_ick,
-        &mmchsdb1_fck,
-        &mmchsdb2_fck,
-};
 
 #endif
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
new file mode 100644
index 000000000000..ece32d8acba4
--- /dev/null
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -0,0 +1,539 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock.c
+ *
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ *  Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+#include <asm/div64.h>
+#include <asm/bitops.h>
+
+#include "memory.h"
+#include "clock.h"
+#include "clock24xx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED                 0
+#define EN_APLL_LOCKED                  3
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ             0
+#define APLLS_CLKIN_13MHZ               2
+#define APLLS_CLKIN_12MHZ               3
+
+/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
+
+static struct prcm_config *curr_prcm_set;
+static struct clk *vclk;
+static struct clk *sclk;
+
+/*-------------------------------------------------------------------------
+ * Omap24xx specific clock functions
+ *-------------------------------------------------------------------------*/
+
+/* This actually returns the rate of core_ck, not dpll_ck. */
+static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
+{
+        long long dpll_clk;
+        u8 amult;
+
+        dpll_clk = omap2_get_dpll_rate(tclk);
+
+        amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        amult &= OMAP24XX_CORE_CLK_SRC_MASK;
+        dpll_clk *= amult;
+
+        return dpll_clk;
+}
+
+static int omap2_enable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
+                      OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        return 0;
+}
+
+static void omap2_disable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+
+        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
+                      OMAP24XX_PRCM_CLKSRC_CTRL);
+}
+
+#ifdef OLD_CK
+/* Recalculate SYST_CLK */
+static void omap2_sys_clk_recalc(struct clk * clk)
+{
+        u32 div = PRCM_CLKSRC_CTRL;
+        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
+        div >>= clk->rate_offset;
+        clk->rate = (clk->parent->rate / div);
+        propagate_rate(clk);
+}
+#endif  /* OLD_CK */
+
+/* Enable an APLL if off */
+static int omap2_clk_fixed_enable(struct clk *clk)
+{
+        u32 cval, apll_mask;
+
+        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+        if ((cval & apll_mask) == apll_mask)
+                return 0;   /* apll already enabled */
+
+        cval &= ~apll_mask;
+        cval |= apll_mask;
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+
+        if (clk == &apll96_ck)
+                cval = OMAP24XX_ST_96M_APLL;
+        else if (clk == &apll54_ck)
+                cval = OMAP24XX_ST_54M_APLL;
+
+        omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+                            clk->name);
+
+        /*
+         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+         * fails?
+         */
+        return 0;
+}
+
+/* Stop APLL */
+static void omap2_clk_fixed_disable(struct clk *clk)
+{
+        u32 cval;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+}
+
+/*
+ * Uses the current prcm set to tell if a rate is valid.
+ * You can go slower, but not faster within a given rate set.
+ */
+static u32 omap2_dpll_round_rate(unsigned long target_rate)
+{
+        u32 high, low, core_clk_src;
+
+        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
+                high = curr_prcm_set->dpll_speed * 2;
+                low = curr_prcm_set->dpll_speed;
+        } else {                                /* DPLL clockout x 2 */
+                high = curr_prcm_set->dpll_speed;
+                low = curr_prcm_set->dpll_speed / 2;
+        }
+
+#ifdef DOWN_VARIABLE_DPLL
+        if (target_rate > high)
+                return high;
+        else
+                return target_rate;
+#else
+        if (target_rate > low)
+                return high;
+        else
+                return low;
+#endif
+
+}
+
+static void omap2_dpll_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_dpll_rate_24xx(clk);
+
+        propagate_rate(clk);
+}
+
+static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, low, mult, div, valid_rate, done_rate;
+        u32 bypass = 0;
+        struct prcm_config tmpset;
+        const struct dpll_data *dd;
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        local_irq_save(flags);
+        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if ((rate == (cur_rate / 2)) && (mult == 2)) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (rate != cur_rate) {
+                valid_rate = omap2_dpll_round_rate(rate);
+                if (valid_rate != rate)
+                        goto dpll_exit;
+
+                if (mult == 1)
+                        low = curr_prcm_set->dpll_speed;
+                else
+                        low = curr_prcm_set->dpll_speed / 2;
+
+                dd = clk->dpll_data;
+                if (!dd)
+                        goto dpll_exit;
+
+                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
+                                           dd->div1_mask);
+                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
+                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
+                if (rate > low) {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
+                        mult = ((rate / 2) / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                } else {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
+                        mult = (rate / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL;
+                }
+                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
+                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
+
+                /* Worst case */
+                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
+
+                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
+                        bypass = 1;
+
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
+
+                /* Force dll lock mode */
+                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
+                               bypass);
+
+                /* Errata: ret dll entry state */
+                omap2_init_memory_params(omap2_dll_force_needed());
+                omap2_reprogram_sdrc(done_rate, 0);
+        }
+        omap2_dpll_recalc(&dpll_ck);
+        ret = 0;
+
+dpll_exit:
+        local_irq_restore(flags);
+        return(ret);
+}
+
+/**
+ * omap2_table_mpu_recalc - just return the MPU speed
+ * @clk: virt_prcm_set struct clk
+ *
+ * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
+ */
+static void omap2_table_mpu_recalc(struct clk *clk)
+{
+        clk->rate = curr_prcm_set->mpu_speed;
+}
+
+/*
+ * Look for a rate equal or less than the target rate given a configuration set.
+ *
+ * What's not entirely clear is "which" field represents the key field.
+ * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
+ * just uses the ARM rates.
+ */
+static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+        struct prcm_config *ptr;
+        long highest_rate;
+
+        if (clk != &virt_prcm_set)
+                return -EINVAL;
+
+        highest_rate = -EINVAL;
+
+        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+                if (ptr->xtal_speed != sys_ck.rate)
+                        continue;
+
+                highest_rate = ptr->mpu_speed;
+
+                /* Can check only after xtal frequency check */
+                if (ptr->mpu_speed <= rate)
+                        break;
+        }
+        return highest_rate;
+}
+
+/* Sets basic clocks based on the specified rate */
+static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, done_rate, bypass = 0, tmp;
+        struct prcm_config *prcm;
+        unsigned long found_speed = 0;
+        unsigned long flags;
+
+        if (clk != &virt_prcm_set)
+                return -EINVAL;
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+
+                if (prcm->mpu_speed <= rate) {
+                        found_speed = prcm->mpu_speed;
+                        break;
+                }
+        }
+
+        if (!found_speed) {
+                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
+                       rate / 1000000);
+                return -EINVAL;
+        }
+
+        curr_prcm_set = prcm;
+        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
+
+        if (prcm->dpll_speed == cur_rate / 2) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+        } else if (prcm->dpll_speed == cur_rate * 2) {
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (prcm->dpll_speed != cur_rate) {
+                local_irq_save(flags);
+
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        bypass = 1;
+
+                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+                    CORE_CLK_SRC_DPLL_X2)
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                else
+                        done_rate = CORE_CLK_SRC_DPLL;
+
+                /* MPU divider */
+                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+
+                /* dsp + iva1 div(2420), iva2.1(2430) */
+                cm_write_mod_reg(prcm->cm_clksel_dsp,
+                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
+
+                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+
+                /* Major subsystem dividers */
+                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
+                if (cpu_is_omap2430())
+                        cm_write_mod_reg(prcm->cm_clksel_mdm,
+                                         OMAP2430_MDM_MOD, CM_CLKSEL);
+
+                /* x2 to enter init_mem */
+                omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+
+                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
+                               bypass);
+
+                omap2_init_memory_params(omap2_dll_force_needed());
+                omap2_reprogram_sdrc(done_rate, 0);
+
+                local_irq_restore(flags);
+        }
+        omap2_dpll_recalc(&dpll_ck);
+
+        return 0;
+}
+
+static struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+};
+
+static u32 omap2_get_apll_clkin(void)
+{
+        u32 aplls, sclk = 0;
+
+        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
+
+        if (aplls == APLLS_CLKIN_19_2MHZ)
+                sclk = 19200000;
+        else if (aplls == APLLS_CLKIN_13MHZ)
+                sclk = 13000000;
+        else if (aplls == APLLS_CLKIN_12MHZ)
+                sclk = 12000000;
+
+        return sclk;
+}
+
+static u32 omap2_get_sysclkdiv(void)
+{
+        u32 div;
+
+        div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+        div &= OMAP_SYSCLKDIV_MASK;
+        div >>= OMAP_SYSCLKDIV_SHIFT;
+
+        return div;
+}
+
+static void omap2_osc_clk_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
+        propagate_rate(clk);
+}
+
+static void omap2_sys_clk_recalc(struct clk *clk)
+{
+        clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
+        propagate_rate(clk);
+}
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+        u32 rate;
+
+        if (vclk == NULL || sclk == NULL)
+                return;
+
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);
+}
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+        if (!mpurate)
+                return -EINVAL;
+
+        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+                printk(KERN_ERR "Could not find matching MPU rate\n");
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+        return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+int __init omap2_clk_init(void)
+{
+        struct prcm_config *prcm;
+        struct clk **clkp;
+        u32 clkrate;
+
+        if (cpu_is_omap242x())
+                cpu_mask = RATE_IN_242X;
+        else if (cpu_is_omap2430())
+                cpu_mask = RATE_IN_243X;
+
+        clk_init(&omap2_clk_functions);
+
+        omap2_osc_clk_recalc(&osc_ck);
+        omap2_sys_clk_recalc(&sys_ck);
+
+        for (clkp = onchip_24xx_clks;
+             clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
+             clkp++) {
+
+                if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
+                        clk_register(*clkp);
+                        continue;
+                }
+
+                if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
+                        clk_register(*clkp);
+                        continue;
+                }
+        }
+
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                         break;
+        }
+        curr_prcm_set = prcm;
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
new file mode 100644
index 000000000000..88081ed13f96
--- /dev/null
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -0,0 +1,2643 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock24xx.h
+ *
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+
+#include "clock.h"
+
+#include "prm.h"
+#include "cm.h"
+#include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
+#include "sdrc.h"
+
+static void omap2_table_mpu_recalc(struct clk *clk);
+static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
+static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
+static void omap2_sys_clk_recalc(struct clk *clk);
+static void omap2_osc_clk_recalc(struct clk *clk);
+static void omap2_sys_clk_recalc(struct clk *clk);
+static void omap2_dpll_recalc(struct clk *clk);
+static int omap2_clk_fixed_enable(struct clk *clk);
+static void omap2_clk_fixed_disable(struct clk *clk);
+static int omap2_enable_osc_ck(struct clk *clk);
+static void omap2_disable_osc_ck(struct clk *clk);
+static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
+
+/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
+ * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ */
+struct prcm_config {
+        unsigned long xtal_speed;       /* crystal rate */
+        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
+        unsigned long mpu_speed;        /* speed of MPU */
+        unsigned long cm_clksel_mpu;    /* mpu divider */
+        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
+        unsigned long cm_clksel_gfx;    /* gfx dividers */
+        unsigned long cm_clksel1_core;  /* major subsystem dividers */
+        unsigned long cm_clksel1_pll;   /* m,n */
+        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
+        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
+        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
+        unsigned char flags;
+};
+
+/*
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ */
+
+/* Core fields for cm_clksel, not ratio governed */
+#define RX_CLKSEL_DSS1                  (0x10 << 8)
+#define RX_CLKSEL_DSS2                  (0x0 << 13)
+#define RX_CLKSEL_SSI                   (0x5 << 20)
+
+/*-------------------------------------------------------------------------
+ * Voltage/DPLL ratios
+ *-------------------------------------------------------------------------*/
+
+/* 2430 Ratio's, 2430-Ratio Config 1 */
+#define R1_CLKSEL_L3                    (4 << 0)
+#define R1_CLKSEL_L4                    (2 << 5)
+#define R1_CLKSEL_USB                   (4 << 25)
+#define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        R1_CLKSEL_L4 | R1_CLKSEL_L3
+#define R1_CLKSEL_MPU                   (2 << 0)
+#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
+#define R1_CLKSEL_DSP                   (2 << 0)
+#define R1_CLKSEL_DSP_IF                (2 << 5)
+#define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
+#define R1_CLKSEL_GFX                   (2 << 0)
+#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
+#define R1_CLKSEL_MDM                   (4 << 0)
+#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
+
+/* 2430-Ratio Config 2 */
+#define R2_CLKSEL_L3                    (6 << 0)
+#define R2_CLKSEL_L4                    (2 << 5)
+#define R2_CLKSEL_USB                   (2 << 25)
+#define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        R2_CLKSEL_L4 | R2_CLKSEL_L3
+#define R2_CLKSEL_MPU                   (2 << 0)
+#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
+#define R2_CLKSEL_DSP                   (2 << 0)
+#define R2_CLKSEL_DSP_IF                (3 << 5)
+#define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
+#define R2_CLKSEL_GFX                   (2 << 0)
+#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
+#define R2_CLKSEL_MDM                   (6 << 0)
+#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
+
+/* 2430-Ratio Bootm (BYPASS) */
+#define RB_CLKSEL_L3                    (1 << 0)
+#define RB_CLKSEL_L4                    (1 << 5)
+#define RB_CLKSEL_USB                   (1 << 25)
+#define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RB_CLKSEL_L4 | RB_CLKSEL_L3
+#define RB_CLKSEL_MPU                   (1 << 0)
+#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
+#define RB_CLKSEL_DSP                   (1 << 0)
+#define RB_CLKSEL_DSP_IF                (1 << 5)
+#define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
+#define RB_CLKSEL_GFX                   (1 << 0)
+#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
+#define RB_CLKSEL_MDM                   (1 << 0)
+#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
+
+/* 2420 Ratio Equivalents */
+#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
+#define RXX_CLKSEL_SSI                  (0x8 << 20)
+
+/* 2420-PRCM III 532MHz core */
+#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
+#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
+#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
+#define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
+                                        RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
+                                        RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
+                                        RIII_CLKSEL_L3
+#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
+#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
+#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
+#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
+#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
+#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
+#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
+#define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
+                                        RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
+                                        RIII_CLKSEL_DSP
+#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
+#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
+
+/* 2420-PRCM II 600MHz core */
+#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
+#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
+#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
+#define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
+                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RII_CLKSEL_L4 | RII_CLKSEL_L3
+#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
+#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
+#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
+#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
+#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
+#define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
+#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
+#define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
+                                        RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
+                                        RII_CLKSEL_DSP
+#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
+#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
+
+/* 2420-PRCM I 660MHz core */
+#define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
+#define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
+#define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
+#define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
+                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                        RI_CLKSEL_L4 | RI_CLKSEL_L3
+#define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
+#define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
+#define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
+#define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
+#define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
+#define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
+#define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
+#define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
+                                        RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
+                                        RI_CLKSEL_DSP
+#define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
+#define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
+
+/* 2420-PRCM VII (boot) */
+#define RVII_CLKSEL_L3                  (1 << 0)
+#define RVII_CLKSEL_L4                  (1 << 5)
+#define RVII_CLKSEL_DSS1                (1 << 8)
+#define RVII_CLKSEL_DSS2                (0 << 13)
+#define RVII_CLKSEL_VLYNQ               (1 << 15)
+#define RVII_CLKSEL_SSI                 (1 << 20)
+#define RVII_CLKSEL_USB                 (1 << 25)
+
+#define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
+                                        RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
+                                        RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
+
+#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
+#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
+
+#define RVII_CLKSEL_DSP                 (1 << 0)
+#define RVII_CLKSEL_DSP_IF              (1 << 5)
+#define RVII_SYNC_DSP                   (0 << 7)
+#define RVII_CLKSEL_IVA                 (1 << 8)
+#define RVII_SYNC_IVA                   (0 << 13)
+#define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
+                                        RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
+
+#define RVII_CLKSEL_GFX                 (1 << 0)
+#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
+
+/*-------------------------------------------------------------------------
+ * 2430 Target modes: Along with each configuration the CPU has several
+ * modes which goes along with them. Modes mainly are the addition of
+ * describe DPLL combinations to go along with a ratio.
+ *-------------------------------------------------------------------------*/
+
+/* Hardware governed */
+#define MX_48M_SRC                      (0 << 3)
+#define MX_54M_SRC                      (0 << 5)
+#define MX_APLLS_CLIKIN_12              (3 << 23)
+#define MX_APLLS_CLIKIN_13              (2 << 23)
+#define MX_APLLS_CLIKIN_19_2            (0 << 23)
+
+/*
+ * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
+ * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
+ */
+#define M5A_DPLL_MULT_12                (133 << 12)
+#define M5A_DPLL_DIV_12                 (5 << 8)
+#define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M5A_DPLL_MULT_13                (61 << 12)
+#define M5A_DPLL_DIV_13                 (2 << 8)
+#define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M5A_DPLL_MULT_19                (55 << 12)
+#define M5A_DPLL_DIV_19                 (3 << 8)
+#define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
+#define M5B_DPLL_MULT_12                (50 << 12)
+#define M5B_DPLL_DIV_12                 (2 << 8)
+#define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M5B_DPLL_MULT_13                (200 << 12)
+#define M5B_DPLL_DIV_13                 (12 << 8)
+
+#define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M5B_DPLL_MULT_19                (125 << 12)
+#define M5B_DPLL_DIV_19                 (31 << 8)
+#define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+/*
+ * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
+ */
+#define M4_DPLL_MULT_12                 (133 << 12)
+#define M4_DPLL_DIV_12                  (3 << 8)
+#define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+#define M4_DPLL_MULT_13                 (399 << 12)
+#define M4_DPLL_DIV_13                  (12 << 8)
+#define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+#define M4_DPLL_MULT_19                 (145 << 12)
+#define M4_DPLL_DIV_19                  (6 << 8)
+#define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/*
+ * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
+ */
+#define M3_DPLL_MULT_12                 (55 << 12)
+#define M3_DPLL_DIV_12                  (1 << 8)
+#define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define M3_DPLL_MULT_13                 (76 << 12)
+#define M3_DPLL_DIV_13                  (2 << 8)
+#define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+#define M3_DPLL_MULT_19                 (17 << 12)
+#define M3_DPLL_DIV_19                  (0 << 8)
+#define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/*
+ * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
+ */
+#define M2_DPLL_MULT_12                 (55 << 12)
+#define M2_DPLL_DIV_12                  (1 << 8)
+#define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
+ * relock time issue */
+/* Core frequency changed from 330/165 to 329/164 MHz*/
+#define M2_DPLL_MULT_13                 (76 << 12)
+#define M2_DPLL_DIV_13                  (2 << 8)
+#define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+#define M2_DPLL_MULT_19                 (17 << 12)
+#define M2_DPLL_DIV_19                  (0 << 8)
+#define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
+                                        MX_APLLS_CLIKIN_19_2
+
+/* boot (boot) */
+#define MB_DPLL_MULT                    (1 << 12)
+#define MB_DPLL_DIV                     (0 << 8)
+#define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_12
+
+#define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_13
+
+#define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
+                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_19
+
+/*
+ * 2430 - chassis (sedna)
+ * 165 (ratio1) same as above #2
+ * 150 (ratio1)
+ * 133 (ratio2) same as above #4
+ * 110 (ratio2) same as above #3
+ * 104 (ratio2)
+ * boot (boot)
+ */
+
+/* PRCM I target DPLL = 2*330MHz = 660MHz */
+#define MI_DPLL_MULT_12                 (55 << 12)
+#define MI_DPLL_DIV_12                  (1 << 8)
+#define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
+                                        MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+
+/*
+ * 2420 Equivalent - mode registers
+ * PRCM II , target DPLL = 2*300MHz = 600MHz
+ */
+#define MII_DPLL_MULT_12                (50 << 12)
+#define MII_DPLL_DIV_12                 (1 << 8)
+#define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define MII_DPLL_MULT_13                (300 << 12)
+#define MII_DPLL_DIV_13                 (12 << 8)
+#define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
+                                        MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+/* PRCM III target DPLL = 2*266 = 532MHz*/
+#define MIII_DPLL_MULT_12               (133 << 12)
+#define MIII_DPLL_DIV_12                (5 << 8)
+#define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
+                                        MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
+                                        MX_APLLS_CLIKIN_12
+#define MIII_DPLL_MULT_13               (266 << 12)
+#define MIII_DPLL_DIV_13                (12 << 8)
+#define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
+                                        MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
+                                        MX_APLLS_CLIKIN_13
+
+/* PRCM VII (boot bypass) */
+#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
+#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
+
+/* High and low operation value */
+#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
+#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
+
+/* MPU speed defines */
+#define S12M    12000000
+#define S13M    13000000
+#define S19M    19200000
+#define S26M    26000000
+#define S100M   100000000
+#define S133M   133000000
+#define S150M   150000000
+#define S164M   164000000
+#define S165M   165000000
+#define S199M   199000000
+#define S200M   200000000
+#define S266M   266000000
+#define S300M   300000000
+#define S329M   329000000
+#define S330M   330000000
+#define S399M   399000000
+#define S400M   400000000
+#define S532M   532000000
+#define S600M   600000000
+#define S658M   658000000
+#define S660M   660000000
+#define S798M   798000000
+
+/*-------------------------------------------------------------------------
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
+ * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
+ * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * There are quite a few more rates combinations which could be defined.
+ *
+ * When multiple values are defined the start up will try and choose the
+ * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * one should be included as it can be used.    Generally having more that
+ * one fast set does not make sense, as static timings need to be changed
+ * to change the set.    The exception is the bypass setting which is
+ * availble for low power bypass.
+ *
+ * Note: This table needs to be sorted, fastest to slowest.
+ *-------------------------------------------------------------------------*/
+static struct prcm_config rate_table[] = {
+        /* PRCM I - FAST */
+        {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
+                RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - FAST */
+        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - FAST */
+        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - SLOW */
+        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - SLOW */
+        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        /* PRCM #4 - ratio2 (ES2.1) - FAST */
+        {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - FAST */
+        {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - FAST */
+        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - FAST */
+        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM #4 - ratio1 (ES2.1) - SLOW */
+        {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - SLOW */
+        {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - SLOW */
+        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - SLOW*/
+        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
+
+/*-------------------------------------------------------------------------
+ * 24xx clock tree.
+ *
+ * NOTE:In many cases here we are assigning a 'default' parent. In many
+ *      cases the parent is selectable. The get/set parent calls will also
+ *      switch sources.
+ *
+ *      Many some clocks say always_enabled, but they can be auto idled for
+ *      power savings. They will always be available upon clock request.
+ *
+ *      Several sources are given initial rates which may be wrong, this will
+ *      be fixed up in the init func.
+ *
+ *      Things are broadly separated below by clock domains. It is
+ *      noteworthy that most periferals have dependencies on multiple clock
+ *      domains. Many get their interface clocks from the L4 domain, but get
+ *      functional clocks from fixed sources or other core domain derived
+ *      clocks.
+ *-------------------------------------------------------------------------*/
+
+/* Base external input clocks */
+static struct clk func_32k_ck = {
+        .name           = "func_32k_ck",
+        .rate           = 32000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &propagate_rate,
+};
+
+/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
+static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
+        .name           = "osc_ck",
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES,
+        .enable         = &omap2_enable_osc_ck,
+        .disable        = &omap2_disable_osc_ck,
+        .recalc         = &omap2_osc_clk_recalc,
+};
+
+/* With out modem likely 12MHz, with modem likely 13MHz */
+static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
+        .name           = "sys_ck",             /* ~ ref_clk also */
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &omap2_sys_clk_recalc,
+};
+
+static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
+        .name           = "alt_ck",
+        .rate           = 54000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &propagate_rate,
+};
+
+/*
+ * Analog domain root source clocks
+ */
+
+/* dpll_ck, is broken out in to special cases through clksel */
+/* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
+ * deal with this
+ */
+
+static const struct dpll_data dpll_dd = {
+        .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
+        .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
+};
+
+static struct clk dpll_ck = {
+        .name           = "dpll_ck",
+        .parent         = &sys_ck,              /* Can be func_32k also */
+        .dpll_data      = &dpll_dd,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_dpll_recalc,
+        .set_rate       = &omap2_reprogram_dpll,
+};
+
+static struct clk apll96_ck = {
+        .name           = "apll96_ck",
+        .parent         = &sys_ck,
+        .rate           = 96000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+        .enable         = &omap2_clk_fixed_enable,
+        .disable        = &omap2_clk_fixed_disable,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk apll54_ck = {
+        .name           = "apll54_ck",
+        .parent         = &sys_ck,
+        .rate           = 54000000,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+        .enable         = &omap2_clk_fixed_enable,
+        .disable        = &omap2_clk_fixed_disable,
+        .recalc         = &propagate_rate,
+};
+
+/*
+ * PRCM digital base sources
+ */
+
+/* func_54m_ck */
+
+static const struct clksel_rate func_54m_apll54_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_54m_clksel[] = {
+        { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
+        { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
+        { .parent = NULL },
+};
+
+static struct clk func_54m_ck = {
+        .name           = "func_54m_ck",
+        .parent         = &apll54_ck,   /* can also be alt_clk */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_54M_SOURCE,
+        .clksel         = func_54m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .parent         = &dpll_ck,             /* can also be 32k */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+/* func_96m_ck */
+static const struct clksel_rate func_96m_apll96_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_96m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_96m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
+        { .parent = &alt_ck,    .rates = func_96m_alt_rates },
+        { .parent = NULL }
+};
+
+/* The parent of this clock is not selectable on 2420. */
+static struct clk func_96m_ck = {
+        .name           = "func_96m_ck",
+        .parent         = &apll96_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP2430_96M_SOURCE,
+        .clksel         = func_96m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* func_48m_ck */
+
+static const struct clksel_rate func_48m_apll96_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate func_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel func_48m_clksel[] = {
+        { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
+        { .parent = &alt_ck, .rates = func_48m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk func_48m_ck = {
+        .name           = "func_48m_ck",
+        .parent         = &apll96_ck,    /* 96M or Alt */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_48M_SOURCE,
+        .clksel         = func_48m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk func_12m_ck = {
+        .name           = "func_12m_ck",
+        .parent         = &func_48m_ck,
+        .fixed_div      = 4,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/* Secure timer, only available in secure mode */
+static struct clk wdt1_osc_ck = {
+        .name           = "ck_wdt1_osc",
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * The common_clkout* clksel_rate structs are common to
+ * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
+ * sys_clkout2_* are 2420-only, so the
+ * clksel_rate flags fields are inaccurate for those clocks. This is
+ * harmless since access to those clocks are gated by the struct clk
+ * flags fields, which mark them as 2420-only.
+ */
+static const struct clksel_rate common_clkout_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_clkout_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel common_clkout_src_clksel[] = {
+        { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
+        { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
+        { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
+        { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
+        { .parent = NULL }
+};
+
+static struct clk sys_clkout_src = {
+        .name           = "sys_clkout_src",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                RATE_PROPAGATES,
+        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate common_clkout_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkout_clksel[] = {
+        { .parent = &sys_clkout_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+
+static struct clk sys_clkout = {
+        .name           = "sys_clkout",
+        .parent         = &sys_clkout_src,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
+        .clksel         = sys_clkout_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2_src = {
+        .name           = "sys_clkout2_src",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
+        .enable_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
+        .clksel         = common_clkout_src_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
+        { .parent = NULL }
+};
+
+/* In 2430, new in 2420 ES2 */
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .parent         = &sys_clkout2_src,
+        .flags          = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP24XX_PRCM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk emul_ck = {
+        .name           = "emul_ck",
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP24XX_PRCM_CLKEMUL_CTRL,
+        .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
+        .recalc         = &followparent_recalc,
+
+};
+
+/*
+ * MPU clock domain
+ *      Clocks:
+ *              MPU_FCLK, MPU_ICLK
+ *              INT_M_FCLK, INT_M_I_CLK
+ *
+ * - Individual clocks are hardware managed.
+ * - Base divider comes from: CM_CLKSEL_MPU
+ *
+ */
+static const struct clksel_rate mpu_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 },
+};
+
+static const struct clksel mpu_clksel[] = {
+        { .parent = &core_ck, .rates = mpu_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk mpu_ck = {    /* Control cpu */
+        .name           = "mpu_ck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
+        .clksel         = mpu_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
+ * Clocks:
+ *      2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
+ *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
+ *
+ * Won't be too specific here. The core clock comes into this block
+ * it is divided then tee'ed. One branch goes directly to xyz enable
+ * controls. The other branch gets further divided by 2 then possibly
+ * routed into a synchronizer and out of clocks abc.
+ */
+static const struct clksel_rate dsp_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 0 },
+};
+
+static const struct clksel dsp_fck_clksel[] = {
+        { .parent = &core_ck, .rates = dsp_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* DSP interface clock */
+static const struct clksel_rate dsp_irate_ick_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X },
+        { .div = 0 },
+};
+
+static const struct clksel dsp_irate_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+        { .parent = NULL }
+};
+
+/*
+ * This clock does not exist as such in the TRM, but is added to
+ * separate source selection from  XXX
+ */
+static struct clk dsp_irate_ick = {
+        .name           = "dsp_irate_ick",
+        .parent         = &dsp_fck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
+                                CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_irate_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate             = &omap2_clksel_set_rate
+};
+
+/* 2420 only */
+static struct clk dsp_ick = {
+        .name           = "dsp_ick",     /* apparently ipi and isp */
+        .parent         = &dsp_irate_ick,
+        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
+};
+
+/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
+static struct clk iva2_1_ick = {
+        .name           = "iva2_1_ick",
+        .parent         = &dsp_irate_ick,
+        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+};
+
+static struct clk iva1_ifck = {
+        .name           = "iva1_ifck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
+                                RATE_PROPAGATES | DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
+        .clksel         = dsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* IVA1 mpu/int/i/f clocks are /2 of parent */
+static struct clk iva1_mpu_int_ifck = {
+        .name           = "iva1_mpu_int_ifck",
+        .parent         = &iva1_ifck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/*
+ * L3 clock domain
+ * L3 clocks are used for both interface and functional clocks to
+ * multiple entities. Some of these clocks are completely managed
+ * by hardware, and some others allow software control. Hardware
+ * managed ones general are based on directly CLK_REQ signals and
+ * various auto idle settings. The functional spec sets many of these
+ * as 'tie-high' for their enables.
+ *
+ * I-CLOCKS:
+ *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
+ *      CAM, HS-USB.
+ * F-CLOCK
+ *      SSI.
+ *
+ * GPMC memories and SDRC have timing and clock sensitive registers which
+ * may very well need notification when the clock changes. Currently for low
+ * operating points, these are taken care of in sleep.S.
+ */
+static const struct clksel_rate core_l3_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel core_l3_clksel[] = {
+        { .parent = &core_ck, .rates = core_l3_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
+        .name           = "core_l3_ck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP |
+                                CONFIG_PARTICIPANT | RATE_PROPAGATES,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
+        .clksel         = core_l3_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/* usb_l4_ick */
+static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel usb_l4_ick_clksel[] = {
+        { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
+        { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {        /* FS-USB interface clock */
+        .name           = "usb_l4_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
+        .clksel         = usb_l4_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * SSI is in L3 management domain, its direct parent is core not l3,
+ * many core power domain entities are grouped into the L3 clock
+ * domain.
+ * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
+ *
+ * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
+ */
+static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_243X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_sst_fck_clksel[] = {
+        { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk ssi_ssr_sst_fck = {
+        .name           = "ssi_fck",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_sst_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+/*
+ * GFX clock domain
+ *      Clocks:
+ * GFX_FCLK, GFX_ICLK
+ * GFX_CG1(2d), GFX_CG2(3d)
+ *
+ * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
+ * The 2d and 3d clocks run at a hardware determined
+ * divided value of fclk.
+ *
+ */
+/* XXX REVISIT: GFX clock is part of CONFIG_PARTICIPANT, no? doublecheck. */
+
+/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
+static const struct clksel gfx_fck_clksel[] = {
+        { .parent = &core_l3_ck, .rates = gfx_l3_rates },
+        { .parent = NULL },
+};
+
+static struct clk gfx_3d_fck = {
+        .name           = "gfx_3d_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_3D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_2d_fck = {
+        .name           = "gfx_2d_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_2D_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gfx_ick = {
+        .name           = "gfx_ick",            /* From l3 */
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * Modem clock domain (2430)
+ *      CLOCKS:
+ *              MDM_OSC_CLK
+ *              MDM_ICLK
+ * These clocks are usable in chassis mode only.
+ */
+static const struct clksel_rate mdm_ick_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_243X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
+        { .div = 6, .val = 6, .flags = RATE_IN_243X },
+        { .div = 9, .val = 9, .flags = RATE_IN_243X },
+        { .div = 0 }
+};
+
+static const struct clksel mdm_ick_clksel[] = {
+        { .parent = &core_ck, .rates = mdm_ick_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk mdm_ick = {           /* used both as a ick and fck */
+        .name           = "mdm_ick",
+        .parent         = &core_ck,
+        .flags          = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP2430_CLKSEL_MDM_MASK,
+        .clksel         = mdm_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk mdm_osc_ck = {
+        .name           = "mdm_osc_ck",
+        .parent         = &osc_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP2430_EN_OSC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * L4 clock management domain
+ *
+ * This domain contains lots of interface clocks from the L4 interface, some
+ * functional clocks.   Fixed APLL functional source clocks are managed in
+ * this domain.
+ */
+static const struct clksel_rate l4_core_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel l4_clksel[] = {
+        { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
+        { .parent = NULL }
+};
+
+static struct clk l4_ck = {             /* used both as an ick and fck */
+        .name           = "l4_ck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
+        .clksel         = l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * DSS clock domain
+ * CLOCKs:
+ * DSS_L4_ICLK, DSS_L3_ICLK,
+ * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
+ *
+ * DSS is both initiator and target.
+ */
+/* XXX Add RATE_NOT_VALIDATED */
+
+static const struct clksel_rate dss1_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dss1_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_24XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_24XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_24XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_24XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_24XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_24XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_24XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel dss1_fck_clksel[] = {
+        { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
+        { .parent = &core_ck, .rates = dss1_fck_core_rates },
+        { .parent = NULL },
+};
+
+static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
+        .name           = "dss_ick",
+        .parent         = &l4_ck,       /* really both l3 and l4 */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss1_fck = {
+        .name           = "dss1_fck",
+        .parent         = &core_ck,             /* Core or sys */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
+        .clksel         = dss1_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static const struct clksel_rate dss2_fck_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dss2_fck_48m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel dss2_fck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
+        { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
+        { .parent = NULL }
+};
+
+static struct clk dss2_fck = {          /* Alt clk used in power management */
+        .name           = "dss2_fck",
+        .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
+        .clksel         = dss2_fck_clksel,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_54m_fck = {       /* Alt clk used in power management */
+        .name           = "dss_54m_fck",        /* 54m tv clk */
+        .parent         = &func_54m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_TV_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * CORE power domain ICLK & FCLK defines.
+ * Many of the these can have more than one possible parent. Entries
+ * here will likely have an L4 interface parent, and may have multiple
+ * functional clock parents.
+ */
+static const struct clksel_rate gpt_alt_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap24xx_gpt_clksel[] = {
+        { .parent = &func_32k_ck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,      .rates = gpt_sys_rates },
+        { .parent = &alt_ck,      .rates = gpt_alt_rates },
+        { .parent = NULL },
+};
+
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
+        .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
+        .clksel         = omap24xx_gpt_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp5_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+        .name           = "mcspi_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+        .name           = "mcspi_fck",
+        .id             = 1,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+        .name           = "mcspi_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+        .name           = "mcspi_fck",
+        .id             = 2,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+        .name           = "mcspi_ick",
+        .id             = 3,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+        .name           = "mcspi_fck",
+        .id             = 3,
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpios_ick = {
+        .name           = "gpios_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpios_fck = {
+        .name           = "gpios_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_ick = {
+        .name           = "mpu_wdt_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mpu_wdt_fck = {
+        .name           = "mpu_wdt_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sync_32k_ick = {
+        .name           = "sync_32k_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP2430_EN_ICR_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_ick = {
+        .name           = "cam_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_fck = {
+        .name           = "cam_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt4_ick = {
+        .name           = "wdt4_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt4_fck = {
+        .name           = "wdt4_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc_ick = {
+        .name           = "mmc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc_fck = {
+        .name           = "mmc_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_MMC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_fck = {
+        .name           = "fac_fck",
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk eac_ick = {
+        .name           = "eac_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk eac_fck = {
+        .name           = "eac_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_EAC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+        .name           = "i2c_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+        .name           = "i2c_fck",
+        .id             = 2,
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2chs2_fck = {
+        .name           = "i2chs_fck",
+        .id             = 2,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+        .name           = "i2c_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+        .name           = "i2c_fck",
+        .id             = 1,
+        .parent         = &func_12m_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2chs1_fck = {
+        .name           = "i2chs_fck",
+        .id             = 1,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_I2CHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdma_fck = {
+        .name           = "sdma_fck",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdma_ick = {
+        .name           = "sdma_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk vlynq_ick = {
+        .name           = "vlynq_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel_rate vlynq_fck_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_242X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate vlynq_fck_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_242X },
+        { .div = 2, .val = 2, .flags = RATE_IN_242X },
+        { .div = 3, .val = 3, .flags = RATE_IN_242X },
+        { .div = 4, .val = 4, .flags = RATE_IN_242X },
+        { .div = 6, .val = 6, .flags = RATE_IN_242X },
+        { .div = 8, .val = 8, .flags = RATE_IN_242X },
+        { .div = 9, .val = 9, .flags = RATE_IN_242X },
+        { .div = 12, .val = 12, .flags = RATE_IN_242X },
+        { .div = 16, .val = 16, .flags = RATE_IN_242X | DEFAULT_RATE },
+        { .div = 18, .val = 18, .flags = RATE_IN_242X },
+        { .div = 0 }
+};
+
+static const struct clksel vlynq_fck_clksel[] = {
+        { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
+        { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
+        { .parent = NULL }
+};
+
+static struct clk vlynq_fck = {
+        .name           = "vlynq_fck",
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP242X | DELAYED_APP,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
+        .clksel         = vlynq_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate
+};
+
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des_ick = {
+        .name           = "des_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_DES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha_ick = {
+        .name           = "sha_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes_ick = {
+        .name           = "aes_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_AES_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+        .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_fck = {
+        .name           = "usb_fck",
+        .parent         = &func_48m_ck,
+        .flags          = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP24XX_EN_USB_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhs_ick = {
+        .name           = "usbhs_ick",
+        .parent         = &core_l3_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_USBHS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+        .name           = "mmchs_ick",
+        .id             = 1,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+        .name           = "mmchs_fck",
+        .id             = 1,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+        .name           = "mmchs_ick",
+        .id             = 2,
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+        .name           = "mmchs_fck",
+        .id             = 2,
+        .parent         = &func_96m_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+        .name           = "gpio5_fck",
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_GPIO5_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mdm_intc_ick = {
+        .name           = "mdm_intc_ick",
+        .parent         = &l4_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP2430_EN_MDM_INTC_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchsdb1_fck = {
+        .name           = "mmchsdb_fck",
+        .id             = 1,
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchsdb2_fck = {
+        .name           = "mmchsdb_fck",
+        .id             = 2,
+        .parent         = &func_32k_ck,
+        .flags          = CLOCK_IN_OMAP243X,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+        .enable_bit     = OMAP2430_EN_MMCHSDB2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * This clock is a composite clock which does entire set changes then
+ * forces a rebalance. It keys on the MPU speed, but it really could
+ * be any key speed part of a set in the rate table.
+ *
+ * to really change a set, you need memory table sets which get changed
+ * in sram, pre-notifiers & post notifiers, changing the top set, without
+ * having low level display recalc's won't work... this is why dpm notifiers
+ * work, isr's off, walk a list of clocks already _off_ and not messing with
+ * the bus.
+ *
+ * This clock should have no parent. It embodies the entire upper level
+ * active set. A parent will mess up some of the init also.
+ */
+static struct clk virt_prcm_set = {
+        .name           = "virt_prcm_set",
+        .flags          = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
+                                VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
+        .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
+        .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
+        .set_rate       = &omap2_select_table_rate,
+        .round_rate     = &omap2_round_to_table_rate,
+};
+
+static struct clk *onchip_24xx_clks[] __initdata = {
+        /* external root sources */
+        &func_32k_ck,
+        &osc_ck,
+        &sys_ck,
+        &alt_ck,
+        /* internal analog sources */
+        &dpll_ck,
+        &apll96_ck,
+        &apll54_ck,
+        /* internal prcm root sources */
+        &func_54m_ck,
+        &core_ck,
+        &func_96m_ck,
+        &func_48m_ck,
+        &func_12m_ck,
+        &wdt1_osc_ck,
+        &sys_clkout_src,
+        &sys_clkout,
+        &sys_clkout2_src,
+        &sys_clkout2,
+        &emul_ck,
+        /* mpu domain clocks */
+        &mpu_ck,
+        /* dsp domain clocks */
+        &dsp_fck,
+        &dsp_irate_ick,
+        &dsp_ick,               /* 242x */
+        &iva2_1_ick,            /* 243x */
+        &iva1_ifck,             /* 242x */
+        &iva1_mpu_int_ifck,     /* 242x */
+        /* GFX domain clocks */
+        &gfx_3d_fck,
+        &gfx_2d_fck,
+        &gfx_ick,
+        /* Modem domain clocks */
+        &mdm_ick,
+        &mdm_osc_ck,
+        /* DSS domain clocks */
+        &dss_ick,
+        &dss1_fck,
+        &dss2_fck,
+        &dss_54m_fck,
+        /* L3 domain clocks */
+        &core_l3_ck,
+        &ssi_ssr_sst_fck,
+        &usb_l4_ick,
+        /* L4 domain clocks */
+        &l4_ck,                 /* used as both core_l4 and wu_l4 */
+        &ssi_l4_ick,
+        /* virtual meta-group clock */
+        &virt_prcm_set,
+        /* general l4 interface ck, multi-parent functional clk */
+        &gpt1_ick,
+        &gpt1_fck,
+        &gpt2_ick,
+        &gpt2_fck,
+        &gpt3_ick,
+        &gpt3_fck,
+        &gpt4_ick,
+        &gpt4_fck,
+        &gpt5_ick,
+        &gpt5_fck,
+        &gpt6_ick,
+        &gpt6_fck,
+        &gpt7_ick,
+        &gpt7_fck,
+        &gpt8_ick,
+        &gpt8_fck,
+        &gpt9_ick,
+        &gpt9_fck,
+        &gpt10_ick,
+        &gpt10_fck,
+        &gpt11_ick,
+        &gpt11_fck,
+        &gpt12_ick,
+        &gpt12_fck,
+        &mcbsp1_ick,
+        &mcbsp1_fck,
+        &mcbsp2_ick,
+        &mcbsp2_fck,
+        &mcbsp3_ick,
+        &mcbsp3_fck,
+        &mcbsp4_ick,
+        &mcbsp4_fck,
+        &mcbsp5_ick,
+        &mcbsp5_fck,
+        &mcspi1_ick,
+        &mcspi1_fck,
+        &mcspi2_ick,
+        &mcspi2_fck,
+        &mcspi3_ick,
+        &mcspi3_fck,
+        &uart1_ick,
+        &uart1_fck,
+        &uart2_ick,
+        &uart2_fck,
+        &uart3_ick,
+        &uart3_fck,
+        &gpios_ick,
+        &gpios_fck,
+        &mpu_wdt_ick,
+        &mpu_wdt_fck,
+        &sync_32k_ick,
+        &wdt1_ick,
+        &omapctrl_ick,
+        &icr_ick,
+        &cam_fck,
+        &cam_ick,
+        &mailboxes_ick,
+        &wdt4_ick,
+        &wdt4_fck,
+        &wdt3_ick,
+        &wdt3_fck,
+        &mspro_ick,
+        &mspro_fck,
+        &mmc_ick,
+        &mmc_fck,
+        &fac_ick,
+        &fac_fck,
+        &eac_ick,
+        &eac_fck,
+        &hdq_ick,
+        &hdq_fck,
+        &i2c1_ick,
+        &i2c1_fck,
+        &i2chs1_fck,
+        &i2c2_ick,
+        &i2c2_fck,
+        &i2chs2_fck,
+        &gpmc_fck,
+        &sdma_fck,
+        &sdma_ick,
+        &vlynq_ick,
+        &vlynq_fck,
+        &sdrc_ick,
+        &des_ick,
+        &sha_ick,
+        &rng_ick,
+        &aes_ick,
+        &pka_ick,
+        &usb_fck,
+        &usbhs_ick,
+        &mmchs1_ick,
+        &mmchs1_fck,
+        &mmchs2_ick,
+        &mmchs2_fck,
+        &gpio5_ick,
+        &gpio5_fck,
+        &mdm_intc_ick,
+        &mmchsdb1_fck,
+        &mmchsdb2_fck,
+};
+
+#endif
+
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
new file mode 100644
index 000000000000..b42bdd6079a5
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -0,0 +1,235 @@
+/*
+ * OMAP3-specific clock framework functions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sram.h>
+#include <asm/div64.h>
+#include <asm/bitops.h>
+
+#include "memory.h"
+#include "clock.h"
+#include "clock34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+
+/* CM_CLKEN_PLL*.EN* bit values */
+#define DPLL_LOCKED             0x7
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+static void omap3_dpll_recalc(struct clk *clk)
+{
+        clk->rate = omap2_get_dpll_rate(clk);
+
+        propagate_rate(clk);
+}
+
+/**
+ * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
+ * @clk: DPLL output struct clk
+ *
+ * Using parent clock DPLL data, look up DPLL state.  If locked, set our
+ * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
+ */
+static void omap3_clkoutx2_recalc(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+        struct clk *pclk;
+
+        /* Walk up the parents of clk, looking for a DPLL */
+        pclk = clk->parent;
+        while (pclk && !pclk->dpll_data)
+                pclk = pclk->parent;
+
+        /* clk does not have a DPLL as a parent? */
+        WARN_ON(!pclk);
+
+        dd = pclk->dpll_data;
+
+        WARN_ON(!dd->control_reg || !dd->enable_mask);
+
+        v = __raw_readl(dd->control_reg) & dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+        if (v != DPLL_LOCKED)
+                clk->rate = clk->parent->rate;
+        else
+                clk->rate = clk->parent->rate * 2;
+
+        if (clk->flags & RATE_PROPAGATES)
+                propagate_rate(clk);
+}
+
+/*
+ * As it is structured now, this will prevent an OMAP2/3 multiboot
+ * kernel from compiling.  This will need further attention.
+ */
+#if defined(CONFIG_ARCH_OMAP3)
+
+static struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+};
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+        /* REVISIT: Not ready for 343x */
+#if 0
+        u32 rate;
+
+        if (vclk == NULL || sclk == NULL)
+                return;
+
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);
+#endif
+}
+
+/* REVISIT: Move this init stuff out into clock.c */
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+        if (!mpurate)
+                return -EINVAL;
+
+        /* REVISIT: not yet ready for 343x */
+#if 0
+        if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+                printk(KERN_ERR "Could not find matching MPU rate\n");
+#endif
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+               (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
+
+        return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+int __init omap2_clk_init(void)
+{
+        /* struct prcm_config *prcm; */
+        struct clk **clkp;
+        /* u32 clkrate; */
+        u32 cpu_clkflg;
+
+        /* REVISIT: Ultimately this will be used for multiboot */
+#if 0
+        if (cpu_is_omap242x()) {
+                cpu_mask = RATE_IN_242X;
+                cpu_clkflg = CLOCK_IN_OMAP242X;
+                clkp = onchip_24xx_clks;
+        } else if (cpu_is_omap2430()) {
+                cpu_mask = RATE_IN_243X;
+                cpu_clkflg = CLOCK_IN_OMAP243X;
+                clkp = onchip_24xx_clks;
+        }
+#endif
+        if (cpu_is_omap34xx()) {
+                cpu_mask = RATE_IN_343X;
+                cpu_clkflg = CLOCK_IN_OMAP343X;
+                clkp = onchip_34xx_clks;
+
+                /*
+                 * Update this if there are further clock changes between ES2
+                 * and production parts
+                 */
+                if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
+                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
+                        cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
+                } else {
+                        cpu_mask |= RATE_IN_3430ES2;
+                        cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
+                }
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (clkp = onchip_34xx_clks;
+             clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
+             clkp++) {
+                if ((*clkp)->flags & cpu_clkflg)
+                        clk_register(*clkp);
+        }
+
+        /* REVISIT: Not yet ready for OMAP3 */
+#if 0
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                         break;
+        }
+        curr_prcm_set = prcm;
+#endif
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
+        /* REVISIT: not yet ready for 343x */
+#if 0
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+#endif
+        return 0;
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
new file mode 100644
index 000000000000..cf4644a94b9b
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -0,0 +1,3009 @@
+/*
+ * OMAP3 clock framework
+ *
+ * Virtual clocks are introduced as a convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
+
+#include <asm/arch/control.h>
+
+#include "clock.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+
+static void omap3_dpll_recalc(struct clk *clk);
+static void omap3_clkoutx2_recalc(struct clk *clk);
+
+/*
+ * DPLL1 supplies clock to the MPU.
+ * DPLL2 supplies clock to the IVA2.
+ * DPLL3 supplies CORE domain clocks.
+ * DPLL4 supplies peripheral clocks.
+ * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
+ */
+
+/* PRM CLOCKS */
+
+/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
+static struct clk omap_32k_fck = {
+        .name           = "omap_32k_fck",
+        .rate           = 32768,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk secure_32k_fck = {
+        .name           = "secure_32k_fck",
+        .rate           = 32768,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* Virtual source clocks for osc_sys_ck */
+static struct clk virt_12m_ck = {
+        .name           = "virt_12m_ck",
+        .rate           = 12000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_13m_ck = {
+        .name           = "virt_13m_ck",
+        .rate           = 13000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_16_8m_ck = {
+        .name           = "virt_16_8m_ck",
+        .rate           = 16800000,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_19_2m_ck = {
+        .name           = "virt_19_2m_ck",
+        .rate           = 19200000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_26m_ck = {
+        .name           = "virt_26m_ck",
+        .rate           = 26000000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static struct clk virt_38_4m_ck = {
+        .name           = "virt_38_4m_ck",
+        .rate           = 38400000,
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+static const struct clksel_rate osc_sys_12m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_13m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_16_8m_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_19_2m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_26m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_38_4m_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel osc_sys_clksel[] = {
+        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
+        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
+        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
+        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
+        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
+        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
+        { .parent = NULL },
+};
+
+/* Oscillator clock */
+/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
+static struct clk osc_sys_ck = {
+        .name           = "osc_sys_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSEL,
+        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
+        .clksel         = osc_sys_clksel,
+        /* REVISIT: deal with autoextclkmode? */
+        .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate div2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel sys_clksel[] = {
+        { .parent = &osc_sys_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
+/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
+static struct clk sys_ck = {
+        .name           = "sys_ck",
+        .parent         = &osc_sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
+        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
+        .clksel         = sys_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sys_altclk = {
+        .name           = "sys_altclk",
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* Optional external clock input for some McBSPs */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &propagate_rate,
+};
+
+/* PRM EXTERNAL CLOCK OUTPUT */
+
+static struct clk sys_clkout1 = {
+        .name           = "sys_clkout1",
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLLS */
+
+/* CM CLOCKS */
+
+static const struct clksel_rate dpll_bypass_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate dpll_locked_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate div16_dpll_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 5, .val = 5, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 7, .val = 7, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 9, .val = 9, .flags = RATE_IN_343X },
+        { .div = 10, .val = 10, .flags = RATE_IN_343X },
+        { .div = 11, .val = 11, .flags = RATE_IN_343X },
+        { .div = 12, .val = 12, .flags = RATE_IN_343X },
+        { .div = 13, .val = 13, .flags = RATE_IN_343X },
+        { .div = 14, .val = 14, .flags = RATE_IN_343X },
+        { .div = 15, .val = 15, .flags = RATE_IN_343X },
+        { .div = 16, .val = 16, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+/* DPLL1 */
+/* MPU clock source */
+/* Type: DPLL */
+static const struct dpll_data dpll1_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll1_ck = {
+        .name           = "dpll1_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll1_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed.
+ */
+static struct clk dpll1_x2_ck = {
+        .name           = "dpll1_x2_ck",
+        .parent         = &dpll1_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
+static const struct clksel div16_dpll1_x2m2_clksel[] = {
+        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * Does not exist in the TRM - needed to separate the M2 divider from
+ * bypass selection in mpu_ck
+ */
+static struct clk dpll1_x2m2_ck = {
+        .name           = "dpll1_x2m2_ck",
+        .parent         = &dpll1_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll1_x2m2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL2 */
+/* IVA2 clock source */
+/* Type: DPLL */
+
+static const struct dpll_data dpll2_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll2_ck = {
+        .name           = "dpll2_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll2_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll2_m2x2_clksel[] = {
+        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
+ * or CLKOUTX2. CLKOUT seems most plausible.
+ */
+static struct clk dpll2_m2_ck = {
+        .name           = "dpll2_m2_ck",
+        .parent         = &dpll2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll2_m2x2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL3 */
+/* Source clock for all interfaces and for some device fclks */
+/* Type: DPLL */
+static const struct dpll_data dpll3_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll3_ck = {
+        .name           = "dpll3_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll3_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed
+ */
+static struct clk dpll3_x2_ck = {
+        .name           = "dpll3_x2_ck",
+        .parent         = &dpll3_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_dpll3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
+        { .div = 0 },
+};
+
+static const struct clksel div31_dpll3m2_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
+        { .parent = NULL }
+};
+
+/*
+ * DPLL3 output M2
+ * REVISIT: This DPLL output divider must be changed in SRAM, so until
+ * that code is ready, this should remain a 'read-only' clksel clock.
+ */
+static struct clk dpll3_m2_ck = {
+        .name           = "dpll3_m2_ck",
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div31_dpll3m2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel core_ck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = core_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel dpll3_m2x2_ck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk dpll3_m2x2_ck = {
+        .name           = "dpll3_m2x2_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = dpll3_m2x2_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static const struct clksel div16_dpll3_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll3_m3x2_ck */
+static struct clk dpll3_m3_ck = {
+        .name           = "dpll3_m3_ck",
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
+        .clksel         = div16_dpll3_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll3_m3x2_ck = {
+        .name           = "dpll3_m3x2_ck",
+        .parent         = &dpll3_m3_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel emu_core_alwon_ck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk emu_core_alwon_ck = {
+        .name           = "emu_core_alwon_ck",
+        .parent         = &dpll3_m3x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_CORE_CLK,
+        .clksel         = emu_core_alwon_ck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL4 */
+/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
+/* Type: DPLL */
+static const struct dpll_data dpll4_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll4_ck = {
+        .name           = "dpll4_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll4_dd,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed --
+ * XXX does this serve any downstream clocks?
+ */
+static struct clk dpll4_x2_ck = {
+        .name           = "dpll4_x2_ck",
+        .parent         = &dpll4_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel div16_dpll4_clksel[] = {
+        { .parent = &dpll4_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll4_m2x2_ck */
+static struct clk dpll4_m2_ck = {
+        .name           = "dpll4_m2_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+        .clksel_mask    = OMAP3430_DIV_96M_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m2x2_ck = {
+        .name           = "dpll4_m2x2_ck",
+        .parent         = &dpll4_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel omap_96m_alwon_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_96m_alwon_fck = {
+        .name           = "omap_96m_alwon_fck",
+        .parent         = &dpll4_m2x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = omap_96m_alwon_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                 PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk omap_96m_fck = {
+        .name           = "omap_96m_fck",
+        .parent         = &omap_96m_alwon_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel cm_96m_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk cm_96m_fck = {
+        .name           = "cm_96m_fck",
+        .parent         = &dpll4_m2x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = cm_96m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m3x2_ck */
+static struct clk dpll4_m3_ck = {
+        .name           = "dpll4_m3_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m3x2_ck = {
+        .name           = "dpll4_m3x2_ck",
+        .parent         = &dpll4_m3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel virt_omap_54m_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk virt_omap_54m_fck = {
+        .name           = "virt_omap_54m_fck",
+        .parent         = &dpll4_m3x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = virt_omap_54m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_54m_clksel[] = {
+        { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
+        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_54m_fck = {
+        .name           = "omap_54m_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_54M,
+        .clksel         = omap_54m_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_48m_96md2_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_48m_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
+        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_48m_fck = {
+        .name           = "omap_48m_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_48M,
+        .clksel         = omap_48m_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk omap_12m_fck = {
+        .name           = "omap_12m_fck",
+        .parent         = &omap_48m_fck,
+        .fixed_div      = 4,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/* This virstual clock is the source for dpll4_m4x2_ck */
+static struct clk dpll4_m4_ck = {
+        .name           = "dpll4_m4_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m4x2_ck = {
+        .name           = "dpll4_m4x2_ck",
+        .parent         = &dpll4_m4_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m5x2_ck */
+static struct clk dpll4_m5_ck = {
+        .name           = "dpll4_m5_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m5x2_ck = {
+        .name           = "dpll4_m5x2_ck",
+        .parent         = &dpll4_m5_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m6x2_ck */
+static struct clk dpll4_m6_ck = {
+        .name           = "dpll4_m6_ck",
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m6x2_ck = {
+        .name           = "dpll4_m6x2_ck",
+        .parent         = &dpll4_m6_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static struct clk emu_per_alwon_ck = {
+        .name           = "emu_per_alwon_ck",
+        .parent         = &dpll4_m6x2_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL5 */
+/* Supplies 120MHz clock, USIM source clock */
+/* Type: DPLL */
+/* 3430ES2 only */
+static const struct dpll_data dpll5_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+};
+
+static struct clk dpll5_ck = {
+        .name           = "dpll5_ck",
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll5_dd,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+                                ALWAYS_ENABLED,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll5_clksel[] = {
+        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+static struct clk dpll5_m2_ck = {
+        .name           = "dpll5_m2_ck",
+        .parent         = &dpll5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
+        .clksel         = div16_dpll5_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel omap_120m_fck_clksel[] = {
+        { .parent = &sys_ck,      .rates = dpll_bypass_rates },
+        { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_120m_fck = {
+        .name           = "omap_120m_fck",
+        .parent         = &dpll5_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+        .clksel         = omap_120m_fck_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM EXTERNAL CLOCK OUTPUTS */
+
+static const struct clksel_rate clkout2_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel clkout2_src_clksel[] = {
+        { .parent = &core_ck,             .rates = clkout2_src_core_rates },
+        { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
+        { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
+        { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
+        { .parent = NULL }
+};
+
+static struct clk clkout2_src_ck = {
+        .name           = "clkout2_src_ck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
+        .clksel         = clkout2_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate sys_clkout2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 4, .val = 2, .flags = RATE_IN_343X },
+        { .div = 8, .val = 3, .flags = RATE_IN_343X },
+        { .div = 16, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
+        { .parent = NULL },
+};
+
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM OUTPUT CLOCKS */
+
+static struct clk corex2_fck = {
+        .name           = "corex2_fck",
+        .parent         = &dpll3_m2x2_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL power domain clock controls */
+
+static const struct clksel div2_core_clksel[] = {
+        { .parent = &core_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+/*
+ * REVISIT: Are these in DPLL power domain or CM power domain? docs
+ * may be inconsistent here?
+ */
+static struct clk dpll1_fck = {
+        .name           = "dpll1_fck",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * MPU clksel:
+ * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
+ * derives from the high-frequency bypass clock originating from DPLL3,
+ * called 'dpll1_fck'
+ */
+static const struct clksel mpu_clksel[] = {
+        { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
+        { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk mpu_ck = {
+        .name           = "mpu_ck",
+        .parent         = &dpll1_x2m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = mpu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
+static const struct clksel_rate arm_fck_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel arm_fck_clksel[] = {
+        { .parent = &mpu_ck, .rates = arm_fck_rates },
+        { .parent = NULL }
+};
+
+static struct clk arm_fck = {
+        .name           = "arm_fck",
+        .parent         = &mpu_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = arm_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * REVISIT: This clock is never specifically defined in the 3430 TRM,
+ * although it is referenced - so this is a guess
+ */
+static struct clk emu_mpu_alwon_ck = {
+        .name           = "emu_mpu_alwon_ck",
+        .parent         = &mpu_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dpll2_fck = {
+        .name           = "dpll2_fck",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * IVA2 clksel:
+ * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
+ * derives from the high-frequency bypass clock originating from DPLL3,
+ * called 'dpll2_fck'
+ */
+
+static const struct clksel iva2_clksel[] = {
+        { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
+        { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk iva2_ck = {
+        .name           = "iva2_ck",
+        .parent         = &dpll2_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
+        .clksel         = iva2_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* Common interface clocks */
+
+static struct clk l3_ick = {
+        .name           = "l3_ick",
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
+        .clksel         = div2_core_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel div2_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk l4_ick = {
+        .name           = "l4_ick",
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
+        .clksel         = div2_l3_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+
+};
+
+static const struct clksel div2_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk rm_ick = {
+        .name           = "rm_ick",
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
+        .clksel         = div2_l4_clksel,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* GFX power domain */
+
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
+
+static const struct clksel gfx_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = gfx_l3_rates },
+        { .parent = NULL }
+};
+
+static struct clk gfx_l3_fck = {
+        .name           = "gfx_l3_fck",
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_l3_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gfx_l3_ick = {
+        .name           = "gfx_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg1_ck = {
+        .name           = "gfx_cg1_ck",
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg2_ck = {
+        .name           = "gfx_cg2_ck",
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+/* SGX power domain - 3430ES2 only */
+
+static const struct clksel_rate sgx_core_rates[] = {
+        { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4, .val = 1, .flags = RATE_IN_343X },
+        { .div = 6, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate sgx_96m_rates[] = {
+        { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel sgx_clksel[] = {
+        { .parent = &core_ck,    .rates = sgx_core_rates },
+        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+        { .parent = NULL },
+};
+
+static struct clk sgx_fck = {
+        .name           = "sgx_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
+        .clksel         = sgx_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sgx_ick = {
+        .name           = "sgx_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE power domain */
+
+static struct clk d2d_26m_fck = {
+        .name           = "d2d_26m_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel omap343x_gpt_clksel[] = {
+        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,       .rates = gpt_sys_rates },
+        { .parent = NULL}
+};
+
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cpefuse_fck = {
+        .name           = "cpefuse_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ts_fck = {
+        .name           = "ts_fck",
+        .parent         = &omap_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_fck = {
+        .name           = "usbtll_fck",
+        .parent         = &omap_120m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE 96M FCLK-derived clocks */
+
+static struct clk core_96m_fck = {
+        .name           = "core_96m_fck",
+        .parent         = &omap_96m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_fck = {
+        .name           = "mmchs_fck",
+        .id             = 3,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+        .name           = "mmchs_fck",
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+        .name           = "mmchs_fck",
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_fck = {
+        .name           = "i2c_fck",
+        .id             = 3,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+        .name           = "i2c_fck",
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+        .name           = "i2c_fck",
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
+ * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
+ */
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_15_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp5_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp1_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CORE_48M_FCK-derived clocks */
+
+static struct clk core_48m_fck = {
+        .name           = "core_48m_fck",
+        .parent         = &omap_48m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_fck = {
+        .name           = "mcspi_fck",
+        .id             = 4,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+        .name           = "mcspi_fck",
+        .id             = 3,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+        .name           = "mcspi_fck",
+        .id             = 2,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+        .name           = "mcspi_fck",
+        .id             = 1,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fshostusb_fck = {
+        .name           = "fshostusb_fck",
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_12M_FCK based clocks */
+
+static struct clk core_12m_fck = {
+        .name           = "core_12m_fck",
+        .parent         = &omap_12m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .parent         = &core_12m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL3-derived clock */
+
+static const struct clksel_rate ssi_ssr_corex2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_clksel[] = {
+        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
+        { .parent = NULL }
+};
+
+static struct clk ssi_ssr_fck = {
+        .name           = "ssi_ssr_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck = {
+        .name           = "ssi_sst_fck",
+        .parent         = &ssi_ssr_fck,
+        .fixed_div      = 2,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+
+
+/* CORE_L3_ICK based clocks */
+
+static struct clk core_l3_ick = {
+        .name           = "core_l3_ick",
+        .parent         = &l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick = {
+        .name           = "hsotgusb_ick",
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .parent         = &core_l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
+                                ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURITY_L3_ICK based clocks */
+
+static struct clk security_l3_ick = {
+        .name           = "security_l3_ick",
+        .parent         = &l3_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .parent         = &security_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_L4_ICK based clocks */
+
+static struct clk core_l4_ick = {
+        .name           = "core_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_ick = {
+        .name           = "usbtll_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_ick = {
+        .name           = "mmchs_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* Intersystem Communication Registers - chassis mode only */
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes2_ick = {
+        .name           = "aes2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha12_ick = {
+        .name           = "sha12_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des2_ick = {
+        .name           = "des2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+        .name           = "mmchs_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+        .name           = "mmchs_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_ick = {
+        .name           = "mcspi_ick",
+        .id             = 4,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+        .name           = "mcspi_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+        .name           = "mcspi_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+        .name           = "mcspi_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_ick = {
+        .name           = "i2c_ick",
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+        .name           = "i2c_ick",
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+        .name           = "i2c_ick",
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp5_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp1_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SSI_L4_ICK based clocks */
+
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ssi_ick = {
+        .name           = "ssi_ick",
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me */
+
+static const struct clksel usb_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {
+        .name           = "usb_l4_ick",
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
+        .clksel         = usb_l4_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES1,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
+
+/* SECURITY_L4_ICK2 based clocks */
+
+static struct clk security_l4_ick2 = {
+        .name           = "security_l4_ick2",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes1_ick = {
+        .name           = "aes1_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha11_ick = {
+        .name           = "sha11_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des1_ick = {
+        .name           = "des1_ick",
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* DSS */
+static const struct clksel dss1_alwon_fck_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk dss1_alwon_fck = {
+        .name           = "dss1_alwon_fck",
+        .parent         = &dpll4_m4x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = dss1_alwon_fck_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk dss_tv_fck = {
+        .name           = "dss_tv_fck",
+        .parent         = &omap_54m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_96m_fck = {
+        .name           = "dss_96m_fck",
+        .parent         = &omap_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss2_alwon_fck = {
+        .name           = "dss2_alwon_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* CAM */
+
+static const struct clksel cam_mclk_clksel[] = {
+        { .parent = &sys_ck,        .rates = dpll_bypass_rates },
+        { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
+        { .parent = NULL }
+};
+
+static struct clk cam_mclk = {
+        .name           = "cam_mclk",
+        .parent         = &dpll4_m5x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
+        .clksel         = cam_mclk_clksel,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cam_l3_ick = {
+        .name           = "cam_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_l4_ick = {
+        .name           = "cam_l4_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* USBHOST - 3430ES2 only */
+
+static struct clk usbhost_120m_fck = {
+        .name           = "usbhost_120m_fck",
+        .parent         = &omap_120m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_48m_fck = {
+        .name           = "usbhost_48m_fck",
+        .parent         = &omap_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_l3_ick = {
+        .name           = "usbhost_l3_ick",
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_l4_ick = {
+        .name           = "usbhost_l4_ick",
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_sar_fck = {
+        .name           = "usbhost_sar_fck",
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
+        .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+/* WKUP */
+
+static const struct clksel_rate usim_96m_rates[] = {
+        { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4,  .val = 4, .flags = RATE_IN_343X },
+        { .div = 8,  .val = 5, .flags = RATE_IN_343X },
+        { .div = 10, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate usim_120m_rates[] = {
+        { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
+        { .div = 16, .val = 9,  .flags = RATE_IN_343X },
+        { .div = 20, .val = 10, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel usim_clksel[] = {
+        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
+        { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
+        { .parent = &sys_ck,            .rates = div2_rates },
+        { .parent = NULL },
+};
+
+/* 3430ES2 only */
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+        .clksel         = usim_clksel,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk wkup_32k_fck = {
+        .name           = "wkup_32k_fck",
+        .parent         = &omap_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_fck = {
+        .name           = "gpio1_fck",
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_fck = {
+        .name           = "wdt2_fck",
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wkup_l4_ick = {
+        .name           = "wkup_l4_ick",
+        .parent         = &sys_ck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
+static struct clk usim_ick = {
+        .name           = "usim_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .flags          = CLOCK_IN_OMAP3430ES2,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_ick = {
+        .name           = "wdt2_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_ick = {
+        .name           = "gpio1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omap_32ksync_ick = {
+        .name           = "omap_32ksync_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+
+
+/* PER clock domain */
+
+static struct clk per_96m_fck = {
+        .name           = "per_96m_fck",
+        .parent         = &omap_96m_alwon_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_48m_fck = {
+        .name           = "per_48m_fck",
+        .parent         = &omap_48m_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk per_32k_alwon_fck = {
+        .name           = "per_32k_alwon_fck",
+        .parent         = &omap_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_fck = {
+        .name           = "gpio6_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_fck = {
+        .name           = "gpio5_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_fck = {
+        .name           = "gpio4_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_fck = {
+        .name           = "gpio3_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_fck = {
+        .name           = "gpio2_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_l4_ick = {
+        .name           = "per_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+                                PARENT_CONTROLS_CLOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_ick = {
+        .name           = "gpio6_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_ick = {
+        .name           = "gpio4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_ick = {
+        .name           = "gpio3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_ick = {
+        .name           = "gpio2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp2_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp3_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp4_ick",
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel mcbsp_234_clksel[] = {
+        { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp3_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp4_fck",
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* EMU clocks */
+
+/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
+
+static const struct clksel_rate emu_src_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_per_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_mpu_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel emu_src_clksel[] = {
+        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
+        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
+        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
+        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
+        { .parent = NULL },
+};
+
+/*
+ * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
+ * to switch the source of some of the EMU clocks.
+ * XXX Are there CLKEN bits for these EMU clks?
+ */
+static struct clk emu_src_ck = {
+        .name           = "emu_src_ck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclk_emu_rates[] = {
+        { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclk_fck = {
+        .name           = "pclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
+        .clksel         = pclk_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclkx2_emu_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclkx2_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclkx2_fck = {
+        .name           = "pclkx2_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
+        .clksel         = pclkx2_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel atclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk atclk_fck = {
+        .name           = "atclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
+        .clksel         = atclk_emu_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk traceclk_src_fck = {
+        .name           = "traceclk_src_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate traceclk_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel traceclk_clksel[] = {
+        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
+        { .parent = NULL },
+};
+
+static struct clk traceclk_fck = {
+        .name           = "traceclk_fck",
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
+        .clksel         = traceclk_clksel,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* SR clocks */
+
+/* SmartReflex fclk (VDD1) */
+static struct clk sr1_fck = {
+        .name           = "sr1_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+/* SmartReflex fclk (VDD2) */
+static struct clk sr2_fck = {
+        .name           = "sr2_fck",
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_l4_ick = {
+        .name           = "sr_l4_ick",
+        .parent         = &l4_ick,
+        .flags          = CLOCK_IN_OMAP343X,
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURE_32K_FCK clocks */
+
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .parent         = &secure_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_fck = {
+        .name           = "wdt1_fck",
+        .parent         = &secure_32k_fck,
+        .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk *onchip_34xx_clks[] __initdata = {
+        &omap_32k_fck,
+        &virt_12m_ck,
+        &virt_13m_ck,
+        &virt_16_8m_ck,
+        &virt_19_2m_ck,
+        &virt_26m_ck,
+        &virt_38_4m_ck,
+        &osc_sys_ck,
+        &sys_ck,
+        &sys_altclk,
+        &mcbsp_clks,
+        &sys_clkout1,
+        &dpll1_ck,
+        &dpll1_x2_ck,
+        &dpll1_x2m2_ck,
+        &dpll2_ck,
+        &dpll2_m2_ck,
+        &dpll3_ck,
+        &core_ck,
+        &dpll3_x2_ck,
+        &dpll3_m2_ck,
+        &dpll3_m2x2_ck,
+        &dpll3_m3_ck,
+        &dpll3_m3x2_ck,
+        &emu_core_alwon_ck,
+        &dpll4_ck,
+        &dpll4_x2_ck,
+        &omap_96m_alwon_fck,
+        &omap_96m_fck,
+        &cm_96m_fck,
+        &virt_omap_54m_fck,
+        &omap_54m_fck,
+        &omap_48m_fck,
+        &omap_12m_fck,
+        &dpll4_m2_ck,
+        &dpll4_m2x2_ck,
+        &dpll4_m3_ck,
+        &dpll4_m3x2_ck,
+        &dpll4_m4_ck,
+        &dpll4_m4x2_ck,
+        &dpll4_m5_ck,
+        &dpll4_m5x2_ck,
+        &dpll4_m6_ck,
+        &dpll4_m6x2_ck,
+        &emu_per_alwon_ck,
+        &dpll5_ck,
+        &dpll5_m2_ck,
+        &omap_120m_fck,
+        &clkout2_src_ck,
+        &sys_clkout2,
+        &corex2_fck,
+        &dpll1_fck,
+        &mpu_ck,
+        &arm_fck,
+        &emu_mpu_alwon_ck,
+        &dpll2_fck,
+        &iva2_ck,
+        &l3_ick,
+        &l4_ick,
+        &rm_ick,
+        &gfx_l3_fck,
+        &gfx_l3_ick,
+        &gfx_cg1_ck,
+        &gfx_cg2_ck,
+        &sgx_fck,
+        &sgx_ick,
+        &d2d_26m_fck,
+        &gpt10_fck,
+        &gpt11_fck,
+        &cpefuse_fck,
+        &ts_fck,
+        &usbtll_fck,
+        &core_96m_fck,
+        &mmchs3_fck,
+        &mmchs2_fck,
+        &mspro_fck,
+        &mmchs1_fck,
+        &i2c3_fck,
+        &i2c2_fck,
+        &i2c1_fck,
+        &mcbsp5_fck,
+        &mcbsp1_fck,
+        &core_48m_fck,
+        &mcspi4_fck,
+        &mcspi3_fck,
+        &mcspi2_fck,
+        &mcspi1_fck,
+        &uart2_fck,
+        &uart1_fck,
+        &fshostusb_fck,
+        &core_12m_fck,
+        &hdq_fck,
+        &ssi_ssr_fck,
+        &ssi_sst_fck,
+        &core_l3_ick,
+        &hsotgusb_ick,
+        &sdrc_ick,
+        &gpmc_fck,
+        &security_l3_ick,
+        &pka_ick,
+        &core_l4_ick,
+        &usbtll_ick,
+        &mmchs3_ick,
+        &icr_ick,
+        &aes2_ick,
+        &sha12_ick,
+        &des2_ick,
+        &mmchs2_ick,
+        &mmchs1_ick,
+        &mspro_ick,
+        &hdq_ick,
+        &mcspi4_ick,
+        &mcspi3_ick,
+        &mcspi2_ick,
+        &mcspi1_ick,
+        &i2c3_ick,
+        &i2c2_ick,
+        &i2c1_ick,
+        &uart2_ick,
+        &uart1_ick,
+        &gpt11_ick,
+        &gpt10_ick,
+        &mcbsp5_ick,
+        &mcbsp1_ick,
+        &fac_ick,
+        &mailboxes_ick,
+        &omapctrl_ick,
+        &ssi_l4_ick,
+        &ssi_ick,
+        &usb_l4_ick,
+        &security_l4_ick2,
+        &aes1_ick,
+        &rng_ick,
+        &sha11_ick,
+        &des1_ick,
+        &dss1_alwon_fck,
+        &dss_tv_fck,
+        &dss_96m_fck,
+        &dss2_alwon_fck,
+        &dss_ick,
+        &cam_mclk,
+        &cam_l3_ick,
+        &cam_l4_ick,
+        &usbhost_120m_fck,
+        &usbhost_48m_fck,
+        &usbhost_l3_ick,
+        &usbhost_l4_ick,
+        &usbhost_sar_fck,
+        &usim_fck,
+        &gpt1_fck,
+        &wkup_32k_fck,
+        &gpio1_fck,
+        &wdt2_fck,
+        &wkup_l4_ick,
+        &usim_ick,
+        &wdt2_ick,
+        &wdt1_ick,
+        &gpio1_ick,
+        &omap_32ksync_ick,
+        &gpt12_ick,
+        &gpt1_ick,
+        &per_96m_fck,
+        &per_48m_fck,
+        &uart3_fck,
+        &gpt2_fck,
+        &gpt3_fck,
+        &gpt4_fck,
+        &gpt5_fck,
+        &gpt6_fck,
+        &gpt7_fck,
+        &gpt8_fck,
+        &gpt9_fck,
+        &per_32k_alwon_fck,
+        &gpio6_fck,
+        &gpio5_fck,
+        &gpio4_fck,
+        &gpio3_fck,
+        &gpio2_fck,
+        &wdt3_fck,
+        &per_l4_ick,
+        &gpio6_ick,
+        &gpio5_ick,
+        &gpio4_ick,
+        &gpio3_ick,
+        &gpio2_ick,
+        &wdt3_ick,
+        &uart3_ick,
+        &gpt9_ick,
+        &gpt8_ick,
+        &gpt7_ick,
+        &gpt6_ick,
+        &gpt5_ick,
+        &gpt4_ick,
+        &gpt3_ick,
+        &gpt2_ick,
+        &mcbsp2_ick,
+        &mcbsp3_ick,
+        &mcbsp4_ick,
+        &mcbsp2_fck,
+        &mcbsp3_fck,
+        &mcbsp4_fck,
+        &emu_src_ck,
+        &pclk_fck,
+        &pclkx2_fck,
+        &atclk_fck,
+        &traceclk_src_fck,
+        &traceclk_fck,
+        &sr1_fck,
+        &sr2_fck,
+        &sr_l4_ick,
+        &secure_32k_fck,
+        &gpt12_fck,
+        &wdt1_fck,
+};
+
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
new file mode 100644
index 000000000000..20ac38100678
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -0,0 +1,401 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Clock Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP24XX_EN_CAM_SHIFT                           31
+#define OMAP24XX_EN_CAM                                 (1 << 31)
+#define OMAP24XX_EN_WDT4_SHIFT                          29
+#define OMAP24XX_EN_WDT4                                (1 << 29)
+#define OMAP2420_EN_WDT3_SHIFT                          28
+#define OMAP2420_EN_WDT3                                (1 << 28)
+#define OMAP24XX_EN_MSPRO_SHIFT                         27
+#define OMAP24XX_EN_MSPRO                               (1 << 27)
+#define OMAP24XX_EN_FAC_SHIFT                           25
+#define OMAP24XX_EN_FAC                                 (1 << 25)
+#define OMAP2420_EN_EAC_SHIFT                           24
+#define OMAP2420_EN_EAC                                 (1 << 24)
+#define OMAP24XX_EN_HDQ_SHIFT                           23
+#define OMAP24XX_EN_HDQ                                 (1 << 23)
+#define OMAP2420_EN_I2C2_SHIFT                          20
+#define OMAP2420_EN_I2C2                                (1 << 20)
+#define OMAP2420_EN_I2C1_SHIFT                          19
+#define OMAP2420_EN_I2C1                                (1 << 19)
+
+/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
+#define OMAP2430_EN_MCBSP5_SHIFT                        5
+#define OMAP2430_EN_MCBSP5                              (1 << 5)
+#define OMAP2430_EN_MCBSP4_SHIFT                        4
+#define OMAP2430_EN_MCBSP4                              (1 << 4)
+#define OMAP2430_EN_MCBSP3_SHIFT                        3
+#define OMAP2430_EN_MCBSP3                              (1 << 3)
+#define OMAP24XX_EN_SSI_SHIFT                           1
+#define OMAP24XX_EN_SSI                                 (1 << 1)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP24XX_EN_MPU_WDT_SHIFT                       3
+#define OMAP24XX_EN_MPU_WDT                             (1 << 3)
+
+/* Bits specific to each register */
+
+/* CM_IDLEST_MPU */
+/* 2430 only */
+#define OMAP2430_ST_MPU                                 (1 << 0)
+
+/* CM_CLKSEL_MPU */
+#define OMAP24XX_CLKSEL_MPU_SHIFT                       0
+#define OMAP24XX_CLKSEL_MPU_MASK                        (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP24XX_AUTOSTATE_MPU                          (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits*/
+#define OMAP24XX_EN_TV_SHIFT                            2
+#define OMAP24XX_EN_TV                                  (1 << 2)
+#define OMAP24XX_EN_DSS2_SHIFT                          1
+#define OMAP24XX_EN_DSS2                                (1 << 1)
+#define OMAP24XX_EN_DSS1_SHIFT                          0
+#define OMAP24XX_EN_DSS1                                (1 << 0)
+
+/* CM_FCLKEN2_CORE specific bits */
+#define OMAP2430_EN_I2CHS2_SHIFT                        20
+#define OMAP2430_EN_I2CHS2                              (1 << 20)
+#define OMAP2430_EN_I2CHS1_SHIFT                        19
+#define OMAP2430_EN_I2CHS1                              (1 << 19)
+#define OMAP2430_EN_MMCHSDB2_SHIFT                      17
+#define OMAP2430_EN_MMCHSDB2                            (1 << 17)
+#define OMAP2430_EN_MMCHSDB1_SHIFT                      16
+#define OMAP2430_EN_MMCHSDB1                            (1 << 16)
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP24XX_EN_MAILBOXES_SHIFT                     30
+#define OMAP24XX_EN_MAILBOXES                           (1 << 30)
+#define OMAP24XX_EN_DSS_SHIFT                           0
+#define OMAP24XX_EN_DSS                                 (1 << 0)
+
+/* CM_ICLKEN2_CORE specific bits */
+
+/* CM_ICLKEN3_CORE */
+/* 2430 only */
+#define OMAP2430_EN_SDRC_SHIFT                          2
+#define OMAP2430_EN_SDRC                                (1 << 2)
+
+/* CM_ICLKEN4_CORE */
+#define OMAP24XX_EN_PKA_SHIFT                           4
+#define OMAP24XX_EN_PKA                                 (1 << 4)
+#define OMAP24XX_EN_AES_SHIFT                           3
+#define OMAP24XX_EN_AES                                 (1 << 3)
+#define OMAP24XX_EN_RNG_SHIFT                           2
+#define OMAP24XX_EN_RNG                                 (1 << 2)
+#define OMAP24XX_EN_SHA_SHIFT                           1
+#define OMAP24XX_EN_SHA                                 (1 << 1)
+#define OMAP24XX_EN_DES_SHIFT                           0
+#define OMAP24XX_EN_DES                                 (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP24XX_ST_MAILBOXES                           (1 << 30)
+#define OMAP24XX_ST_WDT4                                (1 << 29)
+#define OMAP2420_ST_WDT3                                (1 << 28)
+#define OMAP24XX_ST_MSPRO                               (1 << 27)
+#define OMAP24XX_ST_FAC                                 (1 << 25)
+#define OMAP2420_ST_EAC                                 (1 << 24)
+#define OMAP24XX_ST_HDQ                                 (1 << 23)
+#define OMAP24XX_ST_I2C2                                (1 << 20)
+#define OMAP24XX_ST_I2C1                                (1 << 19)
+#define OMAP24XX_ST_MCBSP2                              (1 << 16)
+#define OMAP24XX_ST_MCBSP1                              (1 << 15)
+#define OMAP24XX_ST_DSS                                 (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP2430_ST_MCBSP5                              (1 << 5)
+#define OMAP2430_ST_MCBSP4                              (1 << 4)
+#define OMAP2430_ST_MCBSP3                              (1 << 3)
+#define OMAP24XX_ST_SSI                                 (1 << 1)
+
+/* CM_IDLEST3_CORE */
+/* 2430 only */
+#define OMAP2430_ST_SDRC                                (1 << 2)
+
+/* CM_IDLEST4_CORE */
+#define OMAP24XX_ST_PKA                                 (1 << 4)
+#define OMAP24XX_ST_AES                                 (1 << 3)
+#define OMAP24XX_ST_RNG                                 (1 << 2)
+#define OMAP24XX_ST_SHA                                 (1 << 1)
+#define OMAP24XX_ST_DES                                 (1 << 0)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP24XX_AUTO_CAM                               (1 << 31)
+#define OMAP24XX_AUTO_MAILBOXES                         (1 << 30)
+#define OMAP24XX_AUTO_WDT4                              (1 << 29)
+#define OMAP2420_AUTO_WDT3                              (1 << 28)
+#define OMAP24XX_AUTO_MSPRO                             (1 << 27)
+#define OMAP2420_AUTO_MMC                               (1 << 26)
+#define OMAP24XX_AUTO_FAC                               (1 << 25)
+#define OMAP2420_AUTO_EAC                               (1 << 24)
+#define OMAP24XX_AUTO_HDQ                               (1 << 23)
+#define OMAP24XX_AUTO_UART2                             (1 << 22)
+#define OMAP24XX_AUTO_UART1                             (1 << 21)
+#define OMAP24XX_AUTO_I2C2                              (1 << 20)
+#define OMAP24XX_AUTO_I2C1                              (1 << 19)
+#define OMAP24XX_AUTO_MCSPI2                            (1 << 18)
+#define OMAP24XX_AUTO_MCSPI1                            (1 << 17)
+#define OMAP24XX_AUTO_MCBSP2                            (1 << 16)
+#define OMAP24XX_AUTO_MCBSP1                            (1 << 15)
+#define OMAP24XX_AUTO_GPT12                             (1 << 14)
+#define OMAP24XX_AUTO_GPT11                             (1 << 13)
+#define OMAP24XX_AUTO_GPT10                             (1 << 12)
+#define OMAP24XX_AUTO_GPT9                              (1 << 11)
+#define OMAP24XX_AUTO_GPT8                              (1 << 10)
+#define OMAP24XX_AUTO_GPT7                              (1 << 9)
+#define OMAP24XX_AUTO_GPT6                              (1 << 8)
+#define OMAP24XX_AUTO_GPT5                              (1 << 7)
+#define OMAP24XX_AUTO_GPT4                              (1 << 6)
+#define OMAP24XX_AUTO_GPT3                              (1 << 5)
+#define OMAP24XX_AUTO_GPT2                              (1 << 4)
+#define OMAP2420_AUTO_VLYNQ                             (1 << 3)
+#define OMAP24XX_AUTO_DSS                               (1 << 0)
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP2430_AUTO_MDM_INTC                          (1 << 11)
+#define OMAP2430_AUTO_GPIO5                             (1 << 10)
+#define OMAP2430_AUTO_MCSPI3                            (1 << 9)
+#define OMAP2430_AUTO_MMCHS2                            (1 << 8)
+#define OMAP2430_AUTO_MMCHS1                            (1 << 7)
+#define OMAP2430_AUTO_USBHS                             (1 << 6)
+#define OMAP2430_AUTO_MCBSP5                            (1 << 5)
+#define OMAP2430_AUTO_MCBSP4                            (1 << 4)
+#define OMAP2430_AUTO_MCBSP3                            (1 << 3)
+#define OMAP24XX_AUTO_UART3                             (1 << 2)
+#define OMAP24XX_AUTO_SSI                               (1 << 1)
+#define OMAP24XX_AUTO_USB                               (1 << 0)
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC                              (1 << 2)
+#define OMAP24XX_AUTO_GPMC                              (1 << 1)
+#define OMAP24XX_AUTO_SDMA                              (1 << 0)
+
+/* CM_AUTOIDLE4_CORE */
+#define OMAP24XX_AUTO_PKA                               (1 << 4)
+#define OMAP24XX_AUTO_AES                               (1 << 3)
+#define OMAP24XX_AUTO_RNG                               (1 << 2)
+#define OMAP24XX_AUTO_SHA                               (1 << 1)
+#define OMAP24XX_AUTO_DES                               (1 << 0)
+
+/* CM_CLKSEL1_CORE */
+#define OMAP24XX_CLKSEL_USB_SHIFT                       25
+#define OMAP24XX_CLKSEL_USB_MASK                        (0x7 << 25)
+#define OMAP24XX_CLKSEL_SSI_SHIFT                       20
+#define OMAP24XX_CLKSEL_SSI_MASK                        (0x1f << 20)
+#define OMAP2420_CLKSEL_VLYNQ_SHIFT                     15
+#define OMAP2420_CLKSEL_VLYNQ_MASK                      (0x1f << 15)
+#define OMAP24XX_CLKSEL_DSS2_SHIFT                      13
+#define OMAP24XX_CLKSEL_DSS2_MASK                       (0x1 << 13)
+#define OMAP24XX_CLKSEL_DSS1_SHIFT                      8
+#define OMAP24XX_CLKSEL_DSS1_MASK                       (0x1f << 8)
+#define OMAP24XX_CLKSEL_L4_SHIFT                        5
+#define OMAP24XX_CLKSEL_L4_MASK                         (0x3 << 5)
+#define OMAP24XX_CLKSEL_L3_SHIFT                        0
+#define OMAP24XX_CLKSEL_L3_MASK                         (0x1f << 0)
+
+/* CM_CLKSEL2_CORE */
+#define OMAP24XX_CLKSEL_GPT12_SHIFT                     22
+#define OMAP24XX_CLKSEL_GPT12_MASK                      (0x3 << 22)
+#define OMAP24XX_CLKSEL_GPT11_SHIFT                     20
+#define OMAP24XX_CLKSEL_GPT11_MASK                      (0x3 << 20)
+#define OMAP24XX_CLKSEL_GPT10_SHIFT                     18
+#define OMAP24XX_CLKSEL_GPT10_MASK                      (0x3 << 18)
+#define OMAP24XX_CLKSEL_GPT9_SHIFT                      16
+#define OMAP24XX_CLKSEL_GPT9_MASK                       (0x3 << 16)
+#define OMAP24XX_CLKSEL_GPT8_SHIFT                      14
+#define OMAP24XX_CLKSEL_GPT8_MASK                       (0x3 << 14)
+#define OMAP24XX_CLKSEL_GPT7_SHIFT                      12
+#define OMAP24XX_CLKSEL_GPT7_MASK                       (0x3 << 12)
+#define OMAP24XX_CLKSEL_GPT6_SHIFT                      10
+#define OMAP24XX_CLKSEL_GPT6_MASK                       (0x3 << 10)
+#define OMAP24XX_CLKSEL_GPT5_SHIFT                      8
+#define OMAP24XX_CLKSEL_GPT5_MASK                       (0x3 << 8)
+#define OMAP24XX_CLKSEL_GPT4_SHIFT                      6
+#define OMAP24XX_CLKSEL_GPT4_MASK                       (0x3 << 6)
+#define OMAP24XX_CLKSEL_GPT3_SHIFT                      4
+#define OMAP24XX_CLKSEL_GPT3_MASK                       (0x3 << 4)
+#define OMAP24XX_CLKSEL_GPT2_SHIFT                      2
+#define OMAP24XX_CLKSEL_GPT2_MASK                       (0x3 << 2)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP24XX_AUTOSTATE_DSS                          (1 << 2)
+#define OMAP24XX_AUTOSTATE_L4                           (1 << 1)
+#define OMAP24XX_AUTOSTATE_L3                           (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP24XX_EN_3D_SHIFT                            2
+#define OMAP24XX_EN_3D                                  (1 << 2)
+#define OMAP24XX_EN_2D_SHIFT                            1
+#define OMAP24XX_EN_2D                                  (1 << 1)
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP24XX_AUTOSTATE_GFX                          (1 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP2430_EN_ICR_SHIFT                           6
+#define OMAP2430_EN_ICR                                 (1 << 6)
+#define OMAP24XX_EN_OMAPCTRL_SHIFT                      5
+#define OMAP24XX_EN_OMAPCTRL                            (1 << 5)
+#define OMAP24XX_EN_WDT1_SHIFT                          4
+#define OMAP24XX_EN_WDT1                                (1 << 4)
+#define OMAP24XX_EN_32KSYNC_SHIFT                       1
+#define OMAP24XX_EN_32KSYNC                             (1 << 1)
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP2430_ST_ICR                                 (1 << 6)
+#define OMAP24XX_ST_OMAPCTRL                            (1 << 5)
+#define OMAP24XX_ST_WDT1                                (1 << 4)
+#define OMAP24XX_ST_MPU_WDT                             (1 << 3)
+#define OMAP24XX_ST_32KSYNC                             (1 << 1)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP24XX_AUTO_OMAPCTRL                          (1 << 5)
+#define OMAP24XX_AUTO_WDT1                              (1 << 4)
+#define OMAP24XX_AUTO_MPU_WDT                           (1 << 3)
+#define OMAP24XX_AUTO_GPIOS                             (1 << 2)
+#define OMAP24XX_AUTO_32KSYNC                           (1 << 1)
+#define OMAP24XX_AUTO_GPT1                              (1 << 0)
+
+/* CM_CLKSEL_WKUP */
+#define OMAP24XX_CLKSEL_GPT1_SHIFT                      0
+#define OMAP24XX_CLKSEL_GPT1_MASK                       (0x3 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP24XX_EN_54M_PLL_SHIFT                       6
+#define OMAP24XX_EN_54M_PLL_MASK                        (0x3 << 6)
+#define OMAP24XX_EN_96M_PLL_SHIFT                       2
+#define OMAP24XX_EN_96M_PLL_MASK                        (0x3 << 2)
+#define OMAP24XX_EN_DPLL_SHIFT                          0
+#define OMAP24XX_EN_DPLL_MASK                           (0x3 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP24XX_ST_54M_APLL                            (1 << 9)
+#define OMAP24XX_ST_96M_APLL                            (1 << 8)
+#define OMAP24XX_ST_54M_CLK                             (1 << 6)
+#define OMAP24XX_ST_12M_CLK                             (1 << 5)
+#define OMAP24XX_ST_48M_CLK                             (1 << 4)
+#define OMAP24XX_ST_96M_CLK                             (1 << 2)
+#define OMAP24XX_ST_CORE_CLK_SHIFT                      0
+#define OMAP24XX_ST_CORE_CLK_MASK                       (0x3 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP24XX_AUTO_54M_SHIFT                         6
+#define OMAP24XX_AUTO_54M_MASK                          (0x3 << 6)
+#define OMAP24XX_AUTO_96M_SHIFT                         2
+#define OMAP24XX_AUTO_96M_MASK                          (0x3 << 2)
+#define OMAP24XX_AUTO_DPLL_SHIFT                        0
+#define OMAP24XX_AUTO_DPLL_MASK                         (0x3 << 0)
+
+/* CM_CLKSEL1_PLL */
+#define OMAP2430_MAXDPLLFASTLOCK_SHIFT                  28
+#define OMAP2430_MAXDPLLFASTLOCK_MASK                   (0x7 << 28)
+#define OMAP24XX_APLLS_CLKIN_SHIFT                      23
+#define OMAP24XX_APLLS_CLKIN_MASK                       (0x7 << 23)
+#define OMAP24XX_DPLL_MULT_SHIFT                        12
+#define OMAP24XX_DPLL_MULT_MASK                         (0x3ff << 12)
+#define OMAP24XX_DPLL_DIV_SHIFT                         8
+#define OMAP24XX_DPLL_DIV_MASK                          (0xf << 8)
+#define OMAP24XX_54M_SOURCE_SHIFT                       5
+#define OMAP24XX_54M_SOURCE                             (1 << 5)
+#define OMAP2430_96M_SOURCE_SHIFT                       4
+#define OMAP2430_96M_SOURCE                             (1 << 4)
+#define OMAP24XX_48M_SOURCE_SHIFT                       3
+#define OMAP24XX_48M_SOURCE                             (1 << 3)
+#define OMAP2430_ALTCLK_SOURCE_SHIFT                    0
+#define OMAP2430_ALTCLK_SOURCE_MASK                     (0x7 << 0)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP24XX_CORE_CLK_SRC_SHIFT                     0
+#define OMAP24XX_CORE_CLK_SRC_MASK                      (0x3 << 0)
+
+/* CM_FCLKEN_DSP */
+#define OMAP2420_EN_IVA_COP_SHIFT                       10
+#define OMAP2420_EN_IVA_COP                             (1 << 10)
+#define OMAP2420_EN_IVA_MPU_SHIFT                       8
+#define OMAP2420_EN_IVA_MPU                             (1 << 8)
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT             0
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP                   (1 << 0)
+
+/* CM_ICLKEN_DSP */
+#define OMAP2420_EN_DSP_IPI_SHIFT                       1
+#define OMAP2420_EN_DSP_IPI                             (1 << 1)
+
+/* CM_IDLEST_DSP */
+#define OMAP2420_ST_IVA                                 (1 << 8)
+#define OMAP2420_ST_IPI                                 (1 << 1)
+#define OMAP24XX_ST_DSP                                 (1 << 0)
+
+/* CM_AUTOIDLE_DSP */
+#define OMAP2420_AUTO_DSP_IPI                           (1 << 1)
+
+/* CM_CLKSEL_DSP */
+#define OMAP2420_SYNC_IVA                               (1 << 13)
+#define OMAP2420_CLKSEL_IVA_SHIFT                       8
+#define OMAP2420_CLKSEL_IVA_MASK                        (0x1f << 8)
+#define OMAP24XX_SYNC_DSP                               (1 << 7)
+#define OMAP24XX_CLKSEL_DSP_IF_SHIFT                    5
+#define OMAP24XX_CLKSEL_DSP_IF_MASK                     (0x3 << 5)
+#define OMAP24XX_CLKSEL_DSP_SHIFT                       0
+#define OMAP24XX_CLKSEL_DSP_MASK                        (0x1f << 0)
+
+/* CM_CLKSTCTRL_DSP */
+#define OMAP2420_AUTOSTATE_IVA                          (1 << 8)
+#define OMAP24XX_AUTOSTATE_DSP                          (1 << 0)
+
+/* CM_FCLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_EN_OSC_SHIFT                           1
+#define OMAP2430_EN_OSC                                 (1 << 1)
+
+/* CM_ICLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT             0
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM                   (1 << 0)
+
+/* CM_IDLEST_MDM specific bits */
+/* 2430 only */
+
+/* CM_AUTOIDLE_MDM */
+/* 2430 only */
+#define OMAP2430_AUTO_OSC                               (1 << 1)
+#define OMAP2430_AUTO_MDM                               (1 << 0)
+
+/* CM_CLKSEL_MDM */
+/* 2430 only */
+#define OMAP2430_SYNC_MDM                               (1 << 4)
+#define OMAP2430_CLKSEL_MDM_SHIFT                       0
+#define OMAP2430_CLKSEL_MDM_MASK                        (0xf << 0)
+
+/* CM_CLKSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_AUTOSTATE_MDM                          (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
new file mode 100644
index 000000000000..9249129a5f46
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -0,0 +1,673 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Clock Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP3430ES2_EN_MMC3_MASK                        (1 << 30)
+#define OMAP3430ES2_EN_MMC3_SHIFT                       30
+#define OMAP3430_EN_MSPRO                               (1 << 23)
+#define OMAP3430_EN_MSPRO_SHIFT                         23
+#define OMAP3430_EN_HDQ                                 (1 << 22)
+#define OMAP3430_EN_HDQ_SHIFT                           22
+#define OMAP3430ES1_EN_FSHOSTUSB                        (1 << 5)
+#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT                  5
+#define OMAP3430ES1_EN_D2D                              (1 << 3)
+#define OMAP3430ES1_EN_D2D_SHIFT                        3
+#define OMAP3430_EN_SSI                                 (1 << 0)
+#define OMAP3430_EN_SSI_SHIFT                           0
+
+/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
+#define OMAP3430ES2_EN_USBTLL_SHIFT                     2
+#define OMAP3430ES2_EN_USBTLL_MASK                      (1 << 2)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP3430_EN_WDT2                                (1 << 5)
+#define OMAP3430_EN_WDT2_SHIFT                          5
+
+/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
+#define OMAP3430_EN_CAM                                 (1 << 0)
+#define OMAP3430_EN_CAM_SHIFT                           0
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
+#define OMAP3430_EN_WDT3                                (1 << 12)
+#define OMAP3430_EN_WDT3_SHIFT                          12
+
+/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
+#define OMAP3430_OVERRIDE_ENABLE                        (1 << 19)
+
+
+/* Bits specific to each register */
+
+/* CM_FCLKEN_IVA2 */
+#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2                 (1 << 0)
+
+/* CM_CLKEN_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT               8
+#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK                (0x3 << 8)
+#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT                4
+#define OMAP3430_IVA2_DPLL_FREQSEL_MASK                 (0xf << 4)
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT          3
+#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK           (1 << 3)
+#define OMAP3430_EN_IVA2_DPLL_SHIFT                     0
+#define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
+
+/* CM_IDLEST_IVA2 */
+#define OMAP3430_ST_IVA2                                (1 << 0)
+
+/* CM_IDLEST_PLL_IVA2 */
+#define OMAP3430_ST_IVA2_CLK                            (1 << 0)
+
+/* CM_AUTOIDLE_PLL_IVA2 */
+#define OMAP3430_AUTO_IVA2_DPLL_SHIFT                   0
+#define OMAP3430_AUTO_IVA2_DPLL_MASK                    (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_IVA2 */
+#define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
+#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x3 << 19)
+#define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
+#define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
+#define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
+#define OMAP3430_IVA2_DPLL_DIV_MASK                     (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_IVA2 */
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT             0
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK              (0x1f << 0)
+
+/* CM_CLKSTCTRL_IVA2 */
+#define OMAP3430_CLKTRCTRL_IVA2_SHIFT                   0
+#define OMAP3430_CLKTRCTRL_IVA2_MASK                    (0x3 << 0)
+
+/* CM_CLKSTST_IVA2 */
+#define OMAP3430_CLKACTIVITY_IVA2                       (1 << 0)
+
+/* CM_REVISION specific bits */
+
+/* CM_SYSCONFIG specific bits */
+
+/* CM_CLKEN_PLL_MPU */
+#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT                8
+#define OMAP3430_MPU_DPLL_RAMPTIME_MASK                 (0x3 << 8)
+#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT                 4
+#define OMAP3430_MPU_DPLL_FREQSEL_MASK                  (0xf << 4)
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT           3
+#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK            (1 << 3)
+#define OMAP3430_EN_MPU_DPLL_SHIFT                      0
+#define OMAP3430_EN_MPU_DPLL_MASK                       (0x7 << 0)
+
+/* CM_IDLEST_MPU */
+#define OMAP3430_ST_MPU                                 (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK                             (1 << 0)
+#define OMAP3430_ST_IVA2_CLK_MASK                       (1 << 0)
+
+/* CM_IDLEST_PLL_MPU */
+#define OMAP3430_ST_MPU_CLK_MASK                        (1 << 0)
+
+/* CM_AUTOIDLE_PLL_MPU */
+#define OMAP3430_AUTO_MPU_DPLL_SHIFT                    0
+#define OMAP3430_AUTO_MPU_DPLL_MASK                     (0x7 << 0)
+
+/* CM_CLKSEL1_PLL_MPU */
+#define OMAP3430_MPU_CLK_SRC_SHIFT                      19
+#define OMAP3430_MPU_CLK_SRC_MASK                       (0x3 << 19)
+#define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
+#define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
+#define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
+#define OMAP3430_MPU_DPLL_DIV_MASK                      (0x7f << 0)
+
+/* CM_CLKSEL2_PLL_MPU */
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT              0
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK               (0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP3430_CLKTRCTRL_MPU_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_MPU_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_MPU */
+#define OMAP3430_CLKACTIVITY_MPU                        (1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits */
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP3430_EN_ICR                                 (1 << 29)
+#define OMAP3430_EN_ICR_SHIFT                           29
+#define OMAP3430_EN_AES2                                (1 << 28)
+#define OMAP3430_EN_AES2_SHIFT                          28
+#define OMAP3430_EN_SHA12                               (1 << 27)
+#define OMAP3430_EN_SHA12_SHIFT                         27
+#define OMAP3430_EN_DES2                                (1 << 26)
+#define OMAP3430_EN_DES2_SHIFT                          26
+#define OMAP3430ES1_EN_FAC                              (1 << 8)
+#define OMAP3430ES1_EN_FAC_SHIFT                        8
+#define OMAP3430_EN_MAILBOXES                           (1 << 7)
+#define OMAP3430_EN_MAILBOXES_SHIFT                     7
+#define OMAP3430_EN_OMAPCTRL                            (1 << 6)
+#define OMAP3430_EN_OMAPCTRL_SHIFT                      6
+#define OMAP3430_EN_SDRC                                (1 << 1)
+#define OMAP3430_EN_SDRC_SHIFT                          1
+
+/* CM_ICLKEN2_CORE */
+#define OMAP3430_EN_PKA                                 (1 << 4)
+#define OMAP3430_EN_PKA_SHIFT                           4
+#define OMAP3430_EN_AES1                                (1 << 3)
+#define OMAP3430_EN_AES1_SHIFT                          3
+#define OMAP3430_EN_RNG                                 (1 << 2)
+#define OMAP3430_EN_RNG_SHIFT                           2
+#define OMAP3430_EN_SHA11                               (1 << 1)
+#define OMAP3430_EN_SHA11_SHIFT                         1
+#define OMAP3430_EN_DES1                                (1 << 0)
+#define OMAP3430_EN_DES1_SHIFT                          0
+
+/* CM_FCLKEN3_CORE specific bits */
+#define OMAP3430ES2_EN_TS_SHIFT                         1
+#define OMAP3430ES2_EN_TS_MASK                          (1 << 1)
+#define OMAP3430ES2_EN_CPEFUSE_SHIFT                    0
+#define OMAP3430ES2_EN_CPEFUSE_MASK                     (1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP3430_ST_ICR                                 (1 << 29)
+#define OMAP3430_ST_AES2                                (1 << 28)
+#define OMAP3430_ST_SHA12                               (1 << 27)
+#define OMAP3430_ST_DES2                                (1 << 26)
+#define OMAP3430_ST_MSPRO                               (1 << 23)
+#define OMAP3430_ST_HDQ                                 (1 << 22)
+#define OMAP3430ES1_ST_FAC                              (1 << 8)
+#define OMAP3430ES1_ST_MAILBOXES                        (1 << 7)
+#define OMAP3430_ST_OMAPCTRL                            (1 << 6)
+#define OMAP3430_ST_SDMA                                (1 << 2)
+#define OMAP3430_ST_SDRC                                (1 << 1)
+#define OMAP3430_ST_SSI                                 (1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP3430_ST_PKA                                 (1 << 4)
+#define OMAP3430_ST_AES1                                (1 << 3)
+#define OMAP3430_ST_RNG                                 (1 << 2)
+#define OMAP3430_ST_SHA11                               (1 << 1)
+#define OMAP3430_ST_DES1                                (1 << 0)
+
+/* CM_IDLEST3_CORE */
+#define OMAP3430ES2_ST_USBTLL_SHIFT                     2
+#define OMAP3430ES2_ST_USBTLL_MASK                      (1 << 2)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_AES2                              (1 << 28)
+#define OMAP3430_AUTO_AES2_SHIFT                        28
+#define OMAP3430_AUTO_SHA12                             (1 << 27)
+#define OMAP3430_AUTO_SHA12_SHIFT                       27
+#define OMAP3430_AUTO_DES2                              (1 << 26)
+#define OMAP3430_AUTO_DES2_SHIFT                        26
+#define OMAP3430_AUTO_MMC2                              (1 << 25)
+#define OMAP3430_AUTO_MMC2_SHIFT                        25
+#define OMAP3430_AUTO_MMC1                              (1 << 24)
+#define OMAP3430_AUTO_MMC1_SHIFT                        24
+#define OMAP3430_AUTO_MSPRO                             (1 << 23)
+#define OMAP3430_AUTO_MSPRO_SHIFT                       23
+#define OMAP3430_AUTO_HDQ                               (1 << 22)
+#define OMAP3430_AUTO_HDQ_SHIFT                         22
+#define OMAP3430_AUTO_MCSPI4                            (1 << 21)
+#define OMAP3430_AUTO_MCSPI4_SHIFT                      21
+#define OMAP3430_AUTO_MCSPI3                            (1 << 20)
+#define OMAP3430_AUTO_MCSPI3_SHIFT                      20
+#define OMAP3430_AUTO_MCSPI2                            (1 << 19)
+#define OMAP3430_AUTO_MCSPI2_SHIFT                      19
+#define OMAP3430_AUTO_MCSPI1                            (1 << 18)
+#define OMAP3430_AUTO_MCSPI1_SHIFT                      18
+#define OMAP3430_AUTO_I2C3                              (1 << 17)
+#define OMAP3430_AUTO_I2C3_SHIFT                        17
+#define OMAP3430_AUTO_I2C2                              (1 << 16)
+#define OMAP3430_AUTO_I2C2_SHIFT                        16
+#define OMAP3430_AUTO_I2C1                              (1 << 15)
+#define OMAP3430_AUTO_I2C1_SHIFT                        15
+#define OMAP3430_AUTO_UART2                             (1 << 14)
+#define OMAP3430_AUTO_UART2_SHIFT                       14
+#define OMAP3430_AUTO_UART1                             (1 << 13)
+#define OMAP3430_AUTO_UART1_SHIFT                       13
+#define OMAP3430_AUTO_GPT11                             (1 << 12)
+#define OMAP3430_AUTO_GPT11_SHIFT                       12
+#define OMAP3430_AUTO_GPT10                             (1 << 11)
+#define OMAP3430_AUTO_GPT10_SHIFT                       11
+#define OMAP3430_AUTO_MCBSP5                            (1 << 10)
+#define OMAP3430_AUTO_MCBSP5_SHIFT                      10
+#define OMAP3430_AUTO_MCBSP1                            (1 << 9)
+#define OMAP3430_AUTO_MCBSP1_SHIFT                      9
+#define OMAP3430ES1_AUTO_FAC                            (1 << 8)
+#define OMAP3430ES1_AUTO_FAC_SHIFT                      8
+#define OMAP3430_AUTO_MAILBOXES                         (1 << 7)
+#define OMAP3430_AUTO_MAILBOXES_SHIFT                   7
+#define OMAP3430_AUTO_OMAPCTRL                          (1 << 6)
+#define OMAP3430_AUTO_OMAPCTRL_SHIFT                    6
+#define OMAP3430ES1_AUTO_FSHOSTUSB                      (1 << 5)
+#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT                5
+#define OMAP3430_AUTO_HSOTGUSB                          (1 << 4)
+#define OMAP3430_AUTO_HSOTGUSB_SHIFT                    4
+#define OMAP3430ES1_AUTO_D2D                            (1 << 3)
+#define OMAP3430ES1_AUTO_D2D_SHIFT                      3
+#define OMAP3430_AUTO_SSI                               (1 << 0)
+#define OMAP3430_AUTO_SSI_SHIFT                         0
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP3430_AUTO_PKA                               (1 << 4)
+#define OMAP3430_AUTO_PKA_SHIFT                         4
+#define OMAP3430_AUTO_AES1                              (1 << 3)
+#define OMAP3430_AUTO_AES1_SHIFT                        3
+#define OMAP3430_AUTO_RNG                               (1 << 2)
+#define OMAP3430_AUTO_RNG_SHIFT                         2
+#define OMAP3430_AUTO_SHA11                             (1 << 1)
+#define OMAP3430_AUTO_SHA11_SHIFT                       1
+#define OMAP3430_AUTO_DES1                              (1 << 0)
+#define OMAP3430_AUTO_DES1_SHIFT                        0
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP3430ES2_AUTO_USBTLL_SHIFT                   2
+#define OMAP3430ES2_AUTO_USBTLL_MASK                    (1 << 2)
+
+/* CM_CLKSEL_CORE */
+#define OMAP3430_CLKSEL_SSI_SHIFT                       8
+#define OMAP3430_CLKSEL_SSI_MASK                        (0xf << 8)
+#define OMAP3430_CLKSEL_GPT11_MASK                      (1 << 7)
+#define OMAP3430_CLKSEL_GPT11_SHIFT                     7
+#define OMAP3430_CLKSEL_GPT10_MASK                      (1 << 6)
+#define OMAP3430_CLKSEL_GPT10_SHIFT                     6
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT              4
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK               (0x3 << 4)
+#define OMAP3430_CLKSEL_L4_SHIFT                        2
+#define OMAP3430_CLKSEL_L4_MASK                         (0x3 << 2)
+#define OMAP3430_CLKSEL_L3_SHIFT                        0
+#define OMAP3430_CLKSEL_L3_MASK                         (0x3 << 0)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT                 4
+#define OMAP3430ES1_CLKTRCTRL_D2D_MASK                  (0x3 << 4)
+#define OMAP3430_CLKTRCTRL_L4_SHIFT                     2
+#define OMAP3430_CLKTRCTRL_L4_MASK                      (0x3 << 2)
+#define OMAP3430_CLKTRCTRL_L3_SHIFT                     0
+#define OMAP3430_CLKTRCTRL_L3_MASK                      (0x3 << 0)
+
+/* CM_CLKSTST_CORE */
+#define OMAP3430ES1_CLKACTIVITY_D2D                     (1 << 2)
+#define OMAP3430_CLKACTIVITY_L4                         (1 << 1)
+#define OMAP3430_CLKACTIVITY_L3                         (1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP3430ES1_EN_3D                               (1 << 2)
+#define OMAP3430ES1_EN_3D_SHIFT                         2
+#define OMAP3430ES1_EN_2D                               (1 << 1)
+#define OMAP3430ES1_EN_2D_SHIFT                         1
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_SLEEPDEP_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT                 0
+#define OMAP3430ES1_CLKTRCTRL_GFX_MASK                  (0x3 << 0)
+
+/* CM_CLKSTST_GFX */
+#define OMAP3430ES1_CLKACTIVITY_GFX                     (1 << 0)
+
+/* CM_FCLKEN_SGX */
+#define OMAP3430ES2_EN_SGX_SHIFT                        1
+#define OMAP3430ES2_EN_SGX_MASK                         (1 << 1)
+
+/* CM_CLKSEL_SGX */
+#define OMAP3430ES2_CLKSEL_SGX_SHIFT                    0
+#define OMAP3430ES2_CLKSEL_SGX_MASK                     (0x7 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+#define OMAP3430ES2_EN_USIMOCP_SHIFT                    9
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP3430_EN_WDT1                                (1 << 4)
+#define OMAP3430_EN_WDT1_SHIFT                          4
+#define OMAP3430_EN_32KSYNC                             (1 << 2)
+#define OMAP3430_EN_32KSYNC_SHIFT                       2
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP3430_ST_WDT2                                (1 << 5)
+#define OMAP3430_ST_WDT1                                (1 << 4)
+#define OMAP3430_ST_32KSYNC                             (1 << 2)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP3430_AUTO_WDT2                              (1 << 5)
+#define OMAP3430_AUTO_WDT2_SHIFT                        5
+#define OMAP3430_AUTO_WDT1                              (1 << 4)
+#define OMAP3430_AUTO_WDT1_SHIFT                        4
+#define OMAP3430_AUTO_GPIO1                             (1 << 3)
+#define OMAP3430_AUTO_GPIO1_SHIFT                       3
+#define OMAP3430_AUTO_32KSYNC                           (1 << 2)
+#define OMAP3430_AUTO_32KSYNC_SHIFT                     2
+#define OMAP3430_AUTO_GPT12                             (1 << 1)
+#define OMAP3430_AUTO_GPT12_SHIFT                       1
+#define OMAP3430_AUTO_GPT1                              (1 << 0)
+#define OMAP3430_AUTO_GPT1_SHIFT                        0
+
+/* CM_CLKSEL_WKUP */
+#define OMAP3430ES2_CLKSEL_USIMOCP_MASK                 (0xf << 3)
+#define OMAP3430_CLKSEL_RM_SHIFT                        1
+#define OMAP3430_CLKSEL_RM_MASK                         (0x3 << 1)
+#define OMAP3430_CLKSEL_GPT1_SHIFT                      0
+#define OMAP3430_CLKSEL_GPT1_MASK                       (1 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT                 31
+#define OMAP3430_PWRDN_CAM_SHIFT                        30
+#define OMAP3430_PWRDN_DSS1_SHIFT                       29
+#define OMAP3430_PWRDN_TV_SHIFT                         28
+#define OMAP3430_PWRDN_96M_SHIFT                        27
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT             24
+#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK              (0x3 << 24)
+#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT              20
+#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK               (0xf << 20)
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT        19
+#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK         (1 << 19)
+#define OMAP3430_EN_PERIPH_DPLL_SHIFT                   16
+#define OMAP3430_EN_PERIPH_DPLL_MASK                    (0x7 << 16)
+#define OMAP3430_PWRDN_EMU_CORE_SHIFT                   12
+#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT               8
+#define OMAP3430_CORE_DPLL_RAMPTIME_MASK                (0x3 << 8)
+#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT                4
+#define OMAP3430_CORE_DPLL_FREQSEL_MASK                 (0xf << 4)
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT          3
+#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK           (1 << 3)
+#define OMAP3430_EN_CORE_DPLL_SHIFT                     0
+#define OMAP3430_EN_CORE_DPLL_MASK                      (0x7 << 0)
+
+/* CM_CLKEN2_PLL */
+#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT                10
+#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK          (0x3 << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT          4
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK           (0xf << 4)
+#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT    3
+#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT               0
+#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK                (0x7 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP3430_ST_54M_CLK                             (1 << 5)
+#define OMAP3430_ST_12M_CLK                             (1 << 4)
+#define OMAP3430_ST_48M_CLK                             (1 << 3)
+#define OMAP3430_ST_96M_CLK                             (1 << 2)
+#define OMAP3430_ST_PERIPH_CLK                          (1 << 1)
+#define OMAP3430_ST_CORE_CLK                            (1 << 0)
+
+/* CM_IDLEST2_CKGEN */
+#define OMAP3430ES2_ST_120M_CLK_SHIFT                   1
+#define OMAP3430ES2_ST_120M_CLK_MASK                    (1 << 1)
+#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT                0
+#define OMAP3430ES2_ST_PERIPH2_CLK_MASK                 (1 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT                 3
+#define OMAP3430_AUTO_PERIPH_DPLL_MASK                  (0x7 << 3)
+#define OMAP3430_AUTO_CORE_DPLL_SHIFT                   0
+#define OMAP3430_AUTO_CORE_DPLL_MASK                    (0x7 << 0)
+
+/* CM_CLKSEL1_PLL */
+/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT             27
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK              (0x1f << 27)
+#define OMAP3430_CORE_DPLL_MULT_SHIFT                   16
+#define OMAP3430_CORE_DPLL_MULT_MASK                    (0x7ff << 16)
+#define OMAP3430_CORE_DPLL_DIV_SHIFT                    8
+#define OMAP3430_CORE_DPLL_DIV_MASK                     (0x7f << 8)
+#define OMAP3430_SOURCE_54M                             (1 << 5)
+#define OMAP3430_SOURCE_48M                             (1 << 3)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP3430_PERIPH_DPLL_MULT_SHIFT                 8
+#define OMAP3430_PERIPH_DPLL_MULT_MASK                  (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_DIV_SHIFT                  0
+#define OMAP3430_PERIPH_DPLL_DIV_MASK                   (0x7f << 0)
+
+/* CM_CLKSEL3_PLL */
+#define OMAP3430_DIV_96M_SHIFT                          0
+#define OMAP3430_DIV_96M_MASK                           (0x1f << 0)
+
+/* CM_CLKSEL4_PLL */
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT             8
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK              (0x7ff << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT              0
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK               (0x7f << 0)
+
+/* CM_CLKSEL5_PLL */
+#define OMAP3430ES2_DIV_120M_SHIFT                      0
+#define OMAP3430ES2_DIV_120M_MASK                       (0x1f << 0)
+
+/* CM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT2_EN_SHIFT                       7
+#define OMAP3430_CLKOUT2_EN                             (1 << 7)
+#define OMAP3430_CLKOUT2_DIV_SHIFT                      3
+#define OMAP3430_CLKOUT2_DIV_MASK                       (0x7 << 3)
+#define OMAP3430_CLKOUT2SOURCE_SHIFT                    0
+#define OMAP3430_CLKOUT2SOURCE_MASK                     (0x3 << 0)
+
+/* CM_FCLKEN_DSS */
+#define OMAP3430_EN_TV                                  (1 << 2)
+#define OMAP3430_EN_TV_SHIFT                            2
+#define OMAP3430_EN_DSS2                                (1 << 1)
+#define OMAP3430_EN_DSS2_SHIFT                          1
+#define OMAP3430_EN_DSS1                                (1 << 0)
+#define OMAP3430_EN_DSS1_SHIFT                          0
+
+/* CM_ICLKEN_DSS */
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS                   (1 << 0)
+#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT             0
+
+/* CM_IDLEST_DSS */
+#define OMAP3430_ST_DSS                                 (1 << 0)
+
+/* CM_AUTOIDLE_DSS */
+#define OMAP3430_AUTO_DSS                               (1 << 0)
+#define OMAP3430_AUTO_DSS_SHIFT                         0
+
+/* CM_CLKSEL_DSS */
+#define OMAP3430_CLKSEL_TV_SHIFT                        8
+#define OMAP3430_CLKSEL_TV_MASK                         (0x1f << 8)
+#define OMAP3430_CLKSEL_DSS1_SHIFT                      0
+#define OMAP3430_CLKSEL_DSS1_MASK                       (0x1f << 0)
+
+/* CM_SLEEPDEP_DSS specific bits */
+
+/* CM_CLKSTCTRL_DSS */
+#define OMAP3430_CLKTRCTRL_DSS_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_DSS_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_DSS */
+#define OMAP3430_CLKACTIVITY_DSS                        (1 << 0)
+
+/* CM_FCLKEN_CAM specific bits */
+
+/* CM_ICLKEN_CAM specific bits */
+
+/* CM_IDLEST_CAM */
+#define OMAP3430_ST_CAM                                 (1 << 0)
+
+/* CM_AUTOIDLE_CAM */
+#define OMAP3430_AUTO_CAM                               (1 << 0)
+#define OMAP3430_AUTO_CAM_SHIFT                         0
+
+/* CM_CLKSEL_CAM */
+#define OMAP3430_CLKSEL_CAM_SHIFT                       0
+#define OMAP3430_CLKSEL_CAM_MASK                        (0x1f << 0)
+
+/* CM_SLEEPDEP_CAM specific bits */
+
+/* CM_CLKSTCTRL_CAM */
+#define OMAP3430_CLKTRCTRL_CAM_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_CAM_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_CAM */
+#define OMAP3430_CLKACTIVITY_CAM                        (1 << 0)
+
+/* CM_FCLKEN_PER specific bits */
+
+/* CM_ICLKEN_PER specific bits */
+
+/* CM_IDLEST_PER */
+#define OMAP3430_ST_WDT3                                (1 << 12)
+#define OMAP3430_ST_MCBSP4                              (1 << 2)
+#define OMAP3430_ST_MCBSP3                              (1 << 1)
+#define OMAP3430_ST_MCBSP2                              (1 << 0)
+
+/* CM_AUTOIDLE_PER */
+#define OMAP3430_AUTO_GPIO6                             (1 << 17)
+#define OMAP3430_AUTO_GPIO6_SHIFT                       17
+#define OMAP3430_AUTO_GPIO5                             (1 << 16)
+#define OMAP3430_AUTO_GPIO5_SHIFT                       16
+#define OMAP3430_AUTO_GPIO4                             (1 << 15)
+#define OMAP3430_AUTO_GPIO4_SHIFT                       15
+#define OMAP3430_AUTO_GPIO3                             (1 << 14)
+#define OMAP3430_AUTO_GPIO3_SHIFT                       14
+#define OMAP3430_AUTO_GPIO2                             (1 << 13)
+#define OMAP3430_AUTO_GPIO2_SHIFT                       13
+#define OMAP3430_AUTO_WDT3                              (1 << 12)
+#define OMAP3430_AUTO_WDT3_SHIFT                        12
+#define OMAP3430_AUTO_UART3                             (1 << 11)
+#define OMAP3430_AUTO_UART3_SHIFT                       11
+#define OMAP3430_AUTO_GPT9                              (1 << 10)
+#define OMAP3430_AUTO_GPT9_SHIFT                        10
+#define OMAP3430_AUTO_GPT8                              (1 << 9)
+#define OMAP3430_AUTO_GPT8_SHIFT                        9
+#define OMAP3430_AUTO_GPT7                              (1 << 8)
+#define OMAP3430_AUTO_GPT7_SHIFT                        8
+#define OMAP3430_AUTO_GPT6                              (1 << 7)
+#define OMAP3430_AUTO_GPT6_SHIFT                        7
+#define OMAP3430_AUTO_GPT5                              (1 << 6)
+#define OMAP3430_AUTO_GPT5_SHIFT                        6
+#define OMAP3430_AUTO_GPT4                              (1 << 5)
+#define OMAP3430_AUTO_GPT4_SHIFT                        5
+#define OMAP3430_AUTO_GPT3                              (1 << 4)
+#define OMAP3430_AUTO_GPT3_SHIFT                        4
+#define OMAP3430_AUTO_GPT2                              (1 << 3)
+#define OMAP3430_AUTO_GPT2_SHIFT                        3
+#define OMAP3430_AUTO_MCBSP4                            (1 << 2)
+#define OMAP3430_AUTO_MCBSP4_SHIFT                      2
+#define OMAP3430_AUTO_MCBSP3                            (1 << 1)
+#define OMAP3430_AUTO_MCBSP3_SHIFT                      1
+#define OMAP3430_AUTO_MCBSP2                            (1 << 0)
+#define OMAP3430_AUTO_MCBSP2_SHIFT                      0
+
+/* CM_CLKSEL_PER */
+#define OMAP3430_CLKSEL_GPT9_MASK                       (1 << 7)
+#define OMAP3430_CLKSEL_GPT9_SHIFT                      7
+#define OMAP3430_CLKSEL_GPT8_MASK                       (1 << 6)
+#define OMAP3430_CLKSEL_GPT8_SHIFT                      6
+#define OMAP3430_CLKSEL_GPT7_MASK                       (1 << 5)
+#define OMAP3430_CLKSEL_GPT7_SHIFT                      5
+#define OMAP3430_CLKSEL_GPT6_MASK                       (1 << 4)
+#define OMAP3430_CLKSEL_GPT6_SHIFT                      4
+#define OMAP3430_CLKSEL_GPT5_MASK                       (1 << 3)
+#define OMAP3430_CLKSEL_GPT5_SHIFT                      3
+#define OMAP3430_CLKSEL_GPT4_MASK                       (1 << 2)
+#define OMAP3430_CLKSEL_GPT4_SHIFT                      2
+#define OMAP3430_CLKSEL_GPT3_MASK                       (1 << 1)
+#define OMAP3430_CLKSEL_GPT3_SHIFT                      1
+#define OMAP3430_CLKSEL_GPT2_MASK                       (1 << 0)
+#define OMAP3430_CLKSEL_GPT2_SHIFT                      0
+
+/* CM_SLEEPDEP_PER specific bits */
+#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2                (1 << 2)
+
+/* CM_CLKSTCTRL_PER */
+#define OMAP3430_CLKTRCTRL_PER_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_PER_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_PER */
+#define OMAP3430_CLKACTIVITY_PER                        (1 << 0)
+
+/* CM_CLKSEL1_EMU */
+#define OMAP3430_DIV_DPLL4_SHIFT                        24
+#define OMAP3430_DIV_DPLL4_MASK                         (0x1f << 24)
+#define OMAP3430_DIV_DPLL3_SHIFT                        16
+#define OMAP3430_DIV_DPLL3_MASK                         (0x1f << 16)
+#define OMAP3430_CLKSEL_TRACECLK_SHIFT                  11
+#define OMAP3430_CLKSEL_TRACECLK_MASK                   (0x7 << 11)
+#define OMAP3430_CLKSEL_PCLK_SHIFT                      8
+#define OMAP3430_CLKSEL_PCLK_MASK                       (0x7 << 8)
+#define OMAP3430_CLKSEL_PCLKX2_SHIFT                    6
+#define OMAP3430_CLKSEL_PCLKX2_MASK                     (0x3 << 6)
+#define OMAP3430_CLKSEL_ATCLK_SHIFT                     4
+#define OMAP3430_CLKSEL_ATCLK_MASK                      (0x3 << 4)
+#define OMAP3430_TRACE_MUX_CTRL_SHIFT                   2
+#define OMAP3430_TRACE_MUX_CTRL_MASK                    (0x3 << 2)
+#define OMAP3430_MUX_CTRL_SHIFT                         0
+#define OMAP3430_MUX_CTRL_MASK                          (0x3 << 0)
+
+/* CM_CLKSTCTRL_EMU */
+#define OMAP3430_CLKTRCTRL_EMU_SHIFT                    0
+#define OMAP3430_CLKTRCTRL_EMU_MASK                     (0x3 << 0)
+
+/* CM_CLKSTST_EMU */
+#define OMAP3430_CLKACTIVITY_EMU                        (1 << 0)
+
+/* CM_CLKSEL2_EMU specific bits */
+#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT               8
+#define OMAP3430_CORE_DPLL_EMU_MULT_MASK                (0x7ff << 8)
+#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT                0
+#define OMAP3430_CORE_DPLL_EMU_DIV_MASK                 (0x7f << 0)
+
+/* CM_CLKSEL3_EMU specific bits */
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT             8
+#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK              (0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT              0
+#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK               (0x7f << 0)
+
+/* CM_POLCTRL */
+#define OMAP3430_CLKOUT2_POL                            (1 << 0)
+
+/* CM_IDLEST_NEON */
+#define OMAP3430_ST_NEON                                (1 << 0)
+
+/* CM_CLKSTCTRL_NEON */
+#define OMAP3430_CLKTRCTRL_NEON_SHIFT                   0
+#define OMAP3430_CLKTRCTRL_NEON_MASK                    (0x3 << 0)
+
+/* CM_FCLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST2_SHIFT                   1
+#define OMAP3430ES2_EN_USBHOST2_MASK                    (1 << 1)
+#define OMAP3430ES2_EN_USBHOST1_SHIFT                   0
+#define OMAP3430ES2_EN_USBHOST1_MASK                    (1 << 0)
+
+/* CM_ICLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST_SHIFT                    0
+#define OMAP3430ES2_EN_USBHOST_MASK                     (1 << 0)
+
+/* CM_IDLEST_USBHOST */
+
+/* CM_AUTOIDLE_USBHOST */
+#define OMAP3430ES2_AUTO_USBHOST_SHIFT                  0
+#define OMAP3430ES2_AUTO_USBHOST_MASK                   (1 << 0)
+
+/* CM_SLEEPDEP_USBHOST */
+#define OMAP3430ES2_EN_MPU_SHIFT                        1
+#define OMAP3430ES2_EN_MPU_MASK                         (1 << 1)
+#define OMAP3430ES2_EN_IVA2_SHIFT                       2
+#define OMAP3430ES2_EN_IVA2_MASK                        (1 << 2)
+
+/* CM_CLKSTCTRL_USBHOST */
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT             0
+#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK              (3 << 0)
+
+
+
+#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
new file mode 100644
index 000000000000..8489f3029fed
--- /dev/null
+++ b/arch/arm/mach-omap2/cm.h
@@ -0,0 +1,124 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
+#define __ARCH_ASM_MACH_OMAP2_CM_H
+
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#ifndef __ASSEMBLER__
+#define OMAP_CM_REGADDR(module, reg)                                    \
+        (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
+#else
+#define OMAP2420_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+#define OMAP34XX_CM_REGADDR(module, reg)                                \
+                        IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+#endif
+
+/*
+ * Architecture-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+
+#define OMAP3430_CM_REVISION            OMAP_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+
+#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific CM registers from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* Common between 24xx and 34xx */
+
+#define CM_FCLKEN                                       0x0000
+#define CM_FCLKEN1                                      CM_FCLKEN
+#define CM_CLKEN                                        CM_FCLKEN
+#define CM_ICLKEN                                       0x0010
+#define CM_ICLKEN1                                      CM_ICLKEN
+#define CM_ICLKEN2                                      0x0014
+#define CM_ICLKEN3                                      0x0018
+#define CM_IDLEST                                       0x0020
+#define CM_IDLEST1                                      CM_IDLEST
+#define CM_IDLEST2                                      0x0024
+#define CM_AUTOIDLE                                     0x0030
+#define CM_AUTOIDLE1                                    CM_AUTOIDLE
+#define CM_AUTOIDLE2                                    0x0034
+#define CM_AUTOIDLE3                                    0x0038
+#define CM_CLKSEL                                       0x0040
+#define CM_CLKSEL1                                      CM_CLKSEL
+#define CM_CLKSEL2                                      0x0044
+#define CM_CLKSTCTRL                                    0x0048
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_CM_FCLKEN2                             0x0004
+#define OMAP24XX_CM_ICLKEN4                             0x001c
+#define OMAP24XX_CM_AUTOIDLE4                           0x003c
+
+#define OMAP2430_CM_IDLEST3                             0x0028
+
+#define OMAP3430_CM_CLKEN_PLL                           0x0004
+#define OMAP3430ES2_CM_CLKEN2                           0x0004
+#define OMAP3430ES2_CM_FCLKEN3                          0x0008
+#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3                             CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST                             0x004c
+#define OMAP3430ES2_CM_CLKSEL4                          0x004c
+#define OMAP3430ES2_CM_CLKSEL5                          0x0050
+#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
+#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
+
+
+/* Clock management domain register get/set */
+
+#ifndef __ASSEMBLER__
+static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+        __raw_writel(val, OMAP_CM_REGADDR(module, idx));
+}
+
+static inline u32 cm_read_mod_reg(s16 module, s16 idx)
+{
+        return __raw_readl(OMAP_CM_REGADDR(module, idx));
+}
+#endif
+
+/* CM register bits shared between 24XX and 3430 */
+
+/* CM_CLKSEL_GFX */
+#define OMAP_CLKSEL_GFX_SHIFT                           0
+#define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
+
+/* CM_ICLKEN_GFX */
+#define OMAP_EN_GFX_SHIFT                               0
+#define OMAP_EN_GFX                                     (1 << 0)
+
+/* CM_IDLEST_GFX */
+#define OMAP_ST_GFX                                     (1 << 0)
+
+
+#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
new file mode 100644
index 000000000000..a5d86a49c213
--- /dev/null
+++ b/arch/arm/mach-omap2/control.c
@@ -0,0 +1,74 @@
+/*
+ * OMAP2/3 System Control Module register access
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/control.h>
+
+static u32 omap2_ctrl_base;
+
+#define OMAP_CTRL_REGADDR(reg)  (void __iomem *)IO_ADDRESS(omap2_ctrl_base \
+                                                                + (reg))
+
+void omap_ctrl_base_set(u32 base)
+{
+        omap2_ctrl_base = base;
+}
+
+u32 omap_ctrl_base_get(void)
+{
+        return omap2_ctrl_base;
+}
+
+u8 omap_ctrl_readb(u16 offset)
+{
+        return __raw_readb(OMAP_CTRL_REGADDR(offset));
+}
+
+u16 omap_ctrl_readw(u16 offset)
+{
+        return __raw_readw(OMAP_CTRL_REGADDR(offset));
+}
+
+u32 omap_ctrl_readl(u16 offset)
+{
+        return __raw_readl(OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writeb(u8 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writew(u16 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writew(val, OMAP_CTRL_REGADDR(offset));
+}
+
+void omap_ctrl_writel(u32 val, u16 offset)
+{
+        pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
+                 (u32)OMAP_CTRL_REGADDR(offset));
+
+        __raw_writel(val, OMAP_CTRL_REGADDR(offset));
+}
+
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5a4cc2076a7d..02cede295e89 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -69,7 +69,7 @@ static void __iomem *gpmc_base =
 static void __iomem *gpmc_cs_base =
         (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
 
-static struct clk *gpmc_l3_clk;
+static struct clk *gpmc_fck;
 
 static void gpmc_write_reg(int idx, u32 val)
 {
@@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx)
         return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
 }
 
-/* TODO: Add support for gpmc_fck to clock framework and use it */
 unsigned long gpmc_get_fclk_period(void)
 {
         /* In picoseconds */
-        return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
+        return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
 }
 
 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -398,8 +397,11 @@ void __init gpmc_init(void)
 {
         u32 l;
 
-        gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
-        BUG_ON(IS_ERR(gpmc_l3_clk));
+        gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
+        if (IS_ERR(gpmc_fck))
+                WARN_ON(1);
+        else
+                clk_enable(gpmc_fck);
 
         l = gpmc_read_reg(GPMC_REVISION);
         printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 3e5d8cd4ea4f..12479081881a 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -27,11 +27,16 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
 
-#include "prcm-regs.h"
+#include "prm.h"
+
 #include "memory.h"
+#include "sdrc.h"
 
+unsigned long omap2_sdrc_base;
+unsigned long omap2_sms_base;
 
 static struct memory_timings mem_timings;
+static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
 
 u32 omap2_memory_get_slow_dll_ctrl(void)
 {
@@ -48,12 +53,60 @@ u32 omap2_memory_get_type(void)
         return mem_timings.m_type;
 }
 
+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compensate for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+        /* dlla and dllb are a set */
+        u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+
+        if ((dll_state & (1 << 2)) == (1 << 2))
+                return 1;
+        else
+                return 0;
+}
+
+/*
+ * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
+ * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
+ * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
+ */
+u32 omap2_reprogram_sdrc(u32 level, u32 force)
+{
+        u32 dll_ctrl, m_type;
+        u32 prev = curr_perf_level;
+        unsigned long flags;
+
+        if ((curr_perf_level == level) && !force)
+                return prev;
+
+        if (level == CORE_CLK_SRC_DPLL) {
+                dll_ctrl = omap2_memory_get_slow_dll_ctrl();
+        } else if (level == CORE_CLK_SRC_DPLL_X2) {
+                dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+        } else {
+                return prev;
+        }
+
+        m_type = omap2_memory_get_type();
+
+        local_irq_save(flags);
+        __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
+        omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
+        curr_perf_level = level;
+        local_irq_restore(flags);
+
+        return prev;
+}
+
 void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
 {
         unsigned long dll_cnt;
         u32 fast_dll = 0;
 
-        mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
+        mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
 
         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
          * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -73,11 +126,11 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
                 mem_timings.dll_mode = M_LOCK;
 
         if (mem_timings.base_cs == 0) {
-                fast_dll = SDRC_DLLA_CTRL;
-                dll_cnt = SDRC_DLLA_STATUS & 0xff00;
+                fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
+                dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
         } else {
-                fast_dll = SDRC_DLLB_CTRL;
-                dll_cnt = SDRC_DLLB_STATUS & 0xff00;
+                fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
+                dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
         }
         if (force_lock_to_unlock_mode) {
                 fast_dll &= ~0xff00;
@@ -106,14 +159,13 @@ void __init omap2_init_memory(void)
 {
         u32 l;
 
-        l = SMS_SYSCONFIG;
+        l = sms_read_reg(SMS_SYSCONFIG);
         l &= ~(0x3 << 3);
         l |= (0x2 << 3);
-        SMS_SYSCONFIG = l;
+        sms_write_reg(l, SMS_SYSCONFIG);
 
-        l = SDRC_SYSCONFIG;
+        l = sdrc_read_reg(SDRC_SYSCONFIG);
         l &= ~(0x3 << 3);
         l |= (0x2 << 3);
-        SDRC_SYSCONFIG = l;
-
+        sdrc_write_reg(l, SDRC_SYSCONFIG);
 }
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index d212eea83a05..9a280b50a893 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -32,3 +32,5 @@ extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
 extern u32 omap2_memory_get_slow_dll_ctrl(void);
 extern u32 omap2_memory_get_fast_dll_ctrl(void);
 extern u32 omap2_memory_get_type(void);
+u32 omap2_dll_force_needed(void);
+u32 omap2_reprogram_sdrc(u32 level, u32 force);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 05750975d746..930770012a75 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,11 +1,12 @@
 /*
  * linux/arch/arm/mach-omap2/mux.c
  *
- * OMAP1 pin multiplexing configurations
+ * OMAP2 pin multiplexing configurations
  *
- * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2003 - 2008 Nokia Corporation
  *
- * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ * Written by Tony Lindgren
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,13 +29,17 @@
 #include <asm/io.h>
 #include <linux/spinlock.h>
 
+#include <asm/arch/control.h>
 #include <asm/arch/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
 
+static struct omap_mux_cfg arch_mux_cfg;
+
 /* NOTE: See mux.h for the enumeration */
 
-struct pin_config __initdata_or_module omap24xx_pins[] = {
+#ifdef CONFIG_ARCH_OMAP24XX
+static struct pin_config __initdata_or_module omap24xx_pins[] = {
 /*
  *      description                     mux     mux     pull    pull    debug
  *                                      offset  mode    ena     type
@@ -77,7 +82,12 @@ MUX_CFG_24XX("AA12_242X_GPIO17",	0x0e9,	3,	0,	0,	1)
 MUX_CFG_24XX("AA8_242X_GPIO58",         0x0ea,  3,      0,      0,      1)
 MUX_CFG_24XX("Y20_24XX_GPIO60",         0x12c,  3,      0,      0,      1)
 MUX_CFG_24XX("W4__24XX_GPIO74",         0x0f2,  3,      0,      0,      1)
+MUX_CFG_24XX("N15_24XX_GPIO85",         0x103,  3,      0,      0,      1)
 MUX_CFG_24XX("M15_24XX_GPIO92",         0x10a,  3,      0,      0,      1)
+MUX_CFG_24XX("P20_24XX_GPIO93",         0x10b,  3,      0,      0,      1)
+MUX_CFG_24XX("P18_24XX_GPIO95",         0x10d,  3,      0,      0,      1)
+MUX_CFG_24XX("M18_24XX_GPIO96",         0x10e,  3,      0,      0,      1)
+MUX_CFG_24XX("L14_24XX_GPIO97",         0x10f,  3,      0,      0,      1)
 MUX_CFG_24XX("J15_24XX_GPIO99",         0x113,  3,      1,      1,      1)
 MUX_CFG_24XX("V14_24XX_GPIO117",        0x128,  3,      1,      0,      1)
 MUX_CFG_24XX("P14_24XX_GPIO125",        0x140,  3,      1,      1,      1)
@@ -102,9 +112,6 @@ MUX_CFG_24XX("G4_242X_DMAREQ3",		0x073,	2,	0,	0,	1)
 MUX_CFG_24XX("D3_242X_DMAREQ4",         0x072,  2,      0,      0,      1)
 MUX_CFG_24XX("E3_242X_DMAREQ5",         0x071,  2,      0,      0,      1)
 
-/* TSC IRQ */
-MUX_CFG_24XX("P20_24XX_TSC_IRQ",        0x108,  0,      0,      0,      1)
-
 /* UART3 */
 MUX_CFG_24XX("K15_24XX_UART3_TX",       0x118,  0,      0,      0,      1)
 MUX_CFG_24XX("K14_24XX_UART3_RX",       0x119,  0,      0,      0,      1)
@@ -167,12 +174,108 @@ MUX_CFG_24XX("B3__24XX_KBR5",		0x30,	3,	1,	1,	1)
 MUX_CFG_24XX("AA4_24XX_KBC2",           0xe7,   3,      0,      0,      1)
 MUX_CFG_24XX("B13_24XX_KBC6",           0x110,  3,      0,      0,      1)
 
+/* 2430 USB */
+MUX_CFG_24XX("AD9_2430_USB0_PUEN",      0x133,  4,      0,      0,      1)
+MUX_CFG_24XX("Y11_2430_USB0_VP",        0x134,  4,      0,      0,      1)
+MUX_CFG_24XX("AD7_2430_USB0_VM",        0x135,  4,      0,      0,      1)
+MUX_CFG_24XX("AE7_2430_USB0_RCV",       0x136,  4,      0,      0,      1)
+MUX_CFG_24XX("AD4_2430_USB0_TXEN",      0x137,  4,      0,      0,      1)
+MUX_CFG_24XX("AF9_2430_USB0_SE0",       0x138,  4,      0,      0,      1)
+MUX_CFG_24XX("AE6_2430_USB0_DAT",       0x139,  4,      0,      0,      1)
+MUX_CFG_24XX("AD24_2430_USB1_SE0",      0x107,  2,      0,      0,      1)
+MUX_CFG_24XX("AB24_2430_USB1_RCV",      0x108,  2,      0,      0,      1)
+MUX_CFG_24XX("Y25_2430_USB1_TXEN",      0x109,  2,      0,      0,      1)
+MUX_CFG_24XX("AA26_2430_USB1_DAT",      0x10A,  2,      0,      0,      1)
+
+/* 2430 HS-USB */
+MUX_CFG_24XX("AD9_2430_USB0HS_DATA3",   0x133,  0,      0,      0,      1)
+MUX_CFG_24XX("Y11_2430_USB0HS_DATA4",   0x134,  0,      0,      0,      1)
+MUX_CFG_24XX("AD7_2430_USB0HS_DATA5",   0x135,  0,      0,      0,      1)
+MUX_CFG_24XX("AE7_2430_USB0HS_DATA6",   0x136,  0,      0,      0,      1)
+MUX_CFG_24XX("AD4_2430_USB0HS_DATA2",   0x137,  0,      0,      0,      1)
+MUX_CFG_24XX("AF9_2430_USB0HS_DATA0",   0x138,  0,      0,      0,      1)
+MUX_CFG_24XX("AE6_2430_USB0HS_DATA1",   0x139,  0,      0,      0,      1)
+MUX_CFG_24XX("AE8_2430_USB0HS_CLK",     0x13A,  0,      0,      0,      1)
+MUX_CFG_24XX("AD8_2430_USB0HS_DIR",     0x13B,  0,      0,      0,      1)
+MUX_CFG_24XX("AE5_2430_USB0HS_STP",     0x13c,  0,      1,      1,      1)
+MUX_CFG_24XX("AE9_2430_USB0HS_NXT",     0x13D,  0,      0,      0,      1)
+MUX_CFG_24XX("AC7_2430_USB0HS_DATA7",   0x13E,  0,      0,      0,      1)
+
+/* 2430 McBSP */
+MUX_CFG_24XX("AC10_2430_MCBSP2_FSX",    0x012E, 1,      0,      0,      1)
+MUX_CFG_24XX("AD16_2430_MCBSP2_CLX",    0x012F, 1,      0,      0,      1)
+MUX_CFG_24XX("AE13_2430_MCBSP2_DX",     0x0130, 1,      0,      0,      1)
+MUX_CFG_24XX("AD13_2430_MCBSP2_DR",     0x0131, 1,      0,      0,      1)
+MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0,      0,      0,      1)
+MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0,      0,      0,      1)
+MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0,      0,      0,      1)
+MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0,      0,      0,      1)
 };
 
-int __init omap2_mux_init(void)
+#define OMAP24XX_PINS_SZ        ARRAY_SIZE(omap24xx_pins)
+
+#else
+#define omap24xx_pins           NULL
+#define OMAP24XX_PINS_SZ        0
+#endif  /* CONFIG_ARCH_OMAP24XX */
+
+#define OMAP24XX_PULL_ENA       (1 << 3)
+#define OMAP24XX_PULL_UP        (1 << 4)
+
+#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
+void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
 {
-        omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
+        u16 orig;
+        u8 warn = 0, debug = 0;
+
+        orig = omap_ctrl_readb(cfg->mux_reg);
+
+#ifdef  CONFIG_OMAP_MUX_DEBUG
+        debug = cfg->debug;
+#endif
+        warn = (orig != reg);
+        if (debug || warn)
+                printk(KERN_WARNING
+                        "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
+                        cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
+                        orig, reg);
+}
+#else
+#define omap2_cfg_debug(x, y)   do {} while (0)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP24XX
+int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
+{
+        static DEFINE_SPINLOCK(mux_spin_lock);
+        unsigned long flags;
+        u8 reg = 0;
+
+        spin_lock_irqsave(&mux_spin_lock, flags);
+        reg |= cfg->mask & 0x7;
+        if (cfg->pull_val)
+                reg |= OMAP24XX_PULL_ENA;
+        if (cfg->pu_pd_val)
+                reg |= OMAP24XX_PULL_UP;
+        omap2_cfg_debug(cfg, reg);
+        omap_ctrl_writeb(reg, cfg->mux_reg);
+        spin_unlock_irqrestore(&mux_spin_lock, flags);
+
         return 0;
 }
+#else
+#define omap24xx_cfg_reg        0
+#endif
+
+int __init omap2_mux_init(void)
+{
+        if (cpu_is_omap24xx()) {
+                arch_mux_cfg.pins       = omap24xx_pins;
+                arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
+        }
+
+        return omap_mux_register(&arch_mux_cfg);
+}
 
 #endif
diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c
deleted file mode 100644
index 2494091a078b..000000000000
--- a/arch/arm/mach-omap2/pm-domain.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/pm-domain.c
- *
- * Power domain functions for OMAP2
- *
- * Copyright (C) 2006 Nokia Corporation
- * Tony Lindgren <tony@atomide.com>
- *
- * Some code based on earlier OMAP2 sample PM code
- * Copyright (C) 2005 Texas Instruments, Inc.
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-
-#include <asm/io.h>
-
-#include "prcm-regs.h"
-
-/* Power domain offsets */
-#define PM_MPU_OFFSET                   0x100
-#define PM_CORE_OFFSET                  0x200
-#define PM_GFX_OFFSET                   0x300
-#define PM_WKUP_OFFSET                  0x400           /* Autoidle only */
-#define PM_PLL_OFFSET                   0x500           /* Autoidle only */
-#define PM_DSP_OFFSET                   0x800
-#define PM_MDM_OFFSET                   0xc00
-
-/* Power domain wake-up dependency control register */
-#define PM_WKDEP_OFFSET                 0xc8
-#define         EN_MDM                  (1 << 5)
-#define         EN_WKUP                 (1 << 4)
-#define         EN_GFX                  (1 << 3)
-#define         EN_DSP                  (1 << 2)
-#define         EN_MPU                  (1 << 1)
-#define         EN_CORE                 (1 << 0)
-
-/* Core power domain state transition control register */
-#define PM_PWSTCTRL_OFFSET              0xe0
-#define         FORCESTATE              (1 << 18)       /* Only for DSP & GFX */
-#define         MEM4RETSTATE            (1 << 6)
-#define         MEM3RETSTATE            (1 << 5)
-#define         MEM2RETSTATE            (1 << 4)
-#define         MEM1RETSTATE            (1 << 3)
-#define         LOGICRETSTATE           (1 << 2)        /* Logic is retained */
-#define         POWERSTATE_OFF          0x3
-#define         POWERSTATE_RETENTION    0x1
-#define         POWERSTATE_ON           0x0
-
-/* Power domain state register */
-#define PM_PWSTST_OFFSET                0xe4
-
-/* Hardware supervised state transition control register */
-#define CM_CLKSTCTRL_OFFSET             0x48
-#define         AUTOSTAT_MPU            (1 << 0)        /* MPU */
-#define         AUTOSTAT_DSS            (1 << 2)        /* Core */
-#define         AUTOSTAT_L4             (1 << 1)        /* Core */
-#define         AUTOSTAT_L3             (1 << 0)        /* Core */
-#define         AUTOSTAT_GFX            (1 << 0)        /* GFX */
-#define         AUTOSTAT_IVA            (1 << 8)        /* 2420 IVA in DSP domain */
-#define         AUTOSTAT_DSP            (1 << 0)        /* DSP */
-#define         AUTOSTAT_MDM            (1 << 0)        /* MDM */
-
-/* Automatic control of interface clock idling */
-#define CM_AUTOIDLE1_OFFSET             0x30
-#define CM_AUTOIDLE2_OFFSET             0x34            /* Core only */
-#define CM_AUTOIDLE3_OFFSET             0x38            /* Core only */
-#define CM_AUTOIDLE4_OFFSET             0x3c            /* Core only */
-#define         AUTO_54M(x)             (((x) & 0x3) << 6)
-#define         AUTO_96M(x)             (((x) & 0x3) << 2)
-#define         AUTO_DPLL(x)            (((x) & 0x3) << 0)
-#define         AUTO_STOPPED            0x3
-#define         AUTO_BYPASS_FAST        0x2             /* DPLL only */
-#define         AUTO_BYPASS_LOW_POWER   0x1             /* DPLL only */
-#define         AUTO_DISABLED           0x0
-
-/* Voltage control PRCM_VOLTCTRL bits */
-#define         AUTO_EXTVOLT            (1 << 15)
-#define         FORCE_EXTVOLT           (1 << 14)
-#define         SETOFF_LEVEL(x)         (((x) & 0x3) << 12)
-#define         MEMRETCTRL              (1 << 8)
-#define         SETRET_LEVEL(x)         (((x) & 0x3) << 6)
-#define         VOLT_LEVEL(x)           (((x) & 0x3) << 0)
-
-#define OMAP24XX_PRCM_VBASE     IO_ADDRESS(OMAP24XX_PRCM_BASE)
-#define prcm_readl(r)           __raw_readl(OMAP24XX_PRCM_VBASE + (r))
-#define prcm_writel(v, r)       __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
-
-static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
-{
-        return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
-}
-
-static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
-}
-
-static u32 pmdomain_get_powerstate(int domain_offset)
-{
-        return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
-}
-
-static void pmdomain_set_powerstate(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
-}
-
-static u32 pmdomain_get_clock_autocontrol(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
-}
-
-static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
-{
-        prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
-}
-
-static u32 pmdomain_get_clock_autoidle1(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle2(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle3(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
-}
-
-/* Core domain only */
-static u32 pmdomain_get_clock_autoidle4(int domain_offset)
-{
-        return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
-}
-
-static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
-}
-
-/* Core domain only */
-static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
-{
-        prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
-}
-
-/*
- * Configures power management domains to idle clocks automatically.
- */
-void pmdomain_set_autoidle(void)
-{
-        u32 val;
-
-        /* Set PLL auto stop for 54M, 96M & DPLL */
-        pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
-                                     AUTO_96M(AUTO_STOPPED) |
-                                     AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
-
-        /* External clock input control
-         * REVISIT: Should this be in clock framework?
-         */
-        PRCM_CLKSRC_CTRL |= (0x3 << 3);
-
-        /* Configure number of 32KHz clock cycles for sys_clk */
-        PRCM_CLKSSETUP = 0x00ff;
-
-        /* Configure automatic voltage transition */
-        PRCM_VOLTSETUP = 0;
-        val = PRCM_VOLTCTRL;
-        val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
-        val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
-        PRCM_VOLTCTRL = val;
-
-        /* Disable emulation tools functional clock */
-        PRCM_CLKEMUL_CTRL = 0x0;
-
-        /* Set core memory retention state */
-        val = pmdomain_get_powerstate(PM_CORE_OFFSET);
-        if (cpu_is_omap2420()) {
-                val &= ~(0x7 << 3);
-                val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
-        } else {
-                val &= ~(0xf << 3);
-                val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
-                        MEM1RETSTATE);
-        }
-        pmdomain_set_powerstate(val, PM_CORE_OFFSET);
-
-        /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
-        val = SMS_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3) | (1 << 0);
-        SMS_SYSCONFIG |= val;
-
-        val = SDRC_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3);
-        SDRC_SYSCONFIG = val;
-
-        /* Configure L3 interface for smart idle.
-         * REVISIT: Enable autoidle bit0 ?
-         */
-        val = GPMC_SYSCONFIG;
-        val &= ~(0x3 << 3);
-        val |= (0x2 << 3) | (1 << 0);
-        GPMC_SYSCONFIG = val;
-
-        pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
-                                PM_MPU_OFFSET);
-        pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
-        if (!cpu_is_omap2420())
-                pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
-
-        /* Assume suspend function has saved the state for DSP and GFX */
-        pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
-        pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
-
-#if 0
-        /* REVISIT: Internal USB needs special handling */
-        force_standby_usb();
-        if (cpu_is_omap2430())
-                force_hsmmc();
-        sdram_self_refresh_on_idle_req(1);
-#endif
-
-        /* Enable clock auto control for all domains.
-         * Note that CORE domain includes also DSS, L4 & L3.
-         */
-        pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
-        pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
-        pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
-                                       PM_CORE_OFFSET);
-        if (cpu_is_omap2420())
-                pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
-                                               PM_DSP_OFFSET);
-        else {
-                pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
-                pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
-        }
-
-        /* Enable clock autoidle for all domains */
-        pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
-        if (cpu_is_omap2420()) {
-                pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
-        } else {
-                pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
-                pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
-                pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
-        }
-        pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
-        pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
-}
-
-/*
- * Initializes power domains by removing wake-up dependencies and powering
- * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
- * must re-enable DSP and GFX when used.
- */
-void __init pmdomain_init(void)
-{
-        /* Remove all domain wakeup dependencies */
-        pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
-        pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
-        pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
-        pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
-        if (cpu_is_omap2430())
-                pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
-
-        /* Power down DSP and GFX */
-        pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
-        pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
-}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index baf7d82b458b..aad781dcf1b1 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -23,6 +23,7 @@
 #include <linux/sysfs.h>
 #include <linux/module.h>
 #include <linux/delay.h>
+#include <linux/clk.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -36,8 +37,6 @@
 #include <asm/arch/sram.h>
 #include <asm/arch/pm.h>
 
-#include "prcm-regs.h"
-
 static struct clk *vclk;
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
@@ -78,251 +77,8 @@ static int omap2_pm_prepare(void)
         return 0;
 }
 
-#define INT0_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) |    \
-                        OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) |     \
-                        OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
-
-#define INT1_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
-
-#define INT2_WAKE_MASK  (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) |     \
-                        OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) |      \
-                        OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
-
-#define preg(reg)       printk("%s\t(0x%p):\t0x%08x\n", #reg, &reg, reg);
-
-static void omap2_pm_debug(char * desc)
-{
-        printk("%s:\n", desc);
-
-        preg(CM_CLKSTCTRL_MPU);
-        preg(CM_CLKSTCTRL_CORE);
-        preg(CM_CLKSTCTRL_GFX);
-        preg(CM_CLKSTCTRL_DSP);
-        preg(CM_CLKSTCTRL_MDM);
-
-        preg(PM_PWSTCTRL_MPU);
-        preg(PM_PWSTCTRL_CORE);
-        preg(PM_PWSTCTRL_GFX);
-        preg(PM_PWSTCTRL_DSP);
-        preg(PM_PWSTCTRL_MDM);
-
-        preg(PM_PWSTST_MPU);
-        preg(PM_PWSTST_CORE);
-        preg(PM_PWSTST_GFX);
-        preg(PM_PWSTST_DSP);
-        preg(PM_PWSTST_MDM);
-
-        preg(CM_AUTOIDLE1_CORE);
-        preg(CM_AUTOIDLE2_CORE);
-        preg(CM_AUTOIDLE3_CORE);
-        preg(CM_AUTOIDLE4_CORE);
-        preg(CM_AUTOIDLE_WKUP);
-        preg(CM_AUTOIDLE_PLL);
-        preg(CM_AUTOIDLE_DSP);
-        preg(CM_AUTOIDLE_MDM);
-
-        preg(CM_ICLKEN1_CORE);
-        preg(CM_ICLKEN2_CORE);
-        preg(CM_ICLKEN3_CORE);
-        preg(CM_ICLKEN4_CORE);
-        preg(CM_ICLKEN_GFX);
-        preg(CM_ICLKEN_WKUP);
-        preg(CM_ICLKEN_DSP);
-        preg(CM_ICLKEN_MDM);
-
-        preg(CM_IDLEST1_CORE);
-        preg(CM_IDLEST2_CORE);
-        preg(CM_IDLEST3_CORE);
-        preg(CM_IDLEST4_CORE);
-        preg(CM_IDLEST_GFX);
-        preg(CM_IDLEST_WKUP);
-        preg(CM_IDLEST_CKGEN);
-        preg(CM_IDLEST_DSP);
-        preg(CM_IDLEST_MDM);
-
-        preg(RM_RSTST_MPU);
-        preg(RM_RSTST_GFX);
-        preg(RM_RSTST_WKUP);
-        preg(RM_RSTST_DSP);
-        preg(RM_RSTST_MDM);
-
-        preg(PM_WKDEP_MPU);
-        preg(PM_WKDEP_CORE);
-        preg(PM_WKDEP_GFX);
-        preg(PM_WKDEP_DSP);
-        preg(PM_WKDEP_MDM);
-
-        preg(CM_FCLKEN_WKUP);
-        preg(CM_ICLKEN_WKUP);
-        preg(CM_IDLEST_WKUP);
-        preg(CM_AUTOIDLE_WKUP);
-        preg(CM_CLKSEL_WKUP);
-
-        preg(PM_WKEN_WKUP);
-        preg(PM_WKST_WKUP);
-}
-
-static inline void omap2_pm_save_registers(void)
-{
-        /* Save interrupt registers */
-        OMAP24XX_SAVE(INTC_MIR0);
-        OMAP24XX_SAVE(INTC_MIR1);
-        OMAP24XX_SAVE(INTC_MIR2);
-
-        /* Save power control registers */
-        OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
-        OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
-
-        /* Save power state registers */
-        OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
-        OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
-        OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
-        OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
-        OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
-
-        /* Save autoidle registers */
-        OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
-        OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
-        OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
-        OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
-        OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
-
-        /* Save idle state registers */
-        OMAP24XX_SAVE(CM_IDLEST1_CORE);
-        OMAP24XX_SAVE(CM_IDLEST2_CORE);
-        OMAP24XX_SAVE(CM_IDLEST3_CORE);
-        OMAP24XX_SAVE(CM_IDLEST4_CORE);
-        OMAP24XX_SAVE(CM_IDLEST_GFX);
-        OMAP24XX_SAVE(CM_IDLEST_WKUP);
-        OMAP24XX_SAVE(CM_IDLEST_CKGEN);
-        OMAP24XX_SAVE(CM_IDLEST_DSP);
-        OMAP24XX_SAVE(CM_IDLEST_MDM);
-
-        /* Save clock registers */
-        OMAP24XX_SAVE(CM_FCLKEN1_CORE);
-        OMAP24XX_SAVE(CM_FCLKEN2_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN1_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN2_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN3_CORE);
-        OMAP24XX_SAVE(CM_ICLKEN4_CORE);
-}
-
-static inline void omap2_pm_restore_registers(void)
-{
-        /* Restore clock state registers */
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
-        OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
-
-        /* Restore power state registers */
-        OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
-        OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
-
-        /* Restore idle state registers */
-        OMAP24XX_RESTORE(CM_IDLEST1_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST2_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST3_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST4_CORE);
-        OMAP24XX_RESTORE(CM_IDLEST_GFX);
-        OMAP24XX_RESTORE(CM_IDLEST_WKUP);
-        OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
-        OMAP24XX_RESTORE(CM_IDLEST_DSP);
-        OMAP24XX_RESTORE(CM_IDLEST_MDM);
-
-        /* Restore autoidle registers */
-        OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
-        OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
-
-        /* Restore clock registers */
-        OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
-        OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
-        OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
-
-        /* REVISIT: Clear interrupts here */
-
-        /* Restore interrupt registers */
-        OMAP24XX_RESTORE(INTC_MIR0);
-        OMAP24XX_RESTORE(INTC_MIR1);
-        OMAP24XX_RESTORE(INTC_MIR2);
-}
-
 static int omap2_pm_suspend(void)
 {
-        int processor_type = 0;
-
-        /* REVISIT: 0x21 or 0x26? */
-        if (cpu_is_omap2420())
-                processor_type = 0x21;
-
-        if (!processor_type)
-                return -ENOTSUPP;
-
-        local_irq_disable();
-        local_fiq_disable();
-
-        omap2_pm_save_registers();
-
-        /* Disable interrupts except for the wake events */
-        INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
-        INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
-        INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
-
-        pmdomain_set_autoidle();
-
-        /* Clear old wake-up events */
-        PM_WKST1_CORE = 0;
-        PM_WKST2_CORE = 0;
-        PM_WKST_WKUP = 0;
-
-        /* Enable wake-up events */
-        PM_WKEN1_CORE = (1 << 22) | (1 << 21);  /* UART1 & 2 */
-        PM_WKEN2_CORE = (1 << 2);               /* UART3 */
-        PM_WKEN_WKUP = (1 << 2) | (1 << 0);     /* GPIO & GPT1 */
-
-        /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
-         * in the SRAM suspend code */
-        CM_FCLKEN1_CORE = 0;
-        CM_FCLKEN2_CORE = 0;
-        CM_ICLKEN1_CORE = 0;
-        CM_ICLKEN3_CORE = 0;
-        CM_ICLKEN4_CORE = 0;
-
-        omap2_pm_debug("Status before suspend");
-
-        /* Must wait for serial buffers to clear */
-        mdelay(200);
-
-        /* Jump to SRAM suspend code
-         * REVISIT: When is this SDRC_DLLB_CTRL?
-         */
-        omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
-
-        /* Back from sleep */
-        omap2_pm_restore_registers();
-
-        local_fiq_enable();
-        local_irq_enable();
-
         return 0;
 }
 
@@ -357,30 +113,6 @@ static struct platform_suspend_ops omap_pm_ops = {
 
 int __init omap2_pm_init(void)
 {
-        printk("Power Management for TI OMAP.\n");
-
-        vclk = clk_get(NULL, "virt_prcm_set");
-        if (IS_ERR(vclk)) {
-                printk(KERN_ERR "Could not get PM vclk\n");
-                return -ENODEV;
-        }
-
-        /*
-         * We copy the assembler sleep/wakeup routines to SRAM.
-         * These routines need to be in SRAM as that's the only
-         * memory the MPU can see when it wakes up.
-         */
-        omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
-                                         omap24xx_idle_loop_suspend_sz);
-
-        omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
-                                            omap24xx_cpu_suspend_sz);
-
-        suspend_set_ops(&omap_pm_ops);
-        pm_idle = omap2_pm_idle;
-
-        pmdomain_init();
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
new file mode 100644
index 000000000000..cacb34086e35
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -0,0 +1,317 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+
+/*
+ * OMAP2/3 PRCM base and module definitions
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* Module offsets from both CM_BASE & PRM_BASE */
+
+/*
+ * Offsets that are the same on 24xx and 34xx
+ *
+ * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ */
+#define OCP_MOD                                         0x000
+#define MPU_MOD                                         0x100
+#define CORE_MOD                                        0x200
+#define GFX_MOD                                         0x300
+#define WKUP_MOD                                        0x400
+#define PLL_MOD                                         0x500
+
+
+/* Chip-specific module offsets */
+#define OMAP24XX_DSP_MOD                                0x800
+
+#define OMAP2430_MDM_MOD                                0xc00
+
+/* IVA2 module is < base on 3430 */
+#define OMAP3430_IVA2_MOD                               -0x800
+#define OMAP3430ES2_SGX_MOD                             GFX_MOD
+#define OMAP3430_CCR_MOD                                PLL_MOD
+#define OMAP3430_DSS_MOD                                0x600
+#define OMAP3430_CAM_MOD                                0x700
+#define OMAP3430_PER_MOD                                0x800
+#define OMAP3430_EMU_MOD                                0x900
+#define OMAP3430_GR_MOD                                 0xa00
+#define OMAP3430_NEON_MOD                               0xb00
+#define OMAP3430ES2_USBHOST_MOD                         0xc00
+
+
+/* 24XX register bits shared between CM & PRM registers */
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP2420_EN_MMC_SHIFT                           26
+#define OMAP2420_EN_MMC                                 (1 << 26)
+#define OMAP24XX_EN_UART2_SHIFT                         22
+#define OMAP24XX_EN_UART2                               (1 << 22)
+#define OMAP24XX_EN_UART1_SHIFT                         21
+#define OMAP24XX_EN_UART1                               (1 << 21)
+#define OMAP24XX_EN_MCSPI2_SHIFT                        18
+#define OMAP24XX_EN_MCSPI2                              (1 << 18)
+#define OMAP24XX_EN_MCSPI1_SHIFT                        17
+#define OMAP24XX_EN_MCSPI1                              (1 << 17)
+#define OMAP24XX_EN_MCBSP2_SHIFT                        16
+#define OMAP24XX_EN_MCBSP2                              (1 << 16)
+#define OMAP24XX_EN_MCBSP1_SHIFT                        15
+#define OMAP24XX_EN_MCBSP1                              (1 << 15)
+#define OMAP24XX_EN_GPT12_SHIFT                         14
+#define OMAP24XX_EN_GPT12                               (1 << 14)
+#define OMAP24XX_EN_GPT11_SHIFT                         13
+#define OMAP24XX_EN_GPT11                               (1 << 13)
+#define OMAP24XX_EN_GPT10_SHIFT                         12
+#define OMAP24XX_EN_GPT10                               (1 << 12)
+#define OMAP24XX_EN_GPT9_SHIFT                          11
+#define OMAP24XX_EN_GPT9                                (1 << 11)
+#define OMAP24XX_EN_GPT8_SHIFT                          10
+#define OMAP24XX_EN_GPT8                                (1 << 10)
+#define OMAP24XX_EN_GPT7_SHIFT                          9
+#define OMAP24XX_EN_GPT7                                (1 << 9)
+#define OMAP24XX_EN_GPT6_SHIFT                          8
+#define OMAP24XX_EN_GPT6                                (1 << 8)
+#define OMAP24XX_EN_GPT5_SHIFT                          7
+#define OMAP24XX_EN_GPT5                                (1 << 7)
+#define OMAP24XX_EN_GPT4_SHIFT                          6
+#define OMAP24XX_EN_GPT4                                (1 << 6)
+#define OMAP24XX_EN_GPT3_SHIFT                          5
+#define OMAP24XX_EN_GPT3                                (1 << 5)
+#define OMAP24XX_EN_GPT2_SHIFT                          4
+#define OMAP24XX_EN_GPT2                                (1 << 4)
+#define OMAP2420_EN_VLYNQ_SHIFT                         3
+#define OMAP2420_EN_VLYNQ                               (1 << 3)
+
+/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_GPIO5_SHIFT                         10
+#define OMAP2430_EN_GPIO5                               (1 << 10)
+#define OMAP2430_EN_MCSPI3_SHIFT                        9
+#define OMAP2430_EN_MCSPI3                              (1 << 9)
+#define OMAP2430_EN_MMCHS2_SHIFT                        8
+#define OMAP2430_EN_MMCHS2                              (1 << 8)
+#define OMAP2430_EN_MMCHS1_SHIFT                        7
+#define OMAP2430_EN_MMCHS1                              (1 << 7)
+#define OMAP24XX_EN_UART3_SHIFT                         2
+#define OMAP24XX_EN_UART3                               (1 << 2)
+#define OMAP24XX_EN_USB_SHIFT                           0
+#define OMAP24XX_EN_USB                                 (1 << 0)
+
+/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_MDM_INTC_SHIFT                      11
+#define OMAP2430_EN_MDM_INTC                            (1 << 11)
+#define OMAP2430_EN_USBHS_SHIFT                         6
+#define OMAP2430_EN_USBHS                               (1 << 6)
+
+/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+#define OMAP2420_ST_MMC                                 (1 << 26)
+#define OMAP24XX_ST_UART2                               (1 << 22)
+#define OMAP24XX_ST_UART1                               (1 << 21)
+#define OMAP24XX_ST_MCSPI2                              (1 << 18)
+#define OMAP24XX_ST_MCSPI1                              (1 << 17)
+#define OMAP24XX_ST_GPT12                               (1 << 14)
+#define OMAP24XX_ST_GPT11                               (1 << 13)
+#define OMAP24XX_ST_GPT10                               (1 << 12)
+#define OMAP24XX_ST_GPT9                                (1 << 11)
+#define OMAP24XX_ST_GPT8                                (1 << 10)
+#define OMAP24XX_ST_GPT7                                (1 << 9)
+#define OMAP24XX_ST_GPT6                                (1 << 8)
+#define OMAP24XX_ST_GPT5                                (1 << 7)
+#define OMAP24XX_ST_GPT4                                (1 << 6)
+#define OMAP24XX_ST_GPT3                                (1 << 5)
+#define OMAP24XX_ST_GPT2                                (1 << 4)
+#define OMAP2420_ST_VLYNQ                               (1 << 3)
+
+/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+#define OMAP2430_ST_MDM_INTC                            (1 << 11)
+#define OMAP2430_ST_GPIO5                               (1 << 10)
+#define OMAP2430_ST_MCSPI3                              (1 << 9)
+#define OMAP2430_ST_MMCHS2                              (1 << 8)
+#define OMAP2430_ST_MMCHS1                              (1 << 7)
+#define OMAP2430_ST_USBHS                               (1 << 6)
+#define OMAP24XX_ST_UART3                               (1 << 2)
+#define OMAP24XX_ST_USB                                 (1 << 0)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP24XX_EN_GPIOS_SHIFT                         2
+#define OMAP24XX_EN_GPIOS                               (1 << 2)
+#define OMAP24XX_EN_GPT1_SHIFT                          0
+#define OMAP24XX_EN_GPT1                                (1 << 0)
+
+/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+#define OMAP24XX_ST_GPIOS                               (1 << 2)
+#define OMAP24XX_ST_GPT1                                (1 << 0)
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM                                 (1 << 0)
+
+
+/* 3430 register bits shared between CM & PRM registers */
+
+/* CM_REVISION, PRM_REVISION shared bits */
+#define OMAP3430_REV_SHIFT                              0
+#define OMAP3430_REV_MASK                               (0xff << 0)
+
+/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+#define OMAP3430_AUTOIDLE                               (1 << 0)
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC2                                (1 << 25)
+#define OMAP3430_EN_MMC2_SHIFT                          25
+#define OMAP3430_EN_MMC1                                (1 << 24)
+#define OMAP3430_EN_MMC1_SHIFT                          24
+#define OMAP3430_EN_MCSPI4                              (1 << 21)
+#define OMAP3430_EN_MCSPI4_SHIFT                        21
+#define OMAP3430_EN_MCSPI3                              (1 << 20)
+#define OMAP3430_EN_MCSPI3_SHIFT                        20
+#define OMAP3430_EN_MCSPI2                              (1 << 19)
+#define OMAP3430_EN_MCSPI2_SHIFT                        19
+#define OMAP3430_EN_MCSPI1                              (1 << 18)
+#define OMAP3430_EN_MCSPI1_SHIFT                        18
+#define OMAP3430_EN_I2C3                                (1 << 17)
+#define OMAP3430_EN_I2C3_SHIFT                          17
+#define OMAP3430_EN_I2C2                                (1 << 16)
+#define OMAP3430_EN_I2C2_SHIFT                          16
+#define OMAP3430_EN_I2C1                                (1 << 15)
+#define OMAP3430_EN_I2C1_SHIFT                          15
+#define OMAP3430_EN_UART2                               (1 << 14)
+#define OMAP3430_EN_UART2_SHIFT                         14
+#define OMAP3430_EN_UART1                               (1 << 13)
+#define OMAP3430_EN_UART1_SHIFT                         13
+#define OMAP3430_EN_GPT11                               (1 << 12)
+#define OMAP3430_EN_GPT11_SHIFT                         12
+#define OMAP3430_EN_GPT10                               (1 << 11)
+#define OMAP3430_EN_GPT10_SHIFT                         11
+#define OMAP3430_EN_MCBSP5                              (1 << 10)
+#define OMAP3430_EN_MCBSP5_SHIFT                        10
+#define OMAP3430_EN_MCBSP1                              (1 << 9)
+#define OMAP3430_EN_MCBSP1_SHIFT                        9
+#define OMAP3430_EN_FSHOSTUSB                           (1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_SHIFT                     5
+#define OMAP3430_EN_D2D                                 (1 << 3)
+#define OMAP3430_EN_D2D_SHIFT                           3
+
+/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_HSOTGUSB                            (1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT                              4
+
+/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC2                                (1 << 25)
+#define OMAP3430_ST_MMC1                                (1 << 24)
+#define OMAP3430_ST_MCSPI4                              (1 << 21)
+#define OMAP3430_ST_MCSPI3                              (1 << 20)
+#define OMAP3430_ST_MCSPI2                              (1 << 19)
+#define OMAP3430_ST_MCSPI1                              (1 << 18)
+#define OMAP3430_ST_I2C3                                (1 << 17)
+#define OMAP3430_ST_I2C2                                (1 << 16)
+#define OMAP3430_ST_I2C1                                (1 << 15)
+#define OMAP3430_ST_UART2                               (1 << 14)
+#define OMAP3430_ST_UART1                               (1 << 13)
+#define OMAP3430_ST_GPT11                               (1 << 12)
+#define OMAP3430_ST_GPT10                               (1 << 11)
+#define OMAP3430_ST_MCBSP5                              (1 << 10)
+#define OMAP3430_ST_MCBSP1                              (1 << 9)
+#define OMAP3430_ST_FSHOSTUSB                           (1 << 5)
+#define OMAP3430_ST_HSOTGUSB                            (1 << 4)
+#define OMAP3430_ST_D2D                                 (1 << 3)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPIO1                               (1 << 3)
+#define OMAP3430_EN_GPIO1_SHIFT                         3
+#define OMAP3430_EN_GPT1                                (1 << 0)
+#define OMAP3430_EN_GPT1_SHIFT                          0
+
+/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_SR2                                 (1 << 7)
+#define OMAP3430_EN_SR2_SHIFT                           7
+#define OMAP3430_EN_SR1                                 (1 << 6)
+#define OMAP3430_EN_SR1_SHIFT                           6
+
+/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP3430_EN_GPT12                               (1 << 1)
+#define OMAP3430_EN_GPT12_SHIFT                         1
+
+/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
+#define OMAP3430_ST_SR2                                 (1 << 7)
+#define OMAP3430_ST_SR1                                 (1 << 6)
+#define OMAP3430_ST_GPIO1                               (1 << 3)
+#define OMAP3430_ST_GPT12                               (1 << 1)
+#define OMAP3430_ST_GPT1                                (1 << 0)
+
+/*
+ * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
+ * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
+ * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
+ */
+#define OMAP3430_EN_MPU                                 (1 << 1)
+#define OMAP3430_EN_MPU_SHIFT                           1
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+#define OMAP3430_EN_GPIO6                               (1 << 17)
+#define OMAP3430_EN_GPIO6_SHIFT                         17
+#define OMAP3430_EN_GPIO5                               (1 << 16)
+#define OMAP3430_EN_GPIO5_SHIFT                         16
+#define OMAP3430_EN_GPIO4                               (1 << 15)
+#define OMAP3430_EN_GPIO4_SHIFT                         15
+#define OMAP3430_EN_GPIO3                               (1 << 14)
+#define OMAP3430_EN_GPIO3_SHIFT                         14
+#define OMAP3430_EN_GPIO2                               (1 << 13)
+#define OMAP3430_EN_GPIO2_SHIFT                         13
+#define OMAP3430_EN_UART3                               (1 << 11)
+#define OMAP3430_EN_UART3_SHIFT                         11
+#define OMAP3430_EN_GPT9                                (1 << 10)
+#define OMAP3430_EN_GPT9_SHIFT                          10
+#define OMAP3430_EN_GPT8                                (1 << 9)
+#define OMAP3430_EN_GPT8_SHIFT                          9
+#define OMAP3430_EN_GPT7                                (1 << 8)
+#define OMAP3430_EN_GPT7_SHIFT                          8
+#define OMAP3430_EN_GPT6                                (1 << 7)
+#define OMAP3430_EN_GPT6_SHIFT                          7
+#define OMAP3430_EN_GPT5                                (1 << 6)
+#define OMAP3430_EN_GPT5_SHIFT                          6
+#define OMAP3430_EN_GPT4                                (1 << 5)
+#define OMAP3430_EN_GPT4_SHIFT                          5
+#define OMAP3430_EN_GPT3                                (1 << 4)
+#define OMAP3430_EN_GPT3_SHIFT                          4
+#define OMAP3430_EN_GPT2                                (1 << 3)
+#define OMAP3430_EN_GPT2_SHIFT                          3
+
+/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
+/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
+ * be ST_* bits instead? */
+#define OMAP3430_EN_MCBSP4                              (1 << 2)
+#define OMAP3430_EN_MCBSP4_SHIFT                        2
+#define OMAP3430_EN_MCBSP3                              (1 << 1)
+#define OMAP3430_EN_MCBSP3_SHIFT                        1
+#define OMAP3430_EN_MCBSP2                              (1 << 0)
+#define OMAP3430_EN_MCBSP2_SHIFT                        0
+
+/* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3430_ST_GPIO6                               (1 << 17)
+#define OMAP3430_ST_GPIO5                               (1 << 16)
+#define OMAP3430_ST_GPIO4                               (1 << 15)
+#define OMAP3430_ST_GPIO3                               (1 << 14)
+#define OMAP3430_ST_GPIO2                               (1 << 13)
+#define OMAP3430_ST_UART3                               (1 << 11)
+#define OMAP3430_ST_GPT9                                (1 << 10)
+#define OMAP3430_ST_GPT8                                (1 << 9)
+#define OMAP3430_ST_GPT7                                (1 << 8)
+#define OMAP3430_ST_GPT6                                (1 << 7)
+#define OMAP3430_ST_GPT5                                (1 << 6)
+#define OMAP3430_ST_GPT4                                (1 << 5)
+#define OMAP3430_ST_GPT3                                (1 << 4)
+#define OMAP3430_ST_GPT2                                (1 << 3)
+
+/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
+#define OMAP3430_EN_CORE                                (1 << 0)
+
+#endif
+
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
deleted file mode 100644
index 5e1c4b53ee9d..000000000000
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/prcm-regs.h
- *
- * OMAP24XX Power Reset and Clock Management (PRCM) registers
- *
- * Copyright (C) 2005 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
-#define __ARCH_ARM_MACH_OMAP2_PRCM_H
-
-/* SET_PERFORMANCE_LEVEL PARAMETERS */
-#define PRCM_HALF_SPEED 1
-#define PRCM_FULL_SPEED 2
-
-#ifndef __ASSEMBLER__
-
-#define PRCM_REG32(offset)      __REG32(OMAP24XX_PRCM_BASE + (offset))
-
-#define PRCM_REVISION           PRCM_REG32(0x000)
-#define PRCM_SYSCONFIG          PRCM_REG32(0x010)
-#define PRCM_IRQSTATUS_MPU      PRCM_REG32(0x018)
-#define PRCM_IRQENABLE_MPU      PRCM_REG32(0x01C)
-#define PRCM_VOLTCTRL           PRCM_REG32(0x050)
-#define PRCM_VOLTST             PRCM_REG32(0x054)
-#define PRCM_CLKSRC_CTRL        PRCM_REG32(0x060)
-#define PRCM_CLKOUT_CTRL        PRCM_REG32(0x070)
-#define PRCM_CLKEMUL_CTRL       PRCM_REG32(0x078)
-#define PRCM_CLKCFG_CTRL        PRCM_REG32(0x080)
-#define PRCM_CLKCFG_STATUS      PRCM_REG32(0x084)
-#define PRCM_VOLTSETUP          PRCM_REG32(0x090)
-#define PRCM_CLKSSETUP          PRCM_REG32(0x094)
-#define PRCM_POLCTRL            PRCM_REG32(0x098)
-
-/* GENERAL PURPOSE */
-#define GENERAL_PURPOSE1        PRCM_REG32(0x0B0)
-#define GENERAL_PURPOSE2        PRCM_REG32(0x0B4)
-#define GENERAL_PURPOSE3        PRCM_REG32(0x0B8)
-#define GENERAL_PURPOSE4        PRCM_REG32(0x0BC)
-#define GENERAL_PURPOSE5        PRCM_REG32(0x0C0)
-#define GENERAL_PURPOSE6        PRCM_REG32(0x0C4)
-#define GENERAL_PURPOSE7        PRCM_REG32(0x0C8)
-#define GENERAL_PURPOSE8        PRCM_REG32(0x0CC)
-#define GENERAL_PURPOSE9        PRCM_REG32(0x0D0)
-#define GENERAL_PURPOSE10       PRCM_REG32(0x0D4)
-#define GENERAL_PURPOSE11       PRCM_REG32(0x0D8)
-#define GENERAL_PURPOSE12       PRCM_REG32(0x0DC)
-#define GENERAL_PURPOSE13       PRCM_REG32(0x0E0)
-#define GENERAL_PURPOSE14       PRCM_REG32(0x0E4)
-#define GENERAL_PURPOSE15       PRCM_REG32(0x0E8)
-#define GENERAL_PURPOSE16       PRCM_REG32(0x0EC)
-#define GENERAL_PURPOSE17       PRCM_REG32(0x0F0)
-#define GENERAL_PURPOSE18       PRCM_REG32(0x0F4)
-#define GENERAL_PURPOSE19       PRCM_REG32(0x0F8)
-#define GENERAL_PURPOSE20       PRCM_REG32(0x0FC)
-
-/* MPU */
-#define CM_CLKSEL_MPU           PRCM_REG32(0x140)
-#define CM_CLKSTCTRL_MPU        PRCM_REG32(0x148)
-#define RM_RSTST_MPU            PRCM_REG32(0x158)
-#define PM_WKDEP_MPU            PRCM_REG32(0x1C8)
-#define PM_EVGENCTRL_MPU        PRCM_REG32(0x1D4)
-#define PM_EVEGENONTIM_MPU      PRCM_REG32(0x1D8)
-#define PM_EVEGENOFFTIM_MPU     PRCM_REG32(0x1DC)
-#define PM_PWSTCTRL_MPU         PRCM_REG32(0x1E0)
-#define PM_PWSTST_MPU           PRCM_REG32(0x1E4)
-
-/* CORE */
-#define CM_FCLKEN1_CORE         PRCM_REG32(0x200)
-#define CM_FCLKEN2_CORE         PRCM_REG32(0x204)
-#define CM_FCLKEN3_CORE         PRCM_REG32(0x208)
-#define CM_ICLKEN1_CORE         PRCM_REG32(0x210)
-#define CM_ICLKEN2_CORE         PRCM_REG32(0x214)
-#define CM_ICLKEN3_CORE         PRCM_REG32(0x218)
-#define CM_ICLKEN4_CORE         PRCM_REG32(0x21C)
-#define CM_IDLEST1_CORE         PRCM_REG32(0x220)
-#define CM_IDLEST2_CORE         PRCM_REG32(0x224)
-#define CM_IDLEST3_CORE         PRCM_REG32(0x228)
-#define CM_IDLEST4_CORE         PRCM_REG32(0x22C)
-#define CM_AUTOIDLE1_CORE       PRCM_REG32(0x230)
-#define CM_AUTOIDLE2_CORE       PRCM_REG32(0x234)
-#define CM_AUTOIDLE3_CORE       PRCM_REG32(0x238)
-#define CM_AUTOIDLE4_CORE       PRCM_REG32(0x23C)
-#define CM_CLKSEL1_CORE         PRCM_REG32(0x240)
-#define CM_CLKSEL2_CORE         PRCM_REG32(0x244)
-#define CM_CLKSTCTRL_CORE       PRCM_REG32(0x248)
-#define PM_WKEN1_CORE           PRCM_REG32(0x2A0)
-#define PM_WKEN2_CORE           PRCM_REG32(0x2A4)
-#define PM_WKST1_CORE           PRCM_REG32(0x2B0)
-#define PM_WKST2_CORE           PRCM_REG32(0x2B4)
-#define PM_WKDEP_CORE           PRCM_REG32(0x2C8)
-#define PM_PWSTCTRL_CORE        PRCM_REG32(0x2E0)
-#define PM_PWSTST_CORE          PRCM_REG32(0x2E4)
-
-/* GFX */
-#define CM_FCLKEN_GFX           PRCM_REG32(0x300)
-#define CM_ICLKEN_GFX           PRCM_REG32(0x310)
-#define CM_IDLEST_GFX           PRCM_REG32(0x320)
-#define CM_CLKSEL_GFX           PRCM_REG32(0x340)
-#define CM_CLKSTCTRL_GFX        PRCM_REG32(0x348)
-#define RM_RSTCTRL_GFX          PRCM_REG32(0x350)
-#define RM_RSTST_GFX            PRCM_REG32(0x358)
-#define PM_WKDEP_GFX            PRCM_REG32(0x3C8)
-#define PM_PWSTCTRL_GFX         PRCM_REG32(0x3E0)
-#define PM_PWSTST_GFX           PRCM_REG32(0x3E4)
-
-/* WAKE-UP */
-#define CM_FCLKEN_WKUP          PRCM_REG32(0x400)
-#define CM_ICLKEN_WKUP          PRCM_REG32(0x410)
-#define CM_IDLEST_WKUP          PRCM_REG32(0x420)
-#define CM_AUTOIDLE_WKUP        PRCM_REG32(0x430)
-#define CM_CLKSEL_WKUP          PRCM_REG32(0x440)
-#define RM_RSTCTRL_WKUP         PRCM_REG32(0x450)
-#define RM_RSTTIME_WKUP         PRCM_REG32(0x454)
-#define RM_RSTST_WKUP           PRCM_REG32(0x458)
-#define PM_WKEN_WKUP            PRCM_REG32(0x4A0)
-#define PM_WKST_WKUP            PRCM_REG32(0x4B0)
-
-/* CLOCKS */
-#define CM_CLKEN_PLL            PRCM_REG32(0x500)
-#define CM_IDLEST_CKGEN         PRCM_REG32(0x520)
-#define CM_AUTOIDLE_PLL         PRCM_REG32(0x530)
-#define CM_CLKSEL1_PLL          PRCM_REG32(0x540)
-#define CM_CLKSEL2_PLL          PRCM_REG32(0x544)
-
-/* DSP */
-#define CM_FCLKEN_DSP           PRCM_REG32(0x800)
-#define CM_ICLKEN_DSP           PRCM_REG32(0x810)
-#define CM_IDLEST_DSP           PRCM_REG32(0x820)
-#define CM_AUTOIDLE_DSP         PRCM_REG32(0x830)
-#define CM_CLKSEL_DSP           PRCM_REG32(0x840)
-#define CM_CLKSTCTRL_DSP        PRCM_REG32(0x848)
-#define RM_RSTCTRL_DSP          PRCM_REG32(0x850)
-#define RM_RSTST_DSP            PRCM_REG32(0x858)
-#define PM_WKEN_DSP             PRCM_REG32(0x8A0)
-#define PM_WKDEP_DSP            PRCM_REG32(0x8C8)
-#define PM_PWSTCTRL_DSP         PRCM_REG32(0x8E0)
-#define PM_PWSTST_DSP           PRCM_REG32(0x8E4)
-#define PRCM_IRQSTATUS_DSP      PRCM_REG32(0x8F0)
-#define PRCM_IRQENABLE_DSP      PRCM_REG32(0x8F4)
-
-/* IVA */
-#define PRCM_IRQSTATUS_IVA      PRCM_REG32(0x8F8)
-#define PRCM_IRQENABLE_IVA      PRCM_REG32(0x8FC)
-
-/* Modem on 2430 */
-#define CM_FCLKEN_MDM           PRCM_REG32(0xC00)
-#define CM_ICLKEN_MDM           PRCM_REG32(0xC10)
-#define CM_IDLEST_MDM           PRCM_REG32(0xC20)
-#define CM_AUTOIDLE_MDM         PRCM_REG32(0xC30)
-#define CM_CLKSEL_MDM           PRCM_REG32(0xC40)
-#define CM_CLKSTCTRL_MDM        PRCM_REG32(0xC48)
-#define RM_RSTCTRL_MDM          PRCM_REG32(0xC50)
-#define RM_RSTST_MDM            PRCM_REG32(0xC58)
-#define PM_WKEN_MDM             PRCM_REG32(0xCA0)
-#define PM_WKST_MDM             PRCM_REG32(0xCB0)
-#define PM_WKDEP_MDM            PRCM_REG32(0xCC8)
-#define PM_PWSTCTRL_MDM         PRCM_REG32(0xCE0)
-#define PM_PWSTST_MDM           PRCM_REG32(0xCE4)
-
-#define OMAP24XX_L4_IO_BASE     0x48000000
-
-#define DISP_BASE               (OMAP24XX_L4_IO_BASE + 0x50000)
-#define DISP_REG32(offset)      __REG32(DISP_BASE + (offset))
-
-#define OMAP24XX_GPMC_BASE      (L3_24XX_BASE + 0xa000)
-#define GPMC_REG32(offset)      __REG32(OMAP24XX_GPMC_BASE + (offset))
-
-/* FIXME: Move these to timer code */
-#define GPT1_BASE               (0x48028000)
-#define GPT1_REG32(offset)      __REG32(GPT1_BASE + (offset))
-
-/* Misc sysconfig */
-#define DISPC_SYSCONFIG         DISP_REG32(0x410)
-#define SPI_BASE                (OMAP24XX_L4_IO_BASE + 0x98000)
-#define MCSPI1_SYSCONFIG        __REG32(SPI_BASE + 0x10)
-#define MCSPI2_SYSCONFIG        __REG32(SPI_BASE + 0x2000 + 0x10)
-#define MCSPI3_SYSCONFIG        __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
-
-#define CAMERA_MMU_SYSCONFIG    __REG32(DISP_BASE + 0x2C10)
-#define CAMERA_DMA_SYSCONFIG    __REG32(DISP_BASE + 0x282C)
-#define SYSTEM_DMA_SYSCONFIG    __REG32(DISP_BASE + 0x602C)
-#define GPMC_SYSCONFIG          GPMC_REG32(0x010)
-#define MAILBOXES_SYSCONFIG     __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
-#define UART1_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
-#define UART2_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
-#define UART3_SYSCONFIG         __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
-#define SDRC_SYSCONFIG          __REG32(OMAP24XX_SDRC_BASE + 0x10)
-#define OMAP24XX_SMS_BASE       (L3_24XX_BASE + 0x8000)
-#define SMS_SYSCONFIG           __REG32(OMAP24XX_SMS_BASE + 0x10)
-#define SSI_SYSCONFIG           __REG32(DISP_BASE + 0x8010)
-
-/* rkw - good cannidates for PM_ to start what nm was trying */
-#define OMAP24XX_GPT2           (OMAP24XX_L4_IO_BASE + 0x2A000)
-#define OMAP24XX_GPT3           (OMAP24XX_L4_IO_BASE + 0x78000)
-#define OMAP24XX_GPT4           (OMAP24XX_L4_IO_BASE + 0x7A000)
-#define OMAP24XX_GPT5           (OMAP24XX_L4_IO_BASE + 0x7C000)
-#define OMAP24XX_GPT6           (OMAP24XX_L4_IO_BASE + 0x7E000)
-#define OMAP24XX_GPT7           (OMAP24XX_L4_IO_BASE + 0x80000)
-#define OMAP24XX_GPT8           (OMAP24XX_L4_IO_BASE + 0x82000)
-#define OMAP24XX_GPT9           (OMAP24XX_L4_IO_BASE + 0x84000)
-#define OMAP24XX_GPT10          (OMAP24XX_L4_IO_BASE + 0x86000)
-#define OMAP24XX_GPT11          (OMAP24XX_L4_IO_BASE + 0x88000)
-#define OMAP24XX_GPT12          (OMAP24XX_L4_IO_BASE + 0x8A000)
-
-/* FIXME: Move these to timer code */
-#define GPTIMER1_SYSCONFIG      GPT1_REG32(0x010)
-#define GPTIMER2_SYSCONFIG      __REG32(OMAP24XX_GPT2 + 0x10)
-#define GPTIMER3_SYSCONFIG      __REG32(OMAP24XX_GPT3 + 0x10)
-#define GPTIMER4_SYSCONFIG      __REG32(OMAP24XX_GPT4 + 0x10)
-#define GPTIMER5_SYSCONFIG      __REG32(OMAP24XX_GPT5 + 0x10)
-#define GPTIMER6_SYSCONFIG      __REG32(OMAP24XX_GPT6 + 0x10)
-#define GPTIMER7_SYSCONFIG      __REG32(OMAP24XX_GPT7 + 0x10)
-#define GPTIMER8_SYSCONFIG      __REG32(OMAP24XX_GPT8 + 0x10)
-#define GPTIMER9_SYSCONFIG      __REG32(OMAP24XX_GPT9 + 0x10)
-#define GPTIMER10_SYSCONFIG     __REG32(OMAP24XX_GPT10 + 0x10)
-#define GPTIMER11_SYSCONFIG     __REG32(OMAP24XX_GPT11 + 0x10)
-#define GPTIMER12_SYSCONFIG     __REG32(OMAP24XX_GPT12 + 0x10)
-
-/* FIXME: Move these to gpio code */
-#define OMAP24XX_GPIO_BASE      0x48018000
-#define GPIOX_BASE(X)           (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
-
-#define GPIO1_SYSCONFIG         __REG32((GPIOX_BASE(1) + 0x10))
-#define GPIO2_SYSCONFIG         __REG32((GPIOX_BASE(2) + 0x10))
-#define GPIO3_SYSCONFIG         __REG32((GPIOX_BASE(3) + 0x10))
-#define GPIO4_SYSCONFIG         __REG32((GPIOX_BASE(4) + 0x10))
-
-#if defined(CONFIG_ARCH_OMAP243X)
-#define GPIO5_SYSCONFIG         __REG32((OMAP24XX_GPIO5_BASE + 0x10))
-#endif
-
-/* GP TIMER 1 */
-#define GPTIMER1_TISTAT         GPT1_REG32(0x014)
-#define GPTIMER1_TISR           GPT1_REG32(0x018)
-#define GPTIMER1_TIER           GPT1_REG32(0x01C)
-#define GPTIMER1_TWER           GPT1_REG32(0x020)
-#define GPTIMER1_TCLR           GPT1_REG32(0x024)
-#define GPTIMER1_TCRR           GPT1_REG32(0x028)
-#define GPTIMER1_TLDR           GPT1_REG32(0x02C)
-#define GPTIMER1_TTGR           GPT1_REG32(0x030)
-#define GPTIMER1_TWPS           GPT1_REG32(0x034)
-#define GPTIMER1_TMAR           GPT1_REG32(0x038)
-#define GPTIMER1_TCAR1          GPT1_REG32(0x03C)
-#define GPTIMER1_TSICR          GPT1_REG32(0x040)
-#define GPTIMER1_TCAR2          GPT1_REG32(0x044)
-
-/* rkw -- base fix up please... */
-#define GPTIMER3_TISR           __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
-
-/* SDRC */
-#define SDRC_DLLA_CTRL          __REG32(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_DLLA_STATUS        __REG32(OMAP24XX_SDRC_BASE + 0x064)
-#define SDRC_DLLB_CTRL          __REG32(OMAP24XX_SDRC_BASE + 0x068)
-#define SDRC_DLLB_STATUS        __REG32(OMAP24XX_SDRC_BASE + 0x06C)
-#define SDRC_POWER              __REG32(OMAP24XX_SDRC_BASE + 0x070)
-#define SDRC_MR_0               __REG32(OMAP24XX_SDRC_BASE + 0x084)
-
-/* GPIO 1 */
-#define GPIO1_BASE              GPIOX_BASE(1)
-#define GPIO1_REG32(offset)     __REG32(GPIO1_BASE + (offset))
-#define GPIO1_IRQENABLE1        GPIO1_REG32(0x01C)
-#define GPIO1_IRQSTATUS1        GPIO1_REG32(0x018)
-#define GPIO1_IRQENABLE2        GPIO1_REG32(0x02C)
-#define GPIO1_IRQSTATUS2        GPIO1_REG32(0x028)
-#define GPIO1_WAKEUPENABLE      GPIO1_REG32(0x020)
-#define GPIO1_RISINGDETECT      GPIO1_REG32(0x048)
-#define GPIO1_DATAIN            GPIO1_REG32(0x038)
-#define GPIO1_OE                GPIO1_REG32(0x034)
-#define GPIO1_DATAOUT           GPIO1_REG32(0x03C)
-
-/* GPIO2 */
-#define GPIO2_BASE              GPIOX_BASE(2)
-#define GPIO2_REG32(offset)     __REG32(GPIO2_BASE + (offset))
-#define GPIO2_IRQENABLE1        GPIO2_REG32(0x01C)
-#define GPIO2_IRQSTATUS1        GPIO2_REG32(0x018)
-#define GPIO2_IRQENABLE2        GPIO2_REG32(0x02C)
-#define GPIO2_IRQSTATUS2        GPIO2_REG32(0x028)
-#define GPIO2_WAKEUPENABLE      GPIO2_REG32(0x020)
-#define GPIO2_RISINGDETECT      GPIO2_REG32(0x048)
-#define GPIO2_DATAIN            GPIO2_REG32(0x038)
-#define GPIO2_OE                GPIO2_REG32(0x034)
-#define GPIO2_DATAOUT           GPIO2_REG32(0x03C)
-#define GPIO2_DEBOUNCENABLE     GPIO2_REG32(0x050)
-#define GPIO2_DEBOUNCINGTIME    GPIO2_REG32(0x054)
-
-/* GPIO 3 */
-#define GPIO3_BASE              GPIOX_BASE(3)
-#define GPIO3_REG32(offset)     __REG32(GPIO3_BASE + (offset))
-#define GPIO3_IRQENABLE1        GPIO3_REG32(0x01C)
-#define GPIO3_IRQSTATUS1        GPIO3_REG32(0x018)
-#define GPIO3_IRQENABLE2        GPIO3_REG32(0x02C)
-#define GPIO3_IRQSTATUS2        GPIO3_REG32(0x028)
-#define GPIO3_WAKEUPENABLE      GPIO3_REG32(0x020)
-#define GPIO3_RISINGDETECT      GPIO3_REG32(0x048)
-#define GPIO3_FALLINGDETECT     GPIO3_REG32(0x04C)
-#define GPIO3_DATAIN            GPIO3_REG32(0x038)
-#define GPIO3_OE                GPIO3_REG32(0x034)
-#define GPIO3_DATAOUT           GPIO3_REG32(0x03C)
-#define GPIO3_DEBOUNCENABLE     GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME    GPIO3_REG32(0x054)
-#define GPIO3_DEBOUNCENABLE     GPIO3_REG32(0x050)
-#define GPIO3_DEBOUNCINGTIME    GPIO3_REG32(0x054)
-
-/* GPIO 4 */
-#define GPIO4_BASE              GPIOX_BASE(4)
-#define GPIO4_REG32(offset)     __REG32(GPIO4_BASE + (offset))
-#define GPIO4_IRQENABLE1        GPIO4_REG32(0x01C)
-#define GPIO4_IRQSTATUS1        GPIO4_REG32(0x018)
-#define GPIO4_IRQENABLE2        GPIO4_REG32(0x02C)
-#define GPIO4_IRQSTATUS2        GPIO4_REG32(0x028)
-#define GPIO4_WAKEUPENABLE      GPIO4_REG32(0x020)
-#define GPIO4_RISINGDETECT      GPIO4_REG32(0x048)
-#define GPIO4_FALLINGDETECT     GPIO4_REG32(0x04C)
-#define GPIO4_DATAIN            GPIO4_REG32(0x038)
-#define GPIO4_OE                GPIO4_REG32(0x034)
-#define GPIO4_DATAOUT           GPIO4_REG32(0x03C)
-#define GPIO4_DEBOUNCENABLE     GPIO4_REG32(0x050)
-#define GPIO4_DEBOUNCINGTIME    GPIO4_REG32(0x054)
-
-#if defined(CONFIG_ARCH_OMAP243X)
-/* GPIO 5 */
-#define GPIO5_REG32(offset)     __REG32((OMAP24XX_GPIO5_BASE + (offset)))
-#define GPIO5_IRQENABLE1        GPIO5_REG32(0x01C)
-#define GPIO5_IRQSTATUS1        GPIO5_REG32(0x018)
-#define GPIO5_IRQENABLE2        GPIO5_REG32(0x02C)
-#define GPIO5_IRQSTATUS2        GPIO5_REG32(0x028)
-#define GPIO5_WAKEUPENABLE      GPIO5_REG32(0x020)
-#define GPIO5_RISINGDETECT      GPIO5_REG32(0x048)
-#define GPIO5_FALLINGDETECT     GPIO5_REG32(0x04C)
-#define GPIO5_DATAIN            GPIO5_REG32(0x038)
-#define GPIO5_OE                GPIO5_REG32(0x034)
-#define GPIO5_DATAOUT           GPIO5_REG32(0x03C)
-#define GPIO5_DEBOUNCENABLE     GPIO5_REG32(0x050)
-#define GPIO5_DEBOUNCINGTIME    GPIO5_REG32(0x054)
-#endif
-
-/* IO CONFIG */
-#define OMAP24XX_CTRL_BASE              (L4_24XX_BASE)
-#define CONTROL_REG32(offset)           __REG32(OMAP24XX_CTRL_BASE + (offset))
-
-#define CONTROL_PADCONF_SPI1_NCS2       CONTROL_REG32(0x104)
-#define CONTROL_PADCONF_SYS_XTALOUT     CONTROL_REG32(0x134)
-#define CONTROL_PADCONF_UART1_RX        CONTROL_REG32(0x0C8)
-#define CONTROL_PADCONF_MCBSP1_DX       CONTROL_REG32(0x10C)
-#define CONTROL_PADCONF_GPMC_NCS4       CONTROL_REG32(0x090)
-#define CONTROL_PADCONF_DSS_D5          CONTROL_REG32(0x0B8)
-#define CONTROL_PADCONF_DSS_D9          CONTROL_REG32(0x0BC)    /* 2420 */
-#define CONTROL_PADCONF_DSS_D13         CONTROL_REG32(0x0C0)
-#define CONTROL_PADCONF_DSS_VSYNC       CONTROL_REG32(0x0CC)
-#define CONTROL_PADCONF_SYS_NIRQW0      CONTROL_REG32(0x0BC)    /* 2430 */
-#define CONTROL_PADCONF_SSI1_FLAG_TX    CONTROL_REG32(0x108)    /* 2430 */
-
-/* CONTROL */
-#define CONTROL_DEVCONF         CONTROL_REG32(0x274)
-#define CONTROL_DEVCONF1        CONTROL_REG32(0x2E8)
-
-/* INTERRUPT CONTROLLER */
-#define INTC_BASE               ((L4_24XX_BASE) + 0xfe000)
-#define INTC_REG32(offset)      __REG32(INTC_BASE + (offset))
-
-#define INTC1_U_BASE            INTC_REG32(0x000)
-#define INTC_MIR0               INTC_REG32(0x084)
-#define INTC_MIR_SET0           INTC_REG32(0x08C)
-#define INTC_MIR_CLEAR0         INTC_REG32(0x088)
-#define INTC_ISR_CLEAR0         INTC_REG32(0x094)
-#define INTC_MIR1               INTC_REG32(0x0A4)
-#define INTC_MIR_SET1           INTC_REG32(0x0AC)
-#define INTC_MIR_CLEAR1         INTC_REG32(0x0A8)
-#define INTC_ISR_CLEAR1         INTC_REG32(0x0B4)
-#define INTC_MIR2               INTC_REG32(0x0C4)
-#define INTC_MIR_SET2           INTC_REG32(0x0CC)
-#define INTC_MIR_CLEAR2         INTC_REG32(0x0C8)
-#define INTC_ISR_CLEAR2         INTC_REG32(0x0D4)
-#define INTC_SIR_IRQ            INTC_REG32(0x040)
-#define INTC_CONTROL            INTC_REG32(0x048)
-#define INTC_ILR11              INTC_REG32(0x12C)       /* PRCM on MPU PIC */
-#define INTC_ILR30              INTC_REG32(0x178)
-#define INTC_ILR31              INTC_REG32(0x17C)
-#define INTC_ILR32              INTC_REG32(0x180)
-#define INTC_ILR37              INTC_REG32(0x194)       /* GPIO4 on MPU PIC */
-#define INTC_SYSCONFIG          INTC_REG32(0x010)       /* GPT1 on MPU PIC */
-
-/* RAM FIREWALL */
-#define RAMFW_BASE              (0x68005000)
-#define RAMFW_REG32(offset)     __REG32(RAMFW_BASE + (offset))
-
-#define RAMFW_REQINFOPERM0      RAMFW_REG32(0x048)
-#define RAMFW_READPERM0         RAMFW_REG32(0x050)
-#define RAMFW_WRITEPERM0        RAMFW_REG32(0x058)
-
-/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
-//#define DEBUG_BOARD_LED_REGISTER 0x04000014
-
-/* GPMC CS0 */
-#define GPMC_CONFIG1_0          GPMC_REG32(0x060)
-#define GPMC_CONFIG2_0          GPMC_REG32(0x064)
-#define GPMC_CONFIG3_0          GPMC_REG32(0x068)
-#define GPMC_CONFIG4_0          GPMC_REG32(0x06C)
-#define GPMC_CONFIG5_0          GPMC_REG32(0x070)
-#define GPMC_CONFIG6_0          GPMC_REG32(0x074)
-#define GPMC_CONFIG7_0          GPMC_REG32(0x078)
-
-/* GPMC CS1 */
-#define GPMC_CONFIG1_1          GPMC_REG32(0x090)
-#define GPMC_CONFIG2_1          GPMC_REG32(0x094)
-#define GPMC_CONFIG3_1          GPMC_REG32(0x098)
-#define GPMC_CONFIG4_1          GPMC_REG32(0x09C)
-#define GPMC_CONFIG5_1          GPMC_REG32(0x0a0)
-#define GPMC_CONFIG6_1          GPMC_REG32(0x0a4)
-#define GPMC_CONFIG7_1          GPMC_REG32(0x0a8)
-
-/* GPMC CS3 */
-#define GPMC_CONFIG1_3          GPMC_REG32(0x0F0)
-#define GPMC_CONFIG2_3          GPMC_REG32(0x0F4)
-#define GPMC_CONFIG3_3          GPMC_REG32(0x0F8)
-#define GPMC_CONFIG4_3          GPMC_REG32(0x0FC)
-#define GPMC_CONFIG5_3          GPMC_REG32(0x100)
-#define GPMC_CONFIG6_3          GPMC_REG32(0x104)
-#define GPMC_CONFIG7_3          GPMC_REG32(0x108)
-
-/* DSS */
-#define DSS_CONTROL             DISP_REG32(0x040)
-#define DISPC_CONTROL           DISP_REG32(0x440)
-#define DISPC_SYSSTATUS         DISP_REG32(0x414)
-#define DISPC_IRQSTATUS         DISP_REG32(0x418)
-#define DISPC_IRQENABLE         DISP_REG32(0x41C)
-#define DISPC_CONFIG            DISP_REG32(0x444)
-#define DISPC_DEFAULT_COLOR0    DISP_REG32(0x44C)
-#define DISPC_DEFAULT_COLOR1    DISP_REG32(0x450)
-#define DISPC_TRANS_COLOR0      DISP_REG32(0x454)
-#define DISPC_TRANS_COLOR1      DISP_REG32(0x458)
-#define DISPC_LINE_NUMBER       DISP_REG32(0x460)
-#define DISPC_TIMING_H          DISP_REG32(0x464)
-#define DISPC_TIMING_V          DISP_REG32(0x468)
-#define DISPC_POL_FREQ          DISP_REG32(0x46C)
-#define DISPC_DIVISOR           DISP_REG32(0x470)
-#define DISPC_SIZE_DIG          DISP_REG32(0x478)
-#define DISPC_SIZE_LCD          DISP_REG32(0x47C)
-#define DISPC_GFX_BA0           DISP_REG32(0x480)
-#define DISPC_GFX_BA1           DISP_REG32(0x484)
-#define DISPC_GFX_POSITION      DISP_REG32(0x488)
-#define DISPC_GFX_SIZE          DISP_REG32(0x48C)
-#define DISPC_GFX_ATTRIBUTES    DISP_REG32(0x4A0)
-#define DISPC_GFX_FIFO_THRESHOLD        DISP_REG32(0x4A4)
-#define DISPC_GFX_ROW_INC       DISP_REG32(0x4AC)
-#define DISPC_GFX_PIXEL_INC     DISP_REG32(0x4B0)
-#define DISPC_GFX_WINDOW_SKIP   DISP_REG32(0x4B4)
-#define DISPC_GFX_TABLE_BA      DISP_REG32(0x4B8)
-#define DISPC_DATA_CYCLE1       DISP_REG32(0x5D4)
-#define DISPC_DATA_CYCLE2       DISP_REG32(0x5D8)
-#define DISPC_DATA_CYCLE3       DISP_REG32(0x5DC)
-
-/* HSUSB Suspend */
-#define HSUSB_CTRL              __REG8(0x480AC001)
-#define USBOTG_POWER            __REG32(0x480AC000)
-
-/* HS MMC */
-#define MMCHS1_SYSCONFIG        __REG32(0x4809C010)
-#define MMCHS2_SYSCONFIG        __REG32(0x480b4010)
-
-#endif  /* __ASSEMBLER__ */
-
-#endif
-
-
-
-
-
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 90f530540c65..b12f423b8595 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,19 +17,27 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
-#include "prcm-regs.h"
+#include <asm/io.h>
+
+#include "prm.h"
+#include "prm-regbits-24xx.h"
 
 extern void omap2_clk_prepare_for_reboot(void);
 
 u32 omap_prcm_get_reset_sources(void)
 {
-        return RM_RSTST_WKUP & 0x7f;
+        return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 
 /* Resets clock rates and reboots the system. Only called from system.h */
 void omap_prcm_arch_reset(char mode)
 {
+        u32 wkup;
         omap2_clk_prepare_for_reboot();
-        RM_RSTCTRL_WKUP |= 2;
+
+        if (cpu_is_omap24xx()) {
+                wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
+                prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
+        }
 }
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
new file mode 100644
index 000000000000..c6d17a3378ec
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -0,0 +1,279 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Power/Reset Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Bits shared between registers */
+
+/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_ST                           (1 << 2)
+#define OMAP24XX_WKUP2_ST                               (1 << 1)
+#define OMAP24XX_WKUP1_ST                               (1 << 0)
+
+/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_EN                           (1 << 2)
+#define OMAP24XX_WKUP2_EN                               (1 << 1)
+#define OMAP24XX_WKUP1_EN                               (1 << 0)
+
+/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
+#define OMAP24XX_EN_MPU                                 (1 << 1)
+#define OMAP24XX_EN_CORE                                (1 << 0)
+
+/*
+ * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
+ * shared bits
+ */
+#define OMAP24XX_MEMONSTATE_SHIFT                       10
+#define OMAP24XX_MEMONSTATE_MASK                        (0x3 << 10)
+#define OMAP24XX_MEMRETSTATE                            (1 << 3)
+
+/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
+#define OMAP24XX_FORCESTATE                             (1 << 18)
+
+/*
+ * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
+ * PM_PWSTST_MDM shared bits
+ */
+#define OMAP24XX_CLKACTIVITY                            (1 << 19)
+
+/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
+#define OMAP24XX_LASTSTATEENTERED_SHIFT                 4
+#define OMAP24XX_LASTSTATEENTERED_MASK                  (0x3 << 4)
+
+/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
+#define OMAP2430_MEMSTATEST_SHIFT                       10
+#define OMAP2430_MEMSTATEST_MASK                        (0x3 << 10)
+
+/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
+#define OMAP24XX_POWERSTATEST_SHIFT                     0
+#define OMAP24XX_POWERSTATEST_MASK                      (0x3 << 0)
+
+
+/* Bits specific to each register */
+
+/* PRCM_REVISION */
+#define OMAP24XX_REV_SHIFT                              0
+#define OMAP24XX_REV_MASK                               (0xff << 0)
+
+/* PRCM_SYSCONFIG */
+#define OMAP24XX_AUTOIDLE                               (1 << 0)
+
+/* PRCM_IRQSTATUS_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_ST                          (1 << 6)
+#define OMAP24XX_TRANSITION_ST                          (1 << 5)
+#define OMAP24XX_EVGENOFF_ST                            (1 << 4)
+#define OMAP24XX_EVGENON_ST                             (1 << 3)
+
+/* PRCM_IRQENABLE_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_EN                          (1 << 6)
+#define OMAP24XX_TRANSITION_EN                          (1 << 5)
+#define OMAP24XX_EVGENOFF_EN                            (1 << 4)
+#define OMAP24XX_EVGENON_EN                             (1 << 3)
+
+/* PRCM_VOLTCTRL */
+#define OMAP24XX_AUTO_EXTVOLT                           (1 << 15)
+#define OMAP24XX_FORCE_EXTVOLT                          (1 << 14)
+#define OMAP24XX_SETOFF_LEVEL_SHIFT                     12
+#define OMAP24XX_SETOFF_LEVEL_MASK                      (0x3 << 12)
+#define OMAP24XX_MEMRETCTRL                             (1 << 8)
+#define OMAP24XX_SETRET_LEVEL_SHIFT                     6
+#define OMAP24XX_SETRET_LEVEL_MASK                      (0x3 << 6)
+#define OMAP24XX_VOLT_LEVEL_SHIFT                       0
+#define OMAP24XX_VOLT_LEVEL_MASK                        (0x3 << 0)
+
+/* PRCM_VOLTST */
+#define OMAP24XX_ST_VOLTLEVEL_SHIFT                     0
+#define OMAP24XX_ST_VOLTLEVEL_MASK                      (0x3 << 0)
+
+/* PRCM_CLKSRC_CTRL specific bits */
+
+/* PRCM_CLKOUT_CTRL */
+#define OMAP2420_CLKOUT2_EN_SHIFT                       15
+#define OMAP2420_CLKOUT2_EN                             (1 << 15)
+#define OMAP2420_CLKOUT2_DIV_SHIFT                      11
+#define OMAP2420_CLKOUT2_DIV_MASK                       (0x7 << 11)
+#define OMAP2420_CLKOUT2_SOURCE_SHIFT                   8
+#define OMAP2420_CLKOUT2_SOURCE_MASK                    (0x3 << 8)
+#define OMAP24XX_CLKOUT_EN_SHIFT                        7
+#define OMAP24XX_CLKOUT_EN                              (1 << 7)
+#define OMAP24XX_CLKOUT_DIV_SHIFT                       3
+#define OMAP24XX_CLKOUT_DIV_MASK                        (0x7 << 3)
+#define OMAP24XX_CLKOUT_SOURCE_SHIFT                    0
+#define OMAP24XX_CLKOUT_SOURCE_MASK                     (0x3 << 0)
+
+/* PRCM_CLKEMUL_CTRL */
+#define OMAP24XX_EMULATION_EN_SHIFT                     0
+#define OMAP24XX_EMULATION_EN                           (1 << 0)
+
+/* PRCM_CLKCFG_CTRL */
+#define OMAP24XX_VALID_CONFIG                           (1 << 0)
+
+/* PRCM_CLKCFG_STATUS */
+#define OMAP24XX_CONFIG_STATUS                          (1 << 0)
+
+/* PRCM_VOLTSETUP specific bits */
+
+/* PRCM_CLKSSETUP specific bits */
+
+/* PRCM_POLCTRL */
+#define OMAP2420_CLKOUT2_POL                            (1 << 10)
+#define OMAP24XX_CLKOUT_POL                             (1 << 9)
+#define OMAP24XX_CLKREQ_POL                             (1 << 8)
+#define OMAP2430_USE_POWEROK                            (1 << 2)
+#define OMAP2430_POWEROK_POL                            (1 << 1)
+#define OMAP24XX_EXTVOL_POL                             (1 << 0)
+
+/* RM_RSTST_MPU specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP2430_PM_WKDEP_MPU_EN_MDM                    (1 << 5)
+#define OMAP24XX_PM_WKDEP_MPU_EN_DSP                    (1 << 2)
+
+/* PM_EVGENCTRL_MPU specific bits */
+
+/* PM_EVEGENONTIM_MPU specific bits */
+
+/* PM_EVEGENOFFTIM_MPU specific bits */
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP2430_FORCESTATE                             (1 << 18)
+
+/* PM_PWSTST_MPU specific bits */
+/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_WKEN2_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits*/
+
+/* PM_WKST2_CORE specific bits */
+
+/* PM_WKDEP_CORE specific bits*/
+#define OMAP2430_PM_WKDEP_CORE_EN_MDM                   (1 << 5)
+#define OMAP24XX_PM_WKDEP_CORE_EN_GFX                   (1 << 3)
+#define OMAP24XX_PM_WKDEP_CORE_EN_DSP                   (1 << 2)
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP24XX_MEMORYCHANGE                           (1 << 20)
+#define OMAP24XX_MEM3ONSTATE_SHIFT                      14
+#define OMAP24XX_MEM3ONSTATE_MASK                       (0x3 << 14)
+#define OMAP24XX_MEM2ONSTATE_SHIFT                      12
+#define OMAP24XX_MEM2ONSTATE_MASK                       (0x3 << 12)
+#define OMAP24XX_MEM1ONSTATE_SHIFT                      10
+#define OMAP24XX_MEM1ONSTATE_MASK                       (0x3 << 10)
+#define OMAP24XX_MEM3RETSTATE                           (1 << 5)
+#define OMAP24XX_MEM2RETSTATE                           (1 << 4)
+#define OMAP24XX_MEM1RETSTATE                           (1 << 3)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP24XX_MEM3STATEST_SHIFT                      14
+#define OMAP24XX_MEM3STATEST_MASK                       (0x3 << 14)
+#define OMAP24XX_MEM2STATEST_SHIFT                      12
+#define OMAP24XX_MEM2STATEST_MASK                       (0x3 << 12)
+#define OMAP24XX_MEM1STATEST_SHIFT                      10
+#define OMAP24XX_MEM1STATEST_MASK                       (0x3 << 10)
+
+/* RM_RSTCTRL_GFX */
+#define OMAP24XX_GFX_RST                                (1 << 0)
+
+/* RM_RSTST_GFX specific bits */
+#define OMAP24XX_GFX_SW_RST                             (1 << 4)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+/* 2430 often calls EN_WAKEUP "EN_WKUP" */
+
+/* RM_RSTCTRL_WKUP specific bits */
+
+/* RM_RSTTIME_WKUP specific bits */
+
+/* RM_RSTST_WKUP specific bits */
+/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP24XX_EXTWMPU_RST                            (1 << 6)
+#define OMAP24XX_SECU_WD_RST                            (1 << 5)
+#define OMAP24XX_MPU_WD_RST                             (1 << 4)
+#define OMAP24XX_SECU_VIOL_RST                          (1 << 3)
+
+/* PM_WKEN_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+
+/* RM_RSTCTRL_DSP */
+#define OMAP2420_RST_IVA                                (1 << 8)
+#define OMAP24XX_RST2_DSP                               (1 << 1)
+#define OMAP24XX_RST1_DSP                               (1 << 0)
+
+/* RM_RSTST_DSP specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP2420_IVA_SW_RST                             (1 << 8)
+#define OMAP24XX_DSP_SW_RST2                            (1 << 5)
+#define OMAP24XX_DSP_SW_RST1                            (1 << 4)
+
+/* PM_WKDEP_DSP specific bits */
+
+/* PM_PWSTCTRL_DSP specific bits */
+/* 2430 only: MEMONSTATE, MEMRETSTATE */
+#define OMAP2420_MEMIONSTATE_SHIFT                      12
+#define OMAP2420_MEMIONSTATE_MASK                       (0x3 << 12)
+#define OMAP2420_MEMIRETSTATE                           (1 << 4)
+
+/* PM_PWSTST_DSP specific bits */
+/* MEMSTATEST is 2430 only */
+#define OMAP2420_MEMISTATEST_SHIFT                      12
+#define OMAP2420_MEMISTATEST_MASK                       (0x3 << 12)
+
+/* PRCM_IRQSTATUS_DSP specific bits */
+
+/* PRCM_IRQENABLE_DSP specific bits */
+
+/* RM_RSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_PWRON1_MDM                             (1 << 1)
+#define OMAP2430_RST1_MDM                               (1 << 0)
+
+/* RM_RSTST_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_MDM_SECU_VIOL                          (1 << 6)
+#define OMAP2430_MDM_SW_PWRON1                          (1 << 5)
+#define OMAP2430_MDM_SW_RST1                            (1 << 4)
+
+/* PM_WKEN_MDM */
+/* 2430 only */
+#define OMAP2430_PM_WKEN_MDM_EN_MDM                     (1 << 0)
+
+/* PM_WKST_MDM specific bits */
+/* 2430 only */
+
+/* PM_WKDEP_MDM specific bits */
+/* 2430 only */
+
+/* PM_PWSTCTRL_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_KILLDOMAINWKUP                         (1 << 19)
+
+/* PM_PWSTST_MDM specific bits */
+/* 2430 only */
+
+/* PRCM_IRQSTATUS_IVA */
+/* 2420 only */
+
+/* PRCM_IRQENABLE_IVA */
+/* 2420 only */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
new file mode 100644
index 000000000000..b4686bc345ca
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -0,0 +1,582 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+
+/*
+ * OMAP3430 Power/Reset Management register bits
+ *
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Shared register bits */
+
+/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
+#define OMAP3430_ON_SHIFT                               24
+#define OMAP3430_ON_MASK                                (0xff << 24)
+#define OMAP3430_ONLP_SHIFT                             16
+#define OMAP3430_ONLP_MASK                              (0xff << 16)
+#define OMAP3430_RET_SHIFT                              8
+#define OMAP3430_RET_MASK                               (0xff << 8)
+#define OMAP3430_OFF_SHIFT                              0
+#define OMAP3430_OFF_MASK                               (0xff << 0)
+
+/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
+#define OMAP3430_ERROROFFSET_SHIFT                      24
+#define OMAP3430_ERROROFFSET_MASK                       (0xff << 24)
+#define OMAP3430_ERRORGAIN_SHIFT                        16
+#define OMAP3430_ERRORGAIN_MASK                         (0xff << 16)
+#define OMAP3430_INITVOLTAGE_SHIFT                      8
+#define OMAP3430_INITVOLTAGE_MASK                       (0xff << 8)
+#define OMAP3430_TIMEOUTEN                              (1 << 3)
+#define OMAP3430_INITVDD                                (1 << 2)
+#define OMAP3430_FORCEUPDATE                            (1 << 1)
+#define OMAP3430_VPENABLE                               (1 << 0)
+
+/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
+#define OMAP3430_SMPSWAITTIMEMIN_SHIFT                  8
+#define OMAP3430_SMPSWAITTIMEMIN_MASK                   (0xffff << 8)
+#define OMAP3430_VSTEPMIN_SHIFT                         0
+#define OMAP3430_VSTEPMIN_MASK                          (0xff << 0)
+
+/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
+#define OMAP3430_SMPSWAITTIMEMAX_SHIFT                  8
+#define OMAP3430_SMPSWAITTIMEMAX_MASK                   (0xffff << 8)
+#define OMAP3430_VSTEPMAX_SHIFT                         0
+#define OMAP3430_VSTEPMAX_MASK                          (0xff << 0)
+
+/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
+#define OMAP3430_VDDMAX_SHIFT                           24
+#define OMAP3430_VDDMAX_MASK                            (0xff << 24)
+#define OMAP3430_VDDMIN_SHIFT                           16
+#define OMAP3430_VDDMIN_MASK                            (0xff << 16)
+#define OMAP3430_TIMEOUT_SHIFT                          0
+#define OMAP3430_TIMEOUT_MASK                           (0xffff << 0)
+
+/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
+#define OMAP3430_VPVOLTAGE_SHIFT                        0
+#define OMAP3430_VPVOLTAGE_MASK                         (0xff << 0)
+
+/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
+#define OMAP3430_VPINIDLE                               (1 << 0)
+
+/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
+#define OMAP3430_EN_PER                                 (1 << 7)
+
+/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
+#define OMAP3430_MEMORYCHANGE                           (1 << 3)
+
+/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
+#define OMAP3430_LOGICSTATEST                           (1 << 2)
+
+/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
+#define OMAP3430_LASTLOGICSTATEENTERED                          (1 << 2)
+
+/*
+ * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
+ * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
+ * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
+ */
+#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT                    0
+#define OMAP3430_LASTPOWERSTATEENTERED_MASK                     (0x3 << 0)
+
+/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
+#define OMAP3430_WKUP_ST                                (1 << 0)
+
+/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
+#define OMAP3430_WKUP_EN                                        (1 << 0)
+
+/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
+#define OMAP3430_GRPSEL_MMC2                            (1 << 25)
+#define OMAP3430_GRPSEL_MMC1                            (1 << 24)
+#define OMAP3430_GRPSEL_MCSPI4                          (1 << 21)
+#define OMAP3430_GRPSEL_MCSPI3                          (1 << 20)
+#define OMAP3430_GRPSEL_MCSPI2                          (1 << 19)
+#define OMAP3430_GRPSEL_MCSPI1                          (1 << 18)
+#define OMAP3430_GRPSEL_I2C3                            (1 << 17)
+#define OMAP3430_GRPSEL_I2C2                            (1 << 16)
+#define OMAP3430_GRPSEL_I2C1                            (1 << 15)
+#define OMAP3430_GRPSEL_UART2                           (1 << 14)
+#define OMAP3430_GRPSEL_UART1                           (1 << 13)
+#define OMAP3430_GRPSEL_GPT11                           (1 << 12)
+#define OMAP3430_GRPSEL_GPT10                           (1 << 11)
+#define OMAP3430_GRPSEL_MCBSP5                          (1 << 10)
+#define OMAP3430_GRPSEL_MCBSP1                          (1 << 9)
+#define OMAP3430_GRPSEL_HSOTGUSB                        (1 << 4)
+#define OMAP3430_GRPSEL_D2D                             (1 << 3)
+
+/*
+ * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
+ * PM_PWSTCTRL_PER shared bits
+ */
+#define OMAP3430_MEMONSTATE_SHIFT                       16
+#define OMAP3430_MEMONSTATE_MASK                        (0x3 << 16)
+#define OMAP3430_MEMRETSTATE                            (1 << 8)
+
+/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3430_GRPSEL_GPIO6                           (1 << 17)
+#define OMAP3430_GRPSEL_GPIO5                           (1 << 16)
+#define OMAP3430_GRPSEL_GPIO4                           (1 << 15)
+#define OMAP3430_GRPSEL_GPIO3                           (1 << 14)
+#define OMAP3430_GRPSEL_GPIO2                           (1 << 13)
+#define OMAP3430_GRPSEL_UART3                           (1 << 11)
+#define OMAP3430_GRPSEL_GPT9                            (1 << 10)
+#define OMAP3430_GRPSEL_GPT8                            (1 << 9)
+#define OMAP3430_GRPSEL_GPT7                            (1 << 8)
+#define OMAP3430_GRPSEL_GPT6                            (1 << 7)
+#define OMAP3430_GRPSEL_GPT5                            (1 << 6)
+#define OMAP3430_GRPSEL_GPT4                            (1 << 5)
+#define OMAP3430_GRPSEL_GPT3                            (1 << 4)
+#define OMAP3430_GRPSEL_GPT2                            (1 << 3)
+#define OMAP3430_GRPSEL_MCBSP4                          (1 << 2)
+#define OMAP3430_GRPSEL_MCBSP3                          (1 << 1)
+#define OMAP3430_GRPSEL_MCBSP2                          (1 << 0)
+
+/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
+#define OMAP3430_GRPSEL_IO                              (1 << 8)
+#define OMAP3430_GRPSEL_SR2                             (1 << 7)
+#define OMAP3430_GRPSEL_SR1                             (1 << 6)
+#define OMAP3430_GRPSEL_GPIO1                           (1 << 3)
+#define OMAP3430_GRPSEL_GPT12                           (1 << 1)
+#define OMAP3430_GRPSEL_GPT1                            (1 << 0)
+
+/* Bits specific to each register */
+
+/* RM_RSTCTRL_IVA2 */
+#define OMAP3430_RST3_IVA2                              (1 << 2)
+#define OMAP3430_RST2_IVA2                              (1 << 1)
+#define OMAP3430_RST1_IVA2                              (1 << 0)
+
+/* RM_RSTST_IVA2 specific bits */
+#define OMAP3430_EMULATION_VSEQ_RST                     (1 << 13)
+#define OMAP3430_EMULATION_VHWA_RST                     (1 << 12)
+#define OMAP3430_EMULATION_IVA2_RST                     (1 << 11)
+#define OMAP3430_IVA2_SW_RST3                           (1 << 10)
+#define OMAP3430_IVA2_SW_RST2                           (1 << 9)
+#define OMAP3430_IVA2_SW_RST1                           (1 << 8)
+
+/* PM_WKDEP_IVA2 specific bits */
+
+/* PM_PWSTCTRL_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMONSTATE_SHIFT                 22
+#define OMAP3430_L2FLATMEMONSTATE_MASK                  (0x3 << 22)
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT         20
+#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK          (0x3 << 20)
+#define OMAP3430_L1FLATMEMONSTATE_SHIFT                 18
+#define OMAP3430_L1FLATMEMONSTATE_MASK                  (0x3 << 18)
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT         16
+#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK          (0x3 << 16)
+#define OMAP3430_L2FLATMEMRETSTATE                      (1 << 11)
+#define OMAP3430_SHAREDL2CACHEFLATRETSTATE              (1 << 10)
+#define OMAP3430_L1FLATMEMRETSTATE                      (1 << 9)
+#define OMAP3430_SHAREDL1CACHEFLATRETSTATE              (1 << 8)
+
+/* PM_PWSTST_IVA2 specific bits */
+#define OMAP3430_L2FLATMEMSTATEST_SHIFT                 10
+#define OMAP3430_L2FLATMEMSTATEST_MASK                  (0x3 << 10)
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT         8
+#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK          (0x3 << 8)
+#define OMAP3430_L1FLATMEMSTATEST_SHIFT                 6
+#define OMAP3430_L1FLATMEMSTATEST_MASK                  (0x3 << 6)
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT         4
+#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK          (0x3 << 4)
+
+/* PM_PREPWSTST_IVA2 specific bits */
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT                10
+#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK                 (0x3 << 10)
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT        8
+#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK         (0x3 << 8)
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT                6
+#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK                 (0x3 << 6)
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT        4
+#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK         (0x3 << 4)
+
+/* PRM_IRQSTATUS_IVA2 specific bits */
+#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST        (1 << 2)
+#define OMAP3430_FORCEWKUP_ST                           (1 << 1)
+
+/* PRM_IRQENABLE_IVA2 specific bits */
+#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN          (1 << 2)
+#define OMAP3430_FORCEWKUP_EN                                   (1 << 1)
+
+/* PRM_REVISION specific bits */
+
+/* PRM_SYSCONFIG specific bits */
+
+/* PRM_IRQSTATUS_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT            25
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST                  (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_ST                       (1 << 24)
+#define OMAP3430_VC_RAERR_ST                            (1 << 23)
+#define OMAP3430_VC_SAERR_ST                            (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_ST                       (1 << 21)
+#define OMAP3430_VP2_EQVALUE_ST                         (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_ST                       (1 << 19)
+#define OMAP3430_VP2_MAXVDD_ST                          (1 << 18)
+#define OMAP3430_VP2_MINVDD_ST                          (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_ST                   (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_ST                       (1 << 15)
+#define OMAP3430_VP1_EQVALUE_ST                         (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_ST                       (1 << 13)
+#define OMAP3430_VP1_MAXVDD_ST                          (1 << 12)
+#define OMAP3430_VP1_MINVDD_ST                          (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_ST                   (1 << 10)
+#define OMAP3430_IO_ST                                  (1 << 9)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST         (1 << 8)
+#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT   8
+#define OMAP3430_MPU_DPLL_ST                            (1 << 7)
+#define OMAP3430_MPU_DPLL_ST_SHIFT                      7
+#define OMAP3430_PERIPH_DPLL_ST                         (1 << 6)
+#define OMAP3430_PERIPH_DPLL_ST_SHIFT                   6
+#define OMAP3430_CORE_DPLL_ST                           (1 << 5)
+#define OMAP3430_CORE_DPLL_ST_SHIFT                     5
+#define OMAP3430_TRANSITION_ST                          (1 << 4)
+#define OMAP3430_EVGENOFF_ST                            (1 << 3)
+#define OMAP3430_EVGENON_ST                             (1 << 2)
+#define OMAP3430_FS_USB_WKUP_ST                         (1 << 1)
+
+/* PRM_IRQENABLE_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT              25
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN                    (1 << 25)
+#define OMAP3430_VC_TIMEOUTERR_EN                               (1 << 24)
+#define OMAP3430_VC_RAERR_EN                                    (1 << 23)
+#define OMAP3430_VC_SAERR_EN                                    (1 << 22)
+#define OMAP3430_VP2_TRANXDONE_EN                               (1 << 21)
+#define OMAP3430_VP2_EQVALUE_EN                                 (1 << 20)
+#define OMAP3430_VP2_NOSMPSACK_EN                               (1 << 19)
+#define OMAP3430_VP2_MAXVDD_EN                                  (1 << 18)
+#define OMAP3430_VP2_MINVDD_EN                                  (1 << 17)
+#define OMAP3430_VP2_OPPCHANGEDONE_EN                           (1 << 16)
+#define OMAP3430_VP1_TRANXDONE_EN                               (1 << 15)
+#define OMAP3430_VP1_EQVALUE_EN                                 (1 << 14)
+#define OMAP3430_VP1_NOSMPSACK_EN                               (1 << 13)
+#define OMAP3430_VP1_MAXVDD_EN                                  (1 << 12)
+#define OMAP3430_VP1_MINVDD_EN                                  (1 << 11)
+#define OMAP3430_VP1_OPPCHANGEDONE_EN                           (1 << 10)
+#define OMAP3430_IO_EN                                          (1 << 9)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN           (1 << 8)
+#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT     8
+#define OMAP3430_MPU_DPLL_RECAL_EN                              (1 << 7)
+#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT                        7
+#define OMAP3430_PERIPH_DPLL_RECAL_EN                           (1 << 6)
+#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT                     6
+#define OMAP3430_CORE_DPLL_RECAL_EN                             (1 << 5)
+#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT                       5
+#define OMAP3430_TRANSITION_EN                                  (1 << 4)
+#define OMAP3430_EVGENOFF_EN                                    (1 << 3)
+#define OMAP3430_EVGENON_EN                                     (1 << 2)
+#define OMAP3430_FS_USB_WKUP_EN                                 (1 << 1)
+
+/* RM_RSTST_MPU specific bits */
+#define OMAP3430_EMULATION_MPU_RST                      (1 << 11)
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP3430_PM_WKDEP_MPU_EN_DSS                    (1 << 5)
+#define OMAP3430_PM_WKDEP_MPU_EN_IVA2                   (1 << 2)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP3430_OFFLOADMODE_SHIFT                      3
+#define OMAP3430_OFFLOADMODE_MASK                       (0x3 << 3)
+#define OMAP3430_ONLOADMODE_SHIFT                       1
+#define OMAP3430_ONLOADMODE_MASK                        (0x3 << 1)
+#define OMAP3430_ENABLE                                 (1 << 0)
+
+/* PM_EVGENONTIM_MPU */
+#define OMAP3430_ONTIMEVAL_SHIFT                        0
+#define OMAP3430_ONTIMEVAL_MASK                         (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+#define OMAP3430_OFFTIMEVAL_SHIFT                       0
+#define OMAP3430_OFFTIMEVAL_MASK                        (0xffffffff << 0)
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP3430_L2CACHEONSTATE_SHIFT                   16
+#define OMAP3430_L2CACHEONSTATE_MASK                    (0x3 << 16)
+#define OMAP3430_L2CACHERETSTATE                        (1 << 8)
+#define OMAP3430_LOGICL1CACHERETSTATE                   (1 << 2)
+
+/* PM_PWSTST_MPU specific bits */
+#define OMAP3430_L2CACHESTATEST_SHIFT                   6
+#define OMAP3430_L2CACHESTATEST_MASK                    (0x3 << 6)
+#define OMAP3430_LOGICL1CACHESTATEST                    (1 << 2)
+
+/* PM_PREPWSTST_MPU specific bits */
+#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT          6
+#define OMAP3430_LASTL2CACHESTATEENTERED_MASK           (0x3 << 6)
+#define OMAP3430_LASTLOGICL1CACHESTATEENTERED           (1 << 2)
+
+/* RM_RSTCTRL_CORE */
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON              (1 << 1)
+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST                   (1 << 0)
+
+/* RM_RSTST_CORE specific bits */
+#define OMAP3430_MODEM_SECURITY_VIOL_RST                (1 << 10)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON        (1 << 9)
+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST             (1 << 8)
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_MPUGRPSEL1_CORE specific bits */
+#define OMAP3430_GRPSEL_FSHOSTUSB                       (1 << 5)
+
+/* PM_IVA2GRPSEL1_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits */
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP3430_MEM2ONSTATE_SHIFT                      18
+#define OMAP3430_MEM2ONSTATE_MASK                       (0x3 << 18)
+#define OMAP3430_MEM1ONSTATE_SHIFT                      16
+#define OMAP3430_MEM1ONSTATE_MASK                       (0x3 << 16)
+#define OMAP3430_MEM2RETSTATE                           (1 << 9)
+#define OMAP3430_MEM1RETSTATE                           (1 << 8)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP3430_MEM2STATEST_SHIFT                      6
+#define OMAP3430_MEM2STATEST_MASK                       (0x3 << 6)
+#define OMAP3430_MEM1STATEST_SHIFT                      4
+#define OMAP3430_MEM1STATEST_MASK                       (0x3 << 4)
+
+/* PM_PREPWSTST_CORE specific bits */
+#define OMAP3430_LASTMEM2STATEENTERED_SHIFT             6
+#define OMAP3430_LASTMEM2STATEENTERED_MASK              (0x3 << 6)
+#define OMAP3430_LASTMEM1STATEENTERED_SHIFT             4
+#define OMAP3430_LASTMEM1STATEENTERED_MASK              (0x3 << 4)
+
+/* RM_RSTST_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+#define OMAP3430_PM_WKDEP_GFX_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_PWSTST_GFX specific bits */
+
+/* PM_PREPWSTST_GFX specific bits */
+
+/* PM_WKEN_WKUP specific bits */
+#define OMAP3430_EN_IO                                  (1 << 8)
+
+/* PM_MPUGRPSEL_WKUP specific bits */
+
+/* PM_IVA2GRPSEL_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+#define OMAP3430_ST_IO                                  (1 << 8)
+
+/* PRM_CLKSEL */
+#define OMAP3430_SYS_CLKIN_SEL_SHIFT                    0
+#define OMAP3430_SYS_CLKIN_SEL_MASK                     (0x7 << 0)
+
+/* PRM_CLKOUT_CTRL */
+#define OMAP3430_CLKOUT_EN                              (1 << 7)
+#define OMAP3430_CLKOUT_EN_SHIFT                        7
+
+/* RM_RSTST_DSS specific bits */
+
+/* PM_WKEN_DSS */
+#define OMAP3430_PM_WKEN_DSS_EN_DSS                     (1 << 0)
+
+/* PM_WKDEP_DSS specific bits */
+#define OMAP3430_PM_WKDEP_DSS_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_DSS specific bits */
+
+/* PM_PWSTST_DSS specific bits */
+
+/* PM_PREPWSTST_DSS specific bits */
+
+/* RM_RSTST_CAM specific bits */
+
+/* PM_WKDEP_CAM specific bits */
+#define OMAP3430_PM_WKDEP_CAM_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_CAM specific bits */
+
+/* PM_PWSTST_CAM specific bits */
+
+/* PM_PREPWSTST_CAM specific bits */
+
+/* PM_PWSTCTRL_USBHOST specific bits */
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT                (1 << 4)
+
+/* RM_RSTST_PER specific bits */
+
+/* PM_WKEN_PER specific bits */
+
+/* PM_MPUGRPSEL_PER specific bits */
+
+/* PM_IVA2GRPSEL_PER specific bits */
+
+/* PM_WKST_PER specific bits */
+
+/* PM_WKDEP_PER specific bits */
+#define OMAP3430_PM_WKDEP_PER_EN_IVA2                   (1 << 2)
+
+/* PM_PWSTCTRL_PER specific bits */
+
+/* PM_PWSTST_PER specific bits */
+
+/* PM_PREPWSTST_PER specific bits */
+
+/* RM_RSTST_EMU specific bits */
+
+/* PM_PWSTST_EMU specific bits */
+
+/* PRM_VC_SMPS_SA */
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT               16
+#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK                (0x7f << 16)
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT               0
+#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK                (0x7f << 0)
+
+/* PRM_VC_SMPS_VOL_RA */
+#define OMAP3430_VOLRA1_SHIFT                           16
+#define OMAP3430_VOLRA1_MASK                            (0xff << 16)
+#define OMAP3430_VOLRA0_SHIFT                           0
+#define OMAP3430_VOLRA0_MASK                            (0xff << 0)
+
+/* PRM_VC_SMPS_CMD_RA */
+#define OMAP3430_CMDRA1_SHIFT                           16
+#define OMAP3430_CMDRA1_MASK                            (0xff << 16)
+#define OMAP3430_CMDRA0_SHIFT                           0
+#define OMAP3430_CMDRA0_MASK                            (0xff << 0)
+
+/* PRM_VC_CMD_VAL_0 specific bits */
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+
+/* PRM_VC_CH_CONF */
+#define OMAP3430_CMD1                                   (1 << 20)
+#define OMAP3430_RACEN1                                 (1 << 19)
+#define OMAP3430_RAC1                                   (1 << 18)
+#define OMAP3430_RAV1                                   (1 << 17)
+#define OMAP3430_PRM_VC_CH_CONF_SA1                     (1 << 16)
+#define OMAP3430_CMD0                                   (1 << 4)
+#define OMAP3430_RACEN0                                 (1 << 3)
+#define OMAP3430_RAC0                                   (1 << 2)
+#define OMAP3430_RAV0                                   (1 << 1)
+#define OMAP3430_PRM_VC_CH_CONF_SA0                     (1 << 0)
+
+/* PRM_VC_I2C_CFG */
+#define OMAP3430_HSMASTER                               (1 << 5)
+#define OMAP3430_SREN                                   (1 << 4)
+#define OMAP3430_HSEN                                   (1 << 3)
+#define OMAP3430_MCODE_SHIFT                            0
+#define OMAP3430_MCODE_MASK                             (0x7 << 0)
+
+/* PRM_VC_BYPASS_VAL */
+#define OMAP3430_VALID                                  (1 << 24)
+#define OMAP3430_DATA_SHIFT                             16
+#define OMAP3430_DATA_MASK                              (0xff << 16)
+#define OMAP3430_REGADDR_SHIFT                          8
+#define OMAP3430_REGADDR_MASK                           (0xff << 8)
+#define OMAP3430_SLAVEADDR_SHIFT                        0
+#define OMAP3430_SLAVEADDR_MASK                         (0x7f << 0)
+
+/* PRM_RSTCTRL */
+#define OMAP3430_RST_DPLL3                              (1 << 2)
+#define OMAP3430_RST_GS                                 (1 << 1)
+
+/* PRM_RSTTIME */
+#define OMAP3430_RSTTIME2_SHIFT                         8
+#define OMAP3430_RSTTIME2_MASK                          (0x1f << 8)
+#define OMAP3430_RSTTIME1_SHIFT                         0
+#define OMAP3430_RSTTIME1_MASK                          (0xff << 0)
+
+/* PRM_RSTST */
+#define OMAP3430_ICECRUSHER_RST                         (1 << 10)
+#define OMAP3430_ICEPICK_RST                            (1 << 9)
+#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST               (1 << 8)
+#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST               (1 << 7)
+#define OMAP3430_EXTERNAL_WARM_RST                      (1 << 6)
+#define OMAP3430_SECURE_WD_RST                          (1 << 5)
+#define OMAP3430_MPU_WD_RST                             (1 << 4)
+#define OMAP3430_SECURITY_VIOL_RST                      (1 << 3)
+#define OMAP3430_GLOBAL_SW_RST                          (1 << 1)
+#define OMAP3430_GLOBAL_COLD_RST                        (1 << 0)
+
+/* PRM_VOLTCTRL */
+#define OMAP3430_SEL_VMODE                              (1 << 4)
+#define OMAP3430_SEL_OFF                                (1 << 3)
+#define OMAP3430_AUTO_OFF                               (1 << 2)
+#define OMAP3430_AUTO_RET                               (1 << 1)
+#define OMAP3430_AUTO_SLEEP                             (1 << 0)
+
+/* PRM_SRAM_PCHARGE */
+#define OMAP3430_PCHARGE_TIME_SHIFT                     0
+#define OMAP3430_PCHARGE_TIME_MASK                      (0xff << 0)
+
+/* PRM_CLKSRC_CTRL */
+#define OMAP3430_SYSCLKDIV_SHIFT                        6
+#define OMAP3430_SYSCLKDIV_MASK                         (0x3 << 6)
+#define OMAP3430_AUTOEXTCLKMODE_SHIFT                   3
+#define OMAP3430_AUTOEXTCLKMODE_MASK                    (0x3 << 3)
+#define OMAP3430_SYSCLKSEL_SHIFT                        0
+#define OMAP3430_SYSCLKSEL_MASK                         (0x3 << 0)
+
+/* PRM_VOLTSETUP1 */
+#define OMAP3430_SETUP_TIME2_SHIFT                      16
+#define OMAP3430_SETUP_TIME2_MASK                       (0xffff << 16)
+#define OMAP3430_SETUP_TIME1_SHIFT                      0
+#define OMAP3430_SETUP_TIME1_MASK                       (0xffff << 0)
+
+/* PRM_VOLTOFFSET */
+#define OMAP3430_OFFSET_TIME_SHIFT                      0
+#define OMAP3430_OFFSET_TIME_MASK                       (0xffff << 0)
+
+/* PRM_CLKSETUP */
+#define OMAP3430_SETUP_TIME_SHIFT                       0
+#define OMAP3430_SETUP_TIME_MASK                        (0xffff << 0)
+
+/* PRM_POLCTRL */
+#define OMAP3430_OFFMODE_POL                            (1 << 3)
+#define OMAP3430_CLKOUT_POL                             (1 << 2)
+#define OMAP3430_CLKREQ_POL                             (1 << 1)
+#define OMAP3430_EXTVOL_POL                             (1 << 0)
+
+/* PRM_VOLTSETUP2 */
+#define OMAP3430_OFFMODESETUPTIME_SHIFT                 0
+#define OMAP3430_OFFMODESETUPTIME_MASK                  (0xffff << 0)
+
+/* PRM_VP1_CONFIG specific bits */
+
+/* PRM_VP1_VSTEPMIN specific bits */
+
+/* PRM_VP1_VSTEPMAX specific bits */
+
+/* PRM_VP1_VLIMITTO specific bits */
+
+/* PRM_VP1_VOLTAGE specific bits */
+
+/* PRM_VP1_STATUS specific bits */
+
+/* PRM_VP2_CONFIG specific bits */
+
+/* PRM_VP2_VSTEPMIN specific bits */
+
+/* PRM_VP2_VSTEPMAX specific bits */
+
+/* PRM_VP2_VLIMITTO specific bits */
+
+/* PRM_VP2_VOLTAGE specific bits */
+
+/* PRM_VP2_STATUS specific bits */
+
+/* RM_RSTST_NEON specific bits */
+
+/* PM_WKDEP_NEON specific bits */
+
+/* PM_PWSTCTRL_NEON specific bits */
+
+/* PM_PWSTST_NEON specific bits */
+
+/* PM_PREPWSTST_NEON specific bits */
+
+#endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
new file mode 100644
index 000000000000..ab7649afd891
--- /dev/null
+++ b/arch/arm/mach-omap2/prm.h
@@ -0,0 +1,316 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_H
+
+/*
+ * OMAP2/3 Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prcm-common.h"
+
+#ifndef __ASSEMBLER__
+#define OMAP_PRM_REGADDR(module, reg)                                   \
+        (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
+#else
+#define OMAP2420_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+#define OMAP34XX_PRM_REGADDR(module, reg)                               \
+                        IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+#endif
+
+/*
+ * Architecture-specific global PRM registers
+ * Use prm_{read,write}_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ *
+ */
+
+#define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP24XX_PRCM_VOLTCTRL          OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP24XX_PRCM_CLKCFG_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP24XX_PRCM_CLKCFG_STATUS     OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP24XX_PRCM_VOLTSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP24XX_PRCM_CLKSSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP24XX_PRCM_POLCTRL           OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP3430_PRM_REVISION           OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3430_PRM_SYSCONFIG          OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3430_PRM_IRQENABLE_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+
+#define OMAP3430_PRM_VC_SMPS_SA         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3430_PRM_VC_CH_CONF         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3430_PRM_VC_I2C_CFG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3430_PRM_RSTCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3430_PRM_RSTTIME            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3430_PRM_RSTST              OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3430_PRM_VOLTCTRL           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3430_PRM_SRAM_PCHARGE       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3430_PRM_CLKSRC_CTRL        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3430_PRM_VOLTSETUP1         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3430_PRM_VOLTOFFSET         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3430_PRM_CLKSETUP           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3430_PRM_POLCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3430_PRM_VOLTSETUP2         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3430_PRM_VP1_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3430_PRM_VP1_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3430_PRM_VP1_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3430_PRM_VP1_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3430_PRM_VP2_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3430_PRM_VP2_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3430_PRM_VP2_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3430_PRM_VP2_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+
+#define OMAP3430_PRM_CLKSEL             OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3430_PRM_CLKOUT_CTRL        OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific PRM registers from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
+ * and IRQENABLE bits.)
+ *
+ */
+
+/* Registers appearing on both 24xx and 34xx */
+
+#define RM_RSTCTRL                                      0x0050
+#define RM_RSTTIME                                      0x0054
+#define RM_RSTST                                        0x0058
+
+#define PM_WKEN                                         0x00a0
+#define PM_WKEN1                                        PM_WKEN
+#define PM_WKST                                         0x00b0
+#define PM_WKST1                                        PM_WKST
+#define PM_WKDEP                                        0x00c8
+#define PM_EVGENCTRL                                    0x00d4
+#define PM_EVGENONTIM                                   0x00d8
+#define PM_EVGENOFFTIM                                  0x00dc
+#define PM_PWSTCTRL                                     0x00e0
+#define PM_PWSTST                                       0x00e4
+
+#define OMAP3430_PM_MPUGRPSEL                           0x00a4
+#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
+
+#define OMAP3430_PM_IVAGRPSEL                           0x00a8
+#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
+
+#define OMAP3430_PM_PREPWSTST                           0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_PM_WKEN2                               0x00a4
+#define OMAP24XX_PM_WKST2                               0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
+
+#ifndef __ASSEMBLER__
+
+/* Power/reset management domain register get/set */
+
+static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+        __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
+}
+
+static inline u32 prm_read_mod_reg(s16 module, s16 idx)
+{
+        return __raw_readl(OMAP_PRM_REGADDR(module, idx));
+}
+
+#endif
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT                            0
+#define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT                           0
+#define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT                           0
+#define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT                            6
+#define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
+#define OMAP_AUTOEXTCLKMODE_SHIFT                       3
+#define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT                            0
+#define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT                          3
+#define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT                           1
+#define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
+#define OMAP_ENABLE                                     (1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT                             8
+#define OMAP_RSTTIME2_MASK                              (0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT                             0
+#define OMAP_RSTTIME1_MASK                              (0xff << 0)
+
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3                                  (1 << 2)
+#define OMAP_RST_GS                                     (1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *       PM_PWSTST_NEON
+ */
+#define OMAP_INTRANSITION                               (1 << 20)
+
+
+/*
+ * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *       PM_PWSTST_NEON
+ */
+#define OMAP_POWERSTATEST_SHIFT                         0
+#define OMAP_POWERSTATEST_MASK                          (0x3 << 0)
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ *       called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST                         (1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST                             (1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST                             (1 << 1)
+#define OMAP_GLOBALCOLD_RST                             (1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ *       PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP                                    (1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *       PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE                              (1 << 2)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
+ *
+ * 2430: PM_PWSTCTRL_MDM shared bits
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
+ *       PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *       PM_PWSTCTRL_NEON shared bits
+ */
+#define OMAP_POWERSTATE_SHIFT                           0
+#define OMAP_POWERSTATE_MASK                            (0x3 << 0)
+
+
+#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
new file mode 100644
index 000000000000..d7f23bc9550a
--- /dev/null
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -0,0 +1,58 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
+#define __ARCH_ARM_MACH_OMAP2_SDRC_H
+
+/*
+ * OMAP2 SDRC register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <asm/arch/sdrc.h>
+
+#ifndef __ASSEMBLER__
+extern unsigned long omap2_sdrc_base;
+extern unsigned long omap2_sms_base;
+
+#define OMAP_SDRC_REGADDR(reg)                                          \
+                (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg))
+#define OMAP_SMS_REGADDR(reg)                                           \
+                (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
+
+/* SDRC global register get/set */
+
+static inline void sdrc_write_reg(u32 val, u16 reg)
+{
+        __raw_writel(val, OMAP_SDRC_REGADDR(reg));
+}
+
+static inline u32 sdrc_read_reg(u16 reg)
+{
+        return __raw_readl(OMAP_SDRC_REGADDR(reg));
+}
+
+/* SMS global register get/set */
+
+static inline void sms_write_reg(u32 val, u16 reg)
+{
+        __raw_writel(val, OMAP_SMS_REGADDR(reg));
+}
+
+static inline u32 sms_read_reg(u16 reg)
+{
+        return __raw_readl(OMAP_SMS_REGADDR(reg));
+}
+#else
+#define OMAP242X_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
+#define OMAP243X_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
+#define OMAP34XX_SDRC_REGADDR(reg)      IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+#endif  /* __ASSEMBLER__ */
+
+#endif
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S
index 16247d557853..46ccb9b8b583 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep.S
@@ -26,19 +26,10 @@
 #include <asm/arch/io.h>
 #include <asm/arch/pm.h>
 
-#define A_32KSYNC_CR_V          IO_ADDRESS(OMAP_TIMER32K_BASE+0x10)
-#define A_PRCM_VOLTCTRL_V       IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
-#define A_PRCM_CLKCFG_CTRL_V    IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
-#define A_CM_CLKEN_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
-#define A_CM_IDLEST_CKGEN_V     IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
-#define A_CM_CLKSEL1_PLL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
-#define A_CM_CLKSEL2_PLL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
+#include "sdrc.h"
 
-#define A_SDRC_DLLA_CTRL_V      IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60)
-#define A_SDRC_POWER_V          IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
-#define A_SDRC_RFR_CTRL_V       IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
+/* First address of reserved address space?  apparently valid for OMAP2 & 3 */
 #define A_SDRC0_V               (0xC0000000)
-#define A_SDRC_MANUAL_V         IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
 
         .text
 
@@ -126,17 +117,11 @@ loop2:
         ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
 
 A_SDRC_POWER:
-        .word A_SDRC_POWER_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
 A_SDRC0:
         .word A_SDRC0_V
-A_CM_CLKSEL2_PLL_S:
-        .word A_CM_CLKSEL2_PLL_V
-A_CM_CLKEN_PLL:
-        .word A_CM_CLKEN_PLL_V
 A_SDRC_DLLA_CTRL_S:
-        .word A_SDRC_DLLA_CTRL_V
-A_SDRC_MANUAL_S:
-        .word A_SDRC_MANUAL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
 ENTRY(omap24xx_cpu_suspend_sz)
         .word   . - omap24xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index b27576690f8d..4a9e49140716 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -27,19 +27,11 @@
 #include <asm/arch/io.h>
 #include <asm/hardware.h>
 
-#include "prcm-regs.h"
+#include "sdrc.h"
+#include "prm.h"
+#include "cm.h"
 
-#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
-
-#define CM_CLKSEL2_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
-#define PRCM_VOLTCTRL_V         IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
-#define PRCM_CLKCFG_CTRL_V      IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
-#define CM_CLKEN_PLL_V          IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
-#define CM_IDLEST_CKGEN_V       IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
-#define CM_CLKSEL1_PLL_V        IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
-
-#define SDRC_DLLA_CTRL_V        IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_RFR_CTRL_V         IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
+#define TIMER_32KSYNCT_CR_V     IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
 
         .text
 
@@ -131,11 +123,11 @@ volt_delay:
 
 /* relative load constants */
 cm_clksel2_pll:
-        .word CM_CLKSEL2_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
 sdrc_dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 prcm_voltctrl:
-        .word PRCM_VOLTCTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
 prcm_mask_val:
         .word 0xFFFF3FFC
 timer_32ksynct_cr:
@@ -225,13 +217,13 @@ volt_delay_c:
         mov     pc, lr                  @ back to caller
 
 ddr_cm_clksel2_pll:
-        .word CM_CLKSEL2_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
 ddr_sdrc_dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 ddr_sdrc_rfr_ctrl:
-        .word SDRC_RFR_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 ddr_prcm_voltctrl:
-        .word PRCM_VOLTCTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
 ddr_prcm_mask_val:
         .word 0xFFFF3FFC
 ddr_timer_32ksynct:
@@ -316,17 +308,17 @@ wait_dll_lock:
         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
 set_config:
-        .word PRCM_CLKCFG_CTRL_V
+        .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
 pll_ctl:
-        .word CM_CLKEN_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
 pll_stat:
-        .word CM_IDLEST_CKGEN_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
 pll_div:
-        .word CM_CLKSEL1_PLL_V
+        .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
 sdrc_rfr:
-        .word SDRC_RFR_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 dlla_ctrl:
-        .word SDRC_DLLA_CTRL_V
+        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
 ENTRY(sram_set_prcm_sz)
         .word   . - sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 3234deedb946..78d05f203fff 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -3,6 +3,11 @@
  *
  * OMAP2 GP timer support.
  *
+ * Update to use new clocksource/clockevent layers
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * Original driver:
  * Copyright (C) 2005 Nokia Corporation
  * Author: Paul Mundt <paul.mundt@nokia.com>
  *         Juha Yrjölä <juha.yrjola@nokia.com>
@@ -25,24 +30,23 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
 #include <asm/arch/dmtimer.h>
 
 static struct omap_dm_timer *gptimer;
-
-static inline void omap2_gp_timer_start(unsigned long load_val)
-{
-        omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
-        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
-        omap_dm_timer_start(gptimer);
-}
+static struct clock_event_device clockevent_gpt;
 
 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
-        omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
-        timer_tick();
+        struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
+        struct clock_event_device *evt = &clockevent_gpt;
+
+        omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
 
+        evt->event_handler(evt);
         return IRQ_HANDLED;
 }
 
@@ -52,20 +56,138 @@ static struct irqaction omap2_gp_timer_irq = {
         .handler        = omap2_gp_timer_interrupt,
 };
 
-static void __init omap2_gp_timer_init(void)
+static int omap2_gp_timer_set_next_event(unsigned long cycles,
+                                         struct clock_event_device *evt)
 {
-        u32 tick_period;
+        omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
+        omap_dm_timer_start(gptimer);
+
+        return 0;
+}
+
+static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+                                    struct clock_event_device *evt)
+{
+        u32 period;
+
+        omap_dm_timer_stop(gptimer);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
+                period -= 1;
+
+                omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
+                omap_dm_timer_start(gptimer);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device clockevent_gpt = {
+        .name           = "gp timer",
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_next_event = omap2_gp_timer_set_next_event,
+        .set_mode       = omap2_gp_timer_set_mode,
+};
+
+static void __init omap2_gp_clockevent_init(void)
+{
+        u32 tick_rate;
 
-        omap_dm_timer_init();
         gptimer = omap_dm_timer_request_specific(1);
         BUG_ON(gptimer == NULL);
 
+#if defined(CONFIG_OMAP_32K_TIMER)
+        omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
+#else
         omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
-        tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
-        tick_period -= 1;
+#endif
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
 
+        omap2_gp_timer_irq.dev_id = (void *)gptimer;
         setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
-        omap2_gp_timer_start(tick_period);
+        omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
+
+        clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
+                                     clockevent_gpt.shift);
+        clockevent_gpt.max_delta_ns =
+                clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+        clockevent_gpt.min_delta_ns =
+                clockevent_delta2ns(1, &clockevent_gpt);
+
+        clockevent_gpt.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&clockevent_gpt);
+}
+
+#ifdef CONFIG_OMAP_32K_TIMER
+/* 
+ * When 32k-timer is enabled, don't use GPTimer for clocksource
+ * instead, just leave default clocksource which uses the 32k
+ * sync counter.  See clocksource setup in see plat-omap/common.c. 
+ */
+
+static inline void __init omap2_gp_clocksource_init(void) {}
+#else
+/*
+ * clocksource
+ */
+static struct omap_dm_timer *gpt_clocksource;
+static cycle_t clocksource_read_cycles(void)
+{
+        return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
+}
+
+static struct clocksource clocksource_gpt = {
+        .name           = "gp timer",
+        .rating         = 300,
+        .read           = clocksource_read_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .shift          = 24,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/* Setup free-running counter for clocksource */
+static void __init omap2_gp_clocksource_init(void)
+{
+        static struct omap_dm_timer *gpt;
+        u32 tick_rate, tick_period;
+        static char err1[] __initdata = KERN_ERR
+                "%s: failed to request dm-timer\n";
+        static char err2[] __initdata = KERN_ERR
+                "%s: can't register clocksource!\n";
+
+        gpt = omap_dm_timer_request();
+        if (!gpt)
+                printk(err1, clocksource_gpt.name);
+        gpt_clocksource = gpt;
+
+        omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
+        tick_period = (tick_rate / HZ) - 1;
+
+        omap_dm_timer_set_load(gpt, 1, 0);
+        omap_dm_timer_start(gpt);
+
+        clocksource_gpt.mult =
+                clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
+        if (clocksource_register(&clocksource_gpt))
+                printk(err2, clocksource_gpt.name);
+}
+#endif
+
+static void __init omap2_gp_timer_init(void)
+{
+        omap_dm_timer_init();
+
+        omap2_gp_clockevent_init();
+        omap2_gp_clocksource_init();
 }
 
 struct sys_timer omap_timer = {