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-rw-r--r--arch/arm/mach-omap2/Kconfig1
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c5
-rw-r--r--arch/arm/mach-omap2/board-flash.c4
-rw-r--r--arch/arm/mach-omap2/board-generic.c45
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c1
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c4
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_osc.c8
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_sys.c2
-rw-r--r--arch/arm/mach-omap2/clockdomain.h3
-rw-r--r--arch/arm/mach-omap2/cm2xxx.c15
-rw-r--r--arch/arm/mach-omap2/cm2xxx_3xxx.h4
-rw-r--r--arch/arm/mach-omap2/cm33xx.c4
-rw-r--r--arch/arm/mach-omap2/cm33xx.h3
-rw-r--r--arch/arm/mach-omap2/cm3xxx.c25
-rw-r--r--arch/arm/mach-omap2/cm3xxx.h5
-rw-r--r--arch/arm/mach-omap2/cm44xx.c11
-rw-r--r--arch/arm/mach-omap2/cm_common.c2
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c14
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/control.c20
-rw-r--r--arch/arm/mach-omap2/display.c62
-rw-r--r--arch/arm/mach-omap2/dma.c4
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c8
-rw-r--r--arch/arm/mach-omap2/hdq1w.c2
-rw-r--r--arch/arm/mach-omap2/id.c39
-rw-r--r--arch/arm/mach-omap2/io.c3
-rw-r--r--arch/arm/mach-omap2/irq.c4
-rw-r--r--arch/arm/mach-omap2/mux.c8
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S6
-rw-r--r--arch/arm/mach-omap2/omap-hotplug.c4
-rw-r--r--arch/arm/mach-omap2/omap-mpuss-lowpower.c26
-rw-r--r--arch/arm/mach-omap2/omap-smp.c6
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c42
-rw-r--r--arch/arm/mach-omap2/omap4-common.c104
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c99
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c283
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c10
-rw-r--r--arch/arm/mach-omap2/omap_phy_internal.c6
-rw-r--r--arch/arm/mach-omap2/omap_twl.c60
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c19
-rw-r--r--arch/arm/mach-omap2/pm.c45
-rw-r--r--arch/arm/mach-omap2/pm.h8
-rw-r--r--arch/arm/mach-omap2/pm24xx.c4
-rw-r--r--arch/arm/mach-omap2/pm34xx.c11
-rw-r--r--arch/arm/mach-omap2/pm44xx.c6
-rw-r--r--arch/arm/mach-omap2/powerdomain-common.c1
-rw-r--r--arch/arm/mach-omap2/powerdomain.c1
-rw-r--r--arch/arm/mach-omap2/powerdomain.h3
-rw-r--r--arch/arm/mach-omap2/prcm-common.h24
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.c4
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h1
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h11
-rw-r--r--arch/arm/mach-omap2/prm.h10
-rw-r--r--arch/arm/mach-omap2/prm2xxx.c13
-rw-r--r--arch/arm/mach-omap2/prm2xxx.h2
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c1
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h4
-rw-r--r--arch/arm/mach-omap2/prm33xx.c5
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c22
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h2
-rw-r--r--arch/arm/mach-omap2/prm44xx.c24
-rw-r--r--arch/arm/mach-omap2/prm_common.c17
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c4
-rw-r--r--arch/arm/mach-omap2/sdrc.h8
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c4
-rw-r--r--arch/arm/mach-omap2/soc.h5
-rw-r--r--arch/arm/mach-omap2/sr_device.c2
-rw-r--r--arch/arm/mach-omap2/sram.c16
-rw-r--r--arch/arm/mach-omap2/timer.c10
-rw-r--r--arch/arm/mach-omap2/usb-host.c10
-rw-r--r--arch/arm/mach-omap2/vc.c236
-rw-r--r--arch/arm/mach-omap2/vc.h3
-rw-r--r--arch/arm/mach-omap2/wd_timer.c8
78 files changed, 875 insertions, 646 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index cb31d4390d52..0ba482638ebf 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -65,6 +65,7 @@ config SOC_AM43XX
65 select ARCH_HAS_OPP 65 select ARCH_HAS_OPP
66 select ARM_GIC 66 select ARM_GIC
67 select MACH_OMAP_GENERIC 67 select MACH_OMAP_GENERIC
68 select MIGHT_HAVE_CACHE_L2X0
68 69
69config SOC_DRA7XX 70config SOC_DRA7XX
70 bool "TI DRA7XX" 71 bool "TI DRA7XX"
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 543d9a882de3..4f9383cecf76 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -262,12 +262,7 @@ static struct usbhs_phy_data phy_data[] __initdata = {
262 262
263static struct usbhs_omap_platform_data usbhs_bdata __initdata = { 263static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
264 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 264 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
265#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
266 defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
267 .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
268#else
269 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 265 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
270#endif
271}; 266};
272 267
273#ifdef CONFIG_OMAP_MUX 268#ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index b6885e42c0a0..e87f2a83d6bf 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -160,13 +160,13 @@ static u8 get_gpmc0_type(void)
160 if (!fpga_map_addr) 160 if (!fpga_map_addr)
161 return -ENOMEM; 161 return -ENOMEM;
162 162
163 if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV))) 163 if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
164 /* we dont have an DEBUG FPGA??? */ 164 /* we dont have an DEBUG FPGA??? */
165 /* Depend on #defines!! default to strata boot return param */ 165 /* Depend on #defines!! default to strata boot return param */
166 goto unmap; 166 goto unmap;
167 167
168 /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */ 168 /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
169 cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf; 169 cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
170 170
171 /* ES2.0 SDP's onwards 4 dip switches are provided for CS */ 171 /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
172 if (omap_rev() >= OMAP3430_REV_ES1_0) 172 if (omap_rev() >= OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index b8920b6bc104..9480997ba616 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -43,7 +43,7 @@ static void __init omap_generic_init(void)
43} 43}
44 44
45#ifdef CONFIG_SOC_OMAP2420 45#ifdef CONFIG_SOC_OMAP2420
46static const char *omap242x_boards_compat[] __initdata = { 46static const char *omap242x_boards_compat[] __initconst = {
47 "ti,omap2420", 47 "ti,omap2420",
48 NULL, 48 NULL,
49}; 49};
@@ -62,7 +62,7 @@ MACHINE_END
62#endif 62#endif
63 63
64#ifdef CONFIG_SOC_OMAP2430 64#ifdef CONFIG_SOC_OMAP2430
65static const char *omap243x_boards_compat[] __initdata = { 65static const char *omap243x_boards_compat[] __initconst = {
66 "ti,omap2430", 66 "ti,omap2430",
67 NULL, 67 NULL,
68}; 68};
@@ -81,7 +81,7 @@ MACHINE_END
81#endif 81#endif
82 82
83#ifdef CONFIG_ARCH_OMAP3 83#ifdef CONFIG_ARCH_OMAP3
84static const char *omap3_boards_compat[] __initdata = { 84static const char *omap3_boards_compat[] __initconst = {
85 "ti,omap3430", 85 "ti,omap3430",
86 "ti,omap3", 86 "ti,omap3",
87 NULL, 87 NULL,
@@ -100,7 +100,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
100 .restart = omap3xxx_restart, 100 .restart = omap3xxx_restart,
101MACHINE_END 101MACHINE_END
102 102
103static const char *omap36xx_boards_compat[] __initdata = { 103static const char *omap36xx_boards_compat[] __initconst = {
104 "ti,omap36xx", 104 "ti,omap36xx",
105 NULL, 105 NULL,
106}; 106};
@@ -118,7 +118,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
118 .restart = omap3xxx_restart, 118 .restart = omap3xxx_restart,
119MACHINE_END 119MACHINE_END
120 120
121static const char *omap3_gp_boards_compat[] __initdata = { 121static const char *omap3_gp_boards_compat[] __initconst = {
122 "ti,omap3-beagle", 122 "ti,omap3-beagle",
123 "timll,omap3-devkit8000", 123 "timll,omap3-devkit8000",
124 NULL, 124 NULL,
@@ -137,7 +137,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
137 .restart = omap3xxx_restart, 137 .restart = omap3xxx_restart,
138MACHINE_END 138MACHINE_END
139 139
140static const char *am3517_boards_compat[] __initdata = { 140static const char *am3517_boards_compat[] __initconst = {
141 "ti,am3517", 141 "ti,am3517",
142 NULL, 142 NULL,
143}; 143};
@@ -157,7 +157,7 @@ MACHINE_END
157#endif 157#endif
158 158
159#ifdef CONFIG_SOC_AM33XX 159#ifdef CONFIG_SOC_AM33XX
160static const char *am33xx_boards_compat[] __initdata = { 160static const char *am33xx_boards_compat[] __initconst = {
161 "ti,am33xx", 161 "ti,am33xx",
162 NULL, 162 NULL,
163}; 163};
@@ -177,7 +177,7 @@ MACHINE_END
177#endif 177#endif
178 178
179#ifdef CONFIG_ARCH_OMAP4 179#ifdef CONFIG_ARCH_OMAP4
180static const char *omap4_boards_compat[] __initdata = { 180static const char *omap4_boards_compat[] __initconst = {
181 "ti,omap4460", 181 "ti,omap4460",
182 "ti,omap4430", 182 "ti,omap4430",
183 "ti,omap4", 183 "ti,omap4",
@@ -199,7 +199,7 @@ MACHINE_END
199#endif 199#endif
200 200
201#ifdef CONFIG_SOC_OMAP5 201#ifdef CONFIG_SOC_OMAP5
202static const char *omap5_boards_compat[] __initdata = { 202static const char *omap5_boards_compat[] __initconst = {
203 "ti,omap5432", 203 "ti,omap5432",
204 "ti,omap5430", 204 "ti,omap5430",
205 "ti,omap5", 205 "ti,omap5",
@@ -221,7 +221,7 @@ MACHINE_END
221#endif 221#endif
222 222
223#ifdef CONFIG_SOC_AM43XX 223#ifdef CONFIG_SOC_AM43XX
224static const char *am43_boards_compat[] __initdata = { 224static const char *am43_boards_compat[] __initconst = {
225 "ti,am4372", 225 "ti,am4372",
226 "ti,am43", 226 "ti,am43",
227 NULL, 227 NULL,
@@ -240,13 +240,13 @@ MACHINE_END
240#endif 240#endif
241 241
242#ifdef CONFIG_SOC_DRA7XX 242#ifdef CONFIG_SOC_DRA7XX
243static const char *dra7xx_boards_compat[] __initdata = { 243static const char *dra74x_boards_compat[] __initconst = {
244 "ti,dra7xx", 244 "ti,dra742",
245 "ti,dra7", 245 "ti,dra7",
246 NULL, 246 NULL,
247}; 247};
248 248
249DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") 249DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
250 .reserve = omap_reserve, 250 .reserve = omap_reserve,
251 .smp = smp_ops(omap4_smp_ops), 251 .smp = smp_ops(omap4_smp_ops),
252 .map_io = omap5_map_io, 252 .map_io = omap5_map_io,
@@ -255,7 +255,24 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
255 .init_irq = omap_gic_of_init, 255 .init_irq = omap_gic_of_init,
256 .init_machine = omap_generic_init, 256 .init_machine = omap_generic_init,
257 .init_time = omap5_realtime_timer_init, 257 .init_time = omap5_realtime_timer_init,
258 .dt_compat = dra7xx_boards_compat, 258 .dt_compat = dra74x_boards_compat,
259 .restart = omap44xx_restart,
260MACHINE_END
261
262static const char *dra72x_boards_compat[] __initconst = {
263 "ti,dra722",
264 NULL,
265};
266
267DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)")
268 .reserve = omap_reserve,
269 .map_io = omap5_map_io,
270 .init_early = dra7xx_init_early,
271 .init_late = dra7xx_init_late,
272 .init_irq = omap_gic_of_init,
273 .init_machine = omap_generic_init,
274 .init_time = omap5_realtime_timer_init,
275 .dt_compat = dra72x_boards_compat,
259 .restart = omap44xx_restart, 276 .restart = omap44xx_restart,
260MACHINE_END 277MACHINE_END
261#endif 278#endif
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index d6ed819ff15c..660bfc5a70d7 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,7 +33,6 @@
33#include <linux/mtd/nand.h> 33#include <linux/mtd/nand.h>
34#include <linux/mmc/host.h> 34#include <linux/mmc/host.h>
35#include <linux/usb/phy.h> 35#include <linux/usb/phy.h>
36#include <linux/usb/usb_phy_gen_xceiv.h>
37 36
38#include <linux/regulator/machine.h> 37#include <linux/regulator/machine.h>
39#include <linux/i2c/twl.h> 38#include <linux/i2c/twl.h>
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 119efaf5808a..a2e035e0792a 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -121,11 +121,7 @@ static struct platform_device omap3stalker_tfp410_device = {
121static struct connector_atv_platform_data omap3stalker_tv_pdata = { 121static struct connector_atv_platform_data omap3stalker_tv_pdata = {
122 .name = "tv", 122 .name = "tv",
123 .source = "venc.0", 123 .source = "venc.0",
124#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO)
125 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
126#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE)
127 .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE, 124 .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE,
128#endif
129 .invert_polarity = false, 125 .invert_polarity = false,
130}; 126};
131 127
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 3ff32543493c..59cf310bc1e9 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -138,7 +138,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
138 if (!dd) 138 if (!dd)
139 return -EINVAL; 139 return -EINVAL;
140 140
141 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); 141 tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg);
142 tmpset.cm_clksel1_pll &= ~(dd->mult_mask | 142 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
143 dd->div1_mask); 143 dd->div1_mask);
144 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 144 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index 19f54d433490..0717dff1bc04 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -39,9 +39,9 @@ int omap2_enable_osc_ck(struct clk_hw *clk)
39{ 39{
40 u32 pcc; 40 u32 pcc;
41 41
42 pcc = __raw_readl(prcm_clksrc_ctrl); 42 pcc = readl_relaxed(prcm_clksrc_ctrl);
43 43
44 __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); 44 writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
45 45
46 return 0; 46 return 0;
47} 47}
@@ -57,9 +57,9 @@ void omap2_disable_osc_ck(struct clk_hw *clk)
57{ 57{
58 u32 pcc; 58 u32 pcc;
59 59
60 pcc = __raw_readl(prcm_clksrc_ctrl); 60 pcc = readl_relaxed(prcm_clksrc_ctrl);
61 61
62 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); 62 writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
63} 63}
64 64
65unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, 65unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index f467d072cd02..58dd3a9b726c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -33,7 +33,7 @@ u32 omap2xxx_get_sysclkdiv(void)
33{ 33{
34 u32 div; 34 u32 div;
35 35
36 div = __raw_readl(prcm_clksrc_ctrl); 36 div = readl_relaxed(prcm_clksrc_ctrl);
37 div &= OMAP_SYSCLKDIV_MASK; 37 div &= OMAP_SYSCLKDIV_MASK;
38 div >>= OMAP_SYSCLKDIV_SHIFT; 38 div >>= OMAP_SYSCLKDIV_SHIFT;
39 39
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f17f00697cc0..82c37b1becc4 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -18,7 +18,6 @@
18 18
19#include "powerdomain.h" 19#include "powerdomain.h"
20#include "clock.h" 20#include "clock.h"
21#include "omap_hwmod.h"
22 21
23/* 22/*
24 * Clockdomain flags 23 * Clockdomain flags
@@ -98,6 +97,8 @@ struct clkdm_dep {
98/* Possible flags for struct clockdomain._flags */ 97/* Possible flags for struct clockdomain._flags */
99#define _CLKDM_FLAG_HWSUP_ENABLED BIT(0) 98#define _CLKDM_FLAG_HWSUP_ENABLED BIT(0)
100 99
100struct omap_hwmod;
101
101/** 102/**
102 * struct clockdomain - OMAP clockdomain 103 * struct clockdomain - OMAP clockdomain
103 * @name: clockdomain name 104 * @name: clockdomain name
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ce25abbcffae..8be6ea50c092 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -18,9 +18,6 @@
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include "soc.h"
22#include "iomap.h"
23#include "common.h"
24#include "prm2xxx.h" 21#include "prm2xxx.h"
25#include "cm.h" 22#include "cm.h"
26#include "cm2xxx.h" 23#include "cm2xxx.h"
@@ -390,7 +387,7 @@ void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
390 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & 387 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
391 OMAP24XX_CLKSEL_DSS2_MASK; 388 OMAP24XX_CLKSEL_DSS2_MASK;
392 omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1); 389 omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
393 if (cpu_is_omap2430()) 390 if (mdm)
394 omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL); 391 omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
395} 392}
396 393
@@ -405,19 +402,11 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
405 402
406int __init omap2xxx_cm_init(void) 403int __init omap2xxx_cm_init(void)
407{ 404{
408 if (!cpu_is_omap24xx())
409 return 0;
410
411 return cm_register(&omap2xxx_cm_ll_data); 405 return cm_register(&omap2xxx_cm_ll_data);
412} 406}
413 407
414static void __exit omap2xxx_cm_exit(void) 408static void __exit omap2xxx_cm_exit(void)
415{ 409{
416 if (!cpu_is_omap24xx()) 410 cm_unregister(&omap2xxx_cm_ll_data);
417 return;
418
419 /* Should never happen */
420 WARN(cm_unregister(&omap2xxx_cm_ll_data),
421 "%s: cm_ll_data function pointer mismatch\n", __func__);
422} 411}
423__exitcall(omap2xxx_cm_exit); 412__exitcall(omap2xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index bfbd16fe9151..72928a3ce2aa 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -52,12 +52,12 @@
52 52
53static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx) 53static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
54{ 54{
55 return __raw_readl(cm_base + module + idx); 55 return readl_relaxed(cm_base + module + idx);
56} 56}
57 57
58static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) 58static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
59{ 59{
60 __raw_writel(val, cm_base + module + idx); 60 writel_relaxed(val, cm_base + module + idx);
61} 61}
62 62
63/* Read-modify-write a register in a CM module. Caller must lock */ 63/* Read-modify-write a register in a CM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 40a22e5649ae..b3f99e93def0 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -50,13 +50,13 @@
50/* Read a register in a CM instance */ 50/* Read a register in a CM instance */
51static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) 51static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
52{ 52{
53 return __raw_readl(cm_base + inst + idx); 53 return readl_relaxed(cm_base + inst + idx);
54} 54}
55 55
56/* Write into a register in a CM */ 56/* Write into a register in a CM */
57static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) 57static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
58{ 58{
59 __raw_writel(val, cm_base + inst + idx); 59 writel_relaxed(val, cm_base + inst + idx);
60} 60}
61 61
62/* Read-modify-write a register in CM */ 62/* Read-modify-write a register in CM */
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index cfb8891b0c0e..15a778ce7707 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,11 +17,8 @@
17#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H 17#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
18#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H 18#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
19 19
20#include "common.h"
21
22#include "cm.h" 20#include "cm.h"
23#include "cm-regbits-33xx.h" 21#include "cm-regbits-33xx.h"
24#include "iomap.h"
25 22
26/* CM base address */ 23/* CM base address */
27#define AM33XX_CM_BASE 0x44e00000 24#define AM33XX_CM_BASE 0x44e00000
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index f6f028867bfe..129a4e7f6ef5 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -18,9 +18,6 @@
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include "soc.h"
22#include "iomap.h"
23#include "common.h"
24#include "prm2xxx_3xxx.h" 21#include "prm2xxx_3xxx.h"
25#include "cm.h" 22#include "cm.h"
26#include "cm3xxx.h" 23#include "cm3xxx.h"
@@ -388,7 +385,8 @@ void omap3_cm_save_context(void)
388 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); 385 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
389 cm_context.iva2_cm_clksel2 = 386 cm_context.iva2_cm_clksel2 =
390 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); 387 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
391 cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); 388 cm_context.cm_sysconfig =
389 omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
392 cm_context.sgx_cm_clksel = 390 cm_context.sgx_cm_clksel =
393 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); 391 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
394 cm_context.dss_cm_clksel = 392 cm_context.dss_cm_clksel =
@@ -418,7 +416,8 @@ void omap3_cm_save_context(void)
418 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); 416 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
419 cm_context.pll_cm_clken2 = 417 cm_context.pll_cm_clken2 =
420 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); 418 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
421 cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); 419 cm_context.cm_polctrl =
420 omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
422 cm_context.iva2_cm_fclken = 421 cm_context.iva2_cm_fclken =
423 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); 422 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
424 cm_context.iva2_cm_clken_pll = 423 cm_context.iva2_cm_clken_pll =
@@ -519,7 +518,8 @@ void omap3_cm_restore_context(void)
519 CM_CLKSEL1); 518 CM_CLKSEL1);
520 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, 519 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
521 CM_CLKSEL2); 520 CM_CLKSEL2);
522 __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); 521 omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
522 OMAP3430_CM_SYSCONFIG);
523 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, 523 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
524 CM_CLKSEL); 524 CM_CLKSEL);
525 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, 525 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
@@ -547,7 +547,8 @@ void omap3_cm_restore_context(void)
547 OMAP3430ES2_CM_CLKSEL5); 547 OMAP3430ES2_CM_CLKSEL5);
548 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, 548 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
549 OMAP3430ES2_CM_CLKEN2); 549 OMAP3430ES2_CM_CLKEN2);
550 __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); 550 omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
551 OMAP3430_CM_POLCTRL);
551 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, 552 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
552 CM_FCLKEN); 553 CM_FCLKEN);
553 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, 554 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
@@ -669,19 +670,11 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
669 670
670int __init omap3xxx_cm_init(void) 671int __init omap3xxx_cm_init(void)
671{ 672{
672 if (!cpu_is_omap34xx())
673 return 0;
674
675 return cm_register(&omap3xxx_cm_ll_data); 673 return cm_register(&omap3xxx_cm_ll_data);
676} 674}
677 675
678static void __exit omap3xxx_cm_exit(void) 676static void __exit omap3xxx_cm_exit(void)
679{ 677{
680 if (!cpu_is_omap34xx()) 678 cm_unregister(&omap3xxx_cm_ll_data);
681 return;
682
683 /* Should never happen */
684 WARN(cm_unregister(&omap3xxx_cm_ll_data),
685 "%s: cm_ll_data function pointer mismatch\n", __func__);
686} 679}
687__exitcall(omap3xxx_cm_exit); 680__exitcall(omap3xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 8224c91b4d7a..7a16b5598127 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -29,9 +29,8 @@
29 * These registers appear once per CM module. 29 * These registers appear once per CM module.
30 */ 30 */
31 31
32#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) 32#define OMAP3430_CM_SYSCONFIG 0x0010
33#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) 33#define OMAP3430_CM_POLCTRL 0x009c
34#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
35 34
36#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 35#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
37#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 36#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 535d66e2822c..fe5cc7bae489 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,35 +18,32 @@
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include "iomap.h"
22#include "common.h"
23#include "cm.h" 21#include "cm.h"
24#include "cm1_44xx.h" 22#include "cm1_44xx.h"
25#include "cm2_44xx.h" 23#include "cm2_44xx.h"
26#include "cm-regbits-44xx.h"
27 24
28/* CM1 hardware module low-level functions */ 25/* CM1 hardware module low-level functions */
29 26
30/* Read a register in CM1 */ 27/* Read a register in CM1 */
31u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg) 28u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
32{ 29{
33 return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg)); 30 return readl_relaxed(cm_base + inst + reg);
34} 31}
35 32
36/* Write into a register in CM1 */ 33/* Write into a register in CM1 */
37void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg) 34void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
38{ 35{
39 __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg)); 36 writel_relaxed(val, cm_base + inst + reg);
40} 37}
41 38
42/* Read a register in CM2 */ 39/* Read a register in CM2 */
43u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg) 40u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
44{ 41{
45 return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg)); 42 return readl_relaxed(cm2_base + inst + reg);
46} 43}
47 44
48/* Write into a register in CM2 */ 45/* Write into a register in CM2 */
49void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg) 46void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
50{ 47{
51 __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg)); 48 writel_relaxed(val, cm2_base + inst + reg);
52} 49}
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 40b3b5a84458..8f6c4710877e 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -14,11 +14,11 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/errno.h> 16#include <linux/errno.h>
17#include <linux/bug.h>
17 18
18#include "cm2xxx.h" 19#include "cm2xxx.h"
19#include "cm3xxx.h" 20#include "cm3xxx.h"
20#include "cm44xx.h" 21#include "cm44xx.h"
21#include "common.h"
22 22
23/* 23/*
24 * cm_ll_data: function pointers to SoC-specific implementations of 24 * cm_ll_data: function pointers to SoC-specific implementations of
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index f5c4731b6f06..12aca56942c0 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -21,8 +21,6 @@
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/io.h> 22#include <linux/io.h>
23 23
24#include "iomap.h"
25#include "common.h"
26#include "clockdomain.h" 24#include "clockdomain.h"
27#include "cm.h" 25#include "cm.h"
28#include "cm1_44xx.h" 26#include "cm1_44xx.h"
@@ -30,12 +28,18 @@
30#include "cm44xx.h" 28#include "cm44xx.h"
31#include "cminst44xx.h" 29#include "cminst44xx.h"
32#include "cm-regbits-34xx.h" 30#include "cm-regbits-34xx.h"
33#include "cm-regbits-44xx.h"
34#include "prcm44xx.h" 31#include "prcm44xx.h"
35#include "prm44xx.h" 32#include "prm44xx.h"
36#include "prcm_mpu44xx.h" 33#include "prcm_mpu44xx.h"
37#include "prcm-common.h" 34#include "prcm-common.h"
38 35
36#define OMAP4430_IDLEST_SHIFT 16
37#define OMAP4430_IDLEST_MASK (0x3 << 16)
38#define OMAP4430_CLKTRCTRL_SHIFT 0
39#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
40#define OMAP4430_MODULEMODE_SHIFT 0
41#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
42
39/* 43/*
40 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 44 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
41 * 45 *
@@ -116,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
116 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 120 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
117 part == OMAP4430_INVALID_PRCM_PARTITION || 121 part == OMAP4430_INVALID_PRCM_PARTITION ||
118 !_cm_bases[part]); 122 !_cm_bases[part]);
119 return __raw_readl(_cm_bases[part] + inst + idx); 123 return readl_relaxed(_cm_bases[part] + inst + idx);
120} 124}
121 125
122/* Write into a register in a CM instance */ 126/* Write into a register in a CM instance */
@@ -125,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
125 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 129 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
126 part == OMAP4430_INVALID_PRCM_PARTITION || 130 part == OMAP4430_INVALID_PRCM_PARTITION ||
127 !_cm_bases[part]); 131 !_cm_bases[part]);
128 __raw_writel(val, _cm_bases[part] + inst + idx); 132 writel_relaxed(val, _cm_bases[part] + inst + idx);
129} 133}
130 134
131/* Read-modify-write a register in CM1. Caller must lock */ 135/* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d88aff7baff8..ff029737c8f0 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -91,6 +91,7 @@ extern void omap3_sync32k_timer_init(void);
91extern void omap3_secure_sync32k_timer_init(void); 91extern void omap3_secure_sync32k_timer_init(void);
92extern void omap3_gptimer_timer_init(void); 92extern void omap3_gptimer_timer_init(void);
93extern void omap4_local_timer_init(void); 93extern void omap4_local_timer_init(void);
94int omap_l2_cache_init(void);
94extern void omap5_realtime_timer_init(void); 95extern void omap5_realtime_timer_init(void);
95 96
96void omap2420_init_early(void); 97void omap2420_init_early(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 44bb4d544dcf..751f3549bf6f 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -151,32 +151,32 @@ void __iomem *omap_ctrl_base_get(void)
151 151
152u8 omap_ctrl_readb(u16 offset) 152u8 omap_ctrl_readb(u16 offset)
153{ 153{
154 return __raw_readb(OMAP_CTRL_REGADDR(offset)); 154 return readb_relaxed(OMAP_CTRL_REGADDR(offset));
155} 155}
156 156
157u16 omap_ctrl_readw(u16 offset) 157u16 omap_ctrl_readw(u16 offset)
158{ 158{
159 return __raw_readw(OMAP_CTRL_REGADDR(offset)); 159 return readw_relaxed(OMAP_CTRL_REGADDR(offset));
160} 160}
161 161
162u32 omap_ctrl_readl(u16 offset) 162u32 omap_ctrl_readl(u16 offset)
163{ 163{
164 return __raw_readl(OMAP_CTRL_REGADDR(offset)); 164 return readl_relaxed(OMAP_CTRL_REGADDR(offset));
165} 165}
166 166
167void omap_ctrl_writeb(u8 val, u16 offset) 167void omap_ctrl_writeb(u8 val, u16 offset)
168{ 168{
169 __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); 169 writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
170} 170}
171 171
172void omap_ctrl_writew(u16 val, u16 offset) 172void omap_ctrl_writew(u16 val, u16 offset)
173{ 173{
174 __raw_writew(val, OMAP_CTRL_REGADDR(offset)); 174 writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
175} 175}
176 176
177void omap_ctrl_writel(u32 val, u16 offset) 177void omap_ctrl_writel(u32 val, u16 offset)
178{ 178{
179 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 179 writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
180} 180}
181 181
182/* 182/*
@@ -188,12 +188,12 @@ void omap_ctrl_writel(u32 val, u16 offset)
188 188
189u32 omap4_ctrl_pad_readl(u16 offset) 189u32 omap4_ctrl_pad_readl(u16 offset)
190{ 190{
191 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); 191 return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
192} 192}
193 193
194void omap4_ctrl_pad_writel(u32 val, u16 offset) 194void omap4_ctrl_pad_writel(u32 val, u16 offset)
195{ 195{
196 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); 196 writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
197} 197}
198 198
199#ifdef CONFIG_ARCH_OMAP3 199#ifdef CONFIG_ARCH_OMAP3
@@ -222,7 +222,7 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
222 * 222 *
223 * XXX This should use some omap_ctrl_writel()-type function 223 * XXX This should use some omap_ctrl_writel()-type function
224 */ 224 */
225 __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 225 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
226} 226}
227 227
228#endif 228#endif
@@ -285,7 +285,7 @@ void omap3_clear_scratchpad_contents(void)
285 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 285 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
286 OMAP3430_GLOBAL_COLD_RST_MASK) { 286 OMAP3430_GLOBAL_COLD_RST_MASK) {
287 for ( ; offset <= max_offset; offset += 0x4) 287 for ( ; offset <= max_offset; offset += 0x4)
288 __raw_writel(0x0, (v_addr + offset)); 288 writel_relaxed(0x0, (v_addr + offset));
289 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, 289 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
290 OMAP3430_GR_MOD, 290 OMAP3430_GR_MOD,
291 OMAP3_PRM_RSTST_OFFSET); 291 OMAP3_PRM_RSTST_OFFSET);
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 16d33d831287..bf852d7ae951 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -279,6 +279,8 @@ static enum omapdss_version __init omap_display_get_version(void)
279 return OMAPDSS_VER_OMAP4; 279 return OMAPDSS_VER_OMAP4;
280 else if (soc_is_omap54xx()) 280 else if (soc_is_omap54xx())
281 return OMAPDSS_VER_OMAP5; 281 return OMAPDSS_VER_OMAP5;
282 else if (soc_is_am43xx())
283 return OMAPDSS_VER_AM43xx;
282 else 284 else
283 return OMAPDSS_VER_UNKNOWN; 285 return OMAPDSS_VER_UNKNOWN;
284} 286}
@@ -555,65 +557,9 @@ int omap_dss_reset(struct omap_hwmod *oh)
555 return r; 557 return r;
556} 558}
557 559
558/* list of 'compatible' nodes to convert to omapdss specific */
559static const char * const dss_compat_conv_list[] __initconst = {
560 "composite-connector",
561 "dvi-connector",
562 "hdmi-connector",
563 "panel-dpi",
564 "panel-dsi-cm",
565 "sony,acx565akm",
566 "svideo-connector",
567 "ti,tfp410",
568 "ti,tpd12s015",
569};
570
571/* prepend compatible string with "omapdss," */
572static __init void omapdss_omapify_node(struct device_node *node,
573 const char *compat)
574{
575 char *new_compat;
576 struct property *prop;
577
578 new_compat = kasprintf(GFP_KERNEL, "omapdss,%s", compat);
579
580 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
581
582 if (!prop) {
583 pr_err("omapdss_omapify_node: kzalloc failed\n");
584 return;
585 }
586
587 prop->name = "compatible";
588 prop->value = new_compat;
589 prop->length = strlen(new_compat) + 1;
590
591 of_update_property(node, prop);
592}
593
594/*
595 * As omapdss panel drivers are omapdss specific, but we want to define the
596 * DT-data in generic manner, we convert the compatible strings of the panel
597 * nodes from "panel-foo" to "omapdss,panel-foo". This way we can have both
598 * correct DT data and omapdss specific drivers.
599 *
600 * When we get generic panel drivers to the kernel, this will be removed.
601 */
602void __init omapdss_early_init_of(void) 560void __init omapdss_early_init_of(void)
603{ 561{
604 int i;
605
606 for (i = 0; i < ARRAY_SIZE(dss_compat_conv_list); ++i) {
607 const char *compat = dss_compat_conv_list[i];
608 struct device_node *node = NULL;
609
610 while ((node = of_find_compatible_node(node, NULL, compat))) {
611 if (!of_device_is_available(node))
612 continue;
613 562
614 omapdss_omapify_node(node, compat);
615 }
616 }
617} 563}
618 564
619struct device_node * __init omapdss_find_dss_of_node(void) 565struct device_node * __init omapdss_find_dss_of_node(void)
@@ -632,6 +578,10 @@ struct device_node * __init omapdss_find_dss_of_node(void)
632 if (node) 578 if (node)
633 return node; 579 return node;
634 580
581 node = of_find_compatible_node(NULL, NULL, "ti,omap5-dss");
582 if (node)
583 return node;
584
635 return NULL; 585 return NULL;
636} 586}
637 587
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 5689c88d986d..a6d2cf1f8d02 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -91,7 +91,7 @@ static inline void dma_write(u32 val, int reg, int lch)
91 addr += reg_map[reg].offset; 91 addr += reg_map[reg].offset;
92 addr += reg_map[reg].stride * lch; 92 addr += reg_map[reg].stride * lch;
93 93
94 __raw_writel(val, addr); 94 writel_relaxed(val, addr);
95} 95}
96 96
97static inline u32 dma_read(int reg, int lch) 97static inline u32 dma_read(int reg, int lch)
@@ -101,7 +101,7 @@ static inline u32 dma_read(int reg, int lch)
101 addr += reg_map[reg].offset; 101 addr += reg_map[reg].offset;
102 addr += reg_map[reg].stride * lch; 102 addr += reg_map[reg].stride * lch;
103 103
104 return __raw_readl(addr); 104 return readl_relaxed(addr);
105} 105}
106 106
107static void omap2_clear_dma(int lch) 107static void omap2_clear_dma(int lch)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 4349e82debfe..17cd39360afe 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -46,7 +46,7 @@ static struct platform_device gpmc_nand_device = {
46static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 46static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
47{ 47{
48 /* platforms which support all ECC schemes */ 48 /* platforms which support all ECC schemes */
49 if (soc_is_am33xx() || cpu_is_omap44xx() || 49 if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() ||
50 soc_is_omap54xx() || soc_is_dra7xx()) 50 soc_is_omap54xx() || soc_is_dra7xx())
51 return 1; 51 return 1;
52 52
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9fe8c949305c..852b19a367f0 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -170,12 +170,12 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev);
170 170
171static void gpmc_write_reg(int idx, u32 val) 171static void gpmc_write_reg(int idx, u32 val)
172{ 172{
173 __raw_writel(val, gpmc_base + idx); 173 writel_relaxed(val, gpmc_base + idx);
174} 174}
175 175
176static u32 gpmc_read_reg(int idx) 176static u32 gpmc_read_reg(int idx)
177{ 177{
178 return __raw_readl(gpmc_base + idx); 178 return readl_relaxed(gpmc_base + idx);
179} 179}
180 180
181void gpmc_cs_write_reg(int cs, int idx, u32 val) 181void gpmc_cs_write_reg(int cs, int idx, u32 val)
@@ -183,7 +183,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
183 void __iomem *reg_addr; 183 void __iomem *reg_addr;
184 184
185 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 185 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
186 __raw_writel(val, reg_addr); 186 writel_relaxed(val, reg_addr);
187} 187}
188 188
189static u32 gpmc_cs_read_reg(int cs, int idx) 189static u32 gpmc_cs_read_reg(int cs, int idx)
@@ -191,7 +191,7 @@ static u32 gpmc_cs_read_reg(int cs, int idx)
191 void __iomem *reg_addr; 191 void __iomem *reg_addr;
192 192
193 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 193 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
194 return __raw_readl(reg_addr); 194 return readl_relaxed(reg_addr);
195} 195}
196 196
197/* TODO: Add support for gpmc_fck to clock framework and use it */ 197/* TODO: Add support for gpmc_fck to clock framework and use it */
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index cbc8e3c480e0..f78b4a161959 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -76,6 +76,7 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
76 return 0; 76 return 0;
77} 77}
78 78
79#ifndef CONFIG_OF
79static int __init omap_init_hdq(void) 80static int __init omap_init_hdq(void)
80{ 81{
81 int id = -1; 82 int id = -1;
@@ -95,3 +96,4 @@ static int __init omap_init_hdq(void)
95 return 0; 96 return 0;
96} 97}
97omap_arch_initcall(omap_init_hdq); 98omap_arch_initcall(omap_init_hdq);
99#endif
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 157412e4273a..43969da5d50b 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -94,7 +94,7 @@ EXPORT_SYMBOL(omap_type);
94#define OMAP_TAP_DIE_ID_44XX_2 0x020c 94#define OMAP_TAP_DIE_ID_44XX_2 0x020c
95#define OMAP_TAP_DIE_ID_44XX_3 0x0210 95#define OMAP_TAP_DIE_ID_44XX_3 0x0210
96 96
97#define read_tap_reg(reg) __raw_readl(tap_base + (reg)) 97#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
98 98
99struct omap_id { 99struct omap_id {
100 u16 hawkeye; /* Silicon type (Hawkeye id) */ 100 u16 hawkeye; /* Silicon type (Hawkeye id) */
@@ -628,6 +628,41 @@ void __init omap5xxx_check_revision(void)
628 pr_info("%s %s\n", soc_name, soc_rev); 628 pr_info("%s %s\n", soc_name, soc_rev);
629} 629}
630 630
631void __init dra7xxx_check_revision(void)
632{
633 u32 idcode;
634 u16 hawkeye;
635 u8 rev;
636
637 idcode = read_tap_reg(OMAP_TAP_IDCODE);
638 hawkeye = (idcode >> 12) & 0xffff;
639 rev = (idcode >> 28) & 0xff;
640 switch (hawkeye) {
641 case 0xb990:
642 switch (rev) {
643 case 0:
644 omap_revision = DRA752_REV_ES1_0;
645 break;
646 case 1:
647 default:
648 omap_revision = DRA752_REV_ES1_1;
649 }
650 break;
651
652 default:
653 /* Unknown default to latest silicon rev as default*/
654 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
655 __func__, idcode, hawkeye, rev);
656 omap_revision = DRA752_REV_ES1_1;
657 }
658
659 sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
660 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
661 (omap_rev() >> 8) & 0xf);
662
663 pr_info("%s %s\n", soc_name, soc_rev);
664}
665
631/* 666/*
632 * Set up things for map_io and processor detection later on. Gets called 667 * Set up things for map_io and processor detection later on. Gets called
633 * pretty much first thing from board init. For multi-omap, this gets 668 * pretty much first thing from board init. For multi-omap, this gets
@@ -669,6 +704,8 @@ static const char * __init omap_get_family(void)
669 return kasprintf(GFP_KERNEL, "OMAP5"); 704 return kasprintf(GFP_KERNEL, "OMAP5");
670 else if (soc_is_am43xx()) 705 else if (soc_is_am43xx())
671 return kasprintf(GFP_KERNEL, "AM43xx"); 706 return kasprintf(GFP_KERNEL, "AM43xx");
707 else if (soc_is_dra7xx())
708 return kasprintf(GFP_KERNEL, "DRA7");
672 else 709 else
673 return kasprintf(GFP_KERNEL, "Unknown"); 710 return kasprintf(GFP_KERNEL, "Unknown");
674} 711}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f14f9ac2dca1..8f559450c876 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -609,6 +609,7 @@ void __init am43xx_init_early(void)
609 am43xx_clockdomains_init(); 609 am43xx_clockdomains_init();
610 am43xx_hwmod_init(); 610 am43xx_hwmod_init();
611 omap_hwmod_init_postsetup(); 611 omap_hwmod_init_postsetup();
612 omap_l2_cache_init();
612 omap_clk_soc_init = am43xx_dt_clk_init; 613 omap_clk_soc_init = am43xx_dt_clk_init;
613} 614}
614 615
@@ -640,6 +641,7 @@ void __init omap4430_init_early(void)
640 omap44xx_clockdomains_init(); 641 omap44xx_clockdomains_init();
641 omap44xx_hwmod_init(); 642 omap44xx_hwmod_init();
642 omap_hwmod_init_postsetup(); 643 omap_hwmod_init_postsetup();
644 omap_l2_cache_init();
643 omap_clk_soc_init = omap4xxx_dt_clk_init; 645 omap_clk_soc_init = omap4xxx_dt_clk_init;
644} 646}
645 647
@@ -693,6 +695,7 @@ void __init dra7xx_init_early(void)
693 omap_prm_base_init(); 695 omap_prm_base_init();
694 omap_cm_base_init(); 696 omap_cm_base_init();
695 omap44xx_prm_init(); 697 omap44xx_prm_init();
698 dra7xxx_check_revision();
696 dra7xx_powerdomains_init(); 699 dra7xx_powerdomains_init();
697 dra7xx_clockdomains_init(); 700 dra7xx_clockdomains_init();
698 dra7xx_hwmod_init(); 701 dra7xx_hwmod_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 6037a9a01ed5..35b8590c322e 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -83,12 +83,12 @@ struct omap3_intc_regs {
83 83
84static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) 84static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
85{ 85{
86 __raw_writel(val, bank->base_reg + reg); 86 writel_relaxed(val, bank->base_reg + reg);
87} 87}
88 88
89static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) 89static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
90{ 90{
91 return __raw_readl(bank->base_reg + reg); 91 return readl_relaxed(bank->base_reg + reg);
92} 92}
93 93
94/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 94/* XXX: FIQ and additional INTC support (only MPU at the moment) */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 48094b58c88f..fd88edeb027f 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -70,18 +70,18 @@ struct omap_mux_partition *omap_mux_get(const char *name)
70u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg) 70u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
71{ 71{
72 if (partition->flags & OMAP_MUX_REG_8BIT) 72 if (partition->flags & OMAP_MUX_REG_8BIT)
73 return __raw_readb(partition->base + reg); 73 return readb_relaxed(partition->base + reg);
74 else 74 else
75 return __raw_readw(partition->base + reg); 75 return readw_relaxed(partition->base + reg);
76} 76}
77 77
78void omap_mux_write(struct omap_mux_partition *partition, u16 val, 78void omap_mux_write(struct omap_mux_partition *partition, u16 val,
79 u16 reg) 79 u16 reg)
80{ 80{
81 if (partition->flags & OMAP_MUX_REG_8BIT) 81 if (partition->flags & OMAP_MUX_REG_8BIT)
82 __raw_writeb(val, partition->base + reg); 82 writeb_relaxed(val, partition->base + reg);
83 else 83 else
84 __raw_writew(val, partition->base + reg); 84 writew_relaxed(val, partition->base + reg);
85} 85}
86 86
87void omap_mux_write_array(struct omap_mux_partition *partition, 87void omap_mux_write_array(struct omap_mux_partition *partition,
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 40c5d5f1451c..4993d4bfe9b2 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -31,10 +31,6 @@
31 * register AuxCoreBoot0. 31 * register AuxCoreBoot0.
32 */ 32 */
33ENTRY(omap5_secondary_startup) 33ENTRY(omap5_secondary_startup)
34.arm
35THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
36THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
37THUMB( .thumb ) @ switch to Thumb now.
38wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 34wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
39 ldr r0, [r2] 35 ldr r0, [r2]
40 mov r0, r0, lsr #5 36 mov r0, r0, lsr #5
@@ -43,7 +39,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
43 cmp r0, r4 39 cmp r0, r4
44 bne wait 40 bne wait
45 b secondary_startup 41 b secondary_startup
46END(omap5_secondary_startup) 42ENDPROC(omap5_secondary_startup)
47/* 43/*
48 * OMAP4 specific entry point for secondary CPU to jump from ROM 44 * OMAP4 specific entry point for secondary CPU to jump from ROM
49 * code. This routine also provides a holding flag into which 45 * code. This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 458f72f9dc8f..971791fe9a3f 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -39,7 +39,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
39 if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0) 39 if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
40 pr_err("Secure clear status failed\n"); 40 pr_err("Secure clear status failed\n");
41 } else { 41 } else {
42 __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0); 42 writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0);
43 } 43 }
44 44
45 45
@@ -53,7 +53,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
53 boot_cpu = omap_read_auxcoreboot0(); 53 boot_cpu = omap_read_auxcoreboot0();
54 else 54 else
55 boot_cpu = 55 boot_cpu =
56 __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5; 56 readl_relaxed(base + OMAP_AUX_CORE_BOOT_0) >> 5;
57 57
58 if (boot_cpu == smp_processor_id()) { 58 if (boot_cpu == smp_processor_id()) {
59 /* 59 /*
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 667915d236f3..4001325f90fb 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -116,7 +116,7 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
116{ 116{
117 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 117 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
118 118
119 __raw_writel(addr, pm_info->wkup_sar_addr); 119 writel_relaxed(addr, pm_info->wkup_sar_addr);
120} 120}
121 121
122/* 122/*
@@ -141,7 +141,7 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
141 break; 141 break;
142 } 142 }
143 143
144 __raw_writel(scu_pwr_st, pm_info->scu_sar_addr); 144 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
145} 145}
146 146
147/* Helper functions for MPUSS OSWR */ 147/* Helper functions for MPUSS OSWR */
@@ -179,7 +179,7 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
179{ 179{
180 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 180 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
181 181
182 __raw_writel(save_state, pm_info->l2x0_sar_addr); 182 writel_relaxed(save_state, pm_info->l2x0_sar_addr);
183} 183}
184 184
185/* 185/*
@@ -187,19 +187,15 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
187 * in every restore MPUSS OFF path. 187 * in every restore MPUSS OFF path.
188 */ 188 */
189#ifdef CONFIG_CACHE_L2X0 189#ifdef CONFIG_CACHE_L2X0
190static void save_l2x0_context(void) 190static void __init save_l2x0_context(void)
191{ 191{
192 u32 val; 192 writel_relaxed(l2x0_saved_regs.aux_ctrl,
193 void __iomem *l2x0_base = omap4_get_l2cache_base(); 193 sar_base + L2X0_AUXCTRL_OFFSET);
194 if (l2x0_base) { 194 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
195 val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); 195 sar_base + L2X0_PREFETCH_CTRL_OFFSET);
196 __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
197 val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
198 __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
199 }
200} 196}
201#else 197#else
202static void save_l2x0_context(void) 198static void __init save_l2x0_context(void)
203{} 199{}
204#endif 200#endif
205 201
@@ -386,9 +382,9 @@ int __init omap4_mpuss_init(void)
386 382
387 /* Save device type on scratchpad for low level code to use */ 383 /* Save device type on scratchpad for low level code to use */
388 if (omap_type() != OMAP2_DEVICE_TYPE_GP) 384 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
389 __raw_writel(1, sar_base + OMAP_TYPE_OFFSET); 385 writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET);
390 else 386 else
391 __raw_writel(0, sar_base + OMAP_TYPE_OFFSET); 387 writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET);
392 388
393 save_l2x0_context(); 389 save_l2x0_context();
394 390
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 17550aa39d0f..256e84ef0f67 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -99,7 +99,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
99 if (omap_secure_apis_support()) 99 if (omap_secure_apis_support())
100 omap_modify_auxcoreboot0(0x200, 0xfffffdff); 100 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
101 else 101 else
102 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); 102 writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
103 103
104 if (!cpu1_clkdm && !cpu1_pwrdm) { 104 if (!cpu1_clkdm && !cpu1_pwrdm) {
105 cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); 105 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
@@ -227,8 +227,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
227 if (omap_secure_apis_support()) 227 if (omap_secure_apis_support())
228 omap_auxcoreboot_addr(virt_to_phys(startup_addr)); 228 omap_auxcoreboot_addr(virt_to_phys(startup_addr));
229 else 229 else
230 __raw_writel(virt_to_phys(omap5_secondary_startup), 230 writel_relaxed(virt_to_phys(omap5_secondary_startup),
231 base + OMAP_AUX_CORE_BOOT_1); 231 base + OMAP_AUX_CORE_BOOT_1);
232 232
233} 233}
234 234
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 693fe486e917..37843a7d3639 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -60,19 +60,19 @@ static unsigned int omap_secure_apis;
60 */ 60 */
61static inline u32 wakeupgen_readl(u8 idx, u32 cpu) 61static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
62{ 62{
63 return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 + 63 return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
64 (cpu * CPU_ENA_OFFSET) + (idx * 4)); 64 (cpu * CPU_ENA_OFFSET) + (idx * 4));
65} 65}
66 66
67static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu) 67static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
68{ 68{
69 __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + 69 writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
70 (cpu * CPU_ENA_OFFSET) + (idx * 4)); 70 (cpu * CPU_ENA_OFFSET) + (idx * 4));
71} 71}
72 72
73static inline void sar_writel(u32 val, u32 offset, u8 idx) 73static inline void sar_writel(u32 val, u32 offset, u8 idx)
74{ 74{
75 __raw_writel(val, sar_base + offset + (idx * 4)); 75 writel_relaxed(val, sar_base + offset + (idx * 4));
76} 76}
77 77
78static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index) 78static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
@@ -231,21 +231,21 @@ static inline void omap4_irq_save_context(void)
231 } 231 }
232 232
233 /* Save AuxBoot* registers */ 233 /* Save AuxBoot* registers */
234 val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); 234 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
235 __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET); 235 writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
236 val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); 236 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
237 __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET); 237 writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
238 238
239 /* Save SyncReq generation logic */ 239 /* Save SyncReq generation logic */
240 val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); 240 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
241 __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET); 241 writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
242 val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN); 242 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
243 __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET); 243 writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
244 244
245 /* Set the Backup Bit Mask status */ 245 /* Set the Backup Bit Mask status */
246 val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); 246 val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
247 val |= SAR_BACKUP_STATUS_WAKEUPGEN; 247 val |= SAR_BACKUP_STATUS_WAKEUPGEN;
248 __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET); 248 writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
249 249
250} 250}
251 251
@@ -264,15 +264,15 @@ static inline void omap5_irq_save_context(void)
264 } 264 }
265 265
266 /* Save AuxBoot* registers */ 266 /* Save AuxBoot* registers */
267 val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); 267 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
268 __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); 268 writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
269 val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); 269 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
270 __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); 270 writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
271 271
272 /* Set the Backup Bit Mask status */ 272 /* Set the Backup Bit Mask status */
273 val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); 273 val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
274 val |= SAR_BACKUP_STATUS_WAKEUPGEN; 274 val |= SAR_BACKUP_STATUS_WAKEUPGEN;
275 __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); 275 writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
276 276
277} 277}
278 278
@@ -306,9 +306,9 @@ static void irq_sar_clear(void)
306 if (soc_is_omap54xx()) 306 if (soc_is_omap54xx())
307 offset = OMAP5_SAR_BACKUP_STATUS_OFFSET; 307 offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
308 308
309 val = __raw_readl(sar_base + offset); 309 val = readl_relaxed(sar_base + offset);
310 val &= ~SAR_BACKUP_STATUS_WAKEUPGEN; 310 val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
311 __raw_writel(val, sar_base + offset); 311 writel_relaxed(val, sar_base + offset);
312} 312}
313 313
314/* 314/*
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 95e171a055f3..326cd982a3cb 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -125,25 +125,25 @@ void __init gic_init_irq(void)
125void gic_dist_disable(void) 125void gic_dist_disable(void)
126{ 126{
127 if (gic_dist_base_addr) 127 if (gic_dist_base_addr)
128 __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL); 128 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
129} 129}
130 130
131void gic_dist_enable(void) 131void gic_dist_enable(void)
132{ 132{
133 if (gic_dist_base_addr) 133 if (gic_dist_base_addr)
134 __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL); 134 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
135} 135}
136 136
137bool gic_dist_disabled(void) 137bool gic_dist_disabled(void)
138{ 138{
139 return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); 139 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
140} 140}
141 141
142void gic_timer_retrigger(void) 142void gic_timer_retrigger(void)
143{ 143{
144 u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT); 144 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
145 u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET); 145 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
146 u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL); 146 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
147 147
148 if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) { 148 if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
149 /* 149 /*
@@ -151,11 +151,11 @@ void gic_timer_retrigger(void)
151 * disabled. Ack the pending interrupt, and retrigger it. 151 * disabled. Ack the pending interrupt, and retrigger it.
152 */ 152 */
153 pr_warn("%s: lost localtimer interrupt\n", __func__); 153 pr_warn("%s: lost localtimer interrupt\n", __func__);
154 __raw_writel(1, twd_base + TWD_TIMER_INTSTAT); 154 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
155 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) { 155 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
156 __raw_writel(1, twd_base + TWD_TIMER_COUNTER); 156 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
157 twd_ctrl |= TWD_TIMER_CONTROL_ENABLE; 157 twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
158 __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL); 158 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
159 } 159 }
160 } 160 }
161} 161}
@@ -167,75 +167,57 @@ void __iomem *omap4_get_l2cache_base(void)
167 return l2cache_base; 167 return l2cache_base;
168} 168}
169 169
170static void omap4_l2x0_disable(void) 170static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
171{ 171{
172 outer_flush_all(); 172 unsigned smc_op;
173 /* Disable PL310 L2 Cache controller */
174 omap_smc1(0x102, 0x0);
175}
176 173
177static void omap4_l2x0_set_debug(unsigned long val) 174 switch (reg) {
178{ 175 case L2X0_CTRL:
179 /* Program PL310 L2 Cache controller debug register */ 176 smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
180 omap_smc1(0x100, val); 177 break;
178
179 case L2X0_AUX_CTRL:
180 smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
181 break;
182
183 case L2X0_DEBUG_CTRL:
184 smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
185 break;
186
187 case L310_PREFETCH_CTRL:
188 smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
189 break;
190
191 default:
192 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
193 return;
194 }
195
196 omap_smc1(smc_op, val);
181} 197}
182 198
183static int __init omap_l2_cache_init(void) 199int __init omap_l2_cache_init(void)
184{ 200{
185 u32 aux_ctrl = 0; 201 u32 aux_ctrl;
186
187 /*
188 * To avoid code running on other OMAPs in
189 * multi-omap builds
190 */
191 if (!cpu_is_omap44xx())
192 return -ENODEV;
193 202
194 /* Static mapping, never released */ 203 /* Static mapping, never released */
195 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); 204 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
196 if (WARN_ON(!l2cache_base)) 205 if (WARN_ON(!l2cache_base))
197 return -ENOMEM; 206 return -ENOMEM;
198 207
199 /* 208 /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
200 * 16-way associativity, parity disabled 209 aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
201 * Way size - 32KB (es1.0) 210 L310_AUX_CTRL_DATA_PREFETCH |
202 * Way size - 64KB (es2.0 +) 211 L310_AUX_CTRL_INSTR_PREFETCH;
203 */
204 aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
205 (0x1 << 25) |
206 (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
207 (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
208
209 if (omap_rev() == OMAP4430_REV_ES1_0) {
210 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
211 } else {
212 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
213 (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
214 (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
215 (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
216 (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
217 }
218 if (omap_rev() != OMAP4430_REV_ES1_0)
219 omap_smc1(0x109, aux_ctrl);
220
221 /* Enable PL310 L2 Cache controller */
222 omap_smc1(0x102, 0x1);
223 212
213 outer_cache.write_sec = omap4_l2c310_write_sec;
224 if (of_have_populated_dt()) 214 if (of_have_populated_dt())
225 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); 215 l2x0_of_init(aux_ctrl, 0xcf9fffff);
226 else 216 else
227 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); 217 l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);
228
229 /*
230 * Override default outer_cache.disable with a OMAP4
231 * specific one
232 */
233 outer_cache.disable = omap4_l2x0_disable;
234 outer_cache.set_debug = omap4_l2x0_set_debug;
235 218
236 return 0; 219 return 0;
237} 220}
238omap_early_initcall(omap_l2_cache_init);
239#endif 221#endif
240 222
241void __iomem *omap4_get_sar_ram_base(void) 223void __iomem *omap4_get_sar_ram_base(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 66c60fe1104c..f7bb435bb543 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -72,7 +72,7 @@
72 * | (../mach-omap2/omap_hwmod*) | 72 * | (../mach-omap2/omap_hwmod*) |
73 * +-------------------------------+ 73 * +-------------------------------+
74 * | OMAP clock/PRCM/register fns | 74 * | OMAP clock/PRCM/register fns |
75 * | (__raw_{read,write}l, clk*) | 75 * | ({read,write}l_relaxed, clk*) |
76 * +-------------------------------+ 76 * +-------------------------------+
77 * 77 *
78 * Device drivers should not contain any OMAP-specific code or data in 78 * Device drivers should not contain any OMAP-specific code or data in
@@ -3230,17 +3230,17 @@ static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
3230u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) 3230u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
3231{ 3231{
3232 if (oh->flags & HWMOD_16BIT_REG) 3232 if (oh->flags & HWMOD_16BIT_REG)
3233 return __raw_readw(oh->_mpu_rt_va + reg_offs); 3233 return readw_relaxed(oh->_mpu_rt_va + reg_offs);
3234 else 3234 else
3235 return __raw_readl(oh->_mpu_rt_va + reg_offs); 3235 return readl_relaxed(oh->_mpu_rt_va + reg_offs);
3236} 3236}
3237 3237
3238void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) 3238void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
3239{ 3239{
3240 if (oh->flags & HWMOD_16BIT_REG) 3240 if (oh->flags & HWMOD_16BIT_REG)
3241 __raw_writew(v, oh->_mpu_rt_va + reg_offs); 3241 writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
3242 else 3242 else
3243 __raw_writel(v, oh->_mpu_rt_va + reg_offs); 3243 writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
3244} 3244}
3245 3245
3246/** 3246/**
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 0f178623e7da..a579b89ce9b7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -24,6 +24,7 @@
24#include "prm33xx.h" 24#include "prm33xx.h"
25#include "omap_hwmod_33xx_43xx_common_data.h" 25#include "omap_hwmod_33xx_43xx_common_data.h"
26#include "prcm43xx.h" 26#include "prcm43xx.h"
27#include "common.h"
27 28
28#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) 29#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
29#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) 30#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 71ac7d5f3385..1cd0cfdc03e0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3689,12 +3689,9 @@ static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
3689 .rev_offs = 0x0000, 3689 .rev_offs = 0x0000,
3690 .sysc_offs = 0x0010, 3690 .sysc_offs = 0x0010,
3691 .syss_offs = 0x0014, 3691 .syss_offs = 0x0014,
3692 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | 3692 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
3693 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | 3693 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3694 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 3694 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3695 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3696 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3697 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3698 .sysc_fields = &omap_hwmod_sysc_type1, 3695 .sysc_fields = &omap_hwmod_sysc_type1,
3699}; 3696};
3700 3697
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 1219280bb976..41e54f759934 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -3635,15 +3635,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3635 .master = &omap44xx_l4_abe_hwmod, 3635 .master = &omap44xx_l4_abe_hwmod,
3636 .slave = &omap44xx_dmic_hwmod, 3636 .slave = &omap44xx_dmic_hwmod,
3637 .clk = "ocp_abe_iclk", 3637 .clk = "ocp_abe_iclk",
3638 .user = OCP_USER_MPU, 3638 .user = OCP_USER_MPU | OCP_USER_SDMA,
3639};
3640
3641/* l4_abe -> dmic (dma) */
3642static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
3643 .master = &omap44xx_l4_abe_hwmod,
3644 .slave = &omap44xx_dmic_hwmod,
3645 .clk = "ocp_abe_iclk",
3646 .user = OCP_USER_SDMA,
3647}; 3639};
3648 3640
3649/* dsp -> iva */ 3641/* dsp -> iva */
@@ -4209,15 +4201,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4209 .master = &omap44xx_l4_abe_hwmod, 4201 .master = &omap44xx_l4_abe_hwmod,
4210 .slave = &omap44xx_mcbsp1_hwmod, 4202 .slave = &omap44xx_mcbsp1_hwmod,
4211 .clk = "ocp_abe_iclk", 4203 .clk = "ocp_abe_iclk",
4212 .user = OCP_USER_MPU, 4204 .user = OCP_USER_MPU | OCP_USER_SDMA,
4213};
4214
4215/* l4_abe -> mcbsp1 (dma) */
4216static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4217 .master = &omap44xx_l4_abe_hwmod,
4218 .slave = &omap44xx_mcbsp1_hwmod,
4219 .clk = "ocp_abe_iclk",
4220 .user = OCP_USER_SDMA,
4221}; 4205};
4222 4206
4223/* l4_abe -> mcbsp2 */ 4207/* l4_abe -> mcbsp2 */
@@ -4225,15 +4209,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4225 .master = &omap44xx_l4_abe_hwmod, 4209 .master = &omap44xx_l4_abe_hwmod,
4226 .slave = &omap44xx_mcbsp2_hwmod, 4210 .slave = &omap44xx_mcbsp2_hwmod,
4227 .clk = "ocp_abe_iclk", 4211 .clk = "ocp_abe_iclk",
4228 .user = OCP_USER_MPU, 4212 .user = OCP_USER_MPU | OCP_USER_SDMA,
4229};
4230
4231/* l4_abe -> mcbsp2 (dma) */
4232static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4233 .master = &omap44xx_l4_abe_hwmod,
4234 .slave = &omap44xx_mcbsp2_hwmod,
4235 .clk = "ocp_abe_iclk",
4236 .user = OCP_USER_SDMA,
4237}; 4213};
4238 4214
4239/* l4_abe -> mcbsp3 */ 4215/* l4_abe -> mcbsp3 */
@@ -4241,15 +4217,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4241 .master = &omap44xx_l4_abe_hwmod, 4217 .master = &omap44xx_l4_abe_hwmod,
4242 .slave = &omap44xx_mcbsp3_hwmod, 4218 .slave = &omap44xx_mcbsp3_hwmod,
4243 .clk = "ocp_abe_iclk", 4219 .clk = "ocp_abe_iclk",
4244 .user = OCP_USER_MPU, 4220 .user = OCP_USER_MPU | OCP_USER_SDMA,
4245};
4246
4247/* l4_abe -> mcbsp3 (dma) */
4248static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
4249 .master = &omap44xx_l4_abe_hwmod,
4250 .slave = &omap44xx_mcbsp3_hwmod,
4251 .clk = "ocp_abe_iclk",
4252 .user = OCP_USER_SDMA,
4253}; 4221};
4254 4222
4255/* l4_per -> mcbsp4 */ 4223/* l4_per -> mcbsp4 */
@@ -4265,15 +4233,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4265 .master = &omap44xx_l4_abe_hwmod, 4233 .master = &omap44xx_l4_abe_hwmod,
4266 .slave = &omap44xx_mcpdm_hwmod, 4234 .slave = &omap44xx_mcpdm_hwmod,
4267 .clk = "ocp_abe_iclk", 4235 .clk = "ocp_abe_iclk",
4268 .user = OCP_USER_MPU, 4236 .user = OCP_USER_MPU | OCP_USER_SDMA,
4269};
4270
4271/* l4_abe -> mcpdm (dma) */
4272static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
4273 .master = &omap44xx_l4_abe_hwmod,
4274 .slave = &omap44xx_mcpdm_hwmod,
4275 .clk = "ocp_abe_iclk",
4276 .user = OCP_USER_SDMA,
4277}; 4237};
4278 4238
4279/* l4_per -> mcspi1 */ 4239/* l4_per -> mcspi1 */
@@ -4575,15 +4535,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4575 .master = &omap44xx_l4_abe_hwmod, 4535 .master = &omap44xx_l4_abe_hwmod,
4576 .slave = &omap44xx_timer5_hwmod, 4536 .slave = &omap44xx_timer5_hwmod,
4577 .clk = "ocp_abe_iclk", 4537 .clk = "ocp_abe_iclk",
4578 .user = OCP_USER_MPU, 4538 .user = OCP_USER_MPU | OCP_USER_SDMA,
4579};
4580
4581/* l4_abe -> timer5 (dma) */
4582static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4583 .master = &omap44xx_l4_abe_hwmod,
4584 .slave = &omap44xx_timer5_hwmod,
4585 .clk = "ocp_abe_iclk",
4586 .user = OCP_USER_SDMA,
4587}; 4539};
4588 4540
4589/* l4_abe -> timer6 */ 4541/* l4_abe -> timer6 */
@@ -4591,15 +4543,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4591 .master = &omap44xx_l4_abe_hwmod, 4543 .master = &omap44xx_l4_abe_hwmod,
4592 .slave = &omap44xx_timer6_hwmod, 4544 .slave = &omap44xx_timer6_hwmod,
4593 .clk = "ocp_abe_iclk", 4545 .clk = "ocp_abe_iclk",
4594 .user = OCP_USER_MPU, 4546 .user = OCP_USER_MPU | OCP_USER_SDMA,
4595};
4596
4597/* l4_abe -> timer6 (dma) */
4598static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4599 .master = &omap44xx_l4_abe_hwmod,
4600 .slave = &omap44xx_timer6_hwmod,
4601 .clk = "ocp_abe_iclk",
4602 .user = OCP_USER_SDMA,
4603}; 4547};
4604 4548
4605/* l4_abe -> timer7 */ 4549/* l4_abe -> timer7 */
@@ -4607,15 +4551,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4607 .master = &omap44xx_l4_abe_hwmod, 4551 .master = &omap44xx_l4_abe_hwmod,
4608 .slave = &omap44xx_timer7_hwmod, 4552 .slave = &omap44xx_timer7_hwmod,
4609 .clk = "ocp_abe_iclk", 4553 .clk = "ocp_abe_iclk",
4610 .user = OCP_USER_MPU, 4554 .user = OCP_USER_MPU | OCP_USER_SDMA,
4611};
4612
4613/* l4_abe -> timer7 (dma) */
4614static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4615 .master = &omap44xx_l4_abe_hwmod,
4616 .slave = &omap44xx_timer7_hwmod,
4617 .clk = "ocp_abe_iclk",
4618 .user = OCP_USER_SDMA,
4619}; 4555};
4620 4556
4621/* l4_abe -> timer8 */ 4557/* l4_abe -> timer8 */
@@ -4623,15 +4559,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4623 .master = &omap44xx_l4_abe_hwmod, 4559 .master = &omap44xx_l4_abe_hwmod,
4624 .slave = &omap44xx_timer8_hwmod, 4560 .slave = &omap44xx_timer8_hwmod,
4625 .clk = "ocp_abe_iclk", 4561 .clk = "ocp_abe_iclk",
4626 .user = OCP_USER_MPU, 4562 .user = OCP_USER_MPU | OCP_USER_SDMA,
4627};
4628
4629/* l4_abe -> timer8 (dma) */
4630static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4631 .master = &omap44xx_l4_abe_hwmod,
4632 .slave = &omap44xx_timer8_hwmod,
4633 .clk = "ocp_abe_iclk",
4634 .user = OCP_USER_SDMA,
4635}; 4563};
4636 4564
4637/* l4_per -> timer9 */ 4565/* l4_per -> timer9 */
@@ -4831,7 +4759,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4831 &omap44xx_l3_instr__debugss, 4759 &omap44xx_l3_instr__debugss,
4832 &omap44xx_l4_cfg__dma_system, 4760 &omap44xx_l4_cfg__dma_system,
4833 &omap44xx_l4_abe__dmic, 4761 &omap44xx_l4_abe__dmic,
4834 &omap44xx_l4_abe__dmic_dma,
4835 &omap44xx_dsp__iva, 4762 &omap44xx_dsp__iva,
4836 /* &omap44xx_dsp__sl2if, */ 4763 /* &omap44xx_dsp__sl2if, */
4837 &omap44xx_l4_cfg__dsp, 4764 &omap44xx_l4_cfg__dsp,
@@ -4874,14 +4801,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4874 &omap44xx_l4_abe__mcasp, 4801 &omap44xx_l4_abe__mcasp,
4875 &omap44xx_l4_abe__mcasp_dma, 4802 &omap44xx_l4_abe__mcasp_dma,
4876 &omap44xx_l4_abe__mcbsp1, 4803 &omap44xx_l4_abe__mcbsp1,
4877 &omap44xx_l4_abe__mcbsp1_dma,
4878 &omap44xx_l4_abe__mcbsp2, 4804 &omap44xx_l4_abe__mcbsp2,
4879 &omap44xx_l4_abe__mcbsp2_dma,
4880 &omap44xx_l4_abe__mcbsp3, 4805 &omap44xx_l4_abe__mcbsp3,
4881 &omap44xx_l4_abe__mcbsp3_dma,
4882 &omap44xx_l4_per__mcbsp4, 4806 &omap44xx_l4_per__mcbsp4,
4883 &omap44xx_l4_abe__mcpdm, 4807 &omap44xx_l4_abe__mcpdm,
4884 &omap44xx_l4_abe__mcpdm_dma,
4885 &omap44xx_l4_per__mcspi1, 4808 &omap44xx_l4_per__mcspi1,
4886 &omap44xx_l4_per__mcspi2, 4809 &omap44xx_l4_per__mcspi2,
4887 &omap44xx_l4_per__mcspi3, 4810 &omap44xx_l4_per__mcspi3,
@@ -4913,13 +4836,9 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4913 &omap44xx_l4_per__timer3, 4836 &omap44xx_l4_per__timer3,
4914 &omap44xx_l4_per__timer4, 4837 &omap44xx_l4_per__timer4,
4915 &omap44xx_l4_abe__timer5, 4838 &omap44xx_l4_abe__timer5,
4916 &omap44xx_l4_abe__timer5_dma,
4917 &omap44xx_l4_abe__timer6, 4839 &omap44xx_l4_abe__timer6,
4918 &omap44xx_l4_abe__timer6_dma,
4919 &omap44xx_l4_abe__timer7, 4840 &omap44xx_l4_abe__timer7,
4920 &omap44xx_l4_abe__timer7_dma,
4921 &omap44xx_l4_abe__timer8, 4841 &omap44xx_l4_abe__timer8,
4922 &omap44xx_l4_abe__timer8_dma,
4923 &omap44xx_l4_per__timer9, 4842 &omap44xx_l4_per__timer9,
4924 &omap44xx_l4_per__timer10, 4843 &omap44xx_l4_per__timer10,
4925 &omap44xx_l4_per__timer11, 4844 &omap44xx_l4_per__timer11,
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index e829664e6a6c..290213f2cbe3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -334,6 +334,235 @@ static struct omap_hwmod omap54xx_dmic_hwmod = {
334}; 334};
335 335
336/* 336/*
337 * 'dss' class
338 * display sub-system
339 */
340static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
341 .rev_offs = 0x0000,
342 .syss_offs = 0x0014,
343 .sysc_flags = SYSS_HAS_RESET_STATUS,
344};
345
346static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
347 .name = "dss",
348 .sysc = &omap54xx_dss_sysc,
349 .reset = omap_dss_reset,
350};
351
352/* dss */
353static struct omap_hwmod_opt_clk dss_opt_clks[] = {
354 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
355 { .role = "sys_clk", .clk = "dss_sys_clk" },
356 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
357};
358
359static struct omap_hwmod omap54xx_dss_hwmod = {
360 .name = "dss_core",
361 .class = &omap54xx_dss_hwmod_class,
362 .clkdm_name = "dss_clkdm",
363 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
364 .main_clk = "dss_dss_clk",
365 .prcm = {
366 .omap4 = {
367 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
368 .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
369 .modulemode = MODULEMODE_SWCTRL,
370 },
371 },
372 .opt_clks = dss_opt_clks,
373 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
374};
375
376/*
377 * 'dispc' class
378 * display controller
379 */
380
381static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
382 .rev_offs = 0x0000,
383 .sysc_offs = 0x0010,
384 .syss_offs = 0x0014,
385 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
386 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
387 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
388 SYSS_HAS_RESET_STATUS),
389 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
390 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
391 .sysc_fields = &omap_hwmod_sysc_type1,
392};
393
394static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
395 .name = "dispc",
396 .sysc = &omap54xx_dispc_sysc,
397};
398
399/* dss_dispc */
400static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
401 { .role = "sys_clk", .clk = "dss_sys_clk" },
402};
403
404/* dss_dispc dev_attr */
405static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
406 .has_framedonetv_irq = 1,
407 .manager_count = 4,
408};
409
410static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
411 .name = "dss_dispc",
412 .class = &omap54xx_dispc_hwmod_class,
413 .clkdm_name = "dss_clkdm",
414 .main_clk = "dss_dss_clk",
415 .prcm = {
416 .omap4 = {
417 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
418 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
419 },
420 },
421 .opt_clks = dss_dispc_opt_clks,
422 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
423 .dev_attr = &dss_dispc_dev_attr,
424};
425
426/*
427 * 'dsi1' class
428 * display serial interface controller
429 */
430
431static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
432 .rev_offs = 0x0000,
433 .sysc_offs = 0x0010,
434 .syss_offs = 0x0014,
435 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
436 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
437 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
438 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
439 .sysc_fields = &omap_hwmod_sysc_type1,
440};
441
442static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
443 .name = "dsi1",
444 .sysc = &omap54xx_dsi1_sysc,
445};
446
447/* dss_dsi1_a */
448static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
449 { .role = "sys_clk", .clk = "dss_sys_clk" },
450};
451
452static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
453 .name = "dss_dsi1",
454 .class = &omap54xx_dsi1_hwmod_class,
455 .clkdm_name = "dss_clkdm",
456 .main_clk = "dss_dss_clk",
457 .prcm = {
458 .omap4 = {
459 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
460 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
461 },
462 },
463 .opt_clks = dss_dsi1_a_opt_clks,
464 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
465};
466
467/* dss_dsi1_c */
468static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
469 { .role = "sys_clk", .clk = "dss_sys_clk" },
470};
471
472static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
473 .name = "dss_dsi2",
474 .class = &omap54xx_dsi1_hwmod_class,
475 .clkdm_name = "dss_clkdm",
476 .main_clk = "dss_dss_clk",
477 .prcm = {
478 .omap4 = {
479 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
480 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
481 },
482 },
483 .opt_clks = dss_dsi1_c_opt_clks,
484 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
485};
486
487/*
488 * 'hdmi' class
489 * hdmi controller
490 */
491
492static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
493 .rev_offs = 0x0000,
494 .sysc_offs = 0x0010,
495 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
496 SYSC_HAS_SOFTRESET),
497 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
498 SIDLE_SMART_WKUP),
499 .sysc_fields = &omap_hwmod_sysc_type2,
500};
501
502static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
503 .name = "hdmi",
504 .sysc = &omap54xx_hdmi_sysc,
505};
506
507static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
508 { .role = "sys_clk", .clk = "dss_sys_clk" },
509};
510
511static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
512 .name = "dss_hdmi",
513 .class = &omap54xx_hdmi_hwmod_class,
514 .clkdm_name = "dss_clkdm",
515 .main_clk = "dss_48mhz_clk",
516 .prcm = {
517 .omap4 = {
518 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
519 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
520 },
521 },
522 .opt_clks = dss_hdmi_opt_clks,
523 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
524};
525
526/*
527 * 'rfbi' class
528 * remote frame buffer interface
529 */
530
531static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
532 .rev_offs = 0x0000,
533 .sysc_offs = 0x0010,
534 .syss_offs = 0x0014,
535 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
536 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
537 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
538 .sysc_fields = &omap_hwmod_sysc_type1,
539};
540
541static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
542 .name = "rfbi",
543 .sysc = &omap54xx_rfbi_sysc,
544};
545
546/* dss_rfbi */
547static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
548 { .role = "ick", .clk = "l3_iclk_div" },
549};
550
551static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
552 .name = "dss_rfbi",
553 .class = &omap54xx_rfbi_hwmod_class,
554 .clkdm_name = "dss_clkdm",
555 .prcm = {
556 .omap4 = {
557 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
558 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
559 },
560 },
561 .opt_clks = dss_rfbi_opt_clks,
562 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
563};
564
565/*
337 * 'emif' class 566 * 'emif' class
338 * external memory interface no1 (wrapper) 567 * external memory interface no1 (wrapper)
339 */ 568 */
@@ -1974,6 +2203,54 @@ static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1974 .user = OCP_USER_MPU, 2203 .user = OCP_USER_MPU,
1975}; 2204};
1976 2205
2206/* l3_main_2 -> dss */
2207static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
2208 .master = &omap54xx_l3_main_2_hwmod,
2209 .slave = &omap54xx_dss_hwmod,
2210 .clk = "l3_iclk_div",
2211 .user = OCP_USER_MPU | OCP_USER_SDMA,
2212};
2213
2214/* l3_main_2 -> dss_dispc */
2215static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
2216 .master = &omap54xx_l3_main_2_hwmod,
2217 .slave = &omap54xx_dss_dispc_hwmod,
2218 .clk = "l3_iclk_div",
2219 .user = OCP_USER_MPU | OCP_USER_SDMA,
2220};
2221
2222/* l3_main_2 -> dss_dsi1_a */
2223static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
2224 .master = &omap54xx_l3_main_2_hwmod,
2225 .slave = &omap54xx_dss_dsi1_a_hwmod,
2226 .clk = "l3_iclk_div",
2227 .user = OCP_USER_MPU | OCP_USER_SDMA,
2228};
2229
2230/* l3_main_2 -> dss_dsi1_c */
2231static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
2232 .master = &omap54xx_l3_main_2_hwmod,
2233 .slave = &omap54xx_dss_dsi1_c_hwmod,
2234 .clk = "l3_iclk_div",
2235 .user = OCP_USER_MPU | OCP_USER_SDMA,
2236};
2237
2238/* l3_main_2 -> dss_hdmi */
2239static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
2240 .master = &omap54xx_l3_main_2_hwmod,
2241 .slave = &omap54xx_dss_hdmi_hwmod,
2242 .clk = "l3_iclk_div",
2243 .user = OCP_USER_MPU | OCP_USER_SDMA,
2244};
2245
2246/* l3_main_2 -> dss_rfbi */
2247static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
2248 .master = &omap54xx_l3_main_2_hwmod,
2249 .slave = &omap54xx_dss_rfbi_hwmod,
2250 .clk = "l3_iclk_div",
2251 .user = OCP_USER_MPU | OCP_USER_SDMA,
2252};
2253
1977/* mpu -> emif1 */ 2254/* mpu -> emif1 */
1978static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = { 2255static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1979 .master = &omap54xx_mpu_hwmod, 2256 .master = &omap54xx_mpu_hwmod,
@@ -2427,6 +2704,12 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2427 &omap54xx_l4_cfg__dma_system, 2704 &omap54xx_l4_cfg__dma_system,
2428 &omap54xx_l4_abe__dmic, 2705 &omap54xx_l4_abe__dmic,
2429 &omap54xx_l4_cfg__mmu_dsp, 2706 &omap54xx_l4_cfg__mmu_dsp,
2707 &omap54xx_l3_main_2__dss,
2708 &omap54xx_l3_main_2__dss_dispc,
2709 &omap54xx_l3_main_2__dss_dsi1_a,
2710 &omap54xx_l3_main_2__dss_dsi1_c,
2711 &omap54xx_l3_main_2__dss_hdmi,
2712 &omap54xx_l3_main_2__dss_rfbi,
2430 &omap54xx_mpu__emif1, 2713 &omap54xx_mpu__emif1,
2431 &omap54xx_mpu__emif2, 2714 &omap54xx_mpu__emif2,
2432 &omap54xx_l4_wkup__gpio1, 2715 &omap54xx_l4_wkup__gpio1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 810c205d668b..20b4398cec05 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -2318,21 +2318,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2318 .user = OCP_USER_MPU | OCP_USER_SDMA, 2318 .user = OCP_USER_MPU | OCP_USER_SDMA,
2319}; 2319};
2320 2320
2321static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
2322 {
2323 .pa_start = 0x4a080000,
2324 .pa_end = 0x4a08001f,
2325 .flags = ADDR_TYPE_RT
2326 },
2327 { }
2328};
2329
2330/* l4_cfg -> ocp2scp1 */ 2321/* l4_cfg -> ocp2scp1 */
2331static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { 2322static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2332 .master = &dra7xx_l4_cfg_hwmod, 2323 .master = &dra7xx_l4_cfg_hwmod,
2333 .slave = &dra7xx_ocp2scp1_hwmod, 2324 .slave = &dra7xx_ocp2scp1_hwmod,
2334 .clk = "l4_root_clk_div", 2325 .clk = "l4_root_clk_div",
2335 .addr = dra7xx_ocp2scp1_addrs,
2336 .user = OCP_USER_MPU | OCP_USER_SDMA, 2326 .user = OCP_USER_MPU | OCP_USER_SDMA,
2337}; 2327};
2338 2328
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index eb8a25de67ed..50640b38f0bf 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -57,7 +57,7 @@ static int __init omap4430_phy_power_down(void)
57 } 57 }
58 58
59 /* Power down the phy */ 59 /* Power down the phy */
60 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); 60 writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
61 61
62 iounmap(ctrl_base); 62 iounmap(ctrl_base);
63 63
@@ -162,7 +162,7 @@ void ti81xx_musb_phy_power(u8 on)
162 return; 162 return;
163 } 163 }
164 164
165 usbphycfg = __raw_readl(scm_base + USBCTRL0); 165 usbphycfg = readl_relaxed(scm_base + USBCTRL0);
166 166
167 if (on) { 167 if (on) {
168 if (cpu_is_ti816x()) { 168 if (cpu_is_ti816x()) {
@@ -181,7 +181,7 @@ void ti81xx_musb_phy_power(u8 on)
181 usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN; 181 usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
182 182
183 } 183 }
184 __raw_writel(usbphycfg, scm_base + USBCTRL0); 184 writel_relaxed(usbphycfg, scm_base + USBCTRL0);
185 185
186 iounmap(scm_base); 186 iounmap(scm_base);
187} 187}
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 615e5b1fb025..6bf626700557 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -46,15 +46,8 @@
46 46
47static bool is_offset_valid; 47static bool is_offset_valid;
48static u8 smps_offset; 48static u8 smps_offset;
49/*
50 * Flag to ensure Smartreflex bit in TWL
51 * being cleared in board file is not overwritten.
52 */
53static bool __initdata twl_sr_enable_autoinit;
54 49
55#define TWL4030_DCDC_GLOBAL_CFG 0x06
56#define REG_SMPS_OFFSET 0xE0 50#define REG_SMPS_OFFSET 0xE0
57#define SMARTREFLEX_ENABLE BIT(3)
58 51
59static unsigned long twl4030_vsel_to_uv(const u8 vsel) 52static unsigned long twl4030_vsel_to_uv(const u8 vsel)
60{ 53{
@@ -251,18 +244,6 @@ int __init omap3_twl_init(void)
251 if (!cpu_is_omap34xx()) 244 if (!cpu_is_omap34xx())
252 return -ENODEV; 245 return -ENODEV;
253 246
254 /*
255 * The smartreflex bit on twl4030 specifies if the setting of voltage
256 * is done over the I2C_SR path. Since this setting is independent of
257 * the actual usage of smartreflex AVS module, we enable TWL SR bit
258 * by default irrespective of whether smartreflex AVS module is enabled
259 * on the OMAP side or not. This is because without this bit enabled,
260 * the voltage scaling through vp forceupdate/bypass mechanism of
261 * voltage scaling will not function on TWL over I2C_SR.
262 */
263 if (!twl_sr_enable_autoinit)
264 omap3_twl_set_sr_bit(true);
265
266 voltdm = voltdm_lookup("mpu_iva"); 247 voltdm = voltdm_lookup("mpu_iva");
267 omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic); 248 omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
268 249
@@ -271,44 +252,3 @@ int __init omap3_twl_init(void)
271 252
272 return 0; 253 return 0;
273} 254}
274
275/**
276 * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
277 * @enable: enable SR mode in twl or not
278 *
279 * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
280 * voltage scaling through OMAP SR works. Else, the smartreflex bit
281 * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
282 * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
283 * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
284 * in those scenarios this bit is to be cleared (enable = false).
285 *
286 * Returns 0 on success, error is returned if I2C read/write fails.
287 */
288int __init omap3_twl_set_sr_bit(bool enable)
289{
290 u8 temp;
291 int ret;
292 if (twl_sr_enable_autoinit)
293 pr_warning("%s: unexpected multiple calls\n", __func__);
294
295 ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
296 TWL4030_DCDC_GLOBAL_CFG);
297 if (ret)
298 goto err;
299
300 if (enable)
301 temp |= SMARTREFLEX_ENABLE;
302 else
303 temp &= ~SMARTREFLEX_ENABLE;
304
305 ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
306 TWL4030_DCDC_GLOBAL_CFG);
307 if (!ret) {
308 twl_sr_enable_autoinit = true;
309 return 0;
310 }
311err:
312 pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
313 return ret;
314}
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index c3b73351cb7a..90c88d498485 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -226,6 +226,14 @@ static void __init am3517_evm_legacy_init(void)
226 am35xx_emac_reset(); 226 am35xx_emac_reset();
227} 227}
228 228
229static struct platform_device omap3_rom_rng_device = {
230 .name = "omap3-rom-rng",
231 .id = -1,
232 .dev = {
233 .platform_data = rx51_secure_rng_call,
234 },
235};
236
229static void __init nokia_n900_legacy_init(void) 237static void __init nokia_n900_legacy_init(void)
230{ 238{
231 hsmmc2_internal_input_clk(); 239 hsmmc2_internal_input_clk();
@@ -239,6 +247,10 @@ static void __init nokia_n900_legacy_init(void)
239 pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n"); 247 pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n");
240 pr_warning("Thumb binaries may crash randomly without this workaround\n"); 248 pr_warning("Thumb binaries may crash randomly without this workaround\n");
241 } 249 }
250
251 pr_info("RX-51: Registring OMAP3 HWRNG device\n");
252 platform_device_register(&omap3_rom_rng_device);
253
242 } 254 }
243} 255}
244#endif /* CONFIG_ARCH_OMAP3 */ 256#endif /* CONFIG_ARCH_OMAP3 */
@@ -254,6 +266,11 @@ static void __init omap4_panda_legacy_init(void)
254{ 266{
255 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53); 267 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53);
256} 268}
269
270static void __init var_som_om44_legacy_init(void)
271{
272 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 41);
273}
257#endif 274#endif
258 275
259#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) 276#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
@@ -364,6 +381,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
364#ifdef CONFIG_ARCH_OMAP4 381#ifdef CONFIG_ARCH_OMAP4
365 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, 382 { "ti,omap4-sdp", omap4_sdp_legacy_init, },
366 { "ti,omap4-panda", omap4_panda_legacy_init, }, 383 { "ti,omap4-panda", omap4_panda_legacy_init, },
384 { "variscite,var-dvk-om44", var_som_om44_legacy_init, },
385 { "variscite,var-stk-om44", var_som_om44_legacy_init, },
367#endif 386#endif
368#ifdef CONFIG_SOC_AM33XX 387#ifdef CONFIG_SOC_AM33XX
369 { "ti,am335x-evmsk", am335x_evmsk_legacy_init, }, 388 { "ti,am335x-evmsk", am335x_evmsk_legacy_init, },
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index e1b41416fbf1..828aee9ea6a8 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -32,11 +32,13 @@
32#include "pm.h" 32#include "pm.h"
33#include "twl-common.h" 33#include "twl-common.h"
34 34
35#ifdef CONFIG_SUSPEND
35/* 36/*
36 * omap_pm_suspend: points to a function that does the SoC-specific 37 * omap_pm_suspend: points to a function that does the SoC-specific
37 * suspend work 38 * suspend work
38 */ 39 */
39int (*omap_pm_suspend)(void); 40static int (*omap_pm_suspend)(void);
41#endif
40 42
41#ifdef CONFIG_PM 43#ifdef CONFIG_PM
42/** 44/**
@@ -243,6 +245,15 @@ static const struct platform_suspend_ops omap_pm_ops = {
243 .valid = suspend_valid_only_mem, 245 .valid = suspend_valid_only_mem,
244}; 246};
245 247
248/**
249 * omap_common_suspend_init - Set common suspend routines for OMAP SoCs
250 * @pm_suspend: function pointer to SoC specific suspend function
251 */
252void omap_common_suspend_init(void *pm_suspend)
253{
254 omap_pm_suspend = pm_suspend;
255 suspend_set_ops(&omap_pm_ops);
256}
246#endif /* CONFIG_SUSPEND */ 257#endif /* CONFIG_SUSPEND */
247 258
248static void __init omap3_init_voltages(void) 259static void __init omap3_init_voltages(void)
@@ -287,32 +298,24 @@ omap_postcore_initcall(omap2_common_pm_init);
287 298
288int __init omap2_common_pm_late_init(void) 299int __init omap2_common_pm_late_init(void)
289{ 300{
290 /* 301 if (of_have_populated_dt()) {
291 * In the case of DT, the PMIC and SR initialization will be done using 302 omap3_twl_init();
292 * a completely different mechanism. 303 omap4_twl_init();
293 * Disable this part if a DT blob is available. 304 }
294 */
295 if (!of_have_populated_dt()) {
296
297 /* Init the voltage layer */
298 omap_pmic_late_init();
299 omap_voltage_late_init();
300 305
301 /* Initialize the voltages */ 306 /* Init the voltage layer */
302 omap3_init_voltages(); 307 omap_pmic_late_init();
303 omap4_init_voltages(); 308 omap_voltage_late_init();
304 309
305 /* Smartreflex device init */ 310 /* Initialize the voltages */
306 omap_devinit_smartreflex(); 311 omap3_init_voltages();
312 omap4_init_voltages();
307 313
308 } 314 /* Smartreflex device init */
315 omap_devinit_smartreflex();
309 316
310 /* cpufreq dummy device instantiation */ 317 /* cpufreq dummy device instantiation */
311 omap_init_cpufreq(); 318 omap_init_cpufreq();
312 319
313#ifdef CONFIG_SUSPEND
314 suspend_set_ops(&omap_pm_ops);
315#endif
316
317 return 0; 320 return 0;
318} 321}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index d4d0fce325c7..e150102d6c06 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -34,7 +34,6 @@ extern void *omap3_secure_ram_storage;
34extern void omap3_pm_off_mode_enable(int); 34extern void omap3_pm_off_mode_enable(int);
35extern void omap_sram_idle(void); 35extern void omap_sram_idle(void);
36extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); 36extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
37extern int (*omap_pm_suspend)(void);
38 37
39#if defined(CONFIG_PM_OPP) 38#if defined(CONFIG_PM_OPP)
40extern int omap3_opp_init(void); 39extern int omap3_opp_init(void);
@@ -147,4 +146,11 @@ static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *
147static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { } 146static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
148#endif 147#endif
149 148
149#ifdef CONFIG_SUSPEND
150void omap_common_suspend_init(void *pm_suspend);
151#else
152static inline void omap_common_suspend_init(void *pm_suspend)
153{
154}
155#endif /* CONFIG_SUSPEND */
150#endif 156#endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 8c0759496c8d..a5ea988ff340 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -229,9 +229,7 @@ static void __init prcm_setup_regs(void)
229 clkdm_for_each(omap_pm_clkdms_setup, NULL); 229 clkdm_for_each(omap_pm_clkdms_setup, NULL);
230 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); 230 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
231 231
232#ifdef CONFIG_SUSPEND 232 omap_common_suspend_init(omap2_enter_full_retention);
233 omap_pm_suspend = omap2_enter_full_retention;
234#endif
235 233
236 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk 234 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
237 * stabilisation */ 235 * stabilisation */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 87099bb6de69..507d8eeaab95 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -50,6 +50,7 @@
50#include "sdrc.h" 50#include "sdrc.h"
51#include "sram.h" 51#include "sram.h"
52#include "control.h" 52#include "control.h"
53#include "vc.h"
53 54
54/* pm34xx errata defined in pm.h */ 55/* pm34xx errata defined in pm.h */
55u16 pm34xx_errata; 56u16 pm34xx_errata;
@@ -288,6 +289,9 @@ void omap_sram_idle(void)
288 } 289 }
289 } 290 }
290 291
292 /* Configure PMIC signaling for I2C4 or sys_off_mode */
293 omap3_vc_set_pmic_signaling(core_next_state);
294
291 omap3_intc_prepare_idle(); 295 omap3_intc_prepare_idle();
292 296
293 /* 297 /*
@@ -391,7 +395,8 @@ restore:
391 395
392 return ret; 396 return ret;
393} 397}
394 398#else
399#define omap3_pm_suspend NULL
395#endif /* CONFIG_SUSPEND */ 400#endif /* CONFIG_SUSPEND */
396 401
397 402
@@ -705,9 +710,7 @@ int __init omap3_pm_init(void)
705 per_clkdm = clkdm_lookup("per_clkdm"); 710 per_clkdm = clkdm_lookup("per_clkdm");
706 wkup_clkdm = clkdm_lookup("wkup_clkdm"); 711 wkup_clkdm = clkdm_lookup("wkup_clkdm");
707 712
708#ifdef CONFIG_SUSPEND 713 omap_common_suspend_init(omap3_pm_suspend);
709 omap_pm_suspend = omap3_pm_suspend;
710#endif
711 714
712 arm_pm_idle = omap3_pm_idle; 715 arm_pm_idle = omap3_pm_idle;
713 omap3_idle_init(); 716 omap3_idle_init();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index eefb30cfcabd..0dda6cf8b855 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -96,6 +96,8 @@ static int omap4_pm_suspend(void)
96 96
97 return 0; 97 return 0;
98} 98}
99#else
100#define omap4_pm_suspend NULL
99#endif /* CONFIG_SUSPEND */ 101#endif /* CONFIG_SUSPEND */
100 102
101static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 103static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
@@ -251,9 +253,7 @@ int __init omap4_pm_init(void)
251 253
252 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 254 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
253 255
254#ifdef CONFIG_SUSPEND 256 omap_common_suspend_init(omap4_pm_suspend);
255 omap_pm_suspend = omap4_pm_suspend;
256#endif
257 257
258 /* Overwrite the default cpu_do_idle() */ 258 /* Overwrite the default cpu_do_idle() */
259 arm_pm_idle = omap_default_idle; 259 arm_pm_idle = omap_default_idle;
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index c0aeabfcf009..c40e5f009826 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -17,7 +17,6 @@
17#include "pm.h" 17#include "pm.h"
18#include "cm.h" 18#include "cm.h"
19#include "cm-regbits-34xx.h" 19#include "cm-regbits-34xx.h"
20#include "cm-regbits-44xx.h"
21#include "prm-regbits-34xx.h" 20#include "prm-regbits-34xx.h"
22#include "prm-regbits-44xx.h" 21#include "prm-regbits-44xx.h"
23 22
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 93a2a6e4260f..faebd5f076af 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -32,6 +32,7 @@
32 32
33#include "powerdomain.h" 33#include "powerdomain.h"
34#include "clockdomain.h" 34#include "clockdomain.h"
35#include "voltage.h"
35 36
36#include "soc.h" 37#include "soc.h"
37#include "pm.h" 38#include "pm.h"
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index da5a59ae77b6..f4727117f6cc 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -21,8 +21,6 @@
21#include <linux/list.h> 21#include <linux/list.h>
22#include <linux/spinlock.h> 22#include <linux/spinlock.h>
23 23
24#include "voltage.h"
25
26/* Powerdomain basic power states */ 24/* Powerdomain basic power states */
27#define PWRDM_POWER_OFF 0x0 25#define PWRDM_POWER_OFF 0x0
28#define PWRDM_POWER_RET 0x1 26#define PWRDM_POWER_RET 0x1
@@ -75,6 +73,7 @@
75 73
76struct clockdomain; 74struct clockdomain;
77struct powerdomain; 75struct powerdomain;
76struct voltagedomain;
78 77
79/** 78/**
80 * struct powerdomain - OMAP powerdomain 79 * struct powerdomain - OMAP powerdomain
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 0e841fd9498a..a8e4b582c527 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -428,6 +428,28 @@
428#define MAX_IOPAD_LATCH_TIME 100 428#define MAX_IOPAD_LATCH_TIME 100
429# ifndef __ASSEMBLER__ 429# ifndef __ASSEMBLER__
430 430
431#include <linux/delay.h>
432
433/**
434 * omap_test_timeout - busy-loop, testing a condition
435 * @cond: condition to test until it evaluates to true
436 * @timeout: maximum number of microseconds in the timeout
437 * @index: loop index (integer)
438 *
439 * Loop waiting for @cond to become true or until at least @timeout
440 * microseconds have passed. To use, define some integer @index in the
441 * calling code. After running, if @index == @timeout, then the loop has
442 * timed out.
443 */
444#define omap_test_timeout(cond, timeout, index) \
445({ \
446 for (index = 0; index < timeout; index++) { \
447 if (cond) \
448 break; \
449 udelay(1); \
450 } \
451})
452
431/** 453/**
432 * struct omap_prcm_irq - describes a PRCM interrupt bit 454 * struct omap_prcm_irq - describes a PRCM interrupt bit
433 * @name: a short name describing the interrupt type, e.g. "wkup" or "io" 455 * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
@@ -458,6 +480,7 @@ struct omap_prcm_irq {
458 * @ocp_barrier: fn ptr to force buffered PRM writes to complete 480 * @ocp_barrier: fn ptr to force buffered PRM writes to complete
459 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs 481 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
460 * @restore_irqen: fn ptr to save and clear IRQENABLE regs 482 * @restore_irqen: fn ptr to save and clear IRQENABLE regs
483 * @reconfigure_io_chain: fn ptr to reconfigure IO chain
461 * @saved_mask: IRQENABLE regs are saved here during suspend 484 * @saved_mask: IRQENABLE regs are saved here during suspend
462 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true 485 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
463 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init 486 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
@@ -479,6 +502,7 @@ struct omap_prcm_irq_setup {
479 void (*ocp_barrier)(void); 502 void (*ocp_barrier)(void);
480 void (*save_and_clear_irqen)(u32 *saved_mask); 503 void (*save_and_clear_irqen)(u32 *saved_mask);
481 void (*restore_irqen)(u32 *saved_mask); 504 void (*restore_irqen)(u32 *saved_mask);
505 void (*reconfigure_io_chain)(void);
482 u32 *saved_mask; 506 u32 *saved_mask;
483 u32 *priority_mask; 507 u32 *priority_mask;
484 int base_irq; 508 int base_irq;
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index c30e44a7fab0..cdbee6326d29 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -30,12 +30,12 @@ void __iomem *prcm_mpu_base;
30 30
31u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg) 31u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
32{ 32{
33 return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); 33 return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
34} 34}
35 35
36void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg) 36void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
37{ 37{
38 __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); 38 writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
39} 39}
40 40
41u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) 41u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 059bd4f49035..ac9cb4550239 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -26,7 +26,6 @@
26#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H 26#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
27 27
28#include "prcm_mpu_44xx_54xx.h" 28#include "prcm_mpu_44xx_54xx.h"
29#include "common.h"
30 29
31#define OMAP4430_PRCM_MPU_BASE 0x48243000 30#define OMAP4430_PRCM_MPU_BASE 0x48243000
32 31
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index cebad565ed37..106132db532b 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -123,8 +123,15 @@
123#define OMAP3430_GLOBAL_SW_RST_SHIFT 1 123#define OMAP3430_GLOBAL_SW_RST_SHIFT 1
124#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 124#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0
125#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) 125#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0)
126#define OMAP3430_SEL_OFF_MASK (1 << 3) 126#define OMAP3430_PRM_VOLTCTRL_SEL_VMODE (1 << 4)
127#define OMAP3430_AUTO_OFF_MASK (1 << 2) 127#define OMAP3430_PRM_VOLTCTRL_SEL_OFF (1 << 3)
128#define OMAP3430_PRM_VOLTCTRL_AUTO_OFF (1 << 2)
129#define OMAP3430_PRM_VOLTCTRL_AUTO_RET (1 << 1)
130#define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP (1 << 0)
128#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) 131#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
129#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) 132#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
133#define OMAP3430_PRM_POLCTRL_OFFMODE_POL (1 << 3)
134#define OMAP3430_PRM_POLCTRL_CLKOUT_POL (1 << 2)
135#define OMAP3430_PRM_POLCTRL_CLKREQ_POL (1 << 1)
136#define OMAP3430_PRM_POLCTRL_EXTVOL_POL (1 << 0)
130#endif 137#endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 623db40fdbbd..48480d557b61 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -17,10 +17,18 @@
17 17
18# ifndef __ASSEMBLER__ 18# ifndef __ASSEMBLER__
19extern void __iomem *prm_base; 19extern void __iomem *prm_base;
20extern u16 prm_features;
20extern void omap2_set_globals_prm(void __iomem *prm); 21extern void omap2_set_globals_prm(void __iomem *prm);
21int of_prcm_init(void); 22int of_prcm_init(void);
22# endif 23# endif
23 24
25/*
26 * prm_features flag values
27 *
28 * PRM_HAS_IO_WAKEUP: has IO wakeup capability
29 * PRM_HAS_VOLTAGE: has voltage domains
30 */
31#define PRM_HAS_IO_WAKEUP (1 << 0)
24 32
25/* 33/*
26 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP 34 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -118,6 +126,7 @@ struct prm_reset_src_map {
118 * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl 126 * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
119 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn 127 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
120 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn 128 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
129 * @late_init: ptr to the late init function
121 * 130 *
122 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are 131 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
123 * deprecated. 132 * deprecated.
@@ -126,6 +135,7 @@ struct prm_ll_data {
126 u32 (*read_reset_sources)(void); 135 u32 (*read_reset_sources)(void);
127 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx); 136 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
128 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx); 137 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
138 int (*late_init)(void);
129}; 139};
130 140
131extern int prm_register(struct prm_ll_data *pld); 141extern int prm_register(struct prm_ll_data *pld);
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 418de9c3b319..a3a3cca2bcc4 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -18,9 +18,6 @@
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/irq.h> 19#include <linux/irq.h>
20 20
21#include "soc.h"
22#include "common.h"
23#include "vp.h"
24#include "powerdomain.h" 21#include "powerdomain.h"
25#include "clockdomain.h" 22#include "clockdomain.h"
26#include "prm2xxx.h" 23#include "prm2xxx.h"
@@ -201,19 +198,11 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
201 198
202int __init omap2xxx_prm_init(void) 199int __init omap2xxx_prm_init(void)
203{ 200{
204 if (!cpu_is_omap24xx())
205 return 0;
206
207 return prm_register(&omap2xxx_prm_ll_data); 201 return prm_register(&omap2xxx_prm_ll_data);
208} 202}
209 203
210static void __exit omap2xxx_prm_exit(void) 204static void __exit omap2xxx_prm_exit(void)
211{ 205{
212 if (!cpu_is_omap24xx()) 206 prm_unregister(&omap2xxx_prm_ll_data);
213 return;
214
215 /* Should never happen */
216 WARN(prm_unregister(&omap2xxx_prm_ll_data),
217 "%s: prm_ll_data function pointer mismatch\n", __func__);
218} 207}
219__exitcall(omap2xxx_prm_exit); 208__exitcall(omap2xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 3194dd87e0e4..d2cb6365716f 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -27,7 +27,7 @@
27 27
28/* 28/*
29 * OMAP2-specific global PRM registers 29 * OMAP2-specific global PRM registers
30 * Use __raw_{read,write}l() with these registers. 30 * Use {read,write}l_relaxed() with these registers.
31 * 31 *
32 * With a few exceptions, these are the register names beginning with 32 * With a few exceptions, these are the register names beginning with
33 * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE 33 * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 947f6adfed0c..c13b4e293ffa 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -16,7 +16,6 @@
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/io.h> 17#include <linux/io.h>
18 18
19#include "common.h"
20#include "powerdomain.h" 19#include "powerdomain.h"
21#include "prm2xxx_3xxx.h" 20#include "prm2xxx_3xxx.h"
22#include "prm-regbits-24xx.h" 21#include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 9624b40836d4..1a3a96392b97 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -55,12 +55,12 @@
55/* Power/reset management domain register get/set */ 55/* Power/reset management domain register get/set */
56static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) 56static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
57{ 57{
58 return __raw_readl(prm_base + module + idx); 58 return readl_relaxed(prm_base + module + idx);
59} 59}
60 60
61static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) 61static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
62{ 62{
63 __raw_writel(val, prm_base + module + idx); 63 writel_relaxed(val, prm_base + module + idx);
64} 64}
65 65
66/* Read-modify-write a register in a PRM module. Caller must lock */ 66/* Read-modify-write a register in a PRM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 720440737744..62709cd2f9c5 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -19,7 +19,6 @@
19#include <linux/err.h> 19#include <linux/err.h>
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include "common.h"
23#include "powerdomain.h" 22#include "powerdomain.h"
24#include "prm33xx.h" 23#include "prm33xx.h"
25#include "prm-regbits-33xx.h" 24#include "prm-regbits-33xx.h"
@@ -27,13 +26,13 @@
27/* Read a register in a PRM instance */ 26/* Read a register in a PRM instance */
28u32 am33xx_prm_read_reg(s16 inst, u16 idx) 27u32 am33xx_prm_read_reg(s16 inst, u16 idx)
29{ 28{
30 return __raw_readl(prm_base + inst + idx); 29 return readl_relaxed(prm_base + inst + idx);
31} 30}
32 31
33/* Write into a register in a PRM instance */ 32/* Write into a register in a PRM instance */
34void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) 33void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
35{ 34{
36 __raw_writel(val, prm_base + inst + idx); 35 writel_relaxed(val, prm_base + inst + idx);
37} 36}
38 37
39/* Read-modify-write a register in PRM. Caller must lock */ 38/* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 7721990d2006..4bd7a2dca8af 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -43,6 +43,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
43 .ocp_barrier = &omap3xxx_prm_ocp_barrier, 43 .ocp_barrier = &omap3xxx_prm_ocp_barrier,
44 .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, 44 .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
45 .restore_irqen = &omap3xxx_prm_restore_irqen, 45 .restore_irqen = &omap3xxx_prm_restore_irqen,
46 .reconfigure_io_chain = &omap3xxx_prm_reconfigure_io_chain,
46}; 47};
47 48
48/* 49/*
@@ -246,7 +247,7 @@ void omap3xxx_prm_reconfigure_io_chain(void)
246 */ 247 */
247static void __init omap3xxx_prm_enable_io_wakeup(void) 248static void __init omap3xxx_prm_enable_io_wakeup(void)
248{ 249{
249 if (omap3_has_io_wakeup()) 250 if (prm_features & PRM_HAS_IO_WAKEUP)
250 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, 251 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
251 PM_WKEN); 252 PM_WKEN);
252} 253}
@@ -400,23 +401,26 @@ struct pwrdm_ops omap3_pwrdm_operations = {
400 * 401 *
401 */ 402 */
402 403
404static int omap3xxx_prm_late_init(void);
405
403static struct prm_ll_data omap3xxx_prm_ll_data = { 406static struct prm_ll_data omap3xxx_prm_ll_data = {
404 .read_reset_sources = &omap3xxx_prm_read_reset_sources, 407 .read_reset_sources = &omap3xxx_prm_read_reset_sources,
408 .late_init = &omap3xxx_prm_late_init,
405}; 409};
406 410
407int __init omap3xxx_prm_init(void) 411int __init omap3xxx_prm_init(void)
408{ 412{
409 if (!cpu_is_omap34xx()) 413 if (omap3_has_io_wakeup())
410 return 0; 414 prm_features |= PRM_HAS_IO_WAKEUP;
411 415
412 return prm_register(&omap3xxx_prm_ll_data); 416 return prm_register(&omap3xxx_prm_ll_data);
413} 417}
414 418
415static int __init omap3xxx_prm_late_init(void) 419static int omap3xxx_prm_late_init(void)
416{ 420{
417 int ret; 421 int ret;
418 422
419 if (!cpu_is_omap34xx()) 423 if (!(prm_features & PRM_HAS_IO_WAKEUP))
420 return 0; 424 return 0;
421 425
422 omap3xxx_prm_enable_io_wakeup(); 426 omap3xxx_prm_enable_io_wakeup();
@@ -427,15 +431,9 @@ static int __init omap3xxx_prm_late_init(void)
427 431
428 return ret; 432 return ret;
429} 433}
430omap_subsys_initcall(omap3xxx_prm_late_init);
431 434
432static void __exit omap3xxx_prm_exit(void) 435static void __exit omap3xxx_prm_exit(void)
433{ 436{
434 if (!cpu_is_omap34xx()) 437 prm_unregister(&omap3xxx_prm_ll_data);
435 return;
436
437 /* Should never happen */
438 WARN(prm_unregister(&omap3xxx_prm_ll_data),
439 "%s: prm_ll_data function pointer mismatch\n", __func__);
440} 438}
441__exitcall(omap3xxx_prm_exit); 439__exitcall(omap3xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index f8eb83323b1a..1dacfc5b1959 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -26,7 +26,7 @@
26 26
27/* 27/*
28 * OMAP3-specific global PRM registers 28 * OMAP3-specific global PRM registers
29 * Use __raw_{read,write}l() with these registers. 29 * Use {read,write}l_relaxed() with these registers.
30 * 30 *
31 * With a few exceptions, these are the register names beginning with 31 * With a few exceptions, these are the register names beginning with
32 * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE 32 * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 03a603476cfc..a7f6ea27180a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -47,6 +47,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
47 .ocp_barrier = &omap44xx_prm_ocp_barrier, 47 .ocp_barrier = &omap44xx_prm_ocp_barrier,
48 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, 48 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
49 .restore_irqen = &omap44xx_prm_restore_irqen, 49 .restore_irqen = &omap44xx_prm_restore_irqen,
50 .reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain,
50}; 51};
51 52
52/* 53/*
@@ -81,13 +82,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
81/* Read a register in a CM/PRM instance in the PRM module */ 82/* Read a register in a CM/PRM instance in the PRM module */
82u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) 83u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
83{ 84{
84 return __raw_readl(prm_base + inst + reg); 85 return readl_relaxed(prm_base + inst + reg);
85} 86}
86 87
87/* Write into a register in a CM/PRM instance in the PRM module */ 88/* Write into a register in a CM/PRM instance in the PRM module */
88void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) 89void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
89{ 90{
90 __raw_writel(val, prm_base + inst + reg); 91 writel_relaxed(val, prm_base + inst + reg);
91} 92}
92 93
93/* Read-modify-write a register in a PRM module. Caller must lock */ 94/* Read-modify-write a register in a PRM module. Caller must lock */
@@ -649,6 +650,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
649 .pwrdm_has_voltdm = omap4_check_vcvp, 650 .pwrdm_has_voltdm = omap4_check_vcvp,
650}; 651};
651 652
653static int omap44xx_prm_late_init(void);
654
652/* 655/*
653 * XXX document 656 * XXX document
654 */ 657 */
@@ -656,34 +659,29 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
656 .read_reset_sources = &omap44xx_prm_read_reset_sources, 659 .read_reset_sources = &omap44xx_prm_read_reset_sources,
657 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old, 660 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
658 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old, 661 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
662 .late_init = &omap44xx_prm_late_init,
659}; 663};
660 664
661int __init omap44xx_prm_init(void) 665int __init omap44xx_prm_init(void)
662{ 666{
663 if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx()) 667 if (cpu_is_omap44xx())
664 return 0; 668 prm_features |= PRM_HAS_IO_WAKEUP;
665 669
666 return prm_register(&omap44xx_prm_ll_data); 670 return prm_register(&omap44xx_prm_ll_data);
667} 671}
668 672
669static int __init omap44xx_prm_late_init(void) 673static int omap44xx_prm_late_init(void)
670{ 674{
671 if (!cpu_is_omap44xx()) 675 if (!(prm_features & PRM_HAS_IO_WAKEUP))
672 return 0; 676 return 0;
673 677
674 omap44xx_prm_enable_io_wakeup(); 678 omap44xx_prm_enable_io_wakeup();
675 679
676 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); 680 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
677} 681}
678omap_subsys_initcall(omap44xx_prm_late_init);
679 682
680static void __exit omap44xx_prm_exit(void) 683static void __exit omap44xx_prm_exit(void)
681{ 684{
682 if (!cpu_is_omap44xx()) 685 prm_unregister(&omap44xx_prm_ll_data);
683 return;
684
685 /* Should never happen */
686 WARN(prm_unregister(&omap44xx_prm_ll_data),
687 "%s: prm_ll_data function pointer mismatch\n", __func__);
688} 686}
689__exitcall(omap44xx_prm_exit); 687__exitcall(omap44xx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index b4c4ab9c8044..25e8b8232115 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -62,6 +62,8 @@ static struct omap_prcm_irq_setup *prcm_irq_setup;
62/* prm_base: base virtual address of the PRM IP block */ 62/* prm_base: base virtual address of the PRM IP block */
63void __iomem *prm_base; 63void __iomem *prm_base;
64 64
65u16 prm_features;
66
65/* 67/*
66 * prm_ll_data: function pointers to SoC-specific implementations of 68 * prm_ll_data: function pointers to SoC-specific implementations of
67 * common PRM functions 69 * common PRM functions
@@ -330,12 +332,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
330 332
331 if (of_have_populated_dt()) { 333 if (of_have_populated_dt()) {
332 int irq = omap_prcm_event_to_irq("io"); 334 int irq = omap_prcm_event_to_irq("io");
333 if (cpu_is_omap34xx()) 335 omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
334 omap_pcs_legacy_init(irq,
335 omap3xxx_prm_reconfigure_io_chain);
336 else
337 omap_pcs_legacy_init(irq,
338 omap44xx_prm_reconfigure_io_chain);
339 } 336 }
340 337
341 return 0; 338 return 0;
@@ -530,3 +527,11 @@ int __init of_prcm_init(void)
530 527
531 return 0; 528 return 0;
532} 529}
530
531static int __init prm_late_init(void)
532{
533 if (prm_ll_data->late_init)
534 return prm_ll_data->late_init();
535 return 0;
536}
537subsys_initcall(prm_late_init);
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 05fcf6de44ee..69f0dd08629c 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -49,7 +49,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
49 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 49 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
50 part == OMAP4430_INVALID_PRCM_PARTITION || 50 part == OMAP4430_INVALID_PRCM_PARTITION ||
51 !_prm_bases[part]); 51 !_prm_bases[part]);
52 return __raw_readl(_prm_bases[part] + inst + idx); 52 return readl_relaxed(_prm_bases[part] + inst + idx);
53} 53}
54 54
55/* Write into a register in a PRM instance */ 55/* Write into a register in a PRM instance */
@@ -58,7 +58,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
58 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 58 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
59 part == OMAP4430_INVALID_PRCM_PARTITION || 59 part == OMAP4430_INVALID_PRCM_PARTITION ||
60 !_prm_bases[part]); 60 !_prm_bases[part]);
61 __raw_writel(val, _prm_bases[part] + inst + idx); 61 writel_relaxed(val, _prm_bases[part] + inst + idx);
62} 62}
63 63
64/* Read-modify-write a register in PRM. Caller must lock */ 64/* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 446aa13511fd..645a2a46b213 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -31,24 +31,24 @@ extern void __iomem *omap2_sms_base;
31 31
32static inline void sdrc_write_reg(u32 val, u16 reg) 32static inline void sdrc_write_reg(u32 val, u16 reg)
33{ 33{
34 __raw_writel(val, OMAP_SDRC_REGADDR(reg)); 34 writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
35} 35}
36 36
37static inline u32 sdrc_read_reg(u16 reg) 37static inline u32 sdrc_read_reg(u16 reg)
38{ 38{
39 return __raw_readl(OMAP_SDRC_REGADDR(reg)); 39 return readl_relaxed(OMAP_SDRC_REGADDR(reg));
40} 40}
41 41
42/* SMS global register get/set */ 42/* SMS global register get/set */
43 43
44static inline void sms_write_reg(u32 val, u16 reg) 44static inline void sms_write_reg(u32 val, u16 reg)
45{ 45{
46 __raw_writel(val, OMAP_SMS_REGADDR(reg)); 46 writel_relaxed(val, OMAP_SMS_REGADDR(reg));
47} 47}
48 48
49static inline u32 sms_read_reg(u16 reg) 49static inline u32 sms_read_reg(u16 reg)
50{ 50{
51 return __raw_readl(OMAP_SMS_REGADDR(reg)); 51 return readl_relaxed(OMAP_SMS_REGADDR(reg));
52} 52}
53 53
54extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms); 54extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 907291714643..ae3f1553158d 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -103,9 +103,9 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
103 * prm2xxx.c function 103 * prm2xxx.c function
104 */ 104 */
105 if (cpu_is_omap2420()) 105 if (cpu_is_omap2420())
106 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); 106 writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
107 else 107 else
108 __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP); 108 writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
109 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type); 109 omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
110 curr_perf_level = level; 110 curr_perf_level = level;
111 local_irq_restore(flags); 111 local_irq_restore(flags);
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 30abcc8b20e0..de2a34c423a7 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -459,10 +459,15 @@ IS_OMAP_TYPE(3430, 0x3430)
459#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) 459#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
460#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) 460#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
461 461
462#define DRA7XX_CLASS 0x07000000
463#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
464#define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
465
462void omap2xxx_check_revision(void); 466void omap2xxx_check_revision(void);
463void omap3xxx_check_revision(void); 467void omap3xxx_check_revision(void);
464void omap4xxx_check_revision(void); 468void omap4xxx_check_revision(void);
465void omap5xxx_check_revision(void); 469void omap5xxx_check_revision(void);
470void dra7xxx_check_revision(void);
466void omap3xxx_check_features(void); 471void omap3xxx_check_features(void);
467void ti81xx_check_features(void); 472void ti81xx_check_features(void);
468void am33xx_check_features(void); 473void am33xx_check_features(void);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d7bc33f15344..1b91ef0c182a 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -57,7 +57,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
57 57
58 /* 58 /*
59 * In OMAP4 the efuse registers are 24 bit aligned. 59 * In OMAP4 the efuse registers are 24 bit aligned.
60 * A __raw_readl will fail for non-32 bit aligned address 60 * A readl_relaxed will fail for non-32 bit aligned address
61 * and hence the 8-bit read and shift. 61 * and hence the 8-bit read and shift.
62 */ 62 */
63 if (cpu_is_omap44xx()) { 63 if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 4bd096836235..ddf1818af228 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -70,16 +70,16 @@ static int is_sram_locked(void)
70 if (OMAP2_DEVICE_TYPE_GP == omap_type()) { 70 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
71 /* RAMFW: R/W access to all initiators for all qualifier sets */ 71 /* RAMFW: R/W access to all initiators for all qualifier sets */
72 if (cpu_is_omap242x()) { 72 if (cpu_is_omap242x()) {
73 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ 73 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
74 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */ 74 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
75 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */ 75 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
76 } 76 }
77 if (cpu_is_omap34xx()) { 77 if (cpu_is_omap34xx()) {
78 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */ 78 writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
79 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */ 79 writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
80 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */ 80 writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
81 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2); 81 writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
82 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0); 82 writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
83 } 83 }
84 return 0; 84 return 0;
85 } else 85 } else
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index b62de9f9d05c..43d03fbf4c0b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -361,7 +361,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
361 361
362/* Clocksource code */ 362/* Clocksource code */
363static struct omap_dm_timer clksrc; 363static struct omap_dm_timer clksrc;
364static bool use_gptimer_clksrc; 364static bool use_gptimer_clksrc __initdata;
365 365
366/* 366/*
367 * clocksource 367 * clocksource
@@ -546,15 +546,15 @@ static void __init realtime_counter_init(void)
546 } 546 }
547 547
548 /* Program numerator and denumerator registers */ 548 /* Program numerator and denumerator registers */
549 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & 549 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
550 NUMERATOR_DENUMERATOR_MASK; 550 NUMERATOR_DENUMERATOR_MASK;
551 reg |= num; 551 reg |= num;
552 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); 552 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
553 553
554 reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & 554 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
555 NUMERATOR_DENUMERATOR_MASK; 555 NUMERATOR_DENUMERATOR_MASK;
556 reg |= den; 556 reg |= den;
557 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 557 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
558 558
559 arch_timer_freq = (rate / den) * num; 559 arch_timer_freq = (rate / den) * num;
560 set_cntfreq(); 560 set_cntfreq();
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 10855eb4ccc1..745367c0c2bb 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,7 +28,7 @@
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/usb/phy.h> 30#include <linux/usb/phy.h>
31#include <linux/usb/usb_phy_gen_xceiv.h> 31#include <linux/usb/usb_phy_generic.h>
32 32
33#include "soc.h" 33#include "soc.h"
34#include "omap_device.h" 34#include "omap_device.h"
@@ -349,7 +349,7 @@ static struct fixed_voltage_config hsusb_reg_config = {
349 /* .init_data filled later */ 349 /* .init_data filled later */
350}; 350};
351 351
352static const char *nop_name = "usb_phy_gen_xceiv"; /* NOP PHY driver */ 352static const char *nop_name = "usb_phy_generic"; /* NOP PHY driver */
353static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */ 353static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
354 354
355/** 355/**
@@ -435,7 +435,7 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
435 struct platform_device *pdev; 435 struct platform_device *pdev;
436 char *phy_id; 436 char *phy_id;
437 struct platform_device_info pdevinfo; 437 struct platform_device_info pdevinfo;
438 struct usb_phy_gen_xceiv_platform_data nop_pdata; 438 struct usb_phy_generic_platform_data nop_pdata;
439 439
440 for (i = 0; i < num_phys; i++) { 440 for (i = 0; i < num_phys; i++) {
441 441
@@ -469,8 +469,8 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
469 pdevinfo.id = phy->port; 469 pdevinfo.id = phy->port;
470 pdevinfo.data = &nop_pdata; 470 pdevinfo.data = &nop_pdata;
471 pdevinfo.size_data = 471 pdevinfo.size_data =
472 sizeof(struct usb_phy_gen_xceiv_platform_data); 472 sizeof(struct usb_phy_generic_platform_data);
473 scnprintf(phy_id, MAX_STR, "usb_phy_gen_xceiv.%d", 473 scnprintf(phy_id, MAX_STR, "usb_phy_generic.%d",
474 phy->port); 474 phy->port);
475 pdev = platform_device_register_full(&pdevinfo); 475 pdev = platform_device_register_full(&pdevinfo);
476 if (IS_ERR(pdev)) { 476 if (IS_ERR(pdev)) {
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 49ac7977e03e..a4628a9e760c 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -220,10 +220,126 @@ static inline u32 omap_usec_to_32k(u32 usec)
220 return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL); 220 return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
221} 221}
222 222
223/* Set oscillator setup time for omap3 */ 223struct omap3_vc_timings {
224static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm) 224 u32 voltsetup1;
225 u32 voltsetup2;
226};
227
228struct omap3_vc {
229 struct voltagedomain *vd;
230 u32 voltctrl;
231 u32 voltsetup1;
232 u32 voltsetup2;
233 struct omap3_vc_timings timings[2];
234};
235static struct omap3_vc vc;
236
237void omap3_vc_set_pmic_signaling(int core_next_state)
238{
239 struct voltagedomain *vd = vc.vd;
240 struct omap3_vc_timings *c = vc.timings;
241 u32 voltctrl, voltsetup1, voltsetup2;
242
243 voltctrl = vc.voltctrl;
244 voltsetup1 = vc.voltsetup1;
245 voltsetup2 = vc.voltsetup2;
246
247 switch (core_next_state) {
248 case PWRDM_POWER_OFF:
249 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET |
250 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
251 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF;
252 if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF)
253 voltsetup2 = c->voltsetup2;
254 else
255 voltsetup1 = c->voltsetup1;
256 break;
257 case PWRDM_POWER_RET:
258 default:
259 c++;
260 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF |
261 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
262 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET;
263 voltsetup1 = c->voltsetup1;
264 break;
265 }
266
267 if (voltctrl != vc.voltctrl) {
268 vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET);
269 vc.voltctrl = voltctrl;
270 }
271 if (voltsetup1 != vc.voltsetup1) {
272 vd->write(c->voltsetup1,
273 OMAP3_PRM_VOLTSETUP1_OFFSET);
274 vc.voltsetup1 = voltsetup1;
275 }
276 if (voltsetup2 != vc.voltsetup2) {
277 vd->write(c->voltsetup2,
278 OMAP3_PRM_VOLTSETUP2_OFFSET);
279 vc.voltsetup2 = voltsetup2;
280 }
281}
282
283#define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \
284 OMAP3430_PRM_POLCTRL_CLKREQ_POL)
285#define PRM_POLCTRL_TWL_VAL OMAP3430_PRM_POLCTRL_CLKREQ_POL
286
287/*
288 * Configure signal polarity for sys_clkreq and sys_off_mode pins
289 * as the default values are wrong and can cause the system to hang
290 * if any twl4030 scripts are loaded.
291 */
292static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
293{
294 u32 val;
295
296 if (vc.vd)
297 return;
298
299 vc.vd = voltdm;
300
301 val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
302 if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
303 (val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) {
304 val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
305 val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
306 pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
307 val);
308 voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET);
309 }
310
311 /*
312 * By default let's use I2C4 signaling for retention idle
313 * and sys_off_mode pin signaling for off idle. This way we
314 * have sys_clk_req pin go down for retention and both
315 * sys_clk_req and sys_off_mode pins will go down for off
316 * idle. And we can also scale voltages to zero for off-idle.
317 * Note that no actual voltage scaling during off-idle will
318 * happen unless the board specific twl4030 PMIC scripts are
319 * loaded.
320 */
321 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
322 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
323 val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF;
324 pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
325 val);
326 voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET);
327 }
328 vc.voltctrl = val;
329
330 omap3_vc_set_pmic_signaling(PWRDM_POWER_ON);
331}
332
333static void omap3_init_voltsetup1(struct voltagedomain *voltdm,
334 struct omap3_vc_timings *c, u32 idle)
225{ 335{
226 voltdm->write(omap_usec_to_32k(usec), OMAP3_PRM_CLKSETUP_OFFSET); 336 unsigned long val;
337
338 val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate;
339 val *= voltdm->sys_clk.rate / 8 / 1000000 + 1;
340 val <<= __ffs(voltdm->vfsm->voltsetup_mask);
341 c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask;
342 c->voltsetup1 |= val;
227} 343}
228 344
229/** 345/**
@@ -236,37 +352,21 @@ static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm)
236 * or retention. Off mode has additionally an option to use sys_off_mode 352 * or retention. Off mode has additionally an option to use sys_off_mode
237 * pad, which uses a global signal to program the whole power IC to 353 * pad, which uses a global signal to program the whole power IC to
238 * off-mode. 354 * off-mode.
355 *
356 * Note that pmic is not controlling the voltage scaling during
357 * retention signaled over I2C4, so we can keep voltsetup2 as 0.
358 * And the oscillator is not shut off over I2C4, so no need to
359 * set clksetup.
239 */ 360 */
240static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode) 361static void omap3_set_i2c_timings(struct voltagedomain *voltdm)
241{ 362{
242 unsigned long voltsetup1; 363 struct omap3_vc_timings *c = vc.timings;
243 u32 tgt_volt;
244
245 /*
246 * Oscillator is shut down only if we are using sys_off_mode pad,
247 * thus we set a minimal setup time here
248 */
249 omap3_set_clksetup(1, voltdm);
250 364
251 if (off_mode) 365 /* Configure PRWDM_POWER_OFF over I2C4 */
252 tgt_volt = voltdm->vc_param->off; 366 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off);
253 else 367 c++;
254 tgt_volt = voltdm->vc_param->ret; 368 /* Configure PRWDM_POWER_RET over I2C4 */
255 369 omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret);
256 voltsetup1 = (voltdm->vc_param->on - tgt_volt) /
257 voltdm->pmic->slew_rate;
258
259 voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1;
260
261 voltdm->rmw(voltdm->vfsm->voltsetup_mask,
262 voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask),
263 voltdm->vfsm->voltsetup_reg);
264
265 /*
266 * pmic is not controlling the voltage scaling during retention,
267 * thus set voltsetup2 to 0
268 */
269 voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET);
270} 370}
271 371
272/** 372/**
@@ -275,69 +375,49 @@ static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode)
275 * 375 *
276 * Calculates and sets up off-mode timings for a channel. Off-mode 376 * Calculates and sets up off-mode timings for a channel. Off-mode
277 * can use either I2C based voltage scaling, or alternatively 377 * can use either I2C based voltage scaling, or alternatively
278 * sys_off_mode pad can be used to send a global command to power IC. 378 * sys_off_mode pad can be used to send a global command to power IC.n,
279 * This function first checks which mode is being used, and calls
280 * omap3_set_i2c_timings() if the system is using I2C control mode.
281 * sys_off_mode has the additional benefit that voltages can be 379 * sys_off_mode has the additional benefit that voltages can be
282 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only 380 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
283 * scale to 600mV. 381 * scale to 600mV.
382 *
383 * Note that omap is not controlling the voltage scaling during
384 * off idle signaled by sys_off_mode, so we can keep voltsetup1
385 * as 0.
284 */ 386 */
285static void omap3_set_off_timings(struct voltagedomain *voltdm) 387static void omap3_set_off_timings(struct voltagedomain *voltdm)
286{ 388{
287 unsigned long clksetup; 389 struct omap3_vc_timings *c = vc.timings;
288 unsigned long voltsetup2; 390 u32 tstart, tshut, clksetup, voltoffset;
289 unsigned long voltsetup2_old;
290 u32 val;
291 u32 tstart, tshut;
292 391
293 /* check if sys_off_mode is used to control off-mode voltages */ 392 if (c->voltsetup2)
294 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
295 if (!(val & OMAP3430_SEL_OFF_MASK)) {
296 /* No, omap is controlling them over I2C */
297 omap3_set_i2c_timings(voltdm, true);
298 return; 393 return;
299 }
300 394
301 omap_pm_get_oscillator(&tstart, &tshut); 395 omap_pm_get_oscillator(&tstart, &tshut);
302 omap3_set_clksetup(tstart, voltdm); 396 if (tstart == ULONG_MAX) {
303 397 pr_debug("PM: oscillator start-up time not initialized, using 10ms\n");
304 clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET); 398 clksetup = omap_usec_to_32k(10000);
305 399 } else {
306 /* voltsetup 2 in us */ 400 clksetup = omap_usec_to_32k(tstart);
307 voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate; 401 }
308
309 /* convert to 32k clk cycles */
310 voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000);
311
312 voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET);
313
314 /*
315 * Update voltsetup2 if higher than current value (needed because
316 * we have multiple channels with different ramp times), also
317 * update voltoffset always to value recommended by TRM
318 */
319 if (voltsetup2 > voltsetup2_old) {
320 voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET);
321 voltdm->write(clksetup - voltsetup2,
322 OMAP3_PRM_VOLTOFFSET_OFFSET);
323 } else
324 voltdm->write(clksetup - voltsetup2_old,
325 OMAP3_PRM_VOLTOFFSET_OFFSET);
326 402
327 /* 403 /*
328 * omap is not controlling voltage scaling during off-mode, 404 * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to
329 * thus set voltsetup1 to 0 405 * switch from HFCLKIN to internal oscillator. That means timings
406 * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And
407 * that means we can calculate the value based on the oscillator
408 * start-up time since voltoffset2 = clksetup - voltoffset.
330 */ 409 */
331 voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0, 410 voltoffset = omap_usec_to_32k(488);
332 voltdm->vfsm->voltsetup_reg); 411 c->voltsetup2 = clksetup - voltoffset;
333 412 voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET);
334 /* voltoffset must be clksetup minus voltsetup2 according to TRM */ 413 voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET);
335 voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET);
336} 414}
337 415
338static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) 416static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
339{ 417{
418 omap3_vc_init_pmic_signaling(voltdm);
340 omap3_set_off_timings(voltdm); 419 omap3_set_off_timings(voltdm);
420 omap3_set_i2c_timings(voltdm);
341} 421}
342 422
343/** 423/**
@@ -462,7 +542,7 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
462 val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT, 542 val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
463 OMAP4_DOWNTIME_MASK); 543 OMAP4_DOWNTIME_MASK);
464 544
465 __raw_writel(val, OMAP4_SCRM_CLKSETUPTIME); 545 writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
466} 546}
467 547
468/* OMAP4 specific voltage init functions */ 548/* OMAP4 specific voltage init functions */
@@ -584,7 +664,7 @@ static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
584 val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29; 664 val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
585 665
586 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */ 666 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
587 __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + 667 writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
588 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2)); 668 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
589 669
590 /* HSSCLH can always be zero */ 670 /* HSSCLH can always be zero */
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index 91c8d75bf2ea..cdbdd78e755e 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -117,6 +117,9 @@ extern struct omap_vc_param omap4_mpu_vc_data;
117extern struct omap_vc_param omap4_iva_vc_data; 117extern struct omap_vc_param omap4_iva_vc_data;
118extern struct omap_vc_param omap4_core_vc_data; 118extern struct omap_vc_param omap4_core_vc_data;
119 119
120void omap3_vc_set_pmic_signaling(int core_next_state);
121
122
120void omap_vc_init_channel(struct voltagedomain *voltdm); 123void omap_vc_init_channel(struct voltagedomain *voltdm);
121int omap_vc_pre_scale(struct voltagedomain *voltdm, 124int omap_vc_pre_scale(struct voltagedomain *voltdm,
122 unsigned long target_volt, 125 unsigned long target_volt,
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index d15c7bbab8e2..97d6607d447a 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -49,12 +49,12 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
49 } 49 }
50 50
51 /* sequence required to disable watchdog */ 51 /* sequence required to disable watchdog */
52 __raw_writel(0xAAAA, base + OMAP_WDT_SPR); 52 writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
53 while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) 53 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
54 cpu_relax(); 54 cpu_relax();
55 55
56 __raw_writel(0x5555, base + OMAP_WDT_SPR); 56 writel_relaxed(0x5555, base + OMAP_WDT_SPR);
57 while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) 57 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
58 cpu_relax(); 58 cpu_relax();
59 59
60 return 0; 60 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 05:54:15 -0500