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-rw-r--r--arch/arm/mach-omap2/Kconfig15
-rw-r--r--arch/arm/mach-omap2/Makefile11
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c11
-rw-r--r--arch/arm/mach-omap2/board-apollon.c18
-rw-r--r--arch/arm/mach-omap2/board-flash.c5
-rw-r--r--arch/arm/mach-omap2/board-h4.c13
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c6
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c28
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c6
-rw-r--r--arch/arm/mach-omap2/clock.c18
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c43
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c49
-rw-r--r--arch/arm/mach-omap2/clock33xx_data.c2
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c40
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c44
-rw-r--r--arch/arm/mach-omap2/clockdomain.h2
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c10
-rw-r--r--arch/arm/mach-omap2/clockdomains2420_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains2430_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomains_common_data.c24
-rw-r--r--arch/arm/mach-omap2/cm.h11
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c18
-rw-r--r--arch/arm/mach-omap2/cminst44xx.h25
-rw-r--r--arch/arm/mach-omap2/common.c10
-rw-r--r--arch/arm/mach-omap2/common.h5
-rw-r--r--arch/arm/mach-omap2/control.c43
-rw-r--r--arch/arm/mach-omap2/control.h3
-rw-r--r--arch/arm/mach-omap2/display.c4
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c26
-rw-r--r--arch/arm/mach-omap2/dsp.c7
-rw-r--r--arch/arm/mach-omap2/id.c15
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h1
-rw-r--r--arch/arm/mach-omap2/irq.c1
-rw-r--r--arch/arm/mach-omap2/mux.c4
-rw-r--r--arch/arm/mach-omap2/mux.h11
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c490
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c16
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c8
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c33
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c18
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.c10
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c3
-rw-r--r--arch/arm/mach-omap2/omap_phy_internal.c6
-rw-r--r--arch/arm/mach-omap2/pm34xx.c1
-rw-r--r--arch/arm/mach-omap2/powerdomain.c6
-rw-r--r--arch/arm/mach-omap2/prcm.c23
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c14
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h65
-rw-r--r--arch/arm/mach-omap2/prm_common.c62
-rw-r--r--arch/arm/mach-omap2/serial.c67
-rw-r--r--arch/arm/mach-omap2/timer.c82
-rw-r--r--arch/arm/mach-omap2/usb-fs.c359
-rw-r--r--arch/arm/mach-omap2/usb-musb.c6
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c2
57 files changed, 805 insertions, 1013 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4cf5142f22cc..6c934778357b 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -21,12 +21,16 @@ config ARCH_OMAP2PLUS_TYPICAL
21 help 21 help
22 Compile a kernel suitable for booting most boards 22 Compile a kernel suitable for booting most boards
23 23
24config SOC_HAS_OMAP2_SDRC
25 bool "OMAP2 SDRAM Controller support"
26
24config ARCH_OMAP2 27config ARCH_OMAP2
25 bool "TI OMAP2" 28 bool "TI OMAP2"
26 depends on ARCH_OMAP2PLUS 29 depends on ARCH_OMAP2PLUS
27 default y 30 default y
28 select CPU_V6 31 select CPU_V6
29 select MULTI_IRQ_HANDLER 32 select MULTI_IRQ_HANDLER
33 select SOC_HAS_OMAP2_SDRC
30 34
31config ARCH_OMAP3 35config ARCH_OMAP3
32 bool "TI OMAP3" 36 bool "TI OMAP3"
@@ -38,6 +42,7 @@ config ARCH_OMAP3
38 select PM_OPP if PM 42 select PM_OPP if PM
39 select ARM_CPU_SUSPEND if PM 43 select ARM_CPU_SUSPEND if PM
40 select MULTI_IRQ_HANDLER 44 select MULTI_IRQ_HANDLER
45 select SOC_HAS_OMAP2_SDRC
41 46
42config ARCH_OMAP4 47config ARCH_OMAP4
43 bool "TI OMAP4" 48 bool "TI OMAP4"
@@ -64,19 +69,19 @@ config SOC_OMAP2420
64 depends on ARCH_OMAP2 69 depends on ARCH_OMAP2
65 default y 70 default y
66 select OMAP_DM_TIMER 71 select OMAP_DM_TIMER
67 select ARCH_OMAP_OTG 72 select SOC_HAS_OMAP2_SDRC
68 73
69config SOC_OMAP2430 74config SOC_OMAP2430
70 bool "OMAP2430 support" 75 bool "OMAP2430 support"
71 depends on ARCH_OMAP2 76 depends on ARCH_OMAP2
72 default y 77 default y
73 select ARCH_OMAP_OTG 78 select SOC_HAS_OMAP2_SDRC
74 79
75config SOC_OMAP3430 80config SOC_OMAP3430
76 bool "OMAP3430 support" 81 bool "OMAP3430 support"
77 depends on ARCH_OMAP3 82 depends on ARCH_OMAP3
78 default y 83 default y
79 select ARCH_OMAP_OTG 84 select SOC_HAS_OMAP2_SDRC
80 85
81config SOC_TI81XX 86config SOC_TI81XX
82 bool "TI81XX support" 87 bool "TI81XX support"
@@ -85,8 +90,10 @@ config SOC_TI81XX
85 90
86config SOC_AM33XX 91config SOC_AM33XX
87 bool "AM33XX support" 92 bool "AM33XX support"
88 depends on ARCH_OMAP3
89 default y 93 default y
94 select CPU_V7
95 select ARM_CPU_SUSPEND if PM
96 select MULTI_IRQ_HANDLER
90 97
91config OMAP_PACKAGE_ZAF 98config OMAP_PACKAGE_ZAF
92 bool 99 bool
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b167152ca69f..3e7d54af4c91 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o 7 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
8 8
9omap-2-3-common = irq.o sdrc.o 9omap-2-3-common = irq.o
10hwmod-common = omap_hwmod.o \ 10hwmod-common = omap_hwmod.o \
11 omap_hwmod_common_data.o 11 omap_hwmod_common_data.o
12clock-common = clock.o clock_common_data.o \ 12clock-common = clock.o clock_common_data.o \
@@ -16,12 +16,14 @@ secure-common = omap-smc.o omap-secure.o
16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) 16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
19obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
19 20
20ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 21ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
21obj-y += mcbsp.o 22obj-y += mcbsp.o
22endif 23endif
23 24
24obj-$(CONFIG_TWL4030_CORE) += omap_twl.o 25obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
26obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
25 27
26# SMP support ONLY available for OMAP4 28# SMP support ONLY available for OMAP4
27 29
@@ -100,6 +102,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
100obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o 102obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
101obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) 103obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
102obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o 104obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
105obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
103obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o 106obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
104 107
105# OMAP powerdomain framework 108# OMAP powerdomain framework
@@ -115,12 +118,12 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
115obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) 118obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
116obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o 119obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
117obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o 120obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
121obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
118obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o 122obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
119obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o 123obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
120 124
121# PRCM clockdomain control 125# PRCM clockdomain control
122clockdomain-common += clockdomain.o 126clockdomain-common += clockdomain.o
123clockdomain-common += clockdomains_common_data.o
124obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) 127obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
125obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o 128obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o
126obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o 129obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
@@ -133,6 +136,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
133obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) 136obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
134obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o 137obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
135obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o 138obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
139obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
136obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o 140obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
137obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o 141obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
138 142
@@ -252,9 +256,6 @@ obj-y += $(omap-flash-y) $(omap-flash-m)
252omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o 256omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
253obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) 257obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
254 258
255
256usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o
257obj-y += $(usbfs-m) $(usbfs-y)
258obj-y += usb-musb.o 259obj-y += usb-musb.o
259obj-y += omap_phy_internal.o 260obj-y += omap_phy_internal.o
260 261
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 99ca6bad5c30..6523aeabf9f2 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -254,16 +254,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
254 {} /* Terminator */ 254 {} /* Terminator */
255}; 255};
256 256
257static struct omap_usb_config sdp2430_usb_config __initdata = {
258 .otg = 1,
259#ifdef CONFIG_USB_GADGET_OMAP
260 .hmc_mode = 0x0,
261#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
262 .hmc_mode = 0x1,
263#endif
264 .pins[0] = 3,
265};
266
267#ifdef CONFIG_OMAP_MUX 257#ifdef CONFIG_OMAP_MUX
268static struct omap_board_mux board_mux[] __initdata = { 258static struct omap_board_mux board_mux[] __initdata = {
269 { .reg_offset = OMAP_MUX_TERMINATOR }, 259 { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -280,7 +270,6 @@ static void __init omap_2430sdp_init(void)
280 omap_serial_init(); 270 omap_serial_init();
281 omap_sdrc_init(NULL, NULL); 271 omap_sdrc_init(NULL, NULL);
282 omap_hsmmc_init(mmc); 272 omap_hsmmc_init(mmc);
283 omap2_usbfs_init(&sdp2430_usb_config);
284 273
285 omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); 274 omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
286 usb_musb_init(NULL); 275 usb_musb_init(NULL);
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 502c31e123be..519bcd3079e8 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -35,7 +35,6 @@
35#include <asm/mach/flash.h> 35#include <asm/mach/flash.h>
36 36
37#include <plat/led.h> 37#include <plat/led.h>
38#include <plat/usb.h>
39#include <plat/board.h> 38#include <plat/board.h>
40#include "common.h" 39#include "common.h"
41#include <plat/gpmc.h> 40#include <plat/gpmc.h>
@@ -253,13 +252,6 @@ out:
253 clk_put(gpmc_fck); 252 clk_put(gpmc_fck);
254} 253}
255 254
256static struct omap_usb_config apollon_usb_config __initdata = {
257 .register_dev = 1,
258 .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */
259
260 .pins[0] = 6,
261};
262
263static struct panel_generic_dpi_data apollon_panel_data = { 255static struct panel_generic_dpi_data apollon_panel_data = {
264 .name = "apollon", 256 .name = "apollon",
265}; 257};
@@ -297,15 +289,6 @@ static void __init apollon_led_init(void)
297 gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds)); 289 gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds));
298} 290}
299 291
300static void __init apollon_usb_init(void)
301{
302 /* USB device */
303 /* DEVICE_SUSPEND */
304 omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
305 gpio_request_one(12, GPIOF_OUT_INIT_LOW, "USB suspend");
306 omap2_usbfs_init(&apollon_usb_config);
307}
308
309#ifdef CONFIG_OMAP_MUX 292#ifdef CONFIG_OMAP_MUX
310static struct omap_board_mux board_mux[] __initdata = { 293static struct omap_board_mux board_mux[] __initdata = {
311 { .reg_offset = OMAP_MUX_TERMINATOR }, 294 { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -321,7 +304,6 @@ static void __init omap_apollon_init(void)
321 apollon_init_smc91x(); 304 apollon_init_smc91x();
322 apollon_led_init(); 305 apollon_led_init();
323 apollon_flash_init(); 306 apollon_flash_init();
324 apollon_usb_init();
325 307
326 /* REVISIT: where's the correct place */ 308 /* REVISIT: where's the correct place */
327 omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); 309 omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 70a81f900bb5..53c39d239d6e 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -97,11 +97,6 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
97 97
98 gpmc_onenand_init(&board_onenand_data); 98 gpmc_onenand_init(&board_onenand_data);
99} 99}
100#else
101void
102__init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
103{
104}
105#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */ 100#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
106 101
107#if defined(CONFIG_MTD_NAND_OMAP2) || \ 102#if defined(CONFIG_MTD_NAND_OMAP2) || \
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 876becf8205a..ace20482e3e1 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -32,7 +32,6 @@
32#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34 34
35#include <plat/usb.h>
36#include <plat/board.h> 35#include <plat/board.h>
37#include "common.h" 36#include "common.h"
38#include <plat/menelaus.h> 37#include <plat/menelaus.h>
@@ -329,17 +328,6 @@ static void __init h4_init_flash(void)
329 h4_flash_resource.end = base + SZ_64M - 1; 328 h4_flash_resource.end = base + SZ_64M - 1;
330} 329}
331 330
332static struct omap_usb_config h4_usb_config __initdata = {
333 /* S1.10 OFF -- usb "download port"
334 * usb0 switched to Mini-B port and isp1105 transceiver;
335 * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging
336 */
337 .register_dev = 1,
338 .pins[0] = 3,
339/* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */
340 .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */
341};
342
343static struct at24_platform_data m24c01 = { 331static struct at24_platform_data m24c01 = {
344 .byte_len = SZ_1K / 8, 332 .byte_len = SZ_1K / 8,
345 .page_size = 16, 333 .page_size = 16,
@@ -381,7 +369,6 @@ static void __init omap_h4_init(void)
381 ARRAY_SIZE(h4_i2c_board_info)); 369 ARRAY_SIZE(h4_i2c_board_info));
382 370
383 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); 371 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
384 omap2_usbfs_init(&h4_usb_config);
385 omap_serial_init(); 372 omap_serial_init();
386 omap_sdrc_init(NULL, NULL); 373 omap_sdrc_init(NULL, NULL);
387 h4_init_flash(); 374 h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 8ca14e88a31a..2c5d0ed75285 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -83,11 +83,9 @@ static struct musb_hdrc_config musb_config = {
83}; 83};
84 84
85static struct musb_hdrc_platform_data tusb_data = { 85static struct musb_hdrc_platform_data tusb_data = {
86#if defined(CONFIG_USB_MUSB_OTG) 86#ifdef CONFIG_USB_GADGET_MUSB_HDRC
87 .mode = MUSB_OTG, 87 .mode = MUSB_OTG,
88#elif defined(CONFIG_USB_MUSB_PERIPHERAL) 88#else
89 .mode = MUSB_PERIPHERAL,
90#else /* defined(CONFIG_USB_MUSB_HOST) */
91 .mode = MUSB_HOST, 89 .mode = MUSB_HOST,
92#endif 90#endif
93 .set_power = tusb_set_power, 91 .set_power = tusb_set_power,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 79c6909eeb78..580fd17208da 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -81,13 +81,13 @@ static u8 omap3_beagle_version;
81static struct { 81static struct {
82 int mmc1_gpio_wp; 82 int mmc1_gpio_wp;
83 int usb_pwr_level; 83 int usb_pwr_level;
84 int reset_gpio; 84 int dvi_pd_gpio;
85 int usr_button_gpio; 85 int usr_button_gpio;
86 int mmc_caps; 86 int mmc_caps;
87} beagle_config = { 87} beagle_config = {
88 .mmc1_gpio_wp = -EINVAL, 88 .mmc1_gpio_wp = -EINVAL,
89 .usb_pwr_level = GPIOF_OUT_INIT_LOW, 89 .usb_pwr_level = GPIOF_OUT_INIT_LOW,
90 .reset_gpio = 129, 90 .dvi_pd_gpio = -EINVAL,
91 .usr_button_gpio = 4, 91 .usr_button_gpio = 4,
92 .mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 92 .mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
93}; 93};
@@ -126,21 +126,21 @@ static void __init omap3_beagle_init_rev(void)
126 printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n"); 126 printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
127 omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX; 127 omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
128 beagle_config.mmc1_gpio_wp = 29; 128 beagle_config.mmc1_gpio_wp = 29;
129 beagle_config.reset_gpio = 170; 129 beagle_config.dvi_pd_gpio = 170;
130 beagle_config.usr_button_gpio = 7; 130 beagle_config.usr_button_gpio = 7;
131 break; 131 break;
132 case 6: 132 case 6:
133 printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n"); 133 printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
134 omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3; 134 omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
135 beagle_config.mmc1_gpio_wp = 23; 135 beagle_config.mmc1_gpio_wp = 23;
136 beagle_config.reset_gpio = 170; 136 beagle_config.dvi_pd_gpio = 170;
137 beagle_config.usr_button_gpio = 7; 137 beagle_config.usr_button_gpio = 7;
138 break; 138 break;
139 case 5: 139 case 5:
140 printk(KERN_INFO "OMAP3 Beagle Rev: C4\n"); 140 printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
141 omap3_beagle_version = OMAP3BEAGLE_BOARD_C4; 141 omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
142 beagle_config.mmc1_gpio_wp = 23; 142 beagle_config.mmc1_gpio_wp = 23;
143 beagle_config.reset_gpio = 170; 143 beagle_config.dvi_pd_gpio = 170;
144 beagle_config.usr_button_gpio = 7; 144 beagle_config.usr_button_gpio = 7;
145 break; 145 break;
146 case 0: 146 case 0:
@@ -274,11 +274,9 @@ static int beagle_twl_gpio_setup(struct device *dev,
274 if (r) 274 if (r)
275 pr_err("%s: unable to configure nDVI_PWR_EN\n", 275 pr_err("%s: unable to configure nDVI_PWR_EN\n",
276 __func__); 276 __func__);
277 r = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH, 277
278 "DVI_LDO_EN"); 278 beagle_config.dvi_pd_gpio = gpio + 2;
279 if (r) 279
280 pr_err("%s: unable to configure DVI_LDO_EN\n",
281 __func__);
282 } else { 280 } else {
283 /* 281 /*
284 * REVISIT: need ehci-omap hooks for external VBUS 282 * REVISIT: need ehci-omap hooks for external VBUS
@@ -287,7 +285,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
287 if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC")) 285 if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
288 pr_err("%s: unable to configure EHCI_nOC\n", __func__); 286 pr_err("%s: unable to configure EHCI_nOC\n", __func__);
289 } 287 }
290 dvi_panel.power_down_gpio = beagle_config.reset_gpio; 288 dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio;
291 289
292 gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level, 290 gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
293 "nEN_USB_PWR"); 291 "nEN_USB_PWR");
@@ -499,7 +497,7 @@ static void __init omap3_beagle_init(void)
499 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 497 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
500 omap3_beagle_init_rev(); 498 omap3_beagle_init_rev();
501 499
502 if (beagle_config.mmc1_gpio_wp != -EINVAL) 500 if (gpio_is_valid(beagle_config.mmc1_gpio_wp))
503 omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT); 501 omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
504 mmc[0].caps = beagle_config.mmc_caps; 502 mmc[0].caps = beagle_config.mmc_caps;
505 omap_hsmmc_init(mmc); 503 omap_hsmmc_init(mmc);
@@ -510,15 +508,13 @@ static void __init omap3_beagle_init(void)
510 508
511 platform_add_devices(omap3_beagle_devices, 509 platform_add_devices(omap3_beagle_devices,
512 ARRAY_SIZE(omap3_beagle_devices)); 510 ARRAY_SIZE(omap3_beagle_devices));
511 if (gpio_is_valid(beagle_config.dvi_pd_gpio))
512 omap_mux_init_gpio(beagle_config.dvi_pd_gpio, OMAP_PIN_OUTPUT);
513 omap_display_init(&beagle_dss_data); 513 omap_display_init(&beagle_dss_data);
514 omap_serial_init(); 514 omap_serial_init();
515 omap_sdrc_init(mt46h32m32lf6_sdrc_params, 515 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
516 mt46h32m32lf6_sdrc_params); 516 mt46h32m32lf6_sdrc_params);
517 517
518 omap_mux_init_gpio(170, OMAP_PIN_INPUT);
519 /* REVISIT leave DVI powered down until it's needed ... */
520 gpio_request_one(170, GPIOF_OUT_INIT_HIGH, "DVI_nPD");
521
522 usb_musb_init(NULL); 518 usb_musb_init(NULL);
523 usbhs_init(&usbhs_bdata); 519 usbhs_init(&usbhs_bdata);
524 omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions, 520 omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index ff53deccecab..df2534de3361 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -144,7 +144,6 @@ static struct lis3lv02d_platform_data rx51_lis3lv02d_data = {
144 .release_resources = lis302_release, 144 .release_resources = lis302_release,
145 .st_min_limits = {-32, 3, 3}, 145 .st_min_limits = {-32, 3, 3},
146 .st_max_limits = {-3, 32, 32}, 146 .st_max_limits = {-3, 32, 32},
147 .irq2 = OMAP_GPIO_IRQ(LIS302_IRQ2_GPIO),
148}; 147};
149#endif 148#endif
150 149
@@ -1030,7 +1029,6 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
1030 { 1029 {
1031 I2C_BOARD_INFO("lis3lv02d", 0x1d), 1030 I2C_BOARD_INFO("lis3lv02d", 0x1d),
1032 .platform_data = &rx51_lis3lv02d_data, 1031 .platform_data = &rx51_lis3lv02d_data,
1033 .irq = OMAP_GPIO_IRQ(LIS302_IRQ1_GPIO),
1034 }, 1032 },
1035#endif 1033#endif
1036}; 1034};
@@ -1056,6 +1054,10 @@ static int __init rx51_i2c_init(void)
1056 omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata); 1054 omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
1057 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2, 1055 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
1058 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2)); 1056 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
1057#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
1058 rx51_lis3lv02d_data.irq2 = gpio_to_irq(LIS302_IRQ2_GPIO);
1059 rx51_peripherals_i2c_board_info_3[0].irq = gpio_to_irq(LIS302_IRQ1_GPIO);
1060#endif
1059 omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3, 1061 omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3,
1060 ARRAY_SIZE(rx51_peripherals_i2c_board_info_3)); 1062 ARRAY_SIZE(rx51_peripherals_i2c_board_info_3));
1061 return 0; 1063 return 0;
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 5c4e66542169..ea3f565ba1a4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -398,24 +398,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
398 return omap2_clksel_set_parent(clk, new_parent); 398 return omap2_clksel_set_parent(clk, new_parent);
399} 399}
400 400
401/* OMAP3/4 non-CORE DPLL clkops */
402
403#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
404
405const struct clkops clkops_omap3_noncore_dpll_ops = {
406 .enable = omap3_noncore_dpll_enable,
407 .disable = omap3_noncore_dpll_disable,
408 .allow_idle = omap3_dpll_allow_idle,
409 .deny_idle = omap3_dpll_deny_idle,
410};
411
412const struct clkops clkops_omap3_core_dpll_ops = {
413 .allow_idle = omap3_dpll_allow_idle,
414 .deny_idle = omap3_dpll_deny_idle,
415};
416
417#endif
418
419/* 401/*
420 * OMAP2+ clock reset and init functions 402 * OMAP2+ clock reset and init functions
421 */ 403 */
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index bace9308a4db..002745181ad6 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1774,8 +1774,6 @@ static struct omap_clk omap2420_clks[] = {
1774 CLK(NULL, "osc_ck", &osc_ck, CK_242X), 1774 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1775 CLK(NULL, "sys_ck", &sys_ck, CK_242X), 1775 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1776 CLK(NULL, "alt_ck", &alt_ck, CK_242X), 1776 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
1777 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X),
1778 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X),
1779 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), 1777 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
1780 /* internal analog sources */ 1778 /* internal analog sources */
1781 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), 1779 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
@@ -1784,8 +1782,6 @@ static struct omap_clk omap2420_clks[] = {
1784 /* internal prcm root sources */ 1782 /* internal prcm root sources */
1785 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), 1783 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1786 CLK(NULL, "core_ck", &core_ck, CK_242X), 1784 CLK(NULL, "core_ck", &core_ck, CK_242X),
1787 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X),
1788 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X),
1789 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), 1785 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1790 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), 1786 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1791 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), 1787 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
@@ -1901,42 +1897,9 @@ static struct omap_clk omap2420_clks[] = {
1901 CLK(NULL, "pka_ick", &pka_ick, CK_242X), 1897 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1902 CLK(NULL, "usb_fck", &usb_fck, CK_242X), 1898 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1903 CLK("musb-hdrc", "fck", &osc_ck, CK_242X), 1899 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1904 CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X), 1900 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
1905 CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X), 1901 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
1906 CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X), 1902 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
1907 CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
1908 CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
1909 CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
1910 CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
1911 CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
1912 CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
1913 CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
1914 CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
1915 CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
1916 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
1917 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
1918 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
1919 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
1920 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
1921 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
1922 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
1923 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
1924 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
1925 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
1926 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
1927 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
1928 CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
1929 CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
1930 CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
1931 CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
1932 CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
1933 CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
1934 CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
1935 CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
1936 CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
1937 CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
1938 CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
1939 CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
1940}; 1903};
1941 1904
1942/* 1905/*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 3b4d09a50399..cacabb070e22 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1858,11 +1858,6 @@ static struct omap_clk omap2430_clks[] = {
1858 CLK(NULL, "osc_ck", &osc_ck, CK_243X), 1858 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1859 CLK(NULL, "sys_ck", &sys_ck, CK_243X), 1859 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1860 CLK(NULL, "alt_ck", &alt_ck, CK_243X), 1860 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1861 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X),
1862 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X),
1863 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X),
1864 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X),
1865 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X),
1866 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), 1861 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
1867 /* internal analog sources */ 1862 /* internal analog sources */
1868 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), 1863 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
@@ -1871,11 +1866,6 @@ static struct omap_clk omap2430_clks[] = {
1871 /* internal prcm root sources */ 1866 /* internal prcm root sources */
1872 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), 1867 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1873 CLK(NULL, "core_ck", &core_ck, CK_243X), 1868 CLK(NULL, "core_ck", &core_ck, CK_243X),
1874 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X),
1875 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X),
1876 CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X),
1877 CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X),
1878 CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X),
1879 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), 1869 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1880 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), 1870 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1881 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), 1871 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
@@ -2000,42 +1990,9 @@ static struct omap_clk omap2430_clks[] = {
2000 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), 1990 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
2001 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), 1991 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2002 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), 1992 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2003 CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X), 1993 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
2004 CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X), 1994 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
2005 CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X), 1995 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
2006 CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
2007 CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
2008 CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
2009 CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
2010 CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
2011 CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
2012 CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
2013 CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
2014 CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
2015 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
2016 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
2017 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
2018 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
2019 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
2020 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
2021 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
2022 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
2023 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
2024 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
2025 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
2026 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
2027 CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
2028 CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
2029 CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
2030 CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
2031 CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
2032 CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
2033 CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
2034 CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
2035 CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
2036 CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
2037 CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
2038 CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
2039}; 1996};
2040 1997
2041/* 1998/*
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 9c8ac7dc9f3c..25bbcc7ca4dc 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1075,7 +1075,7 @@ int __init am33xx_clk_init(void)
1075 struct omap_clk *c; 1075 struct omap_clk *c;
1076 u32 cpu_clkflg; 1076 u32 cpu_clkflg;
1077 1077
1078 if (cpu_is_am33xx()) { 1078 if (soc_is_am33xx()) {
1079 cpu_mask = RATE_IN_AM33XX; 1079 cpu_mask = RATE_IN_AM33XX;
1080 cpu_clkflg = CK_AM33XX; 1080 cpu_clkflg = CK_AM33XX;
1081 } 1081 }
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 9d7ef6c13745..095a133128eb 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3224,11 +3224,6 @@ static struct omap_clk omap3xxx_clks[] = {
3224 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), 3224 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3225 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), 3225 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3226 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), 3226 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3227 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3228 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3229 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3230 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3231 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3232 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), 3227 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3233 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), 3228 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3234 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3229 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
@@ -3295,8 +3290,6 @@ static struct omap_clk omap3xxx_clks[] = {
3295 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3290 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3296 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3291 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3297 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3292 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3298 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3299 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3300 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3293 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3301 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3294 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3302 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), 3295 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
@@ -3401,9 +3394,6 @@ static struct omap_clk omap3xxx_clks[] = {
3401 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), 3394 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3402 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), 3395 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3403 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), 3396 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3404 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3405 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3406 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3407 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), 3397 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3408 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), 3398 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3409 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), 3399 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
@@ -3470,30 +3460,8 @@ static struct omap_clk omap3xxx_clks[] = {
3470 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), 3460 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3471 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), 3461 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3472 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), 3462 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3473 CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), 3463 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3474 CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX), 3464 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3475 CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
3476 CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX),
3477 CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX),
3478 CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX),
3479 CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX),
3480 CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX),
3481 CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX),
3482 CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX),
3483 CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX),
3484 CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX),
3485 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX),
3486 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX),
3487 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX),
3488 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX),
3489 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX),
3490 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX),
3491 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX),
3492 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX),
3493 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX),
3494 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX),
3495 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX),
3496 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX),
3497}; 3465};
3498 3466
3499 3467
@@ -3502,7 +3470,7 @@ int __init omap3xxx_clk_init(void)
3502 struct omap_clk *c; 3470 struct omap_clk *c;
3503 u32 cpu_clkflg = 0; 3471 u32 cpu_clkflg = 0;
3504 3472
3505 if (cpu_is_omap3517()) { 3473 if (soc_is_am35xx()) {
3506 cpu_mask = RATE_IN_34XX; 3474 cpu_mask = RATE_IN_34XX;
3507 cpu_clkflg = CK_AM35XX; 3475 cpu_clkflg = CK_AM35XX;
3508 } else if (cpu_is_omap3630()) { 3476 } else if (cpu_is_omap3630()) {
@@ -3511,7 +3479,7 @@ int __init omap3xxx_clk_init(void)
3511 } else if (cpu_is_ti816x()) { 3479 } else if (cpu_is_ti816x()) {
3512 cpu_mask = RATE_IN_TI816X; 3480 cpu_mask = RATE_IN_TI816X;
3513 cpu_clkflg = CK_TI816X; 3481 cpu_clkflg = CK_TI816X;
3514 } else if (cpu_is_am33xx()) { 3482 } else if (soc_is_am33xx()) {
3515 cpu_mask = RATE_IN_AM33XX; 3483 cpu_mask = RATE_IN_AM33XX;
3516 } else if (cpu_is_ti814x()) { 3484 } else if (cpu_is_ti814x()) {
3517 cpu_mask = RATE_IN_TI814X; 3485 cpu_mask = RATE_IN_TI814X;
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 66c2e2701f0c..abbefc84a61b 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -84,6 +84,7 @@ static struct clk slimbus_clk = {
84 84
85static struct clk sys_32k_ck = { 85static struct clk sys_32k_ck = {
86 .name = "sys_32k_ck", 86 .name = "sys_32k_ck",
87 .clkdm_name = "prm_clkdm",
87 .rate = 32768, 88 .rate = 32768,
88 .ops = &clkops_null, 89 .ops = &clkops_null,
89}; 90};
@@ -440,6 +441,7 @@ static struct clk ddrphy_ck = {
440 .name = "ddrphy_ck", 441 .name = "ddrphy_ck",
441 .parent = &dpll_core_m2_ck, 442 .parent = &dpll_core_m2_ck,
442 .ops = &clkops_null, 443 .ops = &clkops_null,
444 .clkdm_name = "l3_emif_clkdm",
443 .fixed_div = 2, 445 .fixed_div = 2,
444 .recalc = &omap_fixed_divisor_recalc, 446 .recalc = &omap_fixed_divisor_recalc,
445}; 447};
@@ -697,6 +699,7 @@ static const struct clksel dpll_mpu_m2_div[] = {
697static struct clk dpll_mpu_m2_ck = { 699static struct clk dpll_mpu_m2_ck = {
698 .name = "dpll_mpu_m2_ck", 700 .name = "dpll_mpu_m2_ck",
699 .parent = &dpll_mpu_ck, 701 .parent = &dpll_mpu_ck,
702 .clkdm_name = "cm_clkdm",
700 .clksel = dpll_mpu_m2_div, 703 .clksel = dpll_mpu_m2_div,
701 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, 704 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
702 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, 705 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
@@ -1077,6 +1080,7 @@ static const struct clksel l3_div_div[] = {
1077static struct clk l3_div_ck = { 1080static struct clk l3_div_ck = {
1078 .name = "l3_div_ck", 1081 .name = "l3_div_ck",
1079 .parent = &div_core_ck, 1082 .parent = &div_core_ck,
1083 .clkdm_name = "cm_clkdm",
1080 .clksel = l3_div_div, 1084 .clksel = l3_div_div,
1081 .clksel_reg = OMAP4430_CM_CLKSEL_CORE, 1085 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1082 .clksel_mask = OMAP4430_CLKSEL_L3_MASK, 1086 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
@@ -2752,6 +2756,7 @@ static const struct clksel trace_clk_div_div[] = {
2752static struct clk trace_clk_div_ck = { 2756static struct clk trace_clk_div_ck = {
2753 .name = "trace_clk_div_ck", 2757 .name = "trace_clk_div_ck",
2754 .parent = &pmd_trace_clk_mux_ck, 2758 .parent = &pmd_trace_clk_mux_ck,
2759 .clkdm_name = "emu_sys_clkdm",
2755 .clksel = trace_clk_div_div, 2760 .clksel = trace_clk_div_div,
2756 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, 2761 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2757 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, 2762 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
@@ -3308,28 +3313,18 @@ static struct omap_clk omap44xx_clks[] = {
3308 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), 3313 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
3309 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), 3314 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
3310 CLK("omap_wdt", "ick", &dummy_ck, CK_443X), 3315 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3311 CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X), 3316 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
3312 CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X), 3317 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3313 CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X), 3318 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3314 CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X), 3319 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3315 CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X), 3320 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3316 CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X), 3321 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3317 CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X), 3322 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3318 CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X), 3323 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3319 CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X), 3324 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3320 CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X), 3325 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3321 CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X), 3326 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3322 CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X), 3327 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3323 CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X),
3324 CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X),
3325 CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X),
3326 CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X),
3327 CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X),
3328 CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X),
3329 CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X),
3330 CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X),
3331 CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X),
3332 CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X),
3333}; 3328};
3334 3329
3335int __init omap4xxx_clk_init(void) 3330int __init omap4xxx_clk_init(void)
@@ -3340,9 +3335,12 @@ int __init omap4xxx_clk_init(void)
3340 if (cpu_is_omap443x()) { 3335 if (cpu_is_omap443x()) {
3341 cpu_mask = RATE_IN_4430; 3336 cpu_mask = RATE_IN_4430;
3342 cpu_clkflg = CK_443X; 3337 cpu_clkflg = CK_443X;
3343 } else if (cpu_is_omap446x()) { 3338 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
3344 cpu_mask = RATE_IN_4460 | RATE_IN_4430; 3339 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
3345 cpu_clkflg = CK_446X | CK_443X; 3340 cpu_clkflg = CK_446X | CK_443X;
3341
3342 if (cpu_is_omap447x())
3343 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
3346 } else { 3344 } else {
3347 return 0; 3345 return 0;
3348 } 3346 }
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 72cb12bbb9c3..0a8c7b67858c 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -208,7 +208,5 @@ extern struct clkdm_ops am33xx_clkdm_operations;
208extern struct clkdm_dep gfx_24xx_wkdeps[]; 208extern struct clkdm_dep gfx_24xx_wkdeps[];
209extern struct clkdm_dep dsp_24xx_wkdeps[]; 209extern struct clkdm_dep dsp_24xx_wkdeps[];
210extern struct clockdomain wkup_common_clkdm; 210extern struct clockdomain wkup_common_clkdm;
211extern struct clockdomain prm_common_clkdm;
212extern struct clockdomain cm_common_clkdm;
213 211
214#endif 212#endif
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 4f04dd11d655..762f2cc542ce 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -70,7 +70,7 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
70 70
71static int omap4_clkdm_sleep(struct clockdomain *clkdm) 71static int omap4_clkdm_sleep(struct clockdomain *clkdm)
72{ 72{
73 omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, 73 omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
74 clkdm->cm_inst, clkdm->clkdm_offs); 74 clkdm->cm_inst, clkdm->clkdm_offs);
75 return 0; 75 return 0;
76} 76}
@@ -90,8 +90,12 @@ static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
90 90
91static void omap4_clkdm_deny_idle(struct clockdomain *clkdm) 91static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
92{ 92{
93 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, 93 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
94 clkdm->cm_inst, clkdm->clkdm_offs); 94 omap4_clkdm_wakeup(clkdm);
95 else
96 omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
97 clkdm->cm_inst,
98 clkdm->clkdm_offs);
95} 99}
96 100
97static int omap4_clkdm_clk_enable(struct clockdomain *clkdm) 101static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 0ab8e46d5b2b..5c741852fac0 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -131,8 +131,6 @@ static struct clockdomain dss_2420_clkdm = {
131 131
132static struct clockdomain *clockdomains_omap242x[] __initdata = { 132static struct clockdomain *clockdomains_omap242x[] __initdata = {
133 &wkup_common_clkdm, 133 &wkup_common_clkdm,
134 &cm_common_clkdm,
135 &prm_common_clkdm,
136 &mpu_2420_clkdm, 134 &mpu_2420_clkdm,
137 &iva1_2420_clkdm, 135 &iva1_2420_clkdm,
138 &dsp_2420_clkdm, 136 &dsp_2420_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index 3645ed044890..f09617555e15 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -157,8 +157,6 @@ static struct clockdomain dss_2430_clkdm = {
157 157
158static struct clockdomain *clockdomains_omap243x[] __initdata = { 158static struct clockdomain *clockdomains_omap243x[] __initdata = {
159 &wkup_common_clkdm, 159 &wkup_common_clkdm,
160 &cm_common_clkdm,
161 &prm_common_clkdm,
162 &mpu_2430_clkdm, 160 &mpu_2430_clkdm,
163 &mdm_clkdm, 161 &mdm_clkdm,
164 &dsp_2430_clkdm, 162 &dsp_2430_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 6038adb97710..2cdc17c9d2fa 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -347,8 +347,6 @@ static struct clkdm_autodep clkdm_autodeps[] = {
347 347
348static struct clockdomain *clockdomains_omap3430_common[] __initdata = { 348static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
349 &wkup_common_clkdm, 349 &wkup_common_clkdm,
350 &cm_common_clkdm,
351 &prm_common_clkdm,
352 &mpu_3xxx_clkdm, 350 &mpu_3xxx_clkdm,
353 &neon_clkdm, 351 &neon_clkdm,
354 &iva2_clkdm, 352 &iva2_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index c53425847493..bd7ed13515cc 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -430,8 +430,6 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
430 &l4_wkup_44xx_clkdm, 430 &l4_wkup_44xx_clkdm,
431 &emu_sys_44xx_clkdm, 431 &emu_sys_44xx_clkdm,
432 &l3_dma_44xx_clkdm, 432 &l3_dma_44xx_clkdm,
433 &prm_common_clkdm,
434 &cm_common_clkdm,
435 NULL 433 NULL
436}; 434};
437 435
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
deleted file mode 100644
index 615b1f04967d..000000000000
--- a/arch/arm/mach-omap2/clockdomains_common_data.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * OMAP2+-common clockdomain data
3 *
4 * Copyright (C) 2008-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Paul Walmsley, Jouni Högander
8 */
9
10#include <linux/kernel.h>
11#include <linux/io.h>
12
13#include "clockdomain.h"
14
15/* These are implicit clockdomains - they are never defined as such in TRM */
16struct clockdomain prm_common_clkdm = {
17 .name = "prm_clkdm",
18 .pwrdm = { .name = "wkup_pwrdm" },
19};
20
21struct clockdomain cm_common_clkdm = {
22 .name = "cm_clkdm",
23 .pwrdm = { .name = "core_pwrdm" },
24};
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index a7bc096bd407..f24e3f7a2bbc 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -22,4 +22,15 @@
22 */ 22 */
23#define MAX_MODULE_READY_TIME 2000 23#define MAX_MODULE_READY_TIME 2000
24 24
25/*
26 * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for
27 * the PRCM to request that a module enter the inactive state in the
28 * case of OMAP2 & 3. In the case of OMAP4 this is the max duration
29 * in microseconds for the module to reach the inactive state from
30 * a functional state.
31 * XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during
32 * kernel init.
33 */
34#define MAX_MODULE_DISABLE_TIME 5000
35
25#endif 36#endif
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 8c86d294b1a3..1894015ff04b 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -235,20 +235,6 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
235} 235}
236 236
237/** 237/**
238 * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
239 * @part: PRCM partition ID that the clockdomain registers exist in
240 * @inst: CM instance register offset (*_INST macro)
241 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
242 *
243 * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
244 * No return value.
245 */
246void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
247{
248 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
249}
250
251/**
252 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle 238 * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
253 * @part: PRCM partition ID that the clockdomain registers exist in 239 * @part: PRCM partition ID that the clockdomain registers exist in
254 * @inst: CM instance register offset (*_INST macro) 240 * @inst: CM instance register offset (*_INST macro)
@@ -313,9 +299,9 @@ int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_off
313 299
314 omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) == 300 omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
315 CLKCTRL_IDLEST_DISABLED), 301 CLKCTRL_IDLEST_DISABLED),
316 MAX_MODULE_READY_TIME, i); 302 MAX_MODULE_DISABLE_TIME, i);
317 303
318 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 304 return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY;
319} 305}
320 306
321/** 307/**
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index a018a7327879..d69fdefef985 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -16,38 +16,13 @@ extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
16extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs); 16extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
17extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs); 17extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
18extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); 18extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
19
20extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs); 19extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
21
22# ifdef CONFIG_ARCH_OMAP4
23extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, 20extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
24 u16 clkctrl_offs); 21 u16 clkctrl_offs);
25
26extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs, 22extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
27 u16 clkctrl_offs); 23 u16 clkctrl_offs);
28extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs, 24extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
29 u16 clkctrl_offs); 25 u16 clkctrl_offs);
30
31# else
32
33static inline int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
34 u16 clkctrl_offs)
35{
36 return 0;
37}
38
39static inline void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
40 s16 cdoffs, u16 clkctrl_offs)
41{
42}
43
44static inline void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
45 u16 clkctrl_offs)
46{
47}
48
49# endif
50
51/* 26/*
52 * In an ideal world, we would not export these low-level functions, 27 * In an ideal world, we would not export these low-level functions,
53 * but this will probably take some time to fix properly 28 * but this will probably take some time to fix properly
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 8a6953a34fe2..73d2a0b9ca04 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -29,8 +29,6 @@
29 29
30/* Global address base setup code */ 30/* Global address base setup code */
31 31
32#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
33
34static void __init __omap2_set_globals(struct omap_globals *omap2_globals) 32static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
35{ 33{
36 omap2_set_globals_tap(omap2_globals); 34 omap2_set_globals_tap(omap2_globals);
@@ -39,8 +37,6 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
39 omap2_set_globals_prcm(omap2_globals); 37 omap2_set_globals_prcm(omap2_globals);
40} 38}
41 39
42#endif
43
44#if defined(CONFIG_SOC_OMAP2420) 40#if defined(CONFIG_SOC_OMAP2420)
45 41
46static struct omap_globals omap242x_globals = { 42static struct omap_globals omap242x_globals = {
@@ -134,7 +130,9 @@ void __init ti81xx_map_io(void)
134{ 130{
135 omapti81xx_map_common_io(); 131 omapti81xx_map_common_io();
136} 132}
133#endif
137 134
135#if defined(CONFIG_SOC_AM33XX)
138#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \ 136#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \
139 TI81XX_CONTROL_DEVICE_ID - 0x204) 137 TI81XX_CONTROL_DEVICE_ID - 0x204)
140 138
@@ -171,9 +169,7 @@ static struct omap_globals omap4_globals = {
171 169
172void __init omap2_set_globals_443x(void) 170void __init omap2_set_globals_443x(void)
173{ 171{
174 omap2_set_globals_tap(&omap4_globals); 172 __omap2_set_globals(&omap4_globals);
175 omap2_set_globals_control(&omap4_globals);
176 omap2_set_globals_prcm(&omap4_globals);
177} 173}
178 174
179void __init omap4_map_io(void) 175void __init omap4_map_io(void)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 5d99c1b2cb48..404f172d95a8 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -174,7 +174,12 @@ void omap2_set_globals_am33xx(void);
174 174
175/* These get called from omap2_set_globals_xxxx(), do not call these */ 175/* These get called from omap2_set_globals_xxxx(), do not call these */
176void omap2_set_globals_tap(struct omap_globals *); 176void omap2_set_globals_tap(struct omap_globals *);
177#if defined(CONFIG_SOC_HAS_OMAP2_SDRC)
177void omap2_set_globals_sdrc(struct omap_globals *); 178void omap2_set_globals_sdrc(struct omap_globals *);
179#else
180static inline void omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
181{ }
182#endif
178void omap2_set_globals_control(struct omap_globals *); 183void omap2_set_globals_control(struct omap_globals *);
179void omap2_set_globals_prcm(struct omap_globals *); 184void omap2_set_globals_prcm(struct omap_globals *);
180 185
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 08e674bb0417..3223b81e7532 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -241,6 +241,49 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
241 241
242#endif 242#endif
243 243
244/**
245 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
246 * @bootaddr: physical address of the boot loader
247 *
248 * Set boot address for the boot loader of a supported processor
249 * when a power ON sequence occurs.
250 */
251void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
252{
253 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
254 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
255 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
256 0;
257
258 if (!offset) {
259 pr_err("%s: unsupported omap type\n", __func__);
260 return;
261 }
262
263 omap_ctrl_writel(bootaddr, offset);
264}
265
266/**
267 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
268 * @bootmode: 8-bit value to pass to some boot code
269 *
270 * Sets boot mode for the boot loader of a supported processor
271 * when a power ON sequence occurs.
272 */
273void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
274{
275 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
276 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
277 0;
278
279 if (!offset) {
280 pr_err("%s: unsupported omap type\n", __func__);
281 return;
282 }
283
284 omap_ctrl_writel(bootmode, offset);
285}
286
244#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 287#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
245/* 288/*
246 * Clears the scratchpad contents in case of cold boot- 289 * Clears the scratchpad contents in case of cold boot-
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index c43f03cbefc5..295b39047a71 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -188,6 +188,7 @@
188#define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) 188#define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
189#define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) 189#define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
190#define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) 190#define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C)
191#define OMAP3630_CONTROL_CAMERA_PHY_CTRL (OMAP2_CONTROL_GENERAL + 0x02f0)
191 192
192/* OMAP44xx control efuse offsets */ 193/* OMAP44xx control efuse offsets */
193#define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C 194#define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C
@@ -404,6 +405,8 @@ extern u32 omap3_arm_context[128];
404extern void omap3_control_save_context(void); 405extern void omap3_control_save_context(void);
405extern void omap3_control_restore_context(void); 406extern void omap3_control_restore_context(void);
406extern void omap3_ctrl_write_boot_mode(u8 bootmode); 407extern void omap3_ctrl_write_boot_mode(u8 bootmode);
408extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
409extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
407extern void omap3630_ctrl_disable_rta(void); 410extern void omap3630_ctrl_disable_rta(void);
408extern int omap3_ctrl_save_padconf(void); 411extern int omap3_ctrl_save_padconf(void);
409#else 412#else
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 54d49ddb9b81..5fb47a14f4ba 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -271,9 +271,9 @@ static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
271 goto err; 271 goto err;
272 } 272 }
273 273
274 r = omap_device_register(pdev); 274 r = platform_device_add(pdev);
275 if (r) { 275 if (r) {
276 pr_err("Could not register omap_device for %s\n", pdev_name); 276 pr_err("Could not register platform_device for %s\n", pdev_name);
277 goto err; 277 goto err;
278 } 278 }
279 279
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f0f10beeffe8..b9c8d2f6a81f 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -135,11 +135,20 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
135 */ 135 */
136static int _omap3_noncore_dpll_lock(struct clk *clk) 136static int _omap3_noncore_dpll_lock(struct clk *clk)
137{ 137{
138 const struct dpll_data *dd;
138 u8 ai; 139 u8 ai;
139 int r; 140 u8 state = 1;
141 int r = 0;
140 142
141 pr_debug("clock: locking DPLL %s\n", clk->name); 143 pr_debug("clock: locking DPLL %s\n", clk->name);
142 144
145 dd = clk->dpll_data;
146 state <<= __ffs(dd->idlest_mask);
147
148 /* Check if already locked */
149 if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
150 goto done;
151
143 ai = omap3_dpll_autoidle_read(clk); 152 ai = omap3_dpll_autoidle_read(clk);
144 153
145 if (ai) 154 if (ai)
@@ -152,6 +161,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
152 if (ai) 161 if (ai)
153 omap3_dpll_allow_idle(clk); 162 omap3_dpll_allow_idle(clk);
154 163
164done:
155 return r; 165 return r;
156} 166}
157 167
@@ -628,3 +638,17 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
628 rate = clk->parent->rate * 2; 638 rate = clk->parent->rate * 2;
629 return rate; 639 return rate;
630} 640}
641
642/* OMAP3/4 non-CORE DPLL clkops */
643
644const struct clkops clkops_omap3_noncore_dpll_ops = {
645 .enable = omap3_noncore_dpll_enable,
646 .disable = omap3_noncore_dpll_disable,
647 .allow_idle = omap3_dpll_allow_idle,
648 .deny_idle = omap3_dpll_deny_idle,
649};
650
651const struct clkops clkops_omap3_core_dpll_ops = {
652 .allow_idle = omap3_dpll_allow_idle,
653 .deny_idle = omap3_dpll_deny_idle,
654};
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 845309f146fe..a636ebc16b39 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -20,6 +20,10 @@
20 20
21#include <linux/module.h> 21#include <linux/module.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23
24#include <asm/memblock.h>
25
26#include "control.h"
23#include "cm2xxx_3xxx.h" 27#include "cm2xxx_3xxx.h"
24#include "prm2xxx_3xxx.h" 28#include "prm2xxx_3xxx.h"
25#ifdef CONFIG_BRIDGE_DVFS 29#ifdef CONFIG_BRIDGE_DVFS
@@ -43,6 +47,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
43 .dsp_cm_read = omap2_cm_read_mod_reg, 47 .dsp_cm_read = omap2_cm_read_mod_reg,
44 .dsp_cm_write = omap2_cm_write_mod_reg, 48 .dsp_cm_write = omap2_cm_write_mod_reg,
45 .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, 49 .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
50
51 .set_bootaddr = omap_ctrl_write_dsp_boot_addr,
52 .set_bootmode = omap_ctrl_write_dsp_boot_mode,
46}; 53};
47 54
48static phys_addr_t omap_dsp_phys_mempool_base; 55static phys_addr_t omap_dsp_phys_mempool_base;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0389b3264abe..37eb95aaf2f6 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -44,7 +44,7 @@ int omap_type(void)
44 44
45 if (cpu_is_omap24xx()) { 45 if (cpu_is_omap24xx()) {
46 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 46 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
47 } else if (cpu_is_am33xx()) { 47 } else if (soc_is_am33xx()) {
48 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 48 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
49 } else if (cpu_is_omap34xx()) { 49 } else if (cpu_is_omap34xx()) {
50 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 50 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
@@ -189,7 +189,7 @@ static void __init omap3_cpuinfo(void)
189 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; 189 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
190 } else if (cpu_is_ti816x()) { 190 } else if (cpu_is_ti816x()) {
191 cpu_name = "TI816X"; 191 cpu_name = "TI816X";
192 } else if (cpu_is_am335x()) { 192 } else if (soc_is_am335x()) {
193 cpu_name = "AM335X"; 193 cpu_name = "AM335X";
194 } else if (cpu_is_ti814x()) { 194 } else if (cpu_is_ti814x()) {
195 cpu_name = "TI814X"; 195 cpu_name = "TI814X";
@@ -247,6 +247,17 @@ void __init omap3xxx_check_features(void)
247 omap_features |= OMAP3_HAS_SDRC; 247 omap_features |= OMAP3_HAS_SDRC;
248 248
249 /* 249 /*
250 * am35x fixups:
251 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
252 * reserved and therefore return 0 when read. Unfortunately,
253 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
254 * mean that a feature is present even though it isn't so clear
255 * the incorrectly set feature bits.
256 */
257 if (soc_is_am35xx())
258 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
259
260 /*
250 * TODO: Get additional info (where applicable) 261 * TODO: Get additional info (where applicable)
251 * e.g. Size of L2 cache. 262 * e.g. Size of L2 cache.
252 */ 263 */
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
index 2f7ac70a20d8..01970824e0e5 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -42,6 +42,7 @@
42#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 42#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
43#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 43#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
44#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 44#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
45#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304
45#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 46#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
46#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 47#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
47#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 48#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 428685f65060..d5b34febd82d 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -149,6 +149,7 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
149 ct->chip.irq_ack = omap_mask_ack_irq; 149 ct->chip.irq_ack = omap_mask_ack_irq;
150 ct->chip.irq_mask = irq_gc_mask_disable_reg; 150 ct->chip.irq_mask = irq_gc_mask_disable_reg;
151 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 151 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
152 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
152 153
153 ct->regs.enable = INTC_MIR_CLEAR0; 154 ct->regs.enable = INTC_MIR_CLEAR0;
154 ct->regs.disable = INTC_MIR_SET0; 155 ct->regs.disable = INTC_MIR_SET0;
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 80e55c5c9998..9fe6829f4c16 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -41,6 +41,7 @@
41#include "control.h" 41#include "control.h"
42#include "mux.h" 42#include "mux.h"
43#include "prm.h" 43#include "prm.h"
44#include "common.h"
44 45
45#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ 46#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
46#define OMAP_MUX_BASE_SZ 0x5ca 47#define OMAP_MUX_BASE_SZ 0x5ca
@@ -217,8 +218,7 @@ static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
217 return -ENODEV; 218 return -ENODEV;
218} 219}
219 220
220static int __init 221int __init omap_mux_get_by_name(const char *muxname,
221omap_mux_get_by_name(const char *muxname,
222 struct omap_mux_partition **found_partition, 222 struct omap_mux_partition **found_partition,
223 struct omap_mux **found_mux) 223 struct omap_mux **found_mux)
224{ 224{
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 69fe060a0b75..471e62a74a16 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -59,6 +59,7 @@
59#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN 59#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
60 60
61#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) 61#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
62#define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0)
62 63
63/* Flags for omapX_mux_init */ 64/* Flags for omapX_mux_init */
64#define OMAP_PACKAGE_MASK 0xffff 65#define OMAP_PACKAGE_MASK 0xffff
@@ -225,8 +226,18 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
225 */ 226 */
226void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state); 227void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
227 228
229int omap_mux_get_by_name(const char *muxname,
230 struct omap_mux_partition **found_partition,
231 struct omap_mux **found_mux);
228#else 232#else
229 233
234static inline int omap_mux_get_by_name(const char *muxname,
235 struct omap_mux_partition **found_partition,
236 struct omap_mux **found_mux)
237{
238 return 0;
239}
240
230static inline int omap_mux_init_gpio(int gpio, int val) 241static inline int omap_mux_init_gpio(int gpio, int val)
231{ 242{
232 return 0; 243 return 0;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index bf86f7e8f91f..ebdf0016e536 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -166,6 +166,31 @@
166 */ 166 */
167#define LINKS_PER_OCP_IF 2 167#define LINKS_PER_OCP_IF 2
168 168
169/**
170 * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
171 * @enable_module: function to enable a module (via MODULEMODE)
172 * @disable_module: function to disable a module (via MODULEMODE)
173 *
174 * XXX Eventually this functionality will be hidden inside the PRM/CM
175 * device drivers. Until then, this should avoid huge blocks of cpu_is_*()
176 * conditionals in this code.
177 */
178struct omap_hwmod_soc_ops {
179 void (*enable_module)(struct omap_hwmod *oh);
180 int (*disable_module)(struct omap_hwmod *oh);
181 int (*wait_target_ready)(struct omap_hwmod *oh);
182 int (*assert_hardreset)(struct omap_hwmod *oh,
183 struct omap_hwmod_rst_info *ohri);
184 int (*deassert_hardreset)(struct omap_hwmod *oh,
185 struct omap_hwmod_rst_info *ohri);
186 int (*is_hardreset_asserted)(struct omap_hwmod *oh,
187 struct omap_hwmod_rst_info *ohri);
188 int (*init_clkdm)(struct omap_hwmod *oh);
189};
190
191/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
192static struct omap_hwmod_soc_ops soc_ops;
193
169/* omap_hwmod_list contains all registered struct omap_hwmods */ 194/* omap_hwmod_list contains all registered struct omap_hwmods */
170static LIST_HEAD(omap_hwmod_list); 195static LIST_HEAD(omap_hwmod_list);
171 196
@@ -186,6 +211,9 @@ static struct omap_hwmod_link *linkspace;
186 */ 211 */
187static unsigned short free_ls, max_ls, ls_supp; 212static unsigned short free_ls, max_ls, ls_supp;
188 213
214/* inited: set to true once the hwmod code is initialized */
215static bool inited;
216
189/* Private functions */ 217/* Private functions */
190 218
191/** 219/**
@@ -388,6 +416,49 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
388} 416}
389 417
390/** 418/**
419 * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v
420 * @oh: struct omap_hwmod *
421 *
422 * The DMADISABLE bit is a semi-automatic bit present in sysconfig register
423 * of some modules. When the DMA must perform read/write accesses, the
424 * DMADISABLE bit is cleared by the hardware. But when the DMA must stop
425 * for power management, software must set the DMADISABLE bit back to 1.
426 *
427 * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon
428 * error or 0 upon success.
429 */
430static int _set_dmadisable(struct omap_hwmod *oh)
431{
432 u32 v;
433 u32 dmadisable_mask;
434
435 if (!oh->class->sysc ||
436 !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE))
437 return -EINVAL;
438
439 if (!oh->class->sysc->sysc_fields) {
440 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
441 return -EINVAL;
442 }
443
444 /* clocks must be on for this operation */
445 if (oh->_state != _HWMOD_STATE_ENABLED) {
446 pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name);
447 return -EINVAL;
448 }
449
450 pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name);
451
452 v = oh->_sysc_cache;
453 dmadisable_mask =
454 (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift);
455 v |= dmadisable_mask;
456 _write_sysconfig(v, oh);
457
458 return 0;
459}
460
461/**
391 * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v 462 * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
392 * @oh: struct omap_hwmod * 463 * @oh: struct omap_hwmod *
393 * @autoidle: desired AUTOIDLE bitfield value (0 or 1) 464 * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
@@ -530,7 +601,7 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
530 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) 601 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
531 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); 602 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
532 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) 603 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
533 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); 604 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v);
534 605
535 /* XXX test pwrdm_get_wken for this hwmod's subsystem */ 606 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
536 607
@@ -771,23 +842,19 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
771} 842}
772 843
773/** 844/**
774 * _enable_module - enable CLKCTRL modulemode on OMAP4 845 * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4
775 * @oh: struct omap_hwmod * 846 * @oh: struct omap_hwmod *
776 * 847 *
777 * Enables the PRCM module mode related to the hwmod @oh. 848 * Enables the PRCM module mode related to the hwmod @oh.
778 * No return value. 849 * No return value.
779 */ 850 */
780static void _enable_module(struct omap_hwmod *oh) 851static void _omap4_enable_module(struct omap_hwmod *oh)
781{ 852{
782 /* The module mode does not exist prior OMAP4 */
783 if (cpu_is_omap24xx() || cpu_is_omap34xx())
784 return;
785
786 if (!oh->clkdm || !oh->prcm.omap4.modulemode) 853 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
787 return; 854 return;
788 855
789 pr_debug("omap_hwmod: %s: _enable_module: %d\n", 856 pr_debug("omap_hwmod: %s: %s: %d\n",
790 oh->name, oh->prcm.omap4.modulemode); 857 oh->name, __func__, oh->prcm.omap4.modulemode);
791 858
792 omap4_cminst_module_enable(oh->prcm.omap4.modulemode, 859 omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
793 oh->clkdm->prcm_partition, 860 oh->clkdm->prcm_partition,
@@ -807,10 +874,7 @@ static void _enable_module(struct omap_hwmod *oh)
807 */ 874 */
808static int _omap4_wait_target_disable(struct omap_hwmod *oh) 875static int _omap4_wait_target_disable(struct omap_hwmod *oh)
809{ 876{
810 if (!cpu_is_omap44xx()) 877 if (!oh || !oh->clkdm)
811 return 0;
812
813 if (!oh)
814 return -EINVAL; 878 return -EINVAL;
815 879
816 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 880 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
@@ -1285,24 +1349,20 @@ static struct omap_hwmod *_lookup(const char *name)
1285 1349
1286 return oh; 1350 return oh;
1287} 1351}
1352
1288/** 1353/**
1289 * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod 1354 * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
1290 * @oh: struct omap_hwmod * 1355 * @oh: struct omap_hwmod *
1291 * 1356 *
1292 * Convert a clockdomain name stored in a struct omap_hwmod into a 1357 * Convert a clockdomain name stored in a struct omap_hwmod into a
1293 * clockdomain pointer, and save it into the struct omap_hwmod. 1358 * clockdomain pointer, and save it into the struct omap_hwmod.
1294 * return -EINVAL if clkdm_name does not exist or if the lookup failed. 1359 * Return -EINVAL if the clkdm_name lookup failed.
1295 */ 1360 */
1296static int _init_clkdm(struct omap_hwmod *oh) 1361static int _init_clkdm(struct omap_hwmod *oh)
1297{ 1362{
1298 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1363 if (!oh->clkdm_name)
1299 return 0; 1364 return 0;
1300 1365
1301 if (!oh->clkdm_name) {
1302 pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
1303 return -EINVAL;
1304 }
1305
1306 oh->clkdm = clkdm_lookup(oh->clkdm_name); 1366 oh->clkdm = clkdm_lookup(oh->clkdm_name);
1307 if (!oh->clkdm) { 1367 if (!oh->clkdm) {
1308 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", 1368 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
@@ -1338,7 +1398,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1338 ret |= _init_main_clk(oh); 1398 ret |= _init_main_clk(oh);
1339 ret |= _init_interface_clks(oh); 1399 ret |= _init_interface_clks(oh);
1340 ret |= _init_opt_clks(oh); 1400 ret |= _init_opt_clks(oh);
1341 ret |= _init_clkdm(oh); 1401 if (soc_ops.init_clkdm)
1402 ret |= soc_ops.init_clkdm(oh);
1342 1403
1343 if (!ret) 1404 if (!ret)
1344 oh->_state = _HWMOD_STATE_CLKS_INITED; 1405 oh->_state = _HWMOD_STATE_CLKS_INITED;
@@ -1349,53 +1410,6 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1349} 1410}
1350 1411
1351/** 1412/**
1352 * _wait_target_ready - wait for a module to leave slave idle
1353 * @oh: struct omap_hwmod *
1354 *
1355 * Wait for a module @oh to leave slave idle. Returns 0 if the module
1356 * does not have an IDLEST bit or if the module successfully leaves
1357 * slave idle; otherwise, pass along the return value of the
1358 * appropriate *_cm*_wait_module_ready() function.
1359 */
1360static int _wait_target_ready(struct omap_hwmod *oh)
1361{
1362 struct omap_hwmod_ocp_if *os;
1363 int ret;
1364
1365 if (!oh)
1366 return -EINVAL;
1367
1368 if (oh->flags & HWMOD_NO_IDLEST)
1369 return 0;
1370
1371 os = _find_mpu_rt_port(oh);
1372 if (!os)
1373 return 0;
1374
1375 /* XXX check module SIDLEMODE */
1376
1377 /* XXX check clock enable states */
1378
1379 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1380 ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
1381 oh->prcm.omap2.idlest_reg_id,
1382 oh->prcm.omap2.idlest_idle_bit);
1383 } else if (cpu_is_omap44xx()) {
1384 if (!oh->clkdm)
1385 return -EINVAL;
1386
1387 ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
1388 oh->clkdm->cm_inst,
1389 oh->clkdm->clkdm_offs,
1390 oh->prcm.omap4.clkctrl_offs);
1391 } else {
1392 BUG();
1393 };
1394
1395 return ret;
1396}
1397
1398/**
1399 * _lookup_hardreset - fill register bit info for this hwmod/reset line 1413 * _lookup_hardreset - fill register bit info for this hwmod/reset line
1400 * @oh: struct omap_hwmod * 1414 * @oh: struct omap_hwmod *
1401 * @name: name of the reset line in the context of this hwmod 1415 * @name: name of the reset line in the context of this hwmod
@@ -1431,32 +1445,31 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
1431 * @oh: struct omap_hwmod * 1445 * @oh: struct omap_hwmod *
1432 * @name: name of the reset line to lookup and assert 1446 * @name: name of the reset line to lookup and assert
1433 * 1447 *
1434 * Some IP like dsp, ipu or iva contain processor that require 1448 * Some IP like dsp, ipu or iva contain processor that require an HW
1435 * an HW reset line to be assert / deassert in order to enable fully 1449 * reset line to be assert / deassert in order to enable fully the IP.
1436 * the IP. 1450 * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
1451 * asserting the hardreset line on the currently-booted SoC, or passes
1452 * along the return value from _lookup_hardreset() or the SoC's
1453 * assert_hardreset code.
1437 */ 1454 */
1438static int _assert_hardreset(struct omap_hwmod *oh, const char *name) 1455static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1439{ 1456{
1440 struct omap_hwmod_rst_info ohri; 1457 struct omap_hwmod_rst_info ohri;
1441 u8 ret; 1458 u8 ret = -EINVAL;
1442 1459
1443 if (!oh) 1460 if (!oh)
1444 return -EINVAL; 1461 return -EINVAL;
1445 1462
1463 if (!soc_ops.assert_hardreset)
1464 return -ENOSYS;
1465
1446 ret = _lookup_hardreset(oh, name, &ohri); 1466 ret = _lookup_hardreset(oh, name, &ohri);
1447 if (IS_ERR_VALUE(ret)) 1467 if (IS_ERR_VALUE(ret))
1448 return ret; 1468 return ret;
1449 1469
1450 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1470 ret = soc_ops.assert_hardreset(oh, &ohri);
1451 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, 1471
1452 ohri.rst_shift); 1472 return ret;
1453 else if (cpu_is_omap44xx())
1454 return omap4_prminst_assert_hardreset(ohri.rst_shift,
1455 oh->clkdm->pwrdm.ptr->prcm_partition,
1456 oh->clkdm->pwrdm.ptr->prcm_offs,
1457 oh->prcm.omap4.rstctrl_offs);
1458 else
1459 return -EINVAL;
1460} 1473}
1461 1474
1462/** 1475/**
@@ -1465,38 +1478,29 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1465 * @oh: struct omap_hwmod * 1478 * @oh: struct omap_hwmod *
1466 * @name: name of the reset line to look up and deassert 1479 * @name: name of the reset line to look up and deassert
1467 * 1480 *
1468 * Some IP like dsp, ipu or iva contain processor that require 1481 * Some IP like dsp, ipu or iva contain processor that require an HW
1469 * an HW reset line to be assert / deassert in order to enable fully 1482 * reset line to be assert / deassert in order to enable fully the IP.
1470 * the IP. 1483 * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
1484 * deasserting the hardreset line on the currently-booted SoC, or passes
1485 * along the return value from _lookup_hardreset() or the SoC's
1486 * deassert_hardreset code.
1471 */ 1487 */
1472static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) 1488static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1473{ 1489{
1474 struct omap_hwmod_rst_info ohri; 1490 struct omap_hwmod_rst_info ohri;
1475 int ret; 1491 int ret = -EINVAL;
1476 1492
1477 if (!oh) 1493 if (!oh)
1478 return -EINVAL; 1494 return -EINVAL;
1479 1495
1496 if (!soc_ops.deassert_hardreset)
1497 return -ENOSYS;
1498
1480 ret = _lookup_hardreset(oh, name, &ohri); 1499 ret = _lookup_hardreset(oh, name, &ohri);
1481 if (IS_ERR_VALUE(ret)) 1500 if (IS_ERR_VALUE(ret))
1482 return ret; 1501 return ret;
1483 1502
1484 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1503 ret = soc_ops.deassert_hardreset(oh, &ohri);
1485 ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
1486 ohri.rst_shift,
1487 ohri.st_shift);
1488 } else if (cpu_is_omap44xx()) {
1489 if (ohri.st_shift)
1490 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
1491 oh->name, name);
1492 ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
1493 oh->clkdm->pwrdm.ptr->prcm_partition,
1494 oh->clkdm->pwrdm.ptr->prcm_offs,
1495 oh->prcm.omap4.rstctrl_offs);
1496 } else {
1497 return -EINVAL;
1498 }
1499
1500 if (ret == -EBUSY) 1504 if (ret == -EBUSY)
1501 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); 1505 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
1502 1506
@@ -1509,31 +1513,28 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1509 * @oh: struct omap_hwmod * 1513 * @oh: struct omap_hwmod *
1510 * @name: name of the reset line to look up and read 1514 * @name: name of the reset line to look up and read
1511 * 1515 *
1512 * Return the state of the reset line. 1516 * Return the state of the reset line. Returns -EINVAL if @oh is
1517 * null, -ENOSYS if we have no way of reading the hardreset line
1518 * status on the currently-booted SoC, or passes along the return
1519 * value from _lookup_hardreset() or the SoC's is_hardreset_asserted
1520 * code.
1513 */ 1521 */
1514static int _read_hardreset(struct omap_hwmod *oh, const char *name) 1522static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1515{ 1523{
1516 struct omap_hwmod_rst_info ohri; 1524 struct omap_hwmod_rst_info ohri;
1517 u8 ret; 1525 u8 ret = -EINVAL;
1518 1526
1519 if (!oh) 1527 if (!oh)
1520 return -EINVAL; 1528 return -EINVAL;
1521 1529
1530 if (!soc_ops.is_hardreset_asserted)
1531 return -ENOSYS;
1532
1522 ret = _lookup_hardreset(oh, name, &ohri); 1533 ret = _lookup_hardreset(oh, name, &ohri);
1523 if (IS_ERR_VALUE(ret)) 1534 if (IS_ERR_VALUE(ret))
1524 return ret; 1535 return ret;
1525 1536
1526 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1537 return soc_ops.is_hardreset_asserted(oh, &ohri);
1527 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
1528 ohri.st_shift);
1529 } else if (cpu_is_omap44xx()) {
1530 return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
1531 oh->clkdm->pwrdm.ptr->prcm_partition,
1532 oh->clkdm->pwrdm.ptr->prcm_offs,
1533 oh->prcm.omap4.rstctrl_offs);
1534 } else {
1535 return -EINVAL;
1536 }
1537} 1538}
1538 1539
1539/** 1540/**
@@ -1571,10 +1572,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
1571{ 1572{
1572 int v; 1573 int v;
1573 1574
1574 /* The module mode does not exist prior OMAP4 */
1575 if (!cpu_is_omap44xx())
1576 return -EINVAL;
1577
1578 if (!oh->clkdm || !oh->prcm.omap4.modulemode) 1575 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
1579 return -EINVAL; 1576 return -EINVAL;
1580 1577
@@ -1698,11 +1695,17 @@ dis_opt_clks:
1698 * therefore have no OCP header registers to access. Others (like the 1695 * therefore have no OCP header registers to access. Others (like the
1699 * IVA) have idiosyncratic reset sequences. So for these relatively 1696 * IVA) have idiosyncratic reset sequences. So for these relatively
1700 * rare cases, custom reset code can be supplied in the struct 1697 * rare cases, custom reset code can be supplied in the struct
1701 * omap_hwmod_class .reset function pointer. Passes along the return 1698 * omap_hwmod_class .reset function pointer.
1702 * value from either _ocp_softreset() or the custom reset function - 1699 *
1703 * these must return -EINVAL if the hwmod cannot be reset this way or 1700 * _set_dmadisable() is called to set the DMADISABLE bit so that it
1704 * if the hwmod is in the wrong state, -ETIMEDOUT if the module did 1701 * does not prevent idling of the system. This is necessary for cases
1705 * not reset in time, or 0 upon success. 1702 * where ROMCODE/BOOTLOADER uses dma and transfers control to the
1703 * kernel without disabling dma.
1704 *
1705 * Passes along the return value from either _ocp_softreset() or the
1706 * custom reset function - these must return -EINVAL if the hwmod
1707 * cannot be reset this way or if the hwmod is in the wrong state,
1708 * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
1706 */ 1709 */
1707static int _reset(struct omap_hwmod *oh) 1710static int _reset(struct omap_hwmod *oh)
1708{ 1711{
@@ -1724,6 +1727,8 @@ static int _reset(struct omap_hwmod *oh)
1724 } 1727 }
1725 } 1728 }
1726 1729
1730 _set_dmadisable(oh);
1731
1727 /* 1732 /*
1728 * OCP_SYSCONFIG bits need to be reprogrammed after a 1733 * OCP_SYSCONFIG bits need to be reprogrammed after a
1729 * softreset. The _enable() function should be split to avoid 1734 * softreset. The _enable() function should be split to avoid
@@ -1814,9 +1819,11 @@ static int _enable(struct omap_hwmod *oh)
1814 } 1819 }
1815 1820
1816 _enable_clocks(oh); 1821 _enable_clocks(oh);
1817 _enable_module(oh); 1822 if (soc_ops.enable_module)
1823 soc_ops.enable_module(oh);
1818 1824
1819 r = _wait_target_ready(oh); 1825 r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
1826 -EINVAL;
1820 if (!r) { 1827 if (!r) {
1821 /* 1828 /*
1822 * Set the clockdomain to HW_AUTO only if the target is ready, 1829 * Set the clockdomain to HW_AUTO only if the target is ready,
@@ -1870,7 +1877,8 @@ static int _idle(struct omap_hwmod *oh)
1870 _idle_sysc(oh); 1877 _idle_sysc(oh);
1871 _del_initiator_dep(oh, mpu_oh); 1878 _del_initiator_dep(oh, mpu_oh);
1872 1879
1873 _omap4_disable_module(oh); 1880 if (soc_ops.disable_module)
1881 soc_ops.disable_module(oh);
1874 1882
1875 /* 1883 /*
1876 * The module must be in idle mode before disabling any parents 1884 * The module must be in idle mode before disabling any parents
@@ -1975,7 +1983,8 @@ static int _shutdown(struct omap_hwmod *oh)
1975 if (oh->_state == _HWMOD_STATE_ENABLED) { 1983 if (oh->_state == _HWMOD_STATE_ENABLED) {
1976 _del_initiator_dep(oh, mpu_oh); 1984 _del_initiator_dep(oh, mpu_oh);
1977 /* XXX what about the other system initiators here? dma, dsp */ 1985 /* XXX what about the other system initiators here? dma, dsp */
1978 _omap4_disable_module(oh); 1986 if (soc_ops.disable_module)
1987 soc_ops.disable_module(oh);
1979 _disable_clocks(oh); 1988 _disable_clocks(oh);
1980 if (oh->clkdm) 1989 if (oh->clkdm)
1981 clkdm_hwmod_disable(oh->clkdm, oh); 1990 clkdm_hwmod_disable(oh->clkdm, oh);
@@ -2431,6 +2440,194 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
2431 return 0; 2440 return 0;
2432} 2441}
2433 2442
2443/* Static functions intended only for use in soc_ops field function pointers */
2444
2445/**
2446 * _omap2_wait_target_ready - wait for a module to leave slave idle
2447 * @oh: struct omap_hwmod *
2448 *
2449 * Wait for a module @oh to leave slave idle. Returns 0 if the module
2450 * does not have an IDLEST bit or if the module successfully leaves
2451 * slave idle; otherwise, pass along the return value of the
2452 * appropriate *_cm*_wait_module_ready() function.
2453 */
2454static int _omap2_wait_target_ready(struct omap_hwmod *oh)
2455{
2456 if (!oh)
2457 return -EINVAL;
2458
2459 if (oh->flags & HWMOD_NO_IDLEST)
2460 return 0;
2461
2462 if (!_find_mpu_rt_port(oh))
2463 return 0;
2464
2465 /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
2466
2467 return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
2468 oh->prcm.omap2.idlest_reg_id,
2469 oh->prcm.omap2.idlest_idle_bit);
2470}
2471
2472/**
2473 * _omap4_wait_target_ready - wait for a module to leave slave idle
2474 * @oh: struct omap_hwmod *
2475 *
2476 * Wait for a module @oh to leave slave idle. Returns 0 if the module
2477 * does not have an IDLEST bit or if the module successfully leaves
2478 * slave idle; otherwise, pass along the return value of the
2479 * appropriate *_cm*_wait_module_ready() function.
2480 */
2481static int _omap4_wait_target_ready(struct omap_hwmod *oh)
2482{
2483 if (!oh || !oh->clkdm)
2484 return -EINVAL;
2485
2486 if (oh->flags & HWMOD_NO_IDLEST)
2487 return 0;
2488
2489 if (!_find_mpu_rt_port(oh))
2490 return 0;
2491
2492 /* XXX check module SIDLEMODE, hardreset status */
2493
2494 return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
2495 oh->clkdm->cm_inst,
2496 oh->clkdm->clkdm_offs,
2497 oh->prcm.omap4.clkctrl_offs);
2498}
2499
2500/**
2501 * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
2502 * @oh: struct omap_hwmod * to assert hardreset
2503 * @ohri: hardreset line data
2504 *
2505 * Call omap2_prm_assert_hardreset() with parameters extracted from
2506 * the hwmod @oh and the hardreset line data @ohri. Only intended for
2507 * use as an soc_ops function pointer. Passes along the return value
2508 * from omap2_prm_assert_hardreset(). XXX This function is scheduled
2509 * for removal when the PRM code is moved into drivers/.
2510 */
2511static int _omap2_assert_hardreset(struct omap_hwmod *oh,
2512 struct omap_hwmod_rst_info *ohri)
2513{
2514 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
2515 ohri->rst_shift);
2516}
2517
2518/**
2519 * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
2520 * @oh: struct omap_hwmod * to deassert hardreset
2521 * @ohri: hardreset line data
2522 *
2523 * Call omap2_prm_deassert_hardreset() with parameters extracted from
2524 * the hwmod @oh and the hardreset line data @ohri. Only intended for
2525 * use as an soc_ops function pointer. Passes along the return value
2526 * from omap2_prm_deassert_hardreset(). XXX This function is
2527 * scheduled for removal when the PRM code is moved into drivers/.
2528 */
2529static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
2530 struct omap_hwmod_rst_info *ohri)
2531{
2532 return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
2533 ohri->rst_shift,
2534 ohri->st_shift);
2535}
2536
2537/**
2538 * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args
2539 * @oh: struct omap_hwmod * to test hardreset
2540 * @ohri: hardreset line data
2541 *
2542 * Call omap2_prm_is_hardreset_asserted() with parameters extracted
2543 * from the hwmod @oh and the hardreset line data @ohri. Only
2544 * intended for use as an soc_ops function pointer. Passes along the
2545 * return value from omap2_prm_is_hardreset_asserted(). XXX This
2546 * function is scheduled for removal when the PRM code is moved into
2547 * drivers/.
2548 */
2549static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
2550 struct omap_hwmod_rst_info *ohri)
2551{
2552 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
2553 ohri->st_shift);
2554}
2555
2556/**
2557 * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
2558 * @oh: struct omap_hwmod * to assert hardreset
2559 * @ohri: hardreset line data
2560 *
2561 * Call omap4_prminst_assert_hardreset() with parameters extracted
2562 * from the hwmod @oh and the hardreset line data @ohri. Only
2563 * intended for use as an soc_ops function pointer. Passes along the
2564 * return value from omap4_prminst_assert_hardreset(). XXX This
2565 * function is scheduled for removal when the PRM code is moved into
2566 * drivers/.
2567 */
2568static int _omap4_assert_hardreset(struct omap_hwmod *oh,
2569 struct omap_hwmod_rst_info *ohri)
2570{
2571 if (!oh->clkdm)
2572 return -EINVAL;
2573
2574 return omap4_prminst_assert_hardreset(ohri->rst_shift,
2575 oh->clkdm->pwrdm.ptr->prcm_partition,
2576 oh->clkdm->pwrdm.ptr->prcm_offs,
2577 oh->prcm.omap4.rstctrl_offs);
2578}
2579
2580/**
2581 * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
2582 * @oh: struct omap_hwmod * to deassert hardreset
2583 * @ohri: hardreset line data
2584 *
2585 * Call omap4_prminst_deassert_hardreset() with parameters extracted
2586 * from the hwmod @oh and the hardreset line data @ohri. Only
2587 * intended for use as an soc_ops function pointer. Passes along the
2588 * return value from omap4_prminst_deassert_hardreset(). XXX This
2589 * function is scheduled for removal when the PRM code is moved into
2590 * drivers/.
2591 */
2592static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
2593 struct omap_hwmod_rst_info *ohri)
2594{
2595 if (!oh->clkdm)
2596 return -EINVAL;
2597
2598 if (ohri->st_shift)
2599 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
2600 oh->name, ohri->name);
2601 return omap4_prminst_deassert_hardreset(ohri->rst_shift,
2602 oh->clkdm->pwrdm.ptr->prcm_partition,
2603 oh->clkdm->pwrdm.ptr->prcm_offs,
2604 oh->prcm.omap4.rstctrl_offs);
2605}
2606
2607/**
2608 * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args
2609 * @oh: struct omap_hwmod * to test hardreset
2610 * @ohri: hardreset line data
2611 *
2612 * Call omap4_prminst_is_hardreset_asserted() with parameters
2613 * extracted from the hwmod @oh and the hardreset line data @ohri.
2614 * Only intended for use as an soc_ops function pointer. Passes along
2615 * the return value from omap4_prminst_is_hardreset_asserted(). XXX
2616 * This function is scheduled for removal when the PRM code is moved
2617 * into drivers/.
2618 */
2619static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
2620 struct omap_hwmod_rst_info *ohri)
2621{
2622 if (!oh->clkdm)
2623 return -EINVAL;
2624
2625 return omap4_prminst_is_hardreset_asserted(ohri->rst_shift,
2626 oh->clkdm->pwrdm.ptr->prcm_partition,
2627 oh->clkdm->pwrdm.ptr->prcm_offs,
2628 oh->prcm.omap4.rstctrl_offs);
2629}
2630
2434/* Public functions */ 2631/* Public functions */
2435 2632
2436u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) 2633u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -2563,12 +2760,18 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
2563 * 2760 *
2564 * Intended to be called early in boot before the clock framework is 2761 * Intended to be called early in boot before the clock framework is
2565 * initialized. If @ois is not null, will register all omap_hwmods 2762 * initialized. If @ois is not null, will register all omap_hwmods
2566 * listed in @ois that are valid for this chip. Returns 0. 2763 * listed in @ois that are valid for this chip. Returns -EINVAL if
2764 * omap_hwmod_init() hasn't been called before calling this function,
2765 * -ENOMEM if the link memory area can't be allocated, or 0 upon
2766 * success.
2567 */ 2767 */
2568int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) 2768int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
2569{ 2769{
2570 int r, i; 2770 int r, i;
2571 2771
2772 if (!inited)
2773 return -EINVAL;
2774
2572 if (!ois) 2775 if (!ois)
2573 return 0; 2776 return 0;
2574 2777
@@ -3401,3 +3604,32 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
3401 3604
3402 return 0; 3605 return 0;
3403} 3606}
3607
3608/**
3609 * omap_hwmod_init - initialize the hwmod code
3610 *
3611 * Sets up some function pointers needed by the hwmod code to operate on the
3612 * currently-booted SoC. Intended to be called once during kernel init
3613 * before any hwmods are registered. No return value.
3614 */
3615void __init omap_hwmod_init(void)
3616{
3617 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3618 soc_ops.wait_target_ready = _omap2_wait_target_ready;
3619 soc_ops.assert_hardreset = _omap2_assert_hardreset;
3620 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3621 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3622 } else if (cpu_is_omap44xx()) {
3623 soc_ops.enable_module = _omap4_enable_module;
3624 soc_ops.disable_module = _omap4_disable_module;
3625 soc_ops.wait_target_ready = _omap4_wait_target_ready;
3626 soc_ops.assert_hardreset = _omap4_assert_hardreset;
3627 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
3628 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3629 soc_ops.init_clkdm = _init_clkdm;
3630 } else {
3631 WARN(1, "omap_hwmod: unknown SoC type\n");
3632 }
3633
3634 inited = true;
3635}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a7640d1b215e..50cfab61b0e2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -192,6 +192,11 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
192 .name = "mcbsp", 192 .name = "mcbsp",
193}; 193};
194 194
195static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
196 { .role = "pad_fck", .clk = "mcbsp_clks" },
197 { .role = "prcm_fck", .clk = "func_96m_ck" },
198};
199
195/* mcbsp1 */ 200/* mcbsp1 */
196static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { 201static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
197 { .name = "tx", .irq = 59 }, 202 { .name = "tx", .irq = 59 },
@@ -214,6 +219,8 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
214 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 219 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
215 }, 220 },
216 }, 221 },
222 .opt_clks = mcbsp_opt_clks,
223 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
217}; 224};
218 225
219/* mcbsp2 */ 226/* mcbsp2 */
@@ -238,6 +245,8 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
238 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 245 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
239 }, 246 },
240 }, 247 },
248 .opt_clks = mcbsp_opt_clks,
249 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
241}; 250};
242 251
243static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { 252static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
@@ -585,5 +594,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
585 594
586int __init omap2420_hwmod_init(void) 595int __init omap2420_hwmod_init(void)
587{ 596{
597 omap_hwmod_init();
588 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); 598 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
589} 599}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4d7264981230..58b5bc196d32 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -296,6 +296,11 @@ static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
296 .rev = MCBSP_CONFIG_TYPE2, 296 .rev = MCBSP_CONFIG_TYPE2,
297}; 297};
298 298
299static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
300 { .role = "pad_fck", .clk = "mcbsp_clks" },
301 { .role = "prcm_fck", .clk = "func_96m_ck" },
302};
303
299/* mcbsp1 */ 304/* mcbsp1 */
300static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { 305static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
301 { .name = "tx", .irq = 59 }, 306 { .name = "tx", .irq = 59 },
@@ -320,6 +325,8 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
320 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 325 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
321 }, 326 },
322 }, 327 },
328 .opt_clks = mcbsp_opt_clks,
329 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
323}; 330};
324 331
325/* mcbsp2 */ 332/* mcbsp2 */
@@ -345,6 +352,8 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
345 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 352 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
346 }, 353 },
347 }, 354 },
355 .opt_clks = mcbsp_opt_clks,
356 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
348}; 357};
349 358
350/* mcbsp3 */ 359/* mcbsp3 */
@@ -370,6 +379,8 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
370 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 379 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
371 }, 380 },
372 }, 381 },
382 .opt_clks = mcbsp_opt_clks,
383 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
373}; 384};
374 385
375/* mcbsp4 */ 386/* mcbsp4 */
@@ -401,6 +412,8 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
401 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 412 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
402 }, 413 },
403 }, 414 },
415 .opt_clks = mcbsp_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
404}; 417};
405 418
406/* mcbsp5 */ 419/* mcbsp5 */
@@ -432,6 +445,8 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
432 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 445 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
433 }, 446 },
434 }, 447 },
448 .opt_clks = mcbsp_opt_clks,
449 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
435}; 450};
436 451
437/* MMC/SD/SDIO common */ 452/* MMC/SD/SDIO common */
@@ -938,5 +953,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
938 953
939int __init omap2430_hwmod_init(void) 954int __init omap2430_hwmod_init(void)
940{ 955{
956 omap_hwmod_init();
941 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); 957 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
942} 958}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 83eafd96ecaa..afad69c6ba6e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -68,7 +68,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
68struct omap_hwmod_class omap2xxx_timer_hwmod_class = { 68struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
69 .name = "timer", 69 .name = "timer",
70 .sysc = &omap2xxx_timer_sysc, 70 .sysc = &omap2xxx_timer_sysc,
71 .rev = OMAP_TIMER_IP_VERSION_1,
72}; 71};
73 72
74/* 73/*
@@ -257,7 +256,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
257 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, 256 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
258 }, 257 },
259 }, 258 },
260 .dev_attr = &capability_alwon_dev_attr,
261 .class = &omap2xxx_timer_hwmod_class, 259 .class = &omap2xxx_timer_hwmod_class,
262}; 260};
263 261
@@ -276,7 +274,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
276 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 274 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
277 }, 275 },
278 }, 276 },
279 .dev_attr = &capability_alwon_dev_attr,
280 .class = &omap2xxx_timer_hwmod_class, 277 .class = &omap2xxx_timer_hwmod_class,
281}; 278};
282 279
@@ -295,7 +292,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
295 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, 292 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
296 }, 293 },
297 }, 294 },
298 .dev_attr = &capability_alwon_dev_attr,
299 .class = &omap2xxx_timer_hwmod_class, 295 .class = &omap2xxx_timer_hwmod_class,
300}; 296};
301 297
@@ -314,7 +310,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
314 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 310 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
315 }, 311 },
316 }, 312 },
317 .dev_attr = &capability_alwon_dev_attr,
318 .class = &omap2xxx_timer_hwmod_class, 313 .class = &omap2xxx_timer_hwmod_class,
319}; 314};
320 315
@@ -333,7 +328,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
333 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 328 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
334 }, 329 },
335 }, 330 },
336 .dev_attr = &capability_alwon_dev_attr,
337 .class = &omap2xxx_timer_hwmod_class, 331 .class = &omap2xxx_timer_hwmod_class,
338}; 332};
339 333
@@ -352,7 +346,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
352 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 346 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
353 }, 347 },
354 }, 348 },
355 .dev_attr = &capability_alwon_dev_attr,
356 .class = &omap2xxx_timer_hwmod_class, 349 .class = &omap2xxx_timer_hwmod_class,
357}; 350};
358 351
@@ -371,7 +364,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
371 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 364 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
372 }, 365 },
373 }, 366 },
374 .dev_attr = &capability_alwon_dev_attr,
375 .class = &omap2xxx_timer_hwmod_class, 367 .class = &omap2xxx_timer_hwmod_class,
376}; 368};
377 369
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index b26d3c9bca16..6491e057d9ce 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -129,7 +129,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
129static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { 129static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
130 .name = "timer", 130 .name = "timer",
131 .sysc = &omap3xxx_timer_1ms_sysc, 131 .sysc = &omap3xxx_timer_1ms_sysc,
132 .rev = OMAP_TIMER_IP_VERSION_1,
133}; 132};
134 133
135static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 134static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
@@ -145,12 +144,11 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
145static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 144static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
146 .name = "timer", 145 .name = "timer",
147 .sysc = &omap3xxx_timer_sysc, 146 .sysc = &omap3xxx_timer_sysc,
148 .rev = OMAP_TIMER_IP_VERSION_1,
149}; 147};
150 148
151/* secure timers dev attribute */ 149/* secure timers dev attribute */
152static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 150static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
153 .timer_capability = OMAP_TIMER_SECURE, 151 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
154}; 152};
155 153
156/* always-on timers dev attribute */ 154/* always-on timers dev attribute */
@@ -195,7 +193,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
195 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 193 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
196 }, 194 },
197 }, 195 },
198 .dev_attr = &capability_alwon_dev_attr,
199 .class = &omap3xxx_timer_1ms_hwmod_class, 196 .class = &omap3xxx_timer_1ms_hwmod_class,
200}; 197};
201 198
@@ -213,7 +210,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
213 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 210 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
214 }, 211 },
215 }, 212 },
216 .dev_attr = &capability_alwon_dev_attr,
217 .class = &omap3xxx_timer_hwmod_class, 213 .class = &omap3xxx_timer_hwmod_class,
218}; 214};
219 215
@@ -231,7 +227,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
231 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 227 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
232 }, 228 },
233 }, 229 },
234 .dev_attr = &capability_alwon_dev_attr,
235 .class = &omap3xxx_timer_hwmod_class, 230 .class = &omap3xxx_timer_hwmod_class,
236}; 231};
237 232
@@ -249,7 +244,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
249 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 244 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
250 }, 245 },
251 }, 246 },
252 .dev_attr = &capability_alwon_dev_attr,
253 .class = &omap3xxx_timer_hwmod_class, 247 .class = &omap3xxx_timer_hwmod_class,
254}; 248};
255 249
@@ -267,7 +261,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
267 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 261 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
268 }, 262 },
269 }, 263 },
270 .dev_attr = &capability_alwon_dev_attr,
271 .class = &omap3xxx_timer_hwmod_class, 264 .class = &omap3xxx_timer_hwmod_class,
272}; 265};
273 266
@@ -285,7 +278,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
285 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 278 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
286 }, 279 },
287 }, 280 },
288 .dev_attr = &capability_alwon_dev_attr,
289 .class = &omap3xxx_timer_hwmod_class, 281 .class = &omap3xxx_timer_hwmod_class,
290}; 282};
291 283
@@ -1074,6 +1066,17 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1074 .rev = MCBSP_CONFIG_TYPE3, 1066 .rev = MCBSP_CONFIG_TYPE3,
1075}; 1067};
1076 1068
1069/* McBSP functional clock mapping */
1070static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1071 { .role = "pad_fck", .clk = "mcbsp_clks" },
1072 { .role = "prcm_fck", .clk = "core_96m_fck" },
1073};
1074
1075static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1076 { .role = "pad_fck", .clk = "mcbsp_clks" },
1077 { .role = "prcm_fck", .clk = "per_96m_fck" },
1078};
1079
1077/* mcbsp1 */ 1080/* mcbsp1 */
1078static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 1081static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1079 { .name = "common", .irq = 16 }, 1082 { .name = "common", .irq = 16 },
@@ -1097,6 +1100,8 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1097 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1100 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1098 }, 1101 },
1099 }, 1102 },
1103 .opt_clks = mcbsp15_opt_clks,
1104 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1100}; 1105};
1101 1106
1102/* mcbsp2 */ 1107/* mcbsp2 */
@@ -1126,6 +1131,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1126 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1131 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1127 }, 1132 },
1128 }, 1133 },
1134 .opt_clks = mcbsp234_opt_clks,
1135 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1129 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1136 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1130}; 1137};
1131 1138
@@ -1156,6 +1163,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1156 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1163 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1157 }, 1164 },
1158 }, 1165 },
1166 .opt_clks = mcbsp234_opt_clks,
1167 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1159 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1168 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1160}; 1169};
1161 1170
@@ -1188,6 +1197,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1188 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1197 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1189 }, 1198 },
1190 }, 1199 },
1200 .opt_clks = mcbsp234_opt_clks,
1201 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1191}; 1202};
1192 1203
1193/* mcbsp5 */ 1204/* mcbsp5 */
@@ -1219,6 +1230,8 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1219 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1230 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1220 }, 1231 },
1221 }, 1232 },
1233 .opt_clks = mcbsp15_opt_clks,
1234 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1222}; 1235};
1223 1236
1224/* 'mcbsp sidetone' class */ 1237/* 'mcbsp sidetone' class */
@@ -3283,6 +3296,8 @@ int __init omap3xxx_hwmod_init(void)
3283 struct omap_hwmod_ocp_if **h = NULL; 3296 struct omap_hwmod_ocp_if **h = NULL;
3284 unsigned int rev; 3297 unsigned int rev;
3285 3298
3299 omap_hwmod_init();
3300
3286 /* Register hwmod links common to all OMAP3 */ 3301 /* Register hwmod links common to all OMAP3 */
3287 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); 3302 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3288 if (r < 0) 3303 if (r < 0)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 950454a3fa31..1b1d04141c3d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -393,8 +393,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
393 .rev_offs = 0x0000, 393 .rev_offs = 0x0000,
394 .sysc_offs = 0x0004, 394 .sysc_offs = 0x0004,
395 .sysc_flags = SYSC_HAS_SIDLEMODE, 395 .sysc_flags = SYSC_HAS_SIDLEMODE,
396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 396 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
397 SIDLE_SMART_WKUP),
398 .sysc_fields = &omap_hwmod_sysc_type1, 397 .sysc_fields = &omap_hwmod_sysc_type1,
399}; 398};
400 399
@@ -854,6 +853,11 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
854 .name = "dss_hdmi", 853 .name = "dss_hdmi",
855 .class = &omap44xx_hdmi_hwmod_class, 854 .class = &omap44xx_hdmi_hwmod_class,
856 .clkdm_name = "l3_dss_clkdm", 855 .clkdm_name = "l3_dss_clkdm",
856 /*
857 * HDMI audio requires to use no-idle mode. Hence,
858 * set idle mode by software.
859 */
860 .flags = HWMOD_SWSUP_SIDLE,
857 .mpu_irqs = omap44xx_dss_hdmi_irqs, 861 .mpu_irqs = omap44xx_dss_hdmi_irqs,
858 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 862 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
859 .main_clk = "dss_48mhz_clk", 863 .main_clk = "dss_48mhz_clk",
@@ -2540,14 +2544,12 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2540static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { 2544static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2541 .name = "cm_core_aon", 2545 .name = "cm_core_aon",
2542 .class = &omap44xx_prcm_hwmod_class, 2546 .class = &omap44xx_prcm_hwmod_class,
2543 .clkdm_name = "cm_clkdm",
2544}; 2547};
2545 2548
2546/* cm_core */ 2549/* cm_core */
2547static struct omap_hwmod omap44xx_cm_core_hwmod = { 2550static struct omap_hwmod omap44xx_cm_core_hwmod = {
2548 .name = "cm_core", 2551 .name = "cm_core",
2549 .class = &omap44xx_prcm_hwmod_class, 2552 .class = &omap44xx_prcm_hwmod_class,
2550 .clkdm_name = "cm_clkdm",
2551}; 2553};
2552 2554
2553/* prm */ 2555/* prm */
@@ -2564,7 +2566,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2564static struct omap_hwmod omap44xx_prm_hwmod = { 2566static struct omap_hwmod omap44xx_prm_hwmod = {
2565 .name = "prm", 2567 .name = "prm",
2566 .class = &omap44xx_prcm_hwmod_class, 2568 .class = &omap44xx_prcm_hwmod_class,
2567 .clkdm_name = "prm_clkdm",
2568 .mpu_irqs = omap44xx_prm_irqs, 2569 .mpu_irqs = omap44xx_prm_irqs,
2569 .rst_lines = omap44xx_prm_resets, 2570 .rst_lines = omap44xx_prm_resets,
2570 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), 2571 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
@@ -2943,7 +2944,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
2943 .modulemode = MODULEMODE_SWCTRL, 2944 .modulemode = MODULEMODE_SWCTRL,
2944 }, 2945 },
2945 }, 2946 },
2946 .dev_attr = &capability_alwon_dev_attr,
2947}; 2947};
2948 2948
2949/* timer3 */ 2949/* timer3 */
@@ -2965,7 +2965,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
2965 .modulemode = MODULEMODE_SWCTRL, 2965 .modulemode = MODULEMODE_SWCTRL,
2966 }, 2966 },
2967 }, 2967 },
2968 .dev_attr = &capability_alwon_dev_attr,
2969}; 2968};
2970 2969
2971/* timer4 */ 2970/* timer4 */
@@ -2987,7 +2986,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
2987 .modulemode = MODULEMODE_SWCTRL, 2986 .modulemode = MODULEMODE_SWCTRL,
2988 }, 2987 },
2989 }, 2988 },
2990 .dev_attr = &capability_alwon_dev_attr,
2991}; 2989};
2992 2990
2993/* timer5 */ 2991/* timer5 */
@@ -3009,7 +3007,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
3009 .modulemode = MODULEMODE_SWCTRL, 3007 .modulemode = MODULEMODE_SWCTRL,
3010 }, 3008 },
3011 }, 3009 },
3012 .dev_attr = &capability_alwon_dev_attr,
3013}; 3010};
3014 3011
3015/* timer6 */ 3012/* timer6 */
@@ -3032,7 +3029,6 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
3032 .modulemode = MODULEMODE_SWCTRL, 3029 .modulemode = MODULEMODE_SWCTRL,
3033 }, 3030 },
3034 }, 3031 },
3035 .dev_attr = &capability_alwon_dev_attr,
3036}; 3032};
3037 3033
3038/* timer7 */ 3034/* timer7 */
@@ -3054,7 +3050,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
3054 .modulemode = MODULEMODE_SWCTRL, 3050 .modulemode = MODULEMODE_SWCTRL,
3055 }, 3051 },
3056 }, 3052 },
3057 .dev_attr = &capability_alwon_dev_attr,
3058}; 3053};
3059 3054
3060/* timer8 */ 3055/* timer8 */
@@ -6144,6 +6139,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6144 6139
6145int __init omap44xx_hwmod_init(void) 6140int __init omap44xx_hwmod_init(void)
6146{ 6141{
6142 omap_hwmod_init();
6147 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); 6143 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6148} 6144}
6149 6145
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 51e5418899fb..9f1ccdc8cc8c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -47,6 +47,16 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
47 .midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT, 47 .midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT,
48 .sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT, 48 .sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT,
49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, 49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
50 .dmadisable_shift = SYSC_TYPE2_DMADISABLE_SHIFT,
51};
52
53/**
54 * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
55 * Used by some IPs on AM33xx
56 */
57struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
58 .midle_shift = SYSC_TYPE3_MIDLEMODE_SHIFT,
59 .sidle_shift = SYSC_TYPE3_SIDLEMODE_SHIFT,
50}; 60};
51 61
52struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = { 62struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index a05a62f9ee5b..acc216491b8a 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -155,10 +155,11 @@ static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
155 u8 multi = error & L3_ERROR_LOG_MULTI; 155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr); 156 u32 address = omap3_l3_decode_addr(error_addr);
157 157
158 WARN(true, "%s seen by %s %s at address %x\n", 158 pr_err("%s seen by %s %s at address %x\n",
159 omap3_l3_code_string(code), 159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid), 160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "", address); 161 multi ? "Multiple Errors" : "", address);
162 WARN_ON(1);
162 163
163 return IRQ_HANDLED; 164 return IRQ_HANDLED;
164} 165}
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 4c90477e6f82..d52651a05daa 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -239,21 +239,15 @@ void am35x_set_mode(u8 musb_mode)
239 239
240 devconf2 &= ~CONF2_OTGMODE; 240 devconf2 &= ~CONF2_OTGMODE;
241 switch (musb_mode) { 241 switch (musb_mode) {
242#ifdef CONFIG_USB_MUSB_HDRC_HCD
243 case MUSB_HOST: /* Force VBUS valid, ID = 0 */ 242 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
244 devconf2 |= CONF2_FORCE_HOST; 243 devconf2 |= CONF2_FORCE_HOST;
245 break; 244 break;
246#endif
247#ifdef CONFIG_USB_GADGET_MUSB_HDRC
248 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ 245 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
249 devconf2 |= CONF2_FORCE_DEVICE; 246 devconf2 |= CONF2_FORCE_DEVICE;
250 break; 247 break;
251#endif
252#ifdef CONFIG_USB_MUSB_OTG
253 case MUSB_OTG: /* Don't override the VBUS/ID comparators */ 248 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
254 devconf2 |= CONF2_NO_OVERRIDE; 249 devconf2 |= CONF2_NO_OVERRIDE;
255 break; 250 break;
256#endif
257 default: 251 default:
258 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); 252 pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
259 } 253 }
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a34023d0ca7c..3a595e899724 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -724,6 +724,7 @@ int __init omap3_pm_init(void)
724 ret = request_irq(omap_prcm_event_to_irq("io"), 724 ret = request_irq(omap_prcm_event_to_irq("io"),
725 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", 725 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
726 omap3_pm_init); 726 omap3_pm_init);
727 enable_irq(omap_prcm_event_to_irq("io"));
727 728
728 if (ret) { 729 if (ret) {
729 pr_err("pm: Failed to request pm_io irq\n"); 730 pr_err("pm: Failed to request pm_io irq\n");
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96114901b932..2f963f702a05 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -526,7 +526,8 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
526 * 526 *
527 * Return the powerdomain @pwrdm's current power state. Returns -EINVAL 527 * Return the powerdomain @pwrdm's current power state. Returns -EINVAL
528 * if the powerdomain pointer is null or returns the current power state 528 * if the powerdomain pointer is null or returns the current power state
529 * upon success. 529 * upon success. Note that if the power domain only supports the ON state
530 * then just return ON as the current state.
530 */ 531 */
531int pwrdm_read_pwrst(struct powerdomain *pwrdm) 532int pwrdm_read_pwrst(struct powerdomain *pwrdm)
532{ 533{
@@ -535,6 +536,9 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm)
535 if (!pwrdm) 536 if (!pwrdm)
536 return -EINVAL; 537 return -EINVAL;
537 538
539 if (pwrdm->pwrsts == PWRSTS_ON)
540 return PWRDM_POWER_ON;
541
538 if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst) 542 if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst)
539 ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm); 543 ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm);
540 544
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 480f40a5ee42..28cbfb2b5733 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -35,6 +35,7 @@
35#include "prm2xxx_3xxx.h" 35#include "prm2xxx_3xxx.h"
36#include "prm44xx.h" 36#include "prm44xx.h"
37#include "prminst44xx.h" 37#include "prminst44xx.h"
38#include "cminst44xx.h"
38#include "prm-regbits-24xx.h" 39#include "prm-regbits-24xx.h"
39#include "prm-regbits-44xx.h" 40#include "prm-regbits-44xx.h"
40#include "control.h" 41#include "control.h"
@@ -164,3 +165,25 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
164 omap_cm_base_init(); 165 omap_cm_base_init();
165 } 166 }
166} 167}
168
169/*
170 * Stubbed functions so that common files continue to build when
171 * custom builds are used
172 * XXX These are temporary and should be removed at the earliest possible
173 * opportunity
174 */
175int __weak omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
176 u16 clkctrl_offs)
177{
178 return 0;
179}
180
181void __weak omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
182 s16 cdoffs, u16 clkctrl_offs)
183{
184}
185
186void __weak omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
187 u16 clkctrl_offs)
188{
189}
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9ce765407ad5..21cb74003a56 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -15,6 +15,7 @@
15#include <linux/errno.h> 15#include <linux/errno.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/irq.h>
18 19
19#include "common.h" 20#include "common.h"
20#include <plat/cpu.h> 21#include <plat/cpu.h>
@@ -303,8 +304,15 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
303 304
304static int __init omap3xxx_prcm_init(void) 305static int __init omap3xxx_prcm_init(void)
305{ 306{
306 if (cpu_is_omap34xx()) 307 int ret = 0;
307 return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); 308
308 return 0; 309 if (cpu_is_omap34xx()) {
310 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
311 if (!ret)
312 irq_set_status_flags(omap_prcm_event_to_irq("io"),
313 IRQ_NOAUTOEN);
314 }
315
316 return ret;
309} 317}
310subsys_initcall(omap3xxx_prcm_init); 318subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 70ac2a19dc5f..f7bb57fff416 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -228,68 +228,6 @@
228 228
229 229
230#ifndef __ASSEMBLER__ 230#ifndef __ASSEMBLER__
231/*
232 * Stub omap2xxx/omap3xxx functions so that common files
233 * continue to build when custom builds are used
234 */
235#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
236 defined(CONFIG_ARCH_OMAP3))
237static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
238{
239 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
240 "not suppose to be used on omap4\n");
241 return 0;
242}
243static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
244{
245 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
246 "not suppose to be used on omap4\n");
247}
248static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
249 s16 module, s16 idx)
250{
251 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
252 "not suppose to be used on omap4\n");
253 return 0;
254}
255static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
256{
257 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
258 "not suppose to be used on omap4\n");
259 return 0;
260}
261static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
262{
263 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
264 "not suppose to be used on omap4\n");
265 return 0;
266}
267static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
268{
269 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
270 "not suppose to be used on omap4\n");
271 return 0;
272}
273static inline int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
274{
275 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
276 "not suppose to be used on omap4\n");
277 return 0;
278}
279static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
280{
281 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
282 "not suppose to be used on omap4\n");
283 return 0;
284}
285static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
286 u8 st_shift)
287{
288 WARN(1, "prm: omap2xxx/omap3xxx specific function and "
289 "not suppose to be used on omap4\n");
290 return 0;
291}
292#else
293/* Power/reset management domain register get/set */ 231/* Power/reset management domain register get/set */
294extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); 232extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
295extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); 233extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
@@ -320,9 +258,6 @@ extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
320extern void omap3xxx_prm_ocp_barrier(void); 258extern void omap3xxx_prm_ocp_barrier(void);
321extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask); 259extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
322extern void omap3xxx_prm_restore_irqen(u32 *saved_mask); 260extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
323
324#endif /* CONFIG_ARCH_OMAP4 */
325
326#endif 261#endif
327 262
328/* 263/*
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index dfe00ddb5c60..663ade3b2f45 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -319,3 +319,65 @@ err:
319 omap_prcm_irq_cleanup(); 319 omap_prcm_irq_cleanup();
320 return -ENOMEM; 320 return -ENOMEM;
321} 321}
322
323/*
324 * Stubbed functions so that common files continue to build when
325 * custom builds are used
326 * XXX These are temporary and should be removed at the earliest possible
327 * opportunity
328 */
329u32 __weak omap2_prm_read_mod_reg(s16 module, u16 idx)
330{
331 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
332 return 0;
333}
334
335void __weak omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
336{
337 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
338}
339
340u32 __weak omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
341 s16 module, s16 idx)
342{
343 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
344 return 0;
345}
346
347u32 __weak omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
348{
349 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
350 return 0;
351}
352
353u32 __weak omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
354{
355 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
356 return 0;
357}
358
359u32 __weak omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
360{
361 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
362 return 0;
363}
364
365int __weak omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
366{
367 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
368 return 0;
369}
370
371int __weak omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
372{
373 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
374 return 0;
375}
376
377int __weak omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
378 u8 st_shift)
379{
380 WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
381 return 0;
382}
383
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 292d4aaca068..c1b93c752d70 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -57,6 +57,7 @@ struct omap_uart_state {
57 57
58 struct list_head node; 58 struct list_head node;
59 struct omap_hwmod *oh; 59 struct omap_hwmod *oh;
60 struct omap_device_pad default_omap_uart_pads[2];
60}; 61};
61 62
62static LIST_HEAD(uart_list); 63static LIST_HEAD(uart_list);
@@ -126,11 +127,70 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
126#endif /* CONFIG_PM */ 127#endif /* CONFIG_PM */
127 128
128#ifdef CONFIG_OMAP_MUX 129#ifdef CONFIG_OMAP_MUX
129static void omap_serial_fill_default_pads(struct omap_board_data *bdata) 130
131#define OMAP_UART_DEFAULT_PAD_NAME_LEN 28
132static char rx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN],
133 tx_pad_name[OMAP_UART_DEFAULT_PAD_NAME_LEN] __initdata;
134
135static void __init
136omap_serial_fill_uart_tx_rx_pads(struct omap_board_data *bdata,
137 struct omap_uart_state *uart)
138{
139 uart->default_omap_uart_pads[0].name = rx_pad_name;
140 uart->default_omap_uart_pads[0].flags = OMAP_DEVICE_PAD_REMUX |
141 OMAP_DEVICE_PAD_WAKEUP;
142 uart->default_omap_uart_pads[0].enable = OMAP_PIN_INPUT |
143 OMAP_MUX_MODE0;
144 uart->default_omap_uart_pads[0].idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0;
145 uart->default_omap_uart_pads[1].name = tx_pad_name;
146 uart->default_omap_uart_pads[1].enable = OMAP_PIN_OUTPUT |
147 OMAP_MUX_MODE0;
148 bdata->pads = uart->default_omap_uart_pads;
149 bdata->pads_cnt = ARRAY_SIZE(uart->default_omap_uart_pads);
150}
151
152static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
153 struct omap_uart_state *uart)
130{ 154{
155 struct omap_mux_partition *tx_partition = NULL, *rx_partition = NULL;
156 struct omap_mux *rx_mux = NULL, *tx_mux = NULL;
157 char *rx_fmt, *tx_fmt;
158 int uart_nr = bdata->id + 1;
159
160 if (bdata->id != 2) {
161 rx_fmt = "uart%d_rx.uart%d_rx";
162 tx_fmt = "uart%d_tx.uart%d_tx";
163 } else {
164 rx_fmt = "uart%d_rx_irrx.uart%d_rx_irrx";
165 tx_fmt = "uart%d_tx_irtx.uart%d_tx_irtx";
166 }
167
168 snprintf(rx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, rx_fmt,
169 uart_nr, uart_nr);
170 snprintf(tx_pad_name, OMAP_UART_DEFAULT_PAD_NAME_LEN, tx_fmt,
171 uart_nr, uart_nr);
172
173 if (omap_mux_get_by_name(rx_pad_name, &rx_partition, &rx_mux) >= 0 &&
174 omap_mux_get_by_name
175 (tx_pad_name, &tx_partition, &tx_mux) >= 0) {
176 u16 tx_mode, rx_mode;
177
178 tx_mode = omap_mux_read(tx_partition, tx_mux->reg_offset);
179 rx_mode = omap_mux_read(rx_partition, rx_mux->reg_offset);
180
181 /*
182 * Check if uart is used in default tx/rx mode i.e. in mux mode0
183 * if yes then configure rx pin for wake up capability
184 */
185 if (OMAP_MODE_UART(rx_mode) && OMAP_MODE_UART(tx_mode))
186 omap_serial_fill_uart_tx_rx_pads(bdata, uart);
187 }
131} 188}
132#else 189#else
133static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} 190static void __init omap_serial_check_wakeup(struct omap_board_data *bdata,
191 struct omap_uart_state *uart)
192{
193}
134#endif 194#endif
135 195
136static char *cmdline_find_option(char *str) 196static char *cmdline_find_option(char *str)
@@ -287,8 +347,7 @@ void __init omap_serial_board_init(struct omap_uart_port_info *info)
287 bdata.pads = NULL; 347 bdata.pads = NULL;
288 bdata.pads_cnt = 0; 348 bdata.pads_cnt = 0;
289 349
290 if (cpu_is_omap44xx() || cpu_is_omap34xx()) 350 omap_serial_check_wakeup(&bdata, uart);
291 omap_serial_fill_default_pads(&bdata);
292 351
293 if (!info) 352 if (!info)
294 omap_serial_init_port(&bdata, NULL); 353 omap_serial_init_port(&bdata, NULL);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index ea6a0eb13f05..b5b5d92acd9d 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -69,11 +69,6 @@
69#define OMAP3_SECURE_TIMER 1 69#define OMAP3_SECURE_TIMER 1
70#endif 70#endif
71 71
72/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
73#define MAX_GPTIMER_ID 12
74
75static u32 sys_timer_reserved;
76
77/* Clockevent code */ 72/* Clockevent code */
78 73
79static struct omap_dm_timer clkev; 74static struct omap_dm_timer clkev;
@@ -180,7 +175,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
180 175
181 omap_hwmod_enable(oh); 176 omap_hwmod_enable(oh);
182 177
183 sys_timer_reserved |= (1 << (gptimer_id - 1)); 178 if (omap_dm_timer_reserve_systimer(gptimer_id))
179 return -ENODEV;
184 180
185 if (gptimer_id != 12) { 181 if (gptimer_id != 12) {
186 struct clk *src; 182 struct clk *src;
@@ -399,66 +395,6 @@ OMAP_SYS_TIMER(4)
399#endif 395#endif
400 396
401/** 397/**
402 * omap2_dm_timer_set_src - change the timer input clock source
403 * @pdev: timer platform device pointer
404 * @source: array index of parent clock source
405 */
406static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
407{
408 int ret;
409 struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
410 struct clk *fclk, *parent;
411 char *parent_name = NULL;
412
413 fclk = clk_get(&pdev->dev, "fck");
414 if (IS_ERR_OR_NULL(fclk)) {
415 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
416 __func__, __LINE__);
417 return -EINVAL;
418 }
419
420 switch (source) {
421 case OMAP_TIMER_SRC_SYS_CLK:
422 parent_name = "sys_ck";
423 break;
424
425 case OMAP_TIMER_SRC_32_KHZ:
426 parent_name = "32k_ck";
427 break;
428
429 case OMAP_TIMER_SRC_EXT_CLK:
430 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
431 parent_name = "alt_ck";
432 break;
433 }
434 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
435 __func__, __LINE__);
436 clk_put(fclk);
437 return -EINVAL;
438 }
439
440 parent = clk_get(&pdev->dev, parent_name);
441 if (IS_ERR_OR_NULL(parent)) {
442 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
443 __func__, __LINE__, parent_name);
444 clk_put(fclk);
445 return -EINVAL;
446 }
447
448 ret = clk_set_parent(fclk, parent);
449 if (IS_ERR_VALUE(ret)) {
450 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
451 __func__, parent_name);
452 ret = -EINVAL;
453 }
454
455 clk_put(parent);
456 clk_put(fclk);
457
458 return ret;
459}
460
461/**
462 * omap_timer_init - build and register timer device with an 398 * omap_timer_init - build and register timer device with an
463 * associated timer hwmod 399 * associated timer hwmod
464 * @oh: timer hwmod pointer to be used to build timer device 400 * @oh: timer hwmod pointer to be used to build timer device
@@ -478,7 +414,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
478 struct dmtimer_platform_data *pdata; 414 struct dmtimer_platform_data *pdata;
479 struct platform_device *pdev; 415 struct platform_device *pdev;
480 struct omap_timer_capability_dev_attr *timer_dev_attr; 416 struct omap_timer_capability_dev_attr *timer_dev_attr;
481 struct powerdomain *pwrdm;
482 417
483 pr_debug("%s: %s\n", __func__, oh->name); 418 pr_debug("%s: %s\n", __func__, oh->name);
484 419
@@ -506,18 +441,9 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
506 */ 441 */
507 sscanf(oh->name, "timer%2d", &id); 442 sscanf(oh->name, "timer%2d", &id);
508 443
509 pdata->set_timer_src = omap2_dm_timer_set_src; 444 if (timer_dev_attr)
510 pdata->timer_ip_version = oh->class->rev; 445 pdata->timer_capability = timer_dev_attr->timer_capability;
511
512 /* Mark clocksource and clockevent timers as reserved */
513 if ((sys_timer_reserved >> (id - 1)) & 0x1)
514 pdata->reserved = 1;
515 446
516 pwrdm = omap_hwmod_get_pwrdm(oh);
517 pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
518#ifdef CONFIG_PM
519 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
520#endif
521 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 447 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
522 NULL, 0, 0); 448 NULL, 0, 0);
523 449
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
deleted file mode 100644
index 1481078763b8..000000000000
--- a/arch/arm/mach-omap2/usb-fs.c
+++ /dev/null
@@ -1,359 +0,0 @@
1/*
2 * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/errno.h>
25#include <linux/init.h>
26#include <linux/platform_device.h>
27#include <linux/clk.h>
28#include <linux/err.h>
29
30#include <asm/irq.h>
31
32#include <plat/usb.h>
33#include <plat/board.h>
34
35#include "control.h"
36#include "mux.h"
37
38#define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN
39#define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO
40#define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO
41#define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN
42#define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG
43
44#if defined(CONFIG_ARCH_OMAP2)
45
46#ifdef CONFIG_USB_GADGET_OMAP
47
48static struct resource udc_resources[] = {
49 /* order is significant! */
50 { /* registers */
51 .start = UDC_BASE,
52 .end = UDC_BASE + 0xff,
53 .flags = IORESOURCE_MEM,
54 }, { /* general IRQ */
55 .start = INT_USB_IRQ_GEN,
56 .flags = IORESOURCE_IRQ,
57 }, { /* PIO IRQ */
58 .start = INT_USB_IRQ_NISO,
59 .flags = IORESOURCE_IRQ,
60 }, { /* SOF IRQ */
61 .start = INT_USB_IRQ_ISO,
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66static u64 udc_dmamask = ~(u32)0;
67
68static struct platform_device udc_device = {
69 .name = "omap_udc",
70 .id = -1,
71 .dev = {
72 .dma_mask = &udc_dmamask,
73 .coherent_dma_mask = 0xffffffff,
74 },
75 .num_resources = ARRAY_SIZE(udc_resources),
76 .resource = udc_resources,
77};
78
79static inline void udc_device_init(struct omap_usb_config *pdata)
80{
81 pdata->udc_device = &udc_device;
82}
83
84#else
85
86static inline void udc_device_init(struct omap_usb_config *pdata)
87{
88}
89
90#endif
91
92#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
93
94/* The dmamask must be set for OHCI to work */
95static u64 ohci_dmamask = ~(u32)0;
96
97static struct resource ohci_resources[] = {
98 {
99 .start = OMAP_OHCI_BASE,
100 .end = OMAP_OHCI_BASE + 0xff,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .start = INT_USB_IRQ_HGEN,
105 .flags = IORESOURCE_IRQ,
106 },
107};
108
109static struct platform_device ohci_device = {
110 .name = "ohci",
111 .id = -1,
112 .dev = {
113 .dma_mask = &ohci_dmamask,
114 .coherent_dma_mask = 0xffffffff,
115 },
116 .num_resources = ARRAY_SIZE(ohci_resources),
117 .resource = ohci_resources,
118};
119
120static inline void ohci_device_init(struct omap_usb_config *pdata)
121{
122 pdata->ohci_device = &ohci_device;
123}
124
125#else
126
127static inline void ohci_device_init(struct omap_usb_config *pdata)
128{
129}
130
131#endif
132
133#if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
134
135static struct resource otg_resources[] = {
136 /* order is significant! */
137 {
138 .start = OTG_BASE,
139 .end = OTG_BASE + 0xff,
140 .flags = IORESOURCE_MEM,
141 }, {
142 .start = INT_USB_IRQ_OTG,
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
147static struct platform_device otg_device = {
148 .name = "omap_otg",
149 .id = -1,
150 .num_resources = ARRAY_SIZE(otg_resources),
151 .resource = otg_resources,
152};
153
154static inline void otg_device_init(struct omap_usb_config *pdata)
155{
156 pdata->otg_device = &otg_device;
157}
158
159#else
160
161static inline void otg_device_init(struct omap_usb_config *pdata)
162{
163}
164
165#endif
166
167static void omap2_usb_devconf_clear(u8 port, u32 mask)
168{
169 u32 r;
170
171 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
172 r &= ~USBTXWRMODEI(port, mask);
173 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
174}
175
176static void omap2_usb_devconf_set(u8 port, u32 mask)
177{
178 u32 r;
179
180 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
181 r |= USBTXWRMODEI(port, mask);
182 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
183}
184
185static void omap2_usb2_disable_5pinbitll(void)
186{
187 u32 r;
188
189 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
190 r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
191 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
192}
193
194static void omap2_usb2_enable_5pinunitll(void)
195{
196 u32 r;
197
198 r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
199 r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
200 omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
201}
202
203static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
204{
205 u32 syscon1 = 0;
206
207 omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
208
209 if (nwires == 0)
210 return 0;
211
212 if (is_device)
213 omap_mux_init_signal("usb0_puen", 0);
214
215 omap_mux_init_signal("usb0_dat", 0);
216 omap_mux_init_signal("usb0_txen", 0);
217 omap_mux_init_signal("usb0_se0", 0);
218 if (nwires != 3)
219 omap_mux_init_signal("usb0_rcv", 0);
220
221 switch (nwires) {
222 case 3:
223 syscon1 = 2;
224 omap2_usb_devconf_set(0, USB_BIDIR);
225 break;
226 case 4:
227 syscon1 = 1;
228 omap2_usb_devconf_set(0, USB_BIDIR);
229 break;
230 case 6:
231 syscon1 = 3;
232 omap_mux_init_signal("usb0_vp", 0);
233 omap_mux_init_signal("usb0_vm", 0);
234 omap2_usb_devconf_set(0, USB_UNIDIR);
235 break;
236 default:
237 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
238 0, nwires);
239 }
240
241 return syscon1 << 16;
242}
243
244static u32 __init omap2_usb1_init(unsigned nwires)
245{
246 u32 syscon1 = 0;
247
248 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
249
250 if (nwires == 0)
251 return 0;
252
253 /* NOTE: board-specific code must set up pin muxing for usb1,
254 * since each signal could come out on either of two balls.
255 */
256
257 switch (nwires) {
258 case 2:
259 /* NOTE: board-specific code must override this setting if
260 * this TLL link is not using DP/DM
261 */
262 syscon1 = 1;
263 omap2_usb_devconf_set(1, USB_BIDIR_TLL);
264 break;
265 case 3:
266 syscon1 = 2;
267 omap2_usb_devconf_set(1, USB_BIDIR);
268 break;
269 case 4:
270 syscon1 = 1;
271 omap2_usb_devconf_set(1, USB_BIDIR);
272 break;
273 case 6:
274 default:
275 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
276 1, nwires);
277 }
278
279 return syscon1 << 20;
280}
281
282static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
283{
284 u32 syscon1 = 0;
285
286 omap2_usb2_disable_5pinbitll();
287 alt_pingroup = 0;
288
289 /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
290 if (alt_pingroup || nwires == 0)
291 return 0;
292
293 omap_mux_init_signal("usb2_dat", 0);
294 omap_mux_init_signal("usb2_se0", 0);
295 if (nwires > 2)
296 omap_mux_init_signal("usb2_txen", 0);
297 if (nwires > 3)
298 omap_mux_init_signal("usb2_rcv", 0);
299
300 switch (nwires) {
301 case 2:
302 /* NOTE: board-specific code must override this setting if
303 * this TLL link is not using DP/DM
304 */
305 syscon1 = 1;
306 omap2_usb_devconf_set(2, USB_BIDIR_TLL);
307 break;
308 case 3:
309 syscon1 = 2;
310 omap2_usb_devconf_set(2, USB_BIDIR);
311 break;
312 case 4:
313 syscon1 = 1;
314 omap2_usb_devconf_set(2, USB_BIDIR);
315 break;
316 case 5:
317 /* NOTE: board-specific code must mux this setting depending
318 * on TLL link using DP/DM. Something must also
319 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
320 * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0
321 * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0
322 */
323
324 syscon1 = 3;
325 omap2_usb2_enable_5pinunitll();
326 break;
327 case 6:
328 default:
329 printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
330 2, nwires);
331 }
332
333 return syscon1 << 24;
334}
335
336void __init omap2_usbfs_init(struct omap_usb_config *pdata)
337{
338 struct clk *ick;
339
340 if (!cpu_is_omap24xx())
341 return;
342
343 ick = clk_get(NULL, "usb_l4_ick");
344 if (IS_ERR(ick))
345 return;
346
347 clk_enable(ick);
348 pdata->usb0_init = omap2_usb0_init;
349 pdata->usb1_init = omap2_usb1_init;
350 pdata->usb2_init = omap2_usb2_init;
351 udc_device_init(pdata);
352 ohci_device_init(pdata);
353 otg_device_init(pdata);
354 omap_otg_init(pdata);
355 clk_disable(ick);
356 clk_put(ick);
357}
358
359#endif
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index b19d1b43c12e..c4a576856661 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -41,12 +41,10 @@ static struct musb_hdrc_config musb_config = {
41}; 41};
42 42
43static struct musb_hdrc_platform_data musb_plat = { 43static struct musb_hdrc_platform_data musb_plat = {
44#ifdef CONFIG_USB_MUSB_OTG 44#ifdef CONFIG_USB_GADGET_MUSB_HDRC
45 .mode = MUSB_OTG, 45 .mode = MUSB_OTG,
46#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 46#else
47 .mode = MUSB_HOST, 47 .mode = MUSB_HOST,
48#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
49 .mode = MUSB_PERIPHERAL,
50#endif 48#endif
51 /* .clock is set dynamically */ 49 /* .clock is set dynamically */
52 .config = &musb_config, 50 .config = &musb_config,
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index db84a46ce7fd..805bea6edf17 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -300,7 +300,7 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
300 printk(error, 3, status); 300 printk(error, 3, status);
301 return status; 301 return status;
302 } 302 }
303 tusb_resources[2].start = irq + IH_GPIO_BASE; 303 tusb_resources[2].start = gpio_to_irq(irq);
304 304
305 /* set up memory timings ... can speed them up later */ 305 /* set up memory timings ... can speed them up later */
306 if (!ps_refclk) { 306 if (!ps_refclk) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 13:16:08 -0400