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-rw-r--r--arch/arm/mach-omap2/Kconfig13
-rw-r--r--arch/arm/mach-omap2/Makefile10
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c273
-rw-r--r--arch/arm/mach-omap2/board-generic.c18
-rw-r--r--arch/arm/mach-omap2/board-h4.c365
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c234
-rw-r--r--arch/arm/mach-omap2/common-board-devices.h1
-rw-r--r--arch/arm/mach-omap2/common.h2
-rw-r--r--arch/arm/mach-omap2/display.c78
-rw-r--r--arch/arm/mach-omap2/dss-common.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c58
-rw-r--r--arch/arm/mach-omap2/msdi.c69
-rw-r--r--arch/arm/mach-omap2/mux.h2
-rw-r--r--arch/arm/mach-omap2/mux2420.c690
-rw-r--r--arch/arm/mach-omap2/mux2420.h282
-rw-r--r--arch/arm/mach-omap2/mux2430.c793
-rw-r--r--arch/arm/mach-omap2/mux2430.h370
-rw-r--r--arch/arm/mach-omap2/omap-secure.h7
-rw-r--r--arch/arm/mach-omap2/omap4-common.c57
-rw-r--r--arch/arm/mach-omap2/omap_device.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c98
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c137
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c266
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c165
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c72
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h5
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c108
-rw-r--r--arch/arm/mach-omap2/pm34xx.c2
-rw-r--r--arch/arm/mach-omap2/powerdomain.c3
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h2
30 files changed, 291 insertions, 3893 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dc21df166161..4191ae08f4c8 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -192,19 +192,6 @@ config MACH_OMAP2_TUSB6010
192 depends on ARCH_OMAP2 && SOC_OMAP2420 192 depends on ARCH_OMAP2 && SOC_OMAP2420
193 default y if MACH_NOKIA_N8X0 193 default y if MACH_NOKIA_N8X0
194 194
195config MACH_OMAP_H4
196 bool "OMAP 2420 H4 board"
197 depends on SOC_OMAP2420
198 default y
199 select OMAP_DEBUG_DEVICES
200 select OMAP_PACKAGE_ZAF
201
202config MACH_OMAP_2430SDP
203 bool "OMAP 2430 SDP board"
204 depends on SOC_OMAP2430
205 default y
206 select OMAP_PACKAGE_ZAC
207
208config MACH_OMAP3_BEAGLE 195config MACH_OMAP3_BEAGLE
209 bool "OMAP3 BEAGLE board" 196 bool "OMAP3 BEAGLE board"
210 depends on ARCH_OMAP3 197 depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 1f25f3e99c05..f78b177e8f4f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -19,11 +19,11 @@ secure-common = omap-smc.o omap-secure.o
19 19
20obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) 20obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
21obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 21obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
22obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 22obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) 24obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) 25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
26obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common) 26obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
27 27
28ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 28ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
29obj-y += mcbsp.o 29obj-y += mcbsp.o
@@ -66,8 +66,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
66obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o 66obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
67 67
68# Pin multiplexing 68# Pin multiplexing
69obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
70obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
71obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o 69obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
72 70
73# SMS/SDRC 71# SMS/SDRC
@@ -237,8 +235,6 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o
237 235
238# Specific board support 236# Specific board support
239obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o 237obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
240obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
241obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
242obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o 238obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
243obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o 239obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
244obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o 240obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
deleted file mode 100644
index c711ad6ac067..000000000000
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ /dev/null
@@ -1,273 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-2430sdp.c
3 *
4 * Copyright (C) 2006 Texas Instruments
5 *
6 * Modified from mach-omap2/board-generic.c
7 *
8 * Initial Code : Based on a patch from Komal Shah and Richard Woodruff
9 * Updated the Code for 2430 SDP : Syed Mohammed Khasim
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/physmap.h>
22#include <linux/mmc/host.h>
23#include <linux/delay.h>
24#include <linux/i2c/twl.h>
25#include <linux/regulator/machine.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28#include <linux/io.h>
29#include <linux/gpio.h>
30#include <linux/usb/phy.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35
36#include "common.h"
37#include "gpmc.h"
38#include "gpmc-smc91x.h"
39
40#include <video/omapdss.h>
41#include <video/omap-panel-data.h>
42
43#include "mux.h"
44#include "hsmmc.h"
45#include "common-board-devices.h"
46
47#define SDP2430_CS0_BASE 0x04000000
48#define SECONDARY_LCD_GPIO 147
49
50static struct mtd_partition sdp2430_partitions[] = {
51 /* bootloader (U-Boot, etc) in first sector */
52 {
53 .name = "bootloader",
54 .offset = 0,
55 .size = SZ_256K,
56 .mask_flags = MTD_WRITEABLE, /* force read-only */
57 },
58 /* bootloader params in the next sector */
59 {
60 .name = "params",
61 .offset = MTDPART_OFS_APPEND,
62 .size = SZ_128K,
63 .mask_flags = 0,
64 },
65 /* kernel */
66 {
67 .name = "kernel",
68 .offset = MTDPART_OFS_APPEND,
69 .size = SZ_2M,
70 .mask_flags = 0
71 },
72 /* file system */
73 {
74 .name = "filesystem",
75 .offset = MTDPART_OFS_APPEND,
76 .size = MTDPART_SIZ_FULL,
77 .mask_flags = 0
78 }
79};
80
81static struct physmap_flash_data sdp2430_flash_data = {
82 .width = 2,
83 .parts = sdp2430_partitions,
84 .nr_parts = ARRAY_SIZE(sdp2430_partitions),
85};
86
87static struct resource sdp2430_flash_resource = {
88 .start = SDP2430_CS0_BASE,
89 .end = SDP2430_CS0_BASE + SZ_64M - 1,
90 .flags = IORESOURCE_MEM,
91};
92
93static struct platform_device sdp2430_flash_device = {
94 .name = "physmap-flash",
95 .id = 0,
96 .dev = {
97 .platform_data = &sdp2430_flash_data,
98 },
99 .num_resources = 1,
100 .resource = &sdp2430_flash_resource,
101};
102
103/* LCD */
104#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
105#define SDP2430_LCD_PANEL_ENABLE_GPIO 154
106
107static const struct display_timing sdp2430_lcd_videomode = {
108 .pixelclock = { 0, 5400000, 0 },
109
110 .hactive = { 0, 240, 0 },
111 .hfront_porch = { 0, 3, 0 },
112 .hback_porch = { 0, 39, 0 },
113 .hsync_len = { 0, 3, 0 },
114
115 .vactive = { 0, 320, 0 },
116 .vfront_porch = { 0, 2, 0 },
117 .vback_porch = { 0, 7, 0 },
118 .vsync_len = { 0, 1, 0 },
119
120 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
121 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
122};
123
124static struct panel_dpi_platform_data sdp2430_lcd_pdata = {
125 .name = "lcd",
126 .source = "dpi.0",
127
128 .data_lines = 16,
129
130 .display_timing = &sdp2430_lcd_videomode,
131
132 .enable_gpio = SDP2430_LCD_PANEL_ENABLE_GPIO,
133 .backlight_gpio = SDP2430_LCD_PANEL_BACKLIGHT_GPIO,
134};
135
136static struct platform_device sdp2430_lcd_device = {
137 .name = "panel-dpi",
138 .id = 0,
139 .dev.platform_data = &sdp2430_lcd_pdata,
140};
141
142static struct omap_dss_board_info sdp2430_dss_data = {
143 .default_display_name = "lcd",
144};
145
146static struct platform_device *sdp2430_devices[] __initdata = {
147 &sdp2430_flash_device,
148 &sdp2430_lcd_device,
149};
150
151#if IS_ENABLED(CONFIG_SMC91X)
152
153static struct omap_smc91x_platform_data board_smc91x_data = {
154 .cs = 5,
155 .gpio_irq = 149,
156 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
157 IORESOURCE_IRQ_LOWLEVEL,
158
159};
160
161static void __init board_smc91x_init(void)
162{
163 omap_mux_init_gpio(149, OMAP_PIN_INPUT);
164 gpmc_smc91x_init(&board_smc91x_data);
165}
166
167#else
168
169static inline void board_smc91x_init(void)
170{
171}
172
173#endif
174
175static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
176 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
177};
178
179/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
180static struct regulator_init_data sdp2430_vmmc1 = {
181 .constraints = {
182 .min_uV = 1850000,
183 .max_uV = 3150000,
184 .valid_modes_mask = REGULATOR_MODE_NORMAL
185 | REGULATOR_MODE_STANDBY,
186 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
187 | REGULATOR_CHANGE_MODE
188 | REGULATOR_CHANGE_STATUS,
189 },
190 .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies),
191 .consumer_supplies = &sdp2430_vmmc1_supplies[0],
192};
193
194static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
195};
196
197static struct twl4030_platform_data sdp2430_twldata = {
198 /* platform_data for children goes here */
199 .gpio = &sdp2430_gpio_data,
200 .vmmc1 = &sdp2430_vmmc1,
201};
202
203static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
204 {
205 I2C_BOARD_INFO("isp1301_omap", 0x2D),
206 .flags = I2C_CLIENT_WAKE,
207 },
208};
209
210static int __init omap2430_i2c_init(void)
211{
212 sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
213 omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
214 ARRAY_SIZE(sdp2430_i2c1_boardinfo));
215 omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START,
216 &sdp2430_twldata);
217 return 0;
218}
219
220static struct omap2_hsmmc_info mmc[] __initdata = {
221 {
222 .mmc = 1,
223 .caps = MMC_CAP_4_BIT_DATA,
224 .gpio_cd = -EINVAL,
225 .gpio_wp = -EINVAL,
226 .ext_clock = 1,
227 },
228 {} /* Terminator */
229};
230
231#ifdef CONFIG_OMAP_MUX
232static struct omap_board_mux board_mux[] __initdata = {
233 { .reg_offset = OMAP_MUX_TERMINATOR },
234};
235#endif
236
237static void __init omap_2430sdp_init(void)
238{
239 omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
240
241 omap2430_i2c_init();
242
243 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
244 omap_serial_init();
245 omap_sdrc_init(NULL, NULL);
246 omap_hsmmc_init(mmc);
247
248 omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
249 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
250 usb_musb_init(NULL);
251
252 board_smc91x_init();
253
254 /* Turn off secondary LCD backlight */
255 gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW,
256 "Secondary LCD backlight");
257
258 omap_display_init(&sdp2430_dss_data);
259}
260
261MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
262 /* Maintainer: Syed Khasim - Texas Instruments Inc */
263 .atag_offset = 0x100,
264 .reserve = omap_reserve,
265 .map_io = omap243x_map_io,
266 .init_early = omap2430_init_early,
267 .init_irq = omap2_init_irq,
268 .handle_irq = omap2_intc_handle_irq,
269 .init_machine = omap_2430sdp_init,
270 .init_late = omap2430_init_late,
271 .init_time = omap2_sync32k_timer_init,
272 .restart = omap2xxx_restart,
273MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 19f1652e94cf..8d972ff18c56 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -131,6 +131,24 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
131 .dt_compat = omap3_gp_boards_compat, 131 .dt_compat = omap3_gp_boards_compat,
132 .restart = omap3xxx_restart, 132 .restart = omap3xxx_restart,
133MACHINE_END 133MACHINE_END
134
135static const char *am3517_boards_compat[] __initdata = {
136 "ti,am3517",
137 NULL,
138};
139
140DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
141 .reserve = omap_reserve,
142 .map_io = omap3_map_io,
143 .init_early = am35xx_init_early,
144 .init_irq = omap_intc_of_init,
145 .handle_irq = omap3_intc_handle_irq,
146 .init_machine = omap_generic_init,
147 .init_late = omap3_init_late,
148 .init_time = omap3_gptimer_timer_init,
149 .dt_compat = am3517_boards_compat,
150 .restart = omap3xxx_restart,
151MACHINE_END
134#endif 152#endif
135 153
136#ifdef CONFIG_SOC_AM33XX 154#ifdef CONFIG_SOC_AM33XX
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
deleted file mode 100644
index f7808349a734..000000000000
--- a/arch/arm/mach-omap2/board-h4.c
+++ /dev/null
@@ -1,365 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-h4.c
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Paul Mundt <paul.mundt@nokia.com>
6 *
7 * Modified from mach-omap/omap1/board-generic.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/gpio.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/mtd.h>
18#include <linux/mtd/partitions.h>
19#include <linux/mtd/physmap.h>
20#include <linux/delay.h>
21#include <linux/workqueue.h>
22#include <linux/i2c.h>
23#include <linux/platform_data/at24.h>
24#include <linux/input.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/io.h>
28#include <linux/input/matrix_keypad.h>
29#include <linux/mfd/menelaus.h>
30#include <linux/omap-dma.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35
36#include <video/omapdss.h>
37#include <video/omap-panel-data.h>
38
39#include "common.h"
40#include "mux.h"
41#include "control.h"
42#include "gpmc.h"
43#include "gpmc-smc91x.h"
44
45#define H4_FLASH_CS 0
46
47#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
48static const uint32_t board_matrix_keys[] = {
49 KEY(0, 0, KEY_LEFT),
50 KEY(1, 0, KEY_RIGHT),
51 KEY(2, 0, KEY_A),
52 KEY(3, 0, KEY_B),
53 KEY(4, 0, KEY_C),
54 KEY(0, 1, KEY_DOWN),
55 KEY(1, 1, KEY_UP),
56 KEY(2, 1, KEY_E),
57 KEY(3, 1, KEY_F),
58 KEY(4, 1, KEY_G),
59 KEY(0, 2, KEY_ENTER),
60 KEY(1, 2, KEY_I),
61 KEY(2, 2, KEY_J),
62 KEY(3, 2, KEY_K),
63 KEY(4, 2, KEY_3),
64 KEY(0, 3, KEY_M),
65 KEY(1, 3, KEY_N),
66 KEY(2, 3, KEY_O),
67 KEY(3, 3, KEY_P),
68 KEY(4, 3, KEY_Q),
69 KEY(0, 4, KEY_R),
70 KEY(1, 4, KEY_4),
71 KEY(2, 4, KEY_T),
72 KEY(3, 4, KEY_U),
73 KEY(4, 4, KEY_ENTER),
74 KEY(0, 5, KEY_V),
75 KEY(1, 5, KEY_W),
76 KEY(2, 5, KEY_L),
77 KEY(3, 5, KEY_S),
78 KEY(4, 5, KEY_ENTER),
79};
80
81static const struct matrix_keymap_data board_keymap_data = {
82 .keymap = board_matrix_keys,
83 .keymap_size = ARRAY_SIZE(board_matrix_keys),
84};
85
86static unsigned int board_keypad_row_gpios[] = {
87 88, 89, 124, 11, 6, 96
88};
89
90static unsigned int board_keypad_col_gpios[] = {
91 90, 91, 100, 36, 12, 97, 98
92};
93
94static struct matrix_keypad_platform_data board_keypad_platform_data = {
95 .keymap_data = &board_keymap_data,
96 .row_gpios = board_keypad_row_gpios,
97 .num_row_gpios = ARRAY_SIZE(board_keypad_row_gpios),
98 .col_gpios = board_keypad_col_gpios,
99 .num_col_gpios = ARRAY_SIZE(board_keypad_col_gpios),
100 .active_low = 1,
101
102 .debounce_ms = 20,
103 .col_scan_delay_us = 5,
104};
105
106static struct platform_device board_keyboard = {
107 .name = "matrix-keypad",
108 .id = -1,
109 .dev = {
110 .platform_data = &board_keypad_platform_data,
111 },
112};
113static void __init board_mkp_init(void)
114{
115 omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
116 omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
117 omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
118 omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
119 if (omap_has_menelaus()) {
120 omap_mux_init_signal("sdrc_a14.gpio0",
121 OMAP_PULL_ENA | OMAP_PULL_UP);
122 omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
123 omap_mux_init_signal("gpio_98", 0);
124 board_keypad_row_gpios[5] = 0;
125 board_keypad_col_gpios[2] = 15;
126 board_keypad_col_gpios[6] = 18;
127 } else {
128 omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
129 omap_mux_init_signal("gpio_100", 0);
130 omap_mux_init_signal("gpio_98", 0);
131 }
132 omap_mux_init_signal("gpio_90", 0);
133 omap_mux_init_signal("gpio_91", 0);
134 omap_mux_init_signal("gpio_36", 0);
135 omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
136 omap_mux_init_signal("gpio_97", 0);
137
138 platform_device_register(&board_keyboard);
139}
140#else
141static inline void board_mkp_init(void)
142{
143}
144#endif
145
146static struct mtd_partition h4_partitions[] = {
147 /* bootloader (U-Boot, etc) in first sector */
148 {
149 .name = "bootloader",
150 .offset = 0,
151 .size = SZ_128K,
152 .mask_flags = MTD_WRITEABLE, /* force read-only */
153 },
154 /* bootloader params in the next sector */
155 {
156 .name = "params",
157 .offset = MTDPART_OFS_APPEND,
158 .size = SZ_128K,
159 .mask_flags = 0,
160 },
161 /* kernel */
162 {
163 .name = "kernel",
164 .offset = MTDPART_OFS_APPEND,
165 .size = SZ_2M,
166 .mask_flags = 0
167 },
168 /* file system */
169 {
170 .name = "filesystem",
171 .offset = MTDPART_OFS_APPEND,
172 .size = MTDPART_SIZ_FULL,
173 .mask_flags = 0
174 }
175};
176
177static struct physmap_flash_data h4_flash_data = {
178 .width = 2,
179 .parts = h4_partitions,
180 .nr_parts = ARRAY_SIZE(h4_partitions),
181};
182
183static struct resource h4_flash_resource = {
184 .flags = IORESOURCE_MEM,
185};
186
187static struct platform_device h4_flash_device = {
188 .name = "physmap-flash",
189 .id = 0,
190 .dev = {
191 .platform_data = &h4_flash_data,
192 },
193 .num_resources = 1,
194 .resource = &h4_flash_resource,
195};
196
197static const struct display_timing cm_t35_lcd_videomode = {
198 .pixelclock = { 0, 6250000, 0 },
199
200 .hactive = { 0, 240, 0 },
201 .hfront_porch = { 0, 15, 0 },
202 .hback_porch = { 0, 60, 0 },
203 .hsync_len = { 0, 15, 0 },
204
205 .vactive = { 0, 320, 0 },
206 .vfront_porch = { 0, 1, 0 },
207 .vback_porch = { 0, 1, 0 },
208 .vsync_len = { 0, 1, 0 },
209
210 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
211 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
212};
213
214static struct panel_dpi_platform_data cm_t35_lcd_pdata = {
215 .name = "lcd",
216 .source = "dpi.0",
217
218 .data_lines = 16,
219
220 .display_timing = &cm_t35_lcd_videomode,
221
222 .enable_gpio = -1,
223 .backlight_gpio = -1,
224};
225
226static struct platform_device cm_t35_lcd_device = {
227 .name = "panel-dpi",
228 .id = 0,
229 .dev.platform_data = &cm_t35_lcd_pdata,
230};
231
232static struct platform_device *h4_devices[] __initdata = {
233 &h4_flash_device,
234 &cm_t35_lcd_device,
235};
236
237static struct omap_dss_board_info h4_dss_data = {
238 .default_display_name = "lcd",
239};
240
241/* 2420 Sysboot setup (2430 is different) */
242static u32 get_sysboot_value(void)
243{
244 return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
245 (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
246 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
247 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
248}
249
250/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
251 *
252 * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
253 * correctly. The macro needs to look at production_id not just hawkeye.
254 */
255static u32 is_gpmc_muxed(void)
256{
257 u32 mux;
258 mux = get_sysboot_value();
259 if ((mux & 0xF) == 0xd)
260 return 1; /* NAND config (could be either) */
261 if (mux & 0x2) /* if mux'ed */
262 return 1;
263 else
264 return 0;
265}
266
267#if IS_ENABLED(CONFIG_SMC91X)
268
269static struct omap_smc91x_platform_data board_smc91x_data = {
270 .cs = 1,
271 .gpio_irq = 92,
272 .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_LOWLEVEL,
273};
274
275static void __init board_smc91x_init(void)
276{
277 if (is_gpmc_muxed())
278 board_smc91x_data.flags |= GPMC_MUX_ADD_DATA;
279
280 omap_mux_init_gpio(board_smc91x_data.gpio_irq, OMAP_PIN_INPUT);
281 gpmc_smc91x_init(&board_smc91x_data);
282}
283
284#else
285
286static inline void board_smc91x_init(void)
287{
288}
289
290#endif
291
292static void __init h4_init_flash(void)
293{
294 unsigned long base;
295
296 if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
297 printk("Can't request GPMC CS for flash\n");
298 return;
299 }
300 h4_flash_resource.start = base;
301 h4_flash_resource.end = base + SZ_64M - 1;
302}
303
304static struct at24_platform_data m24c01 = {
305 .byte_len = SZ_1K / 8,
306 .page_size = 16,
307};
308
309static struct i2c_board_info __initdata h4_i2c_board_info[] = {
310 {
311 I2C_BOARD_INFO("isp1301_omap", 0x2d),
312 },
313 { /* EEPROM on mainboard */
314 I2C_BOARD_INFO("24c01", 0x52),
315 .platform_data = &m24c01,
316 },
317 { /* EEPROM on cpu card */
318 I2C_BOARD_INFO("24c01", 0x57),
319 .platform_data = &m24c01,
320 },
321};
322
323#ifdef CONFIG_OMAP_MUX
324static struct omap_board_mux board_mux[] __initdata = {
325 { .reg_offset = OMAP_MUX_TERMINATOR },
326};
327#endif
328
329static void __init omap_h4_init(void)
330{
331 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
332
333 /*
334 * Make sure the serial ports are muxed on at this point.
335 * You have to mux them off in device drivers later on
336 * if not needed.
337 */
338
339 board_mkp_init();
340 h4_i2c_board_info[0].irq = gpio_to_irq(125);
341 i2c_register_board_info(1, h4_i2c_board_info,
342 ARRAY_SIZE(h4_i2c_board_info));
343
344 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
345 omap_serial_init();
346 omap_sdrc_init(NULL, NULL);
347 h4_init_flash();
348 board_smc91x_init();
349
350 omap_display_init(&h4_dss_data);
351}
352
353MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
354 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
355 .atag_offset = 0x100,
356 .reserve = omap_reserve,
357 .map_io = omap242x_map_io,
358 .init_early = omap2420_init_early,
359 .init_irq = omap2_init_irq,
360 .handle_irq = omap2_intc_handle_irq,
361 .init_machine = omap_h4_init,
362 .init_late = omap2420_init_late,
363 .init_time = omap2_sync32k_timer_init,
364 .restart = omap2xxx_restart,
365MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 827d15009a86..aead77a4bc6d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -21,7 +21,6 @@
21#include <linux/i2c.h> 21#include <linux/i2c.h>
22#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
23#include <linux/usb/musb.h> 23#include <linux/usb/musb.h>
24#include <linux/platform_data/i2c-cbus-gpio.h>
25#include <linux/platform_data/spi-omap2-mcspi.h> 24#include <linux/platform_data/spi-omap2-mcspi.h>
26#include <linux/platform_data/mtd-onenand-omap2.h> 25#include <linux/platform_data/mtd-onenand-omap2.h>
27#include <linux/mfd/menelaus.h> 26#include <linux/mfd/menelaus.h>
@@ -32,8 +31,7 @@
32 31
33#include "common.h" 32#include "common.h"
34#include "mmc.h" 33#include "mmc.h"
35 34#include "soc.h"
36#include "mux.h"
37#include "gpmc-onenand.h" 35#include "gpmc-onenand.h"
38 36
39#define TUSB6010_ASYNC_CS 1 37#define TUSB6010_ASYNC_CS 1
@@ -42,44 +40,30 @@
42#define TUSB6010_GPIO_ENABLE 0 40#define TUSB6010_GPIO_ENABLE 0
43#define TUSB6010_DMACHAN 0x3f 41#define TUSB6010_DMACHAN 0x3f
44 42
45#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE) 43#define NOKIA_N810_WIMAX (1 << 2)
46static struct i2c_cbus_platform_data n8x0_cbus_data = { 44#define NOKIA_N810 (1 << 1)
47 .clk_gpio = 66, 45#define NOKIA_N800 (1 << 0)
48 .dat_gpio = 65,
49 .sel_gpio = 64,
50};
51 46
52static struct platform_device n8x0_cbus_device = { 47static u32 board_caps;
53 .name = "i2c-cbus-gpio",
54 .id = 3,
55 .dev = {
56 .platform_data = &n8x0_cbus_data,
57 },
58};
59 48
60static struct i2c_board_info n8x0_i2c_board_info_3[] __initdata = { 49#define board_is_n800() (board_caps & NOKIA_N800)
61 { 50#define board_is_n810() (board_caps & NOKIA_N810)
62 I2C_BOARD_INFO("retu-mfd", 0x01), 51#define board_is_n810_wimax() (board_caps & NOKIA_N810_WIMAX)
63 },
64};
65 52
66static void __init n8x0_cbus_init(void) 53static void board_check_revision(void)
67{ 54{
68 const int retu_irq_gpio = 108; 55 if (of_have_populated_dt()) {
56 if (of_machine_is_compatible("nokia,n800"))
57 board_caps = NOKIA_N800;
58 else if (of_machine_is_compatible("nokia,n810"))
59 board_caps = NOKIA_N810;
60 else if (of_machine_is_compatible("nokia,n810-wimax"))
61 board_caps = NOKIA_N810_WIMAX;
62 }
69 63
70 if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ")) 64 if (!board_caps)
71 return; 65 pr_err("Unknown board\n");
72 irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING);
73 n8x0_i2c_board_info_3[0].irq = gpio_to_irq(retu_irq_gpio);
74 i2c_register_board_info(3, n8x0_i2c_board_info_3,
75 ARRAY_SIZE(n8x0_i2c_board_info_3));
76 platform_device_register(&n8x0_cbus_device);
77}
78#else /* CONFIG_I2C_CBUS_GPIO */
79static void __init n8x0_cbus_init(void)
80{
81} 66}
82#endif /* CONFIG_I2C_CBUS_GPIO */
83 67
84#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) 68#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
85/* 69/*
@@ -178,49 +162,6 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
178 }, 162 },
179}; 163};
180 164
181#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
182 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
183
184static struct mtd_partition onenand_partitions[] = {
185 {
186 .name = "bootloader",
187 .offset = 0,
188 .size = 0x20000,
189 .mask_flags = MTD_WRITEABLE, /* Force read-only */
190 },
191 {
192 .name = "config",
193 .offset = MTDPART_OFS_APPEND,
194 .size = 0x60000,
195 },
196 {
197 .name = "kernel",
198 .offset = MTDPART_OFS_APPEND,
199 .size = 0x200000,
200 },
201 {
202 .name = "initfs",
203 .offset = MTDPART_OFS_APPEND,
204 .size = 0x400000,
205 },
206 {
207 .name = "rootfs",
208 .offset = MTDPART_OFS_APPEND,
209 .size = MTDPART_SIZ_FULL,
210 },
211};
212
213static struct omap_onenand_platform_data board_onenand_data[] = {
214 {
215 .cs = 0,
216 .gpio_irq = 26,
217 .parts = onenand_partitions,
218 .nr_parts = ARRAY_SIZE(onenand_partitions),
219 .flags = ONENAND_SYNC_READ,
220 }
221};
222#endif
223
224#if defined(CONFIG_MENELAUS) && \ 165#if defined(CONFIG_MENELAUS) && \
225 (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)) 166 (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
226 167
@@ -342,7 +283,7 @@ static void n810_set_power_emmc(struct device *dev,
342static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on, 283static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
343 int vdd) 284 int vdd)
344{ 285{
345 if (machine_is_nokia_n800() || slot == 0) 286 if (board_is_n800() || slot == 0)
346 return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd); 287 return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
347 288
348 n810_set_power_emmc(dev, power_on); 289 n810_set_power_emmc(dev, power_on);
@@ -388,7 +329,7 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
388{ 329{
389 int bit, *openp, index; 330 int bit, *openp, index;
390 331
391 if (machine_is_nokia_n800()) { 332 if (board_is_n800()) {
392 bit = 1 << 1; 333 bit = 1 << 1;
393 openp = &slot2_cover_open; 334 openp = &slot2_cover_open;
394 index = 1; 335 index = 1;
@@ -421,7 +362,7 @@ static int n8x0_mmc_late_init(struct device *dev)
421 if (r < 0) 362 if (r < 0)
422 return r; 363 return r;
423 364
424 if (machine_is_nokia_n800()) 365 if (board_is_n800())
425 vs2sel = 0; 366 vs2sel = 0;
426 else 367 else
427 vs2sel = 2; 368 vs2sel = 2;
@@ -444,7 +385,7 @@ static int n8x0_mmc_late_init(struct device *dev)
444 if (r < 0) 385 if (r < 0)
445 return r; 386 return r;
446 387
447 if (machine_is_nokia_n800()) { 388 if (board_is_n800()) {
448 bit = 1 << 1; 389 bit = 1 << 1;
449 openp = &slot2_cover_open; 390 openp = &slot2_cover_open;
450 } else { 391 } else {
@@ -471,7 +412,7 @@ static void n8x0_mmc_shutdown(struct device *dev)
471{ 412{
472 int vs2sel; 413 int vs2sel;
473 414
474 if (machine_is_nokia_n800()) 415 if (board_is_n800())
475 vs2sel = 0; 416 vs2sel = 0;
476 else 417 else
477 vs2sel = 2; 418 vs2sel = 2;
@@ -486,7 +427,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
486 427
487 gpio_free(N8X0_SLOT_SWITCH_GPIO); 428 gpio_free(N8X0_SLOT_SWITCH_GPIO);
488 429
489 if (machine_is_nokia_n810()) { 430 if (board_is_n810()) {
490 gpio_free(N810_EMMC_VSD_GPIO); 431 gpio_free(N810_EMMC_VSD_GPIO);
491 gpio_free(N810_EMMC_VIO_GPIO); 432 gpio_free(N810_EMMC_VIO_GPIO);
492 } 433 }
@@ -497,7 +438,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
497 * MMC controller2 is not in use. 438 * MMC controller2 is not in use.
498 */ 439 */
499static struct omap_mmc_platform_data mmc1_data = { 440static struct omap_mmc_platform_data mmc1_data = {
500 .nr_slots = 2, 441 .nr_slots = 0,
501 .switch_slot = n8x0_mmc_switch_slot, 442 .switch_slot = n8x0_mmc_switch_slot,
502 .init = n8x0_mmc_late_init, 443 .init = n8x0_mmc_late_init,
503 .cleanup = n8x0_mmc_cleanup, 444 .cleanup = n8x0_mmc_cleanup,
@@ -537,7 +478,7 @@ static void __init n8x0_mmc_init(void)
537{ 478{
538 int err; 479 int err;
539 480
540 if (machine_is_nokia_n810()) { 481 if (board_is_n810()) {
541 mmc1_data.slots[0].name = "external"; 482 mmc1_data.slots[0].name = "external";
542 483
543 /* 484 /*
@@ -555,7 +496,7 @@ static void __init n8x0_mmc_init(void)
555 if (err) 496 if (err)
556 return; 497 return;
557 498
558 if (machine_is_nokia_n810()) { 499 if (board_is_n810()) {
559 err = gpio_request_array(n810_emmc_gpios, 500 err = gpio_request_array(n810_emmc_gpios,
560 ARRAY_SIZE(n810_emmc_gpios)); 501 ARRAY_SIZE(n810_emmc_gpios));
561 if (err) { 502 if (err) {
@@ -564,11 +505,11 @@ static void __init n8x0_mmc_init(void)
564 } 505 }
565 } 506 }
566 507
508 mmc1_data.nr_slots = 2;
567 mmc_data[0] = &mmc1_data; 509 mmc_data[0] = &mmc1_data;
568 omap242x_init_mmc(mmc_data);
569} 510}
570#else 511#else
571 512static struct omap_mmc_platform_data mmc1_data;
572void __init n8x0_mmc_init(void) 513void __init n8x0_mmc_init(void)
573{ 514{
574} 515}
@@ -650,109 +591,32 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
650 }, 591 },
651}; 592};
652 593
653#ifdef CONFIG_OMAP_MUX 594static int __init n8x0_late_initcall(void)
654static struct omap_board_mux board_mux[] __initdata = {
655 /* I2S codec port pins for McBSP block */
656 OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
657 OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
658 OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
659 OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
660 { .reg_offset = OMAP_MUX_TERMINATOR },
661};
662
663static struct omap_device_pad serial2_pads[] __initdata = {
664 {
665 .name = "uart3_rx_irrx.uart3_rx_irrx",
666 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
667 .enable = OMAP_MUX_MODE0,
668 .idle = OMAP_MUX_MODE3 /* Mux as GPIO for idle */
669 },
670};
671
672static inline void board_serial_init(void)
673{ 595{
674 struct omap_board_data bdata; 596 if (!board_caps)
675 597 return -ENODEV;
676 bdata.flags = 0;
677 bdata.pads = NULL;
678 bdata.pads_cnt = 0;
679
680 bdata.id = 0;
681 omap_serial_init_port(&bdata, NULL);
682
683 bdata.id = 1;
684 omap_serial_init_port(&bdata, NULL);
685
686 bdata.id = 2;
687 bdata.pads = serial2_pads;
688 bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
689 omap_serial_init_port(&bdata, NULL);
690}
691 598
692#else 599 n8x0_mmc_init();
600 n8x0_usb_init();
693 601
694static inline void board_serial_init(void) 602 return 0;
695{
696 omap_serial_init();
697} 603}
604omap_late_initcall(n8x0_late_initcall);
698 605
699#endif 606/*
700 607 * Legacy init pdata init for n8x0. Note that we want to follow the
701static void __init n8x0_init_machine(void) 608 * I2C bus numbering starting at 0 for device tree like other omaps.
609 */
610void * __init n8x0_legacy_init(void)
702{ 611{
703 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); 612 board_check_revision();
704 /* FIXME: add n810 spi devices */
705 spi_register_board_info(n800_spi_board_info, 613 spi_register_board_info(n800_spi_board_info,
706 ARRAY_SIZE(n800_spi_board_info)); 614 ARRAY_SIZE(n800_spi_board_info));
707 omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, 615 i2c_register_board_info(0, n8x0_i2c_board_info_1,
708 ARRAY_SIZE(n8x0_i2c_board_info_1)); 616 ARRAY_SIZE(n8x0_i2c_board_info_1));
709 omap_register_i2c_bus(2, 400, NULL, 0); 617 if (board_is_n810())
710 if (machine_is_nokia_n810()) 618 i2c_register_board_info(1, n810_i2c_board_info_2,
711 i2c_register_board_info(2, n810_i2c_board_info_2,
712 ARRAY_SIZE(n810_i2c_board_info_2)); 619 ARRAY_SIZE(n810_i2c_board_info_2));
713 board_serial_init();
714 omap_sdrc_init(NULL, NULL);
715 gpmc_onenand_init(board_onenand_data);
716 n8x0_mmc_init();
717 n8x0_usb_init();
718 n8x0_cbus_init();
719}
720 620
721MACHINE_START(NOKIA_N800, "Nokia N800") 621 return &mmc1_data;
722 .atag_offset = 0x100, 622}
723 .reserve = omap_reserve,
724 .map_io = omap242x_map_io,
725 .init_early = omap2420_init_early,
726 .init_irq = omap2_init_irq,
727 .handle_irq = omap2_intc_handle_irq,
728 .init_machine = n8x0_init_machine,
729 .init_late = omap2420_init_late,
730 .init_time = omap2_sync32k_timer_init,
731 .restart = omap2xxx_restart,
732MACHINE_END
733
734MACHINE_START(NOKIA_N810, "Nokia N810")
735 .atag_offset = 0x100,
736 .reserve = omap_reserve,
737 .map_io = omap242x_map_io,
738 .init_early = omap2420_init_early,
739 .init_irq = omap2_init_irq,
740 .handle_irq = omap2_intc_handle_irq,
741 .init_machine = n8x0_init_machine,
742 .init_late = omap2420_init_late,
743 .init_time = omap2_sync32k_timer_init,
744 .restart = omap2xxx_restart,
745MACHINE_END
746
747MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
748 .atag_offset = 0x100,
749 .reserve = omap_reserve,
750 .map_io = omap242x_map_io,
751 .init_early = omap2420_init_early,
752 .init_irq = omap2_init_irq,
753 .handle_irq = omap2_intc_handle_irq,
754 .init_machine = n8x0_init_machine,
755 .init_late = omap2420_init_late,
756 .init_time = omap2_sync32k_timer_init,
757 .restart = omap2xxx_restart,
758MACHINE_END
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 72bb41b3fd25..f338177e6900 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,5 +10,6 @@ struct ads7846_platform_data;
10 10
11void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, 11void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
12 struct ads7846_platform_data *board_pdata); 12 struct ads7846_platform_data *board_pdata);
13void *n8x0_legacy_init(void);
13 14
14#endif /* __OMAP_COMMON_BOARD_DEVICES__ */ 15#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index f7644febee81..240db38f232c 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -293,13 +293,13 @@ static inline void omap4_cpu_resume(void)
293#endif 293#endif
294 294
295void pdata_quirks_init(struct of_device_id *); 295void pdata_quirks_init(struct of_device_id *);
296void omap_auxdata_legacy_init(struct device *dev);
296void omap_pcs_legacy_init(int irq, void (*rearm)(void)); 297void omap_pcs_legacy_init(int irq, void (*rearm)(void));
297 298
298struct omap_sdrc_params; 299struct omap_sdrc_params;
299extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 300extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
300 struct omap_sdrc_params *sdrc_cs1); 301 struct omap_sdrc_params *sdrc_cs1);
301struct omap2_hsmmc_info; 302struct omap2_hsmmc_info;
302extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
303extern void omap_reserve(void); 303extern void omap_reserve(void);
304 304
305struct omap_hwmod; 305struct omap_hwmod;
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index a4e536b11ec9..58347bb874a0 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -32,7 +32,6 @@
32 32
33#include "soc.h" 33#include "soc.h"
34#include "iomap.h" 34#include "iomap.h"
35#include "mux.h"
36#include "control.h" 35#include "control.h"
37#include "display.h" 36#include "display.h"
38#include "prm.h" 37#include "prm.h"
@@ -102,90 +101,13 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
102 { "dss_hdmi", "omapdss_hdmi", -1 }, 101 { "dss_hdmi", "omapdss_hdmi", -1 },
103}; 102};
104 103
105static void __init omap4_tpd12s015_mux_pads(void)
106{
107 omap_mux_init_signal("hdmi_cec",
108 OMAP_PIN_INPUT_PULLUP);
109 omap_mux_init_signal("hdmi_ddc_scl",
110 OMAP_PIN_INPUT_PULLUP);
111 omap_mux_init_signal("hdmi_ddc_sda",
112 OMAP_PIN_INPUT_PULLUP);
113}
114
115static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
116{
117 u32 reg;
118 u16 control_i2c_1;
119
120 /*
121 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
122 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
123 * internal pull up resistor.
124 */
125 if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
126 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
127 reg = omap4_ctrl_pad_readl(control_i2c_1);
128 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
129 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
130 omap4_ctrl_pad_writel(reg, control_i2c_1);
131 }
132}
133
134static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
135{
136 u32 enable_mask, enable_shift;
137 u32 pipd_mask, pipd_shift;
138 u32 reg;
139
140 if (dsi_id == 0) {
141 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
142 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
143 pipd_mask = OMAP4_DSI1_PIPD_MASK;
144 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
145 } else if (dsi_id == 1) {
146 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
147 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
148 pipd_mask = OMAP4_DSI2_PIPD_MASK;
149 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
150 } else {
151 return -ENODEV;
152 }
153
154 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
155
156 reg &= ~enable_mask;
157 reg &= ~pipd_mask;
158
159 reg |= (lanes << enable_shift) & enable_mask;
160 reg |= (lanes << pipd_shift) & pipd_mask;
161
162 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
163
164 return 0;
165}
166
167int __init omap_hdmi_init(enum omap_hdmi_flags flags)
168{
169 if (cpu_is_omap44xx()) {
170 omap4_hdmi_mux_pads(flags);
171 omap4_tpd12s015_mux_pads();
172 }
173
174 return 0;
175}
176
177static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 104static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
178{ 105{
179 if (cpu_is_omap44xx())
180 return omap4_dsi_mux_pads(dsi_id, lane_mask);
181
182 return 0; 106 return 0;
183} 107}
184 108
185static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 109static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
186{ 110{
187 if (cpu_is_omap44xx())
188 omap4_dsi_mux_pads(dsi_id, 0);
189} 111}
190 112
191static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) 113static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index 365bfd3d9c68..dadccc91488c 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -223,7 +223,7 @@ void __init omap_4430sdp_display_init_of(void)
223static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = { 223static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
224 .name = "dvi", 224 .name = "dvi",
225 .source = "tfp410.0", 225 .source = "tfp410.0",
226 .i2c_bus_num = 3, 226 .i2c_bus_num = 2,
227}; 227};
228 228
229static struct platform_device omap3_igep2_dvi_connector_device = { 229static struct platform_device omap3_igep2_dvi_connector_device = {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 81de56251955..d24926e6340f 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1502,6 +1502,22 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1502 } 1502 }
1503 1503
1504 /* 1504 /*
1505 * For some GPMC devices we still need to rely on the bootloader
1506 * timings because the devices can be connected via FPGA. So far
1507 * the list is smc91x on the omap2 SDP boards, and 8250 on zooms.
1508 * REVISIT: Add timing support from slls644g.pdf and from the
1509 * lan91c96 manual.
1510 */
1511 if (of_device_is_compatible(child, "ns16550a") ||
1512 of_device_is_compatible(child, "smsc,lan91c94") ||
1513 of_device_is_compatible(child, "smsc,lan91c111")) {
1514 dev_warn(&pdev->dev,
1515 "%s using bootloader timings on CS%d\n",
1516 child->name, cs);
1517 goto no_timings;
1518 }
1519
1520 /*
1505 * FIXME: gpmc_cs_request() will map the CS to an arbitary 1521 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1506 * location in the gpmc address space. When booting with 1522 * location in the gpmc address space. When booting with
1507 * device-tree we want the NOR flash to be mapped to the 1523 * device-tree we want the NOR flash to be mapped to the
@@ -1529,6 +1545,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1529 gpmc_read_timings_dt(child, &gpmc_t); 1545 gpmc_read_timings_dt(child, &gpmc_t);
1530 gpmc_cs_set_timings(cs, &gpmc_t); 1546 gpmc_cs_set_timings(cs, &gpmc_t);
1531 1547
1548no_timings:
1532 if (of_platform_device_create(child, NULL, &pdev->dev)) 1549 if (of_platform_device_create(child, NULL, &pdev->dev))
1533 return 0; 1550 return 0;
1534 1551
@@ -1541,42 +1558,6 @@ err:
1541 return ret; 1558 return ret;
1542} 1559}
1543 1560
1544/*
1545 * REVISIT: Add timing support from slls644g.pdf
1546 */
1547static int gpmc_probe_8250(struct platform_device *pdev,
1548 struct device_node *child)
1549{
1550 struct resource res;
1551 unsigned long base;
1552 int ret, cs;
1553
1554 if (of_property_read_u32(child, "reg", &cs) < 0) {
1555 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1556 child->full_name);
1557 return -ENODEV;
1558 }
1559
1560 if (of_address_to_resource(child, 0, &res) < 0) {
1561 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1562 child->full_name);
1563 return -ENODEV;
1564 }
1565
1566 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1567 if (ret < 0) {
1568 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1569 return ret;
1570 }
1571
1572 if (of_platform_device_create(child, NULL, &pdev->dev))
1573 return 0;
1574
1575 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1576
1577 return -ENODEV;
1578}
1579
1580static int gpmc_probe_dt(struct platform_device *pdev) 1561static int gpmc_probe_dt(struct platform_device *pdev)
1581{ 1562{
1582 int ret; 1563 int ret;
@@ -1618,10 +1599,9 @@ static int gpmc_probe_dt(struct platform_device *pdev)
1618 else if (of_node_cmp(child->name, "onenand") == 0) 1599 else if (of_node_cmp(child->name, "onenand") == 0)
1619 ret = gpmc_probe_onenand_child(pdev, child); 1600 ret = gpmc_probe_onenand_child(pdev, child);
1620 else if (of_node_cmp(child->name, "ethernet") == 0 || 1601 else if (of_node_cmp(child->name, "ethernet") == 0 ||
1621 of_node_cmp(child->name, "nor") == 0) 1602 of_node_cmp(child->name, "nor") == 0 ||
1603 of_node_cmp(child->name, "uart") == 0)
1622 ret = gpmc_probe_generic_child(pdev, child); 1604 ret = gpmc_probe_generic_child(pdev, child);
1623 else if (of_node_cmp(child->name, "8250") == 0)
1624 ret = gpmc_probe_8250(pdev, child);
1625 1605
1626 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", 1606 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1627 __func__, child->full_name)) 1607 __func__, child->full_name))
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index c52d8b4a3e91..828e0db3d943 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -88,72 +88,3 @@ int omap_msdi_reset(struct omap_hwmod *oh)
88 88
89 return 0; 89 return 0;
90} 90}
91
92#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
93
94static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
95 *mmc_controller)
96{
97 if ((mmc_controller->slots[0].switch_pin > 0) && \
98 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
99 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
100 OMAP_PIN_INPUT_PULLUP);
101 if ((mmc_controller->slots[0].gpio_wp > 0) && \
102 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
103 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
104 OMAP_PIN_INPUT_PULLUP);
105
106 omap_mux_init_signal("sdmmc_cmd", 0);
107 omap_mux_init_signal("sdmmc_clki", 0);
108 omap_mux_init_signal("sdmmc_clko", 0);
109 omap_mux_init_signal("sdmmc_dat0", 0);
110 omap_mux_init_signal("sdmmc_dat_dir0", 0);
111 omap_mux_init_signal("sdmmc_cmd_dir", 0);
112 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
113 omap_mux_init_signal("sdmmc_dat1", 0);
114 omap_mux_init_signal("sdmmc_dat2", 0);
115 omap_mux_init_signal("sdmmc_dat3", 0);
116 omap_mux_init_signal("sdmmc_dat_dir1", 0);
117 omap_mux_init_signal("sdmmc_dat_dir2", 0);
118 omap_mux_init_signal("sdmmc_dat_dir3", 0);
119 }
120
121 /*
122 * Use internal loop-back in MMC/SDIO Module Input Clock
123 * selection
124 */
125 if (mmc_controller->slots[0].internal_clock) {
126 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
127 v |= (1 << 24);
128 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
129 }
130}
131
132void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
133{
134 struct platform_device *pdev;
135 struct omap_hwmod *oh;
136 int id = 0;
137 char *oh_name = "msdi1";
138 char *dev_name = "mmci-omap";
139
140 if (!mmc_data[0]) {
141 pr_err("%s fails: Incomplete platform data\n", __func__);
142 return;
143 }
144
145 omap242x_mmc_mux(mmc_data[0]);
146
147 oh = omap_hwmod_lookup(oh_name);
148 if (!oh) {
149 pr_err("Could not look up %s\n", oh_name);
150 return;
151 }
152 pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
153 sizeof(struct omap_mmc_platform_data));
154 if (IS_ERR(pdev))
155 WARN(1, "Can'd build omap_device for %s:%s.\n",
156 dev_name, oh->name);
157}
158
159#endif
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 16f78a990d04..a722330d4d53 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -7,8 +7,6 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9 9
10#include "mux2420.h"
11#include "mux2430.h"
12#include "mux34xx.h" 10#include "mux34xx.h"
13 11
14#define OMAP_MUX_TERMINATOR 0xffff 12#define OMAP_MUX_TERMINATOR 0xffff
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
deleted file mode 100644
index cf6de0971c6c..000000000000
--- a/arch/arm/mach-omap2/mux2420.c
+++ /dev/null
@@ -1,690 +0,0 @@
1/*
2 * Copyright (C) 2010 Nokia
3 * Copyright (C) 2010 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP2420_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap2420
42 */
43static struct omap_mux __initdata omap2420_muxmodes[] = {
44 _OMAP2420_MUXENTRY(CAM_D0, 54,
45 "cam_d0", "hw_dbg2", "sti_dout", "gpio_54",
46 NULL, NULL, "etk_d2", NULL),
47 _OMAP2420_MUXENTRY(CAM_D1, 53,
48 "cam_d1", "hw_dbg3", "sti_din", "gpio_53",
49 NULL, NULL, "etk_d3", NULL),
50 _OMAP2420_MUXENTRY(CAM_D2, 52,
51 "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52",
52 NULL, NULL, "etk_d4", NULL),
53 _OMAP2420_MUXENTRY(CAM_D3, 51,
54 "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51",
55 NULL, NULL, "etk_d5", NULL),
56 _OMAP2420_MUXENTRY(CAM_D4, 50,
57 "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50",
58 NULL, NULL, "etk_d6", NULL),
59 _OMAP2420_MUXENTRY(CAM_D5, 49,
60 "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49",
61 NULL, NULL, "etk_d7", NULL),
62 _OMAP2420_MUXENTRY(CAM_D6, 0,
63 "cam_d6", "hw_dbg8", NULL, NULL,
64 NULL, NULL, "etk_d8", NULL),
65 _OMAP2420_MUXENTRY(CAM_D7, 0,
66 "cam_d7", "hw_dbg9", NULL, NULL,
67 NULL, NULL, "etk_d9", NULL),
68 _OMAP2420_MUXENTRY(CAM_D8, 54,
69 "cam_d8", "hw_dbg10", NULL, "gpio_54",
70 NULL, NULL, "etk_d10", NULL),
71 _OMAP2420_MUXENTRY(CAM_D9, 53,
72 "cam_d9", "hw_dbg11", NULL, "gpio_53",
73 NULL, NULL, "etk_d11", NULL),
74 _OMAP2420_MUXENTRY(CAM_HS, 55,
75 "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55",
76 NULL, NULL, "etk_d1", NULL),
77 _OMAP2420_MUXENTRY(CAM_LCLK, 57,
78 "cam_lclk", NULL, "mcbsp_clks", "gpio_57",
79 NULL, NULL, "etk_c1", NULL),
80 _OMAP2420_MUXENTRY(CAM_VS, 56,
81 "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56",
82 NULL, NULL, "etk_d0", NULL),
83 _OMAP2420_MUXENTRY(CAM_XCLK, 0,
84 "cam_xclk", NULL, "sti_clk", NULL,
85 NULL, NULL, "etk_c2", NULL),
86 _OMAP2420_MUXENTRY(DSS_ACBIAS, 48,
87 "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
88 NULL, NULL, NULL, NULL),
89 _OMAP2420_MUXENTRY(DSS_DATA10, 40,
90 "dss_data10", NULL, NULL, "gpio_40",
91 NULL, NULL, NULL, NULL),
92 _OMAP2420_MUXENTRY(DSS_DATA11, 41,
93 "dss_data11", NULL, NULL, "gpio_41",
94 NULL, NULL, NULL, NULL),
95 _OMAP2420_MUXENTRY(DSS_DATA12, 42,
96 "dss_data12", NULL, NULL, "gpio_42",
97 NULL, NULL, NULL, NULL),
98 _OMAP2420_MUXENTRY(DSS_DATA13, 43,
99 "dss_data13", NULL, NULL, "gpio_43",
100 NULL, NULL, NULL, NULL),
101 _OMAP2420_MUXENTRY(DSS_DATA14, 44,
102 "dss_data14", NULL, NULL, "gpio_44",
103 NULL, NULL, NULL, NULL),
104 _OMAP2420_MUXENTRY(DSS_DATA15, 45,
105 "dss_data15", NULL, NULL, "gpio_45",
106 NULL, NULL, NULL, NULL),
107 _OMAP2420_MUXENTRY(DSS_DATA16, 46,
108 "dss_data16", NULL, NULL, "gpio_46",
109 NULL, NULL, NULL, NULL),
110 _OMAP2420_MUXENTRY(DSS_DATA17, 47,
111 "dss_data17", NULL, NULL, "gpio_47",
112 NULL, NULL, NULL, NULL),
113 _OMAP2420_MUXENTRY(DSS_DATA8, 38,
114 "dss_data8", NULL, NULL, "gpio_38",
115 NULL, NULL, NULL, NULL),
116 _OMAP2420_MUXENTRY(DSS_DATA9, 39,
117 "dss_data9", NULL, NULL, "gpio_39",
118 NULL, NULL, NULL, NULL),
119 _OMAP2420_MUXENTRY(EAC_AC_DIN, 115,
120 "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115",
121 NULL, NULL, NULL, NULL),
122 _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116,
123 "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116",
124 NULL, NULL, NULL, NULL),
125 _OMAP2420_MUXENTRY(EAC_AC_FS, 114,
126 "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114",
127 NULL, NULL, NULL, NULL),
128 _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117,
129 "eac_ac_mclk", NULL, NULL, "gpio_117",
130 NULL, NULL, NULL, NULL),
131 _OMAP2420_MUXENTRY(EAC_AC_RST, 118,
132 "eac_ac_rst", "eac_bt_din", NULL, "gpio_118",
133 NULL, NULL, NULL, NULL),
134 _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113,
135 "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113",
136 NULL, NULL, NULL, NULL),
137 _OMAP2420_MUXENTRY(EAC_BT_DIN, 73,
138 "eac_bt_din", NULL, NULL, "gpio_73",
139 NULL, NULL, "etk_d9", NULL),
140 _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74,
141 "eac_bt_dout", NULL, "sti_clk", "gpio_74",
142 NULL, NULL, "etk_d8", NULL),
143 _OMAP2420_MUXENTRY(EAC_BT_FS, 72,
144 "eac_bt_fs", NULL, NULL, "gpio_72",
145 NULL, NULL, "etk_d10", NULL),
146 _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71,
147 "eac_bt_sclk", NULL, NULL, "gpio_71",
148 NULL, NULL, "etk_d11", NULL),
149 _OMAP2420_MUXENTRY(GPIO_119, 119,
150 "gpio_119", NULL, "sti_din", "gpio_119",
151 NULL, "sys_boot0", "etk_d12", NULL),
152 _OMAP2420_MUXENTRY(GPIO_120, 120,
153 "gpio_120", NULL, "sti_dout", "gpio_120",
154 "cam_d9", "sys_boot1", "etk_d13", NULL),
155 _OMAP2420_MUXENTRY(GPIO_121, 121,
156 "gpio_121", NULL, NULL, "gpio_121",
157 "jtag_emu2", "sys_boot2", "etk_d14", NULL),
158 _OMAP2420_MUXENTRY(GPIO_122, 122,
159 "gpio_122", NULL, NULL, "gpio_122",
160 "jtag_emu3", "sys_boot3", "etk_d15", NULL),
161 _OMAP2420_MUXENTRY(GPIO_124, 124,
162 "gpio_124", NULL, NULL, "gpio_124",
163 NULL, "sys_boot5", NULL, NULL),
164 _OMAP2420_MUXENTRY(GPIO_125, 125,
165 "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125",
166 NULL, NULL, NULL, NULL),
167 _OMAP2420_MUXENTRY(GPIO_36, 36,
168 "gpio_36", NULL, NULL, "gpio_36",
169 NULL, "sys_boot4", NULL, NULL),
170 _OMAP2420_MUXENTRY(GPIO_62, 62,
171 "gpio_62", "uart1_rx", "usb1_dat", "gpio_62",
172 NULL, NULL, NULL, NULL),
173 _OMAP2420_MUXENTRY(GPIO_6, 6,
174 "gpio_6", "tv_detpulse", NULL, "gpio_6",
175 NULL, NULL, NULL, NULL),
176 _OMAP2420_MUXENTRY(GPMC_A10, 3,
177 "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3",
178 NULL, NULL, NULL, NULL),
179 _OMAP2420_MUXENTRY(GPMC_A1, 12,
180 "gpmc_a1", "dss_data18", NULL, "gpio_12",
181 NULL, NULL, NULL, NULL),
182 _OMAP2420_MUXENTRY(GPMC_A2, 11,
183 "gpmc_a2", "dss_data19", NULL, "gpio_11",
184 NULL, NULL, NULL, NULL),
185 _OMAP2420_MUXENTRY(GPMC_A3, 10,
186 "gpmc_a3", "dss_data20", NULL, "gpio_10",
187 NULL, NULL, NULL, NULL),
188 _OMAP2420_MUXENTRY(GPMC_A4, 9,
189 "gpmc_a4", "dss_data21", NULL, "gpio_9",
190 NULL, NULL, NULL, NULL),
191 _OMAP2420_MUXENTRY(GPMC_A5, 8,
192 "gpmc_a5", "dss_data22", NULL, "gpio_8",
193 NULL, NULL, NULL, NULL),
194 _OMAP2420_MUXENTRY(GPMC_A6, 7,
195 "gpmc_a6", "dss_data23", NULL, "gpio_7",
196 NULL, NULL, NULL, NULL),
197 _OMAP2420_MUXENTRY(GPMC_A7, 6,
198 "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6",
199 NULL, NULL, NULL, NULL),
200 _OMAP2420_MUXENTRY(GPMC_A8, 5,
201 "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5",
202 NULL, NULL, NULL, NULL),
203 _OMAP2420_MUXENTRY(GPMC_A9, 4,
204 "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4",
205 NULL, NULL, NULL, NULL),
206 _OMAP2420_MUXENTRY(GPMC_CLK, 21,
207 "gpmc_clk", NULL, NULL, "gpio_21",
208 NULL, NULL, NULL, NULL),
209 _OMAP2420_MUXENTRY(GPMC_D10, 18,
210 "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18",
211 NULL, NULL, NULL, NULL),
212 _OMAP2420_MUXENTRY(GPMC_D11, 17,
213 "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17",
214 NULL, NULL, NULL, NULL),
215 _OMAP2420_MUXENTRY(GPMC_D12, 16,
216 "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16",
217 NULL, NULL, NULL, NULL),
218 _OMAP2420_MUXENTRY(GPMC_D13, 15,
219 "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15",
220 NULL, NULL, NULL, NULL),
221 _OMAP2420_MUXENTRY(GPMC_D14, 14,
222 "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14",
223 NULL, NULL, NULL, NULL),
224 _OMAP2420_MUXENTRY(GPMC_D15, 13,
225 "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13",
226 NULL, NULL, NULL, NULL),
227 _OMAP2420_MUXENTRY(GPMC_D8, 20,
228 "gpmc_d8", NULL, NULL, "gpio_20",
229 NULL, NULL, NULL, NULL),
230 _OMAP2420_MUXENTRY(GPMC_D9, 19,
231 "gpmc_d9", "ssi2_wake", NULL, "gpio_19",
232 NULL, NULL, NULL, NULL),
233 _OMAP2420_MUXENTRY(GPMC_NBE0, 29,
234 "gpmc_nbe0", NULL, NULL, "gpio_29",
235 NULL, NULL, NULL, NULL),
236 _OMAP2420_MUXENTRY(GPMC_NBE1, 30,
237 "gpmc_nbe1", NULL, NULL, "gpio_30",
238 NULL, NULL, NULL, NULL),
239 _OMAP2420_MUXENTRY(GPMC_NCS1, 22,
240 "gpmc_ncs1", NULL, NULL, "gpio_22",
241 NULL, NULL, NULL, NULL),
242 _OMAP2420_MUXENTRY(GPMC_NCS2, 23,
243 "gpmc_ncs2", NULL, NULL, "gpio_23",
244 NULL, NULL, NULL, NULL),
245 _OMAP2420_MUXENTRY(GPMC_NCS3, 24,
246 "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
247 NULL, NULL, NULL, NULL),
248 _OMAP2420_MUXENTRY(GPMC_NCS4, 25,
249 "gpmc_ncs4", NULL, NULL, "gpio_25",
250 NULL, NULL, NULL, NULL),
251 _OMAP2420_MUXENTRY(GPMC_NCS5, 26,
252 "gpmc_ncs5", NULL, NULL, "gpio_26",
253 NULL, NULL, NULL, NULL),
254 _OMAP2420_MUXENTRY(GPMC_NCS6, 27,
255 "gpmc_ncs6", NULL, NULL, "gpio_27",
256 NULL, NULL, NULL, NULL),
257 _OMAP2420_MUXENTRY(GPMC_NCS7, 28,
258 "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL,
259 NULL, NULL, NULL, NULL),
260 _OMAP2420_MUXENTRY(GPMC_NWP, 31,
261 "gpmc_nwp", NULL, NULL, "gpio_31",
262 NULL, NULL, NULL, NULL),
263 _OMAP2420_MUXENTRY(GPMC_WAIT1, 33,
264 "gpmc_wait1", NULL, NULL, "gpio_33",
265 NULL, NULL, NULL, NULL),
266 _OMAP2420_MUXENTRY(GPMC_WAIT2, 34,
267 "gpmc_wait2", NULL, NULL, "gpio_34",
268 NULL, NULL, NULL, NULL),
269 _OMAP2420_MUXENTRY(GPMC_WAIT3, 35,
270 "gpmc_wait3", NULL, NULL, "gpio_35",
271 NULL, NULL, NULL, NULL),
272 _OMAP2420_MUXENTRY(HDQ_SIO, 101,
273 "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
274 NULL, NULL, NULL, NULL),
275 _OMAP2420_MUXENTRY(I2C2_SCL, 99,
276 "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99",
277 NULL, NULL, NULL, NULL),
278 _OMAP2420_MUXENTRY(I2C2_SDA, 100,
279 "i2c2_sda", NULL, "spi2_ncs1", "gpio_100",
280 NULL, NULL, NULL, NULL),
281 _OMAP2420_MUXENTRY(JTAG_EMU0, 127,
282 "jtag_emu0", NULL, NULL, "gpio_127",
283 NULL, NULL, NULL, NULL),
284 _OMAP2420_MUXENTRY(JTAG_EMU1, 126,
285 "jtag_emu1", NULL, NULL, "gpio_126",
286 NULL, NULL, NULL, NULL),
287 _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92,
288 "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92",
289 NULL, NULL, NULL, NULL),
290 _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98,
291 "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98",
292 NULL, NULL, NULL, NULL),
293 _OMAP2420_MUXENTRY(MCBSP1_DR, 95,
294 "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95",
295 NULL, NULL, NULL, NULL),
296 _OMAP2420_MUXENTRY(MCBSP1_DX, 94,
297 "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94",
298 NULL, NULL, NULL, NULL),
299 _OMAP2420_MUXENTRY(MCBSP1_FSR, 93,
300 "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93",
301 "spi2_ncs1", NULL, NULL, NULL),
302 _OMAP2420_MUXENTRY(MCBSP1_FSX, 97,
303 "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
304 NULL, NULL, NULL, NULL),
305 _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12,
306 "mcbsp2_clkx", NULL, "dss_data23", "gpio_12",
307 NULL, NULL, NULL, NULL),
308 _OMAP2420_MUXENTRY(MCBSP2_DR, 11,
309 "mcbsp2_dr", NULL, "dss_data22", "gpio_11",
310 NULL, NULL, NULL, NULL),
311 _OMAP2420_MUXENTRY(MCBSP_CLKS, 96,
312 "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96",
313 NULL, NULL, NULL, NULL),
314 _OMAP2420_MUXENTRY(MMC_CLKI, 59,
315 "sdmmc_clki", "ms_clki", NULL, "gpio_59",
316 NULL, NULL, NULL, NULL),
317 _OMAP2420_MUXENTRY(MMC_CLKO, 0,
318 "sdmmc_clko", "ms_clko", NULL, NULL,
319 NULL, NULL, NULL, NULL),
320 _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8,
321 "sdmmc_cmd_dir", NULL, NULL, "gpio_8",
322 NULL, NULL, NULL, NULL),
323 _OMAP2420_MUXENTRY(MMC_CMD, 0,
324 "sdmmc_cmd", "ms_bs", NULL, NULL,
325 NULL, NULL, NULL, NULL),
326 _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7,
327 "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7",
328 NULL, NULL, NULL, NULL),
329 _OMAP2420_MUXENTRY(MMC_DAT0, 0,
330 "sdmmc_dat0", "ms_dat0", NULL, NULL,
331 NULL, NULL, NULL, NULL),
332 _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78,
333 "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78",
334 NULL, NULL, NULL, NULL),
335 _OMAP2420_MUXENTRY(MMC_DAT1, 75,
336 "sdmmc_dat1", "ms_dat1", NULL, "gpio_75",
337 NULL, NULL, NULL, NULL),
338 _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79,
339 "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79",
340 NULL, NULL, NULL, NULL),
341 _OMAP2420_MUXENTRY(MMC_DAT2, 76,
342 "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76",
343 NULL, NULL, NULL, NULL),
344 _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80,
345 "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80",
346 NULL, NULL, NULL, NULL),
347 _OMAP2420_MUXENTRY(MMC_DAT3, 77,
348 "sdmmc_dat3", "ms_dat3", NULL, "gpio_77",
349 NULL, NULL, NULL, NULL),
350 _OMAP2420_MUXENTRY(SDRC_A12, 2,
351 "sdrc_a12", NULL, NULL, "gpio_2",
352 NULL, NULL, NULL, NULL),
353 _OMAP2420_MUXENTRY(SDRC_A13, 1,
354 "sdrc_a13", NULL, NULL, "gpio_1",
355 NULL, NULL, NULL, NULL),
356 _OMAP2420_MUXENTRY(SDRC_A14, 0,
357 "sdrc_a14", NULL, NULL, "gpio_0",
358 NULL, NULL, NULL, NULL),
359 _OMAP2420_MUXENTRY(SDRC_CKE1, 38,
360 "sdrc_cke1", NULL, NULL, "gpio_38",
361 NULL, NULL, NULL, NULL),
362 _OMAP2420_MUXENTRY(SDRC_NCS1, 37,
363 "sdrc_ncs1", NULL, NULL, "gpio_37",
364 NULL, NULL, NULL, NULL),
365 _OMAP2420_MUXENTRY(SPI1_CLK, 81,
366 "spi1_clk", NULL, NULL, "gpio_81",
367 NULL, NULL, NULL, NULL),
368 _OMAP2420_MUXENTRY(SPI1_NCS0, 84,
369 "spi1_ncs0", NULL, NULL, "gpio_84",
370 NULL, NULL, NULL, NULL),
371 _OMAP2420_MUXENTRY(SPI1_NCS1, 85,
372 "spi1_ncs1", NULL, NULL, "gpio_85",
373 NULL, NULL, NULL, NULL),
374 _OMAP2420_MUXENTRY(SPI1_NCS2, 86,
375 "spi1_ncs2", NULL, NULL, "gpio_86",
376 NULL, NULL, NULL, NULL),
377 _OMAP2420_MUXENTRY(SPI1_NCS3, 87,
378 "spi1_ncs3", NULL, NULL, "gpio_87",
379 NULL, NULL, NULL, NULL),
380 _OMAP2420_MUXENTRY(SPI1_SIMO, 82,
381 "spi1_simo", NULL, NULL, "gpio_82",
382 NULL, NULL, NULL, NULL),
383 _OMAP2420_MUXENTRY(SPI1_SOMI, 83,
384 "spi1_somi", NULL, NULL, "gpio_83",
385 NULL, NULL, NULL, NULL),
386 _OMAP2420_MUXENTRY(SPI2_CLK, 88,
387 "spi2_clk", NULL, NULL, "gpio_88",
388 NULL, NULL, NULL, NULL),
389 _OMAP2420_MUXENTRY(SPI2_NCS0, 91,
390 "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91",
391 NULL, NULL, NULL, NULL),
392 _OMAP2420_MUXENTRY(SPI2_SIMO, 89,
393 "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
394 NULL, NULL, NULL, NULL),
395 _OMAP2420_MUXENTRY(SPI2_SOMI, 90,
396 "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
397 NULL, NULL, NULL, NULL),
398 _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63,
399 "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63",
400 NULL, NULL, NULL, NULL),
401 _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59,
402 "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
403 NULL, NULL, NULL, NULL),
404 _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64,
405 "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64",
406 NULL, NULL, NULL, NULL),
407 _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25,
408 "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25",
409 NULL, NULL, NULL, NULL),
410 _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65,
411 "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65",
412 NULL, NULL, NULL, NULL),
413 _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61,
414 "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
415 NULL, NULL, NULL, NULL),
416 _OMAP2420_MUXENTRY(SSI1_WAKE, 66,
417 "ssi1_wake", "eac_md_fs", NULL, "gpio_66",
418 NULL, NULL, NULL, NULL),
419 _OMAP2420_MUXENTRY(SYS_CLKOUT, 123,
420 "sys_clkout", NULL, NULL, "gpio_123",
421 NULL, NULL, NULL, NULL),
422 _OMAP2420_MUXENTRY(SYS_CLKREQ, 52,
423 "sys_clkreq", NULL, NULL, "gpio_52",
424 NULL, NULL, NULL, NULL),
425 _OMAP2420_MUXENTRY(SYS_NIRQ, 60,
426 "sys_nirq", NULL, NULL, "gpio_60",
427 NULL, NULL, NULL, NULL),
428 _OMAP2420_MUXENTRY(UART1_CTS, 32,
429 "uart1_cts", NULL, "dss_data18", "gpio_32",
430 NULL, NULL, NULL, NULL),
431 _OMAP2420_MUXENTRY(UART1_RTS, 8,
432 "uart1_rts", NULL, "dss_data19", "gpio_8",
433 NULL, NULL, NULL, NULL),
434 _OMAP2420_MUXENTRY(UART1_RX, 10,
435 "uart1_rx", NULL, "dss_data21", "gpio_10",
436 NULL, NULL, NULL, NULL),
437 _OMAP2420_MUXENTRY(UART1_TX, 9,
438 "uart1_tx", NULL, "dss_data20", "gpio_9",
439 NULL, NULL, NULL, NULL),
440 _OMAP2420_MUXENTRY(UART2_CTS, 67,
441 "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
442 NULL, NULL, NULL, NULL),
443 _OMAP2420_MUXENTRY(UART2_RTS, 68,
444 "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
445 NULL, NULL, NULL, NULL),
446 _OMAP2420_MUXENTRY(UART2_RX, 70,
447 "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
448 NULL, NULL, NULL, NULL),
449 _OMAP2420_MUXENTRY(UART2_TX, 69,
450 "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
451 NULL, NULL, NULL, NULL),
452 _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102,
453 "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
454 NULL, NULL, NULL, NULL),
455 _OMAP2420_MUXENTRY(UART3_RTS_SD, 103,
456 "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
457 NULL, NULL, NULL, NULL),
458 _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105,
459 "uart3_rx_irrx", NULL, NULL, "gpio_105",
460 NULL, NULL, NULL, NULL),
461 _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104,
462 "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
463 NULL, NULL, NULL, NULL),
464 _OMAP2420_MUXENTRY(USB0_DAT, 112,
465 "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112",
466 "uart2_tx", NULL, NULL, NULL),
467 _OMAP2420_MUXENTRY(USB0_PUEN, 106,
468 "usb0_puen", "mcbsp2_dx", NULL, "gpio_106",
469 NULL, NULL, NULL, NULL),
470 _OMAP2420_MUXENTRY(USB0_RCV, 109,
471 "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109",
472 "uart2_cts", NULL, NULL, NULL),
473 _OMAP2420_MUXENTRY(USB0_SE0, 111,
474 "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111",
475 "uart2_rx", NULL, NULL, NULL),
476 _OMAP2420_MUXENTRY(USB0_TXEN, 110,
477 "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110",
478 NULL, NULL, NULL, NULL),
479 _OMAP2420_MUXENTRY(USB0_VM, 108,
480 "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108",
481 "uart2_rx", NULL, NULL, NULL),
482 _OMAP2420_MUXENTRY(USB0_VP, 107,
483 "usb0_vp", "mcbsp2_dr", NULL, "gpio_107",
484 NULL, NULL, NULL, NULL),
485 _OMAP2420_MUXENTRY(VLYNQ_CLK, 13,
486 "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13",
487 NULL, NULL, NULL, NULL),
488 _OMAP2420_MUXENTRY(VLYNQ_NLA, 58,
489 "vlynq_nla", NULL, NULL, "gpio_58",
490 "cam_d6", NULL, NULL, NULL),
491 _OMAP2420_MUXENTRY(VLYNQ_RX0, 15,
492 "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15",
493 "cam_d7", NULL, NULL, NULL),
494 _OMAP2420_MUXENTRY(VLYNQ_RX1, 14,
495 "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14",
496 "cam_d8", NULL, NULL, NULL),
497 _OMAP2420_MUXENTRY(VLYNQ_TX0, 17,
498 "vlynq_tx0", "usb2_txen", NULL, "gpio_17",
499 NULL, NULL, NULL, NULL),
500 _OMAP2420_MUXENTRY(VLYNQ_TX1, 16,
501 "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16",
502 NULL, NULL, NULL, NULL),
503 { .reg_offset = OMAP_MUX_TERMINATOR },
504};
505
506/*
507 * Balls for 447-pin POP package
508 */
509#ifdef CONFIG_DEBUG_FS
510static struct omap_ball __initdata omap2420_pop_ball[] = {
511 _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
512 _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
513 _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
514 _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL),
515 _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL),
516 _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL),
517 _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL),
518 _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL),
519 _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL),
520 _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL),
521 _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL),
522 _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL),
523 _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL),
524 _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL),
525 _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL),
526 _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL),
527 _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL),
528 _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL),
529 _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL),
530 _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL),
531 _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL),
532 _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL),
533 _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL),
534 _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL),
535 _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL),
536 _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL),
537 _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL),
538 _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL),
539 _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL),
540 _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL),
541 _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL),
542 _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL),
543 _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL),
544 _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL),
545 _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL),
546 _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL),
547 _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL),
548 _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL),
549 _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL),
550 _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL),
551 _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL),
552 _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL),
553 _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL),
554 _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL),
555 _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL),
556 _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL),
557 _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL),
558 _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL),
559 _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL),
560 _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL),
561 _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL),
562 _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL),
563 _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL),
564 _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL),
565 _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"),
566 _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"),
567 _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"),
568 _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"),
569 _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"),
570 _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"),
571 _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"),
572 _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"),
573 _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"),
574 _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"),
575 _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL),
576 _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"),
577 _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL),
578 _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL),
579 _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL),
580 _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL),
581 _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL),
582 _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL),
583 _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"),
584 _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"),
585 _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL),
586 _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL),
587 _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL),
588 _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL),
589 _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL),
590 _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL),
591 _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL),
592 _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL),
593 _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL),
594 _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL),
595 _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL),
596 _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL),
597 _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL),
598 _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL),
599 _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL),
600 _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL),
601 _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL),
602 _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL),
603 _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL),
604 _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL),
605 _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL),
606 _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL),
607 _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL),
608 _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL),
609 _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL),
610 _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL),
611 _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL),
612 _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL),
613 _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"),
614 _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"),
615 _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"),
616 _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"),
617 _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"),
618 _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL),
619 _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL),
620 _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL),
621 _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL),
622 _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL),
623 _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL),
624 _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL),
625 _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL),
626 _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL),
627 _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL),
628 _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL),
629 _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL),
630 _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL),
631 _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL),
632 _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL),
633 _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL),
634 _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL),
635 _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL),
636 _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL),
637 _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL),
638 _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL),
639 _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL),
640 _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL),
641 _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL),
642 _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL),
643 _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL),
644 _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL),
645 _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL),
646 _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL),
647 _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL),
648 _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL),
649 _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
650 _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
651 _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL),
652 _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL),
653 _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL),
654 _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL),
655 _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL),
656 _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL),
657 _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL),
658 _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL),
659 _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL),
660 _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL),
661 _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL),
662 _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL),
663 _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL),
664 { .reg_offset = OMAP_MUX_TERMINATOR },
665};
666#else
667#define omap2420_pop_ball NULL
668#endif
669
670int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
671{
672 struct omap_ball *package_balls = NULL;
673
674 switch (flags & OMAP_PACKAGE_MASK) {
675 case OMAP_PACKAGE_ZAC:
676 package_balls = omap2420_pop_ball;
677 break;
678 case OMAP_PACKAGE_ZAF:
679 /* REVISIT: Please add data */
680 default:
681 pr_warning("%s: No ball data available for omap2420 package\n",
682 __func__);
683 }
684
685 return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
686 OMAP2420_CONTROL_PADCONF_MUX_PBASE,
687 OMAP2420_CONTROL_PADCONF_MUX_SIZE,
688 omap2420_muxmodes, NULL, board_subset,
689 package_balls);
690}
diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h
deleted file mode 100644
index 0f555aa847b5..000000000000
--- a/arch/arm/mach-omap2/mux2420.h
+++ /dev/null
@@ -1,282 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU
11
12#define OMAP2420_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x48000030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 8-bits wide.
24 */
25#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000
26#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001
27#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002
28#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003
29#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004
30#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005
31#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006
32#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007
33#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008
34#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009
35#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a
36#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b
37#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c
38#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d
39#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e
40#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f
41#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010
42#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021
43#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022
44#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023
45#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024
46#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025
47#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026
48#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027
49#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028
50#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029
51#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a
52#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b
53#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c
54#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d
55#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e
56#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f
57#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030
58#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031
59#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032
60#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033
61#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034
62#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035
63#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036
64#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037
65#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038
66#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039
67#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a
68#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b
69#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c
70#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d
71#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e
72#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f
73#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040
74#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041
75#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042
76#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043
77#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044
78#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045
79#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046
80#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047
81#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048
82#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049
83#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
84#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b
85#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c
86#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d
87#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e
88#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f
89#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050
90#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051
91#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052
92#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053
93#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054
94#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055
95#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056
96#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057
97#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058
98#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059
99#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a
100#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b
101#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c
102#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d
103#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e
104#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f
105#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060
106#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061
107#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062
108#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063
109#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064
110#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065
111#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066
112#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067
113#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068
114#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069
115#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a
116#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b
117#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c
118#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d
119#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e
120#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f
121#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070
122#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071
123#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072
124#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073
125#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074
126#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075
127#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076
128#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077
129#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078
130#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079
131#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a
132#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f
133#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080
134#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081
135#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082
136#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083
137#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084
138#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085
139#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086
140#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087
141#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088
142#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089
143#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a
144#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b
145#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c
146#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d
147#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e
148#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f
149#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090
150#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091
151#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092
152#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093
153#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094
154#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095
155#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096
156#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097
157#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098
158#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099
159#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a
160#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b
161#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c
162#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d
163#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e
164#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f
165#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0
166#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1
167#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2
168#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3
169#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4
170#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5
171#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6
172#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7
173#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8
174#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9
175#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa
176#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab
177#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac
178#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad
179#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae
180#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af
181#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0
182#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1
183#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2
184#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3
185#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4
186#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5
187#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6
188#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7
189#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8
190#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9
191#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba
192#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb
193#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc
194#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd
195#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be
196#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf
197#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0
198#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1
199#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2
200#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3
201#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4
202#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5
203#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6
204#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7
205#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8
206#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9
207#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca
208#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb
209#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc
210#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd
211#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce
212#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf
213#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0
214#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1
215#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2
216#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3
217#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4
218#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5
219#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6
220#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7
221#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8
222#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9
223#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da
224#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db
225#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc
226#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd
227#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de
228#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df
229#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0
230#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1
231#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2
232#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3
233#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4
234#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5
235#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6
236#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7
237#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8
238#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9
239#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea
240#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb
241#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec
242#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed
243#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee
244#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef
245#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0
246#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1
247#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2
248#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3
249#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4
250#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5
251#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6
252#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7
253#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8
254#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9
255#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa
256#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb
257#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc
258#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd
259#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe
260#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff
261#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100
262#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101
263#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102
264#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103
265#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104
266#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105
267#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106
268#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107
269#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108
270#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109
271#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a
272#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b
273#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c
274#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d
275#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e
276#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f
277#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110
278#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111
279#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112
280
281#define OMAP2420_CONTROL_PADCONF_MUX_SIZE \
282 (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1)
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
deleted file mode 100644
index 4185f92553db..000000000000
--- a/arch/arm/mach-omap2/mux2430.c
+++ /dev/null
@@ -1,793 +0,0 @@
1/*
2 * Copyright (C) 2010 Nokia
3 * Copyright (C) 2010 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP2430_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap2430
42 */
43static struct omap_mux __initdata omap2430_muxmodes[] = {
44 _OMAP2430_MUXENTRY(CAM_D0, 133,
45 "cam_d0", "hw_dbg0", "sti_dout", "gpio_133",
46 NULL, NULL, "etk_d2", "safe_mode"),
47 _OMAP2430_MUXENTRY(CAM_D10, 146,
48 "cam_d10", NULL, NULL, "gpio_146",
49 NULL, NULL, "etk_d12", "safe_mode"),
50 _OMAP2430_MUXENTRY(CAM_D11, 145,
51 "cam_d11", NULL, NULL, "gpio_145",
52 NULL, NULL, "etk_d13", "safe_mode"),
53 _OMAP2430_MUXENTRY(CAM_D1, 132,
54 "cam_d1", "hw_dbg1", "sti_din", "gpio_132",
55 NULL, NULL, "etk_d3", "safe_mode"),
56 _OMAP2430_MUXENTRY(CAM_D2, 129,
57 "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129",
58 NULL, NULL, "etk_d4", "safe_mode"),
59 _OMAP2430_MUXENTRY(CAM_D3, 128,
60 "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128",
61 NULL, NULL, "etk_d5", "safe_mode"),
62 _OMAP2430_MUXENTRY(CAM_D4, 143,
63 "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143",
64 NULL, NULL, "etk_d6", "safe_mode"),
65 _OMAP2430_MUXENTRY(CAM_D5, 112,
66 "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112",
67 NULL, NULL, "etk_d7", "safe_mode"),
68 _OMAP2430_MUXENTRY(CAM_D6, 137,
69 "cam_d6", "hw_dbg6", NULL, "gpio_137",
70 NULL, NULL, "etk_d8", "safe_mode"),
71 _OMAP2430_MUXENTRY(CAM_D7, 136,
72 "cam_d7", "hw_dbg7", NULL, "gpio_136",
73 NULL, NULL, "etk_d9", "safe_mode"),
74 _OMAP2430_MUXENTRY(CAM_D8, 135,
75 "cam_d8", "hw_dbg8", NULL, "gpio_135",
76 NULL, NULL, "etk_d10", "safe_mode"),
77 _OMAP2430_MUXENTRY(CAM_D9, 134,
78 "cam_d9", "hw_dbg9", NULL, "gpio_134",
79 NULL, NULL, "etk_d11", "safe_mode"),
80 _OMAP2430_MUXENTRY(CAM_HS, 11,
81 "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11",
82 NULL, NULL, "etk_d1", "safe_mode"),
83 _OMAP2430_MUXENTRY(CAM_LCLK, 0,
84 "cam_lclk", NULL, "mcbsp_clks", NULL,
85 NULL, NULL, "etk_c1", "safe_mode"),
86 _OMAP2430_MUXENTRY(CAM_VS, 12,
87 "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12",
88 NULL, NULL, "etk_d0", "safe_mode"),
89 _OMAP2430_MUXENTRY(CAM_XCLK, 0,
90 "cam_xclk", NULL, "sti_clk", NULL,
91 NULL, NULL, "etk_c2", NULL),
92 _OMAP2430_MUXENTRY(DSS_ACBIAS, 48,
93 "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
94 NULL, NULL, NULL, "safe_mode"),
95 _OMAP2430_MUXENTRY(DSS_DATA0, 40,
96 "dss_data0", "uart1_cts", NULL, "gpio_40",
97 NULL, NULL, NULL, "safe_mode"),
98 _OMAP2430_MUXENTRY(DSS_DATA10, 128,
99 "dss_data10", "sdi_data1n", NULL, "gpio_128",
100 NULL, NULL, NULL, "safe_mode"),
101 _OMAP2430_MUXENTRY(DSS_DATA11, 129,
102 "dss_data11", "sdi_data1p", NULL, "gpio_129",
103 NULL, NULL, NULL, "safe_mode"),
104 _OMAP2430_MUXENTRY(DSS_DATA12, 130,
105 "dss_data12", "sdi_data2n", NULL, "gpio_130",
106 NULL, NULL, NULL, "safe_mode"),
107 _OMAP2430_MUXENTRY(DSS_DATA13, 131,
108 "dss_data13", "sdi_data2p", NULL, "gpio_131",
109 NULL, NULL, NULL, "safe_mode"),
110 _OMAP2430_MUXENTRY(DSS_DATA14, 132,
111 "dss_data14", "sdi_data3n", NULL, "gpio_132",
112 NULL, NULL, NULL, "safe_mode"),
113 _OMAP2430_MUXENTRY(DSS_DATA15, 133,
114 "dss_data15", "sdi_data3p", NULL, "gpio_133",
115 NULL, NULL, NULL, "safe_mode"),
116 _OMAP2430_MUXENTRY(DSS_DATA16, 46,
117 "dss_data16", NULL, NULL, "gpio_46",
118 NULL, NULL, NULL, "safe_mode"),
119 _OMAP2430_MUXENTRY(DSS_DATA17, 47,
120 "dss_data17", NULL, NULL, "gpio_47",
121 NULL, NULL, NULL, "safe_mode"),
122 _OMAP2430_MUXENTRY(DSS_DATA1, 41,
123 "dss_data1", "uart1_rts", NULL, "gpio_41",
124 NULL, NULL, NULL, "safe_mode"),
125 _OMAP2430_MUXENTRY(DSS_DATA2, 42,
126 "dss_data2", "uart1_tx", NULL, "gpio_42",
127 NULL, NULL, NULL, "safe_mode"),
128 _OMAP2430_MUXENTRY(DSS_DATA3, 43,
129 "dss_data3", "uart1_rx", NULL, "gpio_43",
130 NULL, NULL, NULL, "safe_mode"),
131 _OMAP2430_MUXENTRY(DSS_DATA4, 44,
132 "dss_data4", "uart3_rx_irrx", NULL, "gpio_44",
133 NULL, NULL, NULL, "safe_mode"),
134 _OMAP2430_MUXENTRY(DSS_DATA5, 45,
135 "dss_data5", "uart3_tx_irtx", NULL, "gpio_45",
136 NULL, NULL, NULL, "safe_mode"),
137 _OMAP2430_MUXENTRY(DSS_DATA6, 144,
138 "dss_data6", NULL, NULL, "gpio_144",
139 NULL, NULL, NULL, "safe_mode"),
140 _OMAP2430_MUXENTRY(DSS_DATA7, 147,
141 "dss_data7", NULL, NULL, "gpio_147",
142 NULL, NULL, NULL, "safe_mode"),
143 _OMAP2430_MUXENTRY(DSS_DATA8, 38,
144 "dss_data8", NULL, NULL, "gpio_38",
145 NULL, NULL, NULL, "safe_mode"),
146 _OMAP2430_MUXENTRY(DSS_DATA9, 39,
147 "dss_data9", NULL, NULL, "gpio_39",
148 NULL, NULL, NULL, "safe_mode"),
149 _OMAP2430_MUXENTRY(DSS_HSYNC, 110,
150 "dss_hsync", NULL, NULL, "gpio_110",
151 NULL, NULL, NULL, "safe_mode"),
152 _OMAP2430_MUXENTRY(GPIO_113, 113,
153 "gpio_113", "mcbsp2_clkx", NULL, "gpio_113",
154 NULL, NULL, NULL, "safe_mode"),
155 _OMAP2430_MUXENTRY(GPIO_114, 114,
156 "gpio_114", "mcbsp2_fsx", NULL, "gpio_114",
157 NULL, NULL, NULL, "safe_mode"),
158 _OMAP2430_MUXENTRY(GPIO_115, 115,
159 "gpio_115", "mcbsp2_dr", NULL, "gpio_115",
160 NULL, NULL, NULL, "safe_mode"),
161 _OMAP2430_MUXENTRY(GPIO_116, 116,
162 "gpio_116", "mcbsp2_dx", NULL, "gpio_116",
163 NULL, NULL, NULL, "safe_mode"),
164 _OMAP2430_MUXENTRY(GPIO_128, 128,
165 "gpio_128", NULL, "sti_din", "gpio_128",
166 NULL, "sys_boot0", NULL, "safe_mode"),
167 _OMAP2430_MUXENTRY(GPIO_129, 129,
168 "gpio_129", NULL, "sti_dout", "gpio_129",
169 NULL, "sys_boot1", NULL, "safe_mode"),
170 _OMAP2430_MUXENTRY(GPIO_130, 130,
171 "gpio_130", NULL, NULL, "gpio_130",
172 "jtag_emu2", "sys_boot2", NULL, "safe_mode"),
173 _OMAP2430_MUXENTRY(GPIO_131, 131,
174 "gpio_131", NULL, NULL, "gpio_131",
175 "jtag_emu3", "sys_boot3", NULL, "safe_mode"),
176 _OMAP2430_MUXENTRY(GPIO_132, 132,
177 "gpio_132", NULL, NULL, "gpio_132",
178 NULL, "sys_boot4", NULL, "safe_mode"),
179 _OMAP2430_MUXENTRY(GPIO_133, 133,
180 "gpio_133", NULL, NULL, "gpio_133",
181 NULL, "sys_boot5", NULL, "safe_mode"),
182 _OMAP2430_MUXENTRY(GPIO_134, 134,
183 "gpio_134", "ccp_datn", NULL, "gpio_134",
184 NULL, NULL, NULL, "safe_mode"),
185 _OMAP2430_MUXENTRY(GPIO_135, 135,
186 "gpio_135", "ccp_datp", NULL, "gpio_135",
187 NULL, NULL, NULL, "safe_mode"),
188 _OMAP2430_MUXENTRY(GPIO_136, 136,
189 "gpio_136", "ccp_clkn", NULL, "gpio_136",
190 NULL, NULL, NULL, "safe_mode"),
191 _OMAP2430_MUXENTRY(GPIO_137, 137,
192 "gpio_137", "ccp_clkp", NULL, "gpio_137",
193 NULL, NULL, NULL, "safe_mode"),
194 _OMAP2430_MUXENTRY(GPIO_138, 138,
195 "gpio_138", "spi3_clk", NULL, "gpio_138",
196 NULL, NULL, NULL, "safe_mode"),
197 _OMAP2430_MUXENTRY(GPIO_139, 139,
198 "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139",
199 NULL, NULL, NULL, "safe_mode"),
200 _OMAP2430_MUXENTRY(GPIO_140, 140,
201 "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140",
202 NULL, NULL, "etk_d14", "safe_mode"),
203 _OMAP2430_MUXENTRY(GPIO_141, 141,
204 "gpio_141", "spi3_somi", NULL, "gpio_141",
205 NULL, NULL, NULL, "safe_mode"),
206 _OMAP2430_MUXENTRY(GPIO_142, 142,
207 "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142",
208 NULL, NULL, "etk_d15", "safe_mode"),
209 _OMAP2430_MUXENTRY(GPIO_148, 148,
210 "gpio_148", "mcbsp5_fsx", NULL, "gpio_148",
211 NULL, NULL, NULL, "safe_mode"),
212 _OMAP2430_MUXENTRY(GPIO_149, 149,
213 "gpio_149", "mcbsp5_dx", NULL, "gpio_149",
214 NULL, NULL, NULL, "safe_mode"),
215 _OMAP2430_MUXENTRY(GPIO_150, 150,
216 "gpio_150", "mcbsp5_dr", NULL, "gpio_150",
217 NULL, NULL, NULL, "safe_mode"),
218 _OMAP2430_MUXENTRY(GPIO_151, 151,
219 "gpio_151", "sys_pwrok", NULL, "gpio_151",
220 NULL, NULL, NULL, "safe_mode"),
221 _OMAP2430_MUXENTRY(GPIO_152, 152,
222 "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152",
223 NULL, NULL, NULL, "safe_mode"),
224 _OMAP2430_MUXENTRY(GPIO_153, 153,
225 "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153",
226 NULL, NULL, NULL, "safe_mode"),
227 _OMAP2430_MUXENTRY(GPIO_154, 154,
228 "gpio_154", "mcbsp5_clkx", NULL, "gpio_154",
229 NULL, NULL, NULL, "safe_mode"),
230 _OMAP2430_MUXENTRY(GPIO_63, 63,
231 "gpio_63", "mcbsp4_clkx", NULL, "gpio_63",
232 NULL, NULL, NULL, "safe_mode"),
233 _OMAP2430_MUXENTRY(GPIO_78, 78,
234 "gpio_78", NULL, "uart2_rts", "gpio_78",
235 "uart3_rts_sd", NULL, NULL, "safe_mode"),
236 _OMAP2430_MUXENTRY(GPIO_79, 79,
237 "gpio_79", "secure_indicator", "uart2_tx", "gpio_79",
238 "uart3_tx_irtx", NULL, NULL, "safe_mode"),
239 _OMAP2430_MUXENTRY(GPIO_7, 7,
240 "gpio_7", NULL, "uart2_cts", "gpio_7",
241 "uart3_cts_rctx", NULL, NULL, "safe_mode"),
242 _OMAP2430_MUXENTRY(GPIO_80, 80,
243 "gpio_80", NULL, "uart2_rx", "gpio_80",
244 "uart3_rx_irrx", NULL, NULL, "safe_mode"),
245 _OMAP2430_MUXENTRY(GPMC_A10, 3,
246 "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3",
247 NULL, NULL, NULL, "safe_mode"),
248 _OMAP2430_MUXENTRY(GPMC_A1, 31,
249 "gpmc_a1", NULL, NULL, "gpio_31",
250 NULL, NULL, NULL, "safe_mode"),
251 _OMAP2430_MUXENTRY(GPMC_A2, 30,
252 "gpmc_a2", NULL, NULL, "gpio_30",
253 NULL, NULL, NULL, "safe_mode"),
254 _OMAP2430_MUXENTRY(GPMC_A3, 29,
255 "gpmc_a3", NULL, NULL, "gpio_29",
256 NULL, NULL, NULL, "safe_mode"),
257 _OMAP2430_MUXENTRY(GPMC_A4, 49,
258 "gpmc_a4", NULL, NULL, "gpio_49",
259 NULL, NULL, NULL, "safe_mode"),
260 _OMAP2430_MUXENTRY(GPMC_A5, 53,
261 "gpmc_a5", NULL, NULL, "gpio_53",
262 NULL, NULL, NULL, "safe_mode"),
263 _OMAP2430_MUXENTRY(GPMC_A6, 52,
264 "gpmc_a6", NULL, NULL, "gpio_52",
265 NULL, NULL, NULL, "safe_mode"),
266 _OMAP2430_MUXENTRY(GPMC_A7, 6,
267 "gpmc_a7", NULL, NULL, "gpio_6",
268 NULL, NULL, NULL, "safe_mode"),
269 _OMAP2430_MUXENTRY(GPMC_A8, 5,
270 "gpmc_a8", NULL, NULL, "gpio_5",
271 NULL, NULL, NULL, "safe_mode"),
272 _OMAP2430_MUXENTRY(GPMC_A9, 4,
273 "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4",
274 NULL, NULL, NULL, "safe_mode"),
275 _OMAP2430_MUXENTRY(GPMC_CLK, 21,
276 "gpmc_clk", NULL, NULL, "gpio_21",
277 NULL, NULL, NULL, "safe_mode"),
278 _OMAP2430_MUXENTRY(GPMC_D10, 18,
279 "gpmc_d10", NULL, NULL, "gpio_18",
280 NULL, NULL, NULL, "safe_mode"),
281 _OMAP2430_MUXENTRY(GPMC_D11, 57,
282 "gpmc_d11", NULL, NULL, "gpio_57",
283 NULL, NULL, NULL, "safe_mode"),
284 _OMAP2430_MUXENTRY(GPMC_D12, 77,
285 "gpmc_d12", NULL, NULL, "gpio_77",
286 NULL, NULL, NULL, "safe_mode"),
287 _OMAP2430_MUXENTRY(GPMC_D13, 76,
288 "gpmc_d13", NULL, NULL, "gpio_76",
289 NULL, NULL, NULL, "safe_mode"),
290 _OMAP2430_MUXENTRY(GPMC_D14, 55,
291 "gpmc_d14", NULL, NULL, "gpio_55",
292 NULL, NULL, NULL, "safe_mode"),
293 _OMAP2430_MUXENTRY(GPMC_D15, 54,
294 "gpmc_d15", NULL, NULL, "gpio_54",
295 NULL, NULL, NULL, "safe_mode"),
296 _OMAP2430_MUXENTRY(GPMC_D8, 20,
297 "gpmc_d8", NULL, NULL, "gpio_20",
298 NULL, NULL, NULL, "safe_mode"),
299 _OMAP2430_MUXENTRY(GPMC_D9, 19,
300 "gpmc_d9", NULL, NULL, "gpio_19",
301 NULL, NULL, NULL, "safe_mode"),
302 _OMAP2430_MUXENTRY(GPMC_NCS1, 22,
303 "gpmc_ncs1", NULL, NULL, "gpio_22",
304 NULL, NULL, NULL, "safe_mode"),
305 _OMAP2430_MUXENTRY(GPMC_NCS2, 23,
306 "gpmc_ncs2", NULL, NULL, "gpio_23",
307 NULL, NULL, NULL, "safe_mode"),
308 _OMAP2430_MUXENTRY(GPMC_NCS3, 24,
309 "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
310 NULL, NULL, NULL, "safe_mode"),
311 _OMAP2430_MUXENTRY(GPMC_NCS4, 25,
312 "gpmc_ncs4", NULL, NULL, "gpio_25",
313 NULL, NULL, NULL, "safe_mode"),
314 _OMAP2430_MUXENTRY(GPMC_NCS5, 26,
315 "gpmc_ncs5", NULL, NULL, "gpio_26",
316 NULL, NULL, NULL, "safe_mode"),
317 _OMAP2430_MUXENTRY(GPMC_NCS6, 27,
318 "gpmc_ncs6", NULL, NULL, "gpio_27",
319 NULL, NULL, NULL, "safe_mode"),
320 _OMAP2430_MUXENTRY(GPMC_NCS7, 28,
321 "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28",
322 NULL, NULL, NULL, "safe_mode"),
323 _OMAP2430_MUXENTRY(GPMC_WAIT1, 33,
324 "gpmc_wait1", NULL, NULL, "gpio_33",
325 NULL, NULL, NULL, "safe_mode"),
326 _OMAP2430_MUXENTRY(GPMC_WAIT2, 34,
327 "gpmc_wait2", NULL, NULL, "gpio_34",
328 NULL, NULL, NULL, "safe_mode"),
329 _OMAP2430_MUXENTRY(GPMC_WAIT3, 35,
330 "gpmc_wait3", NULL, NULL, "gpio_35",
331 NULL, NULL, NULL, "safe_mode"),
332 _OMAP2430_MUXENTRY(HDQ_SIO, 101,
333 "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
334 "uart3_rx_irrx", NULL, NULL, "safe_mode"),
335 _OMAP2430_MUXENTRY(I2C1_SCL, 50,
336 "i2c1_scl", NULL, NULL, "gpio_50",
337 NULL, NULL, NULL, "safe_mode"),
338 _OMAP2430_MUXENTRY(I2C1_SDA, 51,
339 "i2c1_sda", NULL, NULL, "gpio_51",
340 NULL, NULL, NULL, "safe_mode"),
341 _OMAP2430_MUXENTRY(I2C2_SCL, 99,
342 "i2c2_scl", NULL, NULL, "gpio_99",
343 NULL, NULL, NULL, "safe_mode"),
344 _OMAP2430_MUXENTRY(I2C2_SDA, 100,
345 "i2c2_sda", NULL, NULL, "gpio_100",
346 NULL, NULL, NULL, "safe_mode"),
347 _OMAP2430_MUXENTRY(JTAG_EMU0, 127,
348 "jtag_emu0", "secure_indicator", NULL, "gpio_127",
349 NULL, NULL, NULL, "safe_mode"),
350 _OMAP2430_MUXENTRY(JTAG_EMU1, 126,
351 "jtag_emu1", NULL, NULL, "gpio_126",
352 NULL, NULL, NULL, "safe_mode"),
353 _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92,
354 "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92",
355 NULL, NULL, NULL, "safe_mode"),
356 _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98,
357 "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98",
358 NULL, NULL, NULL, "safe_mode"),
359 _OMAP2430_MUXENTRY(MCBSP1_DR, 95,
360 "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95",
361 NULL, NULL, NULL, "safe_mode"),
362 _OMAP2430_MUXENTRY(MCBSP1_DX, 94,
363 "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94",
364 NULL, NULL, NULL, "safe_mode"),
365 _OMAP2430_MUXENTRY(MCBSP1_FSR, 93,
366 "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93",
367 "spi2_cs1", NULL, NULL, "safe_mode"),
368 _OMAP2430_MUXENTRY(MCBSP1_FSX, 97,
369 "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
370 NULL, NULL, NULL, "safe_mode"),
371 _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147,
372 "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147",
373 NULL, NULL, NULL, "safe_mode"),
374 _OMAP2430_MUXENTRY(MCBSP2_DR, 144,
375 "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144",
376 NULL, NULL, NULL, "safe_mode"),
377 _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71,
378 "mcbsp3_clkx", NULL, NULL, "gpio_71",
379 NULL, NULL, NULL, "safe_mode"),
380 _OMAP2430_MUXENTRY(MCBSP3_DR, 73,
381 "mcbsp3_dr", NULL, NULL, "gpio_73",
382 NULL, NULL, NULL, "safe_mode"),
383 _OMAP2430_MUXENTRY(MCBSP3_DX, 74,
384 "mcbsp3_dx", NULL, "sti_clk", "gpio_74",
385 NULL, NULL, NULL, "safe_mode"),
386 _OMAP2430_MUXENTRY(MCBSP3_FSX, 72,
387 "mcbsp3_fsx", NULL, NULL, "gpio_72",
388 NULL, NULL, NULL, "safe_mode"),
389 _OMAP2430_MUXENTRY(MCBSP_CLKS, 96,
390 "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96",
391 NULL, NULL, NULL, "safe_mode"),
392 _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0,
393 "sdmmc1_clko", "ms_clko", NULL, NULL,
394 NULL, "hw_dbg9", "hw_dbg3", "safe_mode"),
395 _OMAP2430_MUXENTRY(SDMMC1_CMD, 0,
396 "sdmmc1_cmd", "ms_bs", NULL, NULL,
397 NULL, "hw_dbg8", "hw_dbg2", "safe_mode"),
398 _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0,
399 "sdmmc1_dat0", "ms_dat0", NULL, NULL,
400 NULL, "hw_dbg7", "hw_dbg1", "safe_mode"),
401 _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75,
402 "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75",
403 NULL, "hw_dbg6", "hw_dbg0", "safe_mode"),
404 _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0,
405 "sdmmc1_dat2", "ms_dat2", NULL, NULL,
406 NULL, "hw_dbg5", "hw_dbg10", "safe_mode"),
407 _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0,
408 "sdmmc1_dat3", "ms_dat3", NULL, NULL,
409 NULL, "hw_dbg4", "hw_dbg11", "safe_mode"),
410 _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13,
411 "sdmmc2_clko", NULL, NULL, "gpio_13",
412 NULL, "spi3_clk", NULL, "safe_mode"),
413 _OMAP2430_MUXENTRY(SDMMC2_CMD, 15,
414 "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15",
415 NULL, "spi3_simo", NULL, "safe_mode"),
416 _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16,
417 "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16",
418 NULL, "spi3_somi", NULL, "safe_mode"),
419 _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58,
420 "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58",
421 NULL, NULL, NULL, "safe_mode"),
422 _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17,
423 "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17",
424 NULL, "spi3_cs1", NULL, "safe_mode"),
425 _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14,
426 "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14",
427 NULL, "spi3_cs0", NULL, "safe_mode"),
428 _OMAP2430_MUXENTRY(SDRC_A12, 2,
429 "sdrc_a12", NULL, NULL, "gpio_2",
430 NULL, NULL, NULL, "safe_mode"),
431 _OMAP2430_MUXENTRY(SDRC_A13, 1,
432 "sdrc_a13", NULL, NULL, "gpio_1",
433 NULL, NULL, NULL, "safe_mode"),
434 _OMAP2430_MUXENTRY(SDRC_A14, 0,
435 "sdrc_a14", NULL, NULL, "gpio_0",
436 NULL, NULL, NULL, "safe_mode"),
437 _OMAP2430_MUXENTRY(SDRC_CKE1, 36,
438 "sdrc_cke1", NULL, NULL, "gpio_36",
439 NULL, NULL, NULL, "safe_mode"),
440 _OMAP2430_MUXENTRY(SDRC_NCS1, 37,
441 "sdrc_ncs1", NULL, NULL, "gpio_37",
442 NULL, NULL, NULL, "safe_mode"),
443 _OMAP2430_MUXENTRY(SPI1_CLK, 81,
444 "spi1_clk", NULL, NULL, "gpio_81",
445 NULL, NULL, NULL, "safe_mode"),
446 _OMAP2430_MUXENTRY(SPI1_CS0, 84,
447 "spi1_cs0", NULL, NULL, "gpio_84",
448 NULL, NULL, NULL, "safe_mode"),
449 _OMAP2430_MUXENTRY(SPI1_CS1, 85,
450 "spi1_cs1", NULL, NULL, "gpio_85",
451 NULL, NULL, NULL, "safe_mode"),
452 _OMAP2430_MUXENTRY(SPI1_CS2, 86,
453 "spi1_cs2", NULL, NULL, "gpio_86",
454 NULL, NULL, NULL, "safe_mode"),
455 _OMAP2430_MUXENTRY(SPI1_CS3, 87,
456 "spi1_cs3", "spi2_cs1", NULL, "gpio_87",
457 NULL, NULL, NULL, "safe_mode"),
458 _OMAP2430_MUXENTRY(SPI1_SIMO, 82,
459 "spi1_simo", NULL, NULL, "gpio_82",
460 NULL, NULL, NULL, "safe_mode"),
461 _OMAP2430_MUXENTRY(SPI1_SOMI, 83,
462 "spi1_somi", NULL, NULL, "gpio_83",
463 NULL, NULL, NULL, "safe_mode"),
464 _OMAP2430_MUXENTRY(SPI2_CLK, 88,
465 "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88",
466 NULL, NULL, NULL, "safe_mode"),
467 _OMAP2430_MUXENTRY(SPI2_CS0, 91,
468 "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91",
469 NULL, NULL, NULL, "safe_mode"),
470 _OMAP2430_MUXENTRY(SPI2_SIMO, 89,
471 "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
472 NULL, NULL, NULL, "safe_mode"),
473 _OMAP2430_MUXENTRY(SPI2_SOMI, 90,
474 "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
475 NULL, NULL, NULL, "safe_mode"),
476 _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62,
477 "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62",
478 NULL, NULL, NULL, "safe_mode"),
479 _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59,
480 "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
481 NULL, NULL, NULL, "safe_mode"),
482 _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64,
483 "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64",
484 NULL, NULL, NULL, "safe_mode"),
485 _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60,
486 "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60",
487 NULL, NULL, NULL, "safe_mode"),
488 _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65,
489 "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65",
490 NULL, NULL, NULL, "safe_mode"),
491 _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61,
492 "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
493 NULL, NULL, NULL, "safe_mode"),
494 _OMAP2430_MUXENTRY(SSI1_WAKE, 66,
495 "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66",
496 NULL, NULL, NULL, "safe_mode"),
497 _OMAP2430_MUXENTRY(SYS_CLKOUT, 111,
498 "sys_clkout", NULL, NULL, "gpio_111",
499 NULL, NULL, NULL, "safe_mode"),
500 _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118,
501 "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118",
502 NULL, NULL, NULL, "safe_mode"),
503 _OMAP2430_MUXENTRY(SYS_NIRQ0, 56,
504 "sys_nirq0", NULL, NULL, "gpio_56",
505 NULL, NULL, NULL, "safe_mode"),
506 _OMAP2430_MUXENTRY(SYS_NIRQ1, 125,
507 "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125",
508 NULL, NULL, NULL, "safe_mode"),
509 _OMAP2430_MUXENTRY(UART1_CTS, 32,
510 "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32",
511 "mcbsp5_clkx", NULL, NULL, "safe_mode"),
512 _OMAP2430_MUXENTRY(UART1_RTS, 8,
513 "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8",
514 "mcbsp5_fsx", NULL, NULL, "safe_mode"),
515 _OMAP2430_MUXENTRY(UART1_RX, 10,
516 "uart1_rx", "sdi_stp", "dss_data21", "gpio_10",
517 "mcbsp5_dr", NULL, NULL, "safe_mode"),
518 _OMAP2430_MUXENTRY(UART1_TX, 9,
519 "uart1_tx", "sdi_den", "dss_data20", "gpio_9",
520 "mcbsp5_dx", NULL, NULL, "safe_mode"),
521 _OMAP2430_MUXENTRY(UART2_CTS, 67,
522 "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
523 NULL, NULL, NULL, "safe_mode"),
524 _OMAP2430_MUXENTRY(UART2_RTS, 68,
525 "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
526 NULL, NULL, NULL, "safe_mode"),
527 _OMAP2430_MUXENTRY(UART2_RX, 70,
528 "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
529 NULL, NULL, NULL, "safe_mode"),
530 _OMAP2430_MUXENTRY(UART2_TX, 69,
531 "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
532 NULL, NULL, NULL, "safe_mode"),
533 _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102,
534 "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
535 NULL, NULL, NULL, "safe_mode"),
536 _OMAP2430_MUXENTRY(UART3_RTS_SD, 103,
537 "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
538 NULL, NULL, NULL, "safe_mode"),
539 _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105,
540 "uart3_rx_irrx", NULL, NULL, "gpio_105",
541 NULL, NULL, NULL, "safe_mode"),
542 _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104,
543 "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
544 NULL, NULL, NULL, "safe_mode"),
545 _OMAP2430_MUXENTRY(USB0HS_CLK, 120,
546 "usb0hs_clk", NULL, NULL, "gpio_120",
547 NULL, NULL, NULL, "safe_mode"),
548 _OMAP2430_MUXENTRY(USB0HS_DATA0, 0,
549 "usb0hs_data0", "uart3_tx_irtx", NULL, NULL,
550 "usb0_txen", NULL, NULL, "safe_mode"),
551 _OMAP2430_MUXENTRY(USB0HS_DATA1, 0,
552 "usb0hs_data1", "uart3_rx_irrx", NULL, NULL,
553 "usb0_dat", NULL, NULL, "safe_mode"),
554 _OMAP2430_MUXENTRY(USB0HS_DATA2, 0,
555 "usb0hs_data2", "uart3_rts_sd", NULL, NULL,
556 "usb0_se0", NULL, NULL, "safe_mode"),
557 _OMAP2430_MUXENTRY(USB0HS_DATA3, 106,
558 "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106",
559 "usb0_puen", NULL, NULL, "safe_mode"),
560 _OMAP2430_MUXENTRY(USB0HS_DATA4, 107,
561 "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107",
562 "usb0_vp", NULL, NULL, "safe_mode"),
563 _OMAP2430_MUXENTRY(USB0HS_DATA5, 108,
564 "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108",
565 "usb0_vm", NULL, NULL, "safe_mode"),
566 _OMAP2430_MUXENTRY(USB0HS_DATA6, 109,
567 "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109",
568 "usb0_rcv", NULL, NULL, "safe_mode"),
569 _OMAP2430_MUXENTRY(USB0HS_DATA7, 124,
570 "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124",
571 NULL, NULL, NULL, "safe_mode"),
572 _OMAP2430_MUXENTRY(USB0HS_DIR, 121,
573 "usb0hs_dir", NULL, NULL, "gpio_121",
574 NULL, NULL, NULL, "safe_mode"),
575 _OMAP2430_MUXENTRY(USB0HS_NXT, 123,
576 "usb0hs_nxt", NULL, NULL, "gpio_123",
577 NULL, NULL, NULL, "safe_mode"),
578 _OMAP2430_MUXENTRY(USB0HS_STP, 122,
579 "usb0hs_stp", NULL, NULL, "gpio_122",
580 NULL, NULL, NULL, "safe_mode"),
581 { .reg_offset = OMAP_MUX_TERMINATOR },
582};
583
584/*
585 * Balls for POP package
586 * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom)
587 */
588#ifdef CONFIG_DEBUG_FS
589static struct omap_ball __initdata omap2430_pop_ball[] = {
590 _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL),
591 _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL),
592 _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL),
593 _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL),
594 _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL),
595 _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL),
596 _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL),
597 _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL),
598 _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL),
599 _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL),
600 _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL),
601 _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL),
602 _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL),
603 _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL),
604 _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL),
605 _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL),
606 _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL),
607 _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL),
608 _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL),
609 _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL),
610 _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL),
611 _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL),
612 _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL),
613 _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL),
614 _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL),
615 _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL),
616 _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL),
617 _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL),
618 _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL),
619 _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL),
620 _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL),
621 _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL),
622 _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL),
623 _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL),
624 _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL),
625 _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL),
626 _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL),
627 _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL),
628 _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL),
629 _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL),
630 _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL),
631 _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL),
632 _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL),
633 _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL),
634 _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL),
635 _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL),
636 _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL),
637 _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL),
638 _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL),
639 _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL),
640 _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL),
641 _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL),
642 _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL),
643 _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL),
644 _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL),
645 _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL),
646 _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL),
647 _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL),
648 _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL),
649 _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL),
650 _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL),
651 _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL),
652 _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL),
653 _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL),
654 _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL),
655 _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL),
656 _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL),
657 _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL),
658 _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL),
659 _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL),
660 _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL),
661 _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL),
662 _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL),
663 _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL),
664 _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL),
665 _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL),
666 _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL),
667 _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"),
668 _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"),
669 _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"),
670 _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"),
671 _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"),
672 _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"),
673 _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"),
674 _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"),
675 _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"),
676 _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"),
677 _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL),
678 _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL),
679 _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL),
680 _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL),
681 _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL),
682 _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL),
683 _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"),
684 _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL),
685 _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL),
686 _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL),
687 _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL),
688 _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL),
689 _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL),
690 _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL),
691 _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL),
692 _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL),
693 _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL),
694 _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL),
695 _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL),
696 _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL),
697 _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL),
698 _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL),
699 _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL),
700 _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL),
701 _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL),
702 _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL),
703 _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL),
704 _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL),
705 _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL),
706 _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL),
707 _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL),
708 _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL),
709 _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL),
710 _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL),
711 _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL),
712 _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL),
713 _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL),
714 _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL),
715 _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL),
716 _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL),
717 _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL),
718 _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"),
719 _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"),
720 _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"),
721 _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"),
722 _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"),
723 _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL),
724 _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL),
725 _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL),
726 _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL),
727 _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL),
728 _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL),
729 _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL),
730 _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL),
731 _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL),
732 _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL),
733 _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL),
734 _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL),
735 _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL),
736 _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL),
737 _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL),
738 _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL),
739 _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL),
740 _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL),
741 _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL),
742 _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL),
743 _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL),
744 _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL),
745 _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL),
746 _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL),
747 _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL),
748 _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL),
749 _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL),
750 _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL),
751 _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL),
752 _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL),
753 _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL),
754 _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL),
755 _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL),
756 _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL),
757 _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL),
758 _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL),
759 _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL),
760 _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL),
761 _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL),
762 _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL),
763 _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL),
764 _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL),
765 _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL),
766 _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL),
767 _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL),
768 _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL),
769 { .reg_offset = OMAP_MUX_TERMINATOR },
770};
771#else
772#define omap2430_pop_ball NULL
773#endif
774
775int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
776{
777 struct omap_ball *package_balls = NULL;
778
779 switch (flags & OMAP_PACKAGE_MASK) {
780 case OMAP_PACKAGE_ZAC:
781 package_balls = omap2430_pop_ball;
782 break;
783 default:
784 pr_warning("%s: No ball data available for omap2420 package\n",
785 __func__);
786 }
787
788 return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
789 OMAP2430_CONTROL_PADCONF_MUX_PBASE,
790 OMAP2430_CONTROL_PADCONF_MUX_SIZE,
791 omap2430_muxmodes, NULL, board_subset,
792 package_balls);
793}
diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h
deleted file mode 100644
index 9fd93149ebd9..000000000000
--- a/arch/arm/mach-omap2/mux2430.h
+++ /dev/null
@@ -1,370 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP2430_CONTROL_PADCONF_MUX_PBASE 0x49002030LU
11
12#define OMAP2430_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x49002030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 8-bits wide.
24 *
25 * Note that these defines use SDMMC instead of MMC for compatibility
26 * with signal names used in 3630.
27 */
28#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000
29#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x001
30#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x002
31#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x003
32#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x004
33#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x005
34#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x006
35#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x007
36#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x008
37#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x009
38#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET 0x00a
39#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x00b
40#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x00c
41#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x00d
42#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x00e
43#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x00f
44#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x010
45#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x011
46#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x012
47#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x013
48#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x014
49#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x015
50#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x016
51#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x017
52#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x018
53#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x019
54#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x01a
55#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x01b
56#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x01c
57#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x01d
58#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x01e
59#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x01f
60#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x020
61#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x021
62#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x022
63#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x023
64#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET 0x024
65#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET 0x025
66#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET 0x026
67#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x027
68#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x028
69#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET 0x029
70#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET 0x02a
71#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET 0x02b
72#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET 0x02c
73#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET 0x02d
74#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET 0x02e
75#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET 0x02f
76#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET 0x030
77#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET 0x031
78#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET 0x032
79#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET 0x033
80#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET 0x034
81#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET 0x035
82#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET 0x036
83#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET 0x037
84#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
85#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET 0x039
86#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET 0x03a
87#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET 0x03b
88#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET 0x03c
89#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET 0x03d
90#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET 0x03e
91#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET 0x03f
92#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET 0x040
93#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET 0x041
94#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET 0x042
95#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET 0x043
96#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET 0x044
97#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET 0x045
98#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET 0x046
99#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET 0x047
100#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET 0x048
101#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET 0x049
102#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET 0x04a
103#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET 0x04b
104#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET 0x04c
105#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET 0x04d
106#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET 0x04e
107#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET 0x04f
108#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET 0x050
109#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET 0x051
110#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET 0x052
111#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET 0x053
112#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET 0x054
113#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET 0x055
114#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET 0x056
115#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET 0x057
116#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET 0x058
117#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET 0x059
118#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET 0x05a
119#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET 0x05b
120#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET 0x05c
121#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET 0x05d
122#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET 0x05e
123#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET 0x05f
124#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET 0x060
125#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET 0x061
126#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET 0x062
127#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET 0x063
128#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET 0x064
129#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET 0x065
130#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET 0x066
131#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET 0x067
132#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET 0x068
133#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET 0x069
134#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET 0x06a
135#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET 0x06b
136#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET 0x06c
137#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET 0x06d
138#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET 0x06e
139#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x06f
140#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x070
141#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x071
142#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x072
143#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x073
144#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x074
145#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x075
146#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x076
147#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x077
148#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x078
149#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x079
150#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x07a
151#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x07b
152#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x07c
153#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x07d
154#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x07e
155#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x07f
156#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x080
157#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET 0x081
158#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET 0x082
159#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET 0x083
160#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET 0x084
161#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x085
162#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x086
163#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x087
164#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x088
165#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x089
166#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x08a
167#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x08b
168#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x08c
169#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET 0x08d
170#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET 0x08e
171#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET 0x08f
172#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET 0x090
173#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET 0x091
174#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET 0x092
175#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET 0x093
176#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET 0x094
177#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x095
178#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x096
179#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET 0x097
180#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x098
181#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x099
182#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET 0x09a
183#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET 0x09b
184#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x09c
185#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x09d
186#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x09e
187#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x09f
188#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x0a0
189#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x0a1
190#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x0a2
191#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x0a3
192#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET 0x0a4
193#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a5
194#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a6
195#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a7
196#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a8
197#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a9
198#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET 0x0aa
199#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ab
200#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET 0x0ac
201#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET 0x0ad
202#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET 0x0ae
203#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET 0x0af
204#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0b0
205#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0b1
206#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET 0x0b2
207#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET 0x0b3
208#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET 0x0b4
209#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET 0x0b5
210#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET 0x0b6
211#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET 0x0b7
212#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET 0x0b8
213#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET 0x0b9
214#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET 0x0ba
215#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET 0x0bb
216#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET 0x0bc
217#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET 0x0bd
218#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET 0x0be
219#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET 0x0bf
220#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET 0x0c0
221#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET 0x0c1
222#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET 0x0c2
223#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET 0x0c3
224#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x0c4
225#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x0c5
226#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x0c6
227#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x0c7
228#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x0c8
229#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET 0x0c9
230#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x0ca
231#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x0cb
232#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x0cc
233#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x0cd
234#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x0ce
235#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0cf
236#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0d0
237#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET 0x0d1
238#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET 0x0d2
239#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x0d3
240#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x0d4
241#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x0d5
242#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x0d6
243#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0d7
244#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0d8
245#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0d9
246#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0da
247#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET 0x0db
248#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0dc
249#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0dd
250#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0de
251#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0df
252#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0e0
253#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0e1
254#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET 0x0e2
255#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET 0x0e3
256#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET 0x0e4
257#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET 0x0e5
258#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0e6
259#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0e7
260#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0e8
261#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET 0x0e9
262#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0ea
263#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0eb
264#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0ec
265#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0ed
266#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0ee
267#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0ef
268#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0f0
269#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0f1
270#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0f2
271#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0f3
272#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0f4
273#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0f5
274#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0f6
275#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0f7
276#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0f8
277#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0f9
278#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET 0x0fa
279#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET 0x0fb
280#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET 0x0fc
281#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET 0x0fd
282#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET 0x0fe
283#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET 0x0ff
284#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET 0x100
285#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET 0x101
286#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET 0x102
287#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET 0x103
288#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET 0x104
289#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET 0x105
290#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET 0x106
291#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET 0x107
292#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET 0x108
293#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET 0x109
294#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET 0x10a
295#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET 0x10b
296#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET 0x10c
297#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET 0x10d
298#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET 0x10e
299#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET 0x10f
300#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET 0x110
301#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET 0x111
302#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET 0x112
303#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET 0x113
304#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET 0x114
305#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET 0x115
306#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET 0x116
307#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET 0x117
308#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET 0x118
309#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET 0x119
310#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET 0x11a
311#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET 0x11b
312#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET 0x11c
313#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET 0x11d
314#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET 0x11e
315#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET 0x11f
316#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET 0x120
317#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET 0x121
318#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET 0x122
319#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET 0x123
320#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET 0x124
321#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET 0x125
322#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET 0x126
323#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET 0x127
324#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET 0x128
325#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET 0x129
326#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET 0x12a
327#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET 0x12b
328#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET 0x12c
329#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET 0x12d
330#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET 0x12e
331#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET 0x12f
332#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET 0x130
333#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET 0x131
334#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET 0x132
335#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET 0x133
336#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET 0x134
337#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET 0x135
338#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET 0x136
339#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET 0x137
340#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET 0x138
341#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET 0x139
342#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET 0x13a
343#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET 0x13b
344#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET 0x13c
345#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET 0x13d
346#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET 0x13e
347#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET 0x13f
348#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET 0x140
349#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET 0x141
350#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET 0x142
351#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET 0x143
352#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET 0x144
353#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET 0x145
354#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET 0x146
355#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET 0x147
356#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET 0x148
357#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET 0x149
358#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET 0x14a
359#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET 0x14b
360#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET 0x14c
361#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET 0x14d
362#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET 0x14e
363#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET 0x14f
364#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET 0x150
365#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET 0x151
366#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET 0x152
367#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET 0x153
368
369#define OMAP2430_CONTROL_PADCONF_MUX_SIZE \
370 (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1)
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 8cc7d331437d..3e97c6c8ecf1 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -76,6 +76,13 @@ static inline void omap_barrier_reserve_memblock(void)
76{ } 76{ }
77#endif 77#endif
78 78
79#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
79void set_cntfreq(void); 80void set_cntfreq(void);
81#else
82static inline void set_cntfreq(void)
83{
84}
85#endif
86
80#endif /* __ASSEMBLER__ */ 87#endif /* __ASSEMBLER__ */
81#endif /* OMAP_ARCH_OMAP_SECURE_H */ 88#endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 57911430324e..b39efd46abf9 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -35,7 +35,6 @@
35#include "iomap.h" 35#include "iomap.h"
36#include "common.h" 36#include "common.h"
37#include "mmc.h" 37#include "mmc.h"
38#include "hsmmc.h"
39#include "prminst44xx.h" 38#include "prminst44xx.h"
40#include "prcm_mpu44xx.h" 39#include "prcm_mpu44xx.h"
41#include "omap4-sar-layout.h" 40#include "omap4-sar-layout.h"
@@ -284,59 +283,3 @@ skip_errata_init:
284 omap_wakeupgen_init(); 283 omap_wakeupgen_init();
285 irqchip_init(); 284 irqchip_init();
286} 285}
287
288#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
289static int omap4_twl6030_hsmmc_late_init(struct device *dev)
290{
291 int irq = 0;
292 struct platform_device *pdev = container_of(dev,
293 struct platform_device, dev);
294 struct omap_mmc_platform_data *pdata = dev->platform_data;
295
296 /* Setting MMC1 Card detect Irq */
297 if (pdev->id == 0) {
298 irq = twl6030_mmc_card_detect_config();
299 if (irq < 0) {
300 dev_err(dev, "%s: Error card detect config(%d)\n",
301 __func__, irq);
302 return irq;
303 }
304 pdata->slots[0].card_detect_irq = irq;
305 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
306 }
307 return 0;
308}
309
310static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
311{
312 struct omap_mmc_platform_data *pdata;
313
314 /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
315 if (!dev) {
316 pr_err("Failed %s\n", __func__);
317 return;
318 }
319 pdata = dev->platform_data;
320 pdata->init = omap4_twl6030_hsmmc_late_init;
321}
322
323int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
324{
325 struct omap2_hsmmc_info *c;
326
327 omap_hsmmc_init(controllers);
328 for (c = controllers; c->mmc; c++) {
329 /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
330 if (!c->pdev)
331 continue;
332 omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
333 }
334
335 return 0;
336}
337#else
338int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
339{
340 return 0;
341}
342#endif
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 53f0735817bb..828f538b1c4e 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -36,6 +36,7 @@
36#include <linux/of.h> 36#include <linux/of.h>
37#include <linux/notifier.h> 37#include <linux/notifier.h>
38 38
39#include "common.h"
39#include "soc.h" 40#include "soc.h"
40#include "omap_device.h" 41#include "omap_device.h"
41#include "omap_hwmod.h" 42#include "omap_hwmod.h"
@@ -200,6 +201,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
200 case BUS_NOTIFY_ADD_DEVICE: 201 case BUS_NOTIFY_ADD_DEVICE:
201 if (pdev->dev.of_node) 202 if (pdev->dev.of_node)
202 omap_device_build_from_dt(pdev); 203 omap_device_build_from_dt(pdev);
204 omap_auxdata_legacy_init(dev);
203 /* fall through */ 205 /* fall through */
204 default: 206 default:
205 od = to_omap_device(pdev); 207 od = to_omap_device(pdev);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index e3f0ecaf87dd..ee655dab672f 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2326,38 +2326,80 @@ static int _shutdown(struct omap_hwmod *oh)
2326 return 0; 2326 return 0;
2327} 2327}
2328 2328
2329static int of_dev_find_hwmod(struct device_node *np,
2330 struct omap_hwmod *oh)
2331{
2332 int count, i, res;
2333 const char *p;
2334
2335 count = of_property_count_strings(np, "ti,hwmods");
2336 if (count < 1)
2337 return -ENODEV;
2338
2339 for (i = 0; i < count; i++) {
2340 res = of_property_read_string_index(np, "ti,hwmods",
2341 i, &p);
2342 if (res)
2343 continue;
2344 if (!strcmp(p, oh->name)) {
2345 pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n",
2346 np->name, i, oh->name);
2347 return i;
2348 }
2349 }
2350
2351 return -ENODEV;
2352}
2353
2329/** 2354/**
2330 * of_dev_hwmod_lookup - look up needed hwmod from dt blob 2355 * of_dev_hwmod_lookup - look up needed hwmod from dt blob
2331 * @np: struct device_node * 2356 * @np: struct device_node *
2332 * @oh: struct omap_hwmod * 2357 * @oh: struct omap_hwmod *
2358 * @index: index of the entry found
2359 * @found: struct device_node * found or NULL
2333 * 2360 *
2334 * Parse the dt blob and find out needed hwmod. Recursive function is 2361 * Parse the dt blob and find out needed hwmod. Recursive function is
2335 * implemented to take care hierarchical dt blob parsing. 2362 * implemented to take care hierarchical dt blob parsing.
2336 * Return: The device node on success or NULL on failure. 2363 * Return: Returns 0 on success, -ENODEV when not found.
2337 */ 2364 */
2338static struct device_node *of_dev_hwmod_lookup(struct device_node *np, 2365static int of_dev_hwmod_lookup(struct device_node *np,
2339 struct omap_hwmod *oh) 2366 struct omap_hwmod *oh,
2367 int *index,
2368 struct device_node **found)
2340{ 2369{
2341 struct device_node *np0 = NULL, *np1 = NULL; 2370 struct device_node *np0 = NULL;
2342 const char *p; 2371 int res;
2372
2373 res = of_dev_find_hwmod(np, oh);
2374 if (res >= 0) {
2375 *found = np;
2376 *index = res;
2377 return 0;
2378 }
2343 2379
2344 for_each_child_of_node(np, np0) { 2380 for_each_child_of_node(np, np0) {
2345 if (of_find_property(np0, "ti,hwmods", NULL)) { 2381 struct device_node *fc;
2346 p = of_get_property(np0, "ti,hwmods", NULL); 2382 int i;
2347 if (!strcmp(p, oh->name)) 2383
2348 return np0; 2384 res = of_dev_hwmod_lookup(np0, oh, &i, &fc);
2349 np1 = of_dev_hwmod_lookup(np0, oh); 2385 if (res == 0) {
2350 if (np1) 2386 *found = fc;
2351 return np1; 2387 *index = i;
2388 return 0;
2352 } 2389 }
2353 } 2390 }
2354 return NULL; 2391
2392 *found = NULL;
2393 *index = 0;
2394
2395 return -ENODEV;
2355} 2396}
2356 2397
2357/** 2398/**
2358 * _init_mpu_rt_base - populate the virtual address for a hwmod 2399 * _init_mpu_rt_base - populate the virtual address for a hwmod
2359 * @oh: struct omap_hwmod * to locate the virtual address 2400 * @oh: struct omap_hwmod * to locate the virtual address
2360 * @data: (unused, caller should pass NULL) 2401 * @data: (unused, caller should pass NULL)
2402 * @index: index of the reg entry iospace in device tree
2361 * @np: struct device_node * of the IP block's device node in the DT data 2403 * @np: struct device_node * of the IP block's device node in the DT data
2362 * 2404 *
2363 * Cache the virtual address used by the MPU to access this IP block's 2405 * Cache the virtual address used by the MPU to access this IP block's
@@ -2368,7 +2410,7 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
2368 * -ENXIO on absent or invalid register target address space. 2410 * -ENXIO on absent or invalid register target address space.
2369 */ 2411 */
2370static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, 2412static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
2371 struct device_node *np) 2413 int index, struct device_node *np)
2372{ 2414{
2373 struct omap_hwmod_addr_space *mem; 2415 struct omap_hwmod_addr_space *mem;
2374 void __iomem *va_start = NULL; 2416 void __iomem *va_start = NULL;
@@ -2390,13 +2432,17 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
2390 if (!np) 2432 if (!np)
2391 return -ENXIO; 2433 return -ENXIO;
2392 2434
2393 va_start = of_iomap(np, oh->mpu_rt_idx); 2435 va_start = of_iomap(np, index + oh->mpu_rt_idx);
2394 } else { 2436 } else {
2395 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); 2437 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
2396 } 2438 }
2397 2439
2398 if (!va_start) { 2440 if (!va_start) {
2399 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); 2441 if (mem)
2442 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
2443 else
2444 pr_err("omap_hwmod: %s: Missing dt reg%i for %s\n",
2445 oh->name, index, np->full_name);
2400 return -ENXIO; 2446 return -ENXIO;
2401 } 2447 }
2402 2448
@@ -2422,17 +2468,29 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
2422 */ 2468 */
2423static int __init _init(struct omap_hwmod *oh, void *data) 2469static int __init _init(struct omap_hwmod *oh, void *data)
2424{ 2470{
2425 int r; 2471 int r, index;
2426 struct device_node *np = NULL; 2472 struct device_node *np = NULL;
2427 2473
2428 if (oh->_state != _HWMOD_STATE_REGISTERED) 2474 if (oh->_state != _HWMOD_STATE_REGISTERED)
2429 return 0; 2475 return 0;
2430 2476
2431 if (of_have_populated_dt()) 2477 if (of_have_populated_dt()) {
2432 np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh); 2478 struct device_node *bus;
2479
2480 bus = of_find_node_by_name(NULL, "ocp");
2481 if (!bus)
2482 return -ENODEV;
2483
2484 r = of_dev_hwmod_lookup(bus, oh, &index, &np);
2485 if (r)
2486 pr_debug("omap_hwmod: %s missing dt data\n", oh->name);
2487 else if (np && index)
2488 pr_warn("omap_hwmod: %s using broken dt data from %s\n",
2489 oh->name, np->name);
2490 }
2433 2491
2434 if (oh->class->sysc) { 2492 if (oh->class->sysc) {
2435 r = _init_mpu_rt_base(oh, NULL, np); 2493 r = _init_mpu_rt_base(oh, NULL, index, np);
2436 if (r < 0) { 2494 if (r < 0) {
2437 WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", 2495 WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
2438 oh->name); 2496 oh->name);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index d8b9d60f854f..2f15979c2e9c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -108,8 +108,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
108/* I2C1 */ 108/* I2C1 */
109static struct omap_hwmod omap2420_i2c1_hwmod = { 109static struct omap_hwmod omap2420_i2c1_hwmod = {
110 .name = "i2c1", 110 .name = "i2c1",
111 .mpu_irqs = omap2_i2c1_mpu_irqs,
112 .sdma_reqs = omap2_i2c1_sdma_reqs,
113 .main_clk = "i2c1_fck", 111 .main_clk = "i2c1_fck",
114 .prcm = { 112 .prcm = {
115 .omap2 = { 113 .omap2 = {
@@ -133,8 +131,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
133/* I2C2 */ 131/* I2C2 */
134static struct omap_hwmod omap2420_i2c2_hwmod = { 132static struct omap_hwmod omap2420_i2c2_hwmod = {
135 .name = "i2c2", 133 .name = "i2c2",
136 .mpu_irqs = omap2_i2c2_mpu_irqs,
137 .sdma_reqs = omap2_i2c2_sdma_reqs,
138 .main_clk = "i2c2_fck", 134 .main_clk = "i2c2_fck",
139 .prcm = { 135 .prcm = {
140 .omap2 = { 136 .omap2 = {
@@ -179,16 +175,9 @@ static struct omap_mbox_pdata omap2420_mailbox_attrs = {
179 .info = omap2420_mailbox_info, 175 .info = omap2420_mailbox_info,
180}; 176};
181 177
182static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
183 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
184 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
185 { .irq = -1 },
186};
187
188static struct omap_hwmod omap2420_mailbox_hwmod = { 178static struct omap_hwmod omap2420_mailbox_hwmod = {
189 .name = "mailbox", 179 .name = "mailbox",
190 .class = &omap2xxx_mailbox_hwmod_class, 180 .class = &omap2xxx_mailbox_hwmod_class,
191 .mpu_irqs = omap2420_mailbox_irqs,
192 .main_clk = "mailboxes_ick", 181 .main_clk = "mailboxes_ick",
193 .prcm = { 182 .prcm = {
194 .omap2 = { 183 .omap2 = {
@@ -217,17 +206,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
217}; 206};
218 207
219/* mcbsp1 */ 208/* mcbsp1 */
220static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
221 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
222 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
223 { .irq = -1 },
224};
225
226static struct omap_hwmod omap2420_mcbsp1_hwmod = { 209static struct omap_hwmod omap2420_mcbsp1_hwmod = {
227 .name = "mcbsp1", 210 .name = "mcbsp1",
228 .class = &omap2420_mcbsp_hwmod_class, 211 .class = &omap2420_mcbsp_hwmod_class,
229 .mpu_irqs = omap2420_mcbsp1_irqs,
230 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
231 .main_clk = "mcbsp1_fck", 212 .main_clk = "mcbsp1_fck",
232 .prcm = { 213 .prcm = {
233 .omap2 = { 214 .omap2 = {
@@ -243,17 +224,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
243}; 224};
244 225
245/* mcbsp2 */ 226/* mcbsp2 */
246static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
247 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
248 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
249 { .irq = -1 },
250};
251
252static struct omap_hwmod omap2420_mcbsp2_hwmod = { 227static struct omap_hwmod omap2420_mcbsp2_hwmod = {
253 .name = "mcbsp2", 228 .name = "mcbsp2",
254 .class = &omap2420_mcbsp_hwmod_class, 229 .class = &omap2420_mcbsp_hwmod_class,
255 .mpu_irqs = omap2420_mcbsp2_irqs,
256 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
257 .main_clk = "mcbsp2_fck", 230 .main_clk = "mcbsp2_fck",
258 .prcm = { 231 .prcm = {
259 .omap2 = { 232 .omap2 = {
@@ -283,22 +256,9 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
283}; 256};
284 257
285/* msdi1 */ 258/* msdi1 */
286static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
287 { .irq = 83 + OMAP_INTC_START, },
288 { .irq = -1 },
289};
290
291static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
292 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
293 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
294 { .dma_req = -1 }
295};
296
297static struct omap_hwmod omap2420_msdi1_hwmod = { 259static struct omap_hwmod omap2420_msdi1_hwmod = {
298 .name = "msdi1", 260 .name = "msdi1",
299 .class = &omap2420_msdi_hwmod_class, 261 .class = &omap2420_msdi_hwmod_class,
300 .mpu_irqs = omap2420_msdi1_irqs,
301 .sdma_reqs = omap2420_msdi1_sdma_reqs,
302 .main_clk = "mmc_fck", 262 .main_clk = "mmc_fck",
303 .prcm = { 263 .prcm = {
304 .omap2 = { 264 .omap2 = {
@@ -315,7 +275,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = {
315/* HDQ1W/1-wire */ 275/* HDQ1W/1-wire */
316static struct omap_hwmod omap2420_hdq1w_hwmod = { 276static struct omap_hwmod omap2420_hdq1w_hwmod = {
317 .name = "hdq1w", 277 .name = "hdq1w",
318 .mpu_irqs = omap2_hdq1w_mpu_irqs,
319 .main_clk = "hdq_fck", 278 .main_clk = "hdq_fck",
320 .prcm = { 279 .prcm = {
321 .omap2 = { 280 .omap2 = {
@@ -338,7 +297,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
338 .master = &omap2xxx_l4_core_hwmod, 297 .master = &omap2xxx_l4_core_hwmod,
339 .slave = &omap2420_i2c1_hwmod, 298 .slave = &omap2420_i2c1_hwmod,
340 .clk = "i2c1_ick", 299 .clk = "i2c1_ick",
341 .addr = omap2_i2c1_addr_space,
342 .user = OCP_USER_MPU | OCP_USER_SDMA, 300 .user = OCP_USER_MPU | OCP_USER_SDMA,
343}; 301};
344 302
@@ -347,7 +305,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
347 .master = &omap2xxx_l4_core_hwmod, 305 .master = &omap2xxx_l4_core_hwmod,
348 .slave = &omap2420_i2c2_hwmod, 306 .slave = &omap2420_i2c2_hwmod,
349 .clk = "i2c2_ick", 307 .clk = "i2c2_ick",
350 .addr = omap2_i2c2_addr_space,
351 .user = OCP_USER_MPU | OCP_USER_SDMA, 308 .user = OCP_USER_MPU | OCP_USER_SDMA,
352}; 309};
353 310
@@ -367,111 +324,51 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
367 .user = OCP_USER_MPU | OCP_USER_SDMA, 324 .user = OCP_USER_MPU | OCP_USER_SDMA,
368}; 325};
369 326
370static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
371 {
372 .pa_start = 0x48028000,
373 .pa_end = 0x48028000 + SZ_1K - 1,
374 .flags = ADDR_TYPE_RT
375 },
376 { }
377};
378
379/* l4_wkup -> timer1 */ 327/* l4_wkup -> timer1 */
380static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 328static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
381 .master = &omap2xxx_l4_wkup_hwmod, 329 .master = &omap2xxx_l4_wkup_hwmod,
382 .slave = &omap2xxx_timer1_hwmod, 330 .slave = &omap2xxx_timer1_hwmod,
383 .clk = "gpt1_ick", 331 .clk = "gpt1_ick",
384 .addr = omap2420_timer1_addrs,
385 .user = OCP_USER_MPU | OCP_USER_SDMA, 332 .user = OCP_USER_MPU | OCP_USER_SDMA,
386}; 333};
387 334
388/* l4_wkup -> wd_timer2 */ 335/* l4_wkup -> wd_timer2 */
389static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
390 {
391 .pa_start = 0x48022000,
392 .pa_end = 0x4802207f,
393 .flags = ADDR_TYPE_RT
394 },
395 { }
396};
397
398static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 336static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
399 .master = &omap2xxx_l4_wkup_hwmod, 337 .master = &omap2xxx_l4_wkup_hwmod,
400 .slave = &omap2xxx_wd_timer2_hwmod, 338 .slave = &omap2xxx_wd_timer2_hwmod,
401 .clk = "mpu_wdt_ick", 339 .clk = "mpu_wdt_ick",
402 .addr = omap2420_wd_timer2_addrs,
403 .user = OCP_USER_MPU | OCP_USER_SDMA, 340 .user = OCP_USER_MPU | OCP_USER_SDMA,
404}; 341};
405 342
406/* l4_wkup -> gpio1 */ 343/* l4_wkup -> gpio1 */
407static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
408 {
409 .pa_start = 0x48018000,
410 .pa_end = 0x480181ff,
411 .flags = ADDR_TYPE_RT
412 },
413 { }
414};
415
416static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 344static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
417 .master = &omap2xxx_l4_wkup_hwmod, 345 .master = &omap2xxx_l4_wkup_hwmod,
418 .slave = &omap2xxx_gpio1_hwmod, 346 .slave = &omap2xxx_gpio1_hwmod,
419 .clk = "gpios_ick", 347 .clk = "gpios_ick",
420 .addr = omap2420_gpio1_addr_space,
421 .user = OCP_USER_MPU | OCP_USER_SDMA, 348 .user = OCP_USER_MPU | OCP_USER_SDMA,
422}; 349};
423 350
424/* l4_wkup -> gpio2 */ 351/* l4_wkup -> gpio2 */
425static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
426 {
427 .pa_start = 0x4801a000,
428 .pa_end = 0x4801a1ff,
429 .flags = ADDR_TYPE_RT
430 },
431 { }
432};
433
434static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 352static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
435 .master = &omap2xxx_l4_wkup_hwmod, 353 .master = &omap2xxx_l4_wkup_hwmod,
436 .slave = &omap2xxx_gpio2_hwmod, 354 .slave = &omap2xxx_gpio2_hwmod,
437 .clk = "gpios_ick", 355 .clk = "gpios_ick",
438 .addr = omap2420_gpio2_addr_space,
439 .user = OCP_USER_MPU | OCP_USER_SDMA, 356 .user = OCP_USER_MPU | OCP_USER_SDMA,
440}; 357};
441 358
442/* l4_wkup -> gpio3 */ 359/* l4_wkup -> gpio3 */
443static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
444 {
445 .pa_start = 0x4801c000,
446 .pa_end = 0x4801c1ff,
447 .flags = ADDR_TYPE_RT
448 },
449 { }
450};
451
452static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 360static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
453 .master = &omap2xxx_l4_wkup_hwmod, 361 .master = &omap2xxx_l4_wkup_hwmod,
454 .slave = &omap2xxx_gpio3_hwmod, 362 .slave = &omap2xxx_gpio3_hwmod,
455 .clk = "gpios_ick", 363 .clk = "gpios_ick",
456 .addr = omap2420_gpio3_addr_space,
457 .user = OCP_USER_MPU | OCP_USER_SDMA, 364 .user = OCP_USER_MPU | OCP_USER_SDMA,
458}; 365};
459 366
460/* l4_wkup -> gpio4 */ 367/* l4_wkup -> gpio4 */
461static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
462 {
463 .pa_start = 0x4801e000,
464 .pa_end = 0x4801e1ff,
465 .flags = ADDR_TYPE_RT
466 },
467 { }
468};
469
470static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 368static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
471 .master = &omap2xxx_l4_wkup_hwmod, 369 .master = &omap2xxx_l4_wkup_hwmod,
472 .slave = &omap2xxx_gpio4_hwmod, 370 .slave = &omap2xxx_gpio4_hwmod,
473 .clk = "gpios_ick", 371 .clk = "gpios_ick",
474 .addr = omap2420_gpio4_addr_space,
475 .user = OCP_USER_MPU | OCP_USER_SDMA, 372 .user = OCP_USER_MPU | OCP_USER_SDMA,
476}; 373};
477 374
@@ -496,7 +393,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
496static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 393static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
497 .master = &omap2xxx_l4_core_hwmod, 394 .master = &omap2xxx_l4_core_hwmod,
498 .slave = &omap2420_mailbox_hwmod, 395 .slave = &omap2420_mailbox_hwmod,
499 .addr = omap2_mailbox_addrs,
500 .user = OCP_USER_MPU | OCP_USER_SDMA, 396 .user = OCP_USER_MPU | OCP_USER_SDMA,
501}; 397};
502 398
@@ -505,7 +401,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
505 .master = &omap2xxx_l4_core_hwmod, 401 .master = &omap2xxx_l4_core_hwmod,
506 .slave = &omap2420_mcbsp1_hwmod, 402 .slave = &omap2420_mcbsp1_hwmod,
507 .clk = "mcbsp1_ick", 403 .clk = "mcbsp1_ick",
508 .addr = omap2_mcbsp1_addrs,
509 .user = OCP_USER_MPU | OCP_USER_SDMA, 404 .user = OCP_USER_MPU | OCP_USER_SDMA,
510}; 405};
511 406
@@ -514,25 +409,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
514 .master = &omap2xxx_l4_core_hwmod, 409 .master = &omap2xxx_l4_core_hwmod,
515 .slave = &omap2420_mcbsp2_hwmod, 410 .slave = &omap2420_mcbsp2_hwmod,
516 .clk = "mcbsp2_ick", 411 .clk = "mcbsp2_ick",
517 .addr = omap2xxx_mcbsp2_addrs,
518 .user = OCP_USER_MPU | OCP_USER_SDMA, 412 .user = OCP_USER_MPU | OCP_USER_SDMA,
519}; 413};
520 414
521static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
522 {
523 .pa_start = 0x4809c000,
524 .pa_end = 0x4809c000 + SZ_128 - 1,
525 .flags = ADDR_TYPE_RT,
526 },
527 { }
528};
529
530/* l4_core -> msdi1 */ 415/* l4_core -> msdi1 */
531static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { 416static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
532 .master = &omap2xxx_l4_core_hwmod, 417 .master = &omap2xxx_l4_core_hwmod,
533 .slave = &omap2420_msdi1_hwmod, 418 .slave = &omap2420_msdi1_hwmod,
534 .clk = "mmc_ick", 419 .clk = "mmc_ick",
535 .addr = omap2420_msdi1_addrs,
536 .user = OCP_USER_MPU | OCP_USER_SDMA, 420 .user = OCP_USER_MPU | OCP_USER_SDMA,
537}; 421};
538 422
@@ -541,36 +425,16 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
541 .master = &omap2xxx_l4_core_hwmod, 425 .master = &omap2xxx_l4_core_hwmod,
542 .slave = &omap2420_hdq1w_hwmod, 426 .slave = &omap2420_hdq1w_hwmod,
543 .clk = "hdq_ick", 427 .clk = "hdq_ick",
544 .addr = omap2_hdq1w_addr_space,
545 .user = OCP_USER_MPU | OCP_USER_SDMA, 428 .user = OCP_USER_MPU | OCP_USER_SDMA,
546 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 429 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
547}; 430};
548 431
549 432
550/* l4_wkup -> 32ksync_counter */ 433/* l4_wkup -> 32ksync_counter */
551static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
552 {
553 .pa_start = 0x48004000,
554 .pa_end = 0x4800401f,
555 .flags = ADDR_TYPE_RT
556 },
557 { }
558};
559
560static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
561 {
562 .pa_start = 0x6800a000,
563 .pa_end = 0x6800afff,
564 .flags = ADDR_TYPE_RT
565 },
566 { }
567};
568
569static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { 434static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
570 .master = &omap2xxx_l4_wkup_hwmod, 435 .master = &omap2xxx_l4_wkup_hwmod,
571 .slave = &omap2xxx_counter_32k_hwmod, 436 .slave = &omap2xxx_counter_32k_hwmod,
572 .clk = "sync_32k_ick", 437 .clk = "sync_32k_ick",
573 .addr = omap2420_counter_32k_addrs,
574 .user = OCP_USER_MPU | OCP_USER_SDMA, 438 .user = OCP_USER_MPU | OCP_USER_SDMA,
575}; 439};
576 440
@@ -578,7 +442,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
578 .master = &omap2xxx_l3_main_hwmod, 442 .master = &omap2xxx_l3_main_hwmod,
579 .slave = &omap2xxx_gpmc_hwmod, 443 .slave = &omap2xxx_gpmc_hwmod,
580 .clk = "core_l3_ck", 444 .clk = "core_l3_ck",
581 .addr = omap2420_gpmc_addrs,
582 .user = OCP_USER_MPU | OCP_USER_SDMA, 445 .user = OCP_USER_MPU | OCP_USER_SDMA,
583}; 446};
584 447
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 5b9083461dc5..6d1b60902179 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -86,8 +86,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
86static struct omap_hwmod omap2430_i2c1_hwmod = { 86static struct omap_hwmod omap2430_i2c1_hwmod = {
87 .name = "i2c1", 87 .name = "i2c1",
88 .flags = HWMOD_16BIT_REG, 88 .flags = HWMOD_16BIT_REG,
89 .mpu_irqs = omap2_i2c1_mpu_irqs,
90 .sdma_reqs = omap2_i2c1_sdma_reqs,
91 .main_clk = "i2chs1_fck", 89 .main_clk = "i2chs1_fck",
92 .prcm = { 90 .prcm = {
93 .omap2 = { 91 .omap2 = {
@@ -114,8 +112,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
114static struct omap_hwmod omap2430_i2c2_hwmod = { 112static struct omap_hwmod omap2430_i2c2_hwmod = {
115 .name = "i2c2", 113 .name = "i2c2",
116 .flags = HWMOD_16BIT_REG, 114 .flags = HWMOD_16BIT_REG,
117 .mpu_irqs = omap2_i2c2_mpu_irqs,
118 .sdma_reqs = omap2_i2c2_sdma_reqs,
119 .main_clk = "i2chs2_fck", 115 .main_clk = "i2chs2_fck",
120 .prcm = { 116 .prcm = {
121 .omap2 = { 117 .omap2 = {
@@ -131,15 +127,9 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
131}; 127};
132 128
133/* gpio5 */ 129/* gpio5 */
134static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
135 { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
136 { .irq = -1 },
137};
138
139static struct omap_hwmod omap2430_gpio5_hwmod = { 130static struct omap_hwmod omap2430_gpio5_hwmod = {
140 .name = "gpio5", 131 .name = "gpio5",
141 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 132 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
142 .mpu_irqs = omap243x_gpio5_irqs,
143 .main_clk = "gpio5_fck", 133 .main_clk = "gpio5_fck",
144 .prcm = { 134 .prcm = {
145 .omap2 = { 135 .omap2 = {
@@ -182,15 +172,9 @@ static struct omap_mbox_pdata omap2430_mailbox_attrs = {
182 .info = omap2430_mailbox_info, 172 .info = omap2430_mailbox_info,
183}; 173};
184 174
185static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
186 { .irq = 26 + OMAP_INTC_START, },
187 { .irq = -1 },
188};
189
190static struct omap_hwmod omap2430_mailbox_hwmod = { 175static struct omap_hwmod omap2430_mailbox_hwmod = {
191 .name = "mailbox", 176 .name = "mailbox",
192 .class = &omap2xxx_mailbox_hwmod_class, 177 .class = &omap2xxx_mailbox_hwmod_class,
193 .mpu_irqs = omap2430_mailbox_irqs,
194 .main_clk = "mailboxes_ick", 178 .main_clk = "mailboxes_ick",
195 .prcm = { 179 .prcm = {
196 .omap2 = { 180 .omap2 = {
@@ -205,27 +189,12 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
205}; 189};
206 190
207/* mcspi3 */ 191/* mcspi3 */
208static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
209 { .irq = 91 + OMAP_INTC_START, },
210 { .irq = -1 },
211};
212
213static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
214 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
215 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
216 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
217 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
218 { .dma_req = -1 }
219};
220
221static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 192static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
222 .num_chipselect = 2, 193 .num_chipselect = 2,
223}; 194};
224 195
225static struct omap_hwmod omap2430_mcspi3_hwmod = { 196static struct omap_hwmod omap2430_mcspi3_hwmod = {
226 .name = "mcspi3", 197 .name = "mcspi3",
227 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
228 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
229 .main_clk = "mcspi3_fck", 198 .main_clk = "mcspi3_fck",
230 .prcm = { 199 .prcm = {
231 .omap2 = { 200 .omap2 = {
@@ -259,16 +228,8 @@ static struct omap_hwmod_class usbotg_class = {
259}; 228};
260 229
261/* usb_otg_hs */ 230/* usb_otg_hs */
262static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
263
264 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
265 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
266 { .irq = -1 },
267};
268
269static struct omap_hwmod omap2430_usbhsotg_hwmod = { 231static struct omap_hwmod omap2430_usbhsotg_hwmod = {
270 .name = "usb_otg_hs", 232 .name = "usb_otg_hs",
271 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
272 .main_clk = "usbhs_ick", 233 .main_clk = "usbhs_ick",
273 .prcm = { 234 .prcm = {
274 .omap2 = { 235 .omap2 = {
@@ -313,19 +274,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
313}; 274};
314 275
315/* mcbsp1 */ 276/* mcbsp1 */
316static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
317 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
318 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
319 { .name = "ovr", .irq = 61 + OMAP_INTC_START, },
320 { .name = "common", .irq = 64 + OMAP_INTC_START, },
321 { .irq = -1 },
322};
323
324static struct omap_hwmod omap2430_mcbsp1_hwmod = { 277static struct omap_hwmod omap2430_mcbsp1_hwmod = {
325 .name = "mcbsp1", 278 .name = "mcbsp1",
326 .class = &omap2430_mcbsp_hwmod_class, 279 .class = &omap2430_mcbsp_hwmod_class,
327 .mpu_irqs = omap2430_mcbsp1_irqs,
328 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
329 .main_clk = "mcbsp1_fck", 280 .main_clk = "mcbsp1_fck",
330 .prcm = { 281 .prcm = {
331 .omap2 = { 282 .omap2 = {
@@ -341,18 +292,9 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
341}; 292};
342 293
343/* mcbsp2 */ 294/* mcbsp2 */
344static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
345 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
346 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
347 { .name = "common", .irq = 16 + OMAP_INTC_START, },
348 { .irq = -1 },
349};
350
351static struct omap_hwmod omap2430_mcbsp2_hwmod = { 295static struct omap_hwmod omap2430_mcbsp2_hwmod = {
352 .name = "mcbsp2", 296 .name = "mcbsp2",
353 .class = &omap2430_mcbsp_hwmod_class, 297 .class = &omap2430_mcbsp_hwmod_class,
354 .mpu_irqs = omap2430_mcbsp2_irqs,
355 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
356 .main_clk = "mcbsp2_fck", 298 .main_clk = "mcbsp2_fck",
357 .prcm = { 299 .prcm = {
358 .omap2 = { 300 .omap2 = {
@@ -368,18 +310,9 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
368}; 310};
369 311
370/* mcbsp3 */ 312/* mcbsp3 */
371static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
372 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
373 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
374 { .name = "common", .irq = 17 + OMAP_INTC_START, },
375 { .irq = -1 },
376};
377
378static struct omap_hwmod omap2430_mcbsp3_hwmod = { 313static struct omap_hwmod omap2430_mcbsp3_hwmod = {
379 .name = "mcbsp3", 314 .name = "mcbsp3",
380 .class = &omap2430_mcbsp_hwmod_class, 315 .class = &omap2430_mcbsp_hwmod_class,
381 .mpu_irqs = omap2430_mcbsp3_irqs,
382 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
383 .main_clk = "mcbsp3_fck", 316 .main_clk = "mcbsp3_fck",
384 .prcm = { 317 .prcm = {
385 .omap2 = { 318 .omap2 = {
@@ -395,24 +328,9 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
395}; 328};
396 329
397/* mcbsp4 */ 330/* mcbsp4 */
398static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
399 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
400 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
401 { .name = "common", .irq = 18 + OMAP_INTC_START, },
402 { .irq = -1 },
403};
404
405static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
406 { .name = "rx", .dma_req = 20 },
407 { .name = "tx", .dma_req = 19 },
408 { .dma_req = -1 }
409};
410
411static struct omap_hwmod omap2430_mcbsp4_hwmod = { 331static struct omap_hwmod omap2430_mcbsp4_hwmod = {
412 .name = "mcbsp4", 332 .name = "mcbsp4",
413 .class = &omap2430_mcbsp_hwmod_class, 333 .class = &omap2430_mcbsp_hwmod_class,
414 .mpu_irqs = omap2430_mcbsp4_irqs,
415 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
416 .main_clk = "mcbsp4_fck", 334 .main_clk = "mcbsp4_fck",
417 .prcm = { 335 .prcm = {
418 .omap2 = { 336 .omap2 = {
@@ -428,24 +346,9 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
428}; 346};
429 347
430/* mcbsp5 */ 348/* mcbsp5 */
431static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
432 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
433 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
434 { .name = "common", .irq = 19 + OMAP_INTC_START, },
435 { .irq = -1 },
436};
437
438static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
439 { .name = "rx", .dma_req = 22 },
440 { .name = "tx", .dma_req = 21 },
441 { .dma_req = -1 }
442};
443
444static struct omap_hwmod omap2430_mcbsp5_hwmod = { 349static struct omap_hwmod omap2430_mcbsp5_hwmod = {
445 .name = "mcbsp5", 350 .name = "mcbsp5",
446 .class = &omap2430_mcbsp_hwmod_class, 351 .class = &omap2430_mcbsp_hwmod_class,
447 .mpu_irqs = omap2430_mcbsp5_irqs,
448 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
449 .main_clk = "mcbsp5_fck", 352 .main_clk = "mcbsp5_fck",
450 .prcm = { 353 .prcm = {
451 .omap2 = { 354 .omap2 = {
@@ -478,17 +381,6 @@ static struct omap_hwmod_class omap2430_mmc_class = {
478}; 381};
479 382
480/* MMC/SD/SDIO1 */ 383/* MMC/SD/SDIO1 */
481static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
482 { .irq = 83 + OMAP_INTC_START, },
483 { .irq = -1 },
484};
485
486static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
487 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
488 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
489 { .dma_req = -1 }
490};
491
492static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 384static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
493 { .role = "dbck", .clk = "mmchsdb1_fck" }, 385 { .role = "dbck", .clk = "mmchsdb1_fck" },
494}; 386};
@@ -500,8 +392,6 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
500static struct omap_hwmod omap2430_mmc1_hwmod = { 392static struct omap_hwmod omap2430_mmc1_hwmod = {
501 .name = "mmc1", 393 .name = "mmc1",
502 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 394 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
503 .mpu_irqs = omap2430_mmc1_mpu_irqs,
504 .sdma_reqs = omap2430_mmc1_sdma_reqs,
505 .opt_clks = omap2430_mmc1_opt_clks, 395 .opt_clks = omap2430_mmc1_opt_clks,
506 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 396 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
507 .main_clk = "mmchs1_fck", 397 .main_clk = "mmchs1_fck",
@@ -519,17 +409,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
519}; 409};
520 410
521/* MMC/SD/SDIO2 */ 411/* MMC/SD/SDIO2 */
522static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
523 { .irq = 86 + OMAP_INTC_START, },
524 { .irq = -1 },
525};
526
527static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
528 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
529 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
530 { .dma_req = -1 }
531};
532
533static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 412static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
534 { .role = "dbck", .clk = "mmchsdb2_fck" }, 413 { .role = "dbck", .clk = "mmchsdb2_fck" },
535}; 414};
@@ -537,8 +416,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
537static struct omap_hwmod omap2430_mmc2_hwmod = { 416static struct omap_hwmod omap2430_mmc2_hwmod = {
538 .name = "mmc2", 417 .name = "mmc2",
539 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 418 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
540 .mpu_irqs = omap2430_mmc2_mpu_irqs,
541 .sdma_reqs = omap2430_mmc2_sdma_reqs,
542 .opt_clks = omap2430_mmc2_opt_clks, 419 .opt_clks = omap2430_mmc2_opt_clks,
543 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 420 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
544 .main_clk = "mmchs2_fck", 421 .main_clk = "mmchs2_fck",
@@ -557,7 +434,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
557/* HDQ1W/1-wire */ 434/* HDQ1W/1-wire */
558static struct omap_hwmod omap2430_hdq1w_hwmod = { 435static struct omap_hwmod omap2430_hdq1w_hwmod = {
559 .name = "hdq1w", 436 .name = "hdq1w",
560 .mpu_irqs = omap2_hdq1w_mpu_irqs,
561 .main_clk = "hdq_fck", 437 .main_clk = "hdq_fck",
562 .prcm = { 438 .prcm = {
563 .omap2 = { 439 .omap2 = {
@@ -589,7 +465,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
589 .master = &omap2xxx_l4_core_hwmod, 465 .master = &omap2xxx_l4_core_hwmod,
590 .slave = &omap2430_i2c1_hwmod, 466 .slave = &omap2430_i2c1_hwmod,
591 .clk = "i2c1_ick", 467 .clk = "i2c1_ick",
592 .addr = omap2_i2c1_addr_space,
593 .user = OCP_USER_MPU | OCP_USER_SDMA, 468 .user = OCP_USER_MPU | OCP_USER_SDMA,
594}; 469};
595 470
@@ -598,25 +473,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
598 .master = &omap2xxx_l4_core_hwmod, 473 .master = &omap2xxx_l4_core_hwmod,
599 .slave = &omap2430_i2c2_hwmod, 474 .slave = &omap2430_i2c2_hwmod,
600 .clk = "i2c2_ick", 475 .clk = "i2c2_ick",
601 .addr = omap2_i2c2_addr_space,
602 .user = OCP_USER_MPU | OCP_USER_SDMA, 476 .user = OCP_USER_MPU | OCP_USER_SDMA,
603}; 477};
604 478
605static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
606 {
607 .pa_start = OMAP243X_HS_BASE,
608 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
609 .flags = ADDR_TYPE_RT
610 },
611 { }
612};
613
614/* l4_core ->usbhsotg interface */ 479/* l4_core ->usbhsotg interface */
615static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 480static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
616 .master = &omap2xxx_l4_core_hwmod, 481 .master = &omap2xxx_l4_core_hwmod,
617 .slave = &omap2430_usbhsotg_hwmod, 482 .slave = &omap2430_usbhsotg_hwmod,
618 .clk = "usb_l4_ick", 483 .clk = "usb_l4_ick",
619 .addr = omap2430_usbhsotg_addrs,
620 .user = OCP_USER_MPU, 484 .user = OCP_USER_MPU,
621}; 485};
622 486
@@ -625,7 +489,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
625 .master = &omap2xxx_l4_core_hwmod, 489 .master = &omap2xxx_l4_core_hwmod,
626 .slave = &omap2430_mmc1_hwmod, 490 .slave = &omap2430_mmc1_hwmod,
627 .clk = "mmchs1_ick", 491 .clk = "mmchs1_ick",
628 .addr = omap2430_mmc1_addr_space,
629 .user = OCP_USER_MPU | OCP_USER_SDMA, 492 .user = OCP_USER_MPU | OCP_USER_SDMA,
630}; 493};
631 494
@@ -634,7 +497,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
634 .master = &omap2xxx_l4_core_hwmod, 497 .master = &omap2xxx_l4_core_hwmod,
635 .slave = &omap2430_mmc2_hwmod, 498 .slave = &omap2430_mmc2_hwmod,
636 .clk = "mmchs2_ick", 499 .clk = "mmchs2_ick",
637 .addr = omap2430_mmc2_addr_space,
638 .user = OCP_USER_MPU | OCP_USER_SDMA, 500 .user = OCP_USER_MPU | OCP_USER_SDMA,
639}; 501};
640 502
@@ -643,7 +505,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
643 .master = &omap2xxx_l4_core_hwmod, 505 .master = &omap2xxx_l4_core_hwmod,
644 .slave = &omap2430_mcspi3_hwmod, 506 .slave = &omap2430_mcspi3_hwmod,
645 .clk = "mcspi3_ick", 507 .clk = "mcspi3_ick",
646 .addr = omap2430_mcspi3_addr_space,
647 .user = OCP_USER_MPU | OCP_USER_SDMA, 508 .user = OCP_USER_MPU | OCP_USER_SDMA,
648}; 509};
649 510
@@ -655,129 +516,59 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = {
655 .user = OCP_USER_MPU | OCP_USER_SDMA, 516 .user = OCP_USER_MPU | OCP_USER_SDMA,
656}; 517};
657 518
658static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
659 {
660 .pa_start = 0x49018000,
661 .pa_end = 0x49018000 + SZ_1K - 1,
662 .flags = ADDR_TYPE_RT
663 },
664 { }
665};
666
667/* l4_wkup -> timer1 */ 519/* l4_wkup -> timer1 */
668static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 520static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
669 .master = &omap2xxx_l4_wkup_hwmod, 521 .master = &omap2xxx_l4_wkup_hwmod,
670 .slave = &omap2xxx_timer1_hwmod, 522 .slave = &omap2xxx_timer1_hwmod,
671 .clk = "gpt1_ick", 523 .clk = "gpt1_ick",
672 .addr = omap2430_timer1_addrs,
673 .user = OCP_USER_MPU | OCP_USER_SDMA, 524 .user = OCP_USER_MPU | OCP_USER_SDMA,
674}; 525};
675 526
676/* l4_wkup -> wd_timer2 */ 527/* l4_wkup -> wd_timer2 */
677static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
678 {
679 .pa_start = 0x49016000,
680 .pa_end = 0x4901607f,
681 .flags = ADDR_TYPE_RT
682 },
683 { }
684};
685
686static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 528static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
687 .master = &omap2xxx_l4_wkup_hwmod, 529 .master = &omap2xxx_l4_wkup_hwmod,
688 .slave = &omap2xxx_wd_timer2_hwmod, 530 .slave = &omap2xxx_wd_timer2_hwmod,
689 .clk = "mpu_wdt_ick", 531 .clk = "mpu_wdt_ick",
690 .addr = omap2430_wd_timer2_addrs,
691 .user = OCP_USER_MPU | OCP_USER_SDMA, 532 .user = OCP_USER_MPU | OCP_USER_SDMA,
692}; 533};
693 534
694/* l4_wkup -> gpio1 */ 535/* l4_wkup -> gpio1 */
695static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
696 {
697 .pa_start = 0x4900C000,
698 .pa_end = 0x4900C1ff,
699 .flags = ADDR_TYPE_RT
700 },
701 { }
702};
703
704static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 536static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
705 .master = &omap2xxx_l4_wkup_hwmod, 537 .master = &omap2xxx_l4_wkup_hwmod,
706 .slave = &omap2xxx_gpio1_hwmod, 538 .slave = &omap2xxx_gpio1_hwmod,
707 .clk = "gpios_ick", 539 .clk = "gpios_ick",
708 .addr = omap2430_gpio1_addr_space,
709 .user = OCP_USER_MPU | OCP_USER_SDMA, 540 .user = OCP_USER_MPU | OCP_USER_SDMA,
710}; 541};
711 542
712/* l4_wkup -> gpio2 */ 543/* l4_wkup -> gpio2 */
713static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
714 {
715 .pa_start = 0x4900E000,
716 .pa_end = 0x4900E1ff,
717 .flags = ADDR_TYPE_RT
718 },
719 { }
720};
721
722static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 544static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
723 .master = &omap2xxx_l4_wkup_hwmod, 545 .master = &omap2xxx_l4_wkup_hwmod,
724 .slave = &omap2xxx_gpio2_hwmod, 546 .slave = &omap2xxx_gpio2_hwmod,
725 .clk = "gpios_ick", 547 .clk = "gpios_ick",
726 .addr = omap2430_gpio2_addr_space,
727 .user = OCP_USER_MPU | OCP_USER_SDMA, 548 .user = OCP_USER_MPU | OCP_USER_SDMA,
728}; 549};
729 550
730/* l4_wkup -> gpio3 */ 551/* l4_wkup -> gpio3 */
731static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
732 {
733 .pa_start = 0x49010000,
734 .pa_end = 0x490101ff,
735 .flags = ADDR_TYPE_RT
736 },
737 { }
738};
739
740static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 552static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
741 .master = &omap2xxx_l4_wkup_hwmod, 553 .master = &omap2xxx_l4_wkup_hwmod,
742 .slave = &omap2xxx_gpio3_hwmod, 554 .slave = &omap2xxx_gpio3_hwmod,
743 .clk = "gpios_ick", 555 .clk = "gpios_ick",
744 .addr = omap2430_gpio3_addr_space,
745 .user = OCP_USER_MPU | OCP_USER_SDMA, 556 .user = OCP_USER_MPU | OCP_USER_SDMA,
746}; 557};
747 558
748/* l4_wkup -> gpio4 */ 559/* l4_wkup -> gpio4 */
749static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
750 {
751 .pa_start = 0x49012000,
752 .pa_end = 0x490121ff,
753 .flags = ADDR_TYPE_RT
754 },
755 { }
756};
757
758static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 560static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
759 .master = &omap2xxx_l4_wkup_hwmod, 561 .master = &omap2xxx_l4_wkup_hwmod,
760 .slave = &omap2xxx_gpio4_hwmod, 562 .slave = &omap2xxx_gpio4_hwmod,
761 .clk = "gpios_ick", 563 .clk = "gpios_ick",
762 .addr = omap2430_gpio4_addr_space,
763 .user = OCP_USER_MPU | OCP_USER_SDMA, 564 .user = OCP_USER_MPU | OCP_USER_SDMA,
764}; 565};
765 566
766/* l4_core -> gpio5 */ 567/* l4_core -> gpio5 */
767static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
768 {
769 .pa_start = 0x480B6000,
770 .pa_end = 0x480B61ff,
771 .flags = ADDR_TYPE_RT
772 },
773 { }
774};
775
776static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 568static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
777 .master = &omap2xxx_l4_core_hwmod, 569 .master = &omap2xxx_l4_core_hwmod,
778 .slave = &omap2430_gpio5_hwmod, 570 .slave = &omap2430_gpio5_hwmod,
779 .clk = "gpio5_ick", 571 .clk = "gpio5_ick",
780 .addr = omap2430_gpio5_addr_space,
781 .user = OCP_USER_MPU | OCP_USER_SDMA, 572 .user = OCP_USER_MPU | OCP_USER_SDMA,
782}; 573};
783 574
@@ -802,7 +593,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
802static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 593static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
803 .master = &omap2xxx_l4_core_hwmod, 594 .master = &omap2xxx_l4_core_hwmod,
804 .slave = &omap2430_mailbox_hwmod, 595 .slave = &omap2430_mailbox_hwmod,
805 .addr = omap2_mailbox_addrs,
806 .user = OCP_USER_MPU | OCP_USER_SDMA, 596 .user = OCP_USER_MPU | OCP_USER_SDMA,
807}; 597};
808 598
@@ -811,7 +601,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
811 .master = &omap2xxx_l4_core_hwmod, 601 .master = &omap2xxx_l4_core_hwmod,
812 .slave = &omap2430_mcbsp1_hwmod, 602 .slave = &omap2430_mcbsp1_hwmod,
813 .clk = "mcbsp1_ick", 603 .clk = "mcbsp1_ick",
814 .addr = omap2_mcbsp1_addrs,
815 .user = OCP_USER_MPU | OCP_USER_SDMA, 604 .user = OCP_USER_MPU | OCP_USER_SDMA,
816}; 605};
817 606
@@ -820,64 +609,30 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
820 .master = &omap2xxx_l4_core_hwmod, 609 .master = &omap2xxx_l4_core_hwmod,
821 .slave = &omap2430_mcbsp2_hwmod, 610 .slave = &omap2430_mcbsp2_hwmod,
822 .clk = "mcbsp2_ick", 611 .clk = "mcbsp2_ick",
823 .addr = omap2xxx_mcbsp2_addrs,
824 .user = OCP_USER_MPU | OCP_USER_SDMA, 612 .user = OCP_USER_MPU | OCP_USER_SDMA,
825}; 613};
826 614
827static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
828 {
829 .name = "mpu",
830 .pa_start = 0x4808C000,
831 .pa_end = 0x4808C0ff,
832 .flags = ADDR_TYPE_RT
833 },
834 { }
835};
836
837/* l4_core -> mcbsp3 */ 615/* l4_core -> mcbsp3 */
838static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { 616static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
839 .master = &omap2xxx_l4_core_hwmod, 617 .master = &omap2xxx_l4_core_hwmod,
840 .slave = &omap2430_mcbsp3_hwmod, 618 .slave = &omap2430_mcbsp3_hwmod,
841 .clk = "mcbsp3_ick", 619 .clk = "mcbsp3_ick",
842 .addr = omap2430_mcbsp3_addrs,
843 .user = OCP_USER_MPU | OCP_USER_SDMA, 620 .user = OCP_USER_MPU | OCP_USER_SDMA,
844}; 621};
845 622
846static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
847 {
848 .name = "mpu",
849 .pa_start = 0x4808E000,
850 .pa_end = 0x4808E0ff,
851 .flags = ADDR_TYPE_RT
852 },
853 { }
854};
855
856/* l4_core -> mcbsp4 */ 623/* l4_core -> mcbsp4 */
857static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { 624static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
858 .master = &omap2xxx_l4_core_hwmod, 625 .master = &omap2xxx_l4_core_hwmod,
859 .slave = &omap2430_mcbsp4_hwmod, 626 .slave = &omap2430_mcbsp4_hwmod,
860 .clk = "mcbsp4_ick", 627 .clk = "mcbsp4_ick",
861 .addr = omap2430_mcbsp4_addrs,
862 .user = OCP_USER_MPU | OCP_USER_SDMA, 628 .user = OCP_USER_MPU | OCP_USER_SDMA,
863}; 629};
864 630
865static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
866 {
867 .name = "mpu",
868 .pa_start = 0x48096000,
869 .pa_end = 0x480960ff,
870 .flags = ADDR_TYPE_RT
871 },
872 { }
873};
874
875/* l4_core -> mcbsp5 */ 631/* l4_core -> mcbsp5 */
876static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { 632static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
877 .master = &omap2xxx_l4_core_hwmod, 633 .master = &omap2xxx_l4_core_hwmod,
878 .slave = &omap2430_mcbsp5_hwmod, 634 .slave = &omap2430_mcbsp5_hwmod,
879 .clk = "mcbsp5_ick", 635 .clk = "mcbsp5_ick",
880 .addr = omap2430_mcbsp5_addrs,
881 .user = OCP_USER_MPU | OCP_USER_SDMA, 636 .user = OCP_USER_MPU | OCP_USER_SDMA,
882}; 637};
883 638
@@ -886,35 +641,15 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
886 .master = &omap2xxx_l4_core_hwmod, 641 .master = &omap2xxx_l4_core_hwmod,
887 .slave = &omap2430_hdq1w_hwmod, 642 .slave = &omap2430_hdq1w_hwmod,
888 .clk = "hdq_ick", 643 .clk = "hdq_ick",
889 .addr = omap2_hdq1w_addr_space,
890 .user = OCP_USER_MPU | OCP_USER_SDMA, 644 .user = OCP_USER_MPU | OCP_USER_SDMA,
891 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 645 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
892}; 646};
893 647
894/* l4_wkup -> 32ksync_counter */ 648/* l4_wkup -> 32ksync_counter */
895static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
896 {
897 .pa_start = 0x49020000,
898 .pa_end = 0x4902001f,
899 .flags = ADDR_TYPE_RT
900 },
901 { }
902};
903
904static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
905 {
906 .pa_start = 0x6e000000,
907 .pa_end = 0x6e000fff,
908 .flags = ADDR_TYPE_RT
909 },
910 { }
911};
912
913static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { 649static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
914 .master = &omap2xxx_l4_wkup_hwmod, 650 .master = &omap2xxx_l4_wkup_hwmod,
915 .slave = &omap2xxx_counter_32k_hwmod, 651 .slave = &omap2xxx_counter_32k_hwmod,
916 .clk = "sync_32k_ick", 652 .clk = "sync_32k_ick",
917 .addr = omap2430_counter_32k_addrs,
918 .user = OCP_USER_MPU | OCP_USER_SDMA, 653 .user = OCP_USER_MPU | OCP_USER_SDMA,
919}; 654};
920 655
@@ -922,7 +657,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
922 .master = &omap2xxx_l3_main_hwmod, 657 .master = &omap2xxx_l3_main_hwmod,
923 .slave = &omap2xxx_gpmc_hwmod, 658 .slave = &omap2xxx_gpmc_hwmod,
924 .clk = "core_l3_ck", 659 .clk = "core_l3_ck",
925 .addr = omap2430_gpmc_addrs,
926 .user = OCP_USER_MPU | OCP_USER_SDMA, 660 .user = OCP_USER_MPU | OCP_USER_SDMA,
927}; 661};
928 662
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 5fd40d4a989e..656861c29d5c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -20,142 +20,6 @@
20 20
21#include "omap_hwmod_common_data.h" 21#include "omap_hwmod_common_data.h"
22 22
23static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
24 {
25 .pa_start = OMAP2_UART1_BASE,
26 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
27 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
28 },
29 { }
30};
31
32static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
33 {
34 .pa_start = OMAP2_UART2_BASE,
35 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
36 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
37 },
38 { }
39};
40
41static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
42 {
43 .pa_start = OMAP2_UART3_BASE,
44 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
45 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
46 },
47 { }
48};
49
50static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
51 {
52 .pa_start = 0x4802a000,
53 .pa_end = 0x4802a000 + SZ_1K - 1,
54 .flags = ADDR_TYPE_RT
55 },
56 { }
57};
58
59static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
60 {
61 .pa_start = 0x48078000,
62 .pa_end = 0x48078000 + SZ_1K - 1,
63 .flags = ADDR_TYPE_RT
64 },
65 { }
66};
67
68static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
69 {
70 .pa_start = 0x4807a000,
71 .pa_end = 0x4807a000 + SZ_1K - 1,
72 .flags = ADDR_TYPE_RT
73 },
74 { }
75};
76
77static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
78 {
79 .pa_start = 0x4807c000,
80 .pa_end = 0x4807c000 + SZ_1K - 1,
81 .flags = ADDR_TYPE_RT
82 },
83 { }
84};
85
86static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
87 {
88 .pa_start = 0x4807e000,
89 .pa_end = 0x4807e000 + SZ_1K - 1,
90 .flags = ADDR_TYPE_RT
91 },
92 { }
93};
94
95static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
96 {
97 .pa_start = 0x48080000,
98 .pa_end = 0x48080000 + SZ_1K - 1,
99 .flags = ADDR_TYPE_RT
100 },
101 { }
102};
103
104static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
105 {
106 .pa_start = 0x48082000,
107 .pa_end = 0x48082000 + SZ_1K - 1,
108 .flags = ADDR_TYPE_RT
109 },
110 { }
111};
112
113static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
114 {
115 .pa_start = 0x48084000,
116 .pa_end = 0x48084000 + SZ_1K - 1,
117 .flags = ADDR_TYPE_RT
118 },
119 { }
120};
121
122struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
123 {
124 .name = "mpu",
125 .pa_start = 0x48076000,
126 .pa_end = 0x480760ff,
127 .flags = ADDR_TYPE_RT
128 },
129 { }
130};
131
132static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
133 {
134 .pa_start = 0x480a0000,
135 .pa_end = 0x480a004f,
136 .flags = ADDR_TYPE_RT
137 },
138 { }
139};
140
141static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
142 {
143 .pa_start = 0x480a4000,
144 .pa_end = 0x480a4000 + 0x64 - 1,
145 .flags = ADDR_TYPE_RT
146 },
147 { }
148};
149
150static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
151 {
152 .pa_start = 0x480a6000,
153 .pa_end = 0x480a6000 + 0x50 - 1,
154 .flags = ADDR_TYPE_RT
155 },
156 { }
157};
158
159/* 23/*
160 * Common interconnect data 24 * Common interconnect data
161 */ 25 */
@@ -182,7 +46,7 @@ struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
182 .omap2 = { 46 .omap2 = {
183 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, 47 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
184 .flags = OMAP_FIREWALL_L3, 48 .flags = OMAP_FIREWALL_L3,
185 } 49 },
186 }, 50 },
187 .user = OCP_USER_MPU | OCP_USER_SDMA, 51 .user = OCP_USER_MPU | OCP_USER_SDMA,
188}; 52};
@@ -199,7 +63,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
199 .master = &omap2xxx_l4_core_hwmod, 63 .master = &omap2xxx_l4_core_hwmod,
200 .slave = &omap2xxx_uart1_hwmod, 64 .slave = &omap2xxx_uart1_hwmod,
201 .clk = "uart1_ick", 65 .clk = "uart1_ick",
202 .addr = omap2xxx_uart1_addr_space,
203 .user = OCP_USER_MPU | OCP_USER_SDMA, 66 .user = OCP_USER_MPU | OCP_USER_SDMA,
204}; 67};
205 68
@@ -208,7 +71,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
208 .master = &omap2xxx_l4_core_hwmod, 71 .master = &omap2xxx_l4_core_hwmod,
209 .slave = &omap2xxx_uart2_hwmod, 72 .slave = &omap2xxx_uart2_hwmod,
210 .clk = "uart2_ick", 73 .clk = "uart2_ick",
211 .addr = omap2xxx_uart2_addr_space,
212 .user = OCP_USER_MPU | OCP_USER_SDMA, 74 .user = OCP_USER_MPU | OCP_USER_SDMA,
213}; 75};
214 76
@@ -217,7 +79,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
217 .master = &omap2xxx_l4_core_hwmod, 79 .master = &omap2xxx_l4_core_hwmod,
218 .slave = &omap2xxx_uart3_hwmod, 80 .slave = &omap2xxx_uart3_hwmod,
219 .clk = "uart3_ick", 81 .clk = "uart3_ick",
220 .addr = omap2xxx_uart3_addr_space,
221 .user = OCP_USER_MPU | OCP_USER_SDMA, 82 .user = OCP_USER_MPU | OCP_USER_SDMA,
222}; 83};
223 84
@@ -226,7 +87,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
226 .master = &omap2xxx_l4_core_hwmod, 87 .master = &omap2xxx_l4_core_hwmod,
227 .slave = &omap2xxx_mcspi1_hwmod, 88 .slave = &omap2xxx_mcspi1_hwmod,
228 .clk = "mcspi1_ick", 89 .clk = "mcspi1_ick",
229 .addr = omap2_mcspi1_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA, 90 .user = OCP_USER_MPU | OCP_USER_SDMA,
231}; 91};
232 92
@@ -235,7 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
235 .master = &omap2xxx_l4_core_hwmod, 95 .master = &omap2xxx_l4_core_hwmod,
236 .slave = &omap2xxx_mcspi2_hwmod, 96 .slave = &omap2xxx_mcspi2_hwmod,
237 .clk = "mcspi2_ick", 97 .clk = "mcspi2_ick",
238 .addr = omap2_mcspi2_addr_space,
239 .user = OCP_USER_MPU | OCP_USER_SDMA, 98 .user = OCP_USER_MPU | OCP_USER_SDMA,
240}; 99};
241 100
@@ -244,7 +103,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
244 .master = &omap2xxx_l4_core_hwmod, 103 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2xxx_timer2_hwmod, 104 .slave = &omap2xxx_timer2_hwmod,
246 .clk = "gpt2_ick", 105 .clk = "gpt2_ick",
247 .addr = omap2xxx_timer2_addrs,
248 .user = OCP_USER_MPU | OCP_USER_SDMA, 106 .user = OCP_USER_MPU | OCP_USER_SDMA,
249}; 107};
250 108
@@ -253,7 +111,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
253 .master = &omap2xxx_l4_core_hwmod, 111 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2xxx_timer3_hwmod, 112 .slave = &omap2xxx_timer3_hwmod,
255 .clk = "gpt3_ick", 113 .clk = "gpt3_ick",
256 .addr = omap2xxx_timer3_addrs,
257 .user = OCP_USER_MPU | OCP_USER_SDMA, 114 .user = OCP_USER_MPU | OCP_USER_SDMA,
258}; 115};
259 116
@@ -262,7 +119,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
262 .master = &omap2xxx_l4_core_hwmod, 119 .master = &omap2xxx_l4_core_hwmod,
263 .slave = &omap2xxx_timer4_hwmod, 120 .slave = &omap2xxx_timer4_hwmod,
264 .clk = "gpt4_ick", 121 .clk = "gpt4_ick",
265 .addr = omap2xxx_timer4_addrs,
266 .user = OCP_USER_MPU | OCP_USER_SDMA, 122 .user = OCP_USER_MPU | OCP_USER_SDMA,
267}; 123};
268 124
@@ -271,7 +127,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
271 .master = &omap2xxx_l4_core_hwmod, 127 .master = &omap2xxx_l4_core_hwmod,
272 .slave = &omap2xxx_timer5_hwmod, 128 .slave = &omap2xxx_timer5_hwmod,
273 .clk = "gpt5_ick", 129 .clk = "gpt5_ick",
274 .addr = omap2xxx_timer5_addrs,
275 .user = OCP_USER_MPU | OCP_USER_SDMA, 130 .user = OCP_USER_MPU | OCP_USER_SDMA,
276}; 131};
277 132
@@ -280,7 +135,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
280 .master = &omap2xxx_l4_core_hwmod, 135 .master = &omap2xxx_l4_core_hwmod,
281 .slave = &omap2xxx_timer6_hwmod, 136 .slave = &omap2xxx_timer6_hwmod,
282 .clk = "gpt6_ick", 137 .clk = "gpt6_ick",
283 .addr = omap2xxx_timer6_addrs,
284 .user = OCP_USER_MPU | OCP_USER_SDMA, 138 .user = OCP_USER_MPU | OCP_USER_SDMA,
285}; 139};
286 140
@@ -289,7 +143,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
289 .master = &omap2xxx_l4_core_hwmod, 143 .master = &omap2xxx_l4_core_hwmod,
290 .slave = &omap2xxx_timer7_hwmod, 144 .slave = &omap2xxx_timer7_hwmod,
291 .clk = "gpt7_ick", 145 .clk = "gpt7_ick",
292 .addr = omap2xxx_timer7_addrs,
293 .user = OCP_USER_MPU | OCP_USER_SDMA, 146 .user = OCP_USER_MPU | OCP_USER_SDMA,
294}; 147};
295 148
@@ -298,7 +151,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
298 .master = &omap2xxx_l4_core_hwmod, 151 .master = &omap2xxx_l4_core_hwmod,
299 .slave = &omap2xxx_timer8_hwmod, 152 .slave = &omap2xxx_timer8_hwmod,
300 .clk = "gpt8_ick", 153 .clk = "gpt8_ick",
301 .addr = omap2xxx_timer8_addrs,
302 .user = OCP_USER_MPU | OCP_USER_SDMA, 154 .user = OCP_USER_MPU | OCP_USER_SDMA,
303}; 155};
304 156
@@ -307,7 +159,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
307 .master = &omap2xxx_l4_core_hwmod, 159 .master = &omap2xxx_l4_core_hwmod,
308 .slave = &omap2xxx_timer9_hwmod, 160 .slave = &omap2xxx_timer9_hwmod,
309 .clk = "gpt9_ick", 161 .clk = "gpt9_ick",
310 .addr = omap2xxx_timer9_addrs,
311 .user = OCP_USER_MPU | OCP_USER_SDMA, 162 .user = OCP_USER_MPU | OCP_USER_SDMA,
312}; 163};
313 164
@@ -316,7 +167,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
316 .master = &omap2xxx_l4_core_hwmod, 167 .master = &omap2xxx_l4_core_hwmod,
317 .slave = &omap2xxx_timer10_hwmod, 168 .slave = &omap2xxx_timer10_hwmod,
318 .clk = "gpt10_ick", 169 .clk = "gpt10_ick",
319 .addr = omap2_timer10_addrs,
320 .user = OCP_USER_MPU | OCP_USER_SDMA, 170 .user = OCP_USER_MPU | OCP_USER_SDMA,
321}; 171};
322 172
@@ -325,7 +175,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
325 .master = &omap2xxx_l4_core_hwmod, 175 .master = &omap2xxx_l4_core_hwmod,
326 .slave = &omap2xxx_timer11_hwmod, 176 .slave = &omap2xxx_timer11_hwmod,
327 .clk = "gpt11_ick", 177 .clk = "gpt11_ick",
328 .addr = omap2_timer11_addrs,
329 .user = OCP_USER_MPU | OCP_USER_SDMA, 178 .user = OCP_USER_MPU | OCP_USER_SDMA,
330}; 179};
331 180
@@ -334,7 +183,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
334 .master = &omap2xxx_l4_core_hwmod, 183 .master = &omap2xxx_l4_core_hwmod,
335 .slave = &omap2xxx_timer12_hwmod, 184 .slave = &omap2xxx_timer12_hwmod,
336 .clk = "gpt12_ick", 185 .clk = "gpt12_ick",
337 .addr = omap2xxx_timer12_addrs,
338 .user = OCP_USER_MPU | OCP_USER_SDMA, 186 .user = OCP_USER_MPU | OCP_USER_SDMA,
339}; 187};
340 188
@@ -348,7 +196,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
348 .omap2 = { 196 .omap2 = {
349 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 197 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
350 .flags = OMAP_FIREWALL_L4, 198 .flags = OMAP_FIREWALL_L4,
351 } 199 },
352 }, 200 },
353 .user = OCP_USER_MPU | OCP_USER_SDMA, 201 .user = OCP_USER_MPU | OCP_USER_SDMA,
354}; 202};
@@ -363,7 +211,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
363 .omap2 = { 211 .omap2 = {
364 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 212 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
365 .flags = OMAP_FIREWALL_L4, 213 .flags = OMAP_FIREWALL_L4,
366 } 214 },
367 }, 215 },
368 .user = OCP_USER_MPU | OCP_USER_SDMA, 216 .user = OCP_USER_MPU | OCP_USER_SDMA,
369}; 217};
@@ -378,7 +226,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
378 .omap2 = { 226 .omap2 = {
379 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 227 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
380 .flags = OMAP_FIREWALL_L4, 228 .flags = OMAP_FIREWALL_L4,
381 } 229 },
382 }, 230 },
383 .user = OCP_USER_MPU | OCP_USER_SDMA, 231 .user = OCP_USER_MPU | OCP_USER_SDMA,
384}; 232};
@@ -393,7 +241,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
393 .omap2 = { 241 .omap2 = {
394 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 242 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
395 .flags = OMAP_FIREWALL_L4, 243 .flags = OMAP_FIREWALL_L4,
396 } 244 },
397 }, 245 },
398 .flags = OCPIF_SWSUP_IDLE, 246 .flags = OCPIF_SWSUP_IDLE,
399 .user = OCP_USER_MPU | OCP_USER_SDMA, 247 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -404,7 +252,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
404 .master = &omap2xxx_l4_core_hwmod, 252 .master = &omap2xxx_l4_core_hwmod,
405 .slave = &omap2xxx_rng_hwmod, 253 .slave = &omap2xxx_rng_hwmod,
406 .clk = "rng_ick", 254 .clk = "rng_ick",
407 .addr = omap2_rng_addr_space,
408 .user = OCP_USER_MPU | OCP_USER_SDMA, 255 .user = OCP_USER_MPU | OCP_USER_SDMA,
409}; 256};
410 257
@@ -413,7 +260,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
413 .master = &omap2xxx_l4_core_hwmod, 260 .master = &omap2xxx_l4_core_hwmod,
414 .slave = &omap2xxx_sham_hwmod, 261 .slave = &omap2xxx_sham_hwmod,
415 .clk = "sha_ick", 262 .clk = "sha_ick",
416 .addr = omap2xxx_sham_addrs,
417 .user = OCP_USER_MPU | OCP_USER_SDMA, 263 .user = OCP_USER_MPU | OCP_USER_SDMA,
418}; 264};
419 265
@@ -422,6 +268,5 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
422 .master = &omap2xxx_l4_core_hwmod, 268 .master = &omap2xxx_l4_core_hwmod,
423 .slave = &omap2xxx_aes_hwmod, 269 .slave = &omap2xxx_aes_hwmod,
424 .clk = "aes_ick", 270 .clk = "aes_ick",
425 .addr = omap2xxx_aes_addrs,
426 .user = OCP_USER_MPU | OCP_USER_SDMA, 271 .user = OCP_USER_MPU | OCP_USER_SDMA,
427}; 272};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 56cebb05509e..8821b9d6bae4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -20,14 +20,9 @@
20#include "prm-regbits-24xx.h" 20#include "prm-regbits-24xx.h"
21#include "wd_timer.h" 21#include "wd_timer.h"
22 22
23struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
24 { .irq = 48 + OMAP_INTC_START, },
25 { .irq = -1 },
26};
27
28struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { 23struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
29 { .name = "dispc", .dma_req = 5 }, 24 { .name = "dispc", .dma_req = 5 },
30 { .dma_req = -1 } 25 { .dma_req = -1, },
31}; 26};
32 27
33/* 28/*
@@ -219,14 +214,8 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
219}; 214};
220 215
221/* MPU */ 216/* MPU */
222static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
223 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
224 { .irq = -1 }
225};
226
227struct omap_hwmod omap2xxx_mpu_hwmod = { 217struct omap_hwmod omap2xxx_mpu_hwmod = {
228 .name = "mpu", 218 .name = "mpu",
229 .mpu_irqs = omap2xxx_mpu_irqs,
230 .class = &mpu_hwmod_class, 219 .class = &mpu_hwmod_class,
231 .main_clk = "mpu_ck", 220 .main_clk = "mpu_ck",
232}; 221};
@@ -256,7 +245,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
256 245
257struct omap_hwmod omap2xxx_timer1_hwmod = { 246struct omap_hwmod omap2xxx_timer1_hwmod = {
258 .name = "timer1", 247 .name = "timer1",
259 .mpu_irqs = omap2_timer1_mpu_irqs,
260 .main_clk = "gpt1_fck", 248 .main_clk = "gpt1_fck",
261 .prcm = { 249 .prcm = {
262 .omap2 = { 250 .omap2 = {
@@ -276,7 +264,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
276 264
277struct omap_hwmod omap2xxx_timer2_hwmod = { 265struct omap_hwmod omap2xxx_timer2_hwmod = {
278 .name = "timer2", 266 .name = "timer2",
279 .mpu_irqs = omap2_timer2_mpu_irqs,
280 .main_clk = "gpt2_fck", 267 .main_clk = "gpt2_fck",
281 .prcm = { 268 .prcm = {
282 .omap2 = { 269 .omap2 = {
@@ -295,7 +282,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
295 282
296struct omap_hwmod omap2xxx_timer3_hwmod = { 283struct omap_hwmod omap2xxx_timer3_hwmod = {
297 .name = "timer3", 284 .name = "timer3",
298 .mpu_irqs = omap2_timer3_mpu_irqs,
299 .main_clk = "gpt3_fck", 285 .main_clk = "gpt3_fck",
300 .prcm = { 286 .prcm = {
301 .omap2 = { 287 .omap2 = {
@@ -314,7 +300,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
314 300
315struct omap_hwmod omap2xxx_timer4_hwmod = { 301struct omap_hwmod omap2xxx_timer4_hwmod = {
316 .name = "timer4", 302 .name = "timer4",
317 .mpu_irqs = omap2_timer4_mpu_irqs,
318 .main_clk = "gpt4_fck", 303 .main_clk = "gpt4_fck",
319 .prcm = { 304 .prcm = {
320 .omap2 = { 305 .omap2 = {
@@ -333,7 +318,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
333 318
334struct omap_hwmod omap2xxx_timer5_hwmod = { 319struct omap_hwmod omap2xxx_timer5_hwmod = {
335 .name = "timer5", 320 .name = "timer5",
336 .mpu_irqs = omap2_timer5_mpu_irqs,
337 .main_clk = "gpt5_fck", 321 .main_clk = "gpt5_fck",
338 .prcm = { 322 .prcm = {
339 .omap2 = { 323 .omap2 = {
@@ -353,7 +337,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
353 337
354struct omap_hwmod omap2xxx_timer6_hwmod = { 338struct omap_hwmod omap2xxx_timer6_hwmod = {
355 .name = "timer6", 339 .name = "timer6",
356 .mpu_irqs = omap2_timer6_mpu_irqs,
357 .main_clk = "gpt6_fck", 340 .main_clk = "gpt6_fck",
358 .prcm = { 341 .prcm = {
359 .omap2 = { 342 .omap2 = {
@@ -373,7 +356,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
373 356
374struct omap_hwmod omap2xxx_timer7_hwmod = { 357struct omap_hwmod omap2xxx_timer7_hwmod = {
375 .name = "timer7", 358 .name = "timer7",
376 .mpu_irqs = omap2_timer7_mpu_irqs,
377 .main_clk = "gpt7_fck", 359 .main_clk = "gpt7_fck",
378 .prcm = { 360 .prcm = {
379 .omap2 = { 361 .omap2 = {
@@ -393,7 +375,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
393 375
394struct omap_hwmod omap2xxx_timer8_hwmod = { 376struct omap_hwmod omap2xxx_timer8_hwmod = {
395 .name = "timer8", 377 .name = "timer8",
396 .mpu_irqs = omap2_timer8_mpu_irqs,
397 .main_clk = "gpt8_fck", 378 .main_clk = "gpt8_fck",
398 .prcm = { 379 .prcm = {
399 .omap2 = { 380 .omap2 = {
@@ -413,7 +394,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
413 394
414struct omap_hwmod omap2xxx_timer9_hwmod = { 395struct omap_hwmod omap2xxx_timer9_hwmod = {
415 .name = "timer9", 396 .name = "timer9",
416 .mpu_irqs = omap2_timer9_mpu_irqs,
417 .main_clk = "gpt9_fck", 397 .main_clk = "gpt9_fck",
418 .prcm = { 398 .prcm = {
419 .omap2 = { 399 .omap2 = {
@@ -433,7 +413,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
433 413
434struct omap_hwmod omap2xxx_timer10_hwmod = { 414struct omap_hwmod omap2xxx_timer10_hwmod = {
435 .name = "timer10", 415 .name = "timer10",
436 .mpu_irqs = omap2_timer10_mpu_irqs,
437 .main_clk = "gpt10_fck", 416 .main_clk = "gpt10_fck",
438 .prcm = { 417 .prcm = {
439 .omap2 = { 418 .omap2 = {
@@ -453,7 +432,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
453 432
454struct omap_hwmod omap2xxx_timer11_hwmod = { 433struct omap_hwmod omap2xxx_timer11_hwmod = {
455 .name = "timer11", 434 .name = "timer11",
456 .mpu_irqs = omap2_timer11_mpu_irqs,
457 .main_clk = "gpt11_fck", 435 .main_clk = "gpt11_fck",
458 .prcm = { 436 .prcm = {
459 .omap2 = { 437 .omap2 = {
@@ -473,7 +451,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
473 451
474struct omap_hwmod omap2xxx_timer12_hwmod = { 452struct omap_hwmod omap2xxx_timer12_hwmod = {
475 .name = "timer12", 453 .name = "timer12",
476 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
477 .main_clk = "gpt12_fck", 454 .main_clk = "gpt12_fck",
478 .prcm = { 455 .prcm = {
479 .omap2 = { 456 .omap2 = {
@@ -509,8 +486,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
509 486
510struct omap_hwmod omap2xxx_uart1_hwmod = { 487struct omap_hwmod omap2xxx_uart1_hwmod = {
511 .name = "uart1", 488 .name = "uart1",
512 .mpu_irqs = omap2_uart1_mpu_irqs,
513 .sdma_reqs = omap2_uart1_sdma_reqs,
514 .main_clk = "uart1_fck", 489 .main_clk = "uart1_fck",
515 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 490 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
516 .prcm = { 491 .prcm = {
@@ -529,8 +504,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
529 504
530struct omap_hwmod omap2xxx_uart2_hwmod = { 505struct omap_hwmod omap2xxx_uart2_hwmod = {
531 .name = "uart2", 506 .name = "uart2",
532 .mpu_irqs = omap2_uart2_mpu_irqs,
533 .sdma_reqs = omap2_uart2_sdma_reqs,
534 .main_clk = "uart2_fck", 507 .main_clk = "uart2_fck",
535 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 508 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
536 .prcm = { 509 .prcm = {
@@ -549,8 +522,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
549 522
550struct omap_hwmod omap2xxx_uart3_hwmod = { 523struct omap_hwmod omap2xxx_uart3_hwmod = {
551 .name = "uart3", 524 .name = "uart3",
552 .mpu_irqs = omap2_uart3_mpu_irqs,
553 .sdma_reqs = omap2_uart3_sdma_reqs,
554 .main_clk = "uart3_fck", 525 .main_clk = "uart3_fck",
555 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 526 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
556 .prcm = { 527 .prcm = {
@@ -610,7 +581,7 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
610 }, 581 },
611 }, 582 },
612 .flags = HWMOD_NO_IDLEST, 583 .flags = HWMOD_NO_IDLEST,
613 .dev_attr = &omap2_3_dss_dispc_dev_attr 584 .dev_attr = &omap2_3_dss_dispc_dev_attr,
614}; 585};
615 586
616static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 587static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
@@ -657,7 +628,6 @@ struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
657struct omap_hwmod omap2xxx_gpio1_hwmod = { 628struct omap_hwmod omap2xxx_gpio1_hwmod = {
658 .name = "gpio1", 629 .name = "gpio1",
659 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 630 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
660 .mpu_irqs = omap2_gpio1_irqs,
661 .main_clk = "gpios_fck", 631 .main_clk = "gpios_fck",
662 .prcm = { 632 .prcm = {
663 .omap2 = { 633 .omap2 = {
@@ -676,7 +646,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = {
676struct omap_hwmod omap2xxx_gpio2_hwmod = { 646struct omap_hwmod omap2xxx_gpio2_hwmod = {
677 .name = "gpio2", 647 .name = "gpio2",
678 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
679 .mpu_irqs = omap2_gpio2_irqs,
680 .main_clk = "gpios_fck", 649 .main_clk = "gpios_fck",
681 .prcm = { 650 .prcm = {
682 .omap2 = { 651 .omap2 = {
@@ -695,7 +664,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = {
695struct omap_hwmod omap2xxx_gpio3_hwmod = { 664struct omap_hwmod omap2xxx_gpio3_hwmod = {
696 .name = "gpio3", 665 .name = "gpio3",
697 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
698 .mpu_irqs = omap2_gpio3_irqs,
699 .main_clk = "gpios_fck", 667 .main_clk = "gpios_fck",
700 .prcm = { 668 .prcm = {
701 .omap2 = { 669 .omap2 = {
@@ -714,7 +682,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = {
714struct omap_hwmod omap2xxx_gpio4_hwmod = { 682struct omap_hwmod omap2xxx_gpio4_hwmod = {
715 .name = "gpio4", 683 .name = "gpio4",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 684 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .mpu_irqs = omap2_gpio4_irqs,
718 .main_clk = "gpios_fck", 685 .main_clk = "gpios_fck",
719 .prcm = { 686 .prcm = {
720 .omap2 = { 687 .omap2 = {
@@ -736,8 +703,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
736 703
737struct omap_hwmod omap2xxx_mcspi1_hwmod = { 704struct omap_hwmod omap2xxx_mcspi1_hwmod = {
738 .name = "mcspi1", 705 .name = "mcspi1",
739 .mpu_irqs = omap2_mcspi1_mpu_irqs,
740 .sdma_reqs = omap2_mcspi1_sdma_reqs,
741 .main_clk = "mcspi1_fck", 706 .main_clk = "mcspi1_fck",
742 .prcm = { 707 .prcm = {
743 .omap2 = { 708 .omap2 = {
@@ -759,8 +724,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
759 724
760struct omap_hwmod omap2xxx_mcspi2_hwmod = { 725struct omap_hwmod omap2xxx_mcspi2_hwmod = {
761 .name = "mcspi2", 726 .name = "mcspi2",
762 .mpu_irqs = omap2_mcspi2_mpu_irqs,
763 .sdma_reqs = omap2_mcspi2_sdma_reqs,
764 .main_clk = "mcspi2_fck", 727 .main_clk = "mcspi2_fck",
765 .prcm = { 728 .prcm = {
766 .omap2 = { 729 .omap2 = {
@@ -795,15 +758,9 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
795}; 758};
796 759
797/* gpmc */ 760/* gpmc */
798static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
799 { .irq = 20 },
800 { .irq = -1 }
801};
802
803struct omap_hwmod omap2xxx_gpmc_hwmod = { 761struct omap_hwmod omap2xxx_gpmc_hwmod = {
804 .name = "gpmc", 762 .name = "gpmc",
805 .class = &omap2xxx_gpmc_hwmod_class, 763 .class = &omap2xxx_gpmc_hwmod_class,
806 .mpu_irqs = omap2xxx_gpmc_irqs,
807 .main_clk = "gpmc_fck", 764 .main_clk = "gpmc_fck",
808 /* 765 /*
809 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP 766 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
@@ -840,14 +797,8 @@ static struct omap_hwmod_class omap2_rng_hwmod_class = {
840 .sysc = &omap2_rng_sysc, 797 .sysc = &omap2_rng_sysc,
841}; 798};
842 799
843static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
844 { .irq = 52 },
845 { .irq = -1 }
846};
847
848struct omap_hwmod omap2xxx_rng_hwmod = { 800struct omap_hwmod omap2xxx_rng_hwmod = {
849 .name = "rng", 801 .name = "rng",
850 .mpu_irqs = omap2_rng_mpu_irqs,
851 .main_clk = "l4_ck", 802 .main_clk = "l4_ck",
852 .prcm = { 803 .prcm = {
853 .omap2 = { 804 .omap2 = {
@@ -884,20 +835,8 @@ static struct omap_hwmod_class omap2xxx_sham_class = {
884 .sysc = &omap2_sham_sysc, 835 .sysc = &omap2_sham_sysc,
885}; 836};
886 837
887static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
888 { .irq = 51 + OMAP_INTC_START, },
889 { .irq = -1 }
890};
891
892static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
893 { .name = "rx", .dma_req = 13 },
894 { .dma_req = -1 }
895};
896
897struct omap_hwmod omap2xxx_sham_hwmod = { 838struct omap_hwmod omap2xxx_sham_hwmod = {
898 .name = "sham", 839 .name = "sham",
899 .mpu_irqs = omap2_sham_mpu_irqs,
900 .sdma_reqs = omap2_sham_sdma_chs,
901 .main_clk = "l4_ck", 840 .main_clk = "l4_ck",
902 .prcm = { 841 .prcm = {
903 .omap2 = { 842 .omap2 = {
@@ -927,15 +866,8 @@ static struct omap_hwmod_class omap2xxx_aes_class = {
927 .sysc = &omap2_aes_sysc, 866 .sysc = &omap2_aes_sysc,
928}; 867};
929 868
930static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
931 { .name = "tx", .dma_req = 9 },
932 { .name = "rx", .dma_req = 10 },
933 { .dma_req = -1 }
934};
935
936struct omap_hwmod omap2xxx_aes_hwmod = { 869struct omap_hwmod omap2xxx_aes_hwmod = {
937 .name = "aes", 870 .name = "aes",
938 .sdma_reqs = omap2_aes_sdma_chs,
939 .main_clk = "l4_ck", 871 .main_clk = "l4_ck",
940 .prcm = { 872 .prcm = {
941 .omap2 = { 873 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 6e04ff7065e1..2c38c6b0ee03 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -18,9 +18,6 @@
18#include "common.h" 18#include "common.h"
19#include "display.h" 19#include "display.h"
20 20
21/* Common address space across OMAP2xxx */
22extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
23
24/* Common address space across OMAP2xxx/3xxx */ 21/* Common address space across OMAP2xxx/3xxx */
25extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[]; 22extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
26extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[]; 23extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
@@ -41,8 +38,6 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
41extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; 38extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
42 39
43/* Common IP block data across OMAP2xxx */ 40/* Common IP block data across OMAP2xxx */
44extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
45extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
46extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; 41extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
47extern struct omap_hwmod omap2xxx_l3_main_hwmod; 42extern struct omap_hwmod omap2xxx_l3_main_hwmod;
48extern struct omap_hwmod omap2xxx_l4_core_hwmod; 43extern struct omap_hwmod omap2xxx_l4_core_hwmod;
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 10c71450cf63..5aaf720211f4 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -8,6 +8,7 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/davinci_emac.h>
11#include <linux/gpio.h> 12#include <linux/gpio.h>
12#include <linux/init.h> 13#include <linux/init.h>
13#include <linux/kernel.h> 14#include <linux/kernel.h>
@@ -16,6 +17,7 @@
16 17
17#include <linux/platform_data/pinctrl-single.h> 18#include <linux/platform_data/pinctrl-single.h>
18 19
20#include "am35xx.h"
19#include "common.h" 21#include "common.h"
20#include "common-board-devices.h" 22#include "common-board-devices.h"
21#include "dss-common.h" 23#include "dss-common.h"
@@ -26,6 +28,9 @@ struct pdata_init {
26 void (*fn)(void); 28 void (*fn)(void);
27}; 29};
28 30
31struct of_dev_auxdata omap_auxdata_lookup[];
32static struct twl4030_gpio_platform_data twl_gpio_auxdata;
33
29/* 34/*
30 * Create alias for USB host PHY clock. 35 * Create alias for USB host PHY clock.
31 * Remove this when clock phandle can be provided via DT 36 * Remove this when clock phandle can be provided via DT
@@ -68,6 +73,15 @@ static inline void legacy_init_wl12xx(unsigned ref_clock,
68} 73}
69#endif 74#endif
70 75
76#ifdef CONFIG_MACH_NOKIA_N8X0
77static void __init omap2420_n8x0_legacy_init(void)
78{
79 omap_auxdata_lookup[0].platform_data = n8x0_legacy_init();
80}
81#else
82#define omap2420_n8x0_legacy_init NULL
83#endif
84
71#ifdef CONFIG_ARCH_OMAP3 85#ifdef CONFIG_ARCH_OMAP3
72static void __init hsmmc2_internal_input_clk(void) 86static void __init hsmmc2_internal_input_clk(void)
73{ 87{
@@ -92,6 +106,42 @@ static void __init omap3_zoom_legacy_init(void)
92{ 106{
93 legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162); 107 legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162);
94} 108}
109
110static void am35xx_enable_emac_int(void)
111{
112 u32 v;
113
114 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
115 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
116 AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
117 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
118 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
119}
120
121static void am35xx_disable_emac_int(void)
122{
123 u32 v;
124
125 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
126 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
127 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
128 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
129}
130
131static struct emac_platform_data am35xx_emac_pdata = {
132 .interrupt_enable = am35xx_enable_emac_int,
133 .interrupt_disable = am35xx_disable_emac_int,
134};
135
136static void __init am3517_evm_legacy_init(void)
137{
138 u32 v;
139
140 v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
141 v &= ~AM35XX_CPGMACSS_SW_RST;
142 omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
143 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
144}
95#endif /* CONFIG_ARCH_OMAP3 */ 145#endif /* CONFIG_ARCH_OMAP3 */
96 146
97#ifdef CONFIG_ARCH_OMAP4 147#ifdef CONFIG_ARCH_OMAP4
@@ -125,10 +175,45 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void))
125 pcs_pdata.rearm = rearm; 175 pcs_pdata.rearm = rearm;
126} 176}
127 177
178/*
179 * GPIOs for TWL are initialized by the I2C bus and need custom
180 * handing until DSS has device tree bindings.
181 */
182void omap_auxdata_legacy_init(struct device *dev)
183{
184 if (dev->platform_data)
185 return;
186
187 if (strcmp("twl4030-gpio", dev_name(dev)))
188 return;
189
190 dev->platform_data = &twl_gpio_auxdata;
191}
192
193/*
194 * Few boards still need auxdata populated before we populate
195 * the dev entries in of_platform_populate().
196 */
197static struct pdata_init auxdata_quirks[] __initdata = {
198#ifdef CONFIG_SOC_OMAP2420
199 { "nokia,n800", omap2420_n8x0_legacy_init, },
200 { "nokia,n810", omap2420_n8x0_legacy_init, },
201 { "nokia,n810-wimax", omap2420_n8x0_legacy_init, },
202#endif
203 { /* sentinel */ },
204};
205
128struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { 206struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
207#ifdef CONFIG_MACH_NOKIA_N8X0
208 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
209#endif
129#ifdef CONFIG_ARCH_OMAP3 210#ifdef CONFIG_ARCH_OMAP3
130 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), 211 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
131 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), 212 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
213 /* Only on am3517 */
214 OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
215 OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
216 &am35xx_emac_pdata),
132#endif 217#endif
133#ifdef CONFIG_ARCH_OMAP4 218#ifdef CONFIG_ARCH_OMAP4
134 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), 219 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
@@ -137,13 +222,19 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
137 { /* sentinel */ }, 222 { /* sentinel */ },
138}; 223};
139 224
225/*
226 * Few boards still need to initialize some legacy devices with
227 * platform data until the drivers support device tree.
228 */
140static struct pdata_init pdata_quirks[] __initdata = { 229static struct pdata_init pdata_quirks[] __initdata = {
141#ifdef CONFIG_ARCH_OMAP3 230#ifdef CONFIG_ARCH_OMAP3
231 { "nokia,omap3-n900", hsmmc2_internal_input_clk, },
142 { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, 232 { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
143 { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, 233 { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
144 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, 234 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
145 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, 235 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
146 { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, 236 { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
237 { "ti,am3517-evm", am3517_evm_legacy_init, },
147#endif 238#endif
148#ifdef CONFIG_ARCH_OMAP4 239#ifdef CONFIG_ARCH_OMAP4
149 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, 240 { "ti,omap4-sdp", omap4_sdp_legacy_init, },
@@ -155,14 +246,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
155 { /* sentinel */ }, 246 { /* sentinel */ },
156}; 247};
157 248
158void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) 249static void pdata_quirks_check(struct pdata_init *quirks)
159{ 250{
160 struct pdata_init *quirks = pdata_quirks;
161
162 omap_sdrc_init(NULL, NULL);
163 of_platform_populate(NULL, omap_dt_match_table,
164 omap_auxdata_lookup, NULL);
165
166 while (quirks->compatible) { 251 while (quirks->compatible) {
167 if (of_machine_is_compatible(quirks->compatible)) { 252 if (of_machine_is_compatible(quirks->compatible)) {
168 if (quirks->fn) 253 if (quirks->fn)
@@ -172,3 +257,12 @@ void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
172 quirks++; 257 quirks++;
173 } 258 }
174} 259}
260
261void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
262{
263 omap_sdrc_init(NULL, NULL);
264 pdata_quirks_check(auxdata_quirks);
265 of_platform_populate(NULL, omap_dt_match_table,
266 omap_auxdata_lookup, NULL);
267 pdata_quirks_check(pdata_quirks);
268}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 93b80e5da8d4..1f3770a8a728 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -120,7 +120,7 @@ static void omap3_save_secure_ram_context(void)
120 * will hang the system. 120 * will hang the system.
121 */ 121 */
122 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 122 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
123 ret = _omap_save_secure_sram((u32 *) 123 ret = _omap_save_secure_sram((u32 *)(unsigned long)
124 __pa(omap3_secure_ram_storage)); 124 __pa(omap3_secure_ram_storage));
125 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 125 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
126 /* Following is for error tracking, it should not happen */ 126 /* Following is for error tracking, it should not happen */
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index e233dfcbc186..93a2a6e4260f 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -128,7 +128,8 @@ skip_voltdm:
128 for (i = 0; i < pwrdm->banks; i++) 128 for (i = 0; i < pwrdm->banks; i++)
129 pwrdm->ret_mem_off_counter[i] = 0; 129 pwrdm->ret_mem_off_counter[i] = 0;
130 130
131 arch_pwrdm->pwrdm_wait_transition(pwrdm); 131 if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
132 arch_pwrdm->pwrdm_wait_transition(pwrdm);
132 pwrdm->state = pwrdm_read_pwrst(pwrdm); 133 pwrdm->state = pwrdm_read_pwrst(pwrdm);
133 pwrdm->state_counter[pwrdm->state] = 1; 134 pwrdm->state_counter[pwrdm->state] = 1;
134 135
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 7a976065e138..8d95aa543ef5 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -43,7 +43,7 @@ extern void omap4_prm_vcvp_write(u32 val, u8 offset);
43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
44 44
45#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 45#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
46 defined(CONFIG_SOC_DRA7XX) 46 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
47void omap44xx_prm_reconfigure_io_chain(void); 47void omap44xx_prm_reconfigure_io_chain(void);
48#else 48#else
49static inline void omap44xx_prm_reconfigure_io_chain(void) 49static inline void omap44xx_prm_reconfigure_io_chain(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-01 11:41:41 -0400