90 files changed, 8705 insertions, 8992 deletions

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8141b76283a6..4cf5142f22cc 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -17,6 +17,7 @@ config ARCH_OMAP2PLUS_TYPICAL
         select MENELAUS if ARCH_OMAP2
         select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
         select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
+        select HIGHMEM
         help
           Compile a kernel suitable for booting most boards
 
@@ -77,12 +78,12 @@ config SOC_OMAP3430
         default y
         select ARCH_OMAP_OTG
 
-config SOC_OMAPTI81XX
+config SOC_TI81XX
         bool "TI81XX support"
         depends on ARCH_OMAP3
         default y
 
-config SOC_OMAPAM33XX
+config SOC_AM33XX
         bool "AM33XX support"
         depends on ARCH_OMAP3
         default y
@@ -319,12 +320,12 @@ config MACH_OMAP_3630SDP
 
 config MACH_TI8168EVM
         bool "TI8168 Evaluation Module"
-        depends on SOC_OMAPTI81XX
+        depends on SOC_TI81XX
         default y
 
 config MACH_TI8148EVM
         bool "TI8148 Evaluation Module"
-        depends on SOC_OMAPTI81XX
+        depends on SOC_TI81XX
         default y
 
 config MACH_OMAP_4430SDP
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 49f92bc1c311..fa742f3c2629 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o i2c.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
 
 omap-2-3-common                         = irq.o sdrc.o
 hwmod-common                            = omap_hwmod.o \
@@ -24,10 +24,11 @@ endif
 obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 
 # SMP support ONLY available for OMAP4
+
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o \
-                                           sleep44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o
+obj-$(CONFIG_ARCH_OMAP4)                += sleep44xx.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -64,10 +65,10 @@ endif
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o \
-                                           cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o \
-                                           cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
@@ -84,88 +85,86 @@ endif
 # PRCM
 obj-y                                   += prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
-obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
-                                           vc3xxx_data.o vp3xxx_data.o
-# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
-# will be removed once the OMAP4 part of the codebase is converted to
-# use OMAP4-specific PRCM functions.
-obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cm2xxx_3xxx.o cminst44xx.o \
-                                           cm44xx.o prcm_mpu44xx.o \
-                                           prminst44xx.o vc44xx_data.o \
-                                           vp44xx_data.o prm44xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cminst44xx.o cm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += prcm_mpu44xx.o prminst44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += vc44xx_data.o vp44xx_data.o prm44xx.o
 
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common) \
-                                           voltagedomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common) \
-                                           voltagedomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common) \
-                                           voltagedomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(voltagedomain-common)
+obj-$(CONFIG_ARCH_OMAP2)                += voltagedomains2xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(voltagedomain-common)
+obj-$(CONFIG_ARCH_OMAP3)                += voltagedomains3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
+obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
 
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
-obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common) \
-                                           powerdomain2xxx_3xxx.o \
-                                           powerdomains2xxx_data.o \
-                                           powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common) \
-                                           powerdomain2xxx_3xxx.o \
-                                           powerdomains3xxx_data.o \
-                                           powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common) \
-                                           powerdomain44xx.o \
-                                           powerdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common)
+obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_data.o
+obj-$(CONFIG_ARCH_OMAP2)                += powerdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common)
+obj-$(CONFIG_ARCH_OMAP3)                += powerdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += powerdomains3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common)
+obj-$(CONFIG_ARCH_OMAP4)                += powerdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
 
 # PRCM clockdomain control
-obj-$(CONFIG_ARCH_OMAP2)                += clockdomain.o \
-                                           clockdomain2xxx_3xxx.o \
-                                           clockdomains2xxx_3xxx_data.o
+clockdomain-common                      += clockdomain.o
+clockdomain-common                      += clockdomains_common_data.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common)
+obj-$(CONFIG_ARCH_OMAP2)                += clockdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clockdomain.o \
-                                           clockdomain2xxx_3xxx.o \
-                                           clockdomains2xxx_3xxx_data.o \
-                                           clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += clockdomain.o \
-                                           clockdomain44xx.o \
-                                           clockdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(clockdomain-common)
+obj-$(CONFIG_ARCH_OMAP3)                += clockdomain2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clockdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += clockdomains3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common)
+obj-$(CONFIG_ARCH_OMAP4)                += clockdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
 
 # Clock framework
-obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o \
-                                           clkt2xxx_sys.o \
-                                           clkt2xxx_dpllcore.o \
-                                           clkt2xxx_virt_prcm_set.o \
-                                           clkt2xxx_apll.o clkt2xxx_osc.o \
-                                           clkt2xxx_dpll.o clkt_iclk.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_sys.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpllcore.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_virt_prcm_set.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_apll.o clkt2xxx_osc.o
+obj-$(CONFIG_ARCH_OMAP2)                += clkt2xxx_dpll.o clkt_iclk.o
 obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o \
-                                           clock34xx.o clkt34xx_dpll3m2.o \
-                                           clock3517.o clock36xx.o \
-                                           dpll3xxx.o clock3xxx_data.o \
-                                           clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o \
-                                           dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o clkt34xx_dpll3m2.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o
+obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o clock3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)              += opp2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += opp2430_data.o
 
 # hwmod data
-obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o \
-                                           omap_hwmod_2xxx_3xxx_ipblock_data.o \
-                                           omap_hwmod_2xxx_interconnect_data.o \
-                                           omap_hwmod_2xxx_3xxx_interconnect_data.o \
-                                           omap_hwmod_2420_data.o
-obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2xxx_ipblock_data.o \
-                                           omap_hwmod_2xxx_3xxx_ipblock_data.o \
-                                           omap_hwmod_2xxx_interconnect_data.o \
-                                           omap_hwmod_2xxx_3xxx_interconnect_data.o \
-                                           omap_hwmod_2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_ipblock_data.o \
-                                           omap_hwmod_2xxx_3xxx_interconnect_data.o \
-                                           omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_ipblock_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_3xxx_ipblock_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_interconnect_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2xxx_3xxx_interconnect_data.o
+obj-$(CONFIG_SOC_OMAP2420)              += omap_hwmod_2420_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2xxx_ipblock_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2xxx_3xxx_ipblock_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2xxx_interconnect_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2xxx_3xxx_interconnect_data.o
+obj-$(CONFIG_SOC_OMAP2430)              += omap_hwmod_2430_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_ipblock_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_interconnect_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 
 # EMU peripherals
@@ -187,6 +186,9 @@ ifneq ($(CONFIG_TIDSPBRIDGE),)
 obj-y                                   += dsp.o
 endif
 
+# OMAP2420 MSDI controller integration support ("MMC")
+obj-$(CONFIG_SOC_OMAP2420)              += msdi.o
+
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
@@ -203,23 +205,19 @@ obj-$(CONFIG_MACH_OMAP3EVM)		+= board-omap3evm.o
 obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o
 obj-$(CONFIG_MACH_OMAP_3430SDP)         += board-3430sdp.o
 obj-$(CONFIG_MACH_NOKIA_N8X0)           += board-n8x0.o
-obj-$(CONFIG_MACH_NOKIA_RM680)          += board-rm680.o \
-                                           sdram-nokia.o
-obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
-                                           sdram-nokia.o \
-                                           board-rx51-peripherals.o \
-                                           board-rx51-video.o
-obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom.o \
-                                           board-zoom-peripherals.o \
-                                           board-zoom-display.o \
-                                           board-zoom-debugboard.o
-obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom.o \
-                                           board-zoom-peripherals.o \
-                                           board-zoom-display.o \
-                                           board-zoom-debugboard.o
-obj-$(CONFIG_MACH_OMAP_3630SDP)         += board-3630sdp.o \
-                                           board-zoom-peripherals.o \
-                                           board-zoom-display.o
+obj-$(CONFIG_MACH_NOKIA_RM680)          += board-rm680.o sdram-nokia.o
+obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o sdram-nokia.o
+obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51-peripherals.o
+obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51-video.o
+obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom.o board-zoom-peripherals.o
+obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom-display.o
+obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom-debugboard.o
+obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom.o board-zoom-peripherals.o
+obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom-display.o
+obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom-debugboard.o
+obj-$(CONFIG_MACH_OMAP_3630SDP)         += board-3630sdp.o
+obj-$(CONFIG_MACH_OMAP_3630SDP)         += board-zoom-peripherals.o
+obj-$(CONFIG_MACH_OMAP_3630SDP)         += board-zoom-display.o
 obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 1f97e7475206..447682c4e11c 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -39,26 +39,23 @@ static struct platform_device am35xx_emac_mdio_device = {
 
 static void am35xx_enable_emac_int(void)
 {
-        u32 regval;
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
-                  AM35XX_CPGMAC_C0_TX_PULSE_CLR |
-                  AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
-                  AM35XX_CPGMAC_C0_RX_THRESH_CLR);
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        u32 v;
+
+        v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
+              AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
+        omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
 }
 
 static void am35xx_disable_emac_int(void)
 {
-        u32 regval;
+        u32 v;
 
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
-                  AM35XX_CPGMAC_C0_TX_PULSE_CLR);
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
+        omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
 }
 
 static struct emac_platform_data am35xx_emac_pdata = {
@@ -92,7 +89,7 @@ static struct platform_device am35xx_emac_device = {
 
 void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
 {
-        unsigned int regval;
+        u32 v;
         int err;
 
         am35xx_emac_pdata.rmii_en = rmii_en;
@@ -110,8 +107,8 @@ void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
                 return;
         }
 
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-        regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
-        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+        v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+        v &= ~AM35XX_CPGMACSS_SW_RST;
+        omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
+        omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
 }
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index da75f239873e..37abb0d49b51 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -37,7 +37,7 @@
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 
 #include <plat/gpmc-smc91x.h>
 
@@ -113,9 +113,6 @@ static struct gpio sdp3430_dss_gpios[] __initdata = {
         {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
 };
 
-static int lcd_enabled;
-static int dvi_enabled;
-
 static void __init sdp3430_display_init(void)
 {
         int r;
@@ -129,44 +126,18 @@ static void __init sdp3430_display_init(void)
 
 static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
 {
-        if (dvi_enabled) {
-                printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-                return -EINVAL;
-        }
-
         gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
         gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
 
-        lcd_enabled = 1;
-
         return 0;
 }
 
 static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
-        lcd_enabled = 0;
-
         gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
         gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
 }
 
-static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-
-        dvi_enabled = 1;
-
-        return 0;
-}
-
-static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        dvi_enabled = 0;
-}
-
 static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
 {
         return 0;
@@ -186,15 +157,14 @@ static struct omap_dss_device sdp3430_lcd_device = {
         .platform_disable       = sdp3430_panel_disable_lcd,
 };
 
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = sdp3430_panel_enable_dvi,
-        .platform_disable       = sdp3430_panel_disable_dvi,
+static struct tfp410_platform_data dvi_panel = {
+        .power_down_gpio        = -1,
 };
 
 static struct omap_dss_device sdp3430_dvi_device = {
         .name                   = "dvi",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
 };
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 130ab00c09a2..94af6cde2e36 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -384,6 +384,11 @@ static struct platform_device sdp4430_dmic_codec = {
         .id     = -1,
 };
 
+static struct platform_device sdp4430_hdmi_audio_codec = {
+        .name   = "hdmi-audio-codec",
+        .id     = -1,
+};
+
 static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
         .card_name = "SDP4430",
         .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
@@ -418,6 +423,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_vbat,
         &sdp4430_dmic_codec,
         &sdp4430_abe_audio,
+        &sdp4430_hdmi_audio_codec,
 };
 
 static struct omap_musb_board_data musb_board_data = {
@@ -489,50 +495,6 @@ static struct platform_device omap_vwlan_device = {
         },
 };
 
-static int omap4_twl6030_hsmmc_late_init(struct device *dev)
-{
-        int irq = 0;
-        struct platform_device *pdev = container_of(dev,
-                                struct platform_device, dev);
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
-
-        /* Setting MMC1 Card detect Irq */
-        if (pdev->id == 0) {
-                irq = twl6030_mmc_card_detect_config();
-                if (irq < 0) {
-                        pr_err("Failed configuring MMC1 card detect\n");
-                        return irq;
-                }
-                pdata->slots[0].card_detect_irq = irq;
-                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
-        }
-        return 0;
-}
-
-static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
-{
-        struct omap_mmc_platform_data *pdata;
-
-        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
-        if (!dev) {
-                pr_err("Failed %s\n", __func__);
-                return;
-        }
-        pdata = dev->platform_data;
-        pdata->init =   omap4_twl6030_hsmmc_late_init;
-}
-
-static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
-{
-        struct omap2_hsmmc_info *c;
-
-        omap_hsmmc_init(controllers);
-        for (c = controllers; c->mmc; c++)
-                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
-
-        return 0;
-}
-
 static struct regulator_init_data sdp4430_vaux1 = {
         .constraints = {
                 .min_uV                 = 1000000,
@@ -615,7 +577,9 @@ static int __init omap4_i2c_init(void)
                         TWL_COMMON_REGULATOR_VANA |
                         TWL_COMMON_REGULATOR_VCXIO |
                         TWL_COMMON_REGULATOR_VUSB |
-                        TWL_COMMON_REGULATOR_CLK32KG);
+                        TWL_COMMON_REGULATOR_CLK32KG |
+                        TWL_COMMON_REGULATOR_V1V8 |
+                        TWL_COMMON_REGULATOR_V2V1);
         omap4_pmic_init("twl6030", &sdp4430_twldata,
                         &twl6040_data, OMAP44XX_IRQ_SYS_2N);
         omap_register_i2c_bus(2, 400, NULL, 0);
@@ -666,6 +630,10 @@ static struct nokia_dsi_panel_data dsi1_panel = {
                 .use_ext_te     = false,
                 .ext_te_gpio    = 101,
                 .esd_interval   = 0,
+                .pin_config = {
+                        .num_pins       = 6,
+                        .pins           = { 0, 1, 2, 3, 4, 5 },
+                },
 };
 
 static struct omap_dss_device sdp4430_lcd_device = {
@@ -674,13 +642,6 @@ static struct omap_dss_device sdp4430_lcd_device = {
         .type                   = OMAP_DISPLAY_TYPE_DSI,
         .data                   = &dsi1_panel,
         .phy.dsi                = {
-                .clk_lane       = 1,
-                .clk_pol        = 0,
-                .data1_lane     = 2,
-                .data1_pol      = 0,
-                .data2_lane     = 3,
-                .data2_pol      = 0,
-
                 .module         = 0,
         },
 
@@ -715,6 +676,10 @@ static struct nokia_dsi_panel_data dsi2_panel = {
                 .use_ext_te     = false,
                 .ext_te_gpio    = 103,
                 .esd_interval   = 0,
+                .pin_config = {
+                        .num_pins       = 6,
+                        .pins           = { 0, 1, 2, 3, 4, 5 },
+                },
 };
 
 static struct omap_dss_device sdp4430_lcd2_device = {
@@ -723,12 +688,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
         .type                   = OMAP_DISPLAY_TYPE_DSI,
         .data                   = &dsi2_panel,
         .phy.dsi                = {
-                .clk_lane       = 1,
-                .clk_pol        = 0,
-                .data1_lane     = 2,
-                .data1_pol      = 0,
-                .data2_lane     = 3,
-                .data2_pol      = 0,
 
                 .module         = 1,
         },
@@ -758,21 +717,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
         .channel                = OMAP_DSS_CHANNEL_LCD2,
 };
 
-static void sdp4430_lcd_init(void)
-{
-        int r;
-
-        r = gpio_request_one(dsi1_panel.reset_gpio, GPIOF_DIR_OUT,
-                "lcd1_reset_gpio");
-        if (r)
-                pr_err("%s: Could not get lcd1_reset_gpio\n", __func__);
-
-        r = gpio_request_one(dsi2_panel.reset_gpio, GPIOF_DIR_OUT,
-                "lcd2_reset_gpio");
-        if (r)
-                pr_err("%s: Could not get lcd2_reset_gpio\n", __func__);
-}
-
 static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
         .hpd_gpio = HDMI_GPIO_HPD,
 };
@@ -858,7 +802,6 @@ static void __init omap_4430sdp_display_init(void)
         if (r)
                 pr_err("%s: Could not get display_sel GPIO\n", __func__);
 
-        sdp4430_lcd_init();
         sdp4430_picodlp_init();
         omap_display_init(&sdp4430_dss_data);
         /*
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index c3851e8de28b..3b8a53c1f2a8 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -30,6 +30,7 @@
 #include "common.h"
 #include <plat/usb.h>
 
+#include "am35xx-emac.h"
 #include "mux.h"
 #include "control.h"
 
@@ -90,6 +91,7 @@ static void __init am3517_crane_init(void)
         }
 
         usbhs_init(&usbhs_bdata);
+        am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
 
 MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 3645285a3e2b..99790eb646e8 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -37,7 +37,7 @@
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 
 #include "am35xx-emac.h"
 #include "mux.h"
@@ -207,31 +207,14 @@ static struct omap_dss_device am3517_evm_tv_device = {
         .platform_disable       = am3517_evm_panel_disable_tv,
 };
 
-static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        dvi_enabled = 1;
-
-        return 0;
-}
-
-static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        dvi_enabled = 0;
-}
-
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = am3517_evm_panel_enable_dvi,
-        .platform_disable       = am3517_evm_panel_disable_dvi,
+static struct tfp410_platform_data dvi_panel = {
+        .power_down_gpio        = -1,
 };
 
 static struct omap_dss_device am3517_evm_dvi_device = {
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .name                   = "dvi",
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
 };
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 909a8b91b564..c03df142ea67 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -44,7 +44,7 @@
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/mcspi.h>
 
 #include <mach/hardware.h>
@@ -218,25 +218,6 @@ static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
         gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
 }
 
-static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-
-        gpio_set_value(CM_T35_DVI_EN_GPIO, 0);
-        dvi_enabled = 1;
-
-        return 0;
-}
-
-static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(CM_T35_DVI_EN_GPIO, 1);
-        dvi_enabled = 0;
-}
-
 static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
 {
         return 0;
@@ -260,15 +241,14 @@ static struct omap_dss_device cm_t35_lcd_device = {
         .phy.dpi.data_lines     = 18,
 };
 
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = cm_t35_panel_enable_dvi,
-        .platform_disable       = cm_t35_panel_disable_dvi,
+static struct tfp410_platform_data dvi_panel = {
+        .power_down_gpio        = CM_T35_DVI_EN_GPIO,
 };
 
 static struct omap_dss_device cm_t35_dvi_device = {
         .name                   = "dvi",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
 };
@@ -316,7 +296,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
 static struct gpio cm_t35_dss_gpios[] __initdata = {
         { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,  "lcd enable"    },
         { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW,  "lcd bl enable" },
-        { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable"    },
 };
 
 static void __init cm_t35_init_display(void)
@@ -335,7 +314,6 @@ static void __init cm_t35_init_display(void)
 
         gpio_export(CM_T35_LCD_EN_GPIO, 0);
         gpio_export(CM_T35_LCD_BL_GPIO, 0);
-        gpio_export(CM_T35_DVI_EN_GPIO, 0);
 
         msleep(50);
         gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
@@ -498,6 +476,10 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
         .setup          = cm_t35_twl_gpio_setup,
 };
 
+static struct twl4030_power_data cm_t35_power_data = {
+        .use_poweroff   = true,
+};
+
 static struct twl4030_platform_data cm_t35_twldata = {
         /* platform_data for children goes here */
         .keypad         = &cm_t35_kp_data,
@@ -505,6 +487,7 @@ static struct twl4030_platform_data cm_t35_twldata = {
         .vmmc1          = &cm_t35_vmmc1,
         .vsim           = &cm_t35_vsim,
         .vio            = &cm_t35_vio,
+        .power          = &cm_t35_power_data,
 };
 
 static void __init cm_t35_init_i2c(void)
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a2010f07de31..b063f0d2faa6 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -47,7 +47,7 @@
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
@@ -118,19 +118,6 @@ static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
                 gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
 
-static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
-        return 0;
-}
-
-static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
-}
-
 static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
         REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
@@ -154,15 +141,14 @@ static struct omap_dss_device devkit8000_lcd_device = {
         .phy.dpi.data_lines     = 24,
 };
 
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = devkit8000_panel_enable_dvi,
-        .platform_disable       = devkit8000_panel_disable_dvi,
+static struct tfp410_platform_data dvi_panel = {
+        .power_down_gpio        = -1,
 };
 
 static struct omap_dss_device devkit8000_dvi_device = {
         .name                   = "dvi",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
 };
@@ -244,13 +230,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
         }
 
         /* gpio + 7 is "DVI_PD" (out, active low) */
-        devkit8000_dvi_device.reset_gpio = gpio + 7;
-        ret = gpio_request_one(devkit8000_dvi_device.reset_gpio,
-                               GPIOF_OUT_INIT_LOW, "DVI PowerDown");
-        if (ret < 0) {
-                devkit8000_dvi_device.reset_gpio = -EINVAL;
-                printk(KERN_ERR "Failed to request GPIO for DVI PowerDown\n");
-        }
+        dvi_panel.power_down_gpio = gpio + 7;
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 0349fd2b68d8..70a81f900bb5 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -87,7 +87,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
         .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
 };
 
-static void
+void
 __init board_onenand_init(struct mtd_partition *onenand_parts,
                                 u8 nr_parts, u8 cs)
 {
@@ -98,7 +98,7 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
         gpmc_onenand_init(&board_onenand_data);
 }
 #else
-static void
+void
 __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
 {
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index d25503a98417..c44b70d52021 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -47,3 +47,14 @@ static inline void board_nand_init(struct mtd_partition *nand_parts,
 {
 }
 #endif
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+                defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+extern void board_onenand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs);
+#else
+static inline void board_onenand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs)
+{
+}
+#endif
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 098d183a0086..7302ba7ff1b9 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -15,7 +15,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
-#include <linux/i2c/twl.h>
 
 #include <mach/hardware.h>
 #include <asm/hardware/gic.h>
@@ -95,22 +94,6 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-static struct twl4030_platform_data beagle_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-};
-
-static void __init omap3_i2c_init(void)
-{
-        omap3_pmic_init("twl4030", &beagle_twldata);
-}
-
-static void __init omap3_init(void)
-{
-        omap3_i2c_init();
-        omap_generic_init();
-}
-
 static const char *omap3_boards_compat[] __initdata = {
         "ti,omap3",
         NULL,
@@ -122,7 +105,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
         .init_early     = omap3430_init_early,
         .init_irq       = omap_init_irq,
         .handle_irq     = omap3_intc_handle_irq,
-        .init_machine   = omap3_init,
+        .init_machine   = omap_generic_init,
         .timer          = &omap3_timer,
         .dt_compat      = omap3_boards_compat,
         .restart        = omap_prcm_restart,
@@ -130,22 +113,6 @@ MACHINE_END
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-static struct twl4030_platform_data sdp4430_twldata = {
-        .irq_base       = TWL6030_IRQ_BASE,
-        .irq_end        = TWL6030_IRQ_END,
-};
-
-static void __init omap4_i2c_init(void)
-{
-        omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0);
-}
-
-static void __init omap4_init(void)
-{
-        omap4_i2c_init();
-        omap_generic_init();
-}
-
 static const char *omap4_boards_compat[] __initdata = {
         "ti,omap4",
         NULL,
@@ -157,7 +124,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
         .init_early     = omap4430_init_early,
         .init_irq       = omap_init_irq,
         .handle_irq     = gic_handle_irq,
-        .init_machine   = omap4_init,
+        .init_machine   = omap_generic_init,
         .timer          = &omap4_timer,
         .dt_compat      = omap4_boards_compat,
         .restart        = omap_prcm_restart,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 930c0d380435..7a274098f67b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -24,6 +24,8 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
 
+#include <linux/mtd/nand.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
@@ -32,13 +34,15 @@
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/onenand.h>
 
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
+#include "control.h"
 
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
@@ -60,6 +64,10 @@
 #define IGEP3_GPIO_LED1_RED     16
 #define IGEP3_GPIO_USBH_NRESET  183
 
+#define IGEP_SYSBOOT_MASK           0x1f
+#define IGEP_SYSBOOT_NAND           0x0f
+#define IGEP_SYSBOOT_ONENAND        0x10
+
 /*
  * IGEP2 Hardware Revision Table
  *
@@ -110,8 +118,10 @@ static void __init igep2_get_revision(void)
         gpio_free(IGEP2_GPIO_LED1_RED);
 }
 
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+#if defined(CONFIG_MTD_ONENAND_OMAP2) ||                \
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) ||     \
+        defined(CONFIG_MTD_NAND_OMAP2) ||               \
+        defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 
 #define ONENAND_MAP             0x20000000
 
@@ -123,7 +133,7 @@ static void __init igep2_get_revision(void)
  * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
  */
 
-static struct mtd_partition igep_onenand_partitions[] = {
+static struct mtd_partition igep_flash_partitions[] = {
         {
                 .name           = "X-Loader",
                 .offset         = 0,
@@ -151,50 +161,28 @@ static struct mtd_partition igep_onenand_partitions[] = {
         },
 };
 
-static struct omap_onenand_platform_data igep_onenand_data = {
-        .parts = igep_onenand_partitions,
-        .nr_parts = ARRAY_SIZE(igep_onenand_partitions),
-        .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
-};
-
-static struct platform_device igep_onenand_device = {
-        .name           = "omap2-onenand",
-        .id             = -1,
-        .dev = {
-                .platform_data = &igep_onenand_data,
-        },
-};
+static inline u32 igep_get_sysboot_value(void)
+{
+        return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK;
+}
 
 static void __init igep_flash_init(void)
 {
-        u8 cs = 0;
-        u8 onenandcs = GPMC_CS_NUM + 1;
-
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-                u32 ret;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                /* Check if NAND/oneNAND is configured */
-                if ((ret & 0xC00) == 0x800)
-                        /* NAND found */
-                        pr_err("IGEP: Unsupported NAND found\n");
-                else {
-                        ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-                        if ((ret & 0x3F) == (ONENAND_MAP >> 24))
-                                /* ONENAND found */
-                                onenandcs = cs;
-                }
-        }
-
-        if (onenandcs > GPMC_CS_NUM) {
-                pr_err("IGEP: Unable to find configuration in GPMC\n");
-                return;
+        u32 mux;
+        mux = igep_get_sysboot_value();
+
+        if (mux == IGEP_SYSBOOT_NAND) {
+                pr_info("IGEP: initializing NAND memory device\n");
+                board_nand_init(igep_flash_partitions,
+                                ARRAY_SIZE(igep_flash_partitions),
+                                0, NAND_BUSWIDTH_16);
+        } else if (mux == IGEP_SYSBOOT_ONENAND) {
+                pr_info("IGEP: initializing OneNAND memory device\n");
+                board_onenand_init(igep_flash_partitions,
+                                   ARRAY_SIZE(igep_flash_partitions), 0);
+        } else {
+                pr_err("IGEP: Flash: unsupported sysboot sequence found\n");
         }
-
-        igep_onenand_data.cs = onenandcs;
-
-        if (platform_device_register(&igep_onenand_device) < 0)
-                pr_err("IGEP: Unable to register OneNAND device\n");
 }
 
 #else
@@ -444,28 +432,15 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
         .setup          = igep_twl_gpio_setup,
 };
 
-static int igep2_enable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
-
-        return 0;
-}
-
-static void igep2_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0);
-}
-
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = igep2_enable_dvi,
-        .platform_disable       = igep2_disable_dvi,
-        .i2c_bus_num = 3,
+static struct tfp410_platform_data dvi_panel = {
+        .i2c_bus_num            = 3,
+        .power_down_gpio        = IGEP2_GPIO_DVI_PUP,
 };
 
 static struct omap_dss_device igep2_dvi_device = {
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .name                   = "dvi",
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
 };
@@ -480,14 +455,6 @@ static struct omap_dss_board_info igep2_dss_data = {
         .default_device = &igep2_dvi_device,
 };
 
-static void __init igep2_display_init(void)
-{
-        int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
-                                   "GPIO_DVI_PUP");
-        if (err)
-                pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
-}
-
 static struct platform_device *igep_devices[] __initdata = {
         &igep_vwlan_device,
 };
@@ -540,7 +507,10 @@ static void __init igep_i2c_init(void)
 {
         int ret;
 
-        omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0);
+        omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB,
+                              TWL_COMMON_REGULATOR_VPLL2);
+        igep_twldata.vpll2->constraints.apply_uV = true;
+        igep_twldata.vpll2->constraints.name = "VDVI";
 
         if (machine_is_igep0020()) {
                 /*
@@ -554,10 +524,7 @@ static void __init igep_i2c_init(void)
 
                 igep_twldata.keypad     = &igep2_keypad_pdata;
                 /* Get common pmic data */
-                omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO,
-                                      TWL_COMMON_REGULATOR_VPLL2);
-                igep_twldata.vpll2->constraints.apply_uV = true;
-                igep_twldata.vpll2->constraints.name = "VDVI";
+                omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0);
         }
 
         omap3_pmic_init("twl4030", &igep_twldata);
@@ -641,7 +608,7 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 
 static void __init igep_init(void)
 {
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+        regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         /* Get IGEP2 hardware revision */
@@ -668,7 +635,6 @@ static void __init igep_init(void)
 
         if (machine_is_igep0020()) {
                 omap_display_init(&igep2_dss_data);
-                igep2_display_init();
                 igep2_init_smsc911x();
                 usbhs_init(&igep2_usbhs_bdata);
         } else {
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7be8d659d91d..2a7b9a9da1db 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -42,7 +42,7 @@
 #include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -83,11 +83,13 @@ static struct {
         int usb_pwr_level;
         int reset_gpio;
         int usr_button_gpio;
+        int mmc_caps;
 } beagle_config = {
         .mmc1_gpio_wp = -EINVAL,
         .usb_pwr_level = GPIOF_OUT_INIT_LOW,
         .reset_gpio = 129,
         .usr_button_gpio = 4,
+        .mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 };
 
 static struct gpio omap3_beagle_rev_gpios[] __initdata = {
@@ -145,10 +147,12 @@ static void __init omap3_beagle_init_rev(void)
                 printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n");
                 omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
                 beagle_config.usb_pwr_level = GPIOF_OUT_INIT_HIGH;
+                beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
                 break;
         case 2:
                 printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n");
                 omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC;
+                beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
                 break;
         default:
                 printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
@@ -189,33 +193,17 @@ static struct mtd_partition omap3beagle_nand_partitions[] = {
 
 /* DSS */
 
-static int beagle_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 1);
-
-        return 0;
-}
-
-static void beagle_disable_dvi(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 0);
-}
-
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable = beagle_enable_dvi,
-        .platform_disable = beagle_disable_dvi,
+static struct tfp410_platform_data dvi_panel = {
         .i2c_bus_num = 3,
+        .power_down_gpio = -1,
 };
 
 static struct omap_dss_device beagle_dvi_device = {
         .type = OMAP_DISPLAY_TYPE_DPI,
         .name = "dvi",
-        .driver_name = "dvi",
+        .driver_name = "tfp410",
         .data = &dvi_panel,
         .phy.dpi.data_lines = 24,
-        .reset_gpio = -EINVAL,
 };
 
 static struct omap_dss_device beagle_tv_device = {
@@ -236,22 +224,12 @@ static struct omap_dss_board_info beagle_dss_data = {
         .default_device = &beagle_dvi_device,
 };
 
-static void __init beagle_display_init(void)
-{
-        int r;
-
-        r = gpio_request_one(beagle_dvi_device.reset_gpio, GPIOF_OUT_INIT_LOW,
-                             "DVI reset");
-        if (r < 0)
-                printk(KERN_ERR "Unable to get DVI reset GPIO\n");
-}
-
 #include "sdram-micron-mt46h32m32lf-6.h"
 
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_wp        = -EINVAL,
                 .deferred       = true,
         },
@@ -309,7 +287,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
                 if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
                         pr_err("%s: unable to configure EHCI_nOC\n", __func__);
         }
-        beagle_dvi_device.reset_gpio = beagle_config.reset_gpio;
+        dvi_panel.power_down_gpio = beagle_config.reset_gpio;
 
         gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
                         "nEN_USB_PWR");
@@ -523,6 +501,7 @@ static void __init omap3_beagle_init(void)
 
         if (beagle_config.mmc1_gpio_wp != -EINVAL)
                 omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+        mmc[0].caps = beagle_config.mmc_caps;
         omap_hsmmc_init(mmc);
 
         omap3_beagle_i2c_init();
@@ -552,7 +531,6 @@ static void __init omap3_beagle_init(void)
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
         omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 
-        beagle_display_init();
         beagle_opp_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 49df12735b41..ace3c675e9c2 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -46,7 +46,7 @@
 #include "common.h"
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -219,35 +219,14 @@ static struct omap_dss_device omap3_evm_tv_device = {
         .platform_disable       = omap3_evm_disable_tv,
 };
 
-static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-
-        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
-
-        dvi_enabled = 1;
-        return 0;
-}
-
-static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
-
-        dvi_enabled = 0;
-}
-
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = omap3_evm_enable_dvi,
-        .platform_disable       = omap3_evm_disable_dvi,
+static struct tfp410_platform_data dvi_panel = {
+        .power_down_gpio        = OMAP3EVM_DVI_PANEL_EN_GPIO,
 };
 
 static struct omap_dss_device omap3_evm_dvi_device = {
         .name                   = "dvi",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
 };
@@ -630,13 +609,13 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 
 static void __init omap3_evm_init(void)
 {
+        struct omap_board_mux *obm;
+
         omap3_evm_get_revision();
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
-        if (cpu_is_omap3630())
-                omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
-        else
-                omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
+        obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
+        omap3_mux_init(obm, OMAP_PACKAGE_CBB);
 
         omap_board_config = omap3_evm_config;
         omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 9b3c141ff51b..c008bf8e1c36 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -4,8 +4,9 @@
  * Copyright (C) 2010 Li-Pro.Net
  * Stephan Linz <linz@li-pro.net>
  *
- * Copyright (C) 2010 Logic Product Development, Inc.
+ * Copyright (C) 2010-2012 Logic Product Development, Inc.
  * Peter Barada <peter.barada@logicpd.com>
+ * Ashwin BIhari <ashwin.bihari@logicpd.com>
  *
  * Modified from Beagle, EVM, and RX51
  *
@@ -45,6 +46,7 @@
 #include <plat/gpmc-smsc911x.h>
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
+#include <plat/usb.h>
 
 #define OMAP3LOGIC_SMSC911X_CS                  1
 
@@ -85,6 +87,11 @@ static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
                         | BIT(13) | BIT(15) | BIT(16) | BIT(17),
 };
 
+static struct twl4030_usb_data omap3logic_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
+
 static struct twl4030_platform_data omap3logic_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -92,6 +99,7 @@ static struct twl4030_platform_data omap3logic_twldata = {
         /* platform_data for children goes here */
         .gpio           = &omap3logic_gpio_data,
         .vmmc1          = &omap3logic_vmmc1,
+        .usb            = &omap3logic_usb_data,
 };
 
 static int __init omap3logic_i2c_init(void)
@@ -185,6 +193,20 @@ static inline void __init board_smsc911x_init(void)
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* mUSB */
+        OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #endif
@@ -205,6 +227,8 @@ static void __init omap3logic_init(void)
         board_mmc_init();
         board_smsc911x_init();
 
+        usb_musb_init(NULL);
+
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
         omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 4dffc95bddd2..4396bae91677 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -42,7 +42,7 @@
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
@@ -92,9 +92,6 @@ static inline void __init omap3stalker_init_eth(void)
 #define LCD_PANEL_BKLIGHT_GPIO  210
 #define ENABLE_VPLL2_DEV_GRP    0xE0
 
-static int lcd_enabled;
-static int dvi_enabled;
-
 static void __init omap3_stalker_display_init(void)
 {
         return;
@@ -122,32 +119,14 @@ static struct omap_dss_device omap3_stalker_tv_device = {
         .platform_disable       = omap3_stalker_disable_tv,
 };
 
-static int omap3_stalker_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        gpio_set_value(DSS_ENABLE_GPIO, 1);
-        dvi_enabled = 1;
-        return 0;
-}
-
-static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(DSS_ENABLE_GPIO, 0);
-        dvi_enabled = 0;
-}
-
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = omap3_stalker_enable_dvi,
-        .platform_disable       = omap3_stalker_disable_dvi,
+static struct tfp410_platform_data dvi_panel = {
+        .power_down_gpio        = DSS_ENABLE_GPIO,
 };
 
 static struct omap_dss_device omap3_stalker_dvi_device = {
         .name                   = "dvi",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
 };
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 1b782ba53433..68b8fc9ff010 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -28,6 +28,7 @@
 #include <linux/mfd/twl6040.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
+#include <linux/ti_wilink_st.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
 
@@ -42,7 +43,7 @@
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 
 #include "hsmmc.h"
 #include "control.h"
@@ -58,12 +59,21 @@
 #define HDMI_GPIO_HPD  63 /* Hotplug detect */
 
 /* wl127x BT, FM, GPS connectivity chip */
-static int wl1271_gpios[] = {46, -1, -1};
+static struct ti_st_plat_data wilink_platform_data = {
+        .nshutdown_gpio = 46,
+        .dev_name       = "/dev/ttyO1",
+        .flow_cntrl     = 1,
+        .baud_rate      = 3000000,
+        .chip_enable    = NULL,
+        .suspend        = NULL,
+        .resume         = NULL,
+};
+
 static struct platform_device wl1271_device = {
         .name   = "kim",
         .id     = -1,
         .dev    = {
-                .platform_data  = &wl1271_gpios,
+                .platform_data  = &wilink_platform_data,
         },
 };
 
@@ -117,6 +127,11 @@ static struct platform_device panda_abe_audio = {
         },
 };
 
+static struct platform_device panda_hdmi_audio_codec = {
+        .name   = "hdmi-audio-codec",
+        .id     = -1,
+};
+
 static struct platform_device btwilink_device = {
         .name   = "btwilink",
         .id     = -1,
@@ -126,6 +141,7 @@ static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
         &wl1271_device,
         &panda_abe_audio,
+        &panda_hdmi_audio_codec,
         &btwilink_device,
 };
 
@@ -231,60 +247,11 @@ static struct platform_device omap_vwlan_device = {
         },
 };
 
-struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
+static struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
         /* PANDA ref clock is 38.4 MHz */
         .board_ref_clock = 2,
 };
 
-static int omap4_twl6030_hsmmc_late_init(struct device *dev)
-{
-        int irq = 0;
-        struct platform_device *pdev = container_of(dev,
-                                struct platform_device, dev);
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
-
-        if (!pdata) {
-                dev_err(dev, "%s: NULL platform data\n", __func__);
-                return -EINVAL;
-        }
-        /* Setting MMC1 Card detect Irq */
-        if (pdev->id == 0) {
-                irq = twl6030_mmc_card_detect_config();
-                if (irq < 0) {
-                        dev_err(dev, "%s: Error card detect config(%d)\n",
-                                __func__, irq);
-                        return irq;
-                }
-                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
-        }
-        return 0;
-}
-
-static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
-{
-        struct omap_mmc_platform_data *pdata;
-
-        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
-        if (!dev) {
-                pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
-                return;
-        }
-        pdata = dev->platform_data;
-
-        pdata->init =   omap4_twl6030_hsmmc_late_init;
-}
-
-static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
-{
-        struct omap2_hsmmc_info *c;
-
-        omap_hsmmc_init(controllers);
-        for (c = controllers; c->mmc; c++)
-                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
-
-        return 0;
-}
-
 static struct twl6040_codec_data twl6040_codec = {
         /* single-step ramp for headset and handsfree */
         .hs_left_step   = 0x0f,
@@ -323,7 +290,9 @@ static int __init omap4_panda_i2c_init(void)
                         TWL_COMMON_REGULATOR_VANA |
                         TWL_COMMON_REGULATOR_VCXIO |
                         TWL_COMMON_REGULATOR_VUSB |
-                        TWL_COMMON_REGULATOR_CLK32KG);
+                        TWL_COMMON_REGULATOR_CLK32KG |
+                        TWL_COMMON_REGULATOR_V1V8 |
+                        TWL_COMMON_REGULATOR_V2V1);
         omap4_pmic_init("twl6030", &omap4_panda_twldata,
                         &twl6040_data, OMAP44XX_IRQ_SYS_2N);
         omap_register_i2c_bus(2, 400, NULL, 0);
@@ -420,47 +389,22 @@ static struct omap_board_mux board_mux[] __initdata = {
 /* Display DVI */
 #define PANDA_DVI_TFP410_POWER_DOWN_GPIO        0
 
-static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(dssdev->reset_gpio, 1);
-        return 0;
-}
-
-static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(dssdev->reset_gpio, 0);
-}
-
 /* Using generic display panel */
-static struct panel_dvi_platform_data omap4_dvi_panel = {
-        .platform_enable        = omap4_panda_enable_dvi,
-        .platform_disable       = omap4_panda_disable_dvi,
-        .i2c_bus_num = 3,
+static struct tfp410_platform_data omap4_dvi_panel = {
+        .i2c_bus_num            = 3,
+        .power_down_gpio        = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
 };
 
-struct omap_dss_device omap4_panda_dvi_device = {
+static struct omap_dss_device omap4_panda_dvi_device = {
         .type                   = OMAP_DISPLAY_TYPE_DPI,
         .name                   = "dvi",
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &omap4_dvi_panel,
         .phy.dpi.data_lines     = 24,
         .reset_gpio             = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
         .channel                = OMAP_DSS_CHANNEL_LCD2,
 };
 
-int __init omap4_panda_dvi_init(void)
-{
-        int r;
-
-        /* Requesting TFP410 DVI GPIO and disabling it, at bootup */
-        r = gpio_request_one(omap4_panda_dvi_device.reset_gpio,
-                                GPIOF_OUT_INIT_LOW, "DVI PD");
-        if (r)
-                pr_err("Failed to get DVI powerdown GPIO\n");
-
-        return r;
-}
-
 static struct gpio panda_hdmi_gpios[] = {
         { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
         { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
@@ -509,13 +453,8 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
         .default_device = &omap4_panda_dvi_device,
 };
 
-void __init omap4_panda_display_init(void)
+static void __init omap4_panda_display_init(void)
 {
-        int r;
-
-        r = omap4_panda_dvi_init();
-        if (r)
-                pr_err("error initializing panda DVI\n");
 
         omap_display_init(&omap4_panda_dss_data);
 
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 33aa3910b09e..5527c1979a16 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -46,7 +46,7 @@
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
 #include <mach/hardware.h>
 #include <plat/nand.h>
@@ -167,32 +167,15 @@ static void __init overo_display_init(void)
         gpio_export(OVERO_GPIO_LCD_BL, 0);
 }
 
-static int overo_panel_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        dvi_enabled = 1;
-
-        return 0;
-}
-
-static void overo_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        dvi_enabled = 0;
-}
-
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = overo_panel_enable_dvi,
-        .platform_disable       = overo_panel_disable_dvi,
+static struct tfp410_platform_data dvi_panel = {
         .i2c_bus_num            = 3,
+        .power_down_gpio        = -1,
 };
 
 static struct omap_dss_device overo_dvi_device = {
         .name                   = "dvi",
         .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
         .data                   = &dvi_panel,
         .phy.dpi.data_lines     = 24,
 };
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index d87ee0612098..ff53deccecab 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -44,6 +44,7 @@
 #include <linux/leds-lp5523.h>
 
 #include <../drivers/staging/iio/light/tsl2563.h>
+#include <linux/lis3lv02d.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -63,6 +64,9 @@
 #define RX51_TSC2005_RESET_GPIO         104
 #define RX51_TSC2005_IRQ_GPIO           100
 
+#define LIS302_IRQ1_GPIO 181
+#define LIS302_IRQ2_GPIO 180  /* Not yet in use */
+
 /* list all spi devices here */
 enum {
         RX51_SPI_WL1251,
@@ -73,6 +77,77 @@ enum {
 static struct wl12xx_platform_data wl1251_pdata;
 static struct tsc2005_platform_data tsc2005_pdata;
 
+#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
+static int lis302_setup(void)
+{
+        int err;
+        int irq1 = LIS302_IRQ1_GPIO;
+        int irq2 = LIS302_IRQ2_GPIO;
+
+        /* gpio for interrupt pin 1 */
+        err = gpio_request(irq1, "lis3lv02dl_irq1");
+        if (err) {
+                printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
+                goto out;
+        }
+
+        /* gpio for interrupt pin 2 */
+        err = gpio_request(irq2, "lis3lv02dl_irq2");
+        if (err) {
+                gpio_free(irq1);
+                printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
+                goto out;
+        }
+
+        gpio_direction_input(irq1);
+        gpio_direction_input(irq2);
+
+out:
+        return err;
+}
+
+static int lis302_release(void)
+{
+        gpio_free(LIS302_IRQ1_GPIO);
+        gpio_free(LIS302_IRQ2_GPIO);
+
+        return 0;
+}
+
+static struct lis3lv02d_platform_data rx51_lis3lv02d_data = {
+        .click_flags    = LIS3_CLICK_SINGLE_X | LIS3_CLICK_SINGLE_Y |
+                          LIS3_CLICK_SINGLE_Z,
+        /* Limits are 0.5g * value */
+        .click_thresh_x = 8,
+        .click_thresh_y = 8,
+        .click_thresh_z = 10,
+        /* Click must be longer than time limit */
+        .click_time_limit = 9,
+        /* Kind of debounce filter */
+        .click_latency    = 50,
+
+        /* Limits for all axis. millig-value / 18 to get HW values */
+        .wakeup_flags = LIS3_WAKEUP_X_HI | LIS3_WAKEUP_Y_HI,
+        .wakeup_thresh = 800 / 18,
+        .wakeup_flags2 = LIS3_WAKEUP_Z_HI ,
+        .wakeup_thresh2 = 900 / 18,
+
+        .hipass_ctrl = LIS3_HIPASS1_DISABLE | LIS3_HIPASS2_DISABLE,
+
+        /* Interrupt line 2 for click detection, line 1 for thresholds */
+        .irq_cfg = LIS3_IRQ2_CLICK | LIS3_IRQ1_FF_WU_12,
+
+        .axis_x = LIS3_DEV_X,
+        .axis_y = LIS3_INV_DEV_Y,
+        .axis_z = LIS3_INV_DEV_Z,
+        .setup_resources = lis302_setup,
+        .release_resources = lis302_release,
+        .st_min_limits = {-32, 3, 3},
+        .st_max_limits = {-3, 32, 32},
+        .irq2 = OMAP_GPIO_IRQ(LIS302_IRQ2_GPIO),
+};
+#endif
+
 #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
 static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
         .cover_comp_gain = 16,
@@ -872,11 +947,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
         .resource_config = twl4030_rconfig,
 };
 
-struct twl4030_vibra_data rx51_vibra_data __initdata = {
+static struct twl4030_vibra_data rx51_vibra_data __initdata = {
         .coexist        = 0,
 };
 
-struct twl4030_audio_data rx51_audio_data __initdata = {
+static struct twl4030_audio_data rx51_audio_data __initdata = {
         .audio_mclk     = 26000000,
         .vibra          = &rx51_vibra_data,
 };
@@ -950,6 +1025,16 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
         }
 };
 
+static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
+#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
+        {
+                I2C_BOARD_INFO("lis3lv02d", 0x1d),
+                .platform_data = &rx51_lis3lv02d_data,
+                .irq = OMAP_GPIO_IRQ(LIS302_IRQ1_GPIO),
+        },
+#endif
+};
+
 static int __init rx51_i2c_init(void)
 {
         if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
@@ -971,7 +1056,8 @@ static int __init rx51_i2c_init(void)
         omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
         omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                               ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
-        omap_register_i2c_bus(3, 400, NULL, 0);
+        omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3,
+                              ARRAY_SIZE(rx51_peripherals_i2c_board_info_3));
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 27f01f051dff..2da92a6ba40a 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -59,25 +59,24 @@ static struct platform_device leds_gpio = {
 };
 
 /*
- * cpuidle C-states definition override from the default values.
- * The 'exit_latency' field is the sum of sleep and wake-up latencies.
- */
-static struct cpuidle_params rx51_cpuidle_params[] = {
-        /* C1 */
-        {110 + 162, 5 , 1},
-        /* C2 */
-        {106 + 180, 309, 1},
-        /* C3 */
-        {107 + 410, 46057, 0},
-        /* C4 */
-        {121 + 3374, 46057, 0},
-        /* C5 */
-        {855 + 1146, 46057, 1},
-        /* C6 */
-        {7580 + 4134, 484329, 0},
-        /* C7 */
-        {7505 + 15274, 484329, 1},
-};
+ * cpuidle C-states definition for rx51.
+ *
+ * The 'exit_latency' field is the sum of sleep
+ * and wake-up latencies.
+
+    ---------------------------------------------
+   | state |  exit_latency  |  target_residency  |
+    ---------------------------------------------
+   |  C1   |    110 + 162   |            5       |
+   |  C2   |    106 + 180   |          309       |
+   |  C3   |    107 + 410   |        46057       |
+   |  C4   |    121 + 3374  |        46057       |
+   |  C5   |    855 + 1146  |        46057       |
+   |  C6   |   7580 + 4134  |       484329       |
+   |  C7   |   7505 + 15274 |       484329       |
+    ---------------------------------------------
+
+*/
 
 extern void __init rx51_peripherals_init(void);
 
@@ -98,7 +97,6 @@ static void __init rx51_init(void)
         struct omap_sdrc_params *sdrc_params;
 
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        omap3_pm_init_cpuidle(rx51_cpuidle_params);
         omap_serial_init();
 
         sdrc_params = nokia_get_sdram_timings();
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index a43a765dd092..28187f134fff 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -16,6 +16,7 @@
 #include <linux/spi/spi.h>
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
+#include <mach/board-zoom.h>
 
 #define LCD_PANEL_RESET_GPIO_PROD       96
 #define LCD_PANEL_RESET_GPIO_PILOT      55
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d9f4931513f9..5c4e66542169 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk)
                 clk->ops->disable(clk);
         }
         if (clk->clkdm != NULL)
-                pwrdm_clkdm_state_switch(clk->clkdm);
+                pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index f4a626f7c79e..4e1a3b0e8cc8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1,7 +1,7 @@
 /*
  * OMAP3 clock data
  *
- * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
  * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -1640,6 +1640,7 @@ static struct clk hdq_fck = {
         .name           = "hdq_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_12m_fck,
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
         .recalc         = &followparent_recalc,
@@ -3294,8 +3295,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
         CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
@@ -3419,7 +3420,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
         CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_3505 | CK_3517),
+        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
@@ -3513,21 +3514,9 @@ int __init omap3xxx_clk_init(void)
         struct omap_clk *c;
         u32 cpu_clkflg = 0;
 
-        /*
-         * 3505 must be tested before 3517, since 3517 returns true
-         * for both AM3517 chips and AM3517 family chips, which
-         * includes 3505.  Unfortunately there's no obvious family
-         * test for 3517/3505 :-(
-         */
-        if (cpu_is_omap3505()) {
-                cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3505;
-        } else if (cpu_is_omap3517()) {
-                cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3517;
-        } else if (cpu_is_omap3505()) {
+        if (cpu_is_omap3517()) {
                 cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3505;
+                cpu_clkflg = CK_AM35XX;
         } else if (cpu_is_omap3630()) {
                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
                 cpu_clkflg = CK_36XX;
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index fa6ea65ad44b..2172f6603848 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3355,17 +3355,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ad07689e1563..8664f5a8bfb6 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
         spin_lock_irqsave(&clkdm->lock, flags);
         clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
         arch_clkdm->clkdm_allow_idle(clkdm);
-        pwrdm_clkdm_state_switch(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
         spin_unlock_irqrestore(&clkdm->lock, flags);
 }
 
@@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 
         spin_lock_irqsave(&clkdm->lock, flags);
         arch_clkdm->clkdm_clk_enable(clkdm);
-        pwrdm_wait_transition(clkdm->pwrdm.ptr);
-        pwrdm_clkdm_state_switch(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
         spin_unlock_irqrestore(&clkdm->lock, flags);
 
         pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
@@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
 
         spin_lock_irqsave(&clkdm->lock, flags);
         arch_clkdm->clkdm_clk_disable(clkdm);
-        pwrdm_clkdm_state_switch(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
         spin_unlock_irqrestore(&clkdm->lock, flags);
 
         pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 935c7f03dab9..4f04dd11d655 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -51,6 +51,9 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
         struct clkdm_dep *cd;
         u32 mask = 0;
 
+        if (!clkdm->prcm_partition)
+                return 0;
+
         for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
                 if (!cd->clkdm)
                         continue; /* only happens if data is erroneous */
@@ -103,6 +106,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
 {
         bool hwsup = false;
 
+        if (!clkdm->prcm_partition)
+                return 0;
+
         hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
                                         clkdm->cm_inst, clkdm->clkdm_offs);
 
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 0a6a04897d89..839145e1cfbe 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -89,13 +89,3 @@ struct clockdomain wkup_common_clkdm = {
         .pwrdm          = { .name = "wkup_pwrdm" },
         .dep_bit        = OMAP_EN_WKUP_SHIFT,
 };
-
-struct clockdomain prm_common_clkdm = {
-        .name           = "prm_clkdm",
-        .pwrdm          = { .name = "wkup_pwrdm" },
-};
-
-struct clockdomain cm_common_clkdm = {
-        .name           = "cm_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-};
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index b84e138d99c8..6038adb97710 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -53,9 +53,9 @@
  * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
  */
 static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
-        { .clkdm_name = "iva2_clkdm", },
-        { .clkdm_name = "mpu_clkdm", },
-        { .clkdm_name = "wkup_clkdm", },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
         { NULL },
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index bd7ed13515cc..c53425847493 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -430,6 +430,8 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
         &l4_wkup_44xx_clkdm,
         &emu_sys_44xx_clkdm,
         &l3_dma_44xx_clkdm,
+        &prm_common_clkdm,
+        &cm_common_clkdm,
         NULL
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
new file mode 100644
index 000000000000..615b1f04967d
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains_common_data.c
@@ -0,0 +1,24 @@
+/*
+ * OMAP2+-common clockdomain data
+ *
+ * Copyright (C) 2008-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+
+/* These are implicit clockdomains - they are never defined as such in TRM */
+struct clockdomain prm_common_clkdm = {
+        .name           = "prm_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+};
+
+struct clockdomain cm_common_clkdm = {
+        .name           = "cm_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+};
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index b91275908f33..8083a8cdc55f 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -79,7 +79,7 @@
 
 /* CM_CLKSEL1_PLL_IVA2 */
 #define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
-#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x3 << 19)
+#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x7 << 19)
 #define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
 #define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
 #define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
@@ -124,7 +124,7 @@
 
 /* CM_CLKSEL1_PLL_MPU */
 #define OMAP3430_MPU_CLK_SRC_SHIFT                      19
-#define OMAP3430_MPU_CLK_SRC_MASK                       (0x3 << 19)
+#define OMAP3430_MPU_CLK_SRC_MASK                       (0x7 << 19)
 #define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
 #define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
 #define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index bd8810c3753f..8c86d294b1a3 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -32,6 +32,7 @@
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
+#include "prcm-common.h"
 
 /*
  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
@@ -49,14 +50,21 @@
 #define CLKCTRL_IDLEST_INTERFACE_IDLE           0x2
 #define CLKCTRL_IDLEST_DISABLED                 0x3
 
-static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
-        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
-        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
-        [OMAP4430_CM1_PARTITION]                = OMAP4430_CM1_BASE,
-        [OMAP4430_CM2_PARTITION]                = OMAP4430_CM2_BASE,
-        [OMAP4430_SCRM_PARTITION]               = 0,
-        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
-};
+static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+
+/**
+ * omap_cm_base_init - Populates the cm partitions
+ *
+ * Populates the base addresses of the _cm_bases
+ * array used for read/write of cm module registers.
+ */
+void omap_cm_base_init(void)
+{
+        _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
+        _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
+        _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
+        _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+}
 
 /* Private functions */
 
@@ -106,7 +114,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_cm_bases[part]);
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+        return __raw_readl(_cm_bases[part] + inst + idx);
 }
 
 /* Write into a register in a CM instance */
@@ -115,7 +123,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_cm_bases[part]);
-        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+        __raw_writel(val, _cm_bases[part] + inst + idx);
 }
 
 /* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 1549c11000d3..8a6953a34fe2 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -166,6 +166,7 @@ static struct omap_globals omap4_globals = {
         .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
         .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
         .cm2    = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
+        .prcm_mpu       = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
 };
 
 void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 57da7f406e28..4cb1fe666311 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -27,6 +27,7 @@
 #ifndef __ASSEMBLER__
 
 #include <linux/delay.h>
+#include <linux/i2c/twl.h>
 #include <plat/common.h>
 #include <asm/proc-fns.h>
 
@@ -54,7 +55,7 @@ static inline void omap34xx_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI81XX
+#ifdef CONFIG_SOC_TI81XX
 extern void omapti81xx_map_common_io(void);
 #else
 static inline void omapti81xx_map_common_io(void)
@@ -62,7 +63,7 @@ static inline void omapti81xx_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAPAM33XX
+#ifdef CONFIG_SOC_AM33XX
 extern void omapam33xx_map_common_io(void);
 #else
 static inline void omapam33xx_map_common_io(void)
@@ -111,6 +112,7 @@ struct omap_globals {
         void __iomem    *prm;            /* Power and Reset Management */
         void __iomem    *cm;             /* Clock Management */
         void __iomem    *cm2;
+        void __iomem    *prcm_mpu;
 };
 
 void omap2_set_globals_242x(void);
@@ -134,8 +136,6 @@ void omap4_map_io(void);
 void ti81xx_map_io(void);
 void omap_barriers_init(void);
 
-extern void __init omap_init_consistent_dma_size(void);
-
 /**
  * omap_test_timeout - busy-loop, testing a condition
  * @cond: condition to test until it evaluates to true
@@ -254,6 +254,8 @@ static inline u32 omap4_mpuss_read_prev_context_state(void)
 struct omap_sdrc_params;
 extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1);
+struct omap2_hsmmc_info;
+extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 535866489ce3..207bc1c7759f 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -38,40 +38,44 @@
 
 #ifdef CONFIG_CPU_IDLE
 
-/*
- * The latencies/thresholds for various C states have
- * to be configured from the respective board files.
- * These are some default values (which might not provide
- * the best power savings) used on boards which do not
- * pass these details from the board file.
- */
-static struct cpuidle_params cpuidle_params_table[] = {
-        /* C1 */
-        {2 + 2, 5, 1},
-        /* C2 */
-        {10 + 10, 30, 1},
-        /* C3 */
-        {50 + 50, 300, 1},
-        /* C4 */
-        {1500 + 1800, 4000, 1},
-        /* C5 */
-        {2500 + 7500, 12000, 1},
-        /* C6 */
-        {3000 + 8500, 15000, 1},
-        /* C7 */
-        {10000 + 30000, 300000, 1},
-};
-#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
-
 /* Mach specific information to be recorded in the C-state driver_data */
 struct omap3_idle_statedata {
         u32 mpu_state;
         u32 core_state;
-        u8 valid;
 };
-struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
 
-struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
+static struct omap3_idle_statedata omap3_idle_data[] = {
+        {
+                .mpu_state = PWRDM_POWER_ON,
+                .core_state = PWRDM_POWER_ON,
+        },
+        {
+                .mpu_state = PWRDM_POWER_ON,
+                .core_state = PWRDM_POWER_ON,
+        },
+        {
+                .mpu_state = PWRDM_POWER_RET,
+                .core_state = PWRDM_POWER_ON,
+        },
+        {
+                .mpu_state = PWRDM_POWER_OFF,
+                .core_state = PWRDM_POWER_ON,
+        },
+        {
+                .mpu_state = PWRDM_POWER_RET,
+                .core_state = PWRDM_POWER_RET,
+        },
+        {
+                .mpu_state = PWRDM_POWER_OFF,
+                .core_state = PWRDM_POWER_RET,
+        },
+        {
+                .mpu_state = PWRDM_POWER_OFF,
+                .core_state = PWRDM_POWER_OFF,
+        },
+};
+
+static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
 
 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
                                 struct clockdomain *clkdm)
@@ -91,8 +95,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
                                 int index)
 {
-        struct omap3_idle_statedata *cx =
-                        cpuidle_get_statedata(&dev->states_usage[index]);
+        struct omap3_idle_statedata *cx = &omap3_idle_data[index];
         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 
         local_fiq_disable();
@@ -169,14 +172,12 @@ static inline int omap3_enter_idle(struct cpuidle_device *dev,
  * if it satisfies the enable_off_mode condition.
  */
 static int next_valid_state(struct cpuidle_device *dev,
-                        struct cpuidle_driver *drv,
-                                int index)
+                            struct cpuidle_driver *drv, int index)
 {
-        struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
-        struct cpuidle_state *curr = &drv->states[index];
-        struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
+        struct omap3_idle_statedata *cx = &omap3_idle_data[index];
         u32 mpu_deepest_state = PWRDM_POWER_RET;
         u32 core_deepest_state = PWRDM_POWER_RET;
+        int idx;
         int next_index = -1;
 
         if (enable_off_mode) {
@@ -191,45 +192,29 @@ static int next_valid_state(struct cpuidle_device *dev,
         }
 
         /* Check if current state is valid */
-        if ((cx->valid) &&
-            (cx->mpu_state >= mpu_deepest_state) &&
-            (cx->core_state >= core_deepest_state)) {
+        if ((cx->mpu_state >= mpu_deepest_state) &&
+            (cx->core_state >= core_deepest_state))
                 return index;
-        } else {
-                int idx = OMAP3_NUM_STATES - 1;
-
-                /* Reach the current state starting at highest C-state */
-                for (; idx >= 0; idx--) {
-                        if (&drv->states[idx] == curr) {
-                                next_index = idx;
-                                break;
-                        }
-                }
-
-                /* Should never hit this condition */
-                WARN_ON(next_index == -1);
 
-                /*
-                 * Drop to next valid state.
-                 * Start search from the next (lower) state.
-                 */
-                idx--;
-                for (; idx >= 0; idx--) {
-                        cx = cpuidle_get_statedata(&dev->states_usage[idx]);
-                        if ((cx->valid) &&
-                            (cx->mpu_state >= mpu_deepest_state) &&
-                            (cx->core_state >= core_deepest_state)) {
-                                next_index = idx;
-                                break;
-                        }
+        /*
+         * Drop to next valid state.
+         * Start search from the next (lower) state.
+         */
+        for (idx = index - 1; idx >= 0; idx--) {
+                cx =  &omap3_idle_data[idx];
+                if ((cx->mpu_state >= mpu_deepest_state) &&
+                    (cx->core_state >= core_deepest_state)) {
+                        next_index = idx;
+                        break;
                 }
-                /*
-                 * C1 is always valid.
-                 * So, no need to check for 'next_index == -1' outside
-                 * this loop.
-                 */
         }
 
+        /*
+         * C1 is always valid.
+         * So, no need to check for 'next_index == -1' outside
+         * this loop.
+         */
+
         return next_index;
 }
 
@@ -273,7 +258,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
          * Prevent PER off if CORE is not in retention or off as this
          * would disable PER wakeups completely.
          */
-        cx = cpuidle_get_statedata(&dev->states_usage[index]);
+        cx = &omap3_idle_data[index];
         core_next_state = cx->core_state;
         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
         if ((per_next_state == PWRDM_POWER_OFF) &&
@@ -298,57 +283,71 @@ select_state:
 
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 
-void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
-{
-        int i;
-
-        if (!cpuidle_board_params)
-                return;
-
-        for (i = 0; i < OMAP3_NUM_STATES; i++) {
-                cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
-                cpuidle_params_table[i].exit_latency =
-                        cpuidle_board_params[i].exit_latency;
-                cpuidle_params_table[i].target_residency =
-                        cpuidle_board_params[i].target_residency;
-        }
-        return;
-}
-
 struct cpuidle_driver omap3_idle_driver = {
         .name =         "omap3_idle",
         .owner =        THIS_MODULE,
+        .states = {
+                {
+                        .enter            = omap3_enter_idle,
+                        .exit_latency     = 2 + 2,
+                        .target_residency = 5,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C1",
+                        .desc             = "MPU ON + CORE ON",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 10 + 10,
+                        .target_residency = 30,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C2",
+                        .desc             = "MPU ON + CORE ON",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 50 + 50,
+                        .target_residency = 300,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C3",
+                        .desc             = "MPU RET + CORE ON",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 1500 + 1800,
+                        .target_residency = 4000,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C4",
+                        .desc             = "MPU OFF + CORE ON",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 2500 + 7500,
+                        .target_residency = 12000,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C5",
+                        .desc             = "MPU RET + CORE RET",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 3000 + 8500,
+                        .target_residency = 15000,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C6",
+                        .desc             = "MPU OFF + CORE RET",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 10000 + 30000,
+                        .target_residency = 30000,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C7",
+                        .desc             = "MPU OFF + CORE OFF",
+                },
+        },
+        .state_count = ARRAY_SIZE(omap3_idle_data),
+        .safe_state_index = 0,
 };
 
-/* Helper to fill the C-state common data*/
-static inline void _fill_cstate(struct cpuidle_driver *drv,
-                                        int idx, const char *descr)
-{
-        struct cpuidle_state *state = &drv->states[idx];
-
-        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
-        state->target_residency = cpuidle_params_table[idx].target_residency;
-        state->flags            = CPUIDLE_FLAG_TIME_VALID;
-        state->enter            = omap3_enter_idle_bm;
-        sprintf(state->name, "C%d", idx + 1);
-        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
-
-}
-
-/* Helper to register the driver_data */
-static inline struct omap3_idle_statedata *_fill_cstate_usage(
-                                        struct cpuidle_device *dev,
-                                        int idx)
-{
-        struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
-        struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
-
-        cx->valid               = cpuidle_params_table[idx].valid;
-        cpuidle_set_statedata(state_usage, cx);
-
-        return cx;
-}
-
 /**
  * omap3_idle_init - Init routine for OMAP3 idle
  *
@@ -358,77 +357,20 @@ static inline struct omap3_idle_statedata *_fill_cstate_usage(
 int __init omap3_idle_init(void)
 {
         struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &omap3_idle_driver;
-        struct omap3_idle_statedata *cx;
 
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
         core_pd = pwrdm_lookup("core_pwrdm");
         per_pd = pwrdm_lookup("per_pwrdm");
         cam_pd = pwrdm_lookup("cam_pwrdm");
 
+        if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
+                return -ENODEV;
 
-        drv->safe_state_index = -1;
-        dev = &per_cpu(omap3_idle_dev, smp_processor_id());
-
-        /* C1 . MPU WFI + Core active */
-        _fill_cstate(drv, 0, "MPU ON + CORE ON");
-        (&drv->states[0])->enter = omap3_enter_idle;
-        drv->safe_state_index = 0;
-        cx = _fill_cstate_usage(dev, 0);
-        cx->valid = 1;  /* C1 is always valid */
-        cx->mpu_state = PWRDM_POWER_ON;
-        cx->core_state = PWRDM_POWER_ON;
-
-        /* C2 . MPU WFI + Core inactive */
-        _fill_cstate(drv, 1, "MPU ON + CORE ON");
-        cx = _fill_cstate_usage(dev, 1);
-        cx->mpu_state = PWRDM_POWER_ON;
-        cx->core_state = PWRDM_POWER_ON;
-
-        /* C3 . MPU CSWR + Core inactive */
-        _fill_cstate(drv, 2, "MPU RET + CORE ON");
-        cx = _fill_cstate_usage(dev, 2);
-        cx->mpu_state = PWRDM_POWER_RET;
-        cx->core_state = PWRDM_POWER_ON;
-
-        /* C4 . MPU OFF + Core inactive */
-        _fill_cstate(drv, 3, "MPU OFF + CORE ON");
-        cx = _fill_cstate_usage(dev, 3);
-        cx->mpu_state = PWRDM_POWER_OFF;
-        cx->core_state = PWRDM_POWER_ON;
-
-        /* C5 . MPU RET + Core RET */
-        _fill_cstate(drv, 4, "MPU RET + CORE RET");
-        cx = _fill_cstate_usage(dev, 4);
-        cx->mpu_state = PWRDM_POWER_RET;
-        cx->core_state = PWRDM_POWER_RET;
-
-        /* C6 . MPU OFF + Core RET */
-        _fill_cstate(drv, 5, "MPU OFF + CORE RET");
-        cx = _fill_cstate_usage(dev, 5);
-        cx->mpu_state = PWRDM_POWER_OFF;
-        cx->core_state = PWRDM_POWER_RET;
-
-        /* C7 . MPU OFF + Core OFF */
-        _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
-        cx = _fill_cstate_usage(dev, 6);
-        /*
-         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
-         * enable OFF mode in a stable form for previous revisions.
-         * We disable C7 state as a result.
-         */
-        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
-                cx->valid = 0;
-                pr_warn("%s: core off state C7 disabled due to i583\n",
-                        __func__);
-        }
-        cx->mpu_state = PWRDM_POWER_OFF;
-        cx->core_state = PWRDM_POWER_OFF;
-
-        drv->state_count = OMAP3_NUM_STATES;
         cpuidle_register_driver(&omap3_idle_driver);
 
-        dev->state_count = OMAP3_NUM_STATES;
+        dev = &per_cpu(omap3_idle_dev, smp_processor_id());
+        dev->cpu = 0;
+
         if (cpuidle_register_device(dev)) {
                 printk(KERN_ERR "%s: CPUidle register device failed\n",
                        __func__);
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index f386cbe9c889..be1617ca84bd 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -24,26 +24,31 @@
 
 #ifdef CONFIG_CPU_IDLE
 
-/* Machine specific information to be recorded in the C-state driver_data */
+/* Machine specific information */
 struct omap4_idle_statedata {
         u32 cpu_state;
         u32 mpu_logic_state;
         u32 mpu_state;
-        u8 valid;
 };
 
-static struct cpuidle_params cpuidle_params_table[] = {
-        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
-        {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
-        /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
-        {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
-        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-        {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
+static struct omap4_idle_statedata omap4_idle_data[] = {
+        {
+                .cpu_state = PWRDM_POWER_ON,
+                .mpu_state = PWRDM_POWER_ON,
+                .mpu_logic_state = PWRDM_POWER_RET,
+        },
+        {
+                .cpu_state = PWRDM_POWER_OFF,
+                .mpu_state = PWRDM_POWER_RET,
+                .mpu_logic_state = PWRDM_POWER_RET,
+        },
+        {
+                .cpu_state = PWRDM_POWER_OFF,
+                .mpu_state = PWRDM_POWER_RET,
+                .mpu_logic_state = PWRDM_POWER_OFF,
+        },
 };
 
-#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
-
-struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
 static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
 
 /**
@@ -60,8 +65,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                         int index)
 {
-        struct omap4_idle_statedata *cx =
-                        cpuidle_get_statedata(&dev->states_usage[index]);
+        struct omap4_idle_statedata *cx = &omap4_idle_data[index];
         u32 cpu1_state;
         int cpu_id = smp_processor_id();
 
@@ -78,7 +82,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
         cpu1_state = pwrdm_read_pwrst(cpu1_pd);
         if (cpu1_state != PWRDM_POWER_OFF) {
                 index = drv->safe_state_index;
-                cx = cpuidle_get_statedata(&dev->states_usage[index]);
+                cx = &omap4_idle_data[index];
         }
 
         if (index > 0)
@@ -133,36 +137,39 @@ struct cpuidle_driver omap4_idle_driver = {
         .name                           = "omap4_idle",
         .owner                          = THIS_MODULE,
         .en_core_tk_irqen               = 1,
+        .states = {
+                {
+                        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+                        .exit_latency = 2 + 2,
+                        .target_residency = 5,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = omap4_enter_idle,
+                        .name = "C1",
+                        .desc = "MPUSS ON"
+                },
+                {
+                        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
+                        .exit_latency = 328 + 440,
+                        .target_residency = 960,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = omap4_enter_idle,
+                        .name = "C2",
+                        .desc = "MPUSS CSWR",
+                },
+                {
+                        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+                        .exit_latency = 460 + 518,
+                        .target_residency = 1100,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = omap4_enter_idle,
+                        .name = "C3",
+                        .desc = "MPUSS OSWR",
+                },
+        },
+        .state_count = ARRAY_SIZE(omap4_idle_data),
+        .safe_state_index = 0,
 };
 
-static inline void _fill_cstate(struct cpuidle_driver *drv,
-                                        int idx, const char *descr)
-{
-        struct cpuidle_state *state = &drv->states[idx];
-
-        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
-        state->target_residency = cpuidle_params_table[idx].target_residency;
-        state->flags            = CPUIDLE_FLAG_TIME_VALID;
-        state->enter            = omap4_enter_idle;
-        sprintf(state->name, "C%d", idx + 1);
-        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
-}
-
-static inline struct omap4_idle_statedata *_fill_cstate_usage(
-                                        struct cpuidle_device *dev,
-                                        int idx)
-{
-        struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
-        struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
-
-        cx->valid               = cpuidle_params_table[idx].valid;
-        cpuidle_set_statedata(state_usage, cx);
-
-        return cx;
-}
-
-
-
 /**
  * omap4_idle_init - Init routine for OMAP4 idle
  *
@@ -171,9 +178,7 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
  */
 int __init omap4_idle_init(void)
 {
-        struct omap4_idle_statedata *cx;
         struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &omap4_idle_driver;
         unsigned int cpu_id = 0;
 
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
@@ -182,42 +187,15 @@ int __init omap4_idle_init(void)
         if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
                 return -ENODEV;
 
-
-        drv->safe_state_index = -1;
         dev = &per_cpu(omap4_idle_dev, cpu_id);
         dev->cpu = cpu_id;
 
-        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
-        _fill_cstate(drv, 0, "MPUSS ON");
-        drv->safe_state_index = 0;
-        cx = _fill_cstate_usage(dev, 0);
-        cx->valid = 1;  /* C1 is always valid */
-        cx->cpu_state = PWRDM_POWER_ON;
-        cx->mpu_state = PWRDM_POWER_ON;
-        cx->mpu_logic_state = PWRDM_POWER_RET;
-
-        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
-        _fill_cstate(drv, 1, "MPUSS CSWR");
-        cx = _fill_cstate_usage(dev, 1);
-        cx->cpu_state = PWRDM_POWER_OFF;
-        cx->mpu_state = PWRDM_POWER_RET;
-        cx->mpu_logic_state = PWRDM_POWER_RET;
-
-        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-        _fill_cstate(drv, 2, "MPUSS OSWR");
-        cx = _fill_cstate_usage(dev, 2);
-        cx->cpu_state = PWRDM_POWER_OFF;
-        cx->mpu_state = PWRDM_POWER_RET;
-        cx->mpu_logic_state = PWRDM_POWER_OFF;
-
-        drv->state_count = OMAP4_NUM_STATES;
         cpuidle_register_driver(&omap4_idle_driver);
 
-        dev->state_count = OMAP4_NUM_STATES;
         if (cpuidle_register_device(dev)) {
                 pr_err("%s: CPUidle register device failed\n", __func__);
-                        return -EIO;
-                }
+                return -EIO;
+        }
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index e4336035c0ea..7b4b9327e543 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -42,7 +42,6 @@
 
 static int __init omap3_l3_init(void)
 {
-        int l;
         struct omap_hwmod *oh;
         struct platform_device *pdev;
         char oh_name[L3_MODULES_MAX_LEN];
@@ -54,7 +53,7 @@ static int __init omap3_l3_init(void)
         if (!(cpu_is_omap34xx()))
                 return -ENODEV;
 
-        l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+        snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
 
         oh = omap_hwmod_lookup(oh_name);
 
@@ -72,7 +71,7 @@ postcore_initcall(omap3_l3_init);
 
 static int __init omap4_l3_init(void)
 {
-        int l, i;
+        int i;
         struct omap_hwmod *oh[3];
         struct platform_device *pdev;
         char oh_name[L3_MODULES_MAX_LEN];
@@ -89,7 +88,7 @@ static int __init omap4_l3_init(void)
                 return -ENODEV;
 
         for (i = 0; i < L3_MODULES; i++) {
-                l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
+                snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
 
                 oh[i] = omap_hwmod_lookup(oh_name);
                 if (!(oh[i]))
@@ -355,6 +354,36 @@ static void __init omap_init_dmic(void)
 static inline void omap_init_dmic(void) {}
 #endif
 
+#if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \
+                defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE)
+
+static struct platform_device omap_hdmi_audio = {
+        .name   = "omap-hdmi-audio",
+        .id     = -1,
+};
+
+static void __init omap_init_hdmi_audio(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+
+        oh = omap_hwmod_lookup("dss_hdmi");
+        if (!oh) {
+                printk(KERN_ERR "Could not look up dss_hdmi hw_mod\n");
+                return;
+        }
+
+        pdev = omap_device_build("omap-hdmi-audio-dai",
+                -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev),
+             "Can't build omap_device for omap-hdmi-audio-dai.\n");
+
+        platform_device_register(&omap_hdmi_audio);
+}
+#else
+static inline void omap_init_hdmi_audio(void) {}
+#endif
+
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
 #include <plat/mcspi.h>
@@ -616,7 +645,11 @@ static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
 
 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
 {
-        char *name = "mmci-omap";
+        struct platform_device *pdev;
+        struct omap_hwmod *oh;
+        int id = 0;
+        char *oh_name = "msdi1";
+        char *dev_name = "mmci-omap";
 
         if (!mmc_data[0]) {
                 pr_err("%s fails: Incomplete platform data\n", __func__);
@@ -624,8 +657,17 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
         }
 
         omap242x_mmc_mux(mmc_data[0]);
-        omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
-                                        INT_24XX_MMC_IRQ, mmc_data[0]);
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return;
+        }
+        pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
+                                 sizeof(struct omap_mmc_platform_data), NULL, 0, 0);
+        if (IS_ERR(pdev))
+                WARN(1, "Can'd build omap_device for %s:%s.\n",
+                                        dev_name, oh->name);
 }
 
 #endif
@@ -701,11 +743,15 @@ static int __init omap2_init_devices(void)
          * in alphabetical order so they're easier to sort through.
          */
         omap_init_audio();
-        omap_init_mcpdm();
-        omap_init_dmic();
         omap_init_camera();
+        omap_init_hdmi_audio();
         omap_init_mbox();
-        omap_init_mcspi();
+        /* If dtb is there, the devices will be created dynamically */
+        if (!of_have_populated_dt()) {
+                omap_init_dmic();
+                omap_init_mcpdm();
+                omap_init_mcspi();
+        }
         omap_init_pmu();
         omap_hdq_init();
         omap_init_sti();
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index b19d8496c16e..ff75abe60af2 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -227,10 +227,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 
         dma_stride              = OMAP2_DMA_STRIDE;
         dma_common_ch_start     = CSDP;
-        if (cpu_is_omap3630() || cpu_is_omap44xx())
-                dma_common_ch_end = CCDN;
-        else
-                dma_common_ch_end = CCFN;
 
         p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
         if (!p) {
@@ -277,6 +273,13 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
                 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
                 return -ENOMEM;
         }
+
+        /* Check the capabilities register for descriptor loading feature */
+        if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
+                dma_common_ch_end = CCDN;
+        else
+                dma_common_ch_end = CCFN;
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fc56745676fa..f0f10beeffe8 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -142,7 +142,8 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
 
         ai = omap3_dpll_autoidle_read(clk);
 
-        omap3_dpll_deny_idle(clk);
+        if (ai)
+                omap3_dpll_deny_idle(clk);
 
         _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 
@@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
 
         if (ai)
                 omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
 
         return r;
 }
@@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
 
         if (ai)
                 omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
 
         return 0;
 }
@@ -519,6 +516,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
 
         dd = clk->dpll_data;
 
+        if (!dd->autoidle_reg)
+                return -EINVAL;
+
         v = __raw_readl(dd->autoidle_reg);
         v &= dd->autoidle_mask;
         v >>= __ffs(dd->autoidle_mask);
@@ -545,6 +545,12 @@ void omap3_dpll_allow_idle(struct clk *clk)
 
         dd = clk->dpll_data;
 
+        if (!dd->autoidle_reg) {
+                pr_debug("clock: DPLL %s: autoidle not supported\n",
+                        clk->name);
+                return;
+        }
+
         /*
          * REVISIT: CORE DPLL can optionally enter low-power bypass
          * by writing 0x5 instead of 0x1.  Add some mechanism to
@@ -554,6 +560,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
         v &= ~dd->autoidle_mask;
         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
         __raw_writel(v, dd->autoidle_reg);
+
 }
 
 /**
@@ -572,6 +579,12 @@ void omap3_dpll_deny_idle(struct clk *clk)
 
         dd = clk->dpll_data;
 
+        if (!dd->autoidle_reg) {
+                pr_debug("clock: DPLL %s: autoidle not supported\n",
+                        clk->name);
+                return;
+        }
+
         v = __raw_readl(dd->autoidle_reg);
         v &= ~dd->autoidle_mask;
         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 74f18f2952df..845309f146fe 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -28,8 +28,6 @@
 
 #include <plat/dsp.h>
 
-extern phys_addr_t omap_dsp_get_mempool_base(void);
-
 static struct platform_device *omap_dsp_pdev;
 
 static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
@@ -47,6 +45,31 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
         .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
 };
 
+static phys_addr_t omap_dsp_phys_mempool_base;
+
+void __init omap_dsp_reserve_sdram_memblock(void)
+{
+        phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
+        phys_addr_t paddr;
+
+        if (!size)
+                return;
+
+        paddr = arm_memblock_steal(size, SZ_1M);
+        if (!paddr) {
+                pr_err("%s: failed to reserve %llx bytes\n",
+                                __func__, (unsigned long long)size);
+                return;
+        }
+
+        omap_dsp_phys_mempool_base = paddr;
+}
+
+static phys_addr_t omap_dsp_get_mempool_base(void)
+{
+        return omap_dsp_phys_mempool_base;
+}
+
 static int __init omap_dsp_init(void)
 {
         struct platform_device *pdev;
@@ -57,8 +80,9 @@ static int __init omap_dsp_init(void)
 
         if (pdata->phys_mempool_base) {
                 pdata->phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
-                pr_info("%s: %x bytes @ %x\n", __func__,
-                        pdata->phys_mempool_size, pdata->phys_mempool_base);
+                pr_info("%s: %llx bytes @ %llx\n", __func__,
+                        (unsigned long long)pdata->phys_mempool_size,
+                        (unsigned long long)pdata->phys_mempool_base);
         }
 
         pdev = platform_device_alloc("omap-dsp", -1);
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 2f994e5194e8..9ad7d489b0de 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -20,6 +20,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
+#include <linux/of.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -55,10 +56,9 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
         dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
         pdata->bank_width = dev_attr->bank_width;
         pdata->dbck_flag = dev_attr->dbck_flag;
-        pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
         pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
-        if (!pdata) {
+        if (!pdata->regs) {
                 pr_err("gpio%d: Memory allocation failed\n", id);
                 return -ENOMEM;
         }
@@ -102,6 +102,8 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 pdata->regs->dataout = OMAP4_GPIO_DATAOUT;
                 pdata->regs->set_dataout = OMAP4_GPIO_SETDATAOUT;
                 pdata->regs->clr_dataout = OMAP4_GPIO_CLEARDATAOUT;
+                pdata->regs->irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0;
+                pdata->regs->irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1;
                 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
                 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
                 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
@@ -146,7 +148,10 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
  */
 static int __init omap2_gpio_init(void)
 {
-        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
-                                                NULL);
+        /* If dtb is there, the devices will be created dynamically */
+        if (of_have_populated_dt())
+                return -ENODEV;
+
+        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL);
 }
 postcore_initcall(omap2_gpio_init);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 385b3e02c4a6..a0fa9bb2bda5 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -176,7 +176,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         const int t_wpl  = 40;
         const int t_wph  = 30;
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-        int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+        int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
         int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
         int err, ticks_cez;
         int cs = cfg->cs, freq = *freq_ptr;
@@ -240,7 +240,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 break;
         }
 
-        tick_ns = gpmc_ticks_to_ns(1);
         div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
         gpmc_clk_ns = gpmc_ticks_to_ns(div);
         if (gpmc_clk_ns < 15) /* >66Mhz */
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d510858e28..46b09dae770e 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -50,6 +50,19 @@
 #define GPMC_ECC_SIZE_CONFIG    0x1fc
 #define GPMC_ECC1_RESULT        0x200
 
+/* GPMC ECC control settings */
+#define GPMC_ECC_CTRL_ECCCLEAR          0x100
+#define GPMC_ECC_CTRL_ECCDISABLE        0x000
+#define GPMC_ECC_CTRL_ECCREG1           0x001
+#define GPMC_ECC_CTRL_ECCREG2           0x002
+#define GPMC_ECC_CTRL_ECCREG3           0x003
+#define GPMC_ECC_CTRL_ECCREG4           0x004
+#define GPMC_ECC_CTRL_ECCREG5           0x005
+#define GPMC_ECC_CTRL_ECCREG6           0x006
+#define GPMC_ECC_CTRL_ECCREG7           0x007
+#define GPMC_ECC_CTRL_ECCREG8           0x008
+#define GPMC_ECC_CTRL_ECCREG9           0x009
+
 #define GPMC_CS0_OFFSET         0x60
 #define GPMC_CS_SIZE            0x30
 
@@ -755,8 +768,7 @@ static int __init gpmc_init(void)
                 irq++;
         }
 
-        ret = request_irq(gpmc_irq,
-                        gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
+        ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
         if (ret)
                 pr_err("gpmc: irq-%d could not claim: err %d\n",
                                                 gpmc_irq, ret);
@@ -861,8 +873,9 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
         gpmc_ecc_used = cs;
 
         /* clear ecc and enable bits */
-        val = ((0x00000001<<8) | 0x00000001);
-        gpmc_write_reg(GPMC_ECC_CONTROL, val);
+        gpmc_write_reg(GPMC_ECC_CONTROL,
+                        GPMC_ECC_CTRL_ECCCLEAR |
+                        GPMC_ECC_CTRL_ECCREG1);
 
         /* program ecc and result sizes */
         val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
@@ -870,13 +883,15 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
 
         switch (mode) {
         case GPMC_ECC_READ:
-                gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
+        case GPMC_ECC_WRITE:
+                gpmc_write_reg(GPMC_ECC_CONTROL,
+                                GPMC_ECC_CTRL_ECCCLEAR |
+                                GPMC_ECC_CTRL_ECCREG1);
                 break;
         case GPMC_ECC_READSYN:
-                 gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
-                break;
-        case GPMC_ECC_WRITE:
-                gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
+                gpmc_write_reg(GPMC_ECC_CONTROL,
+                                GPMC_ECC_CTRL_ECCCLEAR |
+                                GPMC_ECC_CTRL_ECCDISABLE);
                 break;
         default:
                 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
new file mode 100644
index 000000000000..297ebe03f09c
--- /dev/null
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -0,0 +1,72 @@
+/*
+ * IP block integration code for the HDQ1W/1-wire IP block
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
+ *     Avinash.H.M <avinashhm@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/hdq1w.h>
+
+#include "common.h"
+
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
+
+/**
+ * omap_hdq1w_reset - reset the OMAP HDQ1W module
+ * @oh: struct omap_hwmod *
+ *
+ * OCP soft reset the HDQ1W IP block.  Section 20.6.1.4 "HDQ1W/1-Wire
+ * Software Reset" of the OMAP34xx Technical Reference Manual Revision
+ * ZR (SWPU223R) does not include the rather important fact that, for
+ * the reset to succeed, the HDQ1W module's internal clock gate must be
+ * programmed to allow the clock to propagate to the rest of the
+ * module.  In this sense, it's rather similar to the I2C custom reset
+ * function.  Returns 0.
+ */
+int omap_hdq1w_reset(struct omap_hwmod *oh)
+{
+        u32 v;
+        int c = 0;
+
+        /* Write to the SOFTRESET bit */
+        omap_hwmod_softreset(oh);
+
+        /* Enable the module's internal clocks */
+        v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
+        v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
+        omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
+
+        /* Poll on RESETDONE bit */
+        omap_test_timeout((omap_hwmod_read(oh,
+                                           oh->class->sysc->syss_offs)
+                           & SYSS_RESETDONE_MASK),
+                          MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+        else
+                pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                         oh->name, c);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index b0268eaffe13..be697d4e0843 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -355,7 +355,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
          *
          * temporary HACK: ocr_mask instead of fixed supply
          */
-        if (cpu_is_omap3505() || cpu_is_omap3517())
+        if (soc_is_am35xx())
                 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
                                          MMC_VDD_26_27 |
                                          MMC_VDD_27_28 |
@@ -365,7 +365,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
         else
                 mmc->slots[0].ocr_mask = c->ocr_mask;
 
-        if (!cpu_is_omap3517() && !cpu_is_omap3505())
+        if (!soc_is_am35xx())
                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 
         if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
@@ -388,7 +388,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                         }
                 }
 
-                if (cpu_is_omap3517() || cpu_is_omap3505())
+                if (soc_is_am35xx())
                         mmc->slots[0].set_power = nop_mmc_set_power;
 
                 /* OMAP3630 HSMMC1 supports only 4-bit */
@@ -400,7 +400,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                 }
                 break;
         case 2:
-                if (cpu_is_omap3517() || cpu_is_omap3505())
+                if (soc_is_am35xx())
                         mmc->slots[0].set_power = am35x_hsmmc2_set_power;
 
                 if (c->ext_clock)
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 454dfce125ca..8763c8520dc2 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -28,7 +28,7 @@ static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
         .base_id = 0,
 };
 
-int __init hwspinlocks_init(void)
+static int __init hwspinlocks_init(void)
 {
         int retval = 0;
         struct omap_hwmod *oh;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0e79b7bc6aa4..0389b3264abe 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -185,8 +185,7 @@ static void __init omap3_cpuinfo(void)
          */
         if (cpu_is_omap3630()) {
                 cpu_name = "OMAP3630";
-        } else if (cpu_is_omap3517()) {
-                /* AM35xx devices */
+        } else if (soc_is_am35xx()) {
                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
         } else if (cpu_is_ti816x()) {
                 cpu_name = "TI816X";
@@ -352,13 +351,13 @@ void __init omap3xxx_check_revision(void)
                  */
                 switch (rev) {
                 case 0:
-                        omap_revision = OMAP3517_REV_ES1_0;
+                        omap_revision = AM35XX_REV_ES1_0;
                         cpu_rev = "1.0";
                         break;
                 case 1:
                 /* FALLTHROUGH */
                 default:
-                        omap_revision = OMAP3517_REV_ES1_1;
+                        omap_revision = AM35XX_REV_ES1_1;
                         cpu_rev = "1.1";
                 }
                 break;
@@ -478,9 +477,12 @@ void __init omap4xxx_check_revision(void)
         case 0xb94e:
                 switch (rev) {
                 case 0:
-                default:
                         omap_revision = OMAP4460_REV_ES1_0;
                         break;
+                case 2:
+                default:
+                        omap_revision = OMAP4460_REV_ES1_1;
+                        break;
                 }
                 break;
         case 0xb975:
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
index 1e2d3322f33e..c88420de1151 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -941,10 +941,10 @@
 #define OMAP4_DSI2_LANEENABLE_MASK                              (0x7 << 29)
 #define OMAP4_DSI1_LANEENABLE_SHIFT                             24
 #define OMAP4_DSI1_LANEENABLE_MASK                              (0x1f << 24)
-#define OMAP4_DSI2_PIPD_SHIFT                                   19
-#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 19)
-#define OMAP4_DSI1_PIPD_SHIFT                                   14
-#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 14)
+#define OMAP4_DSI1_PIPD_SHIFT                                   19
+#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT                                   14
+#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 14)
 
 /* CONTROL_MCBSPLP */
 #define OMAP4_ALBCTRLRX_FSX_SHIFT                               31
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
index d79321b0f2a2..548de90b58c2 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -16,18 +16,10 @@
 #define OMAP_WKG_ENB_B_0                        0x14
 #define OMAP_WKG_ENB_C_0                        0x18
 #define OMAP_WKG_ENB_D_0                        0x1c
-#define OMAP_WKG_ENB_SECURE_A_0                 0x20
-#define OMAP_WKG_ENB_SECURE_B_0                 0x24
-#define OMAP_WKG_ENB_SECURE_C_0                 0x28
-#define OMAP_WKG_ENB_SECURE_D_0                 0x2c
 #define OMAP_WKG_ENB_A_1                        0x410
 #define OMAP_WKG_ENB_B_1                        0x414
 #define OMAP_WKG_ENB_C_1                        0x418
 #define OMAP_WKG_ENB_D_1                        0x41c
-#define OMAP_WKG_ENB_SECURE_A_1                 0x420
-#define OMAP_WKG_ENB_SECURE_B_1                 0x424
-#define OMAP_WKG_ENB_SECURE_C_1                 0x428
-#define OMAP_WKG_ENB_SECURE_D_1                 0x42c
 #define OMAP_AUX_CORE_BOOT_0                    0x800
 #define OMAP_AUX_CORE_BOOT_1                    0x804
 #define OMAP_PTMSYNCREQ_MASK                    0xc00
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 065bd768987c..e1f9c6fc0414 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -31,6 +31,7 @@
 #include <plat/omap-pm.h>
 #include <plat/omap_hwmod.h>
 #include <plat/multi.h>
+#include <plat/dma.h>
 
 #include "iomap.h"
 #include "voltage.h"
@@ -172,7 +173,7 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
 };
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI81XX
+#ifdef CONFIG_SOC_TI81XX
 static struct map_desc omapti81xx_io_desc[] __initdata = {
         {
                 .virtual        = L4_34XX_VIRT,
@@ -183,7 +184,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = {
 };
 #endif
 
-#ifdef CONFIG_SOC_OMAPAM33XX
+#ifdef CONFIG_SOC_AM33XX
 static struct map_desc omapam33xx_io_desc[] __initdata = {
         {
                 .virtual        = L4_34XX_VIRT,
@@ -215,41 +216,11 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
                 .type           = MT_DEVICE,
         },
         {
-                .virtual        = OMAP44XX_GPMC_VIRT,
-                .pfn            = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
-                .length         = OMAP44XX_GPMC_SIZE,
-                .type           = MT_DEVICE,
-        },
-        {
-                .virtual        = OMAP44XX_EMIF1_VIRT,
-                .pfn            = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
-                .length         = OMAP44XX_EMIF1_SIZE,
-                .type           = MT_DEVICE,
-        },
-        {
-                .virtual        = OMAP44XX_EMIF2_VIRT,
-                .pfn            = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
-                .length         = OMAP44XX_EMIF2_SIZE,
-                .type           = MT_DEVICE,
-        },
-        {
-                .virtual        = OMAP44XX_DMM_VIRT,
-                .pfn            = __phys_to_pfn(OMAP44XX_DMM_PHYS),
-                .length         = OMAP44XX_DMM_SIZE,
-                .type           = MT_DEVICE,
-        },
-        {
                 .virtual        = L4_PER_44XX_VIRT,
                 .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
                 .length         = L4_PER_44XX_SIZE,
                 .type           = MT_DEVICE,
         },
-        {
-                .virtual        = L4_EMU_44XX_VIRT,
-                .pfn            = __phys_to_pfn(L4_EMU_44XX_PHYS),
-                .length         = L4_EMU_44XX_SIZE,
-                .type           = MT_DEVICE,
-        },
 #ifdef CONFIG_OMAP4_ERRATA_I688
         {
                 .virtual        = OMAP4_SRAM_VA,
@@ -285,14 +256,14 @@ void __init omap34xx_map_common_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAPTI81XX
+#ifdef CONFIG_SOC_TI81XX
 void __init omapti81xx_map_common_io(void)
 {
         iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAPAM33XX
+#ifdef CONFIG_SOC_AM33XX
 void __init omapam33xx_map_common_io(void)
 {
         iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
@@ -363,24 +334,6 @@ static void __init omap_hwmod_init_postsetup(void)
 #endif
         omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
 
-        /*
-         * Set the default postsetup state for unusual modules (like
-         * MPU WDT).
-         *
-         * The postsetup_state is not actually used until
-         * omap_hwmod_late_init(), so boards that desire full watchdog
-         * coverage of kernel initialization can reprogram the
-         * postsetup_state between the calls to
-         * omap2_init_common_infra() and omap_sdrc_init().
-         *
-         * XXX ideally we could detect whether the MPU WDT was currently
-         * enabled here and make this conditional
-         */
-        postsetup_state = _HWMOD_STATE_DISABLED;
-        omap_hwmod_for_each_by_class("wd_timer",
-                                     _set_hwmod_postsetup_state,
-                                     &postsetup_state);
-
         omap_pm_if_early_init();
 }
 
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index 0812b154f5b5..80b88921faba 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -37,9 +37,6 @@
 #define OMAP4_L3_PER_IO_OFFSET  0xb1100000
 #define OMAP4_L3_PER_IO_ADDRESS(pa)     IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
 
-#define OMAP4_GPMC_IO_OFFSET            0xa9000000
-#define OMAP4_GPMC_IO_ADDRESS(pa)       IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
-
 #define OMAP2_EMU_IO_OFFSET             0xaa800000      /* Emulation */
 #define OMAP2_EMU_IO_ADDRESS(pa)        IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
 
@@ -170,28 +167,3 @@
 #define L4_ABE_44XX_VIRT        (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_ABE_44XX_SIZE        SZ_1M
 
-#define L4_EMU_44XX_PHYS        L4_EMU_44XX_BASE
-                                                /* 0x54000000 --> 0xfe800000 */
-#define L4_EMU_44XX_VIRT        (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
-#define L4_EMU_44XX_SIZE        SZ_8M
-
-#define OMAP44XX_GPMC_PHYS      OMAP44XX_GPMC_BASE
-                                                /* 0x50000000 --> 0xf9000000 */
-#define OMAP44XX_GPMC_VIRT      (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
-#define OMAP44XX_GPMC_SIZE      SZ_1M
-
-
-#define OMAP44XX_EMIF1_PHYS     OMAP44XX_EMIF1_BASE
-                                                /* 0x4c000000 --> 0xfd100000 */
-#define OMAP44XX_EMIF1_VIRT     (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
-#define OMAP44XX_EMIF1_SIZE     SZ_1M
-
-#define OMAP44XX_EMIF2_PHYS     OMAP44XX_EMIF2_BASE
-                                                /* 0x4d000000 --> 0xfd200000 */
-#define OMAP44XX_EMIF2_SIZE     SZ_1M
-#define OMAP44XX_EMIF2_VIRT     (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
-
-#define OMAP44XX_DMM_PHYS       OMAP44XX_DMM_BASE
-                                                /* 0x4e000000 --> 0xfd300000 */
-#define OMAP44XX_DMM_SIZE       SZ_1M
-#define OMAP44XX_DMM_VIRT       (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f0d2571c9a..fdc4303be563 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -25,6 +25,7 @@
 #include <mach/hardware.h>
 
 #include "iomap.h"
+#include "common.h"
 
 /* selected INTC register offsets */
 
@@ -149,7 +150,6 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
         ct->chip.irq_mask = irq_gc_mask_disable_reg;
         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 
-        ct->regs.ack = INTC_CONTROL;
         ct->regs.enable = INTC_MIR_CLEAR0;
         ct->regs.disable = INTC_MIR_SET0;
         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
@@ -231,7 +231,7 @@ static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs
                         goto out;
 
                 irqnr = readl_relaxed(base_addr + 0xd8);
-#ifdef CONFIG_SOC_OMAPTI816X
+#ifdef CONFIG_SOC_TI81XX
                 if (irqnr)
                         goto out;
                 irqnr = readl_relaxed(base_addr + 0xf8);
@@ -334,7 +334,7 @@ void omap_intc_restore_context(void)
 void omap3_intc_suspend(void)
 {
         /* A pending interrupt would prevent OMAP from entering suspend */
-        omap_ack_irq(0);
+        omap_ack_irq(NULL);
 }
 
 void omap3_intc_prepare_idle(void)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 415a6f1cf419..19b8b6774862 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -26,9 +26,9 @@
 #define MAILBOX_IRQSTATUS(u)            (0x100 + 8 * (u))
 #define MAILBOX_IRQENABLE(u)            (0x104 + 8 * (u))
 
-#define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 0x10 * (u))
 
 #define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
new file mode 100644
index 000000000000..ef2a6924731a
--- /dev/null
+++ b/arch/arm/mach-omap2/msdi.c
@@ -0,0 +1,88 @@
+/*
+ * MSDI IP block reset
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * XXX What about pad muxing?
+ */
+
+#include <linux/kernel.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/mmc.h>
+
+#include "common.h"
+
+/*
+ * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
+ *     from the IP block's base address
+ */
+#define MSDI_CON_OFFSET                         0x0c
+
+/* Register bitfields in the CON register */
+#define MSDI_CON_POW_MASK                       BIT(11)
+#define MSDI_CON_CLKD_MASK                      (0x3f << 0)
+#define MSDI_CON_CLKD_SHIFT                     0
+
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
+
+/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
+#define MSDI_TARGET_RESET_CLKD          0x3ff
+
+/**
+ * omap_msdi_reset - reset the MSDI IP block
+ * @oh: struct omap_hwmod *
+ *
+ * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
+ * fields set inside its CON register for a reset to complete
+ * successfully.  This is not documented in the TRM.  For CLKD, we use
+ * the value that results in the lowest possible clock rate, to attempt
+ * to avoid disturbing any cards.
+ */
+int omap_msdi_reset(struct omap_hwmod *oh)
+{
+        u16 v = 0;
+        int c = 0;
+
+        /* Write to the SOFTRESET bit */
+        omap_hwmod_softreset(oh);
+
+        /* Enable the MSDI core and internal clock */
+        v |= MSDI_CON_POW_MASK;
+        v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
+        omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
+
+        /* Poll on RESETDONE bit */
+        omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
+                           & SYSS_RESETDONE_MASK),
+                          MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+        else
+                pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                         oh->name, c);
+
+        /* Disable the MSDI internal clock */
+        v &= ~MSDI_CON_CLKD_MASK;
+        omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 65c33911341f..3268ee24eada 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -247,7 +247,7 @@ int __init omap_mux_init_signal(const char *muxname, int val)
         int mux_mode;
 
         mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
-        if (mux_mode < 0)
+        if (mux_mode < 0 || !mux)
                 return mux_mode;
 
         old_mode = omap_mux_read(partition, mux->reg_offset);
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index d8f8ef40290f..d9ae4a53d818 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -18,6 +18,7 @@
 #include <asm/cacheflush.h>
 #include <asm/memblock.h>
 
+#include <plat/omap-secure.h>
 #include <mach/omap-secure.h>
 
 static phys_addr_t omap_secure_memblock_base;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 42cd7fb52414..d811c7790350 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -259,7 +259,7 @@ static void irq_save_context(void)
 /*
  * Clear WakeupGen SAR backup status.
  */
-void irq_sar_clear(void)
+static void irq_sar_clear(void)
 {
         u32 val;
         val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 70de277f5c15..a8161e5f3204 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -25,11 +25,13 @@
 #include <plat/irqs.h>
 #include <plat/sram.h>
 #include <plat/omap-secure.h>
+#include <plat/mmc.h>
 
 #include <mach/hardware.h>
 #include <mach/omap-wakeupgen.h>
 
 #include "common.h"
+#include "hsmmc.h"
 #include "omap4-sar-layout.h"
 #include <linux/export.h>
 
@@ -207,3 +209,59 @@ static int __init omap4_sar_ram_init(void)
         return 0;
 }
 early_initcall(omap4_sar_ram_init);
+
+#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+{
+        int irq = 0;
+        struct platform_device *pdev = container_of(dev,
+                                struct platform_device, dev);
+        struct omap_mmc_platform_data *pdata = dev->platform_data;
+
+        /* Setting MMC1 Card detect Irq */
+        if (pdev->id == 0) {
+                irq = twl6030_mmc_card_detect_config();
+                if (irq < 0) {
+                        dev_err(dev, "%s: Error card detect config(%d)\n",
+                                __func__, irq);
+                        return irq;
+                }
+                pdata->slots[0].card_detect_irq = irq;
+                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+        }
+        return 0;
+}
+
+static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
+{
+        struct omap_mmc_platform_data *pdata;
+
+        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+        if (!dev) {
+                pr_err("Failed %s\n", __func__);
+                return;
+        }
+        pdata = dev->platform_data;
+        pdata->init =   omap4_twl6030_hsmmc_late_init;
+}
+
+int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+        struct omap2_hsmmc_info *c;
+
+        omap_hsmmc_init(controllers);
+        for (c = controllers; c->mmc; c++) {
+                /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
+                if (!c->pdev)
+                        continue;
+                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
+        }
+
+        return 0;
+}
+#else
+int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7144ae651d3d..bf86f7e8f91f 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,7 +2,7 @@
  * omap_hwmod implementation for OMAP2/3/4
  *
  * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011-2012 Texas Instruments, Inc.
  *
  * Paul Walmsley, Benoît Cousson, Kevin Hilman
  *
@@ -137,6 +137,7 @@
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 #include <linux/slab.h>
+#include <linux/bootmem.h>
 
 #include "common.h"
 #include <plat/cpu.h>
@@ -159,16 +160,58 @@
 /* Name of the OMAP hwmod for the MPU */
 #define MPU_INITIATOR_NAME              "mpu"
 
+/*
+ * Number of struct omap_hwmod_link records per struct
+ * omap_hwmod_ocp_if record (master->slave and slave->master)
+ */
+#define LINKS_PER_OCP_IF                2
+
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
 
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
+/*
+ * linkspace: ptr to a buffer that struct omap_hwmod_link records are
+ * allocated from - used to reduce the number of small memory
+ * allocations, which has a significant impact on performance
+ */
+static struct omap_hwmod_link *linkspace;
+
+/*
+ * free_ls, max_ls: array indexes into linkspace; representing the
+ * next free struct omap_hwmod_link index, and the maximum number of
+ * struct omap_hwmod_link records allocated (respectively)
+ */
+static unsigned short free_ls, max_ls, ls_supp;
 
 /* Private functions */
 
 /**
+ * _fetch_next_ocp_if - return the next OCP interface in a list
+ * @p: ptr to a ptr to the list_head inside the ocp_if to return
+ * @i: pointer to the index of the element pointed to by @p in the list
+ *
+ * Return a pointer to the struct omap_hwmod_ocp_if record
+ * containing the struct list_head pointed to by @p, and increment
+ * @p such that a future call to this routine will return the next
+ * record.
+ */
+static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
+                                                    int *i)
+{
+        struct omap_hwmod_ocp_if *oi;
+
+        oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
+        *p = (*p)->next;
+
+        *i = *i + 1;
+
+        return oi;
+}
+
+/**
  * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
  * @oh: struct omap_hwmod *
  *
@@ -582,16 +625,16 @@ static int _init_main_clk(struct omap_hwmod *oh)
  */
 static int _init_interface_clks(struct omap_hwmod *oh)
 {
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
         struct clk *c;
-        int i;
+        int i = 0;
         int ret = 0;
 
-        if (oh->slaves_cnt == 0)
-                return 0;
-
-        for (i = 0; i < oh->slaves_cnt; i++) {
-                struct omap_hwmod_ocp_if *os = oh->slaves[i];
+        p = oh->slave_ports.next;
 
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
                 if (!os->clk)
                         continue;
 
@@ -643,21 +686,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
  */
 static int _enable_clocks(struct omap_hwmod *oh)
 {
-        int i;
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int i = 0;
 
         pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
 
         if (oh->_clk)
                 clk_enable(oh->_clk);
 
-        if (oh->slaves_cnt > 0) {
-                for (i = 0; i < oh->slaves_cnt; i++) {
-                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
-                        struct clk *c = os->_clk;
+        p = oh->slave_ports.next;
 
-                        if (c && (os->flags & OCPIF_SWSUP_IDLE))
-                                clk_enable(c);
-                }
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+
+                if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+                        clk_enable(os->_clk);
         }
 
         /* The opt clocks are controlled by the device driver. */
@@ -673,21 +717,22 @@ static int _enable_clocks(struct omap_hwmod *oh)
  */
 static int _disable_clocks(struct omap_hwmod *oh)
 {
-        int i;
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int i = 0;
 
         pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
 
         if (oh->_clk)
                 clk_disable(oh->_clk);
 
-        if (oh->slaves_cnt > 0) {
-                for (i = 0; i < oh->slaves_cnt; i++) {
-                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
-                        struct clk *c = os->_clk;
+        p = oh->slave_ports.next;
 
-                        if (c && (os->flags & OCPIF_SWSUP_IDLE))
-                                clk_disable(c);
-                }
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+
+                if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+                        clk_disable(os->_clk);
         }
 
         /* The opt clocks are controlled by the device driver. */
@@ -781,39 +826,6 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 }
 
 /**
- * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
- * @oh: struct omap_hwmod *
- *
- * Disable the PRCM module mode related to the hwmod @oh.
- * Return EINVAL if the modulemode is not supported and 0 in case of success.
- */
-static int _omap4_disable_module(struct omap_hwmod *oh)
-{
-        int v;
-
-        /* The module mode does not exist prior OMAP4 */
-        if (!cpu_is_omap44xx())
-                return -EINVAL;
-
-        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
-                return -EINVAL;
-
-        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
-
-        omap4_cminst_module_disable(oh->clkdm->prcm_partition,
-                                    oh->clkdm->cm_inst,
-                                    oh->clkdm->clkdm_offs,
-                                    oh->prcm.omap4.clkctrl_offs);
-
-        v = _omap4_wait_target_disable(oh);
-        if (v)
-                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
-                        oh->name);
-
-        return 0;
-}
-
-/**
  * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
  * @oh: struct omap_hwmod *oh
  *
@@ -883,59 +895,220 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
 }
 
 /**
- * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
- * @oh: struct omap_hwmod *
+ * _get_mpu_irq_by_name - fetch MPU interrupt line number by name
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the MPU interrupt number to fetch (optional)
+ * @irq: pointer to an unsigned int to store the MPU IRQ number to
  *
- * Returns the array index of the OCP slave port that the MPU
- * addresses the device on, or -EINVAL upon error or not found.
+ * Retrieve a MPU hardware IRQ line number named by @name associated
+ * with the IP block pointed to by @oh.  The IRQ number will be filled
+ * into the address pointed to by @dma.  When @name is non-null, the
+ * IRQ line number associated with the named entry will be returned.
+ * If @name is null, the first matching entry will be returned.  Data
+ * order is not meaningful in hwmod data, so callers are strongly
+ * encouraged to use a non-null @name whenever possible to avoid
+ * unpredictable effects if hwmod data is later added that causes data
+ * ordering to change.  Returns 0 upon success or a negative error
+ * code upon error.
  */
-static int __init _find_mpu_port_index(struct omap_hwmod *oh)
+static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name,
+                                unsigned int *irq)
 {
         int i;
-        int found = 0;
+        bool found = false;
 
-        if (!oh || oh->slaves_cnt == 0)
-                return -EINVAL;
+        if (!oh->mpu_irqs)
+                return -ENOENT;
 
-        for (i = 0; i < oh->slaves_cnt; i++) {
-                struct omap_hwmod_ocp_if *os = oh->slaves[i];
+        i = 0;
+        while (oh->mpu_irqs[i].irq != -1) {
+                if (name == oh->mpu_irqs[i].name ||
+                    !strcmp(name, oh->mpu_irqs[i].name)) {
+                        found = true;
+                        break;
+                }
+                i++;
+        }
 
-                if (os->user & OCP_USER_MPU) {
-                        found = 1;
+        if (!found)
+                return -ENOENT;
+
+        *irq = oh->mpu_irqs[i].irq;
+
+        return 0;
+}
+
+/**
+ * _get_sdma_req_by_name - fetch SDMA request line ID by name
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the SDMA request line to fetch (optional)
+ * @dma: pointer to an unsigned int to store the request line ID to
+ *
+ * Retrieve an SDMA request line ID named by @name on the IP block
+ * pointed to by @oh.  The ID will be filled into the address pointed
+ * to by @dma.  When @name is non-null, the request line ID associated
+ * with the named entry will be returned.  If @name is null, the first
+ * matching entry will be returned.  Data order is not meaningful in
+ * hwmod data, so callers are strongly encouraged to use a non-null
+ * @name whenever possible to avoid unpredictable effects if hwmod
+ * data is later added that causes data ordering to change.  Returns 0
+ * upon success or a negative error code upon error.
+ */
+static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name,
+                                 unsigned int *dma)
+{
+        int i;
+        bool found = false;
+
+        if (!oh->sdma_reqs)
+                return -ENOENT;
+
+        i = 0;
+        while (oh->sdma_reqs[i].dma_req != -1) {
+                if (name == oh->sdma_reqs[i].name ||
+                    !strcmp(name, oh->sdma_reqs[i].name)) {
+                        found = true;
                         break;
                 }
+                i++;
         }
 
-        if (found)
-                pr_debug("omap_hwmod: %s: MPU OCP slave port ID  %d\n",
-                         oh->name, i);
-        else
-                pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
-                         oh->name);
+        if (!found)
+                return -ENOENT;
+
+        *dma = oh->sdma_reqs[i].dma_req;
 
-        return (found) ? i : -EINVAL;
+        return 0;
 }
 
 /**
- * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
- * @oh: struct omap_hwmod *
+ * _get_addr_space_by_name - fetch address space start & end by name
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the address space to fetch (optional)
+ * @pa_start: pointer to a u32 to store the starting address to
+ * @pa_end: pointer to a u32 to store the ending address to
  *
- * Return the virtual address of the base of the register target of
- * device @oh, or NULL on error.
+ * Retrieve address space start and end addresses for the IP block
+ * pointed to by @oh.  The data will be filled into the addresses
+ * pointed to by @pa_start and @pa_end.  When @name is non-null, the
+ * address space data associated with the named entry will be
+ * returned.  If @name is null, the first matching entry will be
+ * returned.  Data order is not meaningful in hwmod data, so callers
+ * are strongly encouraged to use a non-null @name whenever possible
+ * to avoid unpredictable effects if hwmod data is later added that
+ * causes data ordering to change.  Returns 0 upon success or a
+ * negative error code upon error.
  */
-static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
+                                   u32 *pa_start, u32 *pa_end)
 {
+        int i, j;
         struct omap_hwmod_ocp_if *os;
-        struct omap_hwmod_addr_space *mem;
-        int i = 0, found = 0;
-        void __iomem *va_start;
+        struct list_head *p = NULL;
+        bool found = false;
+
+        p = oh->slave_ports.next;
+
+        i = 0;
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+
+                if (!os->addr)
+                        return -ENOENT;
+
+                j = 0;
+                while (os->addr[j].pa_start != os->addr[j].pa_end) {
+                        if (name == os->addr[j].name ||
+                            !strcmp(name, os->addr[j].name)) {
+                                found = true;
+                                break;
+                        }
+                        j++;
+                }
+
+                if (found)
+                        break;
+        }
+
+        if (!found)
+                return -ENOENT;
+
+        *pa_start = os->addr[j].pa_start;
+        *pa_end = os->addr[j].pa_end;
+
+        return 0;
+}
+
+/**
+ * _save_mpu_port_index - find and save the index to @oh's MPU port
+ * @oh: struct omap_hwmod *
+ *
+ * Determines the array index of the OCP slave port that the MPU uses
+ * to address the device, and saves it into the struct omap_hwmod.
+ * Intended to be called during hwmod registration only. No return
+ * value.
+ */
+static void __init _save_mpu_port_index(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os = NULL;
+        struct list_head *p;
+        int i = 0;
+
+        if (!oh)
+                return;
 
-        if (!oh || oh->slaves_cnt == 0)
+        oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+
+        p = oh->slave_ports.next;
+
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+                if (os->user & OCP_USER_MPU) {
+                        oh->_mpu_port = os;
+                        oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
+                        break;
+                }
+        }
+
+        return;
+}
+
+/**
+ * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU
+ * @oh: struct omap_hwmod *
+ *
+ * Given a pointer to a struct omap_hwmod record @oh, return a pointer
+ * to the struct omap_hwmod_ocp_if record that is used by the MPU to
+ * communicate with the IP block.  This interface need not be directly
+ * connected to the MPU (and almost certainly is not), but is directly
+ * connected to the IP block represented by @oh.  Returns a pointer
+ * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon
+ * error or if there does not appear to be a path from the MPU to this
+ * IP block.
+ */
+static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
+{
+        if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
                 return NULL;
 
-        os = oh->slaves[index];
+        return oh->_mpu_port;
+};
+
+/**
+ * _find_mpu_rt_addr_space - return MPU register target address space for @oh
+ * @oh: struct omap_hwmod *
+ *
+ * Returns a pointer to the struct omap_hwmod_addr_space record representing
+ * the register target MPU address space; or returns NULL upon error.
+ */
+static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        struct omap_hwmod_addr_space *mem;
+        int found = 0, i = 0;
 
-        if (!os->addr)
+        os = _find_mpu_rt_port(oh);
+        if (!os || !os->addr)
                 return NULL;
 
         do {
@@ -944,20 +1117,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
                         found = 1;
         } while (!found && mem->pa_start != mem->pa_end);
 
-        if (found) {
-                va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
-                if (!va_start) {
-                        pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
-                        return NULL;
-                }
-                pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
-                         oh->name, va_start);
-        } else {
-                pr_debug("omap_hwmod: %s: no MPU register target found\n",
-                         oh->name);
-        }
-
-        return (found) ? va_start : NULL;
+        return (found) ? mem : NULL;
 }
 
 /**
@@ -1205,12 +1365,11 @@ static int _wait_target_ready(struct omap_hwmod *oh)
         if (!oh)
                 return -EINVAL;
 
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+        if (oh->flags & HWMOD_NO_IDLEST)
                 return 0;
 
-        os = oh->slaves[oh->_mpu_port_index];
-
-        if (oh->flags & HWMOD_NO_IDLEST)
+        os = _find_mpu_rt_port(oh);
+        if (!os)
                 return 0;
 
         /* XXX check module SIDLEMODE */
@@ -1378,13 +1537,73 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 }
 
 /**
+ * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
+ * @oh: struct omap_hwmod *
+ *
+ * If any hardreset line associated with @oh is asserted, then return true.
+ * Otherwise, if @oh has no hardreset lines associated with it, or if
+ * no hardreset lines associated with @oh are asserted, then return false.
+ * This function is used to avoid executing some parts of the IP block
+ * enable/disable sequence if a hardreset line is set.
+ */
+static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+{
+        int i;
+
+        if (oh->rst_lines_cnt == 0)
+                return false;
+
+        for (i = 0; i < oh->rst_lines_cnt; i++)
+                if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
+                        return true;
+
+        return false;
+}
+
+/**
+ * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Disable the PRCM module mode related to the hwmod @oh.
+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
+ */
+static int _omap4_disable_module(struct omap_hwmod *oh)
+{
+        int v;
+
+        /* The module mode does not exist prior OMAP4 */
+        if (!cpu_is_omap44xx())
+                return -EINVAL;
+
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return -EINVAL;
+
+        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
+
+        omap4_cminst_module_disable(oh->clkdm->prcm_partition,
+                                    oh->clkdm->cm_inst,
+                                    oh->clkdm->clkdm_offs,
+                                    oh->prcm.omap4.clkctrl_offs);
+
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
+
+        v = _omap4_wait_target_disable(oh);
+        if (v)
+                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                        oh->name);
+
+        return 0;
+}
+
+/**
  * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
  * @oh: struct omap_hwmod *
  *
  * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
- * enabled for this to work.  Returns -EINVAL if the hwmod cannot be
- * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
- * the module did not reset in time, or 0 upon success.
+ * enabled for this to work.  Returns -ENOENT if the hwmod cannot be
+ * reset this way, -EINVAL if the hwmod is in the wrong state,
+ * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
  *
  * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
  * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
@@ -1401,7 +1620,7 @@ static int _ocp_softreset(struct omap_hwmod *oh)
 
         if (!oh->class->sysc ||
             !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
-                return -EINVAL;
+                return -ENOENT;
 
         /* clocks must be on for this operation */
         if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -1462,32 +1681,60 @@ dis_opt_clks:
  * _reset - reset an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Resets an omap_hwmod @oh.  The default software reset mechanism for
- * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET
- * bit.  However, some hwmods cannot be reset via this method: some
- * are not targets and therefore have no OCP header registers to
- * access; others (like the IVA) have idiosyncratic reset sequences.
- * So for these relatively rare cases, custom reset code can be
- * supplied in the struct omap_hwmod_class .reset function pointer.
- * Passes along the return value from either _reset() or the custom
- * reset function - these must return -EINVAL if the hwmod cannot be
- * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
- * the module did not reset in time, or 0 upon success.
+ * Resets an omap_hwmod @oh.  If the module has a custom reset
+ * function pointer defined, then call it to reset the IP block, and
+ * pass along its return value to the caller.  Otherwise, if the IP
+ * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield
+ * associated with it, call a function to reset the IP block via that
+ * method, and pass along the return value to the caller.  Finally, if
+ * the IP block has some hardreset lines associated with it, assert
+ * all of those, but do _not_ deassert them. (This is because driver
+ * authors have expressed an apparent requirement to control the
+ * deassertion of the hardreset lines themselves.)
+ *
+ * The default software reset mechanism for most OMAP IP blocks is
+ * triggered via the OCP_SYSCONFIG.SOFTRESET bit.  However, some
+ * hwmods cannot be reset via this method.  Some are not targets and
+ * therefore have no OCP header registers to access.  Others (like the
+ * IVA) have idiosyncratic reset sequences.  So for these relatively
+ * rare cases, custom reset code can be supplied in the struct
+ * omap_hwmod_class .reset function pointer.  Passes along the return
+ * value from either _ocp_softreset() or the custom reset function -
+ * these must return -EINVAL if the hwmod cannot be reset this way or
+ * if the hwmod is in the wrong state, -ETIMEDOUT if the module did
+ * not reset in time, or 0 upon success.
  */
 static int _reset(struct omap_hwmod *oh)
 {
-        int ret;
+        int i, r;
 
         pr_debug("omap_hwmod: %s: resetting\n", oh->name);
 
-        ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
+        if (oh->class->reset) {
+                r = oh->class->reset(oh);
+        } else {
+                if (oh->rst_lines_cnt > 0) {
+                        for (i = 0; i < oh->rst_lines_cnt; i++)
+                                _assert_hardreset(oh, oh->rst_lines[i].name);
+                        return 0;
+                } else {
+                        r = _ocp_softreset(oh);
+                        if (r == -ENOENT)
+                                r = 0;
+                }
+        }
 
+        /*
+         * OCP_SYSCONFIG bits need to be reprogrammed after a
+         * softreset.  The _enable() function should be split to avoid
+         * the rewrite of the OCP_SYSCONFIG register.
+         */
         if (oh->class->sysc) {
                 _update_sysc_cache(oh);
                 _enable_sysc(oh);
         }
 
-        return ret;
+        return r;
 }
 
 /**
@@ -1506,10 +1753,9 @@ static int _enable(struct omap_hwmod *oh)
         pr_debug("omap_hwmod: %s: enabling\n", oh->name);
 
         /*
-         * hwmods with HWMOD_INIT_NO_IDLE flag set are left
-         * in enabled state at init.
-         * Now that someone is really trying to enable them,
-         * just ensure that the hwmod mux is set.
+         * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
+         * state at init.  Now that someone is really trying to enable
+         * them, just ensure that the hwmod mux is set.
          */
         if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
                 /*
@@ -1532,15 +1778,17 @@ static int _enable(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
-
         /*
-         * If an IP contains only one HW reset line, then de-assert it in order
-         * to allow the module state transition. Otherwise the PRCM will return
-         * Intransition status, and the init will failed.
+         * If an IP block contains HW reset lines and any of them are
+         * asserted, we let integration code associated with that
+         * block handle the enable.  We've received very little
+         * information on what those driver authors need, and until
+         * detailed information is provided and the driver code is
+         * posted to the public lists, this is probably the best we
+         * can do.
          */
-        if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
-             oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
-                _deassert_hardreset(oh, oh->rst_lines[0].name);
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
 
         /* Mux pins for device runtime if populated */
         if (oh->mux && (!oh->mux->enabled ||
@@ -1615,6 +1863,9 @@ static int _idle(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
+
         if (oh->class->sysc)
                 _idle_sysc(oh);
         _del_initiator_dep(oh, mpu_oh);
@@ -1687,7 +1938,7 @@ int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
  */
 static int _shutdown(struct omap_hwmod *oh)
 {
-        int ret;
+        int ret, i;
         u8 prev_state;
 
         if (oh->_state != _HWMOD_STATE_IDLE &&
@@ -1697,6 +1948,9 @@ static int _shutdown(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
+
         pr_debug("omap_hwmod: %s: disabling\n", oh->name);
 
         if (oh->class->pre_shutdown) {
@@ -1728,12 +1982,8 @@ static int _shutdown(struct omap_hwmod *oh)
         }
         /* XXX Should this code also force-disable the optional clocks? */
 
-        /*
-         * If an IP contains only one HW reset line, then assert it
-         * after disabling the clocks and before shutting down the IP.
-         */
-        if (oh->rst_lines_cnt == 1)
-                _assert_hardreset(oh, oh->rst_lines[0].name);
+        for (i = 0; i < oh->rst_lines_cnt; i++)
+                _assert_hardreset(oh, oh->rst_lines[i].name);
 
         /* Mux pins to safe mode or use populated off mode values */
         if (oh->mux)
@@ -1745,59 +1995,186 @@ static int _shutdown(struct omap_hwmod *oh)
 }
 
 /**
- * _setup - do initial configuration of omap_hwmod
- * @oh: struct omap_hwmod *
+ * _init_mpu_rt_base - populate the virtual address for a hwmod
+ * @oh: struct omap_hwmod * to locate the virtual address
  *
- * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Returns 0.
+ * Cache the virtual address used by the MPU to access this IP block's
+ * registers.  This address is needed early so the OCP registers that
+ * are part of the device's address space can be ioremapped properly.
+ * No return value.
  */
-static int _setup(struct omap_hwmod *oh, void *data)
+static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
 {
-        int i, r;
-        u8 postsetup_state;
+        struct omap_hwmod_addr_space *mem;
+        void __iomem *va_start;
+
+        if (!oh)
+                return;
+
+        _save_mpu_port_index(oh);
 
-        if (oh->_state != _HWMOD_STATE_CLKS_INITED)
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return;
+
+        mem = _find_mpu_rt_addr_space(oh);
+        if (!mem) {
+                pr_debug("omap_hwmod: %s: no MPU register target found\n",
+                         oh->name);
+                return;
+        }
+
+        va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+        if (!va_start) {
+                pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
+                return;
+        }
+
+        pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
+                 oh->name, va_start);
+
+        oh->_mpu_rt_va = va_start;
+}
+
+/**
+ * _init - initialize internal data for the hwmod @oh
+ * @oh: struct omap_hwmod *
+ * @n: (unused)
+ *
+ * Look up the clocks and the address space used by the MPU to access
+ * registers belonging to the hwmod @oh.  @oh must already be
+ * registered at this point.  This is the first of two phases for
+ * hwmod initialization.  Code called here does not touch any hardware
+ * registers, it simply prepares internal data structures.  Returns 0
+ * upon success or if the hwmod isn't registered, or -EINVAL upon
+ * failure.
+ */
+static int __init _init(struct omap_hwmod *oh, void *data)
+{
+        int r;
+
+        if (oh->_state != _HWMOD_STATE_REGISTERED)
                 return 0;
 
-        /* Set iclk autoidle mode */
-        if (oh->slaves_cnt > 0) {
-                for (i = 0; i < oh->slaves_cnt; i++) {
-                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
-                        struct clk *c = os->_clk;
+        _init_mpu_rt_base(oh, NULL);
 
-                        if (!c)
-                                continue;
+        r = _init_clocks(oh, NULL);
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
+                return -EINVAL;
+        }
 
-                        if (os->flags & OCPIF_SWSUP_IDLE) {
-                                /* XXX omap_iclk_deny_idle(c); */
-                        } else {
-                                /* XXX omap_iclk_allow_idle(c); */
-                                clk_enable(c);
-                        }
+        oh->_state = _HWMOD_STATE_INITIALIZED;
+
+        return 0;
+}
+
+/**
+ * _setup_iclk_autoidle - configure an IP block's interface clocks
+ * @oh: struct omap_hwmod *
+ *
+ * Set up the module's interface clocks.  XXX This function is still mostly
+ * a stub; implementing this properly requires iclk autoidle usecounting in
+ * the clock code.   No return value.
+ */
+static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int i = 0;
+        if (oh->_state != _HWMOD_STATE_INITIALIZED)
+                return;
+
+        p = oh->slave_ports.next;
+
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+                if (!os->_clk)
+                        continue;
+
+                if (os->flags & OCPIF_SWSUP_IDLE) {
+                        /* XXX omap_iclk_deny_idle(c); */
+                } else {
+                        /* XXX omap_iclk_allow_idle(c); */
+                        clk_enable(os->_clk);
                 }
         }
 
-        oh->_state = _HWMOD_STATE_INITIALIZED;
+        return;
+}
 
-        /*
-         * In the case of hwmod with hardreset that should not be
-         * de-assert at boot time, we have to keep the module
-         * initialized, because we cannot enable it properly with the
-         * reset asserted. Exit without warning because that behavior is
-         * expected.
-         */
-        if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
-                return 0;
+/**
+ * _setup_reset - reset an IP block during the setup process
+ * @oh: struct omap_hwmod *
+ *
+ * Reset the IP block corresponding to the hwmod @oh during the setup
+ * process.  The IP block is first enabled so it can be successfully
+ * reset.  Returns 0 upon success or a negative error code upon
+ * failure.
+ */
+static int __init _setup_reset(struct omap_hwmod *oh)
+{
+        int r;
 
-        r = _enable(oh);
-        if (r) {
-                pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
-                           oh->name, oh->_state);
-                return 0;
+        if (oh->_state != _HWMOD_STATE_INITIALIZED)
+                return -EINVAL;
+
+        if (oh->rst_lines_cnt == 0) {
+                r = _enable(oh);
+                if (r) {
+                        pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
+                                   oh->name, oh->_state);
+                        return -EINVAL;
+                }
         }
 
         if (!(oh->flags & HWMOD_INIT_NO_RESET))
-                _reset(oh);
+                r = _reset(oh);
+
+        return r;
+}
+
+/**
+ * _setup_postsetup - transition to the appropriate state after _setup
+ * @oh: struct omap_hwmod *
+ *
+ * Place an IP block represented by @oh into a "post-setup" state --
+ * either IDLE, ENABLED, or DISABLED.  ("post-setup" simply means that
+ * this function is called at the end of _setup().)  The postsetup
+ * state for an IP block can be changed by calling
+ * omap_hwmod_enter_postsetup_state() early in the boot process,
+ * before one of the omap_hwmod_setup*() functions are called for the
+ * IP block.
+ *
+ * The IP block stays in this state until a PM runtime-based driver is
+ * loaded for that IP block.  A post-setup state of IDLE is
+ * appropriate for almost all IP blocks with runtime PM-enabled
+ * drivers, since those drivers are able to enable the IP block.  A
+ * post-setup state of ENABLED is appropriate for kernels with PM
+ * runtime disabled.  The DISABLED state is appropriate for unusual IP
+ * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers
+ * included, since the WDTIMER starts running on reset and will reset
+ * the MPU if left active.
+ *
+ * This post-setup mechanism is deprecated.  Once all of the OMAP
+ * drivers have been converted to use PM runtime, and all of the IP
+ * block data and interconnect data is available to the hwmod code, it
+ * should be possible to replace this mechanism with a "lazy reset"
+ * arrangement.  In a "lazy reset" setup, each IP block is enabled
+ * when the driver first probes, then all remaining IP blocks without
+ * drivers are either shut down or enabled after the drivers have
+ * loaded.  However, this cannot take place until the above
+ * preconditions have been met, since otherwise the late reset code
+ * has no way of knowing which IP blocks are in use by drivers, and
+ * which ones are unused.
+ *
+ * No return value.
+ */
+static void __init _setup_postsetup(struct omap_hwmod *oh)
+{
+        u8 postsetup_state;
+
+        if (oh->rst_lines_cnt > 0)
+                return;
 
         postsetup_state = oh->_postsetup_state;
         if (postsetup_state == _HWMOD_STATE_UNKNOWN)
@@ -1821,6 +2198,35 @@ static int _setup(struct omap_hwmod *oh, void *data)
                 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
                      oh->name, postsetup_state);
 
+        return;
+}
+
+/**
+ * _setup - prepare IP block hardware for use
+ * @oh: struct omap_hwmod *
+ * @n: (unused, pass NULL)
+ *
+ * Configure the IP block represented by @oh.  This may include
+ * enabling the IP block, resetting it, and placing it into a
+ * post-setup state, depending on the type of IP block and applicable
+ * flags.  IP blocks are reset to prevent any previous configuration
+ * by the bootloader or previous operating system from interfering
+ * with power management or other parts of the system.  The reset can
+ * be avoided; see omap_hwmod_no_setup_reset().  This is the second of
+ * two phases for hwmod initialization.  Code called here generally
+ * affects the IP block hardware, or system integration hardware
+ * associated with the IP block.  Returns 0.
+ */
+static int __init _setup(struct omap_hwmod *oh, void *data)
+{
+        if (oh->_state != _HWMOD_STATE_INITIALIZED)
+                return 0;
+
+        _setup_iclk_autoidle(oh);
+
+        if (!_setup_reset(oh))
+                _setup_postsetup(oh);
+
         return 0;
 }
 
@@ -1843,8 +2249,6 @@ static int _setup(struct omap_hwmod *oh, void *data)
  */
 static int __init _register(struct omap_hwmod *oh)
 {
-        int ms_id;
-
         if (!oh || !oh->name || !oh->class || !oh->class->name ||
             (oh->_state != _HWMOD_STATE_UNKNOWN))
                 return -EINVAL;
@@ -1854,14 +2258,10 @@ static int __init _register(struct omap_hwmod *oh)
         if (_lookup(oh->name))
                 return -EEXIST;
 
-        ms_id = _find_mpu_port_index(oh);
-        if (!IS_ERR_VALUE(ms_id))
-                oh->_mpu_port_index = ms_id;
-        else
-                oh->_int_flags |= _HWMOD_NO_MPU_PORT;
-
         list_add_tail(&oh->node, &omap_hwmod_list);
 
+        INIT_LIST_HEAD(&oh->master_ports);
+        INIT_LIST_HEAD(&oh->slave_ports);
         spin_lock_init(&oh->_lock);
 
         oh->_state = _HWMOD_STATE_REGISTERED;
@@ -1876,6 +2276,160 @@ static int __init _register(struct omap_hwmod *oh)
         return 0;
 }
 
+/**
+ * _alloc_links - return allocated memory for hwmod links
+ * @ml: pointer to a struct omap_hwmod_link * for the master link
+ * @sl: pointer to a struct omap_hwmod_link * for the slave link
+ *
+ * Return pointers to two struct omap_hwmod_link records, via the
+ * addresses pointed to by @ml and @sl.  Will first attempt to return
+ * memory allocated as part of a large initial block, but if that has
+ * been exhausted, will allocate memory itself.  Since ideally this
+ * second allocation path will never occur, the number of these
+ * 'supplemental' allocations will be logged when debugging is
+ * enabled.  Returns 0.
+ */
+static int __init _alloc_links(struct omap_hwmod_link **ml,
+                               struct omap_hwmod_link **sl)
+{
+        unsigned int sz;
+
+        if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) {
+                *ml = &linkspace[free_ls++];
+                *sl = &linkspace[free_ls++];
+                return 0;
+        }
+
+        sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
+
+        *sl = NULL;
+        *ml = alloc_bootmem(sz);
+
+        memset(*ml, 0, sz);
+
+        *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
+
+        ls_supp++;
+        pr_debug("omap_hwmod: supplemental link allocations needed: %d\n",
+                 ls_supp * LINKS_PER_OCP_IF);
+
+        return 0;
+};
+
+/**
+ * _add_link - add an interconnect between two IP blocks
+ * @oi: pointer to a struct omap_hwmod_ocp_if record
+ *
+ * Add struct omap_hwmod_link records connecting the master IP block
+ * specified in @oi->master to @oi, and connecting the slave IP block
+ * specified in @oi->slave to @oi.  This code is assumed to run before
+ * preemption or SMP has been enabled, thus avoiding the need for
+ * locking in this code.  Changes to this assumption will require
+ * additional locking.  Returns 0.
+ */
+static int __init _add_link(struct omap_hwmod_ocp_if *oi)
+{
+        struct omap_hwmod_link *ml, *sl;
+
+        pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
+                 oi->slave->name);
+
+        _alloc_links(&ml, &sl);
+
+        ml->ocp_if = oi;
+        INIT_LIST_HEAD(&ml->node);
+        list_add(&ml->node, &oi->master->master_ports);
+        oi->master->masters_cnt++;
+
+        sl->ocp_if = oi;
+        INIT_LIST_HEAD(&sl->node);
+        list_add(&sl->node, &oi->slave->slave_ports);
+        oi->slave->slaves_cnt++;
+
+        return 0;
+}
+
+/**
+ * _register_link - register a struct omap_hwmod_ocp_if
+ * @oi: struct omap_hwmod_ocp_if *
+ *
+ * Registers the omap_hwmod_ocp_if record @oi.  Returns -EEXIST if it
+ * has already been registered; -EINVAL if @oi is NULL or if the
+ * record pointed to by @oi is missing required fields; or 0 upon
+ * success.
+ *
+ * XXX The data should be copied into bootmem, so the original data
+ * should be marked __initdata and freed after init.  This would allow
+ * unneeded omap_hwmods to be freed on multi-OMAP configurations.
+ */
+static int __init _register_link(struct omap_hwmod_ocp_if *oi)
+{
+        if (!oi || !oi->master || !oi->slave || !oi->user)
+                return -EINVAL;
+
+        if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
+                return -EEXIST;
+
+        pr_debug("omap_hwmod: registering link from %s to %s\n",
+                 oi->master->name, oi->slave->name);
+
+        /*
+         * Register the connected hwmods, if they haven't been
+         * registered already
+         */
+        if (oi->master->_state != _HWMOD_STATE_REGISTERED)
+                _register(oi->master);
+
+        if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
+                _register(oi->slave);
+
+        _add_link(oi);
+
+        oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
+
+        return 0;
+}
+
+/**
+ * _alloc_linkspace - allocate large block of hwmod links
+ * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count
+ *
+ * Allocate a large block of struct omap_hwmod_link records.  This
+ * improves boot time significantly by avoiding the need to allocate
+ * individual records one by one.  If the number of records to
+ * allocate in the block hasn't been manually specified, this function
+ * will count the number of struct omap_hwmod_ocp_if records in @ois
+ * and use that to determine the allocation size.  For SoC families
+ * that require multiple list registrations, such as OMAP3xxx, this
+ * estimation process isn't optimal, so manual estimation is advised
+ * in those cases.  Returns -EEXIST if the allocation has already occurred
+ * or 0 upon success.
+ */
+static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
+{
+        unsigned int i = 0;
+        unsigned int sz;
+
+        if (linkspace) {
+                WARN(1, "linkspace already allocated\n");
+                return -EEXIST;
+        }
+
+        if (max_ls == 0)
+                while (ois[i++])
+                        max_ls += LINKS_PER_OCP_IF;
+
+        sz = sizeof(struct omap_hwmod_link) * max_ls;
+
+        pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
+                 __func__, sz, max_ls);
+
+        linkspace = alloc_bootmem(sz);
+
+        memset(linkspace, 0, sz);
+
+        return 0;
+}
 
 /* Public functions */
 
@@ -2004,120 +2558,101 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
 }
 
 /**
- * omap_hwmod_register - register an array of hwmods
- * @ohs: pointer to an array of omap_hwmods to register
+ * omap_hwmod_register_links - register an array of hwmod links
+ * @ois: pointer to an array of omap_hwmod_ocp_if to register
  *
  * Intended to be called early in boot before the clock framework is
- * initialized.  If @ohs is not null, will register all omap_hwmods
- * listed in @ohs that are valid for this chip.  Returns 0.
+ * initialized.  If @ois is not null, will register all omap_hwmods
+ * listed in @ois that are valid for this chip.  Returns 0.
  */
-int __init omap_hwmod_register(struct omap_hwmod **ohs)
+int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
 {
         int r, i;
 
-        if (!ohs)
+        if (!ois)
                 return 0;
 
+        if (!linkspace) {
+                if (_alloc_linkspace(ois)) {
+                        pr_err("omap_hwmod: could not allocate link space\n");
+                        return -ENOMEM;
+                }
+        }
+
         i = 0;
         do {
-                r = _register(ohs[i]);
-                WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
-                     r);
-        } while (ohs[++i]);
+                r = _register_link(ois[i]);
+                WARN(r && r != -EEXIST,
+                     "omap_hwmod: _register_link(%s -> %s) returned %d\n",
+                     ois[i]->master->name, ois[i]->slave->name, r);
+        } while (ois[++i]);
 
         return 0;
 }
 
-/*
- * _populate_mpu_rt_base - populate the virtual address for a hwmod
+/**
+ * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
+ * @oh: pointer to the hwmod currently being set up (usually not the MPU)
  *
- * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
- * Assumes the caller takes care of locking if needed.
+ * If the hwmod data corresponding to the MPU subsystem IP block
+ * hasn't been initialized and set up yet, do so now.  This must be
+ * done first since sleep dependencies may be added from other hwmods
+ * to the MPU.  Intended to be called only by omap_hwmod_setup*().  No
+ * return value.
  */
-static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
 {
-        if (oh->_state != _HWMOD_STATE_REGISTERED)
-                return 0;
-
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
-                return 0;
-
-        oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
-
-        return 0;
+        if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
+                pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
+                       __func__, MPU_INITIATOR_NAME);
+        else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
+                omap_hwmod_setup_one(MPU_INITIATOR_NAME);
 }
 
 /**
  * omap_hwmod_setup_one - set up a single hwmod
  * @oh_name: const char * name of the already-registered hwmod to set up
  *
- * Must be called after omap2_clk_init().  Resolves the struct clk
- * names to struct clk pointers for each registered omap_hwmod.  Also
- * calls _setup() on each hwmod.  Returns -EINVAL upon error or 0 upon
- * success.
+ * Initialize and set up a single hwmod.  Intended to be used for a
+ * small number of early devices, such as the timer IP blocks used for
+ * the scheduler clock.  Must be called after omap2_clk_init().
+ * Resolves the struct clk names to struct clk pointers for each
+ * registered omap_hwmod.  Also calls _setup() on each hwmod.  Returns
+ * -EINVAL upon error or 0 upon success.
  */
 int __init omap_hwmod_setup_one(const char *oh_name)
 {
         struct omap_hwmod *oh;
-        int r;
 
         pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
 
-        if (!mpu_oh) {
-                pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
-                       oh_name, MPU_INITIATOR_NAME);
-                return -EINVAL;
-        }
-
         oh = _lookup(oh_name);
         if (!oh) {
                 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
                 return -EINVAL;
         }
 
-        if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
-                omap_hwmod_setup_one(MPU_INITIATOR_NAME);
-
-        r = _populate_mpu_rt_base(oh, NULL);
-        if (IS_ERR_VALUE(r)) {
-                WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
-                return -EINVAL;
-        }
-
-        r = _init_clocks(oh, NULL);
-        if (IS_ERR_VALUE(r)) {
-                WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
-                return -EINVAL;
-        }
+        _ensure_mpu_hwmod_is_setup(oh);
 
+        _init(oh, NULL);
         _setup(oh, NULL);
 
         return 0;
 }
 
 /**
- * omap_hwmod_setup - do some post-clock framework initialization
+ * omap_hwmod_setup_all - set up all registered IP blocks
  *
- * Must be called after omap2_clk_init().  Resolves the struct clk names
- * to struct clk pointers for each registered omap_hwmod.  Also calls
- * _setup() on each hwmod.  Returns 0 upon success.
+ * Initialize and set up all IP blocks registered with the hwmod code.
+ * Must be called after omap2_clk_init().  Resolves the struct clk
+ * names to struct clk pointers for each registered omap_hwmod.  Also
+ * calls _setup() on each hwmod.  Returns 0 upon success.
  */
 static int __init omap_hwmod_setup_all(void)
 {
-        int r;
-
-        if (!mpu_oh) {
-                pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
-                       __func__, MPU_INITIATOR_NAME);
-                return -EINVAL;
-        }
-
-        r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
-
-        r = omap_hwmod_for_each(_init_clocks, NULL);
-        WARN(IS_ERR_VALUE(r),
-             "omap_hwmod: %s: _init_clocks failed\n", __func__);
+        _ensure_mpu_hwmod_is_setup(NULL);
 
+        omap_hwmod_for_each(_init, NULL);
         omap_hwmod_for_each(_setup, NULL);
 
         return 0;
@@ -2274,6 +2809,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
         return r;
 }
 
+/*
+ * IP block data retrieval functions
+ */
+
 /**
  * omap_hwmod_count_resources - count number of struct resources needed by hwmod
  * @oh: struct omap_hwmod *
@@ -2292,12 +2831,19 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
  */
 int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
-        int ret, i;
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int ret;
+        int i = 0;
 
         ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
 
-        for (i = 0; i < oh->slaves_cnt; i++)
-                ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
+        p = oh->slave_ports.next;
+
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+                ret += _count_ocp_if_addr_spaces(os);
+        }
 
         return ret;
 }
@@ -2314,7 +2860,9 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
  */
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 {
-        int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
         int r = 0;
 
         /* For each IRQ, DMA, memory area, fill in array.*/
@@ -2337,11 +2885,11 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
                 r++;
         }
 
-        for (i = 0; i < oh->slaves_cnt; i++) {
-                struct omap_hwmod_ocp_if *os;
-                int addr_cnt;
+        p = oh->slave_ports.next;
 
-                os = oh->slaves[i];
+        i = 0;
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
                 addr_cnt = _count_ocp_if_addr_spaces(os);
 
                 for (j = 0; j < addr_cnt; j++) {
@@ -2357,6 +2905,69 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 }
 
 /**
+ * omap_hwmod_get_resource_byname - fetch IP block integration data by name
+ * @oh: struct omap_hwmod * to operate on
+ * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
+ * @name: pointer to the name of the data to fetch (optional)
+ * @rsrc: pointer to a struct resource, allocated by the caller
+ *
+ * Retrieve MPU IRQ, SDMA request line, or address space start/end
+ * data for the IP block pointed to by @oh.  The data will be filled
+ * into a struct resource record pointed to by @rsrc.  The struct
+ * resource must be allocated by the caller.  When @name is non-null,
+ * the data associated with the matching entry in the IRQ/SDMA/address
+ * space hwmod data arrays will be returned.  If @name is null, the
+ * first array entry will be returned.  Data order is not meaningful
+ * in hwmod data, so callers are strongly encouraged to use a non-null
+ * @name whenever possible to avoid unpredictable effects if hwmod
+ * data is later added that causes data ordering to change.  This
+ * function is only intended for use by OMAP core code.  Device
+ * drivers should not call this function - the appropriate bus-related
+ * data accessor functions should be used instead.  Returns 0 upon
+ * success or a negative error code upon error.
+ */
+int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
+                                   const char *name, struct resource *rsrc)
+{
+        int r;
+        unsigned int irq, dma;
+        u32 pa_start, pa_end;
+
+        if (!oh || !rsrc)
+                return -EINVAL;
+
+        if (type == IORESOURCE_IRQ) {
+                r = _get_mpu_irq_by_name(oh, name, &irq);
+                if (r)
+                        return r;
+
+                rsrc->start = irq;
+                rsrc->end = irq;
+        } else if (type == IORESOURCE_DMA) {
+                r = _get_sdma_req_by_name(oh, name, &dma);
+                if (r)
+                        return r;
+
+                rsrc->start = dma;
+                rsrc->end = dma;
+        } else if (type == IORESOURCE_MEM) {
+                r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end);
+                if (r)
+                        return r;
+
+                rsrc->start = pa_start;
+                rsrc->end = pa_end;
+        } else {
+                return -EINVAL;
+        }
+
+        rsrc->flags = type;
+        rsrc->name = name;
+
+        return 0;
+}
+
+/**
  * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
  * @oh: struct omap_hwmod *
  *
@@ -2370,6 +2981,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
 {
         struct clk *c;
+        struct omap_hwmod_ocp_if *oi;
 
         if (!oh)
                 return NULL;
@@ -2377,9 +2989,10 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
         if (oh->_clk) {
                 c = oh->_clk;
         } else {
-                if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                oi = _find_mpu_rt_port(oh);
+                if (!oi)
                         return NULL;
-                c = oh->slaves[oh->_mpu_port_index]->_clk;
+                c = oi->_clk;
         }
 
         if (!c->clkdm)
@@ -2653,10 +3266,10 @@ int omap_hwmod_for_each_by_class(const char *classname,
  * @state: state that _setup() should leave the hwmod in
  *
  * Sets the hwmod state that @oh will enter at the end of _setup()
- * (called by omap_hwmod_setup_*()).  Only valid to call between
- * calling omap_hwmod_register() and omap_hwmod_setup_*().  Returns
- * 0 upon success or -EINVAL if there is a problem with the arguments
- * or if the hwmod is in the wrong state.
+ * (called by omap_hwmod_setup_*()).  See also the documentation
+ * for _setup_postsetup(), above.  Returns 0 upon success or
+ * -EINVAL if there is a problem with the arguments or if the hwmod is
+ * in the wrong state.
  */
 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
 {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a6bde34e443a..a7640d1b215e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -2,6 +2,7 @@
  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
  *
  * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -22,6 +23,7 @@
 #include <plat/dmtimer.h>
 #include <plat/l3_2xxx.h>
 #include <plat/l4_2xxx.h>
+#include <plat/mmc.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -32,707 +34,329 @@
 /*
  * OMAP2420 hardware module integration data
  *
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
  * TI hardware database or other technical documentation.  Data that
  * is driver-specific or driver-kernel integration-specific belongs
  * elsewhere.
  */
 
-static struct omap_hwmod omap2420_mpu_hwmod;
-static struct omap_hwmod omap2420_iva_hwmod;
-static struct omap_hwmod omap2420_l3_main_hwmod;
-static struct omap_hwmod omap2420_l4_core_hwmod;
-static struct omap_hwmod omap2420_dss_core_hwmod;
-static struct omap_hwmod omap2420_dss_dispc_hwmod;
-static struct omap_hwmod omap2420_dss_rfbi_hwmod;
-static struct omap_hwmod omap2420_dss_venc_hwmod;
-static struct omap_hwmod omap2420_wd_timer2_hwmod;
-static struct omap_hwmod omap2420_gpio1_hwmod;
-static struct omap_hwmod omap2420_gpio2_hwmod;
-static struct omap_hwmod omap2420_gpio3_hwmod;
-static struct omap_hwmod omap2420_gpio4_hwmod;
-static struct omap_hwmod omap2420_dma_system_hwmod;
-static struct omap_hwmod omap2420_mcspi1_hwmod;
-static struct omap_hwmod omap2420_mcspi2_hwmod;
-
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
-        .master = &omap2420_l3_main_hwmod,
-        .slave  = &omap2420_l4_core_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
-        .master = &omap2420_mpu_hwmod,
-        .slave  = &omap2420_l3_main_hwmod,
-        .user   = OCP_USER_MPU,
-};
-
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
-        &omap2420_mpu__l3_main,
-};
-
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
-        .master         = &omap2420_dss_core_hwmod,
-        .slave          = &omap2420_l3_main_hwmod,
-        .fw = {
-                .omap2 = {
-                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
-                        .flags  = OMAP_FIREWALL_L3,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
-        &omap2420_l3_main__l4_core,
-};
-
-/* L3 */
-static struct omap_hwmod omap2420_l3_main_hwmod = {
-        .name           = "l3_main",
-        .class          = &l3_hwmod_class,
-        .masters        = omap2420_l3_main_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
-        .slaves         = omap2420_l3_main_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod omap2420_l4_wkup_hwmod;
-static struct omap_hwmod omap2420_uart1_hwmod;
-static struct omap_hwmod omap2420_uart2_hwmod;
-static struct omap_hwmod omap2420_uart3_hwmod;
-static struct omap_hwmod omap2420_i2c1_hwmod;
-static struct omap_hwmod omap2420_i2c2_hwmod;
-static struct omap_hwmod omap2420_mcbsp1_hwmod;
-static struct omap_hwmod omap2420_mcbsp2_hwmod;
-
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_mcspi1_hwmod,
-        .clk            = "mcspi1_ick",
-        .addr           = omap2_mcspi1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_mcspi2_hwmod,
-        .clk            = "mcspi2_ick",
-        .addr           = omap2_mcspi2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
-        .master = &omap2420_l4_core_hwmod,
-        .slave  = &omap2420_l4_wkup_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_uart1_hwmod,
-        .clk            = "uart1_ick",
-        .addr           = omap2xxx_uart1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_uart2_hwmod,
-        .clk            = "uart2_ick",
-        .addr           = omap2xxx_uart2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_uart3_hwmod,
-        .clk            = "uart3_ick",
-        .addr           = omap2xxx_uart3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_i2c1_hwmod,
-        .clk            = "i2c1_ick",
-        .addr           = omap2_i2c1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_i2c2_hwmod,
-        .clk            = "i2c2_ick",
-        .addr           = omap2_i2c2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
-        &omap2420_l3_main__l4_core,
-};
-
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
-        &omap2420_l4_core__l4_wkup,
-        &omap2_l4_core__uart1,
-        &omap2_l4_core__uart2,
-        &omap2_l4_core__uart3,
-        &omap2420_l4_core__i2c1,
-        &omap2420_l4_core__i2c2
-};
-
-/* L4 CORE */
-static struct omap_hwmod omap2420_l4_core_hwmod = {
-        .name           = "l4_core",
-        .class          = &l4_hwmod_class,
-        .masters        = omap2420_l4_core_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
-        .slaves         = omap2420_l4_core_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
-        &omap2420_l4_core__l4_wkup,
-};
-
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
-};
-
-/* L4 WKUP */
-static struct omap_hwmod omap2420_l4_wkup_hwmod = {
-        .name           = "l4_wkup",
-        .class          = &l4_hwmod_class,
-        .masters        = omap2420_l4_wkup_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
-        .slaves         = omap2420_l4_wkup_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
-        &omap2420_mpu__l3_main,
-};
-
-/* MPU */
-static struct omap_hwmod omap2420_mpu_hwmod = {
-        .name           = "mpu",
-        .class          = &mpu_hwmod_class,
-        .main_clk       = "mpu_ck",
-        .masters        = omap2420_mpu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
-};
-
 /*
- * IVA1 interface data
+ * IP blocks
  */
 
-/* IVA <- L3 interface */
-static struct omap_hwmod_ocp_if omap2420_l3__iva = {
-        .master         = &omap2420_l3_main_hwmod,
-        .slave          = &omap2420_iva_hwmod,
-        .clk            = "iva1_ifck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+/* IVA1 (IVA1) */
+static struct omap_hwmod_class iva1_hwmod_class = {
+        .name           = "iva1",
 };
 
-static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
-        &omap2420_l3__iva,
+static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
+        { .name = "iva", .rst_shift = 8 },
 };
 
-/*
- * IVA2 (IVA2)
- */
-
 static struct omap_hwmod omap2420_iva_hwmod = {
         .name           = "iva",
-        .class          = &iva_hwmod_class,
-        .masters        = omap2420_iva_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
-};
-
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
-        .timer_capability       = OMAP_TIMER_ALWON,
+        .class          = &iva1_hwmod_class,
+        .clkdm_name     = "iva1_clkdm",
+        .rst_lines      = omap2420_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
+        .main_clk       = "iva1_ifck",
 };
 
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
-        .timer_capability       = OMAP_TIMER_HAS_PWM,
-};
-
-/* timer1 */
-static struct omap_hwmod omap2420_timer1_hwmod;
-
-static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
-        {
-                .pa_start       = 0x48028000,
-                .pa_end         = 0x48028000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
+/* DSP */
+static struct omap_hwmod_class dsp_hwmod_class = {
+        .name           = "dsp",
 };
 
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
-        .master         = &omap2420_l4_wkup_hwmod,
-        .slave          = &omap2420_timer1_hwmod,
-        .clk            = "gpt1_ick",
-        .addr           = omap2420_timer1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
+        { .name = "logic", .rst_shift = 0 },
+        { .name = "mmu", .rst_shift = 1 },
 };
 
-/* timer1 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
-        &omap2420_l4_wkup__timer1,
+static struct omap_hwmod omap2420_dsp_hwmod = {
+        .name           = "dsp",
+        .class          = &dsp_hwmod_class,
+        .clkdm_name     = "dsp_clkdm",
+        .rst_lines      = omap2420_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
+        .main_clk       = "dsp_fck",
 };
 
-/* timer1 hwmod */
-static struct omap_hwmod omap2420_timer1_hwmod = {
-        .name           = "timer1",
-        .mpu_irqs       = omap2_timer1_mpu_irqs,
-        .main_clk       = "gpt1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x20,
+        .syss_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
-/* timer2 */
-static struct omap_hwmod omap2420_timer2_hwmod;
-
-/* l4_core -> timer2 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer2_hwmod,
-        .clk            = "gpt2_ick",
-        .addr           = omap2xxx_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &i2c_sysc,
+        .rev            = OMAP_I2C_IP_VERSION_1,
+        .reset          = &omap_i2c_reset,
 };
 
-/* timer2 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
-        &omap2420_l4_core__timer2,
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags          = OMAP_I2C_FLAG_NO_FIFO |
+                          OMAP_I2C_FLAG_SIMPLE_CLOCK |
+                          OMAP_I2C_FLAG_16BIT_DATA_REG |
+                          OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
-/* timer2 hwmod */
-static struct omap_hwmod omap2420_timer2_hwmod = {
-        .name           = "timer2",
-        .mpu_irqs       = omap2_timer2_mpu_irqs,
-        .main_clk       = "gpt2_fck",
+/* I2C1 */
+static struct omap_hwmod omap2420_i2c1_hwmod = {
+        .name           = "i2c1",
+        .mpu_irqs       = omap2_i2c1_mpu_irqs,
+        .sdma_reqs      = omap2_i2c1_sdma_reqs,
+        .main_clk       = "i2c1_fck",
         .prcm           = {
                 .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
                         .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2420_EN_I2C1_SHIFT,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                        .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer3 */
-static struct omap_hwmod omap2420_timer3_hwmod;
-
-/* l4_core -> timer3 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer3_hwmod,
-        .clk            = "gpt3_ick",
-        .addr           = omap2xxx_timer3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
-        &omap2420_l4_core__timer3,
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .flags          = HWMOD_16BIT_REG,
 };
 
-/* timer3 hwmod */
-static struct omap_hwmod omap2420_timer3_hwmod = {
-        .name           = "timer3",
-        .mpu_irqs       = omap2_timer3_mpu_irqs,
-        .main_clk       = "gpt3_fck",
+/* I2C2 */
+static struct omap_hwmod omap2420_i2c2_hwmod = {
+        .name           = "i2c2",
+        .mpu_irqs       = omap2_i2c2_mpu_irqs,
+        .sdma_reqs      = omap2_i2c2_sdma_reqs,
+        .main_clk       = "i2c2_fck",
         .prcm           = {
                 .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
                         .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2420_EN_I2C2_SHIFT,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                        .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .flags          = HWMOD_16BIT_REG,
 };
 
-/* timer4 */
-static struct omap_hwmod omap2420_timer4_hwmod;
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                                IS_CSSA_32 | IS_CDSA_32,
+        .lch_count = 32,
+};
 
-/* l4_core -> timer4 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer4_hwmod,
-        .clk            = "gpt4_ick",
-        .addr           = omap2xxx_timer4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod omap2420_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap2xxx_dma_hwmod_class,
+        .mpu_irqs       = omap2_dma_system_irqs,
+        .main_clk       = "core_l3_ck",
+        .dev_attr       = &dma_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
 };
 
-/* timer4 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
-        &omap2420_l4_core__timer4,
+/* mailbox */
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+        { .name = "dsp", .irq = 26 },
+        { .name = "iva", .irq = 34 },
+        { .irq = -1 }
 };
 
-/* timer4 hwmod */
-static struct omap_hwmod omap2420_timer4_hwmod = {
-        .name           = "timer4",
-        .mpu_irqs       = omap2_timer4_mpu_irqs,
-        .main_clk       = "gpt4_fck",
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap2xxx_mailbox_hwmod_class,
+        .mpu_irqs       = omap2420_mailbox_irqs,
+        .main_clk       = "mailboxes_ick",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
                         .module_offs = CORE_MOD,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
 
-/* timer5 */
-static struct omap_hwmod omap2420_timer5_hwmod;
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
 
-/* l4_core -> timer5 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer5_hwmod,
-        .clk            = "gpt5_ick",
-        .addr           = omap2xxx_timer5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
+        .name = "mcbsp",
 };
 
-/* timer5 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
-        &omap2420_l4_core__timer5,
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
+        { .name = "tx", .irq = 59 },
+        { .name = "rx", .irq = 60 },
+        { .irq = -1 }
 };
 
-/* timer5 hwmod */
-static struct omap_hwmod omap2420_timer5_hwmod = {
-        .name           = "timer5",
-        .mpu_irqs       = omap2_timer5_mpu_irqs,
-        .main_clk       = "gpt5_fck",
+static struct omap_hwmod omap2420_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap2420_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2420_mcbsp1_irqs,
+        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
+        .main_clk       = "mcbsp1_fck",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
                         .module_offs = CORE_MOD,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
 
-
-/* timer6 */
-static struct omap_hwmod omap2420_timer6_hwmod;
-
-/* l4_core -> timer6 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer6_hwmod,
-        .clk            = "gpt6_ick",
-        .addr           = omap2xxx_timer6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
-        &omap2420_l4_core__timer6,
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
+        { .name = "tx", .irq = 62 },
+        { .name = "rx", .irq = 63 },
+        { .irq = -1 }
 };
 
-/* timer6 hwmod */
-static struct omap_hwmod omap2420_timer6_hwmod = {
-        .name           = "timer6",
-        .mpu_irqs       = omap2_timer6_mpu_irqs,
-        .main_clk       = "gpt6_fck",
+static struct omap_hwmod omap2420_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap2420_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2420_mcbsp2_irqs,
+        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
+        .main_clk       = "mcbsp2_fck",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
                         .module_offs = CORE_MOD,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
 
-/* timer7 */
-static struct omap_hwmod omap2420_timer7_hwmod;
-
-/* l4_core -> timer7 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer7_hwmod,
-        .clk            = "gpt7_ick",
-        .addr           = omap2xxx_timer7_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
-        &omap2420_l4_core__timer7,
+static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
+        .rev_offs       = 0x3c,
+        .sysc_offs      = 0x64,
+        .syss_offs      = 0x68,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
-/* timer7 hwmod */
-static struct omap_hwmod omap2420_timer7_hwmod = {
-        .name           = "timer7",
-        .mpu_irqs       = omap2_timer7_mpu_irqs,
-        .main_clk       = "gpt7_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer7_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
+static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
+        .name   = "msdi",
+        .sysc   = &omap2420_msdi_sysc,
+        .reset  = &omap_msdi_reset,
 };
 
-/* timer8 */
-static struct omap_hwmod omap2420_timer8_hwmod;
-
-/* l4_core -> timer8 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer8_hwmod,
-        .clk            = "gpt8_ick",
-        .addr           = omap2xxx_timer8_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+/* msdi1 */
+static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
+        { .irq = 83 },
+        { .irq = -1 }
 };
 
-/* timer8 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
-        &omap2420_l4_core__timer8,
+static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
+        { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
+        { .dma_req = -1 }
 };
 
-/* timer8 hwmod */
-static struct omap_hwmod omap2420_timer8_hwmod = {
-        .name           = "timer8",
-        .mpu_irqs       = omap2_timer8_mpu_irqs,
-        .main_clk       = "gpt8_fck",
+static struct omap_hwmod omap2420_msdi1_hwmod = {
+        .name           = "msdi1",
+        .class          = &omap2420_msdi_hwmod_class,
+        .mpu_irqs       = omap2420_msdi1_irqs,
+        .sdma_reqs      = omap2420_msdi1_sdma_reqs,
+        .main_clk       = "mmc_fck",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_bit = OMAP2420_EN_MMC_SHIFT,
                         .module_offs = CORE_MOD,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                        .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer8_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer9 */
-static struct omap_hwmod omap2420_timer9_hwmod;
-
-/* l4_core -> timer9 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer9_hwmod,
-        .clk            = "gpt9_ick",
-        .addr           = omap2xxx_timer9_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
-        &omap2420_l4_core__timer9,
+        .flags          = HWMOD_16BIT_REG,
 };
 
-/* timer9 hwmod */
-static struct omap_hwmod omap2420_timer9_hwmod = {
-        .name           = "timer9",
-        .mpu_irqs       = omap2_timer9_mpu_irqs,
-        .main_clk       = "gpt9_fck",
+/* HDQ1W/1-wire */
+static struct omap_hwmod omap2420_hdq1w_hwmod = {
+        .name           = "hdq1w",
+        .mpu_irqs       = omap2_hdq1w_mpu_irqs,
+        .main_clk       = "hdq_fck",
         .prcm           = {
                 .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
                         .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_HDQ_SHIFT,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                        .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
                 },
         },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2420_timer9_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
+        .class          = &omap2_hdq1w_class,
 };
 
-/* timer10 */
-static struct omap_hwmod omap2420_timer10_hwmod;
+/*
+ * interfaces
+ */
 
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer10_hwmod,
-        .clk            = "gpt10_ick",
-        .addr           = omap2_timer10_addrs,
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2420_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap2_i2c1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* timer10 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
-        &omap2420_l4_core__timer10,
-};
-
-/* timer10 hwmod */
-static struct omap_hwmod omap2420_timer10_hwmod = {
-        .name           = "timer10",
-        .mpu_irqs       = omap2_timer10_mpu_irqs,
-        .main_clk       = "gpt10_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2420_timer10_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2420_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2_i2c2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* timer11 */
-static struct omap_hwmod omap2420_timer11_hwmod;
-
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer11_hwmod,
-        .clk            = "gpt11_ick",
-        .addr           = omap2_timer11_addrs,
+/* IVA <- L3 interface */
+static struct omap_hwmod_ocp_if omap2420_l3__iva = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2420_iva_hwmod,
+        .clk            = "core_l3_ck",
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* timer11 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
-        &omap2420_l4_core__timer11,
+/* DSP <- L3 interface */
+static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2420_dsp_hwmod,
+        .clk            = "dsp_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* timer11 hwmod */
-static struct omap_hwmod omap2420_timer11_hwmod = {
-        .name           = "timer11",
-        .mpu_irqs       = omap2_timer11_mpu_irqs,
-        .main_clk       = "gpt11_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
-                },
+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48028000,
+                .pa_end         = 0x48028000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
         },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2420_timer11_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
+        { }
 };
 
-/* timer12 */
-static struct omap_hwmod omap2420_timer12_hwmod;
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer12_hwmod,
-        .clk            = "gpt12_ick",
-        .addr           = omap2xxx_timer12_addrs,
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2420_timer1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
-        &omap2420_l4_core__timer12,
-};
-
-/* timer12 hwmod */
-static struct omap_hwmod omap2420_timer12_hwmod = {
-        .name           = "timer12",
-        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
-        .main_clk       = "gpt12_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2420_timer12_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
         {
@@ -744,363 +368,13 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
-        .master         = &omap2420_l4_wkup_hwmod,
-        .slave          = &omap2420_wd_timer2_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_wd_timer2_hwmod,
         .clk            = "mpu_wdt_ick",
         .addr           = omap2420_wd_timer2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
-        &omap2420_l4_wkup__wd_timer2,
-};
-
-static struct omap_hwmod omap2420_wd_timer2_hwmod = {
-        .name           = "wd_timer2",
-        .class          = &omap2xxx_wd_timer_hwmod_class,
-        .main_clk       = "mpu_wdt_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
-                },
-        },
-        .slaves         = omap2420_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
-};
-
-/* UART1 */
-
-static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
-        &omap2_l4_core__uart1,
-};
-
-static struct omap_hwmod omap2420_uart1_hwmod = {
-        .name           = "uart1",
-        .mpu_irqs       = omap2_uart1_mpu_irqs,
-        .sdma_reqs      = omap2_uart1_sdma_reqs,
-        .main_clk       = "uart1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
-                },
-        },
-        .slaves         = omap2420_uart1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
-        .class          = &omap2_uart_class,
-};
-
-/* UART2 */
-
-static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
-        &omap2_l4_core__uart2,
-};
-
-static struct omap_hwmod omap2420_uart2_hwmod = {
-        .name           = "uart2",
-        .mpu_irqs       = omap2_uart2_mpu_irqs,
-        .sdma_reqs      = omap2_uart2_sdma_reqs,
-        .main_clk       = "uart2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
-                },
-        },
-        .slaves         = omap2420_uart2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
-        .class          = &omap2_uart_class,
-};
-
-/* UART3 */
-
-static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
-        &omap2_l4_core__uart3,
-};
-
-static struct omap_hwmod omap2420_uart3_hwmod = {
-        .name           = "uart3",
-        .mpu_irqs       = omap2_uart3_mpu_irqs,
-        .sdma_reqs      = omap2_uart3_sdma_reqs,
-        .main_clk       = "uart3_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 2,
-                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
-                        .idlest_reg_id = 2,
-                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
-                },
-        },
-        .slaves         = omap2420_uart3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
-        .class          = &omap2_uart_class,
-};
-
-/* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
-        &omap2420_dss__l3,
-};
-
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_dss_core_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
-        &omap2420_l4_core__dss,
-};
-
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-        /*
-         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
-         * driver does not use these clocks.
-         */
-        { .role = "tv_clk", .clk = "dss_54m_fck" },
-        { .role = "sys_clk", .clk = "dss2_fck" },
-};
-
-static struct omap_hwmod omap2420_dss_core_hwmod = {
-        .name           = "dss_core",
-        .class          = &omap2_dss_hwmod_class,
-        .main_clk       = "dss1_fck", /* instead of dss_fck */
-        .sdma_reqs      = omap2xxx_dss_sdma_chs,
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-                },
-        },
-        .opt_clks       = dss_opt_clks,
-        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap2420_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
-        .masters        = omap2420_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
-        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_dss_dispc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_dispc_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
-        &omap2420_l4_core__dss_dispc,
-};
-
-static struct omap_hwmod omap2420_dss_dispc_hwmod = {
-        .name           = "dss_dispc",
-        .class          = &omap2_dispc_hwmod_class,
-        .mpu_irqs       = omap2_dispc_irqs,
-        .main_clk       = "dss1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_dss_dispc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-        .dev_attr       = &omap2_3_dss_dispc_dev_attr
-};
-
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_dss_rfbi_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_rfbi_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
-        &omap2420_l4_core__dss_rfbi,
-};
-
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
-        { .role = "ick", .clk = "dss_ick" },
-};
-
-static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
-        .name           = "dss_rfbi",
-        .class          = &omap2_rfbi_hwmod_class,
-        .main_clk       = "dss1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                },
-        },
-        .opt_clks       = dss_rfbi_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
-        .slaves         = omap2420_dss_rfbi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_dss_venc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_venc_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
-        &omap2420_l4_core__dss_venc,
-};
-
-static struct omap_hwmod omap2420_dss_venc_hwmod = {
-        .name           = "dss_venc",
-        .class          = &omap2_venc_hwmod_class,
-        .main_clk       = "dss_54m_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                },
-        },
-        .slaves         = omap2420_dss_venc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
-        .rev_offs       = 0x00,
-        .sysc_offs      = 0x20,
-        .syss_offs      = 0x10,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class i2c_class = {
-        .name           = "i2c",
-        .sysc           = &i2c_sysc,
-        .rev            = OMAP_I2C_IP_VERSION_1,
-        .reset          = &omap_i2c_reset,
-};
-
-static struct omap_i2c_dev_attr i2c_dev_attr = {
-        .flags          = OMAP_I2C_FLAG_NO_FIFO |
-                          OMAP_I2C_FLAG_SIMPLE_CLOCK |
-                          OMAP_I2C_FLAG_16BIT_DATA_REG |
-                          OMAP_I2C_FLAG_BUS_SHIFT_2,
-};
-
-/* I2C1 */
-
-static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
-        &omap2420_l4_core__i2c1,
-};
-
-static struct omap_hwmod omap2420_i2c1_hwmod = {
-        .name           = "i2c1",
-        .mpu_irqs       = omap2_i2c1_mpu_irqs,
-        .sdma_reqs      = omap2_i2c1_sdma_reqs,
-        .main_clk       = "i2c1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP2420_EN_I2C1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
-                },
-        },
-        .slaves         = omap2420_i2c1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
-        .class          = &i2c_class,
-        .dev_attr       = &i2c_dev_attr,
-        .flags          = HWMOD_16BIT_REG,
-};
-
-/* I2C2 */
-
-static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
-        &omap2420_l4_core__i2c2,
-};
-
-static struct omap_hwmod omap2420_i2c2_hwmod = {
-        .name           = "i2c2",
-        .mpu_irqs       = omap2_i2c2_mpu_irqs,
-        .sdma_reqs      = omap2_i2c2_sdma_reqs,
-        .main_clk       = "i2c2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP2420_EN_I2C2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
-                },
-        },
-        .slaves         = omap2420_i2c2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
-        .class          = &i2c_class,
-        .dev_attr       = &i2c_dev_attr,
-        .flags          = HWMOD_16BIT_REG,
-};
-
 /* l4_wkup -> gpio1 */
 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
         {
@@ -1112,8 +386,8 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
-        .master         = &omap2420_l4_wkup_hwmod,
-        .slave          = &omap2420_gpio1_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio1_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2420_gpio1_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1130,8 +404,8 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
-        .master         = &omap2420_l4_wkup_hwmod,
-        .slave          = &omap2420_gpio2_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio2_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2420_gpio2_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1148,8 +422,8 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
-        .master         = &omap2420_l4_wkup_hwmod,
-        .slave          = &omap2420_gpio3_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio3_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2420_gpio3_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1166,408 +440,150 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
 };
 
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
-        .master         = &omap2420_l4_wkup_hwmod,
-        .slave          = &omap2420_gpio4_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio4_hwmod,
         .clk            = "gpios_ick",
         .addr           = omap2420_gpio4_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
-        .bank_width = 32,
-        .dbck_flag = false,
-};
-
-/* gpio1 */
-static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
-        &omap2420_l4_wkup__gpio1,
-};
-
-static struct omap_hwmod omap2420_gpio1_hwmod = {
-        .name           = "gpio1",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio1_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_gpio1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpio2 */
-static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
-        &omap2420_l4_wkup__gpio2,
-};
-
-static struct omap_hwmod omap2420_gpio2_hwmod = {
-        .name           = "gpio2",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio2_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_gpio2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpio3 */
-static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
-        &omap2420_l4_wkup__gpio3,
-};
-
-static struct omap_hwmod omap2420_gpio3_hwmod = {
-        .name           = "gpio3",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio3_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_gpio3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpio4 */
-static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
-        &omap2420_l4_wkup__gpio4,
-};
-
-static struct omap_hwmod omap2420_gpio4_hwmod = {
-        .name           = "gpio4",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio4_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_gpio4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
-        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
-                                                IS_CSSA_32 | IS_CDSA_32,
-        .lch_count = 32,
-};
-
 /* dma_system -> L3 */
 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
         .master         = &omap2420_dma_system_hwmod,
-        .slave          = &omap2420_l3_main_hwmod,
+        .slave          = &omap2xxx_l3_main_hwmod,
         .clk            = "core_l3_ck",
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
-        &omap2420_dma_system__l3,
-};
-
 /* l4_core -> dma_system */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_dma_system_hwmod,
         .clk            = "sdma_ick",
         .addr           = omap2_dma_system_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
-        &omap2420_l4_core__dma_system,
-};
-
-static struct omap_hwmod omap2420_dma_system_hwmod = {
-        .name           = "dma",
-        .class          = &omap2xxx_dma_hwmod_class,
-        .mpu_irqs       = omap2_dma_system_irqs,
-        .main_clk       = "core_l3_ck",
-        .slaves         = omap2420_dma_system_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
-        .masters        = omap2420_dma_system_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
-        .dev_attr       = &dma_dev_attr,
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-/* mailbox */
-static struct omap_hwmod omap2420_mailbox_hwmod;
-static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
-        { .name = "dsp", .irq = 26 },
-        { .name = "iva", .irq = 34 },
-        { .irq = -1 }
-};
-
 /* l4_core -> mailbox */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_mailbox_hwmod,
         .addr           = omap2_mailbox_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
-        &omap2420_l4_core__mailbox,
-};
-
-static struct omap_hwmod omap2420_mailbox_hwmod = {
-        .name           = "mailbox",
-        .class          = &omap2xxx_mailbox_hwmod_class,
-        .mpu_irqs       = omap2420_mailbox_irqs,
-        .main_clk       = "mailboxes_ick",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
-                },
-        },
-        .slaves         = omap2420_mailbox_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
-};
-
-/* mcspi1 */
-static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
-        &omap2420_l4_core__mcspi1,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
-        .num_chipselect = 4,
-};
-
-static struct omap_hwmod omap2420_mcspi1_hwmod = {
-        .name           = "mcspi1_hwmod",
-        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
-        .main_clk       = "mcspi1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
-                },
-        },
-        .slaves         = omap2420_mcspi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
-        .class          = &omap2xxx_mcspi_class,
-        .dev_attr       = &omap_mcspi1_dev_attr,
-};
-
-/* mcspi2 */
-static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
-        &omap2420_l4_core__mcspi2,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
-        .num_chipselect = 2,
-};
-
-static struct omap_hwmod omap2420_mcspi2_hwmod = {
-        .name           = "mcspi2_hwmod",
-        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
-        .main_clk       = "mcspi2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
-                },
-        },
-        .slaves         = omap2420_mcspi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
-        .class          = &omap2xxx_mcspi_class,
-        .dev_attr       = &omap_mcspi2_dev_attr,
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
-        .name = "mcbsp",
-};
-
-/* mcbsp1 */
-static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
-        { .name = "tx", .irq = 59 },
-        { .name = "rx", .irq = 60 },
-        { .irq = -1 }
-};
-
 /* l4_core -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_mcbsp1_hwmod,
         .clk            = "mcbsp1_ick",
         .addr           = omap2_mcbsp1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
-        &omap2420_l4_core__mcbsp1,
-};
-
-static struct omap_hwmod omap2420_mcbsp1_hwmod = {
-        .name           = "mcbsp1",
-        .class          = &omap2420_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2420_mcbsp1_irqs,
-        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
-        .main_clk       = "mcbsp1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
-                },
-        },
-        .slaves         = omap2420_mcbsp1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
-        { .name = "tx", .irq = 62 },
-        { .name = "rx", .irq = 63 },
-        { .irq = -1 }
-};
-
 /* l4_core -> mcbsp2 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
         .slave          = &omap2420_mcbsp2_hwmod,
         .clk            = "mcbsp2_ick",
         .addr           = omap2xxx_mcbsp2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
-        &omap2420_l4_core__mcbsp2,
-};
-
-static struct omap_hwmod omap2420_mcbsp2_hwmod = {
-        .name           = "mcbsp2",
-        .class          = &omap2420_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2420_mcbsp2_irqs,
-        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
-        .main_clk       = "mcbsp2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
-                },
+static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c000 + SZ_128 - 1,
+                .flags          = ADDR_TYPE_RT,
         },
-        .slaves         = omap2420_mcbsp2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
+        { }
 };
 
-static __initdata struct omap_hwmod *omap2420_hwmods[] = {
-        &omap2420_l3_main_hwmod,
-        &omap2420_l4_core_hwmod,
-        &omap2420_l4_wkup_hwmod,
-        &omap2420_mpu_hwmod,
-        &omap2420_iva_hwmod,
-
-        &omap2420_timer1_hwmod,
-        &omap2420_timer2_hwmod,
-        &omap2420_timer3_hwmod,
-        &omap2420_timer4_hwmod,
-        &omap2420_timer5_hwmod,
-        &omap2420_timer6_hwmod,
-        &omap2420_timer7_hwmod,
-        &omap2420_timer8_hwmod,
-        &omap2420_timer9_hwmod,
-        &omap2420_timer10_hwmod,
-        &omap2420_timer11_hwmod,
-        &omap2420_timer12_hwmod,
-
-        &omap2420_wd_timer2_hwmod,
-        &omap2420_uart1_hwmod,
-        &omap2420_uart2_hwmod,
-        &omap2420_uart3_hwmod,
-        /* dss class */
-        &omap2420_dss_core_hwmod,
-        &omap2420_dss_dispc_hwmod,
-        &omap2420_dss_rfbi_hwmod,
-        &omap2420_dss_venc_hwmod,
-        /* i2c class */
-        &omap2420_i2c1_hwmod,
-        &omap2420_i2c2_hwmod,
+/* l4_core -> msdi1 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2420_msdi1_hwmod,
+        .clk            = "mmc_ick",
+        .addr           = omap2420_msdi1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 
-        /* gpio class */
-        &omap2420_gpio1_hwmod,
-        &omap2420_gpio2_hwmod,
-        &omap2420_gpio3_hwmod,
-        &omap2420_gpio4_hwmod,
+/* l4_core -> hdq1w interface */
+static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2420_hdq1w_hwmod,
+        .clk            = "hdq_ick",
+        .addr           = omap2_hdq1w_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
+};
 
-        /* dma_system class*/
-        &omap2420_dma_system_hwmod,
 
-        /* mailbox class */
-        &omap2420_mailbox_hwmod,
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
+        {
+                .pa_start       = 0x48004000,
+                .pa_end         = 0x4800401f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
 
-        /* mcbsp class */
-        &omap2420_mcbsp1_hwmod,
-        &omap2420_mcbsp2_hwmod,
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_counter_32k_hwmod,
+        .clk            = "sync_32k_ick",
+        .addr           = omap2420_counter_32k_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 
-        /* mcspi class */
-        &omap2420_mcspi1_hwmod,
-        &omap2420_mcspi2_hwmod,
+static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
+        &omap2xxx_l3_main__l4_core,
+        &omap2xxx_mpu__l3_main,
+        &omap2xxx_dss__l3,
+        &omap2xxx_l4_core__mcspi1,
+        &omap2xxx_l4_core__mcspi2,
+        &omap2xxx_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
+        &omap2420_l4_core__i2c1,
+        &omap2420_l4_core__i2c2,
+        &omap2420_l3__iva,
+        &omap2420_l3__dsp,
+        &omap2420_l4_wkup__timer1,
+        &omap2xxx_l4_core__timer2,
+        &omap2xxx_l4_core__timer3,
+        &omap2xxx_l4_core__timer4,
+        &omap2xxx_l4_core__timer5,
+        &omap2xxx_l4_core__timer6,
+        &omap2xxx_l4_core__timer7,
+        &omap2xxx_l4_core__timer8,
+        &omap2xxx_l4_core__timer9,
+        &omap2xxx_l4_core__timer10,
+        &omap2xxx_l4_core__timer11,
+        &omap2xxx_l4_core__timer12,
+        &omap2420_l4_wkup__wd_timer2,
+        &omap2xxx_l4_core__dss,
+        &omap2xxx_l4_core__dss_dispc,
+        &omap2xxx_l4_core__dss_rfbi,
+        &omap2xxx_l4_core__dss_venc,
+        &omap2420_l4_wkup__gpio1,
+        &omap2420_l4_wkup__gpio2,
+        &omap2420_l4_wkup__gpio3,
+        &omap2420_l4_wkup__gpio4,
+        &omap2420_dma_system__l3,
+        &omap2420_l4_core__dma_system,
+        &omap2420_l4_core__mailbox,
+        &omap2420_l4_core__mcbsp1,
+        &omap2420_l4_core__mcbsp2,
+        &omap2420_l4_core__msdi1,
+        &omap2420_l4_core__hdq1w,
+        &omap2420_l4_wkup__counter_32k,
         NULL,
 };
 
 int __init omap2420_hwmod_init(void)
 {
-        return omap_hwmod_register(omap2420_hwmods);
+        return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 04a3885f4475..4d7264981230 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -2,6 +2,7 @@
  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
  *
  * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -33,1044 +34,29 @@
 /*
  * OMAP2430 hardware module integration data
  *
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
  * TI hardware database or other technical documentation.  Data that
  * is driver-specific or driver-kernel integration-specific belongs
  * elsewhere.
  */
 
-static struct omap_hwmod omap2430_mpu_hwmod;
-static struct omap_hwmod omap2430_iva_hwmod;
-static struct omap_hwmod omap2430_l3_main_hwmod;
-static struct omap_hwmod omap2430_l4_core_hwmod;
-static struct omap_hwmod omap2430_dss_core_hwmod;
-static struct omap_hwmod omap2430_dss_dispc_hwmod;
-static struct omap_hwmod omap2430_dss_rfbi_hwmod;
-static struct omap_hwmod omap2430_dss_venc_hwmod;
-static struct omap_hwmod omap2430_wd_timer2_hwmod;
-static struct omap_hwmod omap2430_gpio1_hwmod;
-static struct omap_hwmod omap2430_gpio2_hwmod;
-static struct omap_hwmod omap2430_gpio3_hwmod;
-static struct omap_hwmod omap2430_gpio4_hwmod;
-static struct omap_hwmod omap2430_gpio5_hwmod;
-static struct omap_hwmod omap2430_dma_system_hwmod;
-static struct omap_hwmod omap2430_mcbsp1_hwmod;
-static struct omap_hwmod omap2430_mcbsp2_hwmod;
-static struct omap_hwmod omap2430_mcbsp3_hwmod;
-static struct omap_hwmod omap2430_mcbsp4_hwmod;
-static struct omap_hwmod omap2430_mcbsp5_hwmod;
-static struct omap_hwmod omap2430_mcspi1_hwmod;
-static struct omap_hwmod omap2430_mcspi2_hwmod;
-static struct omap_hwmod omap2430_mcspi3_hwmod;
-static struct omap_hwmod omap2430_mmc1_hwmod;
-static struct omap_hwmod omap2430_mmc2_hwmod;
-
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
-        .master = &omap2430_l3_main_hwmod,
-        .slave  = &omap2430_l4_core_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
-        .master = &omap2430_mpu_hwmod,
-        .slave  = &omap2430_l3_main_hwmod,
-        .user   = OCP_USER_MPU,
-};
-
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
-        &omap2430_mpu__l3_main,
-};
-
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
-        .master         = &omap2430_dss_core_hwmod,
-        .slave          = &omap2430_l3_main_hwmod,
-        .fw = {
-                .omap2 = {
-                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
-                        .flags  = OMAP_FIREWALL_L3,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
-        &omap2430_l3_main__l4_core,
-};
-
-/* L3 */
-static struct omap_hwmod omap2430_l3_main_hwmod = {
-        .name           = "l3_main",
-        .class          = &l3_hwmod_class,
-        .masters        = omap2430_l3_main_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
-        .slaves         = omap2430_l3_main_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod omap2430_l4_wkup_hwmod;
-static struct omap_hwmod omap2430_uart1_hwmod;
-static struct omap_hwmod omap2430_uart2_hwmod;
-static struct omap_hwmod omap2430_uart3_hwmod;
-static struct omap_hwmod omap2430_i2c1_hwmod;
-static struct omap_hwmod omap2430_i2c2_hwmod;
-
-static struct omap_hwmod omap2430_usbhsotg_hwmod;
-
-/* l3_core -> usbhsotg  interface */
-static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
-        .master         = &omap2430_usbhsotg_hwmod,
-        .slave          = &omap2430_l3_main_hwmod,
-        .clk            = "core_l3_ck",
-        .user           = OCP_USER_MPU,
-};
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_i2c1_hwmod,
-        .clk            = "i2c1_ick",
-        .addr           = omap2_i2c1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_i2c2_hwmod,
-        .clk            = "i2c2_ick",
-        .addr           = omap2_i2c2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
-        .master = &omap2430_l4_core_hwmod,
-        .slave  = &omap2430_l4_wkup_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_uart1_hwmod,
-        .clk            = "uart1_ick",
-        .addr           = omap2xxx_uart1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_uart2_hwmod,
-        .clk            = "uart2_ick",
-        .addr           = omap2xxx_uart2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_uart3_hwmod,
-        .clk            = "uart3_ick",
-        .addr           = omap2xxx_uart3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/*
-* usbhsotg interface data
-*/
-static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
-        {
-                .pa_start       = OMAP243X_HS_BASE,
-                .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/*  l4_core ->usbhsotg  interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_usbhsotg_hwmod,
-        .clk            = "usb_l4_ick",
-        .addr           = omap2430_usbhsotg_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
-        &omap2430_usbhsotg__l3,
-};
-
-static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
-        &omap2430_l4_core__usbhsotg,
-};
-
-/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mmc1_hwmod,
-        .clk            = "mmchs1_ick",
-        .addr           = omap2430_mmc1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mmc2_hwmod,
-        .clk            = "mmchs2_ick",
-        .addr           = omap2430_mmc2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
-        &omap2430_l3_main__l4_core,
-};
-
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
-        &omap2430_l4_core__l4_wkup,
-        &omap2430_l4_core__mmc1,
-        &omap2430_l4_core__mmc2,
-};
-
-/* L4 CORE */
-static struct omap_hwmod omap2430_l4_core_hwmod = {
-        .name           = "l4_core",
-        .class          = &l4_hwmod_class,
-        .masters        = omap2430_l4_core_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
-        .slaves         = omap2430_l4_core_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
-        &omap2430_l4_core__l4_wkup,
-        &omap2_l4_core__uart1,
-        &omap2_l4_core__uart2,
-        &omap2_l4_core__uart3,
-};
-
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
-};
-
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcspi1_hwmod,
-        .clk            = "mcspi1_ick",
-        .addr           = omap2_mcspi1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcspi2_hwmod,
-        .clk            = "mcspi2_ick",
-        .addr           = omap2_mcspi2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcspi3_hwmod,
-        .clk            = "mcspi3_ick",
-        .addr           = omap2430_mcspi3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 WKUP */
-static struct omap_hwmod omap2430_l4_wkup_hwmod = {
-        .name           = "l4_wkup",
-        .class          = &l4_hwmod_class,
-        .masters        = omap2430_l4_wkup_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
-        .slaves         = omap2430_l4_wkup_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
-        &omap2430_mpu__l3_main,
-};
-
-/* MPU */
-static struct omap_hwmod omap2430_mpu_hwmod = {
-        .name           = "mpu",
-        .class          = &mpu_hwmod_class,
-        .main_clk       = "mpu_ck",
-        .masters        = omap2430_mpu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
-};
-
 /*
- * IVA2_1 interface data
+ * IP blocks
  */
 
-/* IVA2 <- L3 interface */
-static struct omap_hwmod_ocp_if omap2430_l3__iva = {
-        .master         = &omap2430_l3_main_hwmod,
-        .slave          = &omap2430_iva_hwmod,
-        .clk            = "dsp_fck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
-        &omap2430_l3__iva,
+/* IVA2 (IVA2) */
+static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
+        { .name = "logic", .rst_shift = 0 },
+        { .name = "mmu", .rst_shift = 1 },
 };
 
-/*
- * IVA2 (IVA2)
- */
-
 static struct omap_hwmod omap2430_iva_hwmod = {
         .name           = "iva",
         .class          = &iva_hwmod_class,
-        .masters        = omap2430_iva_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
-};
-
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
-        .timer_capability       = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
-        .timer_capability       = OMAP_TIMER_HAS_PWM,
-};
-
-/* timer1 */
-static struct omap_hwmod omap2430_timer1_hwmod;
-
-static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
-        {
-                .pa_start       = 0x49018000,
-                .pa_end         = 0x49018000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_timer1_hwmod,
-        .clk            = "gpt1_ick",
-        .addr           = omap2430_timer1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer1 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
-        &omap2430_l4_wkup__timer1,
-};
-
-/* timer1 hwmod */
-static struct omap_hwmod omap2430_timer1_hwmod = {
-        .name           = "timer1",
-        .mpu_irqs       = omap2_timer1_mpu_irqs,
-        .main_clk       = "gpt1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer2 */
-static struct omap_hwmod omap2430_timer2_hwmod;
-
-/* l4_core -> timer2 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer2_hwmod,
-        .clk            = "gpt2_ick",
-        .addr           = omap2xxx_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer2 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
-        &omap2430_l4_core__timer2,
-};
-
-/* timer2 hwmod */
-static struct omap_hwmod omap2430_timer2_hwmod = {
-        .name           = "timer2",
-        .mpu_irqs       = omap2_timer2_mpu_irqs,
-        .main_clk       = "gpt2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer3 */
-static struct omap_hwmod omap2430_timer3_hwmod;
-
-/* l4_core -> timer3 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer3_hwmod,
-        .clk            = "gpt3_ick",
-        .addr           = omap2xxx_timer3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
-        &omap2430_l4_core__timer3,
-};
-
-/* timer3 hwmod */
-static struct omap_hwmod omap2430_timer3_hwmod = {
-        .name           = "timer3",
-        .mpu_irqs       = omap2_timer3_mpu_irqs,
-        .main_clk       = "gpt3_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer4 */
-static struct omap_hwmod omap2430_timer4_hwmod;
-
-/* l4_core -> timer4 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer4_hwmod,
-        .clk            = "gpt4_ick",
-        .addr           = omap2xxx_timer4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer4 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
-        &omap2430_l4_core__timer4,
-};
-
-/* timer4 hwmod */
-static struct omap_hwmod omap2430_timer4_hwmod = {
-        .name           = "timer4",
-        .mpu_irqs       = omap2_timer4_mpu_irqs,
-        .main_clk       = "gpt4_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer5 */
-static struct omap_hwmod omap2430_timer5_hwmod;
-
-/* l4_core -> timer5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer5_hwmod,
-        .clk            = "gpt5_ick",
-        .addr           = omap2xxx_timer5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer5 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
-        &omap2430_l4_core__timer5,
-};
-
-/* timer5 hwmod */
-static struct omap_hwmod omap2430_timer5_hwmod = {
-        .name           = "timer5",
-        .mpu_irqs       = omap2_timer5_mpu_irqs,
-        .main_clk       = "gpt5_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer6 */
-static struct omap_hwmod omap2430_timer6_hwmod;
-
-/* l4_core -> timer6 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer6_hwmod,
-        .clk            = "gpt6_ick",
-        .addr           = omap2xxx_timer6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
-        &omap2430_l4_core__timer6,
-};
-
-/* timer6 hwmod */
-static struct omap_hwmod omap2430_timer6_hwmod = {
-        .name           = "timer6",
-        .mpu_irqs       = omap2_timer6_mpu_irqs,
-        .main_clk       = "gpt6_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer7 */
-static struct omap_hwmod omap2430_timer7_hwmod;
-
-/* l4_core -> timer7 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer7_hwmod,
-        .clk            = "gpt7_ick",
-        .addr           = omap2xxx_timer7_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
-        &omap2430_l4_core__timer7,
-};
-
-/* timer7 hwmod */
-static struct omap_hwmod omap2430_timer7_hwmod = {
-        .name           = "timer7",
-        .mpu_irqs       = omap2_timer7_mpu_irqs,
-        .main_clk       = "gpt7_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer7_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer8 */
-static struct omap_hwmod omap2430_timer8_hwmod;
-
-/* l4_core -> timer8 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer8_hwmod,
-        .clk            = "gpt8_ick",
-        .addr           = omap2xxx_timer8_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer8 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
-        &omap2430_l4_core__timer8,
-};
-
-/* timer8 hwmod */
-static struct omap_hwmod omap2430_timer8_hwmod = {
-        .name           = "timer8",
-        .mpu_irqs       = omap2_timer8_mpu_irqs,
-        .main_clk       = "gpt8_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer8_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer9 */
-static struct omap_hwmod omap2430_timer9_hwmod;
-
-/* l4_core -> timer9 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer9_hwmod,
-        .clk            = "gpt9_ick",
-        .addr           = omap2xxx_timer9_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
-        &omap2430_l4_core__timer9,
-};
-
-/* timer9 hwmod */
-static struct omap_hwmod omap2430_timer9_hwmod = {
-        .name           = "timer9",
-        .mpu_irqs       = omap2_timer9_mpu_irqs,
-        .main_clk       = "gpt9_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2430_timer9_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer10 */
-static struct omap_hwmod omap2430_timer10_hwmod;
-
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer10_hwmod,
-        .clk            = "gpt10_ick",
-        .addr           = omap2_timer10_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer10 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
-        &omap2430_l4_core__timer10,
-};
-
-/* timer10 hwmod */
-static struct omap_hwmod omap2430_timer10_hwmod = {
-        .name           = "timer10",
-        .mpu_irqs       = omap2_timer10_mpu_irqs,
-        .main_clk       = "gpt10_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2430_timer10_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer11 */
-static struct omap_hwmod omap2430_timer11_hwmod;
-
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer11_hwmod,
-        .clk            = "gpt11_ick",
-        .addr           = omap2_timer11_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer11 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
-        &omap2430_l4_core__timer11,
-};
-
-/* timer11 hwmod */
-static struct omap_hwmod omap2430_timer11_hwmod = {
-        .name           = "timer11",
-        .mpu_irqs       = omap2_timer11_mpu_irqs,
-        .main_clk       = "gpt11_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2430_timer11_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* timer12 */
-static struct omap_hwmod omap2430_timer12_hwmod;
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer12_hwmod,
-        .clk            = "gpt12_ick",
-        .addr           = omap2xxx_timer12_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
-        &omap2430_l4_core__timer12,
-};
-
-/* timer12 hwmod */
-static struct omap_hwmod omap2430_timer12_hwmod = {
-        .name           = "timer12",
-        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
-        .main_clk       = "gpt12_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2430_timer12_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x49016000,
-                .pa_end         = 0x4901607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_wd_timer2_hwmod,
-        .clk            = "mpu_wdt_ick",
-        .addr           = omap2430_wd_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
-        &omap2430_l4_wkup__wd_timer2,
-};
-
-static struct omap_hwmod omap2430_wd_timer2_hwmod = {
-        .name           = "wd_timer2",
-        .class          = &omap2xxx_wd_timer_hwmod_class,
-        .main_clk       = "mpu_wdt_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
-                },
-        },
-        .slaves         = omap2430_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
-};
-
-/* UART1 */
-
-static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
-        &omap2_l4_core__uart1,
-};
-
-static struct omap_hwmod omap2430_uart1_hwmod = {
-        .name           = "uart1",
-        .mpu_irqs       = omap2_uart1_mpu_irqs,
-        .sdma_reqs      = omap2_uart1_sdma_reqs,
-        .main_clk       = "uart1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
-                },
-        },
-        .slaves         = omap2430_uart1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
-        .class          = &omap2_uart_class,
-};
-
-/* UART2 */
-
-static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
-        &omap2_l4_core__uart2,
-};
-
-static struct omap_hwmod omap2430_uart2_hwmod = {
-        .name           = "uart2",
-        .mpu_irqs       = omap2_uart2_mpu_irqs,
-        .sdma_reqs      = omap2_uart2_sdma_reqs,
-        .main_clk       = "uart2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
-                },
-        },
-        .slaves         = omap2430_uart2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
-        .class          = &omap2_uart_class,
-};
-
-/* UART3 */
-
-static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
-        &omap2_l4_core__uart3,
-};
-
-static struct omap_hwmod omap2430_uart3_hwmod = {
-        .name           = "uart3",
-        .mpu_irqs       = omap2_uart3_mpu_irqs,
-        .sdma_reqs      = omap2_uart3_sdma_reqs,
-        .main_clk       = "uart3_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 2,
-                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
-                        .idlest_reg_id = 2,
-                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
-                },
-        },
-        .slaves         = omap2430_uart3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
-        .class          = &omap2_uart_class,
-};
-
-/* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
-        &omap2430_dss__l3,
-};
-
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dss_core_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
-        &omap2430_l4_core__dss,
-};
-
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-        /*
-         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
-         * driver does not use these clocks.
-         */
-        { .role = "tv_clk", .clk = "dss_54m_fck" },
-        { .role = "sys_clk", .clk = "dss2_fck" },
-};
-
-static struct omap_hwmod omap2430_dss_core_hwmod = {
-        .name           = "dss_core",
-        .class          = &omap2_dss_hwmod_class,
-        .main_clk       = "dss1_fck", /* instead of dss_fck */
-        .sdma_reqs      = omap2xxx_dss_sdma_chs,
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-                },
-        },
-        .opt_clks       = dss_opt_clks,
-        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap2430_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
-        .masters        = omap2430_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
-        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dss_dispc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_dispc_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
-        &omap2430_l4_core__dss_dispc,
-};
-
-static struct omap_hwmod omap2430_dss_dispc_hwmod = {
-        .name           = "dss_dispc",
-        .class          = &omap2_dispc_hwmod_class,
-        .mpu_irqs       = omap2_dispc_irqs,
-        .main_clk       = "dss1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_dss_dispc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-        .dev_attr       = &omap2_3_dss_dispc_dev_attr
-};
-
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dss_rfbi_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_rfbi_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
-        &omap2430_l4_core__dss_rfbi,
-};
-
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
-        { .role = "ick", .clk = "dss_ick" },
-};
-
-static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
-        .name           = "dss_rfbi",
-        .class          = &omap2_rfbi_hwmod_class,
-        .main_clk       = "dss1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                },
-        },
-        .opt_clks       = dss_rfbi_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
-        .slaves         = omap2430_dss_rfbi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dss_venc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_venc_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
-        &omap2430_l4_core__dss_venc,
-};
-
-static struct omap_hwmod omap2430_dss_venc_hwmod = {
-        .name           = "dss_venc",
-        .class          = &omap2_venc_hwmod_class,
-        .main_clk       = "dss_54m_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                },
-        },
-        .slaves         = omap2430_dss_venc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
-        .flags          = HWMOD_NO_IDLEST,
+        .clkdm_name     = "dsp_clkdm",
+        .rst_lines      = omap2430_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap2430_iva_resets),
+        .main_clk       = "dsp_fck",
 };
 
 /* I2C common */
@@ -1098,11 +84,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 };
 
 /* I2C1 */
-
-static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
-        &omap2430_l4_core__i2c1,
-};
-
 static struct omap_hwmod omap2430_i2c1_hwmod = {
         .name           = "i2c1",
         .flags          = HWMOD_16BIT_REG,
@@ -1126,18 +107,11 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
                 },
         },
-        .slaves         = omap2430_i2c1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c_dev_attr,
 };
 
 /* I2C2 */
-
-static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
-        &omap2430_l4_core__i2c2,
-};
-
 static struct omap_hwmod omap2430_i2c2_hwmod = {
         .name           = "i2c2",
         .flags          = HWMOD_16BIT_REG,
@@ -1153,218 +127,16 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
                 },
         },
-        .slaves         = omap2430_i2c2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c_dev_attr,
 };
 
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
-        {
-                .pa_start       = 0x4900C000,
-                .pa_end         = 0x4900C1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_gpio1_hwmod,
-        .clk            = "gpios_ick",
-        .addr           = omap2430_gpio1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio2 */
-static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
-        {
-                .pa_start       = 0x4900E000,
-                .pa_end         = 0x4900E1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_gpio2_hwmod,
-        .clk            = "gpios_ick",
-        .addr           = omap2430_gpio2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio3 */
-static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
-        {
-                .pa_start       = 0x49010000,
-                .pa_end         = 0x490101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_gpio3_hwmod,
-        .clk            = "gpios_ick",
-        .addr           = omap2430_gpio3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> gpio4 */
-static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
-        {
-                .pa_start       = 0x49012000,
-                .pa_end         = 0x490121ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_gpio4_hwmod,
-        .clk            = "gpios_ick",
-        .addr           = omap2430_gpio4_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> gpio5 */
-static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
-        {
-                .pa_start       = 0x480B6000,
-                .pa_end         = 0x480B61ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_gpio5_hwmod,
-        .clk            = "gpio5_ick",
-        .addr           = omap2430_gpio5_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
-        .bank_width = 32,
-        .dbck_flag = false,
-};
-
-/* gpio1 */
-static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
-        &omap2430_l4_wkup__gpio1,
-};
-
-static struct omap_hwmod omap2430_gpio1_hwmod = {
-        .name           = "gpio1",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio1_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_gpio1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpio2 */
-static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
-        &omap2430_l4_wkup__gpio2,
-};
-
-static struct omap_hwmod omap2430_gpio2_hwmod = {
-        .name           = "gpio2",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio2_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_gpio2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpio3 */
-static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
-        &omap2430_l4_wkup__gpio3,
-};
-
-static struct omap_hwmod omap2430_gpio3_hwmod = {
-        .name           = "gpio3",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio3_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_gpio3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-
-/* gpio4 */
-static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
-        &omap2430_l4_wkup__gpio4,
-};
-
-static struct omap_hwmod omap2430_gpio4_hwmod = {
-        .name           = "gpio4",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio4_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_gpio4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-
 /* gpio5 */
 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
         { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
         { .irq = -1 }
 };
 
-static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
-        &omap2430_l4_core__gpio5,
-};
-
 static struct omap_hwmod omap2430_gpio5_hwmod = {
         .name           = "gpio5",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1379,10 +151,8 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
                 },
         },
-        .slaves         = omap2430_gpio5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
         .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
 };
 
 /* dma attributes */
@@ -1392,66 +162,21 @@ static struct omap_dma_dev_attr dma_dev_attr = {
         .lch_count = 32,
 };
 
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
-        .master         = &omap2430_dma_system_hwmod,
-        .slave          = &omap2430_l3_main_hwmod,
-        .clk            = "core_l3_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
-        &omap2430_dma_system__l3,
-};
-
-/* l4_core -> dma_system */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dma_system_hwmod,
-        .clk            = "sdma_ick",
-        .addr           = omap2_dma_system_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
-        &omap2430_l4_core__dma_system,
-};
-
 static struct omap_hwmod omap2430_dma_system_hwmod = {
         .name           = "dma",
         .class          = &omap2xxx_dma_hwmod_class,
         .mpu_irqs       = omap2_dma_system_irqs,
         .main_clk       = "core_l3_ck",
-        .slaves         = omap2430_dma_system_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
-        .masters        = omap2430_dma_system_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
         .dev_attr       = &dma_dev_attr,
         .flags          = HWMOD_NO_IDLEST,
 };
 
 /* mailbox */
-static struct omap_hwmod omap2430_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
         { .irq = 26 },
         { .irq = -1 }
 };
 
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mailbox_hwmod,
-        .addr           = omap2_mailbox_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
-        &omap2430_l4_core__mailbox,
-};
-
 static struct omap_hwmod omap2430_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap2xxx_mailbox_hwmod_class,
@@ -1466,66 +191,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                 },
         },
-        .slaves         = omap2430_mailbox_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
-};
-
-/* mcspi1 */
-static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
-        &omap2430_l4_core__mcspi1,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
-        .num_chipselect = 4,
-};
-
-static struct omap_hwmod omap2430_mcspi1_hwmod = {
-        .name           = "mcspi1_hwmod",
-        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
-        .main_clk       = "mcspi1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
-                },
-        },
-        .slaves         = omap2430_mcspi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
-        .class          = &omap2xxx_mcspi_class,
-        .dev_attr       = &omap_mcspi1_dev_attr,
-};
-
-/* mcspi2 */
-static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
-        &omap2430_l4_core__mcspi2,
-};
-
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
-        .num_chipselect = 2,
-};
-
-static struct omap_hwmod omap2430_mcspi2_hwmod = {
-        .name           = "mcspi2_hwmod",
-        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
-        .main_clk       = "mcspi2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
-                },
-        },
-        .slaves         = omap2430_mcspi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
-        .class          = &omap2xxx_mcspi_class,
-        .dev_attr       = &omap_mcspi2_dev_attr,
 };
 
 /* mcspi3 */
@@ -1542,16 +207,12 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
-        &omap2430_l4_core__mcspi3,
-};
-
 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
         .num_chipselect = 2,
 };
 
 static struct omap_hwmod omap2430_mcspi3_hwmod = {
-        .name           = "mcspi3_hwmod",
+        .name           = "mcspi3",
         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
         .main_clk       = "mcspi3_fck",
@@ -1564,15 +225,11 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
                 },
         },
-        .slaves         = omap2430_mcspi3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
         .class          = &omap2xxx_mcspi_class,
         .dev_attr       = &omap_mcspi3_dev_attr,
 };
 
-/*
- * usbhsotg
- */
+/* usbhsotg */
 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
         .rev_offs       = 0x0400,
         .sysc_offs      = 0x0404,
@@ -1611,10 +268,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
                 },
         },
-        .masters        = omap2430_usbhsotg_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
-        .slaves         = omap2430_usbhsotg_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
         .class          = &usbotg_class,
         /*
          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
@@ -1652,20 +305,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
         { .irq = -1 }
 };
 
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp1_hwmod,
-        .clk            = "mcbsp1_ick",
-        .addr           = omap2_mcbsp1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
-        &omap2430_l4_core__mcbsp1,
-};
-
 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap2430_mcbsp_hwmod_class,
@@ -1681,8 +320,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
                 },
         },
-        .slaves         = omap2430_mcbsp1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
 };
 
 /* mcbsp2 */
@@ -1693,20 +330,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
         { .irq = -1 }
 };
 
-/* l4_core -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp2_hwmod,
-        .clk            = "mcbsp2_ick",
-        .addr           = omap2xxx_mcbsp2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
-        &omap2430_l4_core__mcbsp2,
-};
-
 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
         .name           = "mcbsp2",
         .class          = &omap2430_mcbsp_hwmod_class,
@@ -1722,8 +345,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
                 },
         },
-        .slaves         = omap2430_mcbsp2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
 };
 
 /* mcbsp3 */
@@ -1734,30 +355,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4808C000,
-                .pa_end         = 0x4808C0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp3_hwmod,
-        .clk            = "mcbsp3_ick",
-        .addr           = omap2430_mcbsp3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
-        &omap2430_l4_core__mcbsp3,
-};
-
 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
         .name           = "mcbsp3",
         .class          = &omap2430_mcbsp_hwmod_class,
@@ -1773,8 +370,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
                 },
         },
-        .slaves         = omap2430_mcbsp3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
 };
 
 /* mcbsp4 */
@@ -1791,30 +386,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4808E000,
-                .pa_end         = 0x4808E0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp4_hwmod,
-        .clk            = "mcbsp4_ick",
-        .addr           = omap2430_mcbsp4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
-        &omap2430_l4_core__mcbsp4,
-};
-
 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
         .name           = "mcbsp4",
         .class          = &omap2430_mcbsp_hwmod_class,
@@ -1830,8 +401,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
                 },
         },
-        .slaves         = omap2430_mcbsp4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
 };
 
 /* mcbsp5 */
@@ -1848,30 +417,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> mcbsp5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp5_hwmod,
-        .clk            = "mcbsp5_ick",
-        .addr           = omap2430_mcbsp5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp5 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
-        &omap2430_l4_core__mcbsp5,
-};
-
 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
         .name           = "mcbsp5",
         .class          = &omap2430_mcbsp_hwmod_class,
@@ -1887,12 +432,9 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
                 },
         },
-        .slaves         = omap2430_mcbsp5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
 };
 
 /* MMC/SD/SDIO common */
-
 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
         .rev_offs       = 0x1fc,
         .sysc_offs      = 0x10,
@@ -1910,7 +452,6 @@ static struct omap_hwmod_class omap2430_mmc_class = {
 };
 
 /* MMC/SD/SDIO1 */
-
 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
         { .irq = 83 },
         { .irq = -1 }
@@ -1926,10 +467,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
         { .role = "dbck", .clk = "mmchsdb1_fck" },
 };
 
-static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
-        &omap2430_l4_core__mmc1,
-};
-
 static struct omap_mmc_dev_attr mmc1_dev_attr = {
         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1952,13 +489,10 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
                 },
         },
         .dev_attr       = &mmc1_dev_attr,
-        .slaves         = omap2430_mmc1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
         .class          = &omap2430_mmc_class,
 };
 
 /* MMC/SD/SDIO2 */
-
 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
         { .irq = 86 },
         { .irq = -1 }
@@ -1974,10 +508,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
         { .role = "dbck", .clk = "mmchsdb2_fck" },
 };
 
-static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
-        &omap2430_l4_core__mmc2,
-};
-
 static struct omap_hwmod omap2430_mmc2_hwmod = {
         .name           = "mmc2",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1995,78 +525,418 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
                 },
         },
-        .slaves         = omap2430_mmc2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
         .class          = &omap2430_mmc_class,
 };
 
-static __initdata struct omap_hwmod *omap2430_hwmods[] = {
-        &omap2430_l3_main_hwmod,
-        &omap2430_l4_core_hwmod,
-        &omap2430_l4_wkup_hwmod,
-        &omap2430_mpu_hwmod,
-        &omap2430_iva_hwmod,
-
-        &omap2430_timer1_hwmod,
-        &omap2430_timer2_hwmod,
-        &omap2430_timer3_hwmod,
-        &omap2430_timer4_hwmod,
-        &omap2430_timer5_hwmod,
-        &omap2430_timer6_hwmod,
-        &omap2430_timer7_hwmod,
-        &omap2430_timer8_hwmod,
-        &omap2430_timer9_hwmod,
-        &omap2430_timer10_hwmod,
-        &omap2430_timer11_hwmod,
-        &omap2430_timer12_hwmod,
-
-        &omap2430_wd_timer2_hwmod,
-        &omap2430_uart1_hwmod,
-        &omap2430_uart2_hwmod,
-        &omap2430_uart3_hwmod,
-        /* dss class */
-        &omap2430_dss_core_hwmod,
-        &omap2430_dss_dispc_hwmod,
-        &omap2430_dss_rfbi_hwmod,
-        &omap2430_dss_venc_hwmod,
-        /* i2c class */
-        &omap2430_i2c1_hwmod,
-        &omap2430_i2c2_hwmod,
-        &omap2430_mmc1_hwmod,
-        &omap2430_mmc2_hwmod,
-
-        /* gpio class */
-        &omap2430_gpio1_hwmod,
-        &omap2430_gpio2_hwmod,
-        &omap2430_gpio3_hwmod,
-        &omap2430_gpio4_hwmod,
-        &omap2430_gpio5_hwmod,
-
-        /* dma_system class*/
-        &omap2430_dma_system_hwmod,
-
-        /* mcbsp class */
-        &omap2430_mcbsp1_hwmod,
-        &omap2430_mcbsp2_hwmod,
-        &omap2430_mcbsp3_hwmod,
-        &omap2430_mcbsp4_hwmod,
-        &omap2430_mcbsp5_hwmod,
-
-        /* mailbox class */
-        &omap2430_mailbox_hwmod,
-
-        /* mcspi class */
-        &omap2430_mcspi1_hwmod,
-        &omap2430_mcspi2_hwmod,
-        &omap2430_mcspi3_hwmod,
-
-        /* usbotg class*/
-        &omap2430_usbhsotg_hwmod,
+/* HDQ1W/1-wire */
+static struct omap_hwmod omap2430_hdq1w_hwmod = {
+        .name           = "hdq1w",
+        .mpu_irqs       = omap2_hdq1w_mpu_irqs,
+        .main_clk       = "hdq_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_HDQ_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
+                },
+        },
+        .class          = &omap2_hdq1w_class,
+};
+
+/*
+ * interfaces
+ */
+
+/* L3 -> L4_CORE interface */
+/* l3_core -> usbhsotg  interface */
+static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
+        .master         = &omap2430_usbhsotg_hwmod,
+        .slave          = &omap2xxx_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU,
+};
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap2_i2c1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2_i2c2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
+        {
+                .pa_start       = OMAP243X_HS_BASE,
+                .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/*  l4_core ->usbhsotg  interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_usbhsotg_hwmod,
+        .clk            = "usb_l4_ick",
+        .addr           = omap2430_usbhsotg_addrs,
+        .user           = OCP_USER_MPU,
+};
 
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mmc2_hwmod,
+        .clk            = "mmchs2_ick",
+        .addr           = omap2430_mmc2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcspi3_hwmod,
+        .clk            = "mcspi3_ick",
+        .addr           = omap2430_mcspi3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if omap2430_l3__iva = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2430_iva_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+        {
+                .pa_start       = 0x49018000,
+                .pa_end         = 0x49018000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2430_timer1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49016000,
+                .pa_end         = 0x4901607f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_wd_timer2_hwmod,
+        .clk            = "mpu_wdt_ick",
+        .addr           = omap2430_wd_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
+        {
+                .pa_start       = 0x4900C000,
+                .pa_end         = 0x4900C1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio1_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
+        {
+                .pa_start       = 0x4900E000,
+                .pa_end         = 0x4900E1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio2_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
+        {
+                .pa_start       = 0x49010000,
+                .pa_end         = 0x490101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio3_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
+        {
+                .pa_start       = 0x49012000,
+                .pa_end         = 0x490121ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio4_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> gpio5 */
+static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
+        {
+                .pa_start       = 0x480B6000,
+                .pa_end         = 0x480B61ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_gpio5_hwmod,
+        .clk            = "gpio5_ick",
+        .addr           = omap2430_gpio5_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
+        .master         = &omap2430_dma_system_hwmod,
+        .slave          = &omap2xxx_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_dma_system_hwmod,
+        .clk            = "sdma_ick",
+        .addr           = omap2_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mailbox_hwmod,
+        .addr           = omap2_mailbox_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap2_mcbsp1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap2xxx_mcbsp2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808C000,
+                .pa_end         = 0x4808C0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap2430_mcbsp3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808E000,
+                .pa_end         = 0x4808E0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap2430_mcbsp4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap2430_mcbsp5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> hdq1w */
+static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_hdq1w_hwmod,
+        .clk            = "hdq_ick",
+        .addr           = omap2_hdq1w_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
+};
+
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
+        {
+                .pa_start       = 0x49020000,
+                .pa_end         = 0x4902001f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_counter_32k_hwmod,
+        .clk            = "sync_32k_ick",
+        .addr           = omap2430_counter_32k_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
+        &omap2xxx_l3_main__l4_core,
+        &omap2xxx_mpu__l3_main,
+        &omap2xxx_dss__l3,
+        &omap2430_usbhsotg__l3,
+        &omap2430_l4_core__i2c1,
+        &omap2430_l4_core__i2c2,
+        &omap2xxx_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
+        &omap2430_l4_core__usbhsotg,
+        &omap2430_l4_core__mmc1,
+        &omap2430_l4_core__mmc2,
+        &omap2xxx_l4_core__mcspi1,
+        &omap2xxx_l4_core__mcspi2,
+        &omap2430_l4_core__mcspi3,
+        &omap2430_l3__iva,
+        &omap2430_l4_wkup__timer1,
+        &omap2xxx_l4_core__timer2,
+        &omap2xxx_l4_core__timer3,
+        &omap2xxx_l4_core__timer4,
+        &omap2xxx_l4_core__timer5,
+        &omap2xxx_l4_core__timer6,
+        &omap2xxx_l4_core__timer7,
+        &omap2xxx_l4_core__timer8,
+        &omap2xxx_l4_core__timer9,
+        &omap2xxx_l4_core__timer10,
+        &omap2xxx_l4_core__timer11,
+        &omap2xxx_l4_core__timer12,
+        &omap2430_l4_wkup__wd_timer2,
+        &omap2xxx_l4_core__dss,
+        &omap2xxx_l4_core__dss_dispc,
+        &omap2xxx_l4_core__dss_rfbi,
+        &omap2xxx_l4_core__dss_venc,
+        &omap2430_l4_wkup__gpio1,
+        &omap2430_l4_wkup__gpio2,
+        &omap2430_l4_wkup__gpio3,
+        &omap2430_l4_wkup__gpio4,
+        &omap2430_l4_core__gpio5,
+        &omap2430_dma_system__l3,
+        &omap2430_l4_core__dma_system,
+        &omap2430_l4_core__mailbox,
+        &omap2430_l4_core__mcbsp1,
+        &omap2430_l4_core__mcbsp2,
+        &omap2430_l4_core__mcbsp3,
+        &omap2430_l4_core__mcbsp4,
+        &omap2430_l4_core__mcbsp5,
+        &omap2430_l4_core__hdq1w,
+        &omap2430_l4_wkup__counter_32k,
         NULL,
 };
 
 int __init omap2430_hwmod_init(void)
 {
-        return omap_hwmod_register(omap2430_hwmods);
+        return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index 04637fabadd2..cbb4ef6544ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -171,3 +171,12 @@ struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
         },
         { }
 };
+
+struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
+        {
+                .pa_start       = 0x480b2000,
+                .pa_end         = 0x480b2fff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index f08e442af397..102d76e9e9ea 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -2,6 +2,7 @@
  * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
  *
  * Copyright (C) 2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -12,6 +13,7 @@
 #include <plat/serial.h>
 #include <plat/dma.h>
 #include <plat/common.h>
+#include <plat/hdq1w.h>
 
 #include <mach/irqs.h>
 
@@ -302,3 +304,23 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
         { .irq = -1 }
 };
 
+struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x14,
+        .syss_offs      = 0x18,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_hdq1w_class = {
+        .name   = "hdq1w",
+        .sysc   = &omap2_hdq1w_sysc,
+        .reset  = &omap_hdq1w_reset,
+};
+
+struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
+        { .irq = 58, },
+        { .irq = -1 }
+};
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 4f3547c2a49e..5178e40e84f9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -15,10 +15,12 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
+#include <plat/l3_2xxx.h>
+#include <plat/l4_2xxx.h>
 
 #include "omap_hwmod_common_data.h"
 
-struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
         {
                 .pa_start       = OMAP2_UART1_BASE,
                 .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
@@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
         {
                 .pa_start       = OMAP2_UART2_BASE,
                 .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
@@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
         {
                 .pa_start       = OMAP2_UART3_BASE,
                 .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
@@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
         {
                 .pa_start       = 0x4802a000,
                 .pa_end         = 0x4802a000 + SZ_1K - 1,
@@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
         {
                 .pa_start       = 0x48078000,
                 .pa_end         = 0x48078000 + SZ_1K - 1,
@@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
         {
                 .pa_start       = 0x4807a000,
                 .pa_end         = 0x4807a000 + SZ_1K - 1,
@@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
         {
                 .pa_start       = 0x4807c000,
                 .pa_end         = 0x4807c000 + SZ_1K - 1,
@@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
         {
                 .pa_start       = 0x4807e000,
                 .pa_end         = 0x4807e000 + SZ_1K - 1,
@@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
         {
                 .pa_start       = 0x48080000,
                 .pa_end         = 0x48080000 + SZ_1K - 1,
@@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
         {
                 .pa_start       = 0x48082000,
                 .pa_end         = 0x48082000 + SZ_1K - 1,
@@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
         { }
 };
 
-struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
         {
                 .pa_start       = 0x48084000,
                 .pa_end         = 0x48084000 + SZ_1K - 1,
@@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
         { }
 };
 
+/*
+ * Common interconnect data
+ */
+
+/* L3 -> L4_CORE interface */
+struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
+        .master = &omap2xxx_l3_main_hwmod,
+        .slave  = &omap2xxx_l4_core_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* MPU -> L3 interface */
+struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
+        .master = &omap2xxx_mpu_hwmod,
+        .slave  = &omap2xxx_l3_main_hwmod,
+        .user   = OCP_USER_MPU,
+};
+
+/* DSS -> l3 */
+struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
+        .master         = &omap2xxx_dss_core_hwmod,
+        .slave          = &omap2xxx_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4_CORE -> L4_WKUP interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
+        .master = &omap2xxx_l4_core_hwmod,
+        .slave  = &omap2xxx_l4_wkup_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART1 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap2xxx_uart1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap2xxx_uart2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap2xxx_uart3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi1 interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_mcspi1_hwmod,
+        .clk            = "mcspi1_ick",
+        .addr           = omap2_mcspi1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_mcspi2_hwmod,
+        .clk            = "mcspi2_ick",
+        .addr           = omap2_mcspi2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer2 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap2xxx_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer3 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap2xxx_timer3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer4 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap2xxx_timer4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer5 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap2xxx_timer5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer6 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap2xxx_timer6_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer7 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap2xxx_timer7_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer8 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap2xxx_timer8_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer9 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap2xxx_timer9_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer10 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2_timer10_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer11 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2_timer11_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer12 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap2xxx_timer12_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_dispc */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_dispc_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_rfbi */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_rfbi_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_venc */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_dss_venc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_venc_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .flags          = OCPIF_SWSUP_IDLE,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 2a6729741b06..83eafd96ecaa 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,6 +10,7 @@
  */
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
+#include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
 #include <plat/mcspi.h>
@@ -17,6 +18,8 @@
 #include <mach/irqs.h>
 
 #include "omap_hwmod_common_data.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
 #include "wd_timer.h"
 
 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
@@ -86,7 +89,8 @@ static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
         .name           = "wd_timer",
         .sysc           = &omap2xxx_wd_timer_sysc,
-        .pre_shutdown   = &omap2_wd_timer_disable
+        .pre_shutdown   = &omap2_wd_timer_disable,
+        .reset          = &omap2_wd_timer_reset,
 };
 
 /*
@@ -170,3 +174,582 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
         .sysc   = &omap2xxx_mcspi_sysc,
         .rev    = OMAP2_MCSPI_REV,
 };
+
+/*
+ * IP blocks
+ */
+
+/* L3 */
+struct omap_hwmod omap2xxx_l3_main_hwmod = {
+        .name           = "l3_main",
+        .class          = &l3_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* L4 CORE */
+struct omap_hwmod omap2xxx_l4_core_hwmod = {
+        .name           = "l4_core",
+        .class          = &l4_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* L4 WKUP */
+struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &l4_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* MPU */
+struct omap_hwmod omap2xxx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &mpu_hwmod_class,
+        .main_clk       = "mpu_ck",
+};
+
+/* IVA2 */
+struct omap_hwmod omap2xxx_iva_hwmod = {
+        .name           = "iva",
+        .class          = &iva_hwmod_class,
+};
+
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
+};
+
+/* timer1 */
+
+struct omap_hwmod omap2xxx_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap2_timer1_mpu_irqs,
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer2 */
+
+struct omap_hwmod omap2xxx_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap2_timer2_mpu_irqs,
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer3 */
+
+struct omap_hwmod omap2xxx_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap2_timer3_mpu_irqs,
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer4 */
+
+struct omap_hwmod omap2xxx_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap2_timer4_mpu_irqs,
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer5 */
+
+struct omap_hwmod omap2xxx_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap2_timer5_mpu_irqs,
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer6 */
+
+struct omap_hwmod omap2xxx_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap2_timer6_mpu_irqs,
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer7 */
+
+struct omap_hwmod omap2xxx_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap2_timer7_mpu_irqs,
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer8 */
+
+struct omap_hwmod omap2xxx_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap2_timer8_mpu_irqs,
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer9 */
+
+struct omap_hwmod omap2xxx_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap2_timer9_mpu_irqs,
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer10 */
+
+struct omap_hwmod omap2xxx_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap2_timer10_mpu_irqs,
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer11 */
+
+struct omap_hwmod omap2xxx_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap2_timer11_mpu_irqs,
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* timer12 */
+
+struct omap_hwmod omap2xxx_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+
+/* wd_timer2 */
+struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap2xxx_wd_timer_hwmod_class,
+        .main_clk       = "mpu_wdt_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+                },
+        },
+};
+
+/* UART1 */
+
+struct omap_hwmod omap2xxx_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = omap2_uart1_mpu_irqs,
+        .sdma_reqs      = omap2_uart1_sdma_reqs,
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+                },
+        },
+        .class          = &omap2_uart_class,
+};
+
+/* UART2 */
+
+struct omap_hwmod omap2xxx_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = omap2_uart2_mpu_irqs,
+        .sdma_reqs      = omap2_uart2_sdma_reqs,
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+                },
+        },
+        .class          = &omap2_uart_class,
+};
+
+/* UART3 */
+
+struct omap_hwmod omap2xxx_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = omap2_uart3_mpu_irqs,
+        .sdma_reqs      = omap2_uart3_sdma_reqs,
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+                },
+        },
+        .class          = &omap2_uart_class,
+};
+
+/* dss */
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        /*
+         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+         * driver does not use these clocks.
+         */
+        { .role = "tv_clk", .clk = "dss_54m_fck" },
+        { .role = "sys_clk", .clk = "dss2_fck" },
+};
+
+struct omap_hwmod omap2xxx_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap2_dss_hwmod_class,
+        .main_clk       = "dss1_fck", /* instead of dss_fck */
+        .sdma_reqs      = omap2xxx_dss_sdma_chs,
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+};
+
+struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap2_dispc_hwmod_class,
+        .mpu_irqs       = omap2_dispc_irqs,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .flags          = HWMOD_NO_IDLEST,
+        .dev_attr       = &omap2_3_dss_dispc_dev_attr
+};
+
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+        { .role = "ick", .clk = "dss_ick" },
+};
+
+struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap2_rfbi_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .opt_clks       = dss_rfbi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+struct omap_hwmod omap2xxx_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap2_venc_hwmod_class,
+        .main_clk       = "dss_54m_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* gpio dev_attr */
+struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
+        .bank_width = 32,
+        .dbck_flag = false,
+};
+
+/* gpio1 */
+struct omap_hwmod omap2xxx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2_gpio1_irqs,
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_gpio_hwmod_class,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio2 */
+struct omap_hwmod omap2xxx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2_gpio2_irqs,
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_gpio_hwmod_class,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio3 */
+struct omap_hwmod omap2xxx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2_gpio3_irqs,
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_gpio_hwmod_class,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
+};
+
+/* gpio4 */
+struct omap_hwmod omap2xxx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2_gpio4_irqs,
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_gpio_hwmod_class,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
+};
+
+/* mcspi1 */
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+struct omap_hwmod omap2xxx_mcspi1_hwmod = {
+        .name           = "mcspi1",
+        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
+        .main_clk       = "mcspi1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+struct omap_hwmod omap2xxx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
+        .main_clk       = "mcspi2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
+};
+
+
+static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
+        .name   = "counter",
+};
+
+struct omap_hwmod omap2xxx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .main_clk       = "func_32k_ck",
+        .prcm           = {
+                .omap2  = {
+                        .module_offs = WKUP_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_counter_hwmod_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index db86ce90c69f..b26d3c9bca16 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2,6 +2,7 @@
  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
  *
  * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -38,491 +39,56 @@
 /*
  * OMAP3xxx hardware module integration data
  *
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
  * TI hardware database or other technical documentation.  Data that
  * is driver-specific or driver-kernel integration-specific belongs
  * elsewhere.
  */
 
-static struct omap_hwmod omap3xxx_mpu_hwmod;
-static struct omap_hwmod omap3xxx_iva_hwmod;
-static struct omap_hwmod omap3xxx_l3_main_hwmod;
-static struct omap_hwmod omap3xxx_l4_core_hwmod;
-static struct omap_hwmod omap3xxx_l4_per_hwmod;
-static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
-static struct omap_hwmod omap3430es1_dss_core_hwmod;
-static struct omap_hwmod omap3xxx_dss_core_hwmod;
-static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
-static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
-static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
-static struct omap_hwmod omap3xxx_dss_venc_hwmod;
-static struct omap_hwmod omap3xxx_i2c1_hwmod;
-static struct omap_hwmod omap3xxx_i2c2_hwmod;
-static struct omap_hwmod omap3xxx_i2c3_hwmod;
-static struct omap_hwmod omap3xxx_gpio1_hwmod;
-static struct omap_hwmod omap3xxx_gpio2_hwmod;
-static struct omap_hwmod omap3xxx_gpio3_hwmod;
-static struct omap_hwmod omap3xxx_gpio4_hwmod;
-static struct omap_hwmod omap3xxx_gpio5_hwmod;
-static struct omap_hwmod omap3xxx_gpio6_hwmod;
-static struct omap_hwmod omap34xx_sr1_hwmod;
-static struct omap_hwmod omap34xx_sr2_hwmod;
-static struct omap_hwmod omap34xx_mcspi1;
-static struct omap_hwmod omap34xx_mcspi2;
-static struct omap_hwmod omap34xx_mcspi3;
-static struct omap_hwmod omap34xx_mcspi4;
-static struct omap_hwmod omap3xxx_mmc1_hwmod;
-static struct omap_hwmod omap3xxx_mmc2_hwmod;
-static struct omap_hwmod omap3xxx_mmc3_hwmod;
-static struct omap_hwmod am35xx_usbhsotg_hwmod;
-
-static struct omap_hwmod omap3xxx_dma_system_hwmod;
-
-static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
-static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
-static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
-
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
-        .master = &omap3xxx_l3_main_hwmod,
-        .slave  = &omap3xxx_l4_core_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L3 -> L4_PER interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
-        .master = &omap3xxx_l3_main_hwmod,
-        .slave  = &omap3xxx_l4_per_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
+/*
+ * IP blocks
+ */
 
-/* L3 taret configuration and error log registers */
+/* L3 */
 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
         { .irq = INT_34XX_L3_DBG_IRQ },
         { .irq = INT_34XX_L3_APP_IRQ },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
-        {
-                .pa_start       = 0x68000000,
-                .pa_end         = 0x6800ffff,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
-        .master   = &omap3xxx_mpu_hwmod,
-        .slave    = &omap3xxx_l3_main_hwmod,
-        .addr     = omap3xxx_l3_main_addrs,
-        .user   = OCP_USER_MPU,
-};
-
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
-        &omap3xxx_mpu__l3_main,
-};
-
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
-        .master         = &omap3xxx_dss_core_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .fw = {
-                .omap2 = {
-                        .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
-                        .flags  = OMAP_FIREWALL_L3,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
-        &omap3xxx_l3_main__l4_core,
-        &omap3xxx_l3_main__l4_per,
-};
-
-/* L3 */
 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
         .name           = "l3_main",
         .class          = &l3_hwmod_class,
         .mpu_irqs       = omap3xxx_l3_main_irqs,
-        .masters        = omap3xxx_l3_main_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
-        .slaves         = omap3xxx_l3_main_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
         .flags          = HWMOD_NO_IDLEST,
 };
 
-static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
-static struct omap_hwmod omap3xxx_uart1_hwmod;
-static struct omap_hwmod omap3xxx_uart2_hwmod;
-static struct omap_hwmod omap3xxx_uart3_hwmod;
-static struct omap_hwmod omap3xxx_uart4_hwmod;
-static struct omap_hwmod am35xx_uart4_hwmod;
-static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
-
-/* l3_core -> usbhsotg interface */
-static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
-        .master         = &omap3xxx_usbhsotg_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
-        .user           = OCP_USER_MPU,
-};
-
-/* l3_core -> am35xx_usbhsotg interface */
-static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
-        .master         = &am35xx_usbhsotg_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
-        .user           = OCP_USER_MPU,
-};
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
-        .master = &omap3xxx_l4_core_hwmod,
-        .slave  = &omap3xxx_l4_wkup_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mmc1_hwmod,
-        .clk            = "mmchs1_ick",
-        .addr           = omap2430_mmc1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        .flags          = OMAP_FIREWALL_L4
-};
-
-/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mmc2_hwmod,
-        .clk            = "mmchs2_ick",
-        .addr           = omap2430_mmc2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        .flags          = OMAP_FIREWALL_L4
-};
-
-/* L4 CORE -> MMC3 interface */
-static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
-        {
-                .pa_start       = 0x480ad000,
-                .pa_end         = 0x480ad1ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mmc3_hwmod,
-        .clk            = "mmchs3_ick",
-        .addr           = omap3xxx_mmc3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        .flags          = OMAP_FIREWALL_L4
-};
-
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART1_BASE,
-                .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_uart1_hwmod,
-        .clk            = "uart1_ick",
-        .addr           = omap3xxx_uart1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART2_BASE,
-                .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_uart2_hwmod,
-        .clk            = "uart2_ick",
-        .addr           = omap3xxx_uart2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART3_BASE,
-                .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_uart3_hwmod,
-        .clk            = "uart3_ick",
-        .addr           = omap3xxx_uart3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 PER -> UART4 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART4_BASE,
-                .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_uart4_hwmod,
-        .clk            = "uart4_ick",
-        .addr           = omap3xxx_uart4_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* AM35xx: L4 CORE -> UART4 interface */
-static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART4_AM35XX_BASE,
-                .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-};
-
-static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &am35xx_uart4_hwmod,
-        .clk            = "uart4_ick",
-        .addr           = am35xx_uart4_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_i2c1_hwmod,
-        .clk            = "i2c1_ick",
-        .addr           = omap2_i2c1_addr_space,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
-                        .l4_prot_group = 7,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_i2c2_hwmod,
-        .clk            = "i2c2_ick",
-        .addr           = omap2_i2c2_addr_space,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
-                        .l4_prot_group = 7,
-                        .flags = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* L4 CORE -> I2C3 interface */
-static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
-        {
-                .pa_start       = 0x48060000,
-                .pa_end         = 0x48060000 + SZ_128 - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_i2c3_hwmod,
-        .clk            = "i2c3_ick",
-        .addr           = omap3xxx_i2c3_addr_space,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
-                        .l4_prot_group = 7,
-                        .flags = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
-        { .irq = 18},
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
-        { .irq = 19},
-        { .irq = -1 }
-};
-
-/* L4 CORE -> SR1 interface */
-static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
-        {
-                .pa_start       = OMAP34XX_SR1_BASE,
-                .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_sr1_hwmod,
-        .clk            = "sr_l4_ick",
-        .addr           = omap3_sr1_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/* L4 CORE -> SR1 interface */
-static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
-        {
-                .pa_start       = OMAP34XX_SR2_BASE,
-                .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_sr2_hwmod,
-        .clk            = "sr_l4_ick",
-        .addr           = omap3_sr2_addr_space,
-        .user           = OCP_USER_MPU,
-};
-
-/*
-* usbhsotg interface data
-*/
-
-static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
-        {
-                .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
-                .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> usbhsotg  */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_usbhsotg_hwmod,
-        .clk            = "l4_ick",
-        .addr           = omap3xxx_usbhsotg_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
-        &omap3xxx_usbhsotg__l3,
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
-        &omap3xxx_l4_core__usbhsotg,
-};
-
-static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
-        {
-                .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
-                .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> usbhsotg  */
-static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &am35xx_usbhsotg_hwmod,
-        .clk            = "l4_ick",
-        .addr           = am35xx_usbhsotg_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
-        &am35xx_usbhsotg__l3,
-};
-
-static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
-        &am35xx_l4_core__usbhsotg,
-};
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
-        &omap3xxx_l3_main__l4_core,
-};
-
 /* L4 CORE */
 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
         .name           = "l4_core",
         .class          = &l4_hwmod_class,
-        .slaves         = omap3xxx_l4_core_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/* Slave interfaces on the L4_PER interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
-        &omap3xxx_l3_main__l4_per,
-};
-
 /* L4 PER */
 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
         .name           = "l4_per",
         .class          = &l4_hwmod_class,
-        .slaves         = omap3xxx_l4_per_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
-        &omap3xxx_l4_core__l4_wkup,
-};
-
 /* L4 WKUP */
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
         .name           = "l4_wkup",
         .class          = &l4_hwmod_class,
-        .slaves         = omap3xxx_l4_wkup_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
-        &omap3xxx_mpu__l3_main,
+/* L4 SEC */
+static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
+        .name           = "l4_sec",
+        .class          = &l4_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
 };
 
 /* MPU */
@@ -530,35 +96,22 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
         .name           = "mpu",
         .class          = &mpu_hwmod_class,
         .main_clk       = "arm_fck",
-        .masters        = omap3xxx_mpu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 };
 
-/*
- * IVA2_2 interface data
- */
-
-/* IVA2 <- L3 interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
-        .master         = &omap3xxx_l3_main_hwmod,
-        .slave          = &omap3xxx_iva_hwmod,
-        .clk            = "iva2_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+/* IVA2 (IVA2) */
+static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
+        { .name = "logic", .rst_shift = 0 },
+        { .name = "seq0", .rst_shift = 1 },
+        { .name = "seq1", .rst_shift = 2 },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
-        &omap3xxx_l3__iva,
-};
-
-/*
- * IVA2 (IVA2)
- */
-
 static struct omap_hwmod omap3xxx_iva_hwmod = {
         .name           = "iva",
         .class          = &iva_hwmod_class,
-        .masters        = omap3xxx_iva_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
+        .clkdm_name     = "iva2_clkdm",
+        .rst_lines      = omap3xxx_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
+        .main_clk       = "iva2_ck",
 };
 
 /* timer class */
@@ -597,46 +150,20 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 
 /* secure timers dev attribute */
 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
-        .timer_capability       = OMAP_TIMER_SECURE,
+        .timer_capability       = OMAP_TIMER_SECURE,
 };
 
 /* always-on timers dev attribute */
 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
-        .timer_capability       = OMAP_TIMER_ALWON,
+        .timer_capability       = OMAP_TIMER_ALWON,
 };
 
 /* pwm timers dev attribute */
 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
-        .timer_capability       = OMAP_TIMER_HAS_PWM,
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
 /* timer1 */
-static struct omap_hwmod omap3xxx_timer1_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
-        {
-                .pa_start       = 0x48318000,
-                .pa_end         = 0x48318000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
-        .master         = &omap3xxx_l4_wkup_hwmod,
-        .slave          = &omap3xxx_timer1_hwmod,
-        .clk            = "gpt1_ick",
-        .addr           = omap3xxx_timer1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer1 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
-        &omap3xxx_l4_wkup__timer1,
-};
-
-/* timer1 hwmod */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
         .name           = "timer1",
         .mpu_irqs       = omap2_timer1_mpu_irqs,
@@ -651,38 +178,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
         .class          = &omap3xxx_timer_1ms_hwmod_class,
 };
 
 /* timer2 */
-static struct omap_hwmod omap3xxx_timer2_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
-        {
-                .pa_start       = 0x49032000,
-                .pa_end         = 0x49032000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer2_hwmod,
-        .clk            = "gpt2_ick",
-        .addr           = omap3xxx_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer2 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
-        &omap3xxx_l4_per__timer2,
-};
-
-/* timer2 hwmod */
 static struct omap_hwmod omap3xxx_timer2_hwmod = {
         .name           = "timer2",
         .mpu_irqs       = omap2_timer2_mpu_irqs,
@@ -697,38 +196,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
         .class          = &omap3xxx_timer_1ms_hwmod_class,
 };
 
 /* timer3 */
-static struct omap_hwmod omap3xxx_timer3_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
-        {
-                .pa_start       = 0x49034000,
-                .pa_end         = 0x49034000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer3_hwmod,
-        .clk            = "gpt3_ick",
-        .addr           = omap3xxx_timer3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
-        &omap3xxx_l4_per__timer3,
-};
-
-/* timer3 hwmod */
 static struct omap_hwmod omap3xxx_timer3_hwmod = {
         .name           = "timer3",
         .mpu_irqs       = omap2_timer3_mpu_irqs,
@@ -743,38 +214,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
 /* timer4 */
-static struct omap_hwmod omap3xxx_timer4_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
-        {
-                .pa_start       = 0x49036000,
-                .pa_end         = 0x49036000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer4_hwmod,
-        .clk            = "gpt4_ick",
-        .addr           = omap3xxx_timer4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer4 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
-        &omap3xxx_l4_per__timer4,
-};
-
-/* timer4 hwmod */
 static struct omap_hwmod omap3xxx_timer4_hwmod = {
         .name           = "timer4",
         .mpu_irqs       = omap2_timer4_mpu_irqs,
@@ -789,38 +232,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
 /* timer5 */
-static struct omap_hwmod omap3xxx_timer5_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
-        {
-                .pa_start       = 0x49038000,
-                .pa_end         = 0x49038000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer5 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer5_hwmod,
-        .clk            = "gpt5_ick",
-        .addr           = omap3xxx_timer5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer5 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
-        &omap3xxx_l4_per__timer5,
-};
-
-/* timer5 hwmod */
 static struct omap_hwmod omap3xxx_timer5_hwmod = {
         .name           = "timer5",
         .mpu_irqs       = omap2_timer5_mpu_irqs,
@@ -835,38 +250,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
 /* timer6 */
-static struct omap_hwmod omap3xxx_timer6_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4903A000,
-                .pa_end         = 0x4903A000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer6 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer6_hwmod,
-        .clk            = "gpt6_ick",
-        .addr           = omap3xxx_timer6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
-        &omap3xxx_l4_per__timer6,
-};
-
-/* timer6 hwmod */
 static struct omap_hwmod omap3xxx_timer6_hwmod = {
         .name           = "timer6",
         .mpu_irqs       = omap2_timer6_mpu_irqs,
@@ -881,38 +268,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
 /* timer7 */
-static struct omap_hwmod omap3xxx_timer7_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
-        {
-                .pa_start       = 0x4903C000,
-                .pa_end         = 0x4903C000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer7 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer7_hwmod,
-        .clk            = "gpt7_ick",
-        .addr           = omap3xxx_timer7_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
-        &omap3xxx_l4_per__timer7,
-};
-
-/* timer7 hwmod */
 static struct omap_hwmod omap3xxx_timer7_hwmod = {
         .name           = "timer7",
         .mpu_irqs       = omap2_timer7_mpu_irqs,
@@ -927,38 +286,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer7_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
 /* timer8 */
-static struct omap_hwmod omap3xxx_timer8_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
-        {
-                .pa_start       = 0x4903E000,
-                .pa_end         = 0x4903E000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer8 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer8_hwmod,
-        .clk            = "gpt8_ick",
-        .addr           = omap3xxx_timer8_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer8 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
-        &omap3xxx_l4_per__timer8,
-};
-
-/* timer8 hwmod */
 static struct omap_hwmod omap3xxx_timer8_hwmod = {
         .name           = "timer8",
         .mpu_irqs       = omap2_timer8_mpu_irqs,
@@ -973,38 +304,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                 },
         },
         .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap3xxx_timer8_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
 /* timer9 */
-static struct omap_hwmod omap3xxx_timer9_hwmod;
-
-static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
-        {
-                .pa_start       = 0x49040000,
-                .pa_end         = 0x49040000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer9_hwmod,
-        .clk            = "gpt9_ick",
-        .addr           = omap3xxx_timer9_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
-        &omap3xxx_l4_per__timer9,
-};
-
-/* timer9 hwmod */
 static struct omap_hwmod omap3xxx_timer9_hwmod = {
         .name           = "timer9",
         .mpu_irqs       = omap2_timer9_mpu_irqs,
@@ -1019,29 +322,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
                 },
         },
         .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap3xxx_timer9_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
 /* timer10 */
-static struct omap_hwmod omap3xxx_timer10_hwmod;
-
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_timer10_hwmod,
-        .clk            = "gpt10_ick",
-        .addr           = omap2_timer10_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer10 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
-        &omap3xxx_l4_core__timer10,
-};
-
-/* timer10 hwmod */
 static struct omap_hwmod omap3xxx_timer10_hwmod = {
         .name           = "timer10",
         .mpu_irqs       = omap2_timer10_mpu_irqs,
@@ -1056,29 +340,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
                 },
         },
         .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap3xxx_timer10_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
         .class          = &omap3xxx_timer_1ms_hwmod_class,
 };
 
 /* timer11 */
-static struct omap_hwmod omap3xxx_timer11_hwmod;
-
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_timer11_hwmod,
-        .clk            = "gpt11_ick",
-        .addr           = omap2_timer11_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer11 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
-        &omap3xxx_l4_core__timer11,
-};
-
-/* timer11 hwmod */
 static struct omap_hwmod omap3xxx_timer11_hwmod = {
         .name           = "timer11",
         .mpu_irqs       = omap2_timer11_mpu_irqs,
@@ -1093,42 +358,15 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
                 },
         },
         .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap3xxx_timer11_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
-/* timer12*/
-static struct omap_hwmod omap3xxx_timer12_hwmod;
+/* timer12 */
 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
         { .irq = 95, },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
-        {
-                .pa_start       = 0x48304000,
-                .pa_end         = 0x48304000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_timer12_hwmod,
-        .clk            = "gpt12_ick",
-        .addr           = omap3xxx_timer12_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
-        &omap3xxx_l4_core__timer12,
-};
-
-/* timer12 hwmod */
 static struct omap_hwmod omap3xxx_timer12_hwmod = {
         .name           = "timer12",
         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
@@ -1143,29 +381,9 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
                 },
         },
         .dev_attr       = &capability_secure_dev_attr,
-        .slaves         = omap3xxx_timer12_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x48314000,
-                .pa_end         = 0x4831407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
-        .master         = &omap3xxx_l4_wkup_hwmod,
-        .slave          = &omap3xxx_wd_timer2_hwmod,
-        .clk            = "wdt2_ick",
-        .addr           = omap3xxx_wd_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /*
  * 'wd_timer' class
  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
@@ -1200,12 +418,8 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
         .name           = "wd_timer",
         .sysc           = &omap3xxx_wd_timer_sysc,
-        .pre_shutdown   = &omap2_wd_timer_disable
-};
-
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
-        &omap3xxx_l4_wkup__wd_timer2,
+        .pre_shutdown   = &omap2_wd_timer_disable,
+        .reset          = &omap2_wd_timer_reset,
 };
 
 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
@@ -1221,8 +435,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
         /*
          * XXX: Use software supervised mode, HW supervised smartidle seems to
          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@@ -1231,11 +443,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 };
 
 /* UART1 */
-
-static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
-        &omap3_l4_core__uart1,
-};
-
 static struct omap_hwmod omap3xxx_uart1_hwmod = {
         .name           = "uart1",
         .mpu_irqs       = omap2_uart1_mpu_irqs,
@@ -1250,17 +457,10 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_uart1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
         .class          = &omap2_uart_class,
 };
 
 /* UART2 */
-
-static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
-        &omap3_l4_core__uart2,
-};
-
 static struct omap_hwmod omap3xxx_uart2_hwmod = {
         .name           = "uart2",
         .mpu_irqs       = omap2_uart2_mpu_irqs,
@@ -1275,17 +475,10 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_uart2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
         .class          = &omap2_uart_class,
 };
 
 /* UART3 */
-
-static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
-        &omap3_l4_per__uart3,
-};
-
 static struct omap_hwmod omap3xxx_uart3_hwmod = {
         .name           = "uart3",
         .mpu_irqs       = omap2_uart3_mpu_irqs,
@@ -1300,13 +493,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_uart3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
         .class          = &omap2_uart_class,
 };
 
 /* UART4 */
-
 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
         { .irq = INT_36XX_UART4_IRQ, },
         { .irq = -1 }
@@ -1318,11 +508,7 @@ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
-        &omap3_l4_per__uart4,
-};
-
-static struct omap_hwmod omap3xxx_uart4_hwmod = {
+static struct omap_hwmod omap36xx_uart4_hwmod = {
         .name           = "uart4",
         .mpu_irqs       = uart4_mpu_irqs,
         .sdma_reqs      = uart4_sdma_reqs,
@@ -1336,8 +522,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_uart4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
         .class          = &omap2_uart_class,
 };
 
@@ -1350,16 +534,12 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 };
 
-static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
-        &am35xx_l4_core__uart4,
-};
-
 static struct omap_hwmod am35xx_uart4_hwmod = {
-        .name           = "uart4",
-        .mpu_irqs       = am35xx_uart4_mpu_irqs,
-        .sdma_reqs      = am35xx_uart4_sdma_reqs,
-        .main_clk       = "uart4_fck",
-        .prcm           = {
+        .name           = "uart4",
+        .mpu_irqs       = am35xx_uart4_mpu_irqs,
+        .sdma_reqs      = am35xx_uart4_sdma_reqs,
+        .main_clk       = "uart4_fck",
+        .prcm           = {
                 .omap2 = {
                         .module_offs = CORE_MOD,
                         .prcm_reg_id = 1,
@@ -1368,12 +548,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
                         .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
                 },
         },
-        .slaves         = am35xx_uart4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(am35xx_uart4_slaves),
-        .class          = &omap2_uart_class,
+        .class          = &omap2_uart_class,
 };
 
-
 static struct omap_hwmod_class i2c_class = {
         .name   = "i2c",
         .sysc   = &i2c_sysc,
@@ -1388,51 +565,6 @@ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 };
 
 /* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
-        &omap3xxx_dss__l3,
-};
-
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3430es1_dss_core_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_core_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
-        &omap3430es1_l4_core__dss,
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
-        &omap3xxx_l4_core__dss,
-};
-
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
         /*
          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
@@ -1460,10 +592,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
         },
         .opt_clks       = dss_opt_clks,
         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap3430es1_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
-        .masters        = omap3xxx_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 };
 
@@ -1485,10 +613,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
         },
         .opt_clks       = dss_opt_clks,
         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap3xxx_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
-        .masters        = omap3xxx_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 };
 
 /*
@@ -1513,27 +637,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = {
         .sysc   = &omap3_dispc_sysc,
 };
 
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_dispc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_dispc_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
-        &omap3xxx_l4_core__dss_dispc,
-};
-
 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
         .name           = "dss_dispc",
         .class          = &omap3_dispc_hwmod_class,
@@ -1546,8 +649,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
                         .module_offs = OMAP3430_DSS_MOD,
                 },
         },
-        .slaves         = omap3xxx_dss_dispc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
         .flags          = HWMOD_NO_IDLEST,
         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 };
@@ -1567,36 +668,6 @@ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 };
 
 /* dss_dsi1 */
-static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
-        {
-                .pa_start       = 0x4804FC00,
-                .pa_end         = 0x4804FFFF,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_dsi1_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap3xxx_dss_dsi1_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_dsi1 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
-        &omap3xxx_l4_core__dss_dsi1,
-};
-
 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 };
@@ -1615,32 +686,9 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
         },
         .opt_clks       = dss_dsi1_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
-        .slaves         = omap3xxx_dss_dsi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_rfbi_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_rfbi_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
-        &omap3xxx_l4_core__dss_rfbi,
-};
-
 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
         { .role = "ick", .clk = "dss_ick" },
 };
@@ -1658,32 +706,9 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
         },
         .opt_clks       = dss_rfbi_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
-        .slaves         = omap3xxx_dss_rfbi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
         .flags          = HWMOD_NO_IDLEST,
 };
 
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_venc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_venc_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
-        &omap3xxx_l4_core__dss_venc,
-};
-
 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
         /* required only on OMAP3430 */
         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
@@ -1702,13 +727,10 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
         },
         .opt_clks       = dss_venc_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
-        .slaves         = omap3xxx_dss_venc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
         .flags          = HWMOD_NO_IDLEST,
 };
 
 /* I2C1 */
-
 static struct omap_i2c_dev_attr i2c1_dev_attr = {
         .fifo_depth     = 8, /* bytes */
         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1716,10 +738,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
-        &omap3_l4_core__i2c1,
-};
-
 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
         .name           = "i2c1",
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1735,14 +753,11 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_i2c1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c1_dev_attr,
 };
 
 /* I2C2 */
-
 static struct omap_i2c_dev_attr i2c2_dev_attr = {
         .fifo_depth     = 8, /* bytes */
         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1750,10 +765,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
-        &omap3_l4_core__i2c2,
-};
-
 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
         .name           = "i2c2",
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1769,14 +780,11 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_i2c2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c2_dev_attr,
 };
 
 /* I2C3 */
-
 static struct omap_i2c_dev_attr i2c3_dev_attr = {
         .fifo_depth     = 64, /* bytes */
         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1795,10 +803,6 @@ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
-        &omap3_l4_core__i2c3,
-};
-
 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
         .name           = "i2c3",
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1814,114 +818,10 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_i2c3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
         .class          = &i2c_class,
         .dev_attr       = &i2c3_dev_attr,
 };
 
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
-        {
-                .pa_start       = 0x48310000,
-                .pa_end         = 0x483101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
-        .master         = &omap3xxx_l4_wkup_hwmod,
-        .slave          = &omap3xxx_gpio1_hwmod,
-        .addr           = omap3xxx_gpio1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio2 */
-static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
-        {
-                .pa_start       = 0x49050000,
-                .pa_end         = 0x490501ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio2_hwmod,
-        .addr           = omap3xxx_gpio2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio3 */
-static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
-        {
-                .pa_start       = 0x49052000,
-                .pa_end         = 0x490521ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio3_hwmod,
-        .addr           = omap3xxx_gpio3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio4 */
-static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
-        {
-                .pa_start       = 0x49054000,
-                .pa_end         = 0x490541ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio4_hwmod,
-        .addr           = omap3xxx_gpio4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio5 */
-static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
-        {
-                .pa_start       = 0x49056000,
-                .pa_end         = 0x490561ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio5_hwmod,
-        .addr           = omap3xxx_gpio5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio6 */
-static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
-        {
-                .pa_start       = 0x49058000,
-                .pa_end         = 0x490581ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio6_hwmod,
-        .addr           = omap3xxx_gpio6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /*
  * 'gpio' class
  * general purpose io module
@@ -1944,7 +844,7 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
         .rev = 1,
 };
 
-/* gpio_dev_attr*/
+/* gpio_dev_attr */
 static struct omap_gpio_dev_attr gpio_dev_attr = {
         .bank_width = 32,
         .dbck_flag = true,
@@ -1955,10 +855,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio1_dbck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
-        &omap3xxx_l4_wkup__gpio1,
-};
-
 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
         .name           = "gpio1",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1975,8 +871,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_gpio1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
 };
@@ -1986,10 +880,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio2_dbck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
-        &omap3xxx_l4_per__gpio2,
-};
-
 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
         .name           = "gpio2",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2006,8 +896,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_gpio2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
 };
@@ -2017,10 +905,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio3_dbck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
-        &omap3xxx_l4_per__gpio3,
-};
-
 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
         .name           = "gpio3",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2037,8 +921,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_gpio3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
 };
@@ -2048,10 +930,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio4_dbck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
-        &omap3xxx_l4_per__gpio4,
-};
-
 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
         .name           = "gpio4",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2068,8 +946,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_gpio4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
 };
@@ -2084,10 +960,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio5_dbck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
-        &omap3xxx_l4_per__gpio5,
-};
-
 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
         .name           = "gpio5",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2104,8 +976,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_gpio5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
 };
@@ -2120,10 +990,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio6_dbck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
-        &omap3xxx_l4_per__gpio6,
-};
-
 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
         .name           = "gpio6",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2140,20 +1006,10 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_gpio6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
         .class          = &omap3xxx_gpio_hwmod_class,
         .dev_attr       = &gpio_dev_attr,
 };
 
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
-        .master         = &omap3xxx_dma_system_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* dma attributes */
 static struct omap_dma_dev_attr dma_dev_attr = {
         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -2180,34 +1036,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
 };
 
 /* dma_system */
-static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
-        {
-                .pa_start       = 0x48056000,
-                .pa_end         = 0x48056fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
-        &omap3xxx_dma_system__l3,
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dma_system_hwmod,
-        .clk            = "core_l4_ick",
-        .addr           = omap3xxx_dma_system_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
-        &omap3xxx_l4_core__dma_system,
-};
-
 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
         .name           = "dma",
         .class          = &omap3xxx_dma_hwmod_class,
@@ -2222,10 +1050,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_dma_system_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
-        .masters        = omap3xxx_dma_system_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
         .dev_attr       = &dma_dev_attr,
         .flags          = HWMOD_NO_IDLEST,
 };
@@ -2252,36 +1076,12 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
 
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
-        { .name = "irq", .irq = 16 },
+        { .name = "common", .irq = 16 },
         { .name = "tx", .irq = 59 },
         { .name = "rx", .irq = 60 },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48074000,
-                .pa_end         = 0x480740ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mcbsp1_hwmod,
-        .clk            = "mcbsp1_ick",
-        .addr           = omap3xxx_mcbsp1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
-        &omap3xxx_l4_core__mcbsp1,
-};
-
 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap3xxx_mcbsp_hwmod_class,
@@ -2297,42 +1097,16 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mcbsp1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
 };
 
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
-        { .name = "irq", .irq = 17 },
+        { .name = "common", .irq = 17 },
         { .name = "tx", .irq = 62 },
         { .name = "rx", .irq = 63 },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x49022000,
-                .pa_end         = 0x490220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp2_hwmod,
-        .clk            = "mcbsp2_ick",
-        .addr           = omap3xxx_mcbsp2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
-        &omap3xxx_l4_per__mcbsp2,
-};
-
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
         .sidetone       = "mcbsp2_sidetone",
 };
@@ -2352,45 +1126,19 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mcbsp2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
 };
 
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
-        { .name = "irq", .irq = 22 },
+        { .name = "common", .irq = 22 },
         { .name = "tx", .irq = 89 },
         { .name = "rx", .irq = 90 },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x49024000,
-                .pa_end         = 0x490240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp3_hwmod,
-        .clk            = "mcbsp3_ick",
-        .addr           = omap3xxx_mcbsp3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
-        &omap3xxx_l4_per__mcbsp3,
-};
-
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
-        .sidetone       = "mcbsp3_sidetone",
+        .sidetone       = "mcbsp3_sidetone",
 };
 
 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
@@ -2408,14 +1156,12 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mcbsp3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
 };
 
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
-        { .name = "irq", .irq = 23 },
+        { .name = "common", .irq = 23 },
         { .name = "tx", .irq = 54 },
         { .name = "rx", .irq = 55 },
         { .irq = -1 }
@@ -2427,30 +1173,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x49026000,
-                .pa_end         = 0x490260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp4_hwmod,
-        .clk            = "mcbsp4_ick",
-        .addr           = omap3xxx_mcbsp4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
-        &omap3xxx_l4_per__mcbsp4,
-};
-
 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
         .name           = "mcbsp4",
         .class          = &omap3xxx_mcbsp_hwmod_class,
@@ -2466,13 +1188,11 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mcbsp4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
 };
 
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
-        { .name = "irq", .irq = 27 },
+        { .name = "common", .irq = 27 },
         { .name = "tx", .irq = 81 },
         { .name = "rx", .irq = 82 },
         { .irq = -1 }
@@ -2484,30 +1204,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_core -> mcbsp5 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mcbsp5_hwmod,
-        .clk            = "mcbsp5_ick",
-        .addr           = omap3xxx_mcbsp5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp5 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
-        &omap3xxx_l4_core__mcbsp5,
-};
-
 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
         .name           = "mcbsp5",
         .class          = &omap3xxx_mcbsp_hwmod_class,
@@ -2523,11 +1219,9 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mcbsp5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
 };
-/* 'mcbsp sidetone' class */
 
+/* 'mcbsp sidetone' class */
 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
         .sysc_offs      = 0x0010,
         .sysc_flags     = SYSC_HAS_AUTOIDLE,
@@ -2545,30 +1239,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
-        {
-                .name           = "sidetone",
-                .pa_start       = 0x49028000,
-                .pa_end         = 0x490280ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcbsp2_sidetone */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
-        .clk            = "mcbsp2_ick",
-        .addr           = omap3xxx_mcbsp2_sidetone_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* mcbsp2_sidetone slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
-        &omap3xxx_l4_per__mcbsp2_sidetone,
-};
-
 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
         .name           = "mcbsp2_sidetone",
         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2583,8 +1253,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
 };
 
 /* mcbsp3_sidetone */
@@ -2593,30 +1261,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
-        {
-                .name           = "sidetone",
-                .pa_start       = 0x4902A000,
-                .pa_end         = 0x4902A0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcbsp3_sidetone */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
-        .clk            = "mcbsp3_ick",
-        .addr           = omap3xxx_mcbsp3_sidetone_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* mcbsp3_sidetone slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
-        &omap3xxx_l4_per__mcbsp3_sidetone,
-};
-
 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
         .name           = "mcbsp3_sidetone",
         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2631,11 +1275,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
 };
 
-
 /* SR common */
 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
         .clkact_shift   = 20,
@@ -2656,7 +1297,7 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
 
 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
         .sidle_shift    = 24,
-        .enwkup_shift   = 26
+        .enwkup_shift   = 26,
 };
 
 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
@@ -2678,12 +1319,13 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
         .sensor_voltdm_name   = "mpu_iva",
 };
 
-static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
-        &omap3_l4_core__sr1,
+static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
+        { .irq = 18 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod omap34xx_sr1_hwmod = {
-        .name           = "sr1_hwmod",
+        .name           = "sr1",
         .class          = &omap34xx_smartreflex_hwmod_class,
         .main_clk       = "sr1_fck",
         .prcm           = {
@@ -2695,15 +1337,13 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
                 },
         },
-        .slaves         = omap3_sr1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
         .dev_attr       = &sr1_dev_attr,
         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 static struct omap_hwmod omap36xx_sr1_hwmod = {
-        .name           = "sr1_hwmod",
+        .name           = "sr1",
         .class          = &omap36xx_smartreflex_hwmod_class,
         .main_clk       = "sr1_fck",
         .prcm           = {
@@ -2715,8 +1355,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
                 },
         },
-        .slaves         = omap3_sr1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
         .dev_attr       = &sr1_dev_attr,
         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
 };
@@ -2726,12 +1364,13 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
         .sensor_voltdm_name     = "core",
 };
 
-static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
-        &omap3_l4_core__sr2,
+static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
+        { .irq = 19 },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod omap34xx_sr2_hwmod = {
-        .name           = "sr2_hwmod",
+        .name           = "sr2",
         .class          = &omap34xx_smartreflex_hwmod_class,
         .main_clk       = "sr2_fck",
         .prcm           = {
@@ -2743,15 +1382,13 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
                 },
         },
-        .slaves         = omap3_sr2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
         .dev_attr       = &sr2_dev_attr,
         .mpu_irqs       = omap3_smartreflex_core_irqs,
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
 static struct omap_hwmod omap36xx_sr2_hwmod = {
-        .name           = "sr2_hwmod",
+        .name           = "sr2",
         .class          = &omap36xx_smartreflex_hwmod_class,
         .main_clk       = "sr2_fck",
         .prcm           = {
@@ -2763,8 +1400,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
                 },
         },
-        .slaves         = omap3_sr2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
         .dev_attr       = &sr2_dev_attr,
         .mpu_irqs       = omap3_smartreflex_core_irqs,
 };
@@ -2790,34 +1425,11 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
         .sysc = &omap3xxx_mailbox_sysc,
 };
 
-static struct omap_hwmod omap3xxx_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
         { .irq = 26 },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x48094000,
-                .pa_end         = 0x480941ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mailbox_hwmod,
-        .addr           = omap3xxx_mailbox_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
-        &omap3xxx_l4_core__mailbox,
-};
-
 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap3xxx_mailbox_hwmod_class,
@@ -2832,53 +1444,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mailbox_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
-};
-
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_mcspi1,
-        .clk            = "mcspi1_ick",
-        .addr           = omap2_mcspi1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_mcspi2,
-        .clk            = "mcspi2_ick",
-        .addr           = omap2_mcspi2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_mcspi3,
-        .clk            = "mcspi3_ick",
-        .addr           = omap2430_mcspi3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 core -> mcspi4 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
-        {
-                .pa_start       = 0x480ba000,
-                .pa_end         = 0x480ba0ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_mcspi4,
-        .clk            = "mcspi4_ick",
-        .addr           = omap34xx_mcspi4_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /*
@@ -2905,10 +1470,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
 };
 
 /* mcspi1 */
-static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
-        &omap34xx_l4_core__mcspi1,
-};
-
 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
         .num_chipselect = 4,
 };
@@ -2927,17 +1488,11 @@ static struct omap_hwmod omap34xx_mcspi1 = {
                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
                 },
         },
-        .slaves         = omap34xx_mcspi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
         .class          = &omap34xx_mcspi_class,
         .dev_attr       = &omap_mcspi1_dev_attr,
 };
 
 /* mcspi2 */
-static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
-        &omap34xx_l4_core__mcspi2,
-};
-
 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
         .num_chipselect = 2,
 };
@@ -2956,8 +1511,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
                 },
         },
-        .slaves         = omap34xx_mcspi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
         .class          = &omap34xx_mcspi_class,
         .dev_attr       = &omap_mcspi2_dev_attr,
 };
@@ -2976,10 +1529,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
-        &omap34xx_l4_core__mcspi3,
-};
-
 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
         .num_chipselect = 2,
 };
@@ -2998,13 +1547,11 @@ static struct omap_hwmod omap34xx_mcspi3 = {
                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
                 },
         },
-        .slaves         = omap34xx_mcspi3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
         .class          = &omap34xx_mcspi_class,
         .dev_attr       = &omap_mcspi3_dev_attr,
 };
 
-/* SPI4 */
+/* mcspi4 */
 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
         { .irq = -1 }
@@ -3016,10 +1563,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
-        &omap34xx_l4_core__mcspi4,
-};
-
 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
         .num_chipselect = 1,
 };
@@ -3038,15 +1581,11 @@ static struct omap_hwmod omap34xx_mcspi4 = {
                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
                 },
         },
-        .slaves         = omap34xx_mcspi4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
         .class          = &omap34xx_mcspi_class,
         .dev_attr       = &omap_mcspi4_dev_attr,
 };
 
-/*
- * usbhsotg
- */
+/* usbhsotg */
 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
         .rev_offs       = 0x0400,
         .sysc_offs      = 0x0404,
@@ -3063,6 +1602,7 @@ static struct omap_hwmod_class usbotg_class = {
         .name = "usbotg",
         .sysc = &omap3xxx_usbhsotg_sysc,
 };
+
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
 
@@ -3085,10 +1625,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
                 },
         },
-        .masters        = omap3xxx_usbhsotg_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
-        .slaves         = omap3xxx_usbhsotg_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
         .class          = &usbotg_class,
 
         /*
@@ -3120,15 +1656,10 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
                 .omap2 = {
                 },
         },
-        .masters        = am35xx_usbhsotg_masters,
-        .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
-        .slaves         = am35xx_usbhsotg_slaves,
-        .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
         .class          = &am35xx_usbotg_class,
 };
 
 /* MMC/SD/SDIO common */
-
 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
         .rev_offs       = 0x1fc,
         .sysc_offs      = 0x10,
@@ -3162,10 +1693,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
         { .role = "dbck", .clk = "omap_32k_fck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
-        &omap3xxx_l4_core__mmc1,
-};
-
 static struct omap_mmc_dev_attr mmc1_dev_attr = {
         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -3193,8 +1720,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
                 },
         },
         .dev_attr       = &mmc1_pre_es3_dev_attr,
-        .slaves         = omap3xxx_mmc1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
         .class          = &omap34xx_mmc_class,
 };
 
@@ -3215,8 +1740,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
                 },
         },
         .dev_attr       = &mmc1_dev_attr,
-        .slaves         = omap3xxx_mmc1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
         .class          = &omap34xx_mmc_class,
 };
 
@@ -3237,10 +1760,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
         { .role = "dbck", .clk = "omap_32k_fck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
-        &omap3xxx_l4_core__mmc2,
-};
-
 /* See 35xx errata 2.1.1.128 in SPRZ278F */
 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
@@ -3263,8 +1782,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
                 },
         },
         .dev_attr       = &mmc2_pre_es3_dev_attr,
-        .slaves         = omap3xxx_mmc2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
         .class          = &omap34xx_mmc_class,
 };
 
@@ -3284,8 +1801,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mmc2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
         .class          = &omap34xx_mmc_class,
 };
 
@@ -3306,10 +1821,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
         { .role = "dbck", .clk = "omap_32k_fck", },
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
-        &omap3xxx_l4_core__mmc3,
-};
-
 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
         .name           = "mmc3",
         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
@@ -3325,8 +1836,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
                 },
         },
-        .slaves         = omap3xxx_mmc3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
         .class          = &omap34xx_mmc_class,
 };
 
@@ -3334,12 +1843,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
  * 'usb_host_hs' class
  * high-speed multi-port usb host controller
  */
-static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
-        .master         = &omap3xxx_usb_host_hs_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
-        .user           = OCP_USER_MPU,
-};
 
 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
         .rev_offs       = 0x0000,
@@ -3358,42 +1861,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
         .sysc = &omap3xxx_usb_host_hs_sysc,
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
-        &omap3xxx_usb_host_hs__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
-        {
-                .name           = "uhh",
-                .pa_start       = 0x48064000,
-                .pa_end         = 0x480643ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "ohci",
-                .pa_start       = 0x48064400,
-                .pa_end         = 0x480647ff,
-        },
-        {
-                .name           = "ehci",
-                .pa_start       = 0x48064800,
-                .pa_end         = 0x48064cff,
-        },
-        {}
-};
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_usb_host_hs_hwmod,
-        .clk            = "usbhost_ick",
-        .addr           = omap3xxx_usb_host_hs_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
-        &omap3xxx_l4_core__usb_host_hs,
-};
-
 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
 };
@@ -3422,10 +1889,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
         },
         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
-        .slaves         = omap3xxx_usb_host_hs_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
-        .masters        = omap3xxx_usb_host_hs_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
 
         /*
          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3501,6 +1964,1134 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
         { .irq = -1 }
 };
 
+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap3xxx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
+        .main_clk       = "usbtll_fck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 3,
+                        .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+                        .idlest_reg_id = 3,
+                        .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
+                },
+        },
+};
+
+static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
+        .name           = "hdq1w",
+        .mpu_irqs       = omap2_hdq1w_mpu_irqs,
+        .main_clk       = "hdq_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_HDQ_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
+                },
+        },
+        .class          = &omap2_hdq1w_class,
+};
+
+/*
+ * '32K sync counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0004,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
+        .name   = "counter",
+        .sysc   = &omap3xxx_counter_sysc,
+};
+
+static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .class          = &omap3xxx_counter_hwmod_class,
+        .clkdm_name     = "wkup_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "wkup_32k_fck",
+        .prcm           = {
+                .omap2  = {
+                        .module_offs = WKUP_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
+                },
+        },
+};
+
+/*
+ * interfaces
+ */
+
+/* L3 -> L4_CORE interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
+        .master = &omap3xxx_l3_main_hwmod,
+        .slave  = &omap3xxx_l4_core_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L3 -> L4_PER interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
+        .master = &omap3xxx_l3_main_hwmod,
+        .slave  = &omap3xxx_l4_per_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
+        {
+                .pa_start       = 0x68000000,
+                .pa_end         = 0x6800ffff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* MPU -> L3 interface */
+static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
+        .master   = &omap3xxx_mpu_hwmod,
+        .slave    = &omap3xxx_l3_main_hwmod,
+        .addr     = omap3xxx_l3_main_addrs,
+        .user   = OCP_USER_MPU,
+};
+
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
+        .master         = &omap3430es1_dss_core_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
+        .master         = &omap3xxx_dss_core_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_core -> usbhsotg interface */
+static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
+        .master         = &omap3xxx_usbhsotg_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3_core -> am35xx_usbhsotg interface */
+static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
+        .master         = &am35xx_usbhsotg_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+/* L4_CORE -> L4_WKUP interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
+        .master = &omap3xxx_l4_core_hwmod,
+        .slave  = &omap3xxx_l4_wkup_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_es3plus_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
+        .clk            = "mmchs2_ick",
+        .addr           = omap2430_mmc2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_es3plus_mmc2_hwmod,
+        .clk            = "mmchs2_ick",
+        .addr           = omap2430_mmc2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+/* L4 CORE -> MMC3 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
+        {
+                .pa_start       = 0x480ad000,
+                .pa_end         = 0x480ad1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmc3_hwmod,
+        .clk            = "mmchs3_ick",
+        .addr           = omap3xxx_mmc3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART1_BASE,
+                .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap3xxx_uart1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART2_BASE,
+                .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap3xxx_uart2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART3_BASE,
+                .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap3xxx_uart3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART4 interface */
+static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_BASE,
+                .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap36xx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = omap36xx_uart4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* AM35xx: L4 CORE -> UART4 interface */
+static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_AM35XX_BASE,
+                .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = am35xx_uart4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap2_i2c1_addr_space,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
+                        .l4_prot_group = 7,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2_i2c2_addr_space,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
+                        .l4_prot_group = 7,
+                        .flags = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C3 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+        {
+                .pa_start       = 0x48060000,
+                .pa_end         = 0x48060000 + SZ_128 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c3_hwmod,
+        .clk            = "i2c3_ick",
+        .addr           = omap3xxx_i2c3_addr_space,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
+                        .l4_prot_group = 7,
+                        .flags = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
+        {
+                .pa_start       = OMAP34XX_SR1_BASE,
+                .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_sr1_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap36xx_sr1_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+        {
+                .pa_start       = OMAP34XX_SR2_BASE,
+                .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_sr2_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap36xx_sr2_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
+        {
+                .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
+                .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> usbhsotg  */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usbhsotg_hwmod,
+        .clk            = "l4_ick",
+        .addr           = omap3xxx_usbhsotg_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
+        {
+                .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
+                .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> usbhsotg  */
+static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_usbhsotg_hwmod,
+        .clk            = "l4_ick",
+        .addr           = am35xx_usbhsotg_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* L4_WKUP -> L4_SEC interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
+        .master = &omap3xxx_l4_wkup_hwmod,
+        .slave  = &omap3xxx_l4_sec_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_iva_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48318000,
+                .pa_end         = 0x48318000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap3xxx_timer1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x49032000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap3xxx_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x49034000,
+                .pa_end         = 0x49034000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap3xxx_timer3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x49036000,
+                .pa_end         = 0x49036000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap3xxx_timer4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x49038000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap3xxx_timer5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4903A000,
+                .pa_end         = 0x4903A000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer6 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap3xxx_timer6_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4903C000,
+                .pa_end         = 0x4903C000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer7 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap3xxx_timer7_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4903E000,
+                .pa_end         = 0x4903E000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer8 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap3xxx_timer8_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x49040000,
+                .pa_end         = 0x49040000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap3xxx_timer9_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2_timer10_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2_timer11_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
+        .master         = &omap3xxx_l4_sec_hwmod,
+        .slave          = &omap3xxx_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap3xxx_timer12_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48314000,
+                .pa_end         = 0x4831407f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_wd_timer2_hwmod,
+        .clk            = "wdt2_ick",
+        .addr           = omap3xxx_wd_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3430es1_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_dispc_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
+        {
+                .pa_start       = 0x4804FC00,
+                .pa_end         = 0x4804FFFF,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_dsi1_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_dsi1_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_rfbi_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_venc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_venc_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .flags          = OCPIF_SWSUP_IDLE,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x48310000,
+                .pa_end         = 0x483101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_gpio1_hwmod,
+        .addr           = omap3xxx_gpio1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x49050000,
+                .pa_end         = 0x490501ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio2_hwmod,
+        .addr           = omap3xxx_gpio2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x49052000,
+                .pa_end         = 0x490521ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio3_hwmod,
+        .addr           = omap3xxx_gpio3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
+        {
+                .pa_start       = 0x49054000,
+                .pa_end         = 0x490541ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio4_hwmod,
+        .addr           = omap3xxx_gpio4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
+        {
+                .pa_start       = 0x49056000,
+                .pa_end         = 0x490561ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio5_hwmod,
+        .addr           = omap3xxx_gpio5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
+        {
+                .pa_start       = 0x49058000,
+                .pa_end         = 0x490581ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio6_hwmod,
+        .addr           = omap3xxx_gpio6_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
+        .master         = &omap3xxx_dma_system_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x48056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dma_system_hwmod,
+        .clk            = "core_l4_ick",
+        .addr           = omap3xxx_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap3xxx_mcbsp1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49022000,
+                .pa_end         = 0x490220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap3xxx_mcbsp2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49024000,
+                .pa_end         = 0x490240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap3xxx_mcbsp3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49026000,
+                .pa_end         = 0x490260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap3xxx_mcbsp4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap3xxx_mcbsp5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
+        {
+                .name           = "sidetone",
+                .pa_start       = 0x49028000,
+                .pa_end         = 0x490280ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcbsp2_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap3xxx_mcbsp2_sidetone_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
+        {
+                .name           = "sidetone",
+                .pa_start       = 0x4902A000,
+                .pa_end         = 0x4902A0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcbsp3_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap3xxx_mcbsp3_sidetone_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mailbox_hwmod,
+        .addr           = omap3xxx_mailbox_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi1,
+        .clk            = "mcspi1_ick",
+        .addr           = omap2_mcspi1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi2,
+        .clk            = "mcspi2_ick",
+        .addr           = omap2_mcspi2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi3,
+        .clk            = "mcspi3_ick",
+        .addr           = omap2430_mcspi3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> mcspi4 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
+        {
+                .pa_start       = 0x480ba000,
+                .pa_end         = 0x480ba0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi4,
+        .clk            = "mcspi4_ick",
+        .addr           = omap34xx_mcspi4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
+        .master         = &omap3xxx_usb_host_hs_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
+        {
+                .name           = "uhh",
+                .pa_start       = 0x48064000,
+                .pa_end         = 0x480643ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "ohci",
+                .pa_start       = 0x48064400,
+                .pa_end         = 0x480647ff,
+        },
+        {
+                .name           = "ehci",
+                .pa_start       = 0x48064800,
+                .pa_end         = 0x48064cff,
+        },
+        {}
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usb_host_hs_hwmod,
+        .clk            = "usbhost_ick",
+        .addr           = omap3xxx_usb_host_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
         {
                 .name           = "tll",
@@ -3519,183 +3110,187 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
-        &omap3xxx_l4_core__usb_tll_hs,
+/* l4_core -> hdq1w interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_hdq1w_hwmod,
+        .clk            = "hdq_ick",
+        .addr           = omap2_hdq1w_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 };
 
-static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
-        .name           = "usb_tll_hs",
-        .class          = &omap3xxx_usb_tll_hs_hwmod_class,
-        .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
-        .main_clk       = "usbtll_fck",
-        .prcm = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 3,
-                        .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
-                        .idlest_reg_id = 3,
-                        .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
-                },
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
+        {
+                .pa_start       = 0x48320000,
+                .pa_end         = 0x4832001f,
+                .flags          = ADDR_TYPE_RT
         },
-        .slaves         = omap3xxx_usb_tll_hs_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
-};
-
-static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
-        &omap3xxx_l3_main_hwmod,
-        &omap3xxx_l4_core_hwmod,
-        &omap3xxx_l4_per_hwmod,
-        &omap3xxx_l4_wkup_hwmod,
-        &omap3xxx_mmc3_hwmod,
-        &omap3xxx_mpu_hwmod,
-
-        &omap3xxx_timer1_hwmod,
-        &omap3xxx_timer2_hwmod,
-        &omap3xxx_timer3_hwmod,
-        &omap3xxx_timer4_hwmod,
-        &omap3xxx_timer5_hwmod,
-        &omap3xxx_timer6_hwmod,
-        &omap3xxx_timer7_hwmod,
-        &omap3xxx_timer8_hwmod,
-        &omap3xxx_timer9_hwmod,
-        &omap3xxx_timer10_hwmod,
-        &omap3xxx_timer11_hwmod,
-
-        &omap3xxx_wd_timer2_hwmod,
-        &omap3xxx_uart1_hwmod,
-        &omap3xxx_uart2_hwmod,
-        &omap3xxx_uart3_hwmod,
-
-        /* i2c class */
-        &omap3xxx_i2c1_hwmod,
-        &omap3xxx_i2c2_hwmod,
-        &omap3xxx_i2c3_hwmod,
-
-        /* gpio class */
-        &omap3xxx_gpio1_hwmod,
-        &omap3xxx_gpio2_hwmod,
-        &omap3xxx_gpio3_hwmod,
-        &omap3xxx_gpio4_hwmod,
-        &omap3xxx_gpio5_hwmod,
-        &omap3xxx_gpio6_hwmod,
-
-        /* dma_system class*/
-        &omap3xxx_dma_system_hwmod,
-
-        /* mcbsp class */
-        &omap3xxx_mcbsp1_hwmod,
-        &omap3xxx_mcbsp2_hwmod,
-        &omap3xxx_mcbsp3_hwmod,
-        &omap3xxx_mcbsp4_hwmod,
-        &omap3xxx_mcbsp5_hwmod,
-        &omap3xxx_mcbsp2_sidetone_hwmod,
-        &omap3xxx_mcbsp3_sidetone_hwmod,
-
-
-        /* mcspi class */
-        &omap34xx_mcspi1,
-        &omap34xx_mcspi2,
-        &omap34xx_mcspi3,
-        &omap34xx_mcspi4,
+        { }
+};
 
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_counter_32k_hwmod,
+        .clk            = "omap_32ksync_ick",
+        .addr           = omap3xxx_counter_32k_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l3_main__l4_core,
+        &omap3xxx_l3_main__l4_per,
+        &omap3xxx_mpu__l3_main,
+        &omap3xxx_l4_core__l4_wkup,
+        &omap3xxx_l4_core__mmc3,
+        &omap3_l4_core__uart1,
+        &omap3_l4_core__uart2,
+        &omap3_l4_per__uart3,
+        &omap3_l4_core__i2c1,
+        &omap3_l4_core__i2c2,
+        &omap3_l4_core__i2c3,
+        &omap3xxx_l4_wkup__l4_sec,
+        &omap3xxx_l4_wkup__timer1,
+        &omap3xxx_l4_per__timer2,
+        &omap3xxx_l4_per__timer3,
+        &omap3xxx_l4_per__timer4,
+        &omap3xxx_l4_per__timer5,
+        &omap3xxx_l4_per__timer6,
+        &omap3xxx_l4_per__timer7,
+        &omap3xxx_l4_per__timer8,
+        &omap3xxx_l4_per__timer9,
+        &omap3xxx_l4_core__timer10,
+        &omap3xxx_l4_core__timer11,
+        &omap3xxx_l4_wkup__wd_timer2,
+        &omap3xxx_l4_wkup__gpio1,
+        &omap3xxx_l4_per__gpio2,
+        &omap3xxx_l4_per__gpio3,
+        &omap3xxx_l4_per__gpio4,
+        &omap3xxx_l4_per__gpio5,
+        &omap3xxx_l4_per__gpio6,
+        &omap3xxx_dma_system__l3,
+        &omap3xxx_l4_core__dma_system,
+        &omap3xxx_l4_core__mcbsp1,
+        &omap3xxx_l4_per__mcbsp2,
+        &omap3xxx_l4_per__mcbsp3,
+        &omap3xxx_l4_per__mcbsp4,
+        &omap3xxx_l4_core__mcbsp5,
+        &omap3xxx_l4_per__mcbsp2_sidetone,
+        &omap3xxx_l4_per__mcbsp3_sidetone,
+        &omap34xx_l4_core__mcspi1,
+        &omap34xx_l4_core__mcspi2,
+        &omap34xx_l4_core__mcspi3,
+        &omap34xx_l4_core__mcspi4,
+        &omap3xxx_l4_wkup__counter_32k,
         NULL,
 };
 
-/* GP-only hwmods */
-static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
-        &omap3xxx_timer12_hwmod,
+/* GP-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l4_sec__timer12,
         NULL
 };
 
-/* 3430ES1-only hwmods */
-static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
-        &omap3430es1_dss_core_hwmod,
+/* 3430ES1-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
+        &omap3430es1_dss__l3,
+        &omap3430es1_l4_core__dss,
         NULL
 };
 
-/* 3430ES2+-only hwmods */
-static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
-        &omap3xxx_dss_core_hwmod,
-        &omap3xxx_usbhsotg_hwmod,
-        &omap3xxx_usb_host_hs_hwmod,
-        &omap3xxx_usb_tll_hs_hwmod,
+/* 3430ES2+-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_dss__l3,
+        &omap3xxx_l4_core__dss,
+        &omap3xxx_usbhsotg__l3,
+        &omap3xxx_l4_core__usbhsotg,
+        &omap3xxx_usb_host_hs__l3_main_2,
+        &omap3xxx_l4_core__usb_host_hs,
+        &omap3xxx_l4_core__usb_tll_hs,
         NULL
 };
 
-/* <= 3430ES3-only hwmods */
-static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
-        &omap3xxx_pre_es3_mmc1_hwmod,
-        &omap3xxx_pre_es3_mmc2_hwmod,
+/* <= 3430ES3-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l4_core__pre_es3_mmc1,
+        &omap3xxx_l4_core__pre_es3_mmc2,
         NULL
 };
 
-/* 3430ES3+-only hwmods */
-static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
-        &omap3xxx_es3plus_mmc1_hwmod,
-        &omap3xxx_es3plus_mmc2_hwmod,
+/* 3430ES3+-only hwmod links */
+static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l4_core__es3plus_mmc1,
+        &omap3xxx_l4_core__es3plus_mmc2,
         NULL
 };
 
-/* 34xx-only hwmods (all ES revisions) */
-static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
-        &omap3xxx_iva_hwmod,
-        &omap34xx_sr1_hwmod,
-        &omap34xx_sr2_hwmod,
-        &omap3xxx_mailbox_hwmod,
+/* 34xx-only hwmod links (all ES revisions) */
+static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l3__iva,
+        &omap34xx_l4_core__sr1,
+        &omap34xx_l4_core__sr2,
+        &omap3xxx_l4_core__mailbox,
+        &omap3xxx_l4_core__hdq1w,
         NULL
 };
 
-/* 36xx-only hwmods (all ES revisions) */
-static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
-        &omap3xxx_iva_hwmod,
-        &omap3xxx_uart4_hwmod,
-        &omap3xxx_dss_core_hwmod,
-        &omap36xx_sr1_hwmod,
-        &omap36xx_sr2_hwmod,
-        &omap3xxx_usbhsotg_hwmod,
-        &omap3xxx_mailbox_hwmod,
-        &omap3xxx_usb_host_hs_hwmod,
-        &omap3xxx_usb_tll_hs_hwmod,
-        &omap3xxx_es3plus_mmc1_hwmod,
-        &omap3xxx_es3plus_mmc2_hwmod,
+/* 36xx-only hwmod links (all ES revisions) */
+static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l3__iva,
+        &omap36xx_l4_per__uart4,
+        &omap3xxx_dss__l3,
+        &omap3xxx_l4_core__dss,
+        &omap36xx_l4_core__sr1,
+        &omap36xx_l4_core__sr2,
+        &omap3xxx_usbhsotg__l3,
+        &omap3xxx_l4_core__usbhsotg,
+        &omap3xxx_l4_core__mailbox,
+        &omap3xxx_usb_host_hs__l3_main_2,
+        &omap3xxx_l4_core__usb_host_hs,
+        &omap3xxx_l4_core__usb_tll_hs,
+        &omap3xxx_l4_core__es3plus_mmc1,
+        &omap3xxx_l4_core__es3plus_mmc2,
+        &omap3xxx_l4_core__hdq1w,
         NULL
 };
 
-static __initdata struct omap_hwmod *am35xx_hwmods[] = {
-        &omap3xxx_dss_core_hwmod, /* XXX ??? */
-        &am35xx_usbhsotg_hwmod,
-        &am35xx_uart4_hwmod,
-        &omap3xxx_usb_host_hs_hwmod,
-        &omap3xxx_usb_tll_hs_hwmod,
-        &omap3xxx_es3plus_mmc1_hwmod,
-        &omap3xxx_es3plus_mmc2_hwmod,
+static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_dss__l3,
+        &omap3xxx_l4_core__dss,
+        &am35xx_usbhsotg__l3,
+        &am35xx_l4_core__usbhsotg,
+        &am35xx_l4_core__uart4,
+        &omap3xxx_usb_host_hs__l3_main_2,
+        &omap3xxx_l4_core__usb_host_hs,
+        &omap3xxx_l4_core__usb_tll_hs,
+        &omap3xxx_l4_core__es3plus_mmc1,
+        &omap3xxx_l4_core__es3plus_mmc2,
         NULL
 };
 
-static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
-        /* dss class */
-        &omap3xxx_dss_dispc_hwmod,
-        &omap3xxx_dss_dsi1_hwmod,
-        &omap3xxx_dss_rfbi_hwmod,
-        &omap3xxx_dss_venc_hwmod,
+static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l4_core__dss_dispc,
+        &omap3xxx_l4_core__dss_dsi1,
+        &omap3xxx_l4_core__dss_rfbi,
+        &omap3xxx_l4_core__dss_venc,
         NULL
 };
 
 int __init omap3xxx_hwmod_init(void)
 {
         int r;
-        struct omap_hwmod **h = NULL;
+        struct omap_hwmod_ocp_if **h = NULL;
         unsigned int rev;
 
-        /* Register hwmods common to all OMAP3 */
-        r = omap_hwmod_register(omap3xxx_hwmods);
+        /* Register hwmod links common to all OMAP3 */
+        r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
         if (r < 0)
                 return r;
 
-        /* Register GP-only hwmods. */
+        /* Register GP-only hwmod links. */
         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
-                r = omap_hwmod_register(omap3xxx_gp_hwmods);
+                r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
                 if (r < 0)
                         return r;
         }
@@ -3703,43 +3298,43 @@ int __init omap3xxx_hwmod_init(void)
         rev = omap_rev();
 
         /*
-         * Register hwmods common to individual OMAP3 families, all
+         * Register hwmod links common to individual OMAP3 families, all
          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
          * All possible revisions should be included in this conditional.
          */
         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
-                h = omap34xx_hwmods;
-        } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
-                h = am35xx_hwmods;
+                h = omap34xx_hwmod_ocp_ifs;
+        } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
+                h = am35xx_hwmod_ocp_ifs;
         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
                    rev == OMAP3630_REV_ES1_2) {
-                h = omap36xx_hwmods;
+                h = omap36xx_hwmod_ocp_ifs;
         } else {
                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
                 return -EINVAL;
         };
 
-        r = omap_hwmod_register(h);
+        r = omap_hwmod_register_links(h);
         if (r < 0)
                 return r;
 
         /*
-         * Register hwmods specific to certain ES levels of a
+         * Register hwmod links specific to certain ES levels of a
          * particular family of silicon (e.g., 34xx ES1.0)
          */
         h = NULL;
         if (rev == OMAP3430_REV_ES1_0) {
-                h = omap3430es1_hwmods;
+                h = omap3430es1_hwmod_ocp_ifs;
         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
                    rev == OMAP3430_REV_ES3_1_2) {
-                h = omap3430es2plus_hwmods;
+                h = omap3430es2plus_hwmod_ocp_ifs;
         };
 
         if (h) {
-                r = omap_hwmod_register(h);
+                r = omap_hwmod_register_links(h);
                 if (r < 0)
                         return r;
         }
@@ -3747,29 +3342,29 @@ int __init omap3xxx_hwmod_init(void)
         h = NULL;
         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
             rev == OMAP3430_REV_ES2_1) {
-                h = omap3430_pre_es3_hwmods;
+                h = omap3430_pre_es3_hwmod_ocp_ifs;
         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
                    rev == OMAP3430_REV_ES3_1_2) {
-                h = omap3430_es3plus_hwmods;
+                h = omap3430_es3plus_hwmod_ocp_ifs;
         };
 
         if (h)
-                r = omap_hwmod_register(h);
+                r = omap_hwmod_register_links(h);
         if (r < 0)
                 return r;
 
         /*
          * DSS code presumes that dss_core hwmod is handled first,
          * _before_ any other DSS related hwmods so register common
-         * DSS hwmods last to ensure that dss_core is already registered.
-         * Otherwise some change things may happen, for ex. if dispc
-         * is handled before dss_core and DSS is enabled in bootloader
-         * DIPSC will be reset with outputs enabled which sometimes leads
-         * to unrecoverable L3 error.
-         * XXX The long-term fix to this is to ensure modules are set up
-         * in dependency order in the hwmod core code.
+         * DSS hwmod links last to ensure that dss_core is already
+         * registered.  Otherwise some change things may happen, for
+         * ex. if dispc is handled before dss_core and DSS is enabled
+         * in bootloader DISPC will be reset with outputs enabled
+         * which sometimes leads to unrecoverable L3 error.  XXX The
+         * long-term fix to this is to ensure hwmods are set up in
+         * dependency order in the hwmod core code.
          */
-        r = omap_hwmod_register(omap3xxx_dss_hwmods);
+        r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
 
         return r;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 6abc75753e42..950454a3fa31 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1,7 +1,7 @@
 /*
  * Hardware modules present on the OMAP44xx chips
  *
- * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
  * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley
@@ -44,41 +44,34 @@
 #define OMAP44XX_IRQ_GIC_START  32
 
 /* Base offset for all OMAP4 dma requests */
-#define OMAP44XX_DMA_REQ_START  1
-
-/* Backward references (IPs with Bus Master capability) */
-static struct omap_hwmod omap44xx_aess_hwmod;
-static struct omap_hwmod omap44xx_dma_system_hwmod;
-static struct omap_hwmod omap44xx_dmm_hwmod;
-static struct omap_hwmod omap44xx_dsp_hwmod;
-static struct omap_hwmod omap44xx_dss_hwmod;
-static struct omap_hwmod omap44xx_emif_fw_hwmod;
-static struct omap_hwmod omap44xx_hsi_hwmod;
-static struct omap_hwmod omap44xx_ipu_hwmod;
-static struct omap_hwmod omap44xx_iss_hwmod;
-static struct omap_hwmod omap44xx_iva_hwmod;
-static struct omap_hwmod omap44xx_l3_instr_hwmod;
-static struct omap_hwmod omap44xx_l3_main_1_hwmod;
-static struct omap_hwmod omap44xx_l3_main_2_hwmod;
-static struct omap_hwmod omap44xx_l3_main_3_hwmod;
-static struct omap_hwmod omap44xx_l4_abe_hwmod;
-static struct omap_hwmod omap44xx_l4_cfg_hwmod;
-static struct omap_hwmod omap44xx_l4_per_hwmod;
-static struct omap_hwmod omap44xx_l4_wkup_hwmod;
-static struct omap_hwmod omap44xx_mmc1_hwmod;
-static struct omap_hwmod omap44xx_mmc2_hwmod;
-static struct omap_hwmod omap44xx_mpu_hwmod;
-static struct omap_hwmod omap44xx_mpu_private_hwmod;
-static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
+#define OMAP44XX_DMA_REQ_START  1
 
 /*
- * Interconnects omap_hwmod structures
- * hwmods that compose the global OMAP interconnect
+ * IP blocks
  */
 
 /*
+ * 'c2c_target_fw' class
+ * instance(s): c2c_target_fw
+ */
+static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
+        .name   = "c2c_target_fw",
+};
+
+/* c2c_target_fw */
+static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
+        .name           = "c2c_target_fw",
+        .class          = &omap44xx_c2c_target_fw_hwmod_class,
+        .clkdm_name     = "d2d_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
  * 'dmm' class
  * instance(s): dmm
  */
@@ -92,51 +85,17 @@ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
         { .irq = -1 }
 };
 
-/* l3_main_1 -> dmm */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_dmm_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
-        {
-                .pa_start       = 0x4e000000,
-                .pa_end         = 0x4e0007ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* mpu -> dmm */
-static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
-        .master         = &omap44xx_mpu_hwmod,
-        .slave          = &omap44xx_dmm_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_dmm_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* dmm slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
-        &omap44xx_l3_main_1__dmm,
-        &omap44xx_mpu__dmm,
-};
-
 static struct omap_hwmod omap44xx_dmm_hwmod = {
         .name           = "dmm",
         .class          = &omap44xx_dmm_hwmod_class,
         .clkdm_name     = "l3_emif_clkdm",
+        .mpu_irqs       = omap44xx_dmm_irqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_dmm_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
-        .mpu_irqs       = omap44xx_dmm_irqs,
 };
 
 /*
@@ -148,38 +107,6 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 };
 
 /* emif_fw */
-/* dmm -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
-        .master         = &omap44xx_dmm_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
-        {
-                .pa_start       = 0x4a20c000,
-                .pa_end         = 0x4a20c0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_emif_fw_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* emif_fw slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
-        &omap44xx_dmm__emif_fw,
-        &omap44xx_l4_cfg__emif_fw,
-};
-
 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
         .name           = "emif_fw",
         .class          = &omap44xx_emif_fw_hwmod_class,
@@ -190,8 +117,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_emif_fw_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 };
 
 /*
@@ -203,28 +128,6 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 };
 
 /* l3_instr */
-/* iva -> l3_instr */
-static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
-        .master         = &omap44xx_iva_hwmod,
-        .slave          = &omap44xx_l3_instr_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_3 -> l3_instr */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
-        .master         = &omap44xx_l3_main_3_hwmod,
-        .slave          = &omap44xx_l3_instr_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_instr slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
-        &omap44xx_iva__l3_instr,
-        &omap44xx_l3_main_3__l3_instr,
-};
-
 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
         .name           = "l3_instr",
         .class          = &omap44xx_l3_hwmod_class,
@@ -236,8 +139,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .slaves         = omap44xx_l3_instr_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 };
 
 /* l3_main_1 */
@@ -247,83 +148,6 @@ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
         { .irq = -1 }
 };
 
-/* dsp -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
-        .master         = &omap44xx_dsp_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
-        .master         = &omap44xx_dss_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc1 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
-        .master         = &omap44xx_mmc1_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
-        .master         = &omap44xx_mmc2_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
-        {
-                .pa_start       = 0x44000000,
-                .pa_end         = 0x44000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* mpu -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
-        .master         = &omap44xx_mpu_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_1_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* l3_main_1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
-        &omap44xx_dsp__l3_main_1,
-        &omap44xx_dss__l3_main_1,
-        &omap44xx_l3_main_2__l3_main_1,
-        &omap44xx_l4_cfg__l3_main_1,
-        &omap44xx_mmc1__l3_main_1,
-        &omap44xx_mmc2__l3_main_1,
-        &omap44xx_mpu__l3_main_1,
-};
-
 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
         .name           = "l3_main_1",
         .class          = &omap44xx_l3_hwmod_class,
@@ -335,97 +159,9 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_l3_main_1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 };
 
 /* l3_main_2 */
-/* dma_system -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
-        .master         = &omap44xx_dma_system_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* hsi -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
-        .master         = &omap44xx_hsi_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* ipu -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
-        .master         = &omap44xx_ipu_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* iss -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
-        .master         = &omap44xx_iss_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* iva -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
-        .master         = &omap44xx_iva_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
-        {
-                .pa_start       = 0x44800000,
-                .pa_end         = 0x44801fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_1 -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_2_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* l4_cfg -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* usb_otg_hs -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
-        .master         = &omap44xx_usb_otg_hs_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
-        &omap44xx_dma_system__l3_main_2,
-        &omap44xx_hsi__l3_main_2,
-        &omap44xx_ipu__l3_main_2,
-        &omap44xx_iss__l3_main_2,
-        &omap44xx_iva__l3_main_2,
-        &omap44xx_l3_main_1__l3_main_2,
-        &omap44xx_l4_cfg__l3_main_2,
-        &omap44xx_usb_otg_hs__l3_main_2,
-};
-
 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
         .name           = "l3_main_2",
         .class          = &omap44xx_l3_hwmod_class,
@@ -436,52 +172,9 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_l3_main_2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 };
 
 /* l3_main_3 */
-static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
-        {
-                .pa_start       = 0x45000000,
-                .pa_end         = 0x45000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_1 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_l3_main_3_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_3_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_l3_main_3_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_l3_main_3_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
-        &omap44xx_l3_main_1__l3_main_3,
-        &omap44xx_l3_main_2__l3_main_3,
-        &omap44xx_l4_cfg__l3_main_3,
-};
-
 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
         .name           = "l3_main_3",
         .class          = &omap44xx_l3_hwmod_class,
@@ -493,8 +186,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .slaves         = omap44xx_l3_main_3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 };
 
 /*
@@ -506,46 +197,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 };
 
 /* l4_abe */
-/* aess -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
-        .master         = &omap44xx_aess_hwmod,
-        .slave          = &omap44xx_l4_abe_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dsp -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
-        .master         = &omap44xx_dsp_hwmod,
-        .slave          = &omap44xx_l4_abe_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_l4_abe_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
-        .master         = &omap44xx_mpu_hwmod,
-        .slave          = &omap44xx_l4_abe_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
-        &omap44xx_aess__l4_abe,
-        &omap44xx_dsp__l4_abe,
-        &omap44xx_l3_main_1__l4_abe,
-        &omap44xx_mpu__l4_abe,
-};
-
 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
         .name           = "l4_abe",
         .class          = &omap44xx_l4_hwmod_class,
@@ -555,24 +206,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
                 },
         },
-        .slaves         = omap44xx_l4_abe_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 };
 
 /* l4_cfg */
-/* l3_main_1 -> l4_cfg */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_l4_cfg_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
-        &omap44xx_l3_main_1__l4_cfg,
-};
-
 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
         .name           = "l4_cfg",
         .class          = &omap44xx_l4_hwmod_class,
@@ -583,24 +219,9 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_l4_cfg_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 };
 
 /* l4_per */
-/* l3_main_2 -> l4_per */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_l4_per_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
-        &omap44xx_l3_main_2__l4_per,
-};
-
 static struct omap_hwmod omap44xx_l4_per_hwmod = {
         .name           = "l4_per",
         .class          = &omap44xx_l4_hwmod_class,
@@ -611,24 +232,9 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_l4_per_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 };
 
 /* l4_wkup */
-/* l4_cfg -> l4_wkup */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_l4_wkup_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
-        &omap44xx_l4_cfg__l4_wkup,
-};
-
 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
         .name           = "l4_wkup",
         .class          = &omap44xx_l4_hwmod_class,
@@ -639,8 +245,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_l4_wkup_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 };
 
 /*
@@ -652,25 +256,32 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 };
 
 /* mpu_private */
-/* mpu -> mpu_private */
-static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
-        .master         = &omap44xx_mpu_hwmod,
-        .slave          = &omap44xx_mpu_private_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu_private slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
-        &omap44xx_mpu__mpu_private,
-};
-
 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
         .name           = "mpu_private",
         .class          = &omap44xx_mpu_bus_hwmod_class,
         .clkdm_name     = "mpuss_clkdm",
-        .slaves         = omap44xx_mpu_private_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
+};
+
+/*
+ * 'ocp_wp_noc' class
+ * instance(s): ocp_wp_noc
+ */
+static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
+        .name   = "ocp_wp_noc",
+};
+
+/* ocp_wp_noc */
+static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
+        .name           = "ocp_wp_noc",
+        .class          = &omap44xx_ocp_wp_noc_hwmod_class,
+        .clkdm_name     = "l3_instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
 };
 
 /*
@@ -681,41 +292,7 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  * - They still need to be validated with the driver
  *   properly adapted to omap_hwmod / omap_device
  *
- *  c2c
- *  c2c_target_fw
- *  cm_core
- *  cm_core_aon
- *  ctrl_module_core
- *  ctrl_module_pad_core
- *  ctrl_module_pad_wkup
- *  ctrl_module_wkup
- *  debugss
- *  efuse_ctrl_cust
- *  efuse_ctrl_std
- *  elm
- *  emif1
- *  emif2
- *  fdif
- *  gpmc
- *  gpu
- *  hdq1w
- *  mcasp
- *  mpu_c0
- *  mpu_c1
- *  ocmc_ram
- *  ocp2scp_usb_phy
- *  ocp_wp_noc
- *  prcm_mpu
- *  prm
- *  scrm
- *  sl2if
- *  slimbus1
- *  slimbus2
- *  usb_host_fs
- *  usb_host_hs
- *  usb_phy_cm
- *  usb_tll_hs
- *  usim
+ * usim
  */
 
 /*
@@ -756,53 +333,6 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-/* aess master ports */
-static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
-        &omap44xx_aess__l4_abe,
-};
-
-static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
-        {
-                .pa_start       = 0x401f1000,
-                .pa_end         = 0x401f13ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> aess */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_aess_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_aess_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
-        {
-                .pa_start       = 0x490f1000,
-                .pa_end         = 0x490f13ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> aess (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_aess_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_aess_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* aess slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
-        &omap44xx_l4_abe__aess,
-        &omap44xx_l4_abe__aess_dma,
-};
-
 static struct omap_hwmod omap44xx_aess_hwmod = {
         .name           = "aess",
         .class          = &omap44xx_aess_hwmod_class,
@@ -817,37 +347,41 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_aess_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
-        .masters        = omap44xx_aess_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 };
 
 /*
- * 'bandgap' class
- * bangap reference for ldo regulators
+ * 'c2c' class
+ * chip 2 chip interface used to plug the ape soc (omap) with an external modem
+ * soc
  */
 
-static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
-        .name   = "bandgap",
+static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
+        .name   = "c2c",
 };
 
-/* bandgap */
-static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
-        { .role = "fclk", .clk = "bandgap_fclk" },
+/* c2c */
+static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
+        { .irq = 88 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
 
-static struct omap_hwmod omap44xx_bandgap_hwmod = {
-        .name           = "bandgap",
-        .class          = &omap44xx_bandgap_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
+static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
+        { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap44xx_c2c_hwmod = {
+        .name           = "c2c",
+        .class          = &omap44xx_c2c_hwmod_class,
+        .clkdm_name     = "d2d_clkdm",
+        .mpu_irqs       = omap44xx_c2c_irqs,
+        .sdma_reqs      = omap44xx_c2c_sdma_reqs,
         .prcm = {
                 .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
+                        .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
                 },
         },
-        .opt_clks       = bandgap_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 };
 
 /*
@@ -870,30 +404,6 @@ static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 };
 
 /* counter_32k */
-static struct omap_hwmod omap44xx_counter_32k_hwmod;
-static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
-        {
-                .pa_start       = 0x4a304000,
-                .pa_end         = 0x4a30401f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_counter_32k_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_counter_32k_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* counter_32k slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
-        &omap44xx_l4_wkup__counter_32k,
-};
-
 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
         .name           = "counter_32k",
         .class          = &omap44xx_counter_hwmod_class,
@@ -906,8 +416,83 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_counter_32k_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
+};
+
+/*
+ * 'ctrl_module' class
+ * attila core control module + core pad control module + wkup pad control
+ * module + attila wkup control module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
+        .name   = "ctrl_module",
+        .sysc   = &omap44xx_ctrl_module_sysc,
+};
+
+/* ctrl_module_core */
+static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
+        { .irq = 8 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
+        .name           = "ctrl_module_core",
+        .class          = &omap44xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "l4_cfg_clkdm",
+        .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
+};
+
+/* ctrl_module_pad_core */
+static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
+        .name           = "ctrl_module_pad_core",
+        .class          = &omap44xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "l4_cfg_clkdm",
+};
+
+/* ctrl_module_wkup */
+static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
+        .name           = "ctrl_module_wkup",
+        .class          = &omap44xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/* ctrl_module_pad_wkup */
+static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
+        .name           = "ctrl_module_pad_wkup",
+        .class          = &omap44xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/*
+ * 'debugss' class
+ * debug and emulation sub system
+ */
+
+static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
+        .name   = "debugss",
+};
+
+/* debugss */
+static struct omap_hwmod omap44xx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &omap44xx_debugss_hwmod_class,
+        .clkdm_name     = "emu_sys_clkdm",
+        .main_clk       = "trace_clk_div_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
+                },
+        },
 };
 
 /*
@@ -950,34 +535,6 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
         { .irq = -1 }
 };
 
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
-        &omap44xx_dma_system__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
-        {
-                .pa_start       = 0x4a056000,
-                .pa_end         = 0x4a056fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_dma_system_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dma_system_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
-        &omap44xx_l4_cfg__dma_system,
-};
-
 static struct omap_hwmod omap44xx_dma_system_hwmod = {
         .name           = "dma_system",
         .class          = &omap44xx_dma_hwmod_class,
@@ -991,10 +548,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
                 },
         },
         .dev_attr       = &dma_dev_attr,
-        .slaves         = omap44xx_dma_system_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
-        .masters        = omap44xx_dma_system_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 };
 
 /*
@@ -1018,7 +571,6 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 };
 
 /* dmic */
-static struct omap_hwmod omap44xx_dmic_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -1029,50 +581,6 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4012e000,
-                .pa_end         = 0x4012e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> dmic */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_dmic_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_dmic_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x4902e000,
-                .pa_end         = 0x4902e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> dmic (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_dmic_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_dmic_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* dmic slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
-        &omap44xx_l4_abe__dmic,
-        &omap44xx_l4_abe__dmic_dma,
-};
-
 static struct omap_hwmod omap44xx_dmic_hwmod = {
         .name           = "dmic",
         .class          = &omap44xx_dmic_hwmod_class,
@@ -1087,8 +595,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_dmic_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
 };
 
 /*
@@ -1107,53 +613,8 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 };
 
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
-        { .name = "mmu_cache", .rst_shift = 1 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
         { .name = "dsp", .rst_shift = 0 },
-};
-
-/* dsp -> iva */
-static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
-        .master         = &omap44xx_dsp_hwmod,
-        .slave          = &omap44xx_iva_hwmod,
-        .clk            = "dpll_iva_m5x2_ck",
-};
-
-/* dsp master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
-        &omap44xx_dsp__l3_main_1,
-        &omap44xx_dsp__l4_abe,
-        &omap44xx_dsp__iva,
-};
-
-/* l4_cfg -> dsp */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_dsp_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dsp slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
-        &omap44xx_l4_cfg__dsp,
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
-        .name           = "dsp_c0",
-        .class          = &omap44xx_dsp_hwmod_class,
-        .clkdm_name     = "tesla_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_dsp_c0_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
-                },
-        },
+        { .name = "mmu_cache", .rst_shift = 1 },
 };
 
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1172,10 +633,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .slaves         = omap44xx_dsp_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
-        .masters        = omap44xx_dsp_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
 };
 
 /*
@@ -1196,53 +653,6 @@ static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 };
 
 /* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
-        &omap44xx_dss__l3_main_1,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
-        {
-                .pa_start       = 0x58000000,
-                .pa_end         = 0x5800007f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_2 -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
-        {
-                .pa_start       = 0x48040000,
-                .pa_end         = 0x4804007f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
-        &omap44xx_l3_main_2__dss,
-        &omap44xx_l4_per__dss,
-};
-
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
         { .role = "sys_clk", .clk = "dss_sys_clk" },
         { .role = "tv_clk", .clk = "dss_tv_clk" },
@@ -1263,10 +673,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
         },
         .opt_clks       = dss_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap44xx_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
-        .masters        = omap44xx_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
 };
 
 /*
@@ -1293,7 +699,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 };
 
 /* dss_dispc */
-static struct omap_hwmod omap44xx_dss_dispc_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -1304,53 +709,11 @@ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
-        {
-                .pa_start       = 0x58001000,
-                .pa_end         = 0x58001fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_2 -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_dispc_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_dispc_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
-        {
-                .pa_start       = 0x48041000,
-                .pa_end         = 0x48041fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
         .manager_count          = 3,
         .has_framedonetv_irq    = 1
 };
 
-/* l4_per -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_dispc_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_dispc_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
-        &omap44xx_l3_main_2__dss_dispc,
-        &omap44xx_l4_per__dss_dispc,
-};
-
 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
         .name           = "dss_dispc",
         .class          = &omap44xx_dispc_hwmod_class,
@@ -1364,8 +727,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_dss_dispc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 };
 
@@ -1391,7 +752,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 };
 
 /* dss_dsi1 */
-static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -1402,48 +762,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
-        {
-                .pa_start       = 0x58004000,
-                .pa_end         = 0x580041ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_2 -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_dsi1_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_dsi1_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
-        {
-                .pa_start       = 0x48044000,
-                .pa_end         = 0x480441ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_dsi1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_dsi1_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* dss_dsi1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
-        &omap44xx_l3_main_2__dss_dsi1,
-        &omap44xx_l4_per__dss_dsi1,
-};
-
 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
         { .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -1463,12 +781,9 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
         },
         .opt_clks       = dss_dsi1_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
-        .slaves         = omap44xx_dss_dsi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
 };
 
 /* dss_dsi2 */
-static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -1479,48 +794,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
-        {
-                .pa_start       = 0x58005000,
-                .pa_end         = 0x580051ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_2 -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_dsi2_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_dsi2_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
-        {
-                .pa_start       = 0x48045000,
-                .pa_end         = 0x480451ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_dsi2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_dsi2_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* dss_dsi2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
-        &omap44xx_l3_main_2__dss_dsi2,
-        &omap44xx_l4_per__dss_dsi2,
-};
-
 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
         { .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -1540,8 +813,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
         },
         .opt_clks       = dss_dsi2_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
-        .slaves         = omap44xx_dss_dsi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
 };
 
 /*
@@ -1565,7 +836,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 };
 
 /* dss_hdmi */
-static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -1576,48 +846,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
-        {
-                .pa_start       = 0x58006000,
-                .pa_end         = 0x58006fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_2 -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_hdmi_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_hdmi_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
-        {
-                .pa_start       = 0x48046000,
-                .pa_end         = 0x48046fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_hdmi_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_hdmi_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* dss_hdmi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
-        &omap44xx_l3_main_2__dss_hdmi,
-        &omap44xx_l4_per__dss_hdmi,
-};
-
 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
         { .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -1637,8 +865,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
         },
         .opt_clks       = dss_hdmi_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
-        .slaves         = omap44xx_dss_hdmi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
 };
 
 /*
@@ -1662,54 +888,11 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 };
 
 /* dss_rfbi */
-static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
-        {
-                .pa_start       = 0x58002000,
-                .pa_end         = 0x580020ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_2 -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_rfbi_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_rfbi_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
-        {
-                .pa_start       = 0x48042000,
-                .pa_end         = 0x480420ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_rfbi_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_rfbi_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
-        &omap44xx_l3_main_2__dss_rfbi,
-        &omap44xx_l4_per__dss_rfbi,
-};
-
 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
         { .role = "ick", .clk = "dss_fck" },
 };
@@ -1728,8 +911,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
         },
         .opt_clks       = dss_rfbi_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
-        .slaves         = omap44xx_dss_rfbi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
 };
 
 /*
@@ -1742,62 +923,165 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 };
 
 /* dss_venc */
-static struct omap_hwmod omap44xx_dss_venc_hwmod;
-static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
-        {
-                .pa_start       = 0x58003000,
-                .pa_end         = 0x580030ff,
-                .flags          = ADDR_TYPE_RT
+static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap44xx_venc_hwmod_class,
+        .clkdm_name     = "l3_dss_clkdm",
+        .main_clk       = "dss_tv_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+                },
         },
-        { }
 };
 
-/* l3_main_2 -> dss_venc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_venc_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_venc_dma_addrs,
-        .user           = OCP_USER_SDMA,
+/*
+ * 'elm' class
+ * bch error location module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
-static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
-        {
-                .pa_start       = 0x48043000,
-                .pa_end         = 0x480430ff,
-                .flags          = ADDR_TYPE_RT
+static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
+        .name   = "elm",
+        .sysc   = &omap44xx_elm_sysc,
+};
+
+/* elm */
+static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
+        { .irq = 4 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_elm_hwmod = {
+        .name           = "elm",
+        .class          = &omap44xx_elm_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
+        .mpu_irqs       = omap44xx_elm_irqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
+                },
         },
-        { }
 };
 
-/* l4_per -> dss_venc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_venc_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_venc_addrs,
-        .user           = OCP_USER_MPU,
+/*
+ * 'emif' class
+ * external memory interface no1
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
+        .rev_offs       = 0x0000,
 };
 
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
-        &omap44xx_l3_main_2__dss_venc,
-        &omap44xx_l4_per__dss_venc,
+static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
+        .name   = "emif",
+        .sysc   = &omap44xx_emif_sysc,
 };
 
-static struct omap_hwmod omap44xx_dss_venc_hwmod = {
-        .name           = "dss_venc",
-        .class          = &omap44xx_venc_hwmod_class,
-        .clkdm_name     = "l3_dss_clkdm",
-        .main_clk       = "dss_tv_clk",
+/* emif1 */
+static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
+        { .irq = 110 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_emif1_hwmod = {
+        .name           = "emif1",
+        .class          = &omap44xx_emif_hwmod_class,
+        .clkdm_name     = "l3_emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_emif1_irqs,
+        .main_clk       = "ddrphy_ck",
         .prcm = {
                 .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+                        .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/* emif2 */
+static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
+        { .irq = 111 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_emif2_hwmod = {
+        .name           = "emif2",
+        .class          = &omap44xx_emif_hwmod_class,
+        .clkdm_name     = "l3_emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_emif2_irqs,
+        .main_clk       = "ddrphy_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'fdif' class
+ * face detection hw accelerator module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        /*
+         * FDIF needs 100 OCP clk cycles delay after a softreset before
+         * accessing sysconfig again.
+         * The lowest frequency at the moment for L3 bus is 100 MHz, so
+         * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
+         *
+         * TODO: Indicate errata when available.
+         */
+        .srst_udelay    = 2,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
+        .name   = "fdif",
+        .sysc   = &omap44xx_fdif_sysc,
+};
+
+/* fdif */
+static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
+        { .irq = 69 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_fdif_hwmod = {
+        .name           = "fdif",
+        .class          = &omap44xx_fdif_hwmod_class,
+        .clkdm_name     = "iss_clkdm",
+        .mpu_irqs       = omap44xx_fdif_irqs,
+        .main_clk       = "fdif_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_dss_venc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
 };
 
 /*
@@ -1830,35 +1114,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
 };
 
 /* gpio1 */
-static struct omap_hwmod omap44xx_gpio1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
-        {
-                .pa_start       = 0x4a310000,
-                .pa_end         = 0x4a3101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_gpio1_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_gpio1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
-        &omap44xx_l4_wkup__gpio1,
-};
-
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio1_dbclk" },
 };
@@ -1879,40 +1139,14 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
         .opt_clks       = gpio1_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
         .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
 };
 
 /* gpio2 */
-static struct omap_hwmod omap44xx_gpio2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
-        {
-                .pa_start       = 0x48055000,
-                .pa_end         = 0x480551ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> gpio2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
-        &omap44xx_l4_per__gpio2,
-};
-
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio2_dbclk" },
 };
@@ -1934,40 +1168,14 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
         .opt_clks       = gpio2_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
         .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
 };
 
 /* gpio3 */
-static struct omap_hwmod omap44xx_gpio3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
-        {
-                .pa_start       = 0x48057000,
-                .pa_end         = 0x480571ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> gpio3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
-        &omap44xx_l4_per__gpio3,
-};
-
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio3_dbclk" },
 };
@@ -1989,40 +1197,14 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
         .opt_clks       = gpio3_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
         .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
 };
 
 /* gpio4 */
-static struct omap_hwmod omap44xx_gpio4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
-        {
-                .pa_start       = 0x48059000,
-                .pa_end         = 0x480591ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> gpio4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
-        &omap44xx_l4_per__gpio4,
-};
-
 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio4_dbclk" },
 };
@@ -2044,40 +1226,14 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
         .opt_clks       = gpio4_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
         .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
 };
 
 /* gpio5 */
-static struct omap_hwmod omap44xx_gpio5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
-        {
-                .pa_start       = 0x4805b000,
-                .pa_end         = 0x4805b1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> gpio5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio5_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
-        &omap44xx_l4_per__gpio5,
-};
-
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio5_dbclk" },
 };
@@ -2099,40 +1255,14 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
         .opt_clks       = gpio5_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
         .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
 };
 
 /* gpio6 */
-static struct omap_hwmod omap44xx_gpio6_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
-        {
-                .pa_start       = 0x4805d000,
-                .pa_end         = 0x4805d1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> gpio6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio6_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gpio6 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
-        &omap44xx_l4_per__gpio6,
-};
-
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio6_dbclk" },
 };
@@ -2154,8 +1284,135 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
         .opt_clks       = gpio6_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
         .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
+};
+
+/*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap44xx_gpmc_sysc,
+};
+
+/* gpmc */
+static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
+        { .irq = 20 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
+        { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap44xx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap44xx_gpmc_hwmod_class,
+        .clkdm_name     = "l3_2_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_gpmc_irqs,
+        .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'gpu' class
+ * 2d/3d graphics accelerator
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
+        .rev_offs       = 0x1fc00,
+        .sysc_offs      = 0x1fc10,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
+        .name   = "gpu",
+        .sysc   = &omap44xx_gpu_sysc,
+};
+
+/* gpu */
+static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
+        { .irq = 21 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_gpu_hwmod = {
+        .name           = "gpu",
+        .class          = &omap44xx_gpu_hwmod_class,
+        .clkdm_name     = "l3_gfx_clkdm",
+        .mpu_irqs       = omap44xx_gpu_irqs,
+        .main_clk       = "gpu_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'hdq1w' class
+ * hdq / 1-wire serial interface controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0014,
+        .syss_offs      = 0x0018,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
+        .name   = "hdq1w",
+        .sysc   = &omap44xx_hdq1w_sysc,
+};
+
+/* hdq1w */
+static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
+        { .irq = 58 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_hdq1w_hwmod = {
+        .name           = "hdq1w",
+        .class          = &omap44xx_hdq1w_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
+        .mpu_irqs       = omap44xx_hdq1w_irqs,
+        .main_clk       = "hdq1w_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
 };
 
 /*
@@ -2190,34 +1447,6 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
         { .irq = -1 }
 };
 
-/* hsi master ports */
-static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
-        &omap44xx_hsi__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
-        {
-                .pa_start       = 0x4a058000,
-                .pa_end         = 0x4a05bfff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> hsi */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_hsi_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_hsi_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* hsi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
-        &omap44xx_l4_cfg__hsi,
-};
-
 static struct omap_hwmod omap44xx_hsi_hwmod = {
         .name           = "hsi",
         .class          = &omap44xx_hsi_hwmod_class,
@@ -2231,10 +1460,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .slaves         = omap44xx_hsi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
-        .masters        = omap44xx_hsi_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
 };
 
 /*
@@ -2262,11 +1487,11 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
 };
 
 static struct omap_i2c_dev_attr i2c_dev_attr = {
-        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+                        OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
 };
 
 /* i2c1 */
-static struct omap_hwmod omap44xx_i2c1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -2278,29 +1503,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
-        {
-                .pa_start       = 0x48070000,
-                .pa_end         = 0x480700ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> i2c1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* i2c1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
-        &omap44xx_l4_per__i2c1,
-};
-
 static struct omap_hwmod omap44xx_i2c1_hwmod = {
         .name           = "i2c1",
         .class          = &omap44xx_i2c_hwmod_class,
@@ -2316,13 +1518,10 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_i2c1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
         .dev_attr       = &i2c_dev_attr,
 };
 
 /* i2c2 */
-static struct omap_hwmod omap44xx_i2c2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -2334,29 +1533,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
-        {
-                .pa_start       = 0x48072000,
-                .pa_end         = 0x480720ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> i2c2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* i2c2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
-        &omap44xx_l4_per__i2c2,
-};
-
 static struct omap_hwmod omap44xx_i2c2_hwmod = {
         .name           = "i2c2",
         .class          = &omap44xx_i2c_hwmod_class,
@@ -2372,13 +1548,10 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_i2c2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
         .dev_attr       = &i2c_dev_attr,
 };
 
 /* i2c3 */
-static struct omap_hwmod omap44xx_i2c3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -2390,29 +1563,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
-        {
-                .pa_start       = 0x48060000,
-                .pa_end         = 0x480600ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> i2c3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* i2c3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
-        &omap44xx_l4_per__i2c3,
-};
-
 static struct omap_hwmod omap44xx_i2c3_hwmod = {
         .name           = "i2c3",
         .class          = &omap44xx_i2c_hwmod_class,
@@ -2428,13 +1578,10 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_i2c3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
         .dev_attr       = &i2c_dev_attr,
 };
 
 /* i2c4 */
-static struct omap_hwmod omap44xx_i2c4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -2446,29 +1593,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
-        {
-                .pa_start       = 0x48350000,
-                .pa_end         = 0x483500ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> i2c4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* i2c4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
-        &omap44xx_l4_per__i2c4,
-};
-
 static struct omap_hwmod omap44xx_i2c4_hwmod = {
         .name           = "i2c4",
         .class          = &omap44xx_i2c_hwmod_class,
@@ -2484,8 +1608,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_i2c4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
         .dev_attr       = &i2c_dev_attr,
 };
 
@@ -2504,66 +1626,12 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
         { .irq = -1 }
 };
 
-static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
+static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
         { .name = "cpu0", .rst_shift = 0 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
         { .name = "cpu1", .rst_shift = 1 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
         { .name = "mmu_cache", .rst_shift = 2 },
 };
 
-/* ipu master ports */
-static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
-        &omap44xx_ipu__l3_main_2,
-};
-
-/* l3_main_2 -> ipu */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_ipu_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* ipu slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
-        &omap44xx_l3_main_2__ipu,
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
-        .name           = "ipu_c0",
-        .class          = &omap44xx_ipu_hwmod_class,
-        .clkdm_name     = "ducati_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_ipu_c0_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
-                },
-        },
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
-        .name           = "ipu_c1",
-        .class          = &omap44xx_ipu_hwmod_class,
-        .clkdm_name     = "ducati_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_ipu_c1_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
-                },
-        },
-};
-
 static struct omap_hwmod omap44xx_ipu_hwmod = {
         .name           = "ipu",
         .class          = &omap44xx_ipu_hwmod_class,
@@ -2580,10 +1648,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .slaves         = omap44xx_ipu_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
-        .masters        = omap44xx_ipu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
 };
 
 /*
@@ -2630,34 +1694,6 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-/* iss master ports */
-static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
-        &omap44xx_iss__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
-        {
-                .pa_start       = 0x52000000,
-                .pa_end         = 0x520000ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_2 -> iss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_iss_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_iss_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* iss slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
-        &omap44xx_l3_main_2__iss,
-};
-
 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
 };
@@ -2678,10 +1714,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
         },
         .opt_clks       = iss_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
-        .slaves         = omap44xx_iss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
-        .masters        = omap44xx_iss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
 };
 
 /*
@@ -2702,75 +1734,9 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
 };
 
 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
-        { .name = "logic", .rst_shift = 2 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
         { .name = "seq0", .rst_shift = 0 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
         { .name = "seq1", .rst_shift = 1 },
-};
-
-/* iva master ports */
-static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
-        &omap44xx_iva__l3_main_2,
-        &omap44xx_iva__l3_instr,
-};
-
-static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
-        {
-                .pa_start       = 0x5a000000,
-                .pa_end         = 0x5a07ffff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l3_main_2 -> iva */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_iva_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_iva_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* iva slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
-        &omap44xx_dsp__iva,
-        &omap44xx_l3_main_2__iva,
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
-        .name           = "iva_seq0",
-        .class          = &omap44xx_iva_hwmod_class,
-        .clkdm_name     = "ivahd_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_iva_seq0_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
-                },
-        },
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
-        .name           = "iva_seq1",
-        .class          = &omap44xx_iva_hwmod_class,
-        .clkdm_name     = "ivahd_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_iva_seq1_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
-                },
-        },
+        { .name = "logic", .rst_shift = 2 },
 };
 
 static struct omap_hwmod omap44xx_iva_hwmod = {
@@ -2789,10 +1755,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .slaves         = omap44xx_iva_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
-        .masters        = omap44xx_iva_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
 };
 
 /*
@@ -2818,35 +1780,11 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
 };
 
 /* kbd */
-static struct omap_hwmod omap44xx_kbd_hwmod;
 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
-        {
-                .pa_start       = 0x4a31c000,
-                .pa_end         = 0x4a31c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_wkup -> kbd */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_kbd_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_kbd_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* kbd slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
-        &omap44xx_l4_wkup__kbd,
-};
-
 static struct omap_hwmod omap44xx_kbd_hwmod = {
         .name           = "kbd",
         .class          = &omap44xx_kbd_hwmod_class,
@@ -2860,8 +1798,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_kbd_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
 };
 
 /*
@@ -2885,35 +1821,11 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
 };
 
 /* mailbox */
-static struct omap_hwmod omap44xx_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x4a0f4000,
-                .pa_end         = 0x4a0f41ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> mailbox */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_mailbox_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mailbox_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
-        &omap44xx_l4_cfg__mailbox,
-};
-
 static struct omap_hwmod omap44xx_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap44xx_mailbox_hwmod_class,
@@ -2925,8 +1837,58 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_mailbox_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
+};
+
+/*
+ * 'mcasp' class
+ * multi-channel audio serial port controller
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
+        .sidle_shift    = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
+        .sysc_offs      = 0x0004,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
+};
+
+static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
+        .name   = "mcasp",
+        .sysc   = &omap44xx_mcasp_sysc,
+};
+
+/* mcasp */
+static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
+        { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
+        { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
+        { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
+        { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap44xx_mcasp_hwmod = {
+        .name           = "mcasp",
+        .class          = &omap44xx_mcasp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .mpu_irqs       = omap44xx_mcasp_irqs,
+        .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
+        .main_clk       = "mcasp_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
 };
 
 /*
@@ -2949,9 +1911,8 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
 };
 
 /* mcbsp1 */
-static struct omap_hwmod omap44xx_mcbsp1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
-        { .irq = 17 + OMAP44XX_IRQ_GIC_START },
+        { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
@@ -2961,50 +1922,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40122000,
-                .pa_end         = 0x401220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp1_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp1_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49022000,
-                .pa_end         = 0x490220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> mcbsp1 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp1_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp1_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
-        &omap44xx_l4_abe__mcbsp1,
-        &omap44xx_l4_abe__mcbsp1_dma,
-};
-
 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
         { .role = "pad_fck", .clk = "pad_clks_ck" },
         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
@@ -3024,16 +1941,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mcbsp1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
         .opt_clks       = mcbsp1_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
 };
 
 /* mcbsp2 */
-static struct omap_hwmod omap44xx_mcbsp2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
-        { .irq = 22 + OMAP44XX_IRQ_GIC_START },
+        { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
@@ -3043,50 +1957,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40124000,
-                .pa_end         = 0x401240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp2_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp2_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49024000,
-                .pa_end         = 0x490240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> mcbsp2 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp2_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp2_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
-        &omap44xx_l4_abe__mcbsp2,
-        &omap44xx_l4_abe__mcbsp2_dma,
-};
-
 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
         { .role = "pad_fck", .clk = "pad_clks_ck" },
         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
@@ -3106,16 +1976,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mcbsp2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
         .opt_clks       = mcbsp2_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
 };
 
 /* mcbsp3 */
-static struct omap_hwmod omap44xx_mcbsp3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
-        { .irq = 23 + OMAP44XX_IRQ_GIC_START },
+        { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
@@ -3125,50 +1992,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40126000,
-                .pa_end         = 0x401260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp3_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp3_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49026000,
-                .pa_end         = 0x490260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> mcbsp3 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp3_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp3_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
-        &omap44xx_l4_abe__mcbsp3,
-        &omap44xx_l4_abe__mcbsp3_dma,
-};
-
 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
         { .role = "pad_fck", .clk = "pad_clks_ck" },
         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
@@ -3188,16 +2011,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mcbsp3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
         .opt_clks       = mcbsp3_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
 };
 
 /* mcbsp4 */
-static struct omap_hwmod omap44xx_mcbsp4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
-        { .irq = 16 + OMAP44XX_IRQ_GIC_START },
+        { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
@@ -3207,29 +2027,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
-        {
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcbsp4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcbsp4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
-        &omap44xx_l4_per__mcbsp4,
-};
-
 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
         { .role = "pad_fck", .clk = "pad_clks_ck" },
         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
@@ -3249,8 +2046,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mcbsp4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
         .opt_clks       = mcbsp4_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
 };
@@ -3277,7 +2072,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
 };
 
 /* mcpdm */
-static struct omap_hwmod omap44xx_mcpdm_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -3289,48 +2083,6 @@ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
-        {
-                .pa_start       = 0x40132000,
-                .pa_end         = 0x4013207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> mcpdm */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcpdm_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcpdm_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
-        {
-                .pa_start       = 0x49032000,
-                .pa_end         = 0x4903207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> mcpdm (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcpdm_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcpdm_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* mcpdm slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
-        &omap44xx_l4_abe__mcpdm,
-        &omap44xx_l4_abe__mcpdm_dma,
-};
-
 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
         .name           = "mcpdm",
         .class          = &omap44xx_mcpdm_hwmod_class,
@@ -3345,8 +2097,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mcpdm_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
 };
 
 /*
@@ -3372,7 +2122,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
 };
 
 /* mcspi1 */
-static struct omap_hwmod omap44xx_mcspi1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -3390,29 +2139,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
-        {
-                .pa_start       = 0x48098000,
-                .pa_end         = 0x480981ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcspi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcspi1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
-        &omap44xx_l4_per__mcspi1,
-};
-
 /* mcspi1 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
         .num_chipselect = 4,
@@ -3433,12 +2159,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
                 },
         },
         .dev_attr       = &mcspi1_dev_attr,
-        .slaves         = omap44xx_mcspi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
 };
 
 /* mcspi2 */
-static struct omap_hwmod omap44xx_mcspi2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -3452,29 +2175,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
-        {
-                .pa_start       = 0x4809a000,
-                .pa_end         = 0x4809a1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcspi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcspi2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
-        &omap44xx_l4_per__mcspi2,
-};
-
 /* mcspi2 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
         .num_chipselect = 2,
@@ -3495,12 +2195,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
                 },
         },
         .dev_attr       = &mcspi2_dev_attr,
-        .slaves         = omap44xx_mcspi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
 };
 
 /* mcspi3 */
-static struct omap_hwmod omap44xx_mcspi3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -3514,29 +2211,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
-        {
-                .pa_start       = 0x480b8000,
-                .pa_end         = 0x480b81ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcspi3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcspi3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
-        &omap44xx_l4_per__mcspi3,
-};
-
 /* mcspi3 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
         .num_chipselect = 2,
@@ -3557,12 +2231,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
                 },
         },
         .dev_attr       = &mcspi3_dev_attr,
-        .slaves         = omap44xx_mcspi3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
 };
 
 /* mcspi4 */
-static struct omap_hwmod omap44xx_mcspi4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -3574,29 +2245,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
-        {
-                .pa_start       = 0x480ba000,
-                .pa_end         = 0x480ba1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mcspi4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mcspi4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
-        &omap44xx_l4_per__mcspi4,
-};
-
 /* mcspi4 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
         .num_chipselect = 1,
@@ -3617,8 +2265,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
                 },
         },
         .dev_attr       = &mcspi4_dev_attr,
-        .slaves         = omap44xx_mcspi4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
 };
 
 /*
@@ -3655,34 +2301,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-/* mmc1 master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
-        &omap44xx_mmc1__l3_main_1,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
-        {
-                .pa_start       = 0x4809c000,
-                .pa_end         = 0x4809c3ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mmc1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
-        &omap44xx_l4_per__mmc1,
-};
-
 /* mmc1 dev_attr */
 static struct omap_mmc_dev_attr mmc1_dev_attr = {
         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
@@ -3703,10 +2321,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
                 },
         },
         .dev_attr       = &mmc1_dev_attr,
-        .slaves         = omap44xx_mmc1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
-        .masters        = omap44xx_mmc1_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
 };
 
 /* mmc2 */
@@ -3721,34 +2335,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-/* mmc2 master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
-        &omap44xx_mmc2__l3_main_1,
-};
-
-static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
-        {
-                .pa_start       = 0x480b4000,
-                .pa_end         = 0x480b43ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mmc2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
-        &omap44xx_l4_per__mmc2,
-};
-
 static struct omap_hwmod omap44xx_mmc2_hwmod = {
         .name           = "mmc2",
         .class          = &omap44xx_mmc_hwmod_class,
@@ -3763,14 +2349,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mmc2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
-        .masters        = omap44xx_mmc2_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
 };
 
 /* mmc3 */
-static struct omap_hwmod omap44xx_mmc3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -3782,29 +2363,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
-        {
-                .pa_start       = 0x480ad000,
-                .pa_end         = 0x480ad3ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mmc3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
-        &omap44xx_l4_per__mmc3,
-};
-
 static struct omap_hwmod omap44xx_mmc3_hwmod = {
         .name           = "mmc3",
         .class          = &omap44xx_mmc_hwmod_class,
@@ -3819,12 +2377,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mmc3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
 };
 
 /* mmc4 */
-static struct omap_hwmod omap44xx_mmc4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -3836,35 +2391,11 @@ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
-        {
-                .pa_start       = 0x480d1000,
-                .pa_end         = 0x480d13ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mmc4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
-        &omap44xx_l4_per__mmc4,
-};
-
 static struct omap_hwmod omap44xx_mmc4_hwmod = {
         .name           = "mmc4",
         .class          = &omap44xx_mmc_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .mpu_irqs       = omap44xx_mmc4_irqs,
-
         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
         .main_clk       = "mmc4_fck",
         .prcm = {
@@ -3874,12 +2405,9 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mmc4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
 };
 
 /* mmc5 */
-static struct omap_hwmod omap44xx_mmc5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -3891,29 +2419,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
-        {
-                .pa_start       = 0x480d5000,
-                .pa_end         = 0x480d53ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> mmc5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc5_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
-        &omap44xx_l4_per__mmc5,
-};
-
 static struct omap_hwmod omap44xx_mmc5_hwmod = {
         .name           = "mmc5",
         .class          = &omap44xx_mmc_hwmod_class,
@@ -3928,8 +2433,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_mmc5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
 };
 
 /*
@@ -3949,13 +2452,6 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
         { .irq = -1 }
 };
 
-/* mpu master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
-        &omap44xx_mpu__l3_main_1,
-        &omap44xx_mpu__l4_abe,
-        &omap44xx_mpu__dmm,
-};
-
 static struct omap_hwmod omap44xx_mpu_hwmod = {
         .name           = "mpu",
         .class          = &omap44xx_mpu_hwmod_class,
@@ -3969,8 +2465,252 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
                 },
         },
-        .masters        = omap44xx_mpu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
+};
+
+/*
+ * 'ocmc_ram' class
+ * top-level core on-chip ram
+ */
+
+static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
+        .name   = "ocmc_ram",
+};
+
+/* ocmc_ram */
+static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
+        .name           = "ocmc_ram",
+        .class          = &omap44xx_ocmc_ram_hwmod_class,
+        .clkdm_name     = "l3_2_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+
+static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
+        .name   = "ocp2scp",
+};
+
+/* ocp2scp_usb_phy */
+static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
+        { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
+};
+
+static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
+        .name           = "ocp2scp_usb_phy",
+        .class          = &omap44xx_ocp2scp_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = ocp2scp_usb_phy_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
+};
+
+/*
+ * 'prcm' class
+ * power and reset manager (part of the prcm infrastructure) + clock manager 2
+ * + clock manager 1 (in always on power domain) + local prm in mpu
+ */
+
+static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
+        .name   = "prcm",
+};
+
+/* prcm_mpu */
+static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
+        .name           = "prcm_mpu",
+        .class          = &omap44xx_prcm_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/* cm_core_aon */
+static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
+        .name           = "cm_core_aon",
+        .class          = &omap44xx_prcm_hwmod_class,
+        .clkdm_name     = "cm_clkdm",
+};
+
+/* cm_core */
+static struct omap_hwmod omap44xx_cm_core_hwmod = {
+        .name           = "cm_core",
+        .class          = &omap44xx_prcm_hwmod_class,
+        .clkdm_name     = "cm_clkdm",
+};
+
+/* prm */
+static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
+        { .irq = 11 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
+        { .name = "rst_global_warm_sw", .rst_shift = 0 },
+        { .name = "rst_global_cold_sw", .rst_shift = 1 },
+};
+
+static struct omap_hwmod omap44xx_prm_hwmod = {
+        .name           = "prm",
+        .class          = &omap44xx_prcm_hwmod_class,
+        .clkdm_name     = "prm_clkdm",
+        .mpu_irqs       = omap44xx_prm_irqs,
+        .rst_lines      = omap44xx_prm_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
+};
+
+/*
+ * 'scrm' class
+ * system clock and reset manager
+ */
+
+static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
+        .name   = "scrm",
+};
+
+/* scrm */
+static struct omap_hwmod omap44xx_scrm_hwmod = {
+        .name           = "scrm",
+        .class          = &omap44xx_scrm_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/*
+ * 'sl2if' class
+ * shared level 2 memory interface
+ */
+
+static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
+        .name   = "sl2if",
+};
+
+/* sl2if */
+static struct omap_hwmod omap44xx_sl2if_hwmod = {
+        .name           = "sl2if",
+        .class          = &omap44xx_sl2if_hwmod_class,
+        .clkdm_name     = "ivahd_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'slimbus' class
+ * bidirectional, multi-drop, multi-channel two-line serial interface between
+ * the device and external components
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
+        .name   = "slimbus",
+        .sysc   = &omap44xx_slimbus_sysc,
+};
+
+/* slimbus1 */
+static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
+        { .irq = 97 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
+        { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
+        { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
+        { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
+        { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
+};
+
+static struct omap_hwmod omap44xx_slimbus1_hwmod = {
+        .name           = "slimbus1",
+        .class          = &omap44xx_slimbus_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .mpu_irqs       = omap44xx_slimbus1_irqs,
+        .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = slimbus1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
+};
+
+/* slimbus2 */
+static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
+        { .irq = 98 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
+        { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
+        { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
+        { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
+};
+
+static struct omap_hwmod omap44xx_slimbus2_hwmod = {
+        .name           = "slimbus2",
+        .class          = &omap44xx_slimbus_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
+        .mpu_irqs       = omap44xx_slimbus2_irqs,
+        .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = slimbus2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
 };
 
 /*
@@ -4004,35 +2744,11 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
         .sensor_voltdm_name   = "core",
 };
 
-static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
-        {
-                .pa_start       = 0x4a0dd000,
-                .pa_end         = 0x4a0dd03f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> smartreflex_core */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_smartreflex_core_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_smartreflex_core_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* smartreflex_core slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
-        &omap44xx_l4_cfg__smartreflex_core,
-};
-
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
         .name           = "smartreflex_core",
         .class          = &omap44xx_smartreflex_hwmod_class,
@@ -4047,8 +2763,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_smartreflex_core_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
         .dev_attr       = &smartreflex_core_dev_attr,
 };
 
@@ -4057,35 +2771,11 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
         .sensor_voltdm_name     = "iva",
 };
 
-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
-        {
-                .pa_start       = 0x4a0db000,
-                .pa_end         = 0x4a0db03f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> smartreflex_iva */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_smartreflex_iva_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_smartreflex_iva_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* smartreflex_iva slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
-        &omap44xx_l4_cfg__smartreflex_iva,
-};
-
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
         .name           = "smartreflex_iva",
         .class          = &omap44xx_smartreflex_hwmod_class,
@@ -4099,8 +2789,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_smartreflex_iva_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
         .dev_attr       = &smartreflex_iva_dev_attr,
 };
 
@@ -4109,35 +2797,11 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
         .sensor_voltdm_name     = "mpu",
 };
 
-static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
-        {
-                .pa_start       = 0x4a0d9000,
-                .pa_end         = 0x4a0d903f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> smartreflex_mpu */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_smartreflex_mpu_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_smartreflex_mpu_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* smartreflex_mpu slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
-        &omap44xx_l4_cfg__smartreflex_mpu,
-};
-
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
         .name           = "smartreflex_mpu",
         .class          = &omap44xx_smartreflex_hwmod_class,
@@ -4151,8 +2815,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_smartreflex_mpu_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
         .dev_attr       = &smartreflex_mpu_dev_attr,
 };
 
@@ -4180,30 +2842,6 @@ static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
 };
 
 /* spinlock */
-static struct omap_hwmod omap44xx_spinlock_hwmod;
-static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
-        {
-                .pa_start       = 0x4a0f6000,
-                .pa_end         = 0x4a0f6fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_spinlock_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_spinlock_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* spinlock slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
-        &omap44xx_l4_cfg__spinlock,
-};
-
 static struct omap_hwmod omap44xx_spinlock_hwmod = {
         .name           = "spinlock",
         .class          = &omap44xx_spinlock_hwmod_class,
@@ -4214,8 +2852,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
                 },
         },
-        .slaves         = omap44xx_spinlock_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
 };
 
 /*
@@ -4267,35 +2903,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 };
 
 /* timer1 */
-static struct omap_hwmod omap44xx_timer1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
-        {
-                .pa_start       = 0x4a318000,
-                .pa_end         = 0x4a31807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_timer1_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_timer1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
-        &omap44xx_l4_wkup__timer1,
-};
-
 static struct omap_hwmod omap44xx_timer1_hwmod = {
         .name           = "timer1",
         .class          = &omap44xx_timer_1ms_hwmod_class,
@@ -4310,40 +2922,14 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
 };
 
 /* timer2 */
-static struct omap_hwmod omap44xx_timer2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
-        {
-                .pa_start       = 0x48032000,
-                .pa_end         = 0x4803207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
-        &omap44xx_l4_per__timer2,
-};
-
 static struct omap_hwmod omap44xx_timer2_hwmod = {
         .name           = "timer2",
         .class          = &omap44xx_timer_1ms_hwmod_class,
@@ -4358,40 +2944,14 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
 };
 
 /* timer3 */
-static struct omap_hwmod omap44xx_timer3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
-        {
-                .pa_start       = 0x48034000,
-                .pa_end         = 0x4803407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
-        &omap44xx_l4_per__timer3,
-};
-
 static struct omap_hwmod omap44xx_timer3_hwmod = {
         .name           = "timer3",
         .class          = &omap44xx_timer_hwmod_class,
@@ -4406,40 +2966,14 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
 };
 
 /* timer4 */
-static struct omap_hwmod omap44xx_timer4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
-        {
-                .pa_start       = 0x48036000,
-                .pa_end         = 0x4803607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
-        &omap44xx_l4_per__timer4,
-};
-
 static struct omap_hwmod omap44xx_timer4_hwmod = {
         .name           = "timer4",
         .class          = &omap44xx_timer_hwmod_class,
@@ -4454,59 +2988,14 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
 };
 
 /* timer5 */
-static struct omap_hwmod omap44xx_timer5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
-        {
-                .pa_start       = 0x40138000,
-                .pa_end         = 0x4013807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> timer5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer5_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer5_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
-        {
-                .pa_start       = 0x49038000,
-                .pa_end         = 0x4903807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> timer5 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer5_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer5_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* timer5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
-        &omap44xx_l4_abe__timer5,
-        &omap44xx_l4_abe__timer5_dma,
-};
-
 static struct omap_hwmod omap44xx_timer5_hwmod = {
         .name           = "timer5",
         .class          = &omap44xx_timer_hwmod_class,
@@ -4521,59 +3010,14 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
 };
 
 /* timer6 */
-static struct omap_hwmod omap44xx_timer6_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4013a000,
-                .pa_end         = 0x4013a07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> timer6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer6_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer6_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903a000,
-                .pa_end         = 0x4903a07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> timer6 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer6_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer6_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* timer6 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
-        &omap44xx_l4_abe__timer6,
-        &omap44xx_l4_abe__timer6_dma,
-};
-
 static struct omap_hwmod omap44xx_timer6_hwmod = {
         .name           = "timer6",
         .class          = &omap44xx_timer_hwmod_class,
@@ -4589,59 +3033,14 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
 };
 
 /* timer7 */
-static struct omap_hwmod omap44xx_timer7_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
-        {
-                .pa_start       = 0x4013c000,
-                .pa_end         = 0x4013c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> timer7 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer7_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer7_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903c000,
-                .pa_end         = 0x4903c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> timer7 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer7_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer7_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* timer7 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
-        &omap44xx_l4_abe__timer7,
-        &omap44xx_l4_abe__timer7_dma,
-};
-
 static struct omap_hwmod omap44xx_timer7_hwmod = {
         .name           = "timer7",
         .class          = &omap44xx_timer_hwmod_class,
@@ -4656,59 +3055,14 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                 },
         },
         .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer7_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
 };
 
 /* timer8 */
-static struct omap_hwmod omap44xx_timer8_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
-        {
-                .pa_start       = 0x4013e000,
-                .pa_end         = 0x4013e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> timer8 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer8_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer8_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903e000,
-                .pa_end         = 0x4903e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_abe -> timer8 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer8_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer8_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-
-/* timer8 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
-        &omap44xx_l4_abe__timer8,
-        &omap44xx_l4_abe__timer8_dma,
-};
-
 static struct omap_hwmod omap44xx_timer8_hwmod = {
         .name           = "timer8",
         .class          = &omap44xx_timer_hwmod_class,
@@ -4723,40 +3077,14 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                 },
         },
         .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap44xx_timer8_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
 };
 
 /* timer9 */
-static struct omap_hwmod omap44xx_timer9_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
-        {
-                .pa_start       = 0x4803e000,
-                .pa_end         = 0x4803e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer9_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer9_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer9 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
-        &omap44xx_l4_per__timer9,
-};
-
 static struct omap_hwmod omap44xx_timer9_hwmod = {
         .name           = "timer9",
         .class          = &omap44xx_timer_hwmod_class,
@@ -4771,40 +3099,14 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
                 },
         },
         .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap44xx_timer9_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
 };
 
 /* timer10 */
-static struct omap_hwmod omap44xx_timer10_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
-        {
-                .pa_start       = 0x48086000,
-                .pa_end         = 0x4808607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer10 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer10_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer10_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer10 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
-        &omap44xx_l4_per__timer10,
-};
-
 static struct omap_hwmod omap44xx_timer10_hwmod = {
         .name           = "timer10",
         .class          = &omap44xx_timer_1ms_hwmod_class,
@@ -4819,40 +3121,14 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
                 },
         },
         .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap44xx_timer10_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
 };
 
 /* timer11 */
-static struct omap_hwmod omap44xx_timer11_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
-        {
-                .pa_start       = 0x48088000,
-                .pa_end         = 0x4808807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> timer11 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer11_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer11_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* timer11 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
-        &omap44xx_l4_per__timer11,
-};
-
 static struct omap_hwmod omap44xx_timer11_hwmod = {
         .name           = "timer11",
         .class          = &omap44xx_timer_hwmod_class,
@@ -4867,8 +3143,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
                 },
         },
         .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap44xx_timer11_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
 };
 
 /*
@@ -4894,7 +3168,6 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 };
 
 /* uart1 */
-static struct omap_hwmod omap44xx_uart1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -4906,29 +3179,6 @@ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
-        {
-                .pa_start       = 0x4806a000,
-                .pa_end         = 0x4806a0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> uart1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* uart1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
-        &omap44xx_l4_per__uart1,
-};
-
 static struct omap_hwmod omap44xx_uart1_hwmod = {
         .name           = "uart1",
         .class          = &omap44xx_uart_hwmod_class,
@@ -4943,12 +3193,9 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_uart1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
 };
 
 /* uart2 */
-static struct omap_hwmod omap44xx_uart2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -4960,29 +3207,6 @@ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
-        {
-                .pa_start       = 0x4806c000,
-                .pa_end         = 0x4806c0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> uart2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* uart2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
-        &omap44xx_l4_per__uart2,
-};
-
 static struct omap_hwmod omap44xx_uart2_hwmod = {
         .name           = "uart2",
         .class          = &omap44xx_uart_hwmod_class,
@@ -4997,12 +3221,9 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_uart2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
 };
 
 /* uart3 */
-static struct omap_hwmod omap44xx_uart3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -5014,29 +3235,6 @@ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
-        {
-                .pa_start       = 0x48020000,
-                .pa_end         = 0x480200ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> uart3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* uart3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
-        &omap44xx_l4_per__uart3,
-};
-
 static struct omap_hwmod omap44xx_uart3_hwmod = {
         .name           = "uart3",
         .class          = &omap44xx_uart_hwmod_class,
@@ -5052,12 +3250,9 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_uart3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
 };
 
 /* uart4 */
-static struct omap_hwmod omap44xx_uart4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
@@ -5069,29 +3264,6 @@ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
         { .dma_req = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
-        {
-                .pa_start       = 0x4806e000,
-                .pa_end         = 0x4806e0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_per -> uart4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* uart4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
-        &omap44xx_l4_per__uart4,
-};
-
 static struct omap_hwmod omap44xx_uart4_hwmod = {
         .name           = "uart4",
         .class          = &omap44xx_uart_hwmod_class,
@@ -5106,8 +3278,147 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_uart4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
+};
+
+/*
+ * 'usb_host_fs' class
+ * full-speed usb host controller
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
+        .midle_shift    = 4,
+        .sidle_shift    = 2,
+        .srst_shift     = 1,
+};
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0210,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
+};
+
+static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
+        .name   = "usb_host_fs",
+        .sysc   = &omap44xx_usb_host_fs_sysc,
+};
+
+/* usb_host_fs */
+static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
+        { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
+        { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
+        .name           = "usb_host_fs",
+        .class          = &omap44xx_usb_host_fs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap44xx_usb_host_fs_irqs,
+        .main_clk       = "usb_host_fs_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
+        .name   = "usb_host_hs",
+        .sysc   = &omap44xx_usb_host_hs_sysc,
+};
+
+/* usb_host_hs */
+static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
+        { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
+        { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
+        .name           = "usb_host_hs",
+        .class          = &omap44xx_usb_host_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "usb_host_hs_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .mpu_irqs       = omap44xx_usb_host_hs_irqs,
+
+        /*
+         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+         * id: i660
+         *
+         * Description:
+         * In the following configuration :
+         * - USBHOST module is set to smart-idle mode
+         * - PRCM asserts idle_req to the USBHOST module ( This typically
+         *   happens when the system is going to a low power mode : all ports
+         *   have been suspended, the master part of the USBHOST module has
+         *   entered the standby state, and SW has cut the functional clocks)
+         * - an USBHOST interrupt occurs before the module is able to answer
+         *   idle_ack, typically a remote wakeup IRQ.
+         * Then the USB HOST module will enter a deadlock situation where it
+         * is no more accessible nor functional.
+         *
+         * Workaround:
+         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+         */
+
+        /*
+         * Errata: USB host EHCI may stall when entering smart-standby mode
+         * Id: i571
+         *
+         * Description:
+         * When the USBHOST module is set to smart-standby mode, and when it is
+         * ready to enter the standby state (i.e. all ports are suspended and
+         * all attached devices are in suspend mode), then it can wrongly assert
+         * the Mstandby signal too early while there are still some residual OCP
+         * transactions ongoing. If this condition occurs, the internal state
+         * machine may go to an undefined state and the USB link may be stuck
+         * upon the next resume.
+         *
+         * Workaround:
+         * Don't use smart standby; use only force standby,
+         * hence HWMOD_SWSUP_MSTANDBY
+         */
+
+        /*
+         * During system boot; If the hwmod framework resets the module
+         * the module will have smart idle settings; which can lead to deadlock
+         * (above Errata Id:i660); so, dont reset the module during boot;
+         * Use HWMOD_INIT_NO_RESET.
+         */
+
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+                          HWMOD_INIT_NO_RESET,
 };
 
 /*
@@ -5140,34 +3451,6 @@ static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
         { .irq = -1 }
 };
 
-/* usb_otg_hs master ports */
-static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
-        &omap44xx_usb_otg_hs__l3_main_2,
-};
-
-static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
-        {
-                .pa_start       = 0x4a0ab000,
-                .pa_end         = 0x4a0ab003,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> usb_otg_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_usb_otg_hs_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_otg_hs_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* usb_otg_hs slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
-        &omap44xx_l4_cfg__usb_otg_hs,
-};
-
 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
 };
@@ -5188,10 +3471,47 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
         },
         .opt_clks       = usb_otg_hs_opt_clks,
         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
-        .slaves         = omap44xx_usb_otg_hs_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
-        .masters        = omap44xx_usb_otg_hs_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
+};
+
+/*
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
+        .name   = "usb_tll_hs",
+        .sysc   = &omap44xx_usb_tll_hs_sysc,
+};
+
+static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
+        { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap44xx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
+        .main_clk       = "usb_tll_hs_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
 };
 
 /*
@@ -5215,38 +3535,15 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
         .name           = "wd_timer",
         .sysc           = &omap44xx_wd_timer_sysc,
         .pre_shutdown   = &omap2_wd_timer_disable,
+        .reset          = &omap2_wd_timer_reset,
 };
 
 /* wd_timer2 */
-static struct omap_hwmod omap44xx_wd_timer2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x4a314000,
-                .pa_end         = 0x4a31407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_wd_timer2_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_wd_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* wd_timer2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
-        &omap44xx_l4_wkup__wd_timer2,
-};
-
 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
         .name           = "wd_timer2",
         .class          = &omap44xx_wd_timer_hwmod_class,
@@ -5260,106 +3557,2308 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .slaves         = omap44xx_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
 };
 
 /* wd_timer3 */
-static struct omap_hwmod omap44xx_wd_timer3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
         { .irq = -1 }
 };
 
-static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+        .name           = "wd_timer3",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .mpu_irqs       = omap44xx_wd_timer3_irqs,
+        .main_clk       = "wd_timer3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+
+/*
+ * interfaces
+ */
+
+static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
         {
-                .pa_start       = 0x40130000,
-                .pa_end         = 0x4013007f,
+                .pa_start       = 0x4a204000,
+                .pa_end         = 0x4a2040ff,
                 .flags          = ADDR_TYPE_RT
         },
         { }
 };
 
-/* l4_abe -> wd_timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+/* c2c -> c2c_target_fw */
+static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
+        .master         = &omap44xx_c2c_hwmod,
+        .slave          = &omap44xx_c2c_target_fw_hwmod,
+        .clk            = "div_core_ck",
+        .addr           = omap44xx_c2c_target_fw_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_cfg -> c2c_target_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_c2c_target_fw_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
+        {
+                .pa_start       = 0x4e000000,
+                .pa_end         = 0x4e0007ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* mpu -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dmm_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* c2c -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
+        .master         = &omap44xx_c2c_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "div_core_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dmm -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
+        .master         = &omap44xx_dmm_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
+        {
+                .pa_start       = 0x4a20c000,
+                .pa_end         = 0x4a20c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_emif_fw_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* iva -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
+        .master         = &omap44xx_l3_main_3_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ocp_wp_noc -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
+        .master         = &omap44xx_ocp_wp_noc_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dsp -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dss -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
+        .master         = &omap44xx_dss_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc1 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
+        .master         = &omap44xx_mmc1_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mmc2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
+        .master         = &omap44xx_mmc2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
+        {
+                .pa_start       = 0x44000000,
+                .pa_end         = 0x44000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_1_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* c2c_target_fw -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
+        .master         = &omap44xx_c2c_target_fw_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* debugss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
+        .master         = &omap44xx_debugss_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "dbgclk_mux_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+        .master         = &omap44xx_dma_system_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* fdif -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
+        .master         = &omap44xx_fdif_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
+        .master         = &omap44xx_gpu_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* hsi -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
+        .master         = &omap44xx_hsi_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ipu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
+        .master         = &omap44xx_ipu_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
+        .master         = &omap44xx_iss_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iva -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
+        {
+                .pa_start       = 0x44800000,
+                .pa_end         = 0x44801fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_2_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_host_fs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
+        .master         = &omap44xx_usb_host_fs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_host_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
+        .master         = &omap44xx_usb_host_hs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* usb_otg_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
+        .master         = &omap44xx_usb_otg_hs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
+        {
+                .pa_start       = 0x45000000,
+                .pa_end         = 0x45000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_3_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* aess -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
+        .master         = &omap44xx_aess_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dsp -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_cfg_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l4_per_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l4_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l4_wkup_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_mpu_private_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
+        {
+                .pa_start       = 0x4a102000,
+                .pa_end         = 0x4a10207f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> ocp_wp_noc */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_ocp_wp_noc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_ocp_wp_noc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
+        {
+                .pa_start       = 0x401f1000,
+                .pa_end         = 0x401f13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> aess */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
         .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_wd_timer3_hwmod,
+        .slave          = &omap44xx_aess_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_wd_timer3_addrs,
+        .addr           = omap44xx_aess_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
         {
-                .pa_start       = 0x49030000,
-                .pa_end         = 0x4903007f,
+                .pa_start       = 0x490f1000,
+                .pa_end         = 0x490f13ff,
                 .flags          = ADDR_TYPE_RT
         },
         { }
 };
 
-/* l4_abe -> wd_timer3 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+/* l4_abe -> aess (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_wd_timer3_hwmod,
+        .slave          = &omap44xx_aess_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_wd_timer3_dma_addrs,
+        .addr           = omap44xx_aess_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-/* wd_timer3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
-        &omap44xx_l4_abe__wd_timer3,
-        &omap44xx_l4_abe__wd_timer3_dma,
+/* l3_main_2 -> c2c */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_c2c_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
-        .name           = "wd_timer3",
-        .class          = &omap44xx_wd_timer_hwmod_class,
-        .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_wd_timer3_irqs,
-        .main_clk       = "wd_timer3_fck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
+static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
+        {
+                .pa_start       = 0x4a304000,
+                .pa_end         = 0x4a30401f,
+                .flags          = ADDR_TYPE_RT
         },
-        .slaves         = omap44xx_wd_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
+        { }
 };
 
-/*
- * 'usb_host_hs' class
- * high-speed multi-port usb host controller
- */
-static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
-        .master         = &omap44xx_usb_host_hs_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_counter_32k_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_counter_32k_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
+        {
+                .pa_start       = 0x4a002000,
+                .pa_end         = 0x4a0027ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> ctrl_module_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_ctrl_module_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_ctrl_module_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
+        {
+                .pa_start       = 0x4a100000,
+                .pa_end         = 0x4a1007ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> ctrl_module_pad_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_ctrl_module_pad_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
+        {
+                .pa_start       = 0x4a30c000,
+                .pa_end         = 0x4a30c7ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> ctrl_module_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_ctrl_module_wkup_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_ctrl_module_wkup_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
+        {
+                .pa_start       = 0x4a31e000,
+                .pa_end         = 0x4a31e7ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> ctrl_module_pad_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
+        {
+                .pa_start       = 0x54160000,
+                .pa_end         = 0x54167fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_instr -> debugss */
+static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
+        .master         = &omap44xx_l3_instr_hwmod,
+        .slave          = &omap44xx_debugss_hwmod,
         .clk            = "l3_div_ck",
+        .addr           = omap44xx_debugss_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
+static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x4a056000,
+                .pa_end         = 0x4a056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
 };
 
-static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
-        .name = "usb_host_hs",
-        .sysc = &omap44xx_usb_host_hs_sysc,
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dma_system_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
-        &omap44xx_usb_host_hs__l3_main_2,
+static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4012e000,
+                .pa_end         = 0x4012e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_dmic_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_dmic_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x4902e000,
+                .pa_end         = 0x4902e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> dmic (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_dmic_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_dmic_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+/* dsp -> iva */
+static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_iva_hwmod,
+        .clk            = "dpll_iva_m5x2_ck",
+        .user           = OCP_USER_DSP,
+};
+
+/* dsp -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_sl2if_hwmod,
+        .clk            = "dpll_iva_m5x2_ck",
+        .user           = OCP_USER_DSP,
+};
+
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dsp_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
+        {
+                .pa_start       = 0x58000000,
+                .pa_end         = 0x5800007f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
+        {
+                .pa_start       = 0x48040000,
+                .pa_end         = 0x4804007f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+        {
+                .pa_start       = 0x58001000,
+                .pa_end         = 0x58001fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dispc_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_dispc_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48041000,
+                .pa_end         = 0x48041fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dispc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dispc_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+        {
+                .pa_start       = 0x58004000,
+                .pa_end         = 0x580041ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dsi1_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_dsi1_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
+        {
+                .pa_start       = 0x48044000,
+                .pa_end         = 0x480441ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dsi1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dsi1_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+        {
+                .pa_start       = 0x58005000,
+                .pa_end         = 0x580051ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dsi2_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_dsi2_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
+        {
+                .pa_start       = 0x48045000,
+                .pa_end         = 0x480451ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dsi2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dsi2_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+        {
+                .pa_start       = 0x58006000,
+                .pa_end         = 0x58006fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_hdmi_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_hdmi_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
+        {
+                .pa_start       = 0x48046000,
+                .pa_end         = 0x48046fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_hdmi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_hdmi_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+        {
+                .pa_start       = 0x58002000,
+                .pa_end         = 0x580020ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_rfbi_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_rfbi_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48042000,
+                .pa_end         = 0x480420ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_rfbi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_rfbi_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+        {
+                .pa_start       = 0x58003000,
+                .pa_end         = 0x580030ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_venc_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_venc_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48043000,
+                .pa_end         = 0x480430ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_venc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_venc_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> elm */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_elm_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_elm_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
+        {
+                .pa_start       = 0x4c000000,
+                .pa_end         = 0x4c0000ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* emif_fw -> emif1 */
+static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
+        .master         = &omap44xx_emif_fw_hwmod,
+        .slave          = &omap44xx_emif1_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_emif1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
+        {
+                .pa_start       = 0x4d000000,
+                .pa_end         = 0x4d0000ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* emif_fw -> emif2 */
+static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
+        .master         = &omap44xx_emif_fw_hwmod,
+        .slave          = &omap44xx_emif2_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_emif2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
+        {
+                .pa_start       = 0x4a10a000,
+                .pa_end         = 0x4a10a1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> fdif */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_fdif_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_fdif_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x4a310000,
+                .pa_end         = 0x4a3101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_gpio1_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_gpio1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x48055000,
+                .pa_end         = 0x480551ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x48057000,
+                .pa_end         = 0x480571ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
+        {
+                .pa_start       = 0x48059000,
+                .pa_end         = 0x480591ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
+        {
+                .pa_start       = 0x4805b000,
+                .pa_end         = 0x4805b1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio5_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
+        {
+                .pa_start       = 0x4805d000,
+                .pa_end         = 0x4805d1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio6_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio6_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x50000000,
+                .pa_end         = 0x500003ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> gpmc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_gpmc_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
+        {
+                .pa_start       = 0x56000000,
+                .pa_end         = 0x5600ffff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> gpu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_gpu_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_gpu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
+        {
+                .pa_start       = 0x480b2000,
+                .pa_end         = 0x480b201f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> hdq1w */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_hdq1w_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_hdq1w_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
+        {
+                .pa_start       = 0x4a058000,
+                .pa_end         = 0x4a05bfff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> hsi */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_hsi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_hsi_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x480700ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x480720ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+        {
+                .pa_start       = 0x48060000,
+                .pa_end         = 0x480600ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+        {
+                .pa_start       = 0x48350000,
+                .pa_end         = 0x483500ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_ipu_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
+        {
+                .pa_start       = 0x52000000,
+                .pa_end         = 0x520000ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> iss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_iss_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_iss_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iva -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_sl2if_hwmod,
+        .clk            = "dpll_iva_m5x2_ck",
+        .user           = OCP_USER_IVA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
+        {
+                .pa_start       = 0x5a000000,
+                .pa_end         = 0x5a07ffff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l3_main_2 -> iva */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_iva_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_iva_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
+        {
+                .pa_start       = 0x4a31c000,
+                .pa_end         = 0x4a31c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_kbd_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_kbd_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x4a0f4000,
+                .pa_end         = 0x4a0f41ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_mailbox_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mailbox_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
+        {
+                .pa_start       = 0x40128000,
+                .pa_end         = 0x401283ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcasp */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcasp_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcasp_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
+        {
+                .pa_start       = 0x49028000,
+                .pa_end         = 0x490283ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcasp (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcasp_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcasp_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40122000,
+                .pa_end         = 0x401220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp1_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49022000,
+                .pa_end         = 0x490220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcbsp1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp1_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40124000,
+                .pa_end         = 0x401240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp2_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp2_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49024000,
+                .pa_end         = 0x490240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcbsp2 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp2_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp2_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40126000,
+                .pa_end         = 0x401260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp3_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49026000,
+                .pa_end         = 0x490260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcbsp3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp3_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
+        {
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcbsp4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcbsp4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
+        {
+                .pa_start       = 0x40132000,
+                .pa_end         = 0x4013207f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcpdm_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcpdm_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x4903207f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> mcpdm (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcpdm_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcpdm_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480981ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b81ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+        {
+                .pa_start       = 0x480ba000,
+                .pa_end         = 0x480ba1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b43ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
+        {
+                .pa_start       = 0x480ad000,
+                .pa_end         = 0x480ad3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
+        {
+                .pa_start       = 0x480d1000,
+                .pa_end         = 0x480d13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
+        {
+                .pa_start       = 0x480d5000,
+                .pa_end         = 0x480d53ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc5_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> ocmc_ram */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_ocmc_ram_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> ocp2scp_usb_phy */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
+        {
+                .pa_start       = 0x48243000,
+                .pa_end         = 0x48243fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* mpu_private -> prcm_mpu */
+static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
+        .master         = &omap44xx_mpu_private_hwmod,
+        .slave          = &omap44xx_prcm_mpu_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_prcm_mpu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
+        {
+                .pa_start       = 0x4a004000,
+                .pa_end         = 0x4a004fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> cm_core_aon */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_cm_core_aon_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_cm_core_aon_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
+        {
+                .pa_start       = 0x4a008000,
+                .pa_end         = 0x4a009fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> cm_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_cm_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_cm_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
+        {
+                .pa_start       = 0x4a306000,
+                .pa_end         = 0x4a307fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> prm */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_prm_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_prm_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
+        {
+                .pa_start       = 0x4a30a000,
+                .pa_end         = 0x4a30a7ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> scrm */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_scrm_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_scrm_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_sl2if_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
+        {
+                .pa_start       = 0x4012c000,
+                .pa_end         = 0x4012c3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> slimbus1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_slimbus1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_slimbus1_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
+        {
+                .pa_start       = 0x4902c000,
+                .pa_end         = 0x4902c3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> slimbus1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_slimbus1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_slimbus1_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
+        {
+                .pa_start       = 0x48076000,
+                .pa_end         = 0x480763ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> slimbus2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_slimbus2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_slimbus2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+        {
+                .pa_start       = 0x4a0dd000,
+                .pa_end         = 0x4a0dd03f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+        {
+                .pa_start       = 0x4a0db000,
+                .pa_end         = 0x4a0db03f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_iva_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_iva_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+        {
+                .pa_start       = 0x4a0d9000,
+                .pa_end         = 0x4a0d903f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_mpu_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_mpu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
+        {
+                .pa_start       = 0x4a0f6000,
+                .pa_end         = 0x4a0f6fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_spinlock_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_spinlock_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x4a318000,
+                .pa_end         = 0x4a31807f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_timer1_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_timer1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48032000,
+                .pa_end         = 0x4803207f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48034000,
+                .pa_end         = 0x4803407f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x48036000,
+                .pa_end         = 0x4803607f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x40138000,
+                .pa_end         = 0x4013807f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer5_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer5_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x4903807f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> timer5 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer5_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer5_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4013a000,
+                .pa_end         = 0x4013a07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer6_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer6_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903a000,
+                .pa_end         = 0x4903a07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> timer6 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer6_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer6_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4013c000,
+                .pa_end         = 0x4013c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer7_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer7_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903c000,
+                .pa_end         = 0x4903c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> timer7 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer7_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer7_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4013e000,
+                .pa_end         = 0x4013e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer8_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer8_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903e000,
+                .pa_end         = 0x4903e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> timer8 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer8_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer8_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x4803e000,
+                .pa_end         = 0x4803e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer9_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer9_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x4808607f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer10_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer10_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x4808807f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer11_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer11_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+        {
+                .pa_start       = 0x4806a000,
+                .pa_end         = 0x4806a0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+        {
+                .pa_start       = 0x4806c000,
+                .pa_end         = 0x4806c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+        {
+                .pa_start       = 0x48020000,
+                .pa_end         = 0x480200ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+        {
+                .pa_start       = 0x4806e000,
+                .pa_end         = 0x4806e0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
+        {
+                .pa_start       = 0x4a0a9000,
+                .pa_end         = 0x4a0a93ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> usb_host_fs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_host_fs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_host_fs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
@@ -5382,12 +5881,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
         {}
 };
 
-static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
-        { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
-        { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
+/* l4_cfg -> usb_host_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_usb_host_hs_hwmod,
@@ -5396,100 +5890,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
-        &omap44xx_l4_cfg__usb_host_hs,
-};
-
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
-        .name           = "usb_host_hs",
-        .class          = &omap44xx_usb_host_hs_hwmod_class,
-        .clkdm_name     = "l3_init_clkdm",
-        .main_clk       = "usb_host_hs_fck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
+        {
+                .pa_start       = 0x4a0ab000,
+                .pa_end         = 0x4a0ab003,
+                .flags          = ADDR_TYPE_RT
         },
-        .mpu_irqs       = omap44xx_usb_host_hs_irqs,
-        .slaves         = omap44xx_usb_host_hs_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
-        .masters        = omap44xx_usb_host_hs_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
-
-        /*
-         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
-         * id: i660
-         *
-         * Description:
-         * In the following configuration :
-         * - USBHOST module is set to smart-idle mode
-         * - PRCM asserts idle_req to the USBHOST module ( This typically
-         *   happens when the system is going to a low power mode : all ports
-         *   have been suspended, the master part of the USBHOST module has
-         *   entered the standby state, and SW has cut the functional clocks)
-         * - an USBHOST interrupt occurs before the module is able to answer
-         *   idle_ack, typically a remote wakeup IRQ.
-         * Then the USB HOST module will enter a deadlock situation where it
-         * is no more accessible nor functional.
-         *
-         * Workaround:
-         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
-         */
-
-        /*
-         * Errata: USB host EHCI may stall when entering smart-standby mode
-         * Id: i571
-         *
-         * Description:
-         * When the USBHOST module is set to smart-standby mode, and when it is
-         * ready to enter the standby state (i.e. all ports are suspended and
-         * all attached devices are in suspend mode), then it can wrongly assert
-         * the Mstandby signal too early while there are still some residual OCP
-         * transactions ongoing. If this condition occurs, the internal state
-         * machine may go to an undefined state and the USB link may be stuck
-         * upon the next resume.
-         *
-         * Workaround:
-         * Don't use smart standby; use only force standby,
-         * hence HWMOD_SWSUP_MSTANDBY
-         */
-
-        /*
-         * During system boot; If the hwmod framework resets the module
-         * the module will have smart idle settings; which can lead to deadlock
-         * (above Errata Id:i660); so, dont reset the module during boot;
-         * Use HWMOD_INIT_NO_RESET.
-         */
-
-        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
-                          HWMOD_INIT_NO_RESET,
-};
-
-/*
- * 'usb_tll_hs' class
- * usb_tll_hs module is the adapter on the usb_host_hs ports
- */
-static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
-        .name = "usb_tll_hs",
-        .sysc = &omap44xx_usb_tll_hs_sysc,
+        { }
 };
 
-static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
-        { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
+/* l4_cfg -> usb_otg_hs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_otg_hs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_otg_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
@@ -5502,6 +5918,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
         {}
 };
 
+/* l4_cfg -> usb_tll_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_usb_tll_hs_hwmod,
@@ -5510,181 +5927,223 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
-        &omap44xx_l4_cfg__usb_tll_hs,
+static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4a314000,
+                .pa_end         = 0x4a31407f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
 };
 
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
-        .name           = "usb_tll_hs",
-        .class          = &omap44xx_usb_tll_hs_hwmod_class,
-        .clkdm_name     = "l3_init_clkdm",
-        .main_clk       = "usb_tll_hs_ick",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_wd_timer2_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_wd_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+        {
+                .pa_start       = 0x40130000,
+                .pa_end         = 0x4013007f,
+                .flags          = ADDR_TYPE_RT
         },
-        .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
-        .slaves         = omap44xx_usb_tll_hs_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
+        { }
 };
 
-static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
-
-        /* dmm class */
-        &omap44xx_dmm_hwmod,
-
-        /* emif_fw class */
-        &omap44xx_emif_fw_hwmod,
-
-        /* l3 class */
-        &omap44xx_l3_instr_hwmod,
-        &omap44xx_l3_main_1_hwmod,
-        &omap44xx_l3_main_2_hwmod,
-        &omap44xx_l3_main_3_hwmod,
-
-        /* l4 class */
-        &omap44xx_l4_abe_hwmod,
-        &omap44xx_l4_cfg_hwmod,
-        &omap44xx_l4_per_hwmod,
-        &omap44xx_l4_wkup_hwmod,
-
-        /* mpu_bus class */
-        &omap44xx_mpu_private_hwmod,
-
-        /* aess class */
-/*      &omap44xx_aess_hwmod, */
-
-        /* bandgap class */
-        &omap44xx_bandgap_hwmod,
-
-        /* counter class */
-/*      &omap44xx_counter_32k_hwmod, */
-
-        /* dma class */
-        &omap44xx_dma_system_hwmod,
-
-        /* dmic class */
-        &omap44xx_dmic_hwmod,
-
-        /* dsp class */
-        &omap44xx_dsp_hwmod,
-        &omap44xx_dsp_c0_hwmod,
-
-        /* dss class */
-        &omap44xx_dss_hwmod,
-        &omap44xx_dss_dispc_hwmod,
-        &omap44xx_dss_dsi1_hwmod,
-        &omap44xx_dss_dsi2_hwmod,
-        &omap44xx_dss_hdmi_hwmod,
-        &omap44xx_dss_rfbi_hwmod,
-        &omap44xx_dss_venc_hwmod,
-
-        /* gpio class */
-        &omap44xx_gpio1_hwmod,
-        &omap44xx_gpio2_hwmod,
-        &omap44xx_gpio3_hwmod,
-        &omap44xx_gpio4_hwmod,
-        &omap44xx_gpio5_hwmod,
-        &omap44xx_gpio6_hwmod,
-
-        /* hsi class */
-/*      &omap44xx_hsi_hwmod, */
-
-        /* i2c class */
-        &omap44xx_i2c1_hwmod,
-        &omap44xx_i2c2_hwmod,
-        &omap44xx_i2c3_hwmod,
-        &omap44xx_i2c4_hwmod,
-
-        /* ipu class */
-        &omap44xx_ipu_hwmod,
-        &omap44xx_ipu_c0_hwmod,
-        &omap44xx_ipu_c1_hwmod,
-
-        /* iss class */
-/*      &omap44xx_iss_hwmod, */
-
-        /* iva class */
-        &omap44xx_iva_hwmod,
-        &omap44xx_iva_seq0_hwmod,
-        &omap44xx_iva_seq1_hwmod,
-
-        /* kbd class */
-        &omap44xx_kbd_hwmod,
-
-        /* mailbox class */
-        &omap44xx_mailbox_hwmod,
-
-        /* mcbsp class */
-        &omap44xx_mcbsp1_hwmod,
-        &omap44xx_mcbsp2_hwmod,
-        &omap44xx_mcbsp3_hwmod,
-        &omap44xx_mcbsp4_hwmod,
-
-        /* mcpdm class */
-        &omap44xx_mcpdm_hwmod,
-
-        /* mcspi class */
-        &omap44xx_mcspi1_hwmod,
-        &omap44xx_mcspi2_hwmod,
-        &omap44xx_mcspi3_hwmod,
-        &omap44xx_mcspi4_hwmod,
-
-        /* mmc class */
-        &omap44xx_mmc1_hwmod,
-        &omap44xx_mmc2_hwmod,
-        &omap44xx_mmc3_hwmod,
-        &omap44xx_mmc4_hwmod,
-        &omap44xx_mmc5_hwmod,
-
-        /* mpu class */
-        &omap44xx_mpu_hwmod,
-
-        /* smartreflex class */
-        &omap44xx_smartreflex_core_hwmod,
-        &omap44xx_smartreflex_iva_hwmod,
-        &omap44xx_smartreflex_mpu_hwmod,
-
-        /* spinlock class */
-        &omap44xx_spinlock_hwmod,
-
-        /* timer class */
-        &omap44xx_timer1_hwmod,
-        &omap44xx_timer2_hwmod,
-        &omap44xx_timer3_hwmod,
-        &omap44xx_timer4_hwmod,
-        &omap44xx_timer5_hwmod,
-        &omap44xx_timer6_hwmod,
-        &omap44xx_timer7_hwmod,
-        &omap44xx_timer8_hwmod,
-        &omap44xx_timer9_hwmod,
-        &omap44xx_timer10_hwmod,
-        &omap44xx_timer11_hwmod,
-
-        /* uart class */
-        &omap44xx_uart1_hwmod,
-        &omap44xx_uart2_hwmod,
-        &omap44xx_uart3_hwmod,
-        &omap44xx_uart4_hwmod,
-
-        /* usb host class */
-        &omap44xx_usb_host_hs_hwmod,
-        &omap44xx_usb_tll_hs_hwmod,
-
-        /* usb_otg_hs class */
-        &omap44xx_usb_otg_hs_hwmod,
-
-        /* wd_timer class */
-        &omap44xx_wd_timer2_hwmod,
-        &omap44xx_wd_timer3_hwmod,
+/* l4_abe -> wd_timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+        {
+                .pa_start       = 0x49030000,
+                .pa_end         = 0x4903007f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_abe -> wd_timer3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
+        &omap44xx_c2c__c2c_target_fw,
+        &omap44xx_l4_cfg__c2c_target_fw,
+        &omap44xx_l3_main_1__dmm,
+        &omap44xx_mpu__dmm,
+        &omap44xx_c2c__emif_fw,
+        &omap44xx_dmm__emif_fw,
+        &omap44xx_l4_cfg__emif_fw,
+        &omap44xx_iva__l3_instr,
+        &omap44xx_l3_main_3__l3_instr,
+        &omap44xx_ocp_wp_noc__l3_instr,
+        &omap44xx_dsp__l3_main_1,
+        &omap44xx_dss__l3_main_1,
+        &omap44xx_l3_main_2__l3_main_1,
+        &omap44xx_l4_cfg__l3_main_1,
+        &omap44xx_mmc1__l3_main_1,
+        &omap44xx_mmc2__l3_main_1,
+        &omap44xx_mpu__l3_main_1,
+        &omap44xx_c2c_target_fw__l3_main_2,
+        &omap44xx_debugss__l3_main_2,
+        &omap44xx_dma_system__l3_main_2,
+        &omap44xx_fdif__l3_main_2,
+        &omap44xx_gpu__l3_main_2,
+        &omap44xx_hsi__l3_main_2,
+        &omap44xx_ipu__l3_main_2,
+        &omap44xx_iss__l3_main_2,
+        &omap44xx_iva__l3_main_2,
+        &omap44xx_l3_main_1__l3_main_2,
+        &omap44xx_l4_cfg__l3_main_2,
+        &omap44xx_usb_host_fs__l3_main_2,
+        &omap44xx_usb_host_hs__l3_main_2,
+        &omap44xx_usb_otg_hs__l3_main_2,
+        &omap44xx_l3_main_1__l3_main_3,
+        &omap44xx_l3_main_2__l3_main_3,
+        &omap44xx_l4_cfg__l3_main_3,
+        &omap44xx_aess__l4_abe,
+        &omap44xx_dsp__l4_abe,
+        &omap44xx_l3_main_1__l4_abe,
+        &omap44xx_mpu__l4_abe,
+        &omap44xx_l3_main_1__l4_cfg,
+        &omap44xx_l3_main_2__l4_per,
+        &omap44xx_l4_cfg__l4_wkup,
+        &omap44xx_mpu__mpu_private,
+        &omap44xx_l4_cfg__ocp_wp_noc,
+        &omap44xx_l4_abe__aess,
+        &omap44xx_l4_abe__aess_dma,
+        &omap44xx_l3_main_2__c2c,
+        &omap44xx_l4_wkup__counter_32k,
+        &omap44xx_l4_cfg__ctrl_module_core,
+        &omap44xx_l4_cfg__ctrl_module_pad_core,
+        &omap44xx_l4_wkup__ctrl_module_wkup,
+        &omap44xx_l4_wkup__ctrl_module_pad_wkup,
+        &omap44xx_l3_instr__debugss,
+        &omap44xx_l4_cfg__dma_system,
+        &omap44xx_l4_abe__dmic,
+        &omap44xx_l4_abe__dmic_dma,
+        &omap44xx_dsp__iva,
+        &omap44xx_dsp__sl2if,
+        &omap44xx_l4_cfg__dsp,
+        &omap44xx_l3_main_2__dss,
+        &omap44xx_l4_per__dss,
+        &omap44xx_l3_main_2__dss_dispc,
+        &omap44xx_l4_per__dss_dispc,
+        &omap44xx_l3_main_2__dss_dsi1,
+        &omap44xx_l4_per__dss_dsi1,
+        &omap44xx_l3_main_2__dss_dsi2,
+        &omap44xx_l4_per__dss_dsi2,
+        &omap44xx_l3_main_2__dss_hdmi,
+        &omap44xx_l4_per__dss_hdmi,
+        &omap44xx_l3_main_2__dss_rfbi,
+        &omap44xx_l4_per__dss_rfbi,
+        &omap44xx_l3_main_2__dss_venc,
+        &omap44xx_l4_per__dss_venc,
+        &omap44xx_l4_per__elm,
+        &omap44xx_emif_fw__emif1,
+        &omap44xx_emif_fw__emif2,
+        &omap44xx_l4_cfg__fdif,
+        &omap44xx_l4_wkup__gpio1,
+        &omap44xx_l4_per__gpio2,
+        &omap44xx_l4_per__gpio3,
+        &omap44xx_l4_per__gpio4,
+        &omap44xx_l4_per__gpio5,
+        &omap44xx_l4_per__gpio6,
+        &omap44xx_l3_main_2__gpmc,
+        &omap44xx_l3_main_2__gpu,
+        &omap44xx_l4_per__hdq1w,
+        &omap44xx_l4_cfg__hsi,
+        &omap44xx_l4_per__i2c1,
+        &omap44xx_l4_per__i2c2,
+        &omap44xx_l4_per__i2c3,
+        &omap44xx_l4_per__i2c4,
+        &omap44xx_l3_main_2__ipu,
+        &omap44xx_l3_main_2__iss,
+        &omap44xx_iva__sl2if,
+        &omap44xx_l3_main_2__iva,
+        &omap44xx_l4_wkup__kbd,
+        &omap44xx_l4_cfg__mailbox,
+        &omap44xx_l4_abe__mcasp,
+        &omap44xx_l4_abe__mcasp_dma,
+        &omap44xx_l4_abe__mcbsp1,
+        &omap44xx_l4_abe__mcbsp1_dma,
+        &omap44xx_l4_abe__mcbsp2,
+        &omap44xx_l4_abe__mcbsp2_dma,
+        &omap44xx_l4_abe__mcbsp3,
+        &omap44xx_l4_abe__mcbsp3_dma,
+        &omap44xx_l4_per__mcbsp4,
+        &omap44xx_l4_abe__mcpdm,
+        &omap44xx_l4_abe__mcpdm_dma,
+        &omap44xx_l4_per__mcspi1,
+        &omap44xx_l4_per__mcspi2,
+        &omap44xx_l4_per__mcspi3,
+        &omap44xx_l4_per__mcspi4,
+        &omap44xx_l4_per__mmc1,
+        &omap44xx_l4_per__mmc2,
+        &omap44xx_l4_per__mmc3,
+        &omap44xx_l4_per__mmc4,
+        &omap44xx_l4_per__mmc5,
+        &omap44xx_l3_main_2__ocmc_ram,
+        &omap44xx_l4_cfg__ocp2scp_usb_phy,
+        &omap44xx_mpu_private__prcm_mpu,
+        &omap44xx_l4_wkup__cm_core_aon,
+        &omap44xx_l4_cfg__cm_core,
+        &omap44xx_l4_wkup__prm,
+        &omap44xx_l4_wkup__scrm,
+        &omap44xx_l3_main_2__sl2if,
+        &omap44xx_l4_abe__slimbus1,
+        &omap44xx_l4_abe__slimbus1_dma,
+        &omap44xx_l4_per__slimbus2,
+        &omap44xx_l4_cfg__smartreflex_core,
+        &omap44xx_l4_cfg__smartreflex_iva,
+        &omap44xx_l4_cfg__smartreflex_mpu,
+        &omap44xx_l4_cfg__spinlock,
+        &omap44xx_l4_wkup__timer1,
+        &omap44xx_l4_per__timer2,
+        &omap44xx_l4_per__timer3,
+        &omap44xx_l4_per__timer4,
+        &omap44xx_l4_abe__timer5,
+        &omap44xx_l4_abe__timer5_dma,
+        &omap44xx_l4_abe__timer6,
+        &omap44xx_l4_abe__timer6_dma,
+        &omap44xx_l4_abe__timer7,
+        &omap44xx_l4_abe__timer7_dma,
+        &omap44xx_l4_abe__timer8,
+        &omap44xx_l4_abe__timer8_dma,
+        &omap44xx_l4_per__timer9,
+        &omap44xx_l4_per__timer10,
+        &omap44xx_l4_per__timer11,
+        &omap44xx_l4_per__uart1,
+        &omap44xx_l4_per__uart2,
+        &omap44xx_l4_per__uart3,
+        &omap44xx_l4_per__uart4,
+        &omap44xx_l4_cfg__usb_host_fs,
+        &omap44xx_l4_cfg__usb_host_hs,
+        &omap44xx_l4_cfg__usb_otg_hs,
+        &omap44xx_l4_cfg__usb_tll_hs,
+        &omap44xx_l4_wkup__wd_timer2,
+        &omap44xx_l4_abe__wd_timer3,
+        &omap44xx_l4_abe__wd_timer3_dma,
         NULL,
 };
 
 int __init omap44xx_hwmod_init(void)
 {
-        return omap_hwmod_register(omap44xx_hwmods);
+        return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index ad5d8f04c0b8..e7e8eeae95e5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -19,18 +19,6 @@
 #include "display.h"
 
 /* Common address space across OMAP2xxx */
-extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
 extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
 
 /* Common address space across OMAP2xxx/3xxx */
@@ -50,10 +38,70 @@ extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
 extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
 extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
 extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
+extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
 
 /* Common IP block data across OMAP2xxx */
 extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
 extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
+extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
+extern struct omap_hwmod omap2xxx_l3_main_hwmod;
+extern struct omap_hwmod omap2xxx_l4_core_hwmod;
+extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
+extern struct omap_hwmod omap2xxx_mpu_hwmod;
+extern struct omap_hwmod omap2xxx_iva_hwmod;
+extern struct omap_hwmod omap2xxx_timer1_hwmod;
+extern struct omap_hwmod omap2xxx_timer2_hwmod;
+extern struct omap_hwmod omap2xxx_timer3_hwmod;
+extern struct omap_hwmod omap2xxx_timer4_hwmod;
+extern struct omap_hwmod omap2xxx_timer5_hwmod;
+extern struct omap_hwmod omap2xxx_timer6_hwmod;
+extern struct omap_hwmod omap2xxx_timer7_hwmod;
+extern struct omap_hwmod omap2xxx_timer8_hwmod;
+extern struct omap_hwmod omap2xxx_timer9_hwmod;
+extern struct omap_hwmod omap2xxx_timer10_hwmod;
+extern struct omap_hwmod omap2xxx_timer11_hwmod;
+extern struct omap_hwmod omap2xxx_timer12_hwmod;
+extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
+extern struct omap_hwmod omap2xxx_uart1_hwmod;
+extern struct omap_hwmod omap2xxx_uart2_hwmod;
+extern struct omap_hwmod omap2xxx_uart3_hwmod;
+extern struct omap_hwmod omap2xxx_dss_core_hwmod;
+extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
+extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
+extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
+extern struct omap_hwmod omap2xxx_gpio1_hwmod;
+extern struct omap_hwmod omap2xxx_gpio2_hwmod;
+extern struct omap_hwmod omap2xxx_gpio3_hwmod;
+extern struct omap_hwmod omap2xxx_gpio4_hwmod;
+extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
+extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
+extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+
+/* Common interface data across OMAP2xxx */
+extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
+extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
+extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
@@ -94,6 +142,8 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
 extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
 extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
 extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
+extern struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[];
 
 /* OMAP hwmod classes - forward declarations */
 extern struct omap_hwmod_class l3_hwmod_class;
@@ -105,6 +155,8 @@ extern struct omap_hwmod_class omap2_dss_hwmod_class;
 extern struct omap_hwmod_class omap2_dispc_hwmod_class;
 extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
 extern struct omap_hwmod_class omap2_venc_hwmod_class;
+extern struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc;
+extern struct omap_hwmod_class omap2_hdq1w_class;
 
 extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
 extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 36fa90b6ece8..78564895e914 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -38,27 +38,6 @@ static inline int omap4_opp_init(void)
 }
 #endif
 
-/*
- * cpuidle mach specific parameters
- *
- * The board code can override the default C-states definition using
- * omap3_pm_init_cpuidle
- */
-struct cpuidle_params {
-        u32 exit_latency;       /* exit_latency = sleep + wake-up latencies */
-        u32 target_residency;
-        u8 valid;               /* validates the C-state */
-};
-
-#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
-extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
-#else
-static
-inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
-{
-}
-#endif
-
 extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
 extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
 
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 95442b69ae27..facfffca9eac 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -171,8 +171,6 @@ static int omap2_allow_mpu_retention(void)
 
 static void omap2_enter_mpu_retention(void)
 {
-        int only_idle = 0;
-
         /* Putting MPU into the WFI state while a transfer is active
          * seems to cause the I2C block to timeout. Why? Good question. */
         if (omap2_i2c_active())
@@ -195,7 +193,6 @@ static void omap2_enter_mpu_retention(void)
 
                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
                                                  OMAP2_PM_PWSTCTRL);
-                only_idle = 1;
         }
 
         omap2_sram_idle();
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 703bd1099259..8b43aefba0ea 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -273,7 +273,7 @@ void omap_sram_idle(void)
         int per_next_state = PWRDM_POWER_ON;
         int core_next_state = PWRDM_POWER_ON;
         int per_going_off;
-        int core_prev_state, per_prev_state;
+        int core_prev_state;
         u32 sdrc_pwr = 0;
 
         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
@@ -375,10 +375,8 @@ void omap_sram_idle(void)
         pwrdm_post_transition();
 
         /* PER */
-        if (per_next_state < PWRDM_POWER_ON) {
-                per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
+        if (per_next_state < PWRDM_POWER_ON)
                 omap2_gpio_resume_after_idle();
-        }
 
         /* Disable IO-PAD and IO-CHAIN wakeup */
         if (omap3_has_io_wakeup() &&
@@ -702,7 +700,7 @@ static void __init pm_errata_configure(void)
 static int __init omap3_pm_init(void)
 {
         struct power_state *pwrst, *tmp;
-        struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
+        struct clockdomain *neon_clkdm, *mpu_clkdm;
         int ret;
 
         if (!cpu_is_omap34xx())
@@ -757,8 +755,6 @@ static int __init omap3_pm_init(void)
 
         neon_clkdm = clkdm_lookup("neon_clkdm");
         mpu_clkdm = clkdm_lookup("mpu_clkdm");
-        per_clkdm = clkdm_lookup("per_clkdm");
-        core_clkdm = clkdm_lookup("core_clkdm");
 
 #ifdef CONFIG_SUSPEND
         omap_pm_suspend = omap3_pm_suspend;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96ad3dbeac34..96114901b932 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
         return ret;
 }
 
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
-{
-        if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
-                pwrdm_wait_transition(clkdm->pwrdm.ptr);
-                return pwrdm_state_switch(clkdm->pwrdm.ptr);
-        }
-
-        return -EINVAL;
-}
-
 int pwrdm_pre_transition(void)
 {
         pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a8ce4d..8f88d65c46ea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 
 int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
 int pwrdm_pre_transition(void);
 int pwrdm_post_transition(void);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index b7ea468eea32..fb0a0a6869d1 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -311,7 +311,7 @@ void __init omap3xxx_powerdomains_init(void)
                  rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
                 pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
         else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
-                 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
+                 rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 ||
                  rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
                 pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
         else
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5aa5435e3ff1..6da3ba483ad1 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -177,6 +177,8 @@
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
 #define OMAP24XX_ST_GPIOS_SHIFT                         2
 #define OMAP24XX_ST_GPIOS_MASK                          (1 << 2)
+#define OMAP24XX_ST_32KSYNC_SHIFT                       1
+#define OMAP24XX_ST_32KSYNC_MASK                        (1 << 1)
 #define OMAP24XX_ST_GPT1_SHIFT                          0
 #define OMAP24XX_ST_GPT1_MASK                           (1 << 0)
 
@@ -307,6 +309,8 @@
 #define OMAP3430_ST_SR1_MASK                            (1 << 6)
 #define OMAP3430_ST_GPIO1_SHIFT                         3
 #define OMAP3430_ST_GPIO1_MASK                          (1 << 3)
+#define OMAP3430_ST_32KSYNC_SHIFT                       2
+#define OMAP3430_ST_32KSYNC_MASK                        (1 << 2)
 #define OMAP3430_ST_GPT12_SHIFT                         1
 #define OMAP3430_ST_GPT12_MASK                          (1 << 1)
 #define OMAP3430_ST_GPT1_SHIFT                          0
@@ -410,6 +414,19 @@
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
 extern void __iomem *cm2_base;
+extern void __iomem *prcm_mpu_base;
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
+extern void omap_prm_base_init(void);
+extern void omap_cm_base_init(void);
+#else
+static inline void omap_prm_base_init(void)
+{
+}
+static inline void omap_cm_base_init(void)
+{
+}
+#endif
 
 /**
  * struct omap_prcm_irq - describes a PRCM interrupt bit
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 626acfad7190..480f40a5ee42 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -42,6 +42,7 @@
 void __iomem *prm_base;
 void __iomem *cm_base;
 void __iomem *cm2_base;
+void __iomem *prcm_mpu_base;
 
 #define MAX_MODULE_ENABLE_WAIT          100000
 
@@ -155,4 +156,11 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
                 cm_base = omap2_globals->cm;
         if (omap2_globals->cm2)
                 cm2_base = omap2_globals->cm2;
+        if (omap2_globals->prcm_mpu)
+                prcm_mpu_base = omap2_globals->prcm_mpu;
+
+        if (cpu_is_omap44xx()) {
+                omap_prm_base_init();
+                omap_cm_base_init();
+        }
 }
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index d28f848897d6..dfe00ddb5c60 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -237,7 +237,7 @@ void omap_prcm_irq_complete(void)
  */
 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 {
-        int nr_regs = irq_setup->nr_regs;
+        int nr_regs;
         u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
         int offset, i;
         struct irq_chip_generic *gc;
@@ -246,6 +246,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
         if (!irq_setup)
                 return -EINVAL;
 
+        nr_regs = irq_setup->nr_regs;
+
         if (prcm_irq_setup) {
                 pr_err("PRCM: already initialized; won't reinitialize\n");
                 return -EINVAL;
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 9b3898a3ac9b..c12320c0ae95 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -18,20 +18,26 @@
 
 #include "iomap.h"
 #include "common.h"
+#include "prcm-common.h"
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prcm_mpu44xx.h"
 
-static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
-        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
-        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
-        [OMAP4430_CM1_PARTITION]                = 0,
-        [OMAP4430_CM2_PARTITION]                = 0,
-        [OMAP4430_SCRM_PARTITION]               = 0,
-        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
-};
+static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+
+/**
+ * omap_prm_base_init - Populates the prm partitions
+ *
+ * Populates the base addresses of the _prm_bases
+ * array used for read/write of prm module registers.
+ */
+void omap_prm_base_init(void)
+{
+        _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
+        _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+}
 
 /* Read a register in a PRM instance */
 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
@@ -39,8 +45,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_prm_bases[part]);
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst +
-                                               idx));
+        return __raw_readl(_prm_bases[part] + inst + idx);
 }
 
 /* Write into a register in a PRM instance */
@@ -49,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_prm_bases[part]);
-        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx));
+        __raw_writel(val, _prm_bases[part] + inst + idx);
 }
 
 /* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 9fc2f44188cb..292d4aaca068 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -133,7 +133,7 @@ static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
 #endif
 
-char *cmdline_find_option(char *str)
+static char *cmdline_find_option(char *str)
 {
         extern char *saved_command_line;
 
@@ -245,14 +245,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
         omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
         omap_up.autosuspend_timeout = info->autosuspend_timeout;
 
-        /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
-        if (!cpu_is_omap2420() && !cpu_is_ti816x())
-                omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
-
-        /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
-        if (cpu_is_omap34xx() || cpu_is_omap3630())
-                omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
-
         pdata = &omap_up;
         pdata_size = sizeof(struct omap_uart_port_info);
 
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index c512bac69ec5..840929bd9dae 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -90,7 +90,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 }
 
 static struct irqaction omap2_gp_timer_irq = {
-        .name           = "gp timer",
+        .name           = "gp_timer",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = omap2_gp_timer_interrupt,
 };
@@ -132,7 +132,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 }
 
 static struct clock_event_device clockevent_gpt = {
-        .name           = "gp timer",
+        .name           = "gp_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .shift          = 32,
         .set_next_event = omap2_gp_timer_set_next_event,
@@ -145,8 +145,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 {
         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
         struct omap_hwmod *oh;
+        struct resource irq_rsrc, mem_rsrc;
         size_t size;
         int res = 0;
+        int r;
 
         sprintf(name, "timer%d", gptimer_id);
         omap_hwmod_setup_one(name);
@@ -154,9 +156,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         if (!oh)
                 return -ENODEV;
 
-        timer->irq = oh->mpu_irqs[0].irq;
-        timer->phys_base = oh->slaves[0]->addr->pa_start;
-        size = oh->slaves[0]->addr->pa_end - timer->phys_base;
+        r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
+        if (r)
+                return -ENXIO;
+        timer->irq = irq_rsrc.start;
+
+        r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
+        if (r)
+                return -ENXIO;
+        timer->phys_base = mem_rsrc.start;
+        size = mem_rsrc.end - mem_rsrc.start;
 
         /* Static mapping, never released */
         timer->io_base = ioremap(timer->phys_base, size);
@@ -169,13 +178,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         if (IS_ERR(timer->fclk))
                 return -ENODEV;
 
-        sprintf(name, "gpt%d_ick", gptimer_id);
-        timer->iclk = clk_get(NULL, name);
-        if (IS_ERR(timer->iclk)) {
-                clk_put(timer->fclk);
-                return -ENODEV;
-        }
-
         omap_hwmod_enable(oh);
 
         sys_timer_reserved |= (1 << (gptimer_id - 1));
@@ -234,22 +236,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 }
 
 /* Clocksource code */
-
-#ifdef CONFIG_OMAP_32K_TIMER
-/*
- * When 32k-timer is enabled, don't use GPTimer for clocksource
- * instead, just leave default clocksource which uses the 32k
- * sync counter.  See clocksource setup in plat-omap/counter_32k.c
- */
-
-static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
-{
-        omap_init_clocksource_32k();
-}
-
-#else
-
 static struct omap_dm_timer clksrc;
+static bool use_gptimer_clksrc;
 
 /*
  * clocksource
@@ -260,7 +248,7 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs)
 }
 
 static struct clocksource clocksource_gpt = {
-        .name           = "gp timer",
+        .name           = "gp_timer",
         .rating         = 300,
         .read           = clocksource_read_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
@@ -276,7 +264,46 @@ static u32 notrace dmtimer_read_sched_clock(void)
 }
 
 /* Setup free-running counter for clocksource */
-static void __init omap2_gp_clocksource_init(int gptimer_id,
+static int __init omap2_sync32k_clocksource_init(void)
+{
+        int ret;
+        struct omap_hwmod *oh;
+        void __iomem *vbase;
+        const char *oh_name = "counter_32k";
+
+        /*
+         * First check hwmod data is available for sync32k counter
+         */
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh || oh->slaves_cnt == 0)
+                return -ENODEV;
+
+        omap_hwmod_setup_one(oh_name);
+
+        vbase = omap_hwmod_get_mpu_rt_va(oh);
+        if (!vbase) {
+                pr_warn("%s: failed to get counter_32k resource\n", __func__);
+                return -ENXIO;
+        }
+
+        ret = omap_hwmod_enable(oh);
+        if (ret) {
+                pr_warn("%s: failed to enable counter_32k module (%d)\n",
+                                                        __func__, ret);
+                return ret;
+        }
+
+        ret = omap_init_clocksource_32k(vbase);
+        if (ret) {
+                pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
+                                                        __func__, ret);
+                omap_hwmod_idle(oh);
+        }
+
+        return ret;
+}
+
+static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                                                 const char *fck_source)
 {
         int res;
@@ -284,9 +311,6 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
         BUG_ON(res);
 
-        pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
-                gptimer_id, clksrc.rate);
-
         __omap_dm_timer_load_start(&clksrc,
                         OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
         setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
@@ -294,15 +318,36 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
                 pr_err("Could not register clocksource %s\n",
                         clocksource_gpt.name);
+        else
+                pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
+                        gptimer_id, clksrc.rate);
+}
+
+static void __init omap2_clocksource_init(int gptimer_id,
+                                                const char *fck_source)
+{
+        /*
+         * First give preference to kernel parameter configuration
+         * by user (clocksource="gp_timer").
+         *
+         * In case of missing kernel parameter for clocksource,
+         * first check for availability for 32k-sync timer, in case
+         * of failure in finding 32k_counter module or registering
+         * it as clocksource, execution will fallback to gp-timer.
+         */
+        if (use_gptimer_clksrc == true)
+                omap2_gptimer_clocksource_init(gptimer_id, fck_source);
+        else if (omap2_sync32k_clocksource_init())
+                /* Fall back to gp-timer code */
+                omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }
-#endif
 
 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
                                 clksrc_nr, clksrc_src)                  \
 static void __init omap##name##_timer_init(void)                        \
 {                                                                       \
         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
-        omap2_gp_clocksource_init((clksrc_nr), clksrc_src);             \
+        omap2_clocksource_init((clksrc_nr), clksrc_src);                \
 }
 
 #define OMAP_SYS_TIMER(name)                                            \
@@ -333,7 +378,7 @@ static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
 static void __init omap4_timer_init(void)
 {
         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
-        omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
+        omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
 #ifdef CONFIG_LOCAL_TIMERS
         /* Local timers are not supprted on OMAP4430 ES1.0 */
         if (omap_rev() != OMAP4430_REV_ES1_0) {
@@ -501,3 +546,28 @@ static int __init omap2_dm_timer_init(void)
         return 0;
 }
 arch_initcall(omap2_dm_timer_init);
+
+/**
+ * omap2_override_clocksource - clocksource override with user configuration
+ *
+ * Allows user to override default clocksource, using kernel parameter
+ *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
+ *
+ * Note that, here we are using same standard kernel parameter "clocksource=",
+ * and not introducing any OMAP specific interface.
+ */
+static int __init omap2_override_clocksource(char *str)
+{
+        if (!str)
+                return 0;
+        /*
+         * For OMAP architecture, we only have two options
+         *    - sync_32k (default)
+         *    - gp_timer (sys_clk based)
+         */
+        if (!strcmp(str, "gp_timer"))
+                use_gptimer_clksrc = true;
+
+        return 0;
+}
+early_param("clocksource", omap2_override_clocksource);
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 7a7b89304c48..119d5a910f3a 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -31,6 +31,7 @@
 
 #include "twl-common.h"
 #include "pm.h"
+#include "voltage.h"
 
 static struct i2c_board_info __initdata pmic_i2c_board_info = {
         .addr           = 0x48,
@@ -47,6 +48,18 @@ static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
         },
 };
 
+static int twl_set_voltage(void *data, int target_uV)
+{
+        struct voltagedomain *voltdm = (struct voltagedomain *)data;
+        return voltdm_scale(voltdm, target_uV);
+}
+
+static int twl_get_voltage(void *data)
+{
+        struct voltagedomain *voltdm = (struct voltagedomain *)data;
+        return voltdm_get_voltage(voltdm);
+}
+
 void __init omap_pmic_init(int bus, u32 clkrate,
                            const char *pmic_type, int pmic_irq,
                            struct twl4030_platform_data *pmic_data)
@@ -153,6 +166,48 @@ static struct regulator_init_data omap3_vpll2_idata = {
         .consumer_supplies              = omap3_vpll2_supplies,
 };
 
+static struct regulator_consumer_supply omap3_vdd1_supply[] = {
+        REGULATOR_SUPPLY("vcc", "mpu.0"),
+};
+
+static struct regulator_consumer_supply omap3_vdd2_supply[] = {
+        REGULATOR_SUPPLY("vcc", "l3_main.0"),
+};
+
+static struct regulator_init_data omap3_vdd1 = {
+        .constraints = {
+                .name                   = "vdd_mpu_iva",
+                .min_uV                 = 600000,
+                .max_uV                 = 1450000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap3_vdd1_supply),
+        .consumer_supplies              = omap3_vdd1_supply,
+};
+
+static struct regulator_init_data omap3_vdd2 = {
+        .constraints = {
+                .name                   = "vdd_core",
+                .min_uV                 = 600000,
+                .max_uV                 = 1450000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap3_vdd2_supply),
+        .consumer_supplies              = omap3_vdd2_supply,
+};
+
+static struct twl_regulator_driver_data omap3_vdd1_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+
+static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+
 void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                                   u32 pdata_flags, u32 regulators_flags)
 {
@@ -160,6 +215,16 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                 pmic_data->irq_base = TWL4030_IRQ_BASE;
         if (!pmic_data->irq_end)
                 pmic_data->irq_end = TWL4030_IRQ_END;
+        if (!pmic_data->vdd1) {
+                omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
+                omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
+                pmic_data->vdd1 = &omap3_vdd1;
+        }
+        if (!pmic_data->vdd2) {
+                omap3_vdd2.driver_data = &omap3_vdd2_drvdata;
+                omap3_vdd2_drvdata.data = voltdm_lookup("core");
+                pmic_data->vdd2 = &omap3_vdd2;
+        }
 
         /* Common platform data configurations */
         if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
@@ -201,6 +266,7 @@ static struct regulator_init_data omap4_vdac_idata = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
+        .supply_regulator       = "V2V1",
 };
 
 static struct regulator_init_data omap4_vaux2_idata = {
@@ -291,6 +357,7 @@ static struct regulator_init_data omap4_vcxio_idata = {
         },
         .num_consumer_supplies  = ARRAY_SIZE(omap4_vcxio_supply),
         .consumer_supplies      = omap4_vcxio_supply,
+        .supply_regulator       = "V2V1",
 };
 
 static struct regulator_init_data omap4_vusb_idata = {
@@ -310,6 +377,105 @@ static struct regulator_init_data omap4_clk32kg_idata = {
         },
 };
 
+static struct regulator_consumer_supply omap4_vdd1_supply[] = {
+        REGULATOR_SUPPLY("vcc", "mpu.0"),
+};
+
+static struct regulator_consumer_supply omap4_vdd2_supply[] = {
+        REGULATOR_SUPPLY("vcc", "iva.0"),
+};
+
+static struct regulator_consumer_supply omap4_vdd3_supply[] = {
+        REGULATOR_SUPPLY("vcc", "l3_main.0"),
+};
+
+static struct regulator_init_data omap4_vdd1 = {
+        .constraints = {
+                .name                   = "vdd_mpu",
+                .min_uV                 = 500000,
+                .max_uV                 = 1500000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap4_vdd1_supply),
+        .consumer_supplies              = omap4_vdd1_supply,
+};
+
+static struct regulator_init_data omap4_vdd2 = {
+        .constraints = {
+                .name                   = "vdd_iva",
+                .min_uV                 = 500000,
+                .max_uV                 = 1500000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap4_vdd2_supply),
+        .consumer_supplies              = omap4_vdd2_supply,
+};
+
+static struct regulator_init_data omap4_vdd3 = {
+        .constraints = {
+                .name                   = "vdd_core",
+                .min_uV                 = 500000,
+                .max_uV                 = 1500000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap4_vdd3_supply),
+        .consumer_supplies              = omap4_vdd3_supply,
+};
+
+
+static struct twl_regulator_driver_data omap4_vdd1_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+
+static struct twl_regulator_driver_data omap4_vdd2_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+
+static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+
+static struct regulator_consumer_supply omap4_v1v8_supply[] = {
+        REGULATOR_SUPPLY("vio", "1-004b"),
+};
+
+static struct regulator_init_data omap4_v1v8_idata = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+                .always_on              = true,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(omap4_v1v8_supply),
+        .consumer_supplies      = omap4_v1v8_supply,
+};
+
+static struct regulator_consumer_supply omap4_v2v1_supply[] = {
+        REGULATOR_SUPPLY("v2v1", "1-004b"),
+};
+
+static struct regulator_init_data omap4_v2v1_idata = {
+        .constraints = {
+                .min_uV                 = 2100000,
+                .max_uV                 = 2100000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(omap4_v2v1_supply),
+        .consumer_supplies      = omap4_v2v1_supply,
+};
+
 void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                                   u32 pdata_flags, u32 regulators_flags)
 {
@@ -318,6 +484,24 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
         if (!pmic_data->irq_end)
                 pmic_data->irq_end = TWL6030_IRQ_END;
 
+        if (!pmic_data->vdd1) {
+                omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
+                omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
+                pmic_data->vdd1 = &omap4_vdd1;
+        }
+
+        if (!pmic_data->vdd2) {
+                omap4_vdd2.driver_data = &omap4_vdd2_drvdata;
+                omap4_vdd2_drvdata.data = voltdm_lookup("iva");
+                pmic_data->vdd2 = &omap4_vdd2;
+        }
+
+        if (!pmic_data->vdd3) {
+                omap4_vdd3.driver_data = &omap4_vdd3_drvdata;
+                omap4_vdd3_drvdata.data = voltdm_lookup("core");
+                pmic_data->vdd3 = &omap4_vdd3;
+        }
+
         /* Common platform data configurations */
         if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
                 pmic_data->usb = &omap4_usb_pdata;
@@ -350,5 +534,11 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
         if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
             !pmic_data->clk32kg)
                 pmic_data->clk32kg = &omap4_clk32kg_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_V1V8 && !pmic_data->v1v8)
+                pmic_data->v1v8 = &omap4_v1v8_idata;
+
+        if (regulators_flags & TWL_COMMON_REGULATOR_V2V1 && !pmic_data->v2v1)
+                pmic_data->v2v1 = &omap4_v2v1_idata;
 }
 #endif /* CONFIG_ARCH_OMAP4 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 09627483a57f..8fe71cfd002c 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -22,6 +22,8 @@
 #define TWL_COMMON_REGULATOR_VCXIO      (1 << 8)
 #define TWL_COMMON_REGULATOR_VUSB       (1 << 9)
 #define TWL_COMMON_REGULATOR_CLK32KG    (1 << 10)
+#define TWL_COMMON_REGULATOR_V1V8       (1 << 11)
+#define TWL_COMMON_REGULATOR_V2V1       (1 << 12)
 
 /* TWL4030 LDO regulators */
 #define TWL_COMMON_REGULATOR_VPLL1      (1 << 4)
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 8d5ed775dd56..b19d1b43c12e 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -90,7 +90,7 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
         musb_plat.mode = board_data->mode;
         musb_plat.extvbus = board_data->extvbus;
 
-        if (cpu_is_omap3517() || cpu_is_omap3505()) {
+        if (soc_is_am35xx()) {
                 oh_name = "am35x_otg_hs";
                 name = "musb-am35x";
         } else if (cpu_is_ti81xx()) {
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 994d8f591a1d..db84a46ce7fd 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
         tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
         if (tmp > 4)
                 return -ERANGE;
-        if (tmp <= 0)
+        if (tmp == 0)
                 tmp = 1;
         t.page_burst_access = (fclk_ps * tmp) / 1000;
 
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index a5ec7f8f2ea8..5d8eaf31569c 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -46,6 +46,7 @@ static struct omap_vc_common omap3_vc_common = {
 };
 
 struct omap_vc_channel omap3_vc_mpu = {
+        .flags = OMAP_VC_CHANNEL_DEFAULT,
         .common = &omap3_vc_common,
         .smps_sa_reg     = OMAP3_PRM_VC_SMPS_SA_OFFSET,
         .smps_volra_reg  = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 8a36342e60d2..4dc60e83e00d 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -73,7 +73,8 @@ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
 int voltdm_scale(struct voltagedomain *voltdm,
                  unsigned long target_volt)
 {
-        int ret;
+        int ret, i;
+        unsigned long volt = 0;
 
         if (!voltdm || IS_ERR(voltdm)) {
                 pr_warning("%s: VDD specified does not exist!\n", __func__);
@@ -86,9 +87,23 @@ int voltdm_scale(struct voltagedomain *voltdm,
                 return -ENODATA;
         }
 
-        ret = voltdm->scale(voltdm, target_volt);
+        /* Adjust voltage to the exact voltage from the OPP table */
+        for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
+                if (voltdm->volt_data[i].volt_nominal >= target_volt) {
+                        volt = voltdm->volt_data[i].volt_nominal;
+                        break;
+                }
+        }
+
+        if (!volt) {
+                pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n",
+                           __func__, target_volt);
+                return -EINVAL;
+        }
+
+        ret = voltdm->scale(voltdm, volt);
         if (!ret)
-                voltdm->nominal_volt = target_volt;
+                voltdm->nominal_volt = volt;
 
         return ret;
 }
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index 57db2038b23c..d0103c80d040 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -118,7 +118,7 @@ void __init omap3xxx_voltagedomains_init(void)
         }
 #endif
 
-        if (cpu_is_omap3517() || cpu_is_omap3505())
+        if (soc_is_am35xx())
                 voltdms = voltagedomains_am35xx;
         else
                 voltdms = voltagedomains_omap3;
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 4067669d96c4..b2f1c67043a2 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -14,6 +14,7 @@
 #include <plat/omap_hwmod.h>
 
 #include "wd_timer.h"
+#include "common.h"
 
 /*
  * In order to avoid any assumptions from bootloader regarding WDT
@@ -25,6 +26,8 @@
 #define OMAP_WDT_WPS            0x34
 #define OMAP_WDT_SPR            0x48
 
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
 
 int omap2_wd_timer_disable(struct omap_hwmod *oh)
 {
@@ -54,3 +57,45 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
         return 0;
 }
 
+/**
+ * omap2_wdtimer_reset - reset and disable the WDTIMER IP block
+ * @oh: struct omap_hwmod *
+ *
+ * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
+ * care to execute the special watchdog disable sequence.  This is
+ * because the watchdog is re-armed upon OCP softreset.  (On OMAP4,
+ * this behavior was apparently changed and the watchdog is no longer
+ * re-armed after an OCP soft-reset.)  Returns -ETIMEDOUT if the reset
+ * did not complete, or 0 upon success.
+ *
+ * XXX Most of this code should be moved to the omap_hwmod.c layer
+ * during a normal merge window.  omap_hwmod_softreset() should be
+ * renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
+ * should call the hwmod _ocp_softreset() code.
+ */
+int omap2_wd_timer_reset(struct omap_hwmod *oh)
+{
+        int c = 0;
+
+        /* Write to the SOFTRESET bit */
+        omap_hwmod_softreset(oh);
+
+        /* Poll on RESETDONE bit */
+        omap_test_timeout((omap_hwmod_read(oh,
+                                           oh->class->sysc->syss_offs)
+                           & SYSS_RESETDONE_MASK),
+                          MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (oh->class->sysc->srst_udelay)
+                udelay(oh->class->sysc->srst_udelay);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+        else
+                pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                         oh->name, c);
+
+        return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
+                omap2_wd_timer_disable(oh);
+}
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h
index e0054a2d5505..f6bbba73b535 100644
--- a/arch/arm/mach-omap2/wd_timer.h
+++ b/arch/arm/mach-omap2/wd_timer.h
@@ -13,5 +13,6 @@
 #include <plat/omap_hwmod.h>
 
 extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
+extern int omap2_wd_timer_reset(struct omap_hwmod *oh);
 
 #endif