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-rw-r--r--arch/arm/mach-omap2/Kconfig41
-rw-r--r--arch/arm/mach-omap2/Makefile11
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c273
-rw-r--r--arch/arm/mach-omap2/board-generic.c7
-rw-r--r--arch/arm/mach-omap2/board-h4.c365
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c234
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c7
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c1064
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c1735
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c10
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c6
-rw-r--r--arch/arm/mach-omap2/clkt_iclk.c20
-rw-r--r--arch/arm/mach-omap2/clock.c57
-rw-r--r--arch/arm/mach-omap2/clock.h179
-rw-r--r--arch/arm/mach-omap2/clock36xx.c7
-rw-r--r--arch/arm/mach-omap2/clock3xxx.h3
-rw-r--r--arch/arm/mach-omap2/common-board-devices.h1
-rw-r--r--arch/arm/mach-omap2/common.h10
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c34
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c125
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c12
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c50
-rw-r--r--arch/arm/mach-omap2/gpmc.c4
-rw-r--r--arch/arm/mach-omap2/io.c58
-rw-r--r--arch/arm/mach-omap2/msdi.c69
-rw-r--r--arch/arm/mach-omap2/mux.h2
-rw-r--r--arch/arm/mach-omap2/mux2420.c690
-rw-r--r--arch/arm/mach-omap2/mux2420.h282
-rw-r--r--arch/arm/mach-omap2/mux2430.c793
-rw-r--r--arch/arm/mach-omap2/mux2430.h370
-rw-r--r--arch/arm/mach-omap2/omap-mpuss-lowpower.c3
-rw-r--r--arch/arm/mach-omap2/omap-smp.c6
-rw-r--r--arch/arm/mach-omap2/omap4-common.c9
-rw-r--r--arch/arm/mach-omap2/omap_device.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c33
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c137
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c266
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c165
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c72
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h5
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c159
-rw-r--r--arch/arm/mach-omap2/pm44xx.c15
-rw-r--r--arch/arm/mach-omap2/prm.h1
-rw-r--r--arch/arm/mach-omap2/prm_common.c66
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c4
-rw-r--r--arch/arm/mach-omap2/timer.c10
48 files changed, 646 insertions, 6837 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index dc21df166161..0af7ca02314d 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -50,11 +50,12 @@ config SOC_OMAP5
50 bool "TI OMAP5" 50 bool "TI OMAP5"
51 depends on ARCH_MULTI_V7 51 depends on ARCH_MULTI_V7
52 select ARCH_OMAP2PLUS 52 select ARCH_OMAP2PLUS
53 select ARCH_HAS_OPP
53 select ARM_CPU_SUSPEND if PM 54 select ARM_CPU_SUSPEND if PM
54 select ARM_GIC 55 select ARM_GIC
55 select CPU_V7 56 select CPU_V7
56 select HAVE_ARM_SCU if SMP 57 select HAVE_ARM_SCU if SMP
57 select HAVE_ARM_TWD if LOCAL_TIMERS 58 select HAVE_ARM_TWD if SMP
58 select HAVE_SMP 59 select HAVE_SMP
59 select HAVE_ARM_ARCH_TIMER 60 select HAVE_ARM_ARCH_TIMER
60 select ARM_ERRATA_798181 if SMP 61 select ARM_ERRATA_798181 if SMP
@@ -63,6 +64,7 @@ config SOC_AM33XX
63 bool "TI AM33XX" 64 bool "TI AM33XX"
64 depends on ARCH_MULTI_V7 65 depends on ARCH_MULTI_V7
65 select ARCH_OMAP2PLUS 66 select ARCH_OMAP2PLUS
67 select ARCH_HAS_OPP
66 select ARM_CPU_SUSPEND if PM 68 select ARM_CPU_SUSPEND if PM
67 select CPU_V7 69 select CPU_V7
68 select MULTI_IRQ_HANDLER 70 select MULTI_IRQ_HANDLER
@@ -72,10 +74,22 @@ config SOC_AM43XX
72 depends on ARCH_MULTI_V7 74 depends on ARCH_MULTI_V7
73 select CPU_V7 75 select CPU_V7
74 select ARCH_OMAP2PLUS 76 select ARCH_OMAP2PLUS
77 select ARCH_HAS_OPP
75 select MULTI_IRQ_HANDLER 78 select MULTI_IRQ_HANDLER
76 select ARM_GIC 79 select ARM_GIC
77 select MACH_OMAP_GENERIC 80 select MACH_OMAP_GENERIC
78 81
82config SOC_DRA7XX
83 bool "TI DRA7XX"
84 depends on ARCH_MULTI_V7
85 select ARCH_OMAP2PLUS
86 select ARCH_HAS_OPP
87 select ARM_CPU_SUSPEND if PM
88 select ARM_GIC
89 select CPU_V7
90 select HAVE_SMP
91 select HAVE_ARM_ARCH_TIMER
92
79config ARCH_OMAP2PLUS 93config ARCH_OMAP2PLUS
80 bool 94 bool
81 select ARCH_HAS_BANDGAP 95 select ARCH_HAS_BANDGAP
@@ -128,14 +142,6 @@ config SOC_HAS_REALTIME_COUNTER
128 depends on SOC_OMAP5 || SOC_DRA7XX 142 depends on SOC_OMAP5 || SOC_DRA7XX
129 default y 143 default y
130 144
131config SOC_DRA7XX
132 bool "TI DRA7XX"
133 select ARM_ARCH_TIMER
134 select CPU_V7
135 select ARM_GIC
136 select HAVE_SMP
137 select COMMON_CLK
138
139comment "OMAP Core Type" 145comment "OMAP Core Type"
140 depends on ARCH_OMAP2 146 depends on ARCH_OMAP2
141 147
@@ -192,19 +198,6 @@ config MACH_OMAP2_TUSB6010
192 depends on ARCH_OMAP2 && SOC_OMAP2420 198 depends on ARCH_OMAP2 && SOC_OMAP2420
193 default y if MACH_NOKIA_N8X0 199 default y if MACH_NOKIA_N8X0
194 200
195config MACH_OMAP_H4
196 bool "OMAP 2420 H4 board"
197 depends on SOC_OMAP2420
198 default y
199 select OMAP_DEBUG_DEVICES
200 select OMAP_PACKAGE_ZAF
201
202config MACH_OMAP_2430SDP
203 bool "OMAP 2430 SDP board"
204 depends on SOC_OMAP2430
205 default y
206 select OMAP_PACKAGE_ZAC
207
208config MACH_OMAP3_BEAGLE 201config MACH_OMAP3_BEAGLE
209 bool "OMAP3 BEAGLE board" 202 bool "OMAP3 BEAGLE board"
210 depends on ARCH_OMAP3 203 depends on ARCH_OMAP3
@@ -279,9 +272,6 @@ config MACH_OMAP_3430SDP
279 default y 272 default y
280 select OMAP_PACKAGE_CBB 273 select OMAP_PACKAGE_CBB
281 274
282config MACH_NOKIA_N800
283 bool
284
285config MACH_NOKIA_N810 275config MACH_NOKIA_N810
286 bool 276 bool
287 277
@@ -292,7 +282,6 @@ config MACH_NOKIA_N8X0
292 bool "Nokia N800/N810" 282 bool "Nokia N800/N810"
293 depends on SOC_OMAP2420 283 depends on SOC_OMAP2420
294 default y 284 default y
295 select MACH_NOKIA_N800
296 select MACH_NOKIA_N810 285 select MACH_NOKIA_N810
297 select MACH_NOKIA_N810_WIMAX 286 select MACH_NOKIA_N810_WIMAX
298 select OMAP_PACKAGE_ZAC 287 select OMAP_PACKAGE_ZAC
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index adcef406ff0a..e6eec6f72fd3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -66,8 +66,6 @@ obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
66obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o 66obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
67 67
68# Pin multiplexing 68# Pin multiplexing
69obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
70obj-$(CONFIG_SOC_OMAP2430) += mux2430.o
71obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o 69obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
72 70
73# SMS/SDRC 71# SMS/SDRC
@@ -132,6 +130,7 @@ obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
132obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common) 130obj-$(CONFIG_SOC_AM43XX) += $(voltagedomain-common)
133obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) 131obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
134obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o 132obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
133obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
135 134
136# OMAP powerdomain framework 135# OMAP powerdomain framework
137powerdomain-common += powerdomain.o powerdomain-common.o 136powerdomain-common += powerdomain.o powerdomain-common.o
@@ -186,12 +185,14 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
186obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 185obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
187obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o 186obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
188obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o 187obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
189obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) cclock44xx_data.o 188obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
190obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 189obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
191obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o 190obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
192obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
193obj-$(CONFIG_SOC_OMAP5) += $(clock-common) 191obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
194obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o 192obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
193obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
194obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
195obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o
195 196
196# OMAP2 clock rate set data (old "OPP" data) 197# OMAP2 clock rate set data (old "OPP" data)
197obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o 198obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
@@ -237,8 +238,6 @@ obj-$(CONFIG_SOC_OMAP2420) += msdi.o
237 238
238# Specific board support 239# Specific board support
239obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o 240obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o pdata-quirks.o
240obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
241obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
242obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o 241obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
243obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o 242obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
244obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o 243obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
deleted file mode 100644
index c711ad6ac067..000000000000
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ /dev/null
@@ -1,273 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-2430sdp.c
3 *
4 * Copyright (C) 2006 Texas Instruments
5 *
6 * Modified from mach-omap2/board-generic.c
7 *
8 * Initial Code : Based on a patch from Komal Shah and Richard Woodruff
9 * Updated the Code for 2430 SDP : Syed Mohammed Khasim
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/physmap.h>
22#include <linux/mmc/host.h>
23#include <linux/delay.h>
24#include <linux/i2c/twl.h>
25#include <linux/regulator/machine.h>
26#include <linux/err.h>
27#include <linux/clk.h>
28#include <linux/io.h>
29#include <linux/gpio.h>
30#include <linux/usb/phy.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35
36#include "common.h"
37#include "gpmc.h"
38#include "gpmc-smc91x.h"
39
40#include <video/omapdss.h>
41#include <video/omap-panel-data.h>
42
43#include "mux.h"
44#include "hsmmc.h"
45#include "common-board-devices.h"
46
47#define SDP2430_CS0_BASE 0x04000000
48#define SECONDARY_LCD_GPIO 147
49
50static struct mtd_partition sdp2430_partitions[] = {
51 /* bootloader (U-Boot, etc) in first sector */
52 {
53 .name = "bootloader",
54 .offset = 0,
55 .size = SZ_256K,
56 .mask_flags = MTD_WRITEABLE, /* force read-only */
57 },
58 /* bootloader params in the next sector */
59 {
60 .name = "params",
61 .offset = MTDPART_OFS_APPEND,
62 .size = SZ_128K,
63 .mask_flags = 0,
64 },
65 /* kernel */
66 {
67 .name = "kernel",
68 .offset = MTDPART_OFS_APPEND,
69 .size = SZ_2M,
70 .mask_flags = 0
71 },
72 /* file system */
73 {
74 .name = "filesystem",
75 .offset = MTDPART_OFS_APPEND,
76 .size = MTDPART_SIZ_FULL,
77 .mask_flags = 0
78 }
79};
80
81static struct physmap_flash_data sdp2430_flash_data = {
82 .width = 2,
83 .parts = sdp2430_partitions,
84 .nr_parts = ARRAY_SIZE(sdp2430_partitions),
85};
86
87static struct resource sdp2430_flash_resource = {
88 .start = SDP2430_CS0_BASE,
89 .end = SDP2430_CS0_BASE + SZ_64M - 1,
90 .flags = IORESOURCE_MEM,
91};
92
93static struct platform_device sdp2430_flash_device = {
94 .name = "physmap-flash",
95 .id = 0,
96 .dev = {
97 .platform_data = &sdp2430_flash_data,
98 },
99 .num_resources = 1,
100 .resource = &sdp2430_flash_resource,
101};
102
103/* LCD */
104#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
105#define SDP2430_LCD_PANEL_ENABLE_GPIO 154
106
107static const struct display_timing sdp2430_lcd_videomode = {
108 .pixelclock = { 0, 5400000, 0 },
109
110 .hactive = { 0, 240, 0 },
111 .hfront_porch = { 0, 3, 0 },
112 .hback_porch = { 0, 39, 0 },
113 .hsync_len = { 0, 3, 0 },
114
115 .vactive = { 0, 320, 0 },
116 .vfront_porch = { 0, 2, 0 },
117 .vback_porch = { 0, 7, 0 },
118 .vsync_len = { 0, 1, 0 },
119
120 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
121 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
122};
123
124static struct panel_dpi_platform_data sdp2430_lcd_pdata = {
125 .name = "lcd",
126 .source = "dpi.0",
127
128 .data_lines = 16,
129
130 .display_timing = &sdp2430_lcd_videomode,
131
132 .enable_gpio = SDP2430_LCD_PANEL_ENABLE_GPIO,
133 .backlight_gpio = SDP2430_LCD_PANEL_BACKLIGHT_GPIO,
134};
135
136static struct platform_device sdp2430_lcd_device = {
137 .name = "panel-dpi",
138 .id = 0,
139 .dev.platform_data = &sdp2430_lcd_pdata,
140};
141
142static struct omap_dss_board_info sdp2430_dss_data = {
143 .default_display_name = "lcd",
144};
145
146static struct platform_device *sdp2430_devices[] __initdata = {
147 &sdp2430_flash_device,
148 &sdp2430_lcd_device,
149};
150
151#if IS_ENABLED(CONFIG_SMC91X)
152
153static struct omap_smc91x_platform_data board_smc91x_data = {
154 .cs = 5,
155 .gpio_irq = 149,
156 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
157 IORESOURCE_IRQ_LOWLEVEL,
158
159};
160
161static void __init board_smc91x_init(void)
162{
163 omap_mux_init_gpio(149, OMAP_PIN_INPUT);
164 gpmc_smc91x_init(&board_smc91x_data);
165}
166
167#else
168
169static inline void board_smc91x_init(void)
170{
171}
172
173#endif
174
175static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
176 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
177};
178
179/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
180static struct regulator_init_data sdp2430_vmmc1 = {
181 .constraints = {
182 .min_uV = 1850000,
183 .max_uV = 3150000,
184 .valid_modes_mask = REGULATOR_MODE_NORMAL
185 | REGULATOR_MODE_STANDBY,
186 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
187 | REGULATOR_CHANGE_MODE
188 | REGULATOR_CHANGE_STATUS,
189 },
190 .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies),
191 .consumer_supplies = &sdp2430_vmmc1_supplies[0],
192};
193
194static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
195};
196
197static struct twl4030_platform_data sdp2430_twldata = {
198 /* platform_data for children goes here */
199 .gpio = &sdp2430_gpio_data,
200 .vmmc1 = &sdp2430_vmmc1,
201};
202
203static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
204 {
205 I2C_BOARD_INFO("isp1301_omap", 0x2D),
206 .flags = I2C_CLIENT_WAKE,
207 },
208};
209
210static int __init omap2430_i2c_init(void)
211{
212 sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78);
213 omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
214 ARRAY_SIZE(sdp2430_i2c1_boardinfo));
215 omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START,
216 &sdp2430_twldata);
217 return 0;
218}
219
220static struct omap2_hsmmc_info mmc[] __initdata = {
221 {
222 .mmc = 1,
223 .caps = MMC_CAP_4_BIT_DATA,
224 .gpio_cd = -EINVAL,
225 .gpio_wp = -EINVAL,
226 .ext_clock = 1,
227 },
228 {} /* Terminator */
229};
230
231#ifdef CONFIG_OMAP_MUX
232static struct omap_board_mux board_mux[] __initdata = {
233 { .reg_offset = OMAP_MUX_TERMINATOR },
234};
235#endif
236
237static void __init omap_2430sdp_init(void)
238{
239 omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
240
241 omap2430_i2c_init();
242
243 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
244 omap_serial_init();
245 omap_sdrc_init(NULL, NULL);
246 omap_hsmmc_init(mmc);
247
248 omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
249 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
250 usb_musb_init(NULL);
251
252 board_smc91x_init();
253
254 /* Turn off secondary LCD backlight */
255 gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW,
256 "Secondary LCD backlight");
257
258 omap_display_init(&sdp2430_dss_data);
259}
260
261MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
262 /* Maintainer: Syed Khasim - Texas Instruments Inc */
263 .atag_offset = 0x100,
264 .reserve = omap_reserve,
265 .map_io = omap243x_map_io,
266 .init_early = omap2430_init_early,
267 .init_irq = omap2_init_irq,
268 .handle_irq = omap2_intc_handle_irq,
269 .init_machine = omap_2430sdp_init,
270 .init_late = omap2430_init_late,
271 .init_time = omap2_sync32k_timer_init,
272 .restart = omap2xxx_restart,
273MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 8d972ff18c56..8e3daa11602b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -78,6 +78,7 @@ MACHINE_END
78 78
79#ifdef CONFIG_ARCH_OMAP3 79#ifdef CONFIG_ARCH_OMAP3
80static const char *omap3_boards_compat[] __initdata = { 80static const char *omap3_boards_compat[] __initdata = {
81 "ti,omap3430",
81 "ti,omap3", 82 "ti,omap3",
82 NULL, 83 NULL,
83}; 84};
@@ -173,6 +174,8 @@ MACHINE_END
173 174
174#ifdef CONFIG_ARCH_OMAP4 175#ifdef CONFIG_ARCH_OMAP4
175static const char *omap4_boards_compat[] __initdata = { 176static const char *omap4_boards_compat[] __initdata = {
177 "ti,omap4460",
178 "ti,omap4430",
176 "ti,omap4", 179 "ti,omap4",
177 NULL, 180 NULL,
178}; 181};
@@ -193,6 +196,8 @@ MACHINE_END
193 196
194#ifdef CONFIG_SOC_OMAP5 197#ifdef CONFIG_SOC_OMAP5
195static const char *omap5_boards_compat[] __initdata = { 198static const char *omap5_boards_compat[] __initdata = {
199 "ti,omap5432",
200 "ti,omap5430",
196 "ti,omap5", 201 "ti,omap5",
197 NULL, 202 NULL,
198}; 203};
@@ -213,6 +218,7 @@ MACHINE_END
213 218
214#ifdef CONFIG_SOC_AM43XX 219#ifdef CONFIG_SOC_AM43XX
215static const char *am43_boards_compat[] __initdata = { 220static const char *am43_boards_compat[] __initdata = {
221 "ti,am4372",
216 "ti,am43", 222 "ti,am43",
217 NULL, 223 NULL,
218}; 224};
@@ -230,6 +236,7 @@ MACHINE_END
230 236
231#ifdef CONFIG_SOC_DRA7XX 237#ifdef CONFIG_SOC_DRA7XX
232static const char *dra7xx_boards_compat[] __initdata = { 238static const char *dra7xx_boards_compat[] __initdata = {
239 "ti,dra7xx",
233 "ti,dra7", 240 "ti,dra7",
234 NULL, 241 NULL,
235}; 242};
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
deleted file mode 100644
index f7808349a734..000000000000
--- a/arch/arm/mach-omap2/board-h4.c
+++ /dev/null
@@ -1,365 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-h4.c
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Paul Mundt <paul.mundt@nokia.com>
6 *
7 * Modified from mach-omap/omap1/board-generic.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/gpio.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/mtd.h>
18#include <linux/mtd/partitions.h>
19#include <linux/mtd/physmap.h>
20#include <linux/delay.h>
21#include <linux/workqueue.h>
22#include <linux/i2c.h>
23#include <linux/platform_data/at24.h>
24#include <linux/input.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/io.h>
28#include <linux/input/matrix_keypad.h>
29#include <linux/mfd/menelaus.h>
30#include <linux/omap-dma.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35
36#include <video/omapdss.h>
37#include <video/omap-panel-data.h>
38
39#include "common.h"
40#include "mux.h"
41#include "control.h"
42#include "gpmc.h"
43#include "gpmc-smc91x.h"
44
45#define H4_FLASH_CS 0
46
47#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
48static const uint32_t board_matrix_keys[] = {
49 KEY(0, 0, KEY_LEFT),
50 KEY(1, 0, KEY_RIGHT),
51 KEY(2, 0, KEY_A),
52 KEY(3, 0, KEY_B),
53 KEY(4, 0, KEY_C),
54 KEY(0, 1, KEY_DOWN),
55 KEY(1, 1, KEY_UP),
56 KEY(2, 1, KEY_E),
57 KEY(3, 1, KEY_F),
58 KEY(4, 1, KEY_G),
59 KEY(0, 2, KEY_ENTER),
60 KEY(1, 2, KEY_I),
61 KEY(2, 2, KEY_J),
62 KEY(3, 2, KEY_K),
63 KEY(4, 2, KEY_3),
64 KEY(0, 3, KEY_M),
65 KEY(1, 3, KEY_N),
66 KEY(2, 3, KEY_O),
67 KEY(3, 3, KEY_P),
68 KEY(4, 3, KEY_Q),
69 KEY(0, 4, KEY_R),
70 KEY(1, 4, KEY_4),
71 KEY(2, 4, KEY_T),
72 KEY(3, 4, KEY_U),
73 KEY(4, 4, KEY_ENTER),
74 KEY(0, 5, KEY_V),
75 KEY(1, 5, KEY_W),
76 KEY(2, 5, KEY_L),
77 KEY(3, 5, KEY_S),
78 KEY(4, 5, KEY_ENTER),
79};
80
81static const struct matrix_keymap_data board_keymap_data = {
82 .keymap = board_matrix_keys,
83 .keymap_size = ARRAY_SIZE(board_matrix_keys),
84};
85
86static unsigned int board_keypad_row_gpios[] = {
87 88, 89, 124, 11, 6, 96
88};
89
90static unsigned int board_keypad_col_gpios[] = {
91 90, 91, 100, 36, 12, 97, 98
92};
93
94static struct matrix_keypad_platform_data board_keypad_platform_data = {
95 .keymap_data = &board_keymap_data,
96 .row_gpios = board_keypad_row_gpios,
97 .num_row_gpios = ARRAY_SIZE(board_keypad_row_gpios),
98 .col_gpios = board_keypad_col_gpios,
99 .num_col_gpios = ARRAY_SIZE(board_keypad_col_gpios),
100 .active_low = 1,
101
102 .debounce_ms = 20,
103 .col_scan_delay_us = 5,
104};
105
106static struct platform_device board_keyboard = {
107 .name = "matrix-keypad",
108 .id = -1,
109 .dev = {
110 .platform_data = &board_keypad_platform_data,
111 },
112};
113static void __init board_mkp_init(void)
114{
115 omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
116 omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
117 omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
118 omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
119 if (omap_has_menelaus()) {
120 omap_mux_init_signal("sdrc_a14.gpio0",
121 OMAP_PULL_ENA | OMAP_PULL_UP);
122 omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
123 omap_mux_init_signal("gpio_98", 0);
124 board_keypad_row_gpios[5] = 0;
125 board_keypad_col_gpios[2] = 15;
126 board_keypad_col_gpios[6] = 18;
127 } else {
128 omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
129 omap_mux_init_signal("gpio_100", 0);
130 omap_mux_init_signal("gpio_98", 0);
131 }
132 omap_mux_init_signal("gpio_90", 0);
133 omap_mux_init_signal("gpio_91", 0);
134 omap_mux_init_signal("gpio_36", 0);
135 omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
136 omap_mux_init_signal("gpio_97", 0);
137
138 platform_device_register(&board_keyboard);
139}
140#else
141static inline void board_mkp_init(void)
142{
143}
144#endif
145
146static struct mtd_partition h4_partitions[] = {
147 /* bootloader (U-Boot, etc) in first sector */
148 {
149 .name = "bootloader",
150 .offset = 0,
151 .size = SZ_128K,
152 .mask_flags = MTD_WRITEABLE, /* force read-only */
153 },
154 /* bootloader params in the next sector */
155 {
156 .name = "params",
157 .offset = MTDPART_OFS_APPEND,
158 .size = SZ_128K,
159 .mask_flags = 0,
160 },
161 /* kernel */
162 {
163 .name = "kernel",
164 .offset = MTDPART_OFS_APPEND,
165 .size = SZ_2M,
166 .mask_flags = 0
167 },
168 /* file system */
169 {
170 .name = "filesystem",
171 .offset = MTDPART_OFS_APPEND,
172 .size = MTDPART_SIZ_FULL,
173 .mask_flags = 0
174 }
175};
176
177static struct physmap_flash_data h4_flash_data = {
178 .width = 2,
179 .parts = h4_partitions,
180 .nr_parts = ARRAY_SIZE(h4_partitions),
181};
182
183static struct resource h4_flash_resource = {
184 .flags = IORESOURCE_MEM,
185};
186
187static struct platform_device h4_flash_device = {
188 .name = "physmap-flash",
189 .id = 0,
190 .dev = {
191 .platform_data = &h4_flash_data,
192 },
193 .num_resources = 1,
194 .resource = &h4_flash_resource,
195};
196
197static const struct display_timing cm_t35_lcd_videomode = {
198 .pixelclock = { 0, 6250000, 0 },
199
200 .hactive = { 0, 240, 0 },
201 .hfront_porch = { 0, 15, 0 },
202 .hback_porch = { 0, 60, 0 },
203 .hsync_len = { 0, 15, 0 },
204
205 .vactive = { 0, 320, 0 },
206 .vfront_porch = { 0, 1, 0 },
207 .vback_porch = { 0, 1, 0 },
208 .vsync_len = { 0, 1, 0 },
209
210 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
211 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
212};
213
214static struct panel_dpi_platform_data cm_t35_lcd_pdata = {
215 .name = "lcd",
216 .source = "dpi.0",
217
218 .data_lines = 16,
219
220 .display_timing = &cm_t35_lcd_videomode,
221
222 .enable_gpio = -1,
223 .backlight_gpio = -1,
224};
225
226static struct platform_device cm_t35_lcd_device = {
227 .name = "panel-dpi",
228 .id = 0,
229 .dev.platform_data = &cm_t35_lcd_pdata,
230};
231
232static struct platform_device *h4_devices[] __initdata = {
233 &h4_flash_device,
234 &cm_t35_lcd_device,
235};
236
237static struct omap_dss_board_info h4_dss_data = {
238 .default_display_name = "lcd",
239};
240
241/* 2420 Sysboot setup (2430 is different) */
242static u32 get_sysboot_value(void)
243{
244 return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
245 (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
246 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
247 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
248}
249
250/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
251 *
252 * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
253 * correctly. The macro needs to look at production_id not just hawkeye.
254 */
255static u32 is_gpmc_muxed(void)
256{
257 u32 mux;
258 mux = get_sysboot_value();
259 if ((mux & 0xF) == 0xd)
260 return 1; /* NAND config (could be either) */
261 if (mux & 0x2) /* if mux'ed */
262 return 1;
263 else
264 return 0;
265}
266
267#if IS_ENABLED(CONFIG_SMC91X)
268
269static struct omap_smc91x_platform_data board_smc91x_data = {
270 .cs = 1,
271 .gpio_irq = 92,
272 .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_LOWLEVEL,
273};
274
275static void __init board_smc91x_init(void)
276{
277 if (is_gpmc_muxed())
278 board_smc91x_data.flags |= GPMC_MUX_ADD_DATA;
279
280 omap_mux_init_gpio(board_smc91x_data.gpio_irq, OMAP_PIN_INPUT);
281 gpmc_smc91x_init(&board_smc91x_data);
282}
283
284#else
285
286static inline void board_smc91x_init(void)
287{
288}
289
290#endif
291
292static void __init h4_init_flash(void)
293{
294 unsigned long base;
295
296 if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
297 printk("Can't request GPMC CS for flash\n");
298 return;
299 }
300 h4_flash_resource.start = base;
301 h4_flash_resource.end = base + SZ_64M - 1;
302}
303
304static struct at24_platform_data m24c01 = {
305 .byte_len = SZ_1K / 8,
306 .page_size = 16,
307};
308
309static struct i2c_board_info __initdata h4_i2c_board_info[] = {
310 {
311 I2C_BOARD_INFO("isp1301_omap", 0x2d),
312 },
313 { /* EEPROM on mainboard */
314 I2C_BOARD_INFO("24c01", 0x52),
315 .platform_data = &m24c01,
316 },
317 { /* EEPROM on cpu card */
318 I2C_BOARD_INFO("24c01", 0x57),
319 .platform_data = &m24c01,
320 },
321};
322
323#ifdef CONFIG_OMAP_MUX
324static struct omap_board_mux board_mux[] __initdata = {
325 { .reg_offset = OMAP_MUX_TERMINATOR },
326};
327#endif
328
329static void __init omap_h4_init(void)
330{
331 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
332
333 /*
334 * Make sure the serial ports are muxed on at this point.
335 * You have to mux them off in device drivers later on
336 * if not needed.
337 */
338
339 board_mkp_init();
340 h4_i2c_board_info[0].irq = gpio_to_irq(125);
341 i2c_register_board_info(1, h4_i2c_board_info,
342 ARRAY_SIZE(h4_i2c_board_info));
343
344 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
345 omap_serial_init();
346 omap_sdrc_init(NULL, NULL);
347 h4_init_flash();
348 board_smc91x_init();
349
350 omap_display_init(&h4_dss_data);
351}
352
353MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
354 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
355 .atag_offset = 0x100,
356 .reserve = omap_reserve,
357 .map_io = omap242x_map_io,
358 .init_early = omap2420_init_early,
359 .init_irq = omap2_init_irq,
360 .handle_irq = omap2_intc_handle_irq,
361 .init_machine = omap_h4_init,
362 .init_late = omap2420_init_late,
363 .init_time = omap2_sync32k_timer_init,
364 .restart = omap2xxx_restart,
365MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 827d15009a86..aead77a4bc6d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -21,7 +21,6 @@
21#include <linux/i2c.h> 21#include <linux/i2c.h>
22#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
23#include <linux/usb/musb.h> 23#include <linux/usb/musb.h>
24#include <linux/platform_data/i2c-cbus-gpio.h>
25#include <linux/platform_data/spi-omap2-mcspi.h> 24#include <linux/platform_data/spi-omap2-mcspi.h>
26#include <linux/platform_data/mtd-onenand-omap2.h> 25#include <linux/platform_data/mtd-onenand-omap2.h>
27#include <linux/mfd/menelaus.h> 26#include <linux/mfd/menelaus.h>
@@ -32,8 +31,7 @@
32 31
33#include "common.h" 32#include "common.h"
34#include "mmc.h" 33#include "mmc.h"
35 34#include "soc.h"
36#include "mux.h"
37#include "gpmc-onenand.h" 35#include "gpmc-onenand.h"
38 36
39#define TUSB6010_ASYNC_CS 1 37#define TUSB6010_ASYNC_CS 1
@@ -42,44 +40,30 @@
42#define TUSB6010_GPIO_ENABLE 0 40#define TUSB6010_GPIO_ENABLE 0
43#define TUSB6010_DMACHAN 0x3f 41#define TUSB6010_DMACHAN 0x3f
44 42
45#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE) 43#define NOKIA_N810_WIMAX (1 << 2)
46static struct i2c_cbus_platform_data n8x0_cbus_data = { 44#define NOKIA_N810 (1 << 1)
47 .clk_gpio = 66, 45#define NOKIA_N800 (1 << 0)
48 .dat_gpio = 65,
49 .sel_gpio = 64,
50};
51 46
52static struct platform_device n8x0_cbus_device = { 47static u32 board_caps;
53 .name = "i2c-cbus-gpio",
54 .id = 3,
55 .dev = {
56 .platform_data = &n8x0_cbus_data,
57 },
58};
59 48
60static struct i2c_board_info n8x0_i2c_board_info_3[] __initdata = { 49#define board_is_n800() (board_caps & NOKIA_N800)
61 { 50#define board_is_n810() (board_caps & NOKIA_N810)
62 I2C_BOARD_INFO("retu-mfd", 0x01), 51#define board_is_n810_wimax() (board_caps & NOKIA_N810_WIMAX)
63 },
64};
65 52
66static void __init n8x0_cbus_init(void) 53static void board_check_revision(void)
67{ 54{
68 const int retu_irq_gpio = 108; 55 if (of_have_populated_dt()) {
56 if (of_machine_is_compatible("nokia,n800"))
57 board_caps = NOKIA_N800;
58 else if (of_machine_is_compatible("nokia,n810"))
59 board_caps = NOKIA_N810;
60 else if (of_machine_is_compatible("nokia,n810-wimax"))
61 board_caps = NOKIA_N810_WIMAX;
62 }
69 63
70 if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ")) 64 if (!board_caps)
71 return; 65 pr_err("Unknown board\n");
72 irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING);
73 n8x0_i2c_board_info_3[0].irq = gpio_to_irq(retu_irq_gpio);
74 i2c_register_board_info(3, n8x0_i2c_board_info_3,
75 ARRAY_SIZE(n8x0_i2c_board_info_3));
76 platform_device_register(&n8x0_cbus_device);
77}
78#else /* CONFIG_I2C_CBUS_GPIO */
79static void __init n8x0_cbus_init(void)
80{
81} 66}
82#endif /* CONFIG_I2C_CBUS_GPIO */
83 67
84#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) 68#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
85/* 69/*
@@ -178,49 +162,6 @@ static struct spi_board_info n800_spi_board_info[] __initdata = {
178 }, 162 },
179}; 163};
180 164
181#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
182 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
183
184static struct mtd_partition onenand_partitions[] = {
185 {
186 .name = "bootloader",
187 .offset = 0,
188 .size = 0x20000,
189 .mask_flags = MTD_WRITEABLE, /* Force read-only */
190 },
191 {
192 .name = "config",
193 .offset = MTDPART_OFS_APPEND,
194 .size = 0x60000,
195 },
196 {
197 .name = "kernel",
198 .offset = MTDPART_OFS_APPEND,
199 .size = 0x200000,
200 },
201 {
202 .name = "initfs",
203 .offset = MTDPART_OFS_APPEND,
204 .size = 0x400000,
205 },
206 {
207 .name = "rootfs",
208 .offset = MTDPART_OFS_APPEND,
209 .size = MTDPART_SIZ_FULL,
210 },
211};
212
213static struct omap_onenand_platform_data board_onenand_data[] = {
214 {
215 .cs = 0,
216 .gpio_irq = 26,
217 .parts = onenand_partitions,
218 .nr_parts = ARRAY_SIZE(onenand_partitions),
219 .flags = ONENAND_SYNC_READ,
220 }
221};
222#endif
223
224#if defined(CONFIG_MENELAUS) && \ 165#if defined(CONFIG_MENELAUS) && \
225 (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)) 166 (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE))
226 167
@@ -342,7 +283,7 @@ static void n810_set_power_emmc(struct device *dev,
342static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on, 283static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
343 int vdd) 284 int vdd)
344{ 285{
345 if (machine_is_nokia_n800() || slot == 0) 286 if (board_is_n800() || slot == 0)
346 return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd); 287 return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
347 288
348 n810_set_power_emmc(dev, power_on); 289 n810_set_power_emmc(dev, power_on);
@@ -388,7 +329,7 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
388{ 329{
389 int bit, *openp, index; 330 int bit, *openp, index;
390 331
391 if (machine_is_nokia_n800()) { 332 if (board_is_n800()) {
392 bit = 1 << 1; 333 bit = 1 << 1;
393 openp = &slot2_cover_open; 334 openp = &slot2_cover_open;
394 index = 1; 335 index = 1;
@@ -421,7 +362,7 @@ static int n8x0_mmc_late_init(struct device *dev)
421 if (r < 0) 362 if (r < 0)
422 return r; 363 return r;
423 364
424 if (machine_is_nokia_n800()) 365 if (board_is_n800())
425 vs2sel = 0; 366 vs2sel = 0;
426 else 367 else
427 vs2sel = 2; 368 vs2sel = 2;
@@ -444,7 +385,7 @@ static int n8x0_mmc_late_init(struct device *dev)
444 if (r < 0) 385 if (r < 0)
445 return r; 386 return r;
446 387
447 if (machine_is_nokia_n800()) { 388 if (board_is_n800()) {
448 bit = 1 << 1; 389 bit = 1 << 1;
449 openp = &slot2_cover_open; 390 openp = &slot2_cover_open;
450 } else { 391 } else {
@@ -471,7 +412,7 @@ static void n8x0_mmc_shutdown(struct device *dev)
471{ 412{
472 int vs2sel; 413 int vs2sel;
473 414
474 if (machine_is_nokia_n800()) 415 if (board_is_n800())
475 vs2sel = 0; 416 vs2sel = 0;
476 else 417 else
477 vs2sel = 2; 418 vs2sel = 2;
@@ -486,7 +427,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
486 427
487 gpio_free(N8X0_SLOT_SWITCH_GPIO); 428 gpio_free(N8X0_SLOT_SWITCH_GPIO);
488 429
489 if (machine_is_nokia_n810()) { 430 if (board_is_n810()) {
490 gpio_free(N810_EMMC_VSD_GPIO); 431 gpio_free(N810_EMMC_VSD_GPIO);
491 gpio_free(N810_EMMC_VIO_GPIO); 432 gpio_free(N810_EMMC_VIO_GPIO);
492 } 433 }
@@ -497,7 +438,7 @@ static void n8x0_mmc_cleanup(struct device *dev)
497 * MMC controller2 is not in use. 438 * MMC controller2 is not in use.
498 */ 439 */
499static struct omap_mmc_platform_data mmc1_data = { 440static struct omap_mmc_platform_data mmc1_data = {
500 .nr_slots = 2, 441 .nr_slots = 0,
501 .switch_slot = n8x0_mmc_switch_slot, 442 .switch_slot = n8x0_mmc_switch_slot,
502 .init = n8x0_mmc_late_init, 443 .init = n8x0_mmc_late_init,
503 .cleanup = n8x0_mmc_cleanup, 444 .cleanup = n8x0_mmc_cleanup,
@@ -537,7 +478,7 @@ static void __init n8x0_mmc_init(void)
537{ 478{
538 int err; 479 int err;
539 480
540 if (machine_is_nokia_n810()) { 481 if (board_is_n810()) {
541 mmc1_data.slots[0].name = "external"; 482 mmc1_data.slots[0].name = "external";
542 483
543 /* 484 /*
@@ -555,7 +496,7 @@ static void __init n8x0_mmc_init(void)
555 if (err) 496 if (err)
556 return; 497 return;
557 498
558 if (machine_is_nokia_n810()) { 499 if (board_is_n810()) {
559 err = gpio_request_array(n810_emmc_gpios, 500 err = gpio_request_array(n810_emmc_gpios,
560 ARRAY_SIZE(n810_emmc_gpios)); 501 ARRAY_SIZE(n810_emmc_gpios));
561 if (err) { 502 if (err) {
@@ -564,11 +505,11 @@ static void __init n8x0_mmc_init(void)
564 } 505 }
565 } 506 }
566 507
508 mmc1_data.nr_slots = 2;
567 mmc_data[0] = &mmc1_data; 509 mmc_data[0] = &mmc1_data;
568 omap242x_init_mmc(mmc_data);
569} 510}
570#else 511#else
571 512static struct omap_mmc_platform_data mmc1_data;
572void __init n8x0_mmc_init(void) 513void __init n8x0_mmc_init(void)
573{ 514{
574} 515}
@@ -650,109 +591,32 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
650 }, 591 },
651}; 592};
652 593
653#ifdef CONFIG_OMAP_MUX 594static int __init n8x0_late_initcall(void)
654static struct omap_board_mux board_mux[] __initdata = {
655 /* I2S codec port pins for McBSP block */
656 OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
657 OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
658 OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
659 OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
660 { .reg_offset = OMAP_MUX_TERMINATOR },
661};
662
663static struct omap_device_pad serial2_pads[] __initdata = {
664 {
665 .name = "uart3_rx_irrx.uart3_rx_irrx",
666 .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
667 .enable = OMAP_MUX_MODE0,
668 .idle = OMAP_MUX_MODE3 /* Mux as GPIO for idle */
669 },
670};
671
672static inline void board_serial_init(void)
673{ 595{
674 struct omap_board_data bdata; 596 if (!board_caps)
675 597 return -ENODEV;
676 bdata.flags = 0;
677 bdata.pads = NULL;
678 bdata.pads_cnt = 0;
679
680 bdata.id = 0;
681 omap_serial_init_port(&bdata, NULL);
682
683 bdata.id = 1;
684 omap_serial_init_port(&bdata, NULL);
685
686 bdata.id = 2;
687 bdata.pads = serial2_pads;
688 bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
689 omap_serial_init_port(&bdata, NULL);
690}
691 598
692#else 599 n8x0_mmc_init();
600 n8x0_usb_init();
693 601
694static inline void board_serial_init(void) 602 return 0;
695{
696 omap_serial_init();
697} 603}
604omap_late_initcall(n8x0_late_initcall);
698 605
699#endif 606/*
700 607 * Legacy init pdata init for n8x0. Note that we want to follow the
701static void __init n8x0_init_machine(void) 608 * I2C bus numbering starting at 0 for device tree like other omaps.
609 */
610void * __init n8x0_legacy_init(void)
702{ 611{
703 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); 612 board_check_revision();
704 /* FIXME: add n810 spi devices */
705 spi_register_board_info(n800_spi_board_info, 613 spi_register_board_info(n800_spi_board_info,
706 ARRAY_SIZE(n800_spi_board_info)); 614 ARRAY_SIZE(n800_spi_board_info));
707 omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, 615 i2c_register_board_info(0, n8x0_i2c_board_info_1,
708 ARRAY_SIZE(n8x0_i2c_board_info_1)); 616 ARRAY_SIZE(n8x0_i2c_board_info_1));
709 omap_register_i2c_bus(2, 400, NULL, 0); 617 if (board_is_n810())
710 if (machine_is_nokia_n810()) 618 i2c_register_board_info(1, n810_i2c_board_info_2,
711 i2c_register_board_info(2, n810_i2c_board_info_2,
712 ARRAY_SIZE(n810_i2c_board_info_2)); 619 ARRAY_SIZE(n810_i2c_board_info_2));
713 board_serial_init();
714 omap_sdrc_init(NULL, NULL);
715 gpmc_onenand_init(board_onenand_data);
716 n8x0_mmc_init();
717 n8x0_usb_init();
718 n8x0_cbus_init();
719}
720 620
721MACHINE_START(NOKIA_N800, "Nokia N800") 621 return &mmc1_data;
722 .atag_offset = 0x100, 622}
723 .reserve = omap_reserve,
724 .map_io = omap242x_map_io,
725 .init_early = omap2420_init_early,
726 .init_irq = omap2_init_irq,
727 .handle_irq = omap2_intc_handle_irq,
728 .init_machine = n8x0_init_machine,
729 .init_late = omap2420_init_late,
730 .init_time = omap2_sync32k_timer_init,
731 .restart = omap2xxx_restart,
732MACHINE_END
733
734MACHINE_START(NOKIA_N810, "Nokia N810")
735 .atag_offset = 0x100,
736 .reserve = omap_reserve,
737 .map_io = omap242x_map_io,
738 .init_early = omap2420_init_early,
739 .init_irq = omap2_init_irq,
740 .handle_irq = omap2_intc_handle_irq,
741 .init_machine = n8x0_init_machine,
742 .init_late = omap2420_init_late,
743 .init_time = omap2_sync32k_timer_init,
744 .restart = omap2xxx_restart,
745MACHINE_END
746
747MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
748 .atag_offset = 0x100,
749 .reserve = omap_reserve,
750 .map_io = omap242x_map_io,
751 .init_early = omap2420_init_early,
752 .init_irq = omap2_init_irq,
753 .handle_irq = omap2_intc_handle_irq,
754 .init_machine = n8x0_init_machine,
755 .init_late = omap2420_init_late,
756 .init_time = omap2_sync32k_timer_init,
757 .restart = omap2xxx_restart,
758MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index f093af17f5e6..8760bbe3baab 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -760,7 +760,14 @@ static struct regulator_init_data rx51_vintdig = {
760 }, 760 },
761}; 761};
762 762
763static const char * const si4713_supply_names[] = {
764 "vio",
765 "vdd",
766};
767
763static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = { 768static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
769 .supplies = ARRAY_SIZE(si4713_supply_names),
770 .supply_names = si4713_supply_names,
764 .gpio_reset = RX51_FMTX_RESET_GPIO, 771 .gpio_reset = RX51_FMTX_RESET_GPIO,
765}; 772};
766 773
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30ee812f..000000000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
1/*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/clk-private.h>
20#include <linux/clkdev.h>
21#include <linux/io.h>
22
23#include "am33xx.h"
24#include "soc.h"
25#include "iomap.h"
26#include "clock.h"
27#include "control.h"
28#include "cm.h"
29#include "cm33xx.h"
30#include "cm-regbits-33xx.h"
31#include "prm.h"
32
33/* Modulemode control */
34#define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
35#define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
36
37/*LIST_HEAD(clocks);*/
38
39/* Root clocks */
40
41/* RTC 32k */
42DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
43
44/* On-Chip 32KHz RC OSC */
45DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
46
47/* Crystal input clks */
48DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
49
50DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
51
52DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
53
54DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
55
56/* Oscillator clock */
57/* 19.2, 24, 25 or 26 MHz */
58static const char *sys_clkin_ck_parents[] = {
59 "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
60 "virt_26000000_ck",
61};
62
63/*
64 * sys_clk in: input to the dpll and also used as funtional clock for,
65 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
66 *
67 */
68DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
69 AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
70 AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
71 AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
72 0, NULL);
73
74/* External clock - 12 MHz */
75DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
76
77/* Module clocks and DPLL outputs */
78
79/* DPLL_CORE */
80static struct dpll_data dpll_core_dd = {
81 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
82 .clk_bypass = &sys_clkin_ck,
83 .clk_ref = &sys_clkin_ck,
84 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
85 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
86 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
87 .mult_mask = AM33XX_DPLL_MULT_MASK,
88 .div1_mask = AM33XX_DPLL_DIV_MASK,
89 .enable_mask = AM33XX_DPLL_EN_MASK,
90 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
91 .max_multiplier = 2047,
92 .max_divider = 128,
93 .min_divider = 1,
94};
95
96/* CLKDCOLDO output */
97static const char *dpll_core_ck_parents[] = {
98 "sys_clkin_ck",
99};
100
101static struct clk dpll_core_ck;
102
103static const struct clk_ops dpll_core_ck_ops = {
104 .recalc_rate = &omap3_dpll_recalc,
105 .get_parent = &omap2_init_dpll_parent,
106};
107
108static struct clk_hw_omap dpll_core_ck_hw = {
109 .hw = {
110 .clk = &dpll_core_ck,
111 },
112 .dpll_data = &dpll_core_dd,
113 .ops = &clkhwops_omap3_dpll,
114};
115
116DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
117
118static const char *dpll_core_x2_ck_parents[] = {
119 "dpll_core_ck",
120};
121
122static struct clk dpll_core_x2_ck;
123
124static const struct clk_ops dpll_x2_ck_ops = {
125 .recalc_rate = &omap3_clkoutx2_recalc,
126};
127
128static struct clk_hw_omap dpll_core_x2_ck_hw = {
129 .hw = {
130 .clk = &dpll_core_x2_ck,
131 },
132 .flags = CLOCK_CLKOUTX2,
133};
134
135DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
136
137DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
138 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
139 AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
140 AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
141 NULL);
142
143DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
144 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
145 AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
146 AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
147 CLK_DIVIDER_ONE_BASED, NULL);
148
149DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
150 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
151 AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
152 AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
153 CLK_DIVIDER_ONE_BASED, NULL);
154
155
156/* DPLL_MPU */
157static struct dpll_data dpll_mpu_dd = {
158 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
159 .clk_bypass = &sys_clkin_ck,
160 .clk_ref = &sys_clkin_ck,
161 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
162 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
163 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
164 .mult_mask = AM33XX_DPLL_MULT_MASK,
165 .div1_mask = AM33XX_DPLL_DIV_MASK,
166 .enable_mask = AM33XX_DPLL_EN_MASK,
167 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
168 .max_multiplier = 2047,
169 .max_divider = 128,
170 .min_divider = 1,
171};
172
173/* CLKOUT: fdpll/M2 */
174static struct clk dpll_mpu_ck;
175
176static const struct clk_ops dpll_mpu_ck_ops = {
177 .enable = &omap3_noncore_dpll_enable,
178 .disable = &omap3_noncore_dpll_disable,
179 .recalc_rate = &omap3_dpll_recalc,
180 .round_rate = &omap2_dpll_round_rate,
181 .set_rate = &omap3_noncore_dpll_set_rate,
182 .get_parent = &omap2_init_dpll_parent,
183};
184
185static struct clk_hw_omap dpll_mpu_ck_hw = {
186 .hw = {
187 .clk = &dpll_mpu_ck,
188 },
189 .dpll_data = &dpll_mpu_dd,
190 .ops = &clkhwops_omap3_dpll,
191};
192
193DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
194
195/*
196 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
197 * and ALT_CLK1/2)
198 */
199DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
200 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
201 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
202
203/* DPLL_DDR */
204static struct dpll_data dpll_ddr_dd = {
205 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
206 .clk_bypass = &sys_clkin_ck,
207 .clk_ref = &sys_clkin_ck,
208 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
209 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
210 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
211 .mult_mask = AM33XX_DPLL_MULT_MASK,
212 .div1_mask = AM33XX_DPLL_DIV_MASK,
213 .enable_mask = AM33XX_DPLL_EN_MASK,
214 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
215 .max_multiplier = 2047,
216 .max_divider = 128,
217 .min_divider = 1,
218};
219
220/* CLKOUT: fdpll/M2 */
221static struct clk dpll_ddr_ck;
222
223static const struct clk_ops dpll_ddr_ck_ops = {
224 .recalc_rate = &omap3_dpll_recalc,
225 .get_parent = &omap2_init_dpll_parent,
226 .round_rate = &omap2_dpll_round_rate,
227 .set_rate = &omap3_noncore_dpll_set_rate,
228};
229
230static struct clk_hw_omap dpll_ddr_ck_hw = {
231 .hw = {
232 .clk = &dpll_ddr_ck,
233 },
234 .dpll_data = &dpll_ddr_dd,
235 .ops = &clkhwops_omap3_dpll,
236};
237
238DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
239
240/*
241 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
242 * and ALT_CLK1/2)
243 */
244DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
245 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
246 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
247 CLK_DIVIDER_ONE_BASED, NULL);
248
249/* emif_fck functional clock */
250DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
251 0x0, 1, 2);
252
253/* DPLL_DISP */
254static struct dpll_data dpll_disp_dd = {
255 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
256 .clk_bypass = &sys_clkin_ck,
257 .clk_ref = &sys_clkin_ck,
258 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
259 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
260 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
261 .mult_mask = AM33XX_DPLL_MULT_MASK,
262 .div1_mask = AM33XX_DPLL_DIV_MASK,
263 .enable_mask = AM33XX_DPLL_EN_MASK,
264 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
265 .max_multiplier = 2047,
266 .max_divider = 128,
267 .min_divider = 1,
268};
269
270/* CLKOUT: fdpll/M2 */
271static struct clk dpll_disp_ck;
272
273static struct clk_hw_omap dpll_disp_ck_hw = {
274 .hw = {
275 .clk = &dpll_disp_ck,
276 },
277 .dpll_data = &dpll_disp_dd,
278 .ops = &clkhwops_omap3_dpll,
279};
280
281DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
282
283/*
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
285 * and ALT_CLK1/2)
286 */
287DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
288 CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
289 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
290 CLK_DIVIDER_ONE_BASED, NULL);
291
292/* DPLL_PER */
293static struct dpll_data dpll_per_dd = {
294 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
295 .clk_bypass = &sys_clkin_ck,
296 .clk_ref = &sys_clkin_ck,
297 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
298 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
299 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
300 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
301 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
302 .enable_mask = AM33XX_DPLL_EN_MASK,
303 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
304 .max_multiplier = 2047,
305 .max_divider = 128,
306 .min_divider = 1,
307 .flags = DPLL_J_TYPE,
308};
309
310/* CLKDCOLDO */
311static struct clk dpll_per_ck;
312
313static struct clk_hw_omap dpll_per_ck_hw = {
314 .hw = {
315 .clk = &dpll_per_ck,
316 },
317 .dpll_data = &dpll_per_dd,
318 .ops = &clkhwops_omap3_dpll,
319};
320
321DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
322
323/* CLKOUT: fdpll/M2 */
324DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
325 AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
326 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
327 NULL);
328
329DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
330 &dpll_per_m2_ck, 0x0, 1, 4);
331
332DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
333 &dpll_per_m2_ck, 0x0, 1, 4);
334
335DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
336 &dpll_core_m4_ck, 0x0, 1, 2);
337
338DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
339 1, 2);
340
341DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
342 8);
343
344/*
345 * Below clock nodes describes clockdomains derived out
346 * of core clock.
347 */
348static const struct clk_ops clk_ops_null = {
349};
350
351static const char *l3_gclk_parents[] = {
352 "dpll_core_m4_ck"
353};
354
355static struct clk l3_gclk;
356DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
357DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
358
359static struct clk l4hs_gclk;
360DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
361DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
362
363static const char *l3s_gclk_parents[] = {
364 "dpll_core_m4_div2_ck"
365};
366
367static struct clk l3s_gclk;
368DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
369DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
370
371static struct clk l4fw_gclk;
372DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
373DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
374
375static struct clk l4ls_gclk;
376DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
377DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
378
379static struct clk sysclk_div_ck;
380DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
381DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
382
383/*
384 * In order to match the clock domain with hwmod clockdomain entry,
385 * separate clock nodes is required for the modules which are
386 * directly getting their funtioncal clock from sys_clkin.
387 */
388static struct clk adc_tsc_fck;
389DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
390DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
391
392static struct clk dcan0_fck;
393DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
394DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
395
396static struct clk dcan1_fck;
397DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
398DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
399
400static struct clk mcasp0_fck;
401DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
402DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
403
404static struct clk mcasp1_fck;
405DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
406DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
407
408static struct clk smartreflex0_fck;
409DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
410DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
411
412static struct clk smartreflex1_fck;
413DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
414DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
415
416static struct clk sha0_fck;
417DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
418DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
419
420static struct clk aes0_fck;
421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
423
424static struct clk rng_fck;
425DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
426DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
427
428/*
429 * Modules clock nodes
430 *
431 * The following clock leaf nodes are added for the moment because:
432 *
433 * - hwmod data is not present for these modules, either hwmod
434 * control is not required or its not populated.
435 * - Driver code is not yet migrated to use hwmod/runtime pm
436 * - Modules outside kernel access (to disable them by default)
437 *
438 * - mmu (gfx domain)
439 * - cefuse
440 * - usbotg_fck (its additional clock and not really a modulemode)
441 * - ieee5000
442 */
443
444DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
445 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
446 0x0, NULL);
447
448DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
449 AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
450 0x0, NULL);
451
452/*
453 * clkdiv32 is generated from fixed division of 732.4219
454 */
455DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
456
457static struct clk clkdiv32k_ick;
458
459static const char *clkdiv32k_ick_parent_names[] = {
460 "clkdiv32k_ck",
461};
462
463static const struct clk_ops clkdiv32k_ick_ops = {
464 .enable = &omap2_dflt_clk_enable,
465 .disable = &omap2_dflt_clk_disable,
466 .is_enabled = &omap2_dflt_clk_is_enabled,
467 .init = &omap2_init_clk_clkdm,
468};
469
470static struct clk_hw_omap clkdiv32k_ick_hw = {
471 .hw = {
472 .clk = &clkdiv32k_ick,
473 },
474 .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
475 .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
476 .clkdm_name = "clk_24mhz_clkdm",
477};
478
479DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
480
481/* "usbotg_fck" is an additional clock and not really a modulemode */
482DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
483 AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
484 0x0, NULL);
485
486DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
487 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
488 AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
489
490/* Timers */
491static const struct clksel timer1_clkmux_sel[] = {
492 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
493 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
494 { .parent = &tclkin_ck, .rates = div_1_2_rates },
495 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
496 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
497 { .parent = NULL },
498};
499
500static const char *timer1_ck_parents[] = {
501 "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
502 "clk_32768_ck",
503};
504
505static struct clk timer1_fck;
506
507static const struct clk_ops timer1_fck_ops = {
508 .recalc_rate = &omap2_clksel_recalc,
509 .get_parent = &omap2_clksel_find_parent_index,
510 .set_parent = &omap2_clksel_set_parent,
511 .init = &omap2_init_clk_clkdm,
512};
513
514static struct clk_hw_omap timer1_fck_hw = {
515 .hw = {
516 .clk = &timer1_fck,
517 },
518 .clkdm_name = "l4ls_clkdm",
519 .clksel = timer1_clkmux_sel,
520 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
521 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
522};
523
524DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
525
526static const struct clksel timer2_to_7_clk_sel[] = {
527 { .parent = &tclkin_ck, .rates = div_1_0_rates },
528 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
529 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
530 { .parent = NULL },
531};
532
533static const char *timer2_to_7_ck_parents[] = {
534 "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
535};
536
537static struct clk timer2_fck;
538
539static struct clk_hw_omap timer2_fck_hw = {
540 .hw = {
541 .clk = &timer2_fck,
542 },
543 .clkdm_name = "l4ls_clkdm",
544 .clksel = timer2_to_7_clk_sel,
545 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
546 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
547};
548
549DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
550
551static struct clk timer3_fck;
552
553static struct clk_hw_omap timer3_fck_hw = {
554 .hw = {
555 .clk = &timer3_fck,
556 },
557 .clkdm_name = "l4ls_clkdm",
558 .clksel = timer2_to_7_clk_sel,
559 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
560 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
561};
562
563DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
564
565static struct clk timer4_fck;
566
567static struct clk_hw_omap timer4_fck_hw = {
568 .hw = {
569 .clk = &timer4_fck,
570 },
571 .clkdm_name = "l4ls_clkdm",
572 .clksel = timer2_to_7_clk_sel,
573 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
574 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
575};
576
577DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
578
579static struct clk timer5_fck;
580
581static struct clk_hw_omap timer5_fck_hw = {
582 .hw = {
583 .clk = &timer5_fck,
584 },
585 .clkdm_name = "l4ls_clkdm",
586 .clksel = timer2_to_7_clk_sel,
587 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
588 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
589};
590
591DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
592
593static struct clk timer6_fck;
594
595static struct clk_hw_omap timer6_fck_hw = {
596 .hw = {
597 .clk = &timer6_fck,
598 },
599 .clkdm_name = "l4ls_clkdm",
600 .clksel = timer2_to_7_clk_sel,
601 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
602 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
603};
604
605DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
606
607static struct clk timer7_fck;
608
609static struct clk_hw_omap timer7_fck_hw = {
610 .hw = {
611 .clk = &timer7_fck,
612 },
613 .clkdm_name = "l4ls_clkdm",
614 .clksel = timer2_to_7_clk_sel,
615 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
616 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
617};
618
619DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
620
621DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
622 "dpll_core_m5_ck",
623 &dpll_core_m5_ck,
624 0x0,
625 1, 2);
626
627static const struct clk_ops cpsw_fck_ops = {
628 .recalc_rate = &omap2_clksel_recalc,
629 .get_parent = &omap2_clksel_find_parent_index,
630 .set_parent = &omap2_clksel_set_parent,
631};
632
633static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
634 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
635 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
636 { .parent = NULL },
637};
638
639static const char *cpsw_cpts_rft_ck_parents[] = {
640 "dpll_core_m5_ck", "dpll_core_m4_ck",
641};
642
643static struct clk cpsw_cpts_rft_clk;
644
645static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
646 .hw = {
647 .clk = &cpsw_cpts_rft_clk,
648 },
649 .clkdm_name = "cpsw_125mhz_clkdm",
650 .clksel = cpsw_cpts_rft_clkmux_sel,
651 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
652 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
653};
654
655DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
656
657
658/* gpio */
659static const char *gpio0_ck_parents[] = {
660 "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
661};
662
663static const struct clksel gpio0_dbclk_mux_sel[] = {
664 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
665 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
666 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
667 { .parent = NULL },
668};
669
670static const struct clk_ops gpio_fck_ops = {
671 .recalc_rate = &omap2_clksel_recalc,
672 .get_parent = &omap2_clksel_find_parent_index,
673 .set_parent = &omap2_clksel_set_parent,
674 .init = &omap2_init_clk_clkdm,
675};
676
677static struct clk gpio0_dbclk_mux_ck;
678
679static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
680 .hw = {
681 .clk = &gpio0_dbclk_mux_ck,
682 },
683 .clkdm_name = "l4_wkup_clkdm",
684 .clksel = gpio0_dbclk_mux_sel,
685 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
686 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
687};
688
689DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
690
691DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
692 AM33XX_CM_WKUP_GPIO0_CLKCTRL,
693 AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
694
695DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
696 AM33XX_CM_PER_GPIO1_CLKCTRL,
697 AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
698
699DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
700 AM33XX_CM_PER_GPIO2_CLKCTRL,
701 AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
702
703DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
704 AM33XX_CM_PER_GPIO3_CLKCTRL,
705 AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
706
707
708static const char *pruss_ck_parents[] = {
709 "l3_gclk", "dpll_disp_m2_ck",
710};
711
712static const struct clksel pruss_ocp_clk_mux_sel[] = {
713 { .parent = &l3_gclk, .rates = div_1_0_rates },
714 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
715 { .parent = NULL },
716};
717
718static struct clk pruss_ocp_gclk;
719
720static struct clk_hw_omap pruss_ocp_gclk_hw = {
721 .hw = {
722 .clk = &pruss_ocp_gclk,
723 },
724 .clkdm_name = "pruss_ocp_clkdm",
725 .clksel = pruss_ocp_clk_mux_sel,
726 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
727 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
728};
729
730DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
731
732static const char *lcd_ck_parents[] = {
733 "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
734};
735
736static const struct clksel lcd_clk_mux_sel[] = {
737 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
738 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
739 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
740 { .parent = NULL },
741};
742
743static struct clk lcd_gclk;
744
745static struct clk_hw_omap lcd_gclk_hw = {
746 .hw = {
747 .clk = &lcd_gclk,
748 },
749 .clkdm_name = "lcdc_clkdm",
750 .clksel = lcd_clk_mux_sel,
751 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
752 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
753};
754
755DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
756 gpio_fck_ops, CLK_SET_RATE_PARENT);
757
758DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
759
760static const char *gfx_ck_parents[] = {
761 "dpll_core_m4_ck", "dpll_per_m2_ck",
762};
763
764static const struct clksel gfx_clksel_sel[] = {
765 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
766 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
767 { .parent = NULL },
768};
769
770static struct clk gfx_fclk_clksel_ck;
771
772static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
773 .hw = {
774 .clk = &gfx_fclk_clksel_ck,
775 },
776 .clksel = gfx_clksel_sel,
777 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
778 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
779};
780
781DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
782
783static const struct clk_div_table div_1_0_2_1_rates[] = {
784 { .div = 1, .val = 0, },
785 { .div = 2, .val = 1, },
786 { .div = 0 },
787};
788
789DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
790 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
791 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
792 0x0, div_1_0_2_1_rates, NULL);
793
794static const char *sysclkout_ck_parents[] = {
795 "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
796 "lcd_gclk",
797};
798
799static const struct clksel sysclkout_pre_sel[] = {
800 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
801 { .parent = &l3_gclk, .rates = div_1_1_rates },
802 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
803 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
804 { .parent = &lcd_gclk, .rates = div_1_4_rates },
805 { .parent = NULL },
806};
807
808static struct clk sysclkout_pre_ck;
809
810static struct clk_hw_omap sysclkout_pre_ck_hw = {
811 .hw = {
812 .clk = &sysclkout_pre_ck,
813 },
814 .clksel = sysclkout_pre_sel,
815 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
816 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
817};
818
819DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
820
821/* Divide by 8 clock rates with default clock is 1/1*/
822static const struct clk_div_table div8_rates[] = {
823 { .div = 1, .val = 0, },
824 { .div = 2, .val = 1, },
825 { .div = 3, .val = 2, },
826 { .div = 4, .val = 3, },
827 { .div = 5, .val = 4, },
828 { .div = 6, .val = 5, },
829 { .div = 7, .val = 6, },
830 { .div = 8, .val = 7, },
831 { .div = 0 },
832};
833
834DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
835 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
836 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
837
838DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
839 AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
840
841static const char *wdt_ck_parents[] = {
842 "clk_rc32k_ck", "clkdiv32k_ick",
843};
844
845static const struct clksel wdt_clkmux_sel[] = {
846 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
847 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
848 { .parent = NULL },
849};
850
851static struct clk wdt1_fck;
852
853static struct clk_hw_omap wdt1_fck_hw = {
854 .hw = {
855 .clk = &wdt1_fck,
856 },
857 .clkdm_name = "l4_wkup_clkdm",
858 .clksel = wdt_clkmux_sel,
859 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
860 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
861};
862
863DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
864
865static const char *pwmss_clk_parents[] = {
866 "dpll_per_m2_ck",
867};
868
869static const struct clk_ops ehrpwm_tbclk_ops = {
870 .enable = &omap2_dflt_clk_enable,
871 .disable = &omap2_dflt_clk_disable,
872};
873
874DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
875 NULL, NULL, 0,
876 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
877 AM33XX_PWMSS0_TBCLKEN_SHIFT,
878 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
879
880DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
881 NULL, NULL, 0,
882 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
883 AM33XX_PWMSS1_TBCLKEN_SHIFT,
884 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
885
886DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
887 NULL, NULL, 0,
888 AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
889 AM33XX_PWMSS2_TBCLKEN_SHIFT,
890 NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
891
892/*
893 * debugss optional clocks
894 */
895DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
896 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
897 AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
898
899DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
900 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
901 AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
902
903static const char *stm_pmd_clock_mux_ck_parents[] = {
904 "dbg_sysclk_ck", "dbg_clka_ck",
905};
906
907DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
908 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
909 AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
910
911DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
912 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
913 AM33XX_TRC_PMD_CLKSEL_SHIFT,
914 AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
915
916DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
917 &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
918 AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
919 AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
920 NULL);
921
922DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
923 &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
924 AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
925 AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
926 NULL);
927
928/*
929 * clkdev
930 */
931static struct omap_clk am33xx_clks[] = {
932 CLK(NULL, "clk_32768_ck", &clk_32768_ck),
933 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
934 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
935 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
936 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
937 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
938 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
939 CLK(NULL, "tclkin_ck", &tclkin_ck),
940 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
941 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
942 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
943 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
944 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
945 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
946 CLK("cpu0", NULL, &dpll_mpu_ck),
947 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
948 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
949 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
950 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
951 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
952 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
953 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
954 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
955 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
956 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
957 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
958 CLK(NULL, "cefuse_fck", &cefuse_fck),
959 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
960 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
961 CLK(NULL, "dcan0_fck", &dcan0_fck),
962 CLK("481cc000.d_can", NULL, &dcan0_fck),
963 CLK(NULL, "dcan1_fck", &dcan1_fck),
964 CLK("481d0000.d_can", NULL, &dcan1_fck),
965 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
966 CLK(NULL, "mcasp0_fck", &mcasp0_fck),
967 CLK(NULL, "mcasp1_fck", &mcasp1_fck),
968 CLK(NULL, "mmu_fck", &mmu_fck),
969 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
970 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
971 CLK(NULL, "sha0_fck", &sha0_fck),
972 CLK(NULL, "aes0_fck", &aes0_fck),
973 CLK(NULL, "rng_fck", &rng_fck),
974 CLK(NULL, "timer1_fck", &timer1_fck),
975 CLK(NULL, "timer2_fck", &timer2_fck),
976 CLK(NULL, "timer3_fck", &timer3_fck),
977 CLK(NULL, "timer4_fck", &timer4_fck),
978 CLK(NULL, "timer5_fck", &timer5_fck),
979 CLK(NULL, "timer6_fck", &timer6_fck),
980 CLK(NULL, "timer7_fck", &timer7_fck),
981 CLK(NULL, "usbotg_fck", &usbotg_fck),
982 CLK(NULL, "ieee5000_fck", &ieee5000_fck),
983 CLK(NULL, "wdt1_fck", &wdt1_fck),
984 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
985 CLK(NULL, "l3_gclk", &l3_gclk),
986 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
987 CLK(NULL, "l4hs_gclk", &l4hs_gclk),
988 CLK(NULL, "l3s_gclk", &l3s_gclk),
989 CLK(NULL, "l4fw_gclk", &l4fw_gclk),
990 CLK(NULL, "l4ls_gclk", &l4ls_gclk),
991 CLK(NULL, "clk_24mhz", &clk_24mhz),
992 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
993 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
994 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
995 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
996 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
997 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
998 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
999 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
1000 CLK(NULL, "lcd_gclk", &lcd_gclk),
1001 CLK(NULL, "mmc_clk", &mmc_clk),
1002 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
1003 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
1004 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
1005 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
1006 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
1007 CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
1008 CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck),
1009 CLK(NULL, "dbg_clka_ck", &dbg_clka_ck),
1010 CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
1011 CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
1012 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
1013 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
1014 CLK(NULL, "clkout2_ck", &clkout2_ck),
1015 CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk),
1016 CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk),
1017 CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk),
1018};
1019
1020
1021static const char *enable_init_clks[] = {
1022 "dpll_ddr_m2_ck",
1023 "dpll_mpu_m2_ck",
1024 "l3_gclk",
1025 "l4hs_gclk",
1026 "l4fw_gclk",
1027 "l4ls_gclk",
1028 "clkout2_ck", /* Required for external peripherals like, Audio codecs */
1029};
1030
1031int __init am33xx_clk_init(void)
1032{
1033 if (soc_is_am33xx())
1034 cpu_mask = RATE_IN_AM33XX;
1035
1036 omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
1037
1038 omap2_clk_disable_autoidle_all();
1039
1040 omap2_clk_enable_init_clocks(enable_init_clks,
1041 ARRAY_SIZE(enable_init_clks));
1042
1043 /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
1044 * physically present, in such a case HWMOD enabling of
1045 * clock would be failure with default parent. And timer
1046 * probe thinks clock is already enabled, this leads to
1047 * crash upon accessing timer 3 & 6 registers in probe.
1048 * Fix by setting parent of both these timers to master
1049 * oscillator clock.
1050 */
1051
1052 clk_set_parent(&timer3_fck, &sys_clkin_ck);
1053 clk_set_parent(&timer6_fck, &sys_clkin_ck);
1054 /*
1055 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
1056 * the design/spec, so as a result, for example, timer which supposed
1057 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
1058 * not expected by any use-case, so change WDT1 clock source to PRCM
1059 * 32KHz clock.
1060 */
1061 clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
1062
1063 return 0;
1064}
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 3b05aea56d1f..11ed9152e665 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -433,7 +433,9 @@ static const struct clk_ops dpll4_m5x2_ck_ops = {
433 .enable = &omap2_dflt_clk_enable, 433 .enable = &omap2_dflt_clk_enable,
434 .disable = &omap2_dflt_clk_disable, 434 .disable = &omap2_dflt_clk_disable,
435 .is_enabled = &omap2_dflt_clk_is_enabled, 435 .is_enabled = &omap2_dflt_clk_is_enabled,
436 .set_rate = &omap3_clkoutx2_set_rate,
436 .recalc_rate = &omap3_clkoutx2_recalc, 437 .recalc_rate = &omap3_clkoutx2_recalc,
438 .round_rate = &omap3_clkoutx2_round_rate,
437}; 439};
438 440
439static const struct clk_ops dpll4_m5x2_ck_3630_ops = { 441static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index ec0dc0b1755e..000000000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1735 +0,0 @@
1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Mike Turquette (mturquette@ti.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * XXX Some of the ES1 clocks have been removed/changed; once support
17 * is added for discriminating clocks by ES level, these should be added back
18 * in.
19 *
20 * XXX All of the remaining MODULEMODE clock nodes should be removed
21 * once the drivers are updated to use pm_runtime or to use the appropriate
22 * upstream clock node for rate/parent selection.
23 */
24
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/clk-private.h>
28#include <linux/clkdev.h>
29#include <linux/io.h>
30
31#include "soc.h"
32#include "iomap.h"
33#include "clock.h"
34#include "clock44xx.h"
35#include "cm1_44xx.h"
36#include "cm2_44xx.h"
37#include "cm-regbits-44xx.h"
38#include "prm44xx.h"
39#include "prm-regbits-44xx.h"
40#include "control.h"
41#include "scrm44xx.h"
42
43/* OMAP4 modulemode control */
44#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
45#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
46
47/*
48 * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
49 * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
50 * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
51 * half of this value.
52 */
53#define OMAP4_DPLL_ABE_DEFFREQ 98304000
54
55/*
56 * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
57 * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
58 * locked frequency for the USB DPLL is 960MHz.
59 */
60#define OMAP4_DPLL_USB_DEFFREQ 960000000
61
62/* Root clocks */
63
64DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
65
66DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
67
68DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
69 OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
70 0x0, NULL);
71
72DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
73
74DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
75
76DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
77
78DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
79 OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
80 0x0, NULL);
81
82DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
83
84DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
85
86DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
87
88DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
89
90DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
91
92DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
93
94DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
95
96DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
97
98static const char *sys_clkin_ck_parents[] = {
99 "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
100 "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
101 "virt_38400000_ck",
102};
103
104DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
105 OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
106 OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
107
108DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
109
110DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
111
112DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
113
114DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
115
116DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
117
118/* Module clocks and DPLL outputs */
119
120static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
121 "sys_clkin_ck", "sys_32k_ck",
122};
123
124DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
125 NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
126 OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
127
128DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
129 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
130 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
131
132/* DPLL_ABE */
133static struct dpll_data dpll_abe_dd = {
134 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
135 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
136 .clk_ref = &abe_dpll_refclk_mux_ck,
137 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
138 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
139 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
140 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
141 .mult_mask = OMAP4430_DPLL_MULT_MASK,
142 .div1_mask = OMAP4430_DPLL_DIV_MASK,
143 .enable_mask = OMAP4430_DPLL_EN_MASK,
144 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
145 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
146 .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK,
147 .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK,
148 .max_multiplier = 2047,
149 .max_divider = 128,
150 .min_divider = 1,
151};
152
153
154static const char *dpll_abe_ck_parents[] = {
155 "abe_dpll_refclk_mux_ck",
156};
157
158static struct clk dpll_abe_ck;
159
160static const struct clk_ops dpll_abe_ck_ops = {
161 .enable = &omap3_noncore_dpll_enable,
162 .disable = &omap3_noncore_dpll_disable,
163 .recalc_rate = &omap4_dpll_regm4xen_recalc,
164 .round_rate = &omap4_dpll_regm4xen_round_rate,
165 .set_rate = &omap3_noncore_dpll_set_rate,
166 .get_parent = &omap2_init_dpll_parent,
167};
168
169static struct clk_hw_omap dpll_abe_ck_hw = {
170 .hw = {
171 .clk = &dpll_abe_ck,
172 },
173 .dpll_data = &dpll_abe_dd,
174 .ops = &clkhwops_omap3_dpll,
175};
176
177DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
178
179static const char *dpll_abe_x2_ck_parents[] = {
180 "dpll_abe_ck",
181};
182
183static struct clk dpll_abe_x2_ck;
184
185static const struct clk_ops dpll_abe_x2_ck_ops = {
186 .recalc_rate = &omap3_clkoutx2_recalc,
187};
188
189static struct clk_hw_omap dpll_abe_x2_ck_hw = {
190 .hw = {
191 .clk = &dpll_abe_x2_ck,
192 },
193 .flags = CLOCK_CLKOUTX2,
194 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
195 .ops = &clkhwops_omap4_dpllmx,
196};
197
198DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
199
200static const struct clk_ops omap_hsdivider_ops = {
201 .set_rate = &omap2_clksel_set_rate,
202 .recalc_rate = &omap2_clksel_recalc,
203 .round_rate = &omap2_clksel_round_rate,
204};
205
206DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
207 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
208 OMAP4430_DPLL_CLKOUT_DIV_MASK);
209
210DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
211 0x0, 1, 8);
212
213DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
214 OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
215 OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
216
217DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
218 OMAP4430_CM1_ABE_AESS_CLKCTRL,
219 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
220 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
221 0x0, NULL);
222
223DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
224 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
225 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
226
227static const char *core_hsd_byp_clk_mux_ck_parents[] = {
228 "sys_clkin_ck", "dpll_abe_m3x2_ck",
229};
230
231DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
232 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
233 OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
234 0x0, NULL);
235
236/* DPLL_CORE */
237static struct dpll_data dpll_core_dd = {
238 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
239 .clk_bypass = &core_hsd_byp_clk_mux_ck,
240 .clk_ref = &sys_clkin_ck,
241 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
242 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
243 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
244 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
245 .mult_mask = OMAP4430_DPLL_MULT_MASK,
246 .div1_mask = OMAP4430_DPLL_DIV_MASK,
247 .enable_mask = OMAP4430_DPLL_EN_MASK,
248 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
249 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
250 .max_multiplier = 2047,
251 .max_divider = 128,
252 .min_divider = 1,
253};
254
255
256static const char *dpll_core_ck_parents[] = {
257 "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
258};
259
260static struct clk dpll_core_ck;
261
262static const struct clk_ops dpll_core_ck_ops = {
263 .recalc_rate = &omap3_dpll_recalc,
264 .get_parent = &omap2_init_dpll_parent,
265};
266
267static struct clk_hw_omap dpll_core_ck_hw = {
268 .hw = {
269 .clk = &dpll_core_ck,
270 },
271 .dpll_data = &dpll_core_dd,
272 .ops = &clkhwops_omap3_dpll,
273};
274
275DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
276
277static const char *dpll_core_x2_ck_parents[] = {
278 "dpll_core_ck",
279};
280
281static struct clk dpll_core_x2_ck;
282
283static struct clk_hw_omap dpll_core_x2_ck_hw = {
284 .hw = {
285 .clk = &dpll_core_x2_ck,
286 },
287};
288
289DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
290
291DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
292 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
293 OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
294
295DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
296 OMAP4430_CM_DIV_M2_DPLL_CORE,
297 OMAP4430_DPLL_CLKOUT_DIV_MASK);
298
299DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
300 2);
301
302DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
303 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
304 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
305
306DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
307 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
308 OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
309
310DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
311 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
312 OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
313
314DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
315 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
316 OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
317
318DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
319 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
320 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
321
322DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
323 0x0, 1, 2);
324
325DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
326 OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
327 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
328
329static const struct clk_ops dpll_hsd_ops = {
330 .enable = &omap2_dflt_clk_enable,
331 .disable = &omap2_dflt_clk_disable,
332 .is_enabled = &omap2_dflt_clk_is_enabled,
333 .recalc_rate = &omap2_clksel_recalc,
334 .get_parent = &omap2_clksel_find_parent_index,
335 .set_parent = &omap2_clksel_set_parent,
336 .init = &omap2_init_clk_clkdm,
337};
338
339static const struct clk_ops func_dmic_abe_gfclk_ops = {
340 .recalc_rate = &omap2_clksel_recalc,
341 .get_parent = &omap2_clksel_find_parent_index,
342 .set_parent = &omap2_clksel_set_parent,
343};
344
345static const char *dpll_core_m3x2_ck_parents[] = {
346 "dpll_core_x2_ck",
347};
348
349static const struct clksel dpll_core_m3x2_div[] = {
350 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
351 { .parent = NULL },
352};
353
354/* XXX Missing round_rate, set_rate in ops */
355DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
356 OMAP4430_CM_DIV_M3_DPLL_CORE,
357 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
358 OMAP4430_CM_DIV_M3_DPLL_CORE,
359 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
360 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
361
362DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
363 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
364 OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
365
366static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
367 "sys_clkin_ck", "div_iva_hs_clk",
368};
369
370DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
371 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
372 OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
373
374/* DPLL_IVA */
375static struct dpll_data dpll_iva_dd = {
376 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
377 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
378 .clk_ref = &sys_clkin_ck,
379 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
380 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
381 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
382 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
383 .mult_mask = OMAP4430_DPLL_MULT_MASK,
384 .div1_mask = OMAP4430_DPLL_DIV_MASK,
385 .enable_mask = OMAP4430_DPLL_EN_MASK,
386 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
387 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
388 .max_multiplier = 2047,
389 .max_divider = 128,
390 .min_divider = 1,
391};
392
393static const char *dpll_iva_ck_parents[] = {
394 "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
395};
396
397static struct clk dpll_iva_ck;
398
399static const struct clk_ops dpll_ck_ops = {
400 .enable = &omap3_noncore_dpll_enable,
401 .disable = &omap3_noncore_dpll_disable,
402 .recalc_rate = &omap3_dpll_recalc,
403 .round_rate = &omap2_dpll_round_rate,
404 .set_rate = &omap3_noncore_dpll_set_rate,
405 .get_parent = &omap2_init_dpll_parent,
406};
407
408static struct clk_hw_omap dpll_iva_ck_hw = {
409 .hw = {
410 .clk = &dpll_iva_ck,
411 },
412 .dpll_data = &dpll_iva_dd,
413 .ops = &clkhwops_omap3_dpll,
414};
415
416DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
417
418static const char *dpll_iva_x2_ck_parents[] = {
419 "dpll_iva_ck",
420};
421
422static struct clk dpll_iva_x2_ck;
423
424static struct clk_hw_omap dpll_iva_x2_ck_hw = {
425 .hw = {
426 .clk = &dpll_iva_x2_ck,
427 },
428};
429
430DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
431
432DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
433 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
434 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
435
436DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
437 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
438 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
439
440/* DPLL_MPU */
441static struct dpll_data dpll_mpu_dd = {
442 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
443 .clk_bypass = &div_mpu_hs_clk,
444 .clk_ref = &sys_clkin_ck,
445 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
446 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
447 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
448 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
449 .mult_mask = OMAP4430_DPLL_MULT_MASK,
450 .div1_mask = OMAP4430_DPLL_DIV_MASK,
451 .enable_mask = OMAP4430_DPLL_EN_MASK,
452 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
453 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
454 .max_multiplier = 2047,
455 .max_divider = 128,
456 .min_divider = 1,
457};
458
459static const char *dpll_mpu_ck_parents[] = {
460 "sys_clkin_ck", "div_mpu_hs_clk"
461};
462
463static struct clk dpll_mpu_ck;
464
465static struct clk_hw_omap dpll_mpu_ck_hw = {
466 .hw = {
467 .clk = &dpll_mpu_ck,
468 },
469 .dpll_data = &dpll_mpu_dd,
470 .ops = &clkhwops_omap3_dpll,
471};
472
473DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
474
475DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
476
477DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
478 OMAP4430_CM_DIV_M2_DPLL_MPU,
479 OMAP4430_DPLL_CLKOUT_DIV_MASK);
480
481DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
482 &dpll_abe_m3x2_ck, 0x0, 1, 2);
483
484static const char *per_hsd_byp_clk_mux_ck_parents[] = {
485 "sys_clkin_ck", "per_hs_clk_div_ck",
486};
487
488DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
489 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
490 OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
491
492/* DPLL_PER */
493static struct dpll_data dpll_per_dd = {
494 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
495 .clk_bypass = &per_hsd_byp_clk_mux_ck,
496 .clk_ref = &sys_clkin_ck,
497 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
498 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
499 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
500 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
501 .mult_mask = OMAP4430_DPLL_MULT_MASK,
502 .div1_mask = OMAP4430_DPLL_DIV_MASK,
503 .enable_mask = OMAP4430_DPLL_EN_MASK,
504 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
505 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
506 .max_multiplier = 2047,
507 .max_divider = 128,
508 .min_divider = 1,
509};
510
511static const char *dpll_per_ck_parents[] = {
512 "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
513};
514
515static struct clk dpll_per_ck;
516
517static struct clk_hw_omap dpll_per_ck_hw = {
518 .hw = {
519 .clk = &dpll_per_ck,
520 },
521 .dpll_data = &dpll_per_dd,
522 .ops = &clkhwops_omap3_dpll,
523};
524
525DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
526
527DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
528 OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
529 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
530
531static const char *dpll_per_x2_ck_parents[] = {
532 "dpll_per_ck",
533};
534
535static struct clk dpll_per_x2_ck;
536
537static struct clk_hw_omap dpll_per_x2_ck_hw = {
538 .hw = {
539 .clk = &dpll_per_x2_ck,
540 },
541 .flags = CLOCK_CLKOUTX2,
542 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
543 .ops = &clkhwops_omap4_dpllmx,
544};
545
546DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
547
548DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
549 0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
550 OMAP4430_DPLL_CLKOUT_DIV_MASK);
551
552static const char *dpll_per_m3x2_ck_parents[] = {
553 "dpll_per_x2_ck",
554};
555
556static const struct clksel dpll_per_m3x2_div[] = {
557 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
558 { .parent = NULL },
559};
560
561/* XXX Missing round_rate, set_rate in ops */
562DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
563 OMAP4430_CM_DIV_M3_DPLL_PER,
564 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
565 OMAP4430_CM_DIV_M3_DPLL_PER,
566 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
567 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
568
569DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
570 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
571 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
572
573DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
574 0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
575 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
576
577DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
578 0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
579 OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
580
581DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
582 0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
583 OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
584
585DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
586 &dpll_abe_m3x2_ck, 0x0, 1, 3);
587
588/* DPLL_USB */
589static struct dpll_data dpll_usb_dd = {
590 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
591 .clk_bypass = &usb_hs_clk_div_ck,
592 .flags = DPLL_J_TYPE,
593 .clk_ref = &sys_clkin_ck,
594 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
595 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
596 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
597 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
598 .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
599 .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
600 .enable_mask = OMAP4430_DPLL_EN_MASK,
601 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
602 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
603 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
604 .max_multiplier = 4095,
605 .max_divider = 256,
606 .min_divider = 1,
607};
608
609static const char *dpll_usb_ck_parents[] = {
610 "sys_clkin_ck", "usb_hs_clk_div_ck"
611};
612
613static struct clk dpll_usb_ck;
614
615static const struct clk_ops dpll_usb_ck_ops = {
616 .enable = &omap3_noncore_dpll_enable,
617 .disable = &omap3_noncore_dpll_disable,
618 .recalc_rate = &omap3_dpll_recalc,
619 .round_rate = &omap2_dpll_round_rate,
620 .set_rate = &omap3_noncore_dpll_set_rate,
621 .get_parent = &omap2_init_dpll_parent,
622 .init = &omap2_init_clk_clkdm,
623};
624
625static struct clk_hw_omap dpll_usb_ck_hw = {
626 .hw = {
627 .clk = &dpll_usb_ck,
628 },
629 .dpll_data = &dpll_usb_dd,
630 .clkdm_name = "l3_init_clkdm",
631 .ops = &clkhwops_omap3_dpll,
632};
633
634DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
635
636static const char *dpll_usb_clkdcoldo_ck_parents[] = {
637 "dpll_usb_ck",
638};
639
640static struct clk dpll_usb_clkdcoldo_ck;
641
642static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
643};
644
645static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
646 .hw = {
647 .clk = &dpll_usb_clkdcoldo_ck,
648 },
649 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
650 .ops = &clkhwops_omap4_dpllmx,
651};
652
653DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
654 dpll_usb_clkdcoldo_ck_ops);
655
656DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
657 OMAP4430_CM_DIV_M2_DPLL_USB,
658 OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
659
660static const char *ducati_clk_mux_ck_parents[] = {
661 "div_core_ck", "dpll_per_m6x2_ck",
662};
663
664DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
665 OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
666 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
667
668DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
669 0x0, 1, 16);
670
671DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
672 1, 4);
673
674DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
675 0x0, 1, 8);
676
677static const struct clk_div_table func_48m_fclk_rates[] = {
678 { .div = 4, .val = 0 },
679 { .div = 8, .val = 1 },
680 { .div = 0 },
681};
682DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
683 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
684 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
685 NULL);
686
687DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
688 0x0, 1, 4);
689
690static const struct clk_div_table func_64m_fclk_rates[] = {
691 { .div = 2, .val = 0 },
692 { .div = 4, .val = 1 },
693 { .div = 0 },
694};
695DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
696 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
697 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
698 NULL);
699
700static const struct clk_div_table func_96m_fclk_rates[] = {
701 { .div = 2, .val = 0 },
702 { .div = 4, .val = 1 },
703 { .div = 0 },
704};
705DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
706 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
707 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
708 NULL);
709
710static const struct clk_div_table init_60m_fclk_rates[] = {
711 { .div = 1, .val = 0 },
712 { .div = 8, .val = 1 },
713 { .div = 0 },
714};
715DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
716 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
717 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
718 0x0, init_60m_fclk_rates, NULL);
719
720DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
721 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
722 OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
723
724DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
725 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
726 OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
727
728DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
729 0x0, 1, 16);
730
731static const char *l4_wkup_clk_mux_ck_parents[] = {
732 "sys_clkin_ck", "lp_clk_div_ck",
733};
734
735DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
736 OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
737 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
738
739static const struct clk_div_table ocp_abe_iclk_rates[] = {
740 { .div = 2, .val = 0 },
741 { .div = 1, .val = 1 },
742 { .div = 0 },
743};
744DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
745 OMAP4430_CM1_ABE_AESS_CLKCTRL,
746 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
747 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
748 0x0, ocp_abe_iclk_rates, NULL);
749
750DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
751 0x0, 1, 4);
752
753DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
754 OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
755 OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
756
757DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
758 OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
759 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
760
761static const char *dbgclk_mux_ck_parents[] = {
762 "sys_clkin_ck"
763};
764
765static struct clk dbgclk_mux_ck;
766DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
767DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
768 dpll_usb_clkdcoldo_ck_ops);
769
770/* Leaf clocks controlled by modules */
771
772DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
773 OMAP4430_CM_L4SEC_AES1_CLKCTRL,
774 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
775
776DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
777 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
778 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
779
780DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
781 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
782 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
783
784static const struct clk_div_table div_ts_ck_rates[] = {
785 { .div = 8, .val = 0 },
786 { .div = 16, .val = 1 },
787 { .div = 32, .val = 2 },
788 { .div = 0 },
789};
790DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
791 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
792 OMAP4430_CLKSEL_24_25_SHIFT,
793 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
794 NULL);
795
796DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
797 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
798 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
799 0x0, NULL);
800
801static const char *dmic_sync_mux_ck_parents[] = {
802 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
803};
804
805DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
806 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
807 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
808 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
809
810static const struct clksel func_dmic_abe_gfclk_sel[] = {
811 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
812 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
813 { .parent = &slimbus_clk, .rates = div_1_2_rates },
814 { .parent = NULL },
815};
816
817static const char *func_dmic_abe_gfclk_parents[] = {
818 "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
819};
820
821DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
822 OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
823 func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
824
825DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
826 OMAP4430_CM_DSS_DSS_CLKCTRL,
827 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
828
829DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
830 OMAP4430_CM_DSS_DSS_CLKCTRL,
831 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
832
833DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
834 CLK_SET_RATE_PARENT,
835 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
836 0x0, NULL);
837
838DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
839 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
840 0x0, NULL);
841
842DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
843 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
844 0x0, NULL);
845
846DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
847 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
848 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
849
850DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
851 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
852 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
853
854DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
855 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
856 0x0, NULL);
857
858DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
859 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
860 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
861
862DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
863 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
864 0x0, NULL);
865
866DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
867 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
868 0x0, NULL);
869
870DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
871 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
872 0x0, NULL);
873
874static const struct clksel sgx_clk_mux_sel[] = {
875 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
876 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
877 { .parent = NULL },
878};
879
880static const char *sgx_clk_mux_parents[] = {
881 "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
882};
883
884DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
885 OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
886 sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
887
888DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
889 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
890 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
891 NULL);
892
893DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
894 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
895 0x0, NULL);
896
897DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
898 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
899 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
900 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
901
902static const struct clksel func_mcasp_abe_gfclk_sel[] = {
903 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
904 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
905 { .parent = &slimbus_clk, .rates = div_1_2_rates },
906 { .parent = NULL },
907};
908
909static const char *func_mcasp_abe_gfclk_parents[] = {
910 "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
911};
912
913DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
914 OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
915 func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
916
917DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
918 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
919 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
920 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
921
922static const struct clksel func_mcbsp1_gfclk_sel[] = {
923 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
924 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
925 { .parent = &slimbus_clk, .rates = div_1_2_rates },
926 { .parent = NULL },
927};
928
929static const char *func_mcbsp1_gfclk_parents[] = {
930 "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
931};
932
933DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
934 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
935 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
936 func_dmic_abe_gfclk_ops);
937
938DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
939 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
940 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
941 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
942
943static const struct clksel func_mcbsp2_gfclk_sel[] = {
944 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
945 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
946 { .parent = &slimbus_clk, .rates = div_1_2_rates },
947 { .parent = NULL },
948};
949
950static const char *func_mcbsp2_gfclk_parents[] = {
951 "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
952};
953
954DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
955 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
956 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
957 func_dmic_abe_gfclk_ops);
958
959DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
960 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
961 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
962 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
963
964static const struct clksel func_mcbsp3_gfclk_sel[] = {
965 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
966 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
967 { .parent = &slimbus_clk, .rates = div_1_2_rates },
968 { .parent = NULL },
969};
970
971static const char *func_mcbsp3_gfclk_parents[] = {
972 "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
973};
974
975DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
976 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
977 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
978 func_dmic_abe_gfclk_ops);
979
980static const char *mcbsp4_sync_mux_ck_parents[] = {
981 "func_96m_fclk", "per_abe_nc_fclk",
982};
983
984DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
985 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
986 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
987 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
988
989static const struct clksel per_mcbsp4_gfclk_sel[] = {
990 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
991 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
992 { .parent = NULL },
993};
994
995static const char *per_mcbsp4_gfclk_parents[] = {
996 "mcbsp4_sync_mux_ck", "pad_clks_ck",
997};
998
999DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1000 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1001 OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
1002 func_dmic_abe_gfclk_ops);
1003
1004static const struct clksel hsmmc1_fclk_sel[] = {
1005 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1006 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1007 { .parent = NULL },
1008};
1009
1010static const char *hsmmc1_fclk_parents[] = {
1011 "func_64m_fclk", "func_96m_fclk",
1012};
1013
1014DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1015 OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1016 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1017
1018DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1019 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1020 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1021
1022DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1023 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1024 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1025
1026DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1027 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1028 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1029
1030DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1031 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1032 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
1033
1034DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
1035 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1036 OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
1037
1038DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
1039 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1040 OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
1041
1042DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1043 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1044 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1045
1046DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1047 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1048 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
1049
1050DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
1051 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1052 OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
1053
1054DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1055 &pad_slimbus_core_clks_ck, 0x0,
1056 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1057 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1058
1059DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1060 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1061 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1062
1063DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1064 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1065 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1066
1067DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1068 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1069 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1070
1071static const struct clksel dmt1_clk_mux_sel[] = {
1072 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1073 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1074 { .parent = NULL },
1075};
1076
1077DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1078 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1079 abe_dpll_bypass_clk_mux_ck_parents,
1080 func_dmic_abe_gfclk_ops);
1081
1082DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1083 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
1084 abe_dpll_bypass_clk_mux_ck_parents,
1085 func_dmic_abe_gfclk_ops);
1086
1087DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1088 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
1089 abe_dpll_bypass_clk_mux_ck_parents,
1090 func_dmic_abe_gfclk_ops);
1091
1092DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1093 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1094 abe_dpll_bypass_clk_mux_ck_parents,
1095 func_dmic_abe_gfclk_ops);
1096
1097DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1098 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
1099 abe_dpll_bypass_clk_mux_ck_parents,
1100 func_dmic_abe_gfclk_ops);
1101
1102DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1103 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
1104 abe_dpll_bypass_clk_mux_ck_parents,
1105 func_dmic_abe_gfclk_ops);
1106
1107static const struct clksel timer5_sync_mux_sel[] = {
1108 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1109 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1110 { .parent = NULL },
1111};
1112
1113static const char *timer5_sync_mux_parents[] = {
1114 "syc_clk_div_ck", "sys_32k_ck",
1115};
1116
1117DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1118 OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1119 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1120
1121DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1122 OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1123 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1124
1125DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1126 OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1127 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1128
1129DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1130 OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1131 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1132
1133DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1134 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
1135 abe_dpll_bypass_clk_mux_ck_parents,
1136 func_dmic_abe_gfclk_ops);
1137
1138static struct clk usb_host_fs_fck;
1139
1140static const char *usb_host_fs_fck_parent_names[] = {
1141 "func_48mc_fclk",
1142};
1143
1144static const struct clk_ops usb_host_fs_fck_ops = {
1145 .enable = &omap2_dflt_clk_enable,
1146 .disable = &omap2_dflt_clk_disable,
1147 .is_enabled = &omap2_dflt_clk_is_enabled,
1148};
1149
1150static struct clk_hw_omap usb_host_fs_fck_hw = {
1151 .hw = {
1152 .clk = &usb_host_fs_fck,
1153 },
1154 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
1155 .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1156 .clkdm_name = "l3_init_clkdm",
1157};
1158
1159DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
1160 usb_host_fs_fck_ops);
1161
1162static const char *utmi_p1_gfclk_parents[] = {
1163 "init_60m_fclk", "xclk60mhsp1_ck",
1164};
1165
1166DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
1167 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1168 OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
1169 0x0, NULL);
1170
1171DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
1172 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1173 OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
1174
1175static const char *utmi_p2_gfclk_parents[] = {
1176 "init_60m_fclk", "xclk60mhsp2_ck",
1177};
1178
1179DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
1180 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1181 OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
1182 0x0, NULL);
1183
1184DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
1185 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1186 OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
1187
1188DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1189 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1190 OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
1191
1192DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
1193 &dpll_usb_m2_ck, 0x0,
1194 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1195 OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
1196
1197DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
1198 &init_60m_fclk, 0x0,
1199 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1200 OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
1201
1202DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
1203 &init_60m_fclk, 0x0,
1204 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1205 OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
1206
1207DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
1208 &dpll_usb_m2_ck, 0x0,
1209 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1210 OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
1211
1212DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
1213 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1214 OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
1215
1216DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
1217 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1218 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1219
1220static const char *otg_60m_gfclk_parents[] = {
1221 "utmi_phy_clkout_ck", "xclk60motg_ck",
1222};
1223
1224DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
1225 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
1226 OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
1227
1228DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
1229 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1230 OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
1231
1232DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
1233 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1234 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1235
1236DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
1237 OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
1238 OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
1239
1240DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1241 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1242 OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
1243
1244DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1245 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1246 OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
1247
1248DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1249 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1250 OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
1251
1252DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
1253 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1254 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1255
1256static const struct clk_div_table usim_ck_rates[] = {
1257 { .div = 14, .val = 0 },
1258 { .div = 18, .val = 1 },
1259 { .div = 0 },
1260};
1261DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
1262 OMAP4430_CM_WKUP_USIM_CLKCTRL,
1263 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
1264 0x0, usim_ck_rates, NULL);
1265
1266DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1267 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1268 0x0, NULL);
1269
1270/* Remaining optional clocks */
1271static const char *pmd_stm_clock_mux_ck_parents[] = {
1272 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
1273};
1274
1275DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1276 OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
1277 OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
1278
1279DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1280 OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1281 OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
1282 OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
1283
1284DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
1285 &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1286 OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
1287 OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
1288 NULL);
1289
1290static const char *trace_clk_div_ck_parents[] = {
1291 "pmd_trace_clk_mux_ck",
1292};
1293
1294static const struct clksel trace_clk_div_div[] = {
1295 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
1296 { .parent = NULL },
1297};
1298
1299static struct clk trace_clk_div_ck;
1300
1301static const struct clk_ops trace_clk_div_ck_ops = {
1302 .recalc_rate = &omap2_clksel_recalc,
1303 .set_rate = &omap2_clksel_set_rate,
1304 .round_rate = &omap2_clksel_round_rate,
1305 .init = &omap2_init_clk_clkdm,
1306 .enable = &omap2_clkops_enable_clkdm,
1307 .disable = &omap2_clkops_disable_clkdm,
1308};
1309
1310static struct clk_hw_omap trace_clk_div_ck_hw = {
1311 .hw = {
1312 .clk = &trace_clk_div_ck,
1313 },
1314 .clkdm_name = "emu_sys_clkdm",
1315 .clksel = trace_clk_div_div,
1316 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1317 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
1318};
1319
1320DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
1321 trace_clk_div_ck_ops);
1322
1323/* SCRM aux clk nodes */
1324
1325static const struct clksel auxclk_src_sel[] = {
1326 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1327 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
1328 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
1329 { .parent = NULL },
1330};
1331
1332static const char *auxclk_src_ck_parents[] = {
1333 "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
1334};
1335
1336static const struct clk_ops auxclk_src_ck_ops = {
1337 .enable = &omap2_dflt_clk_enable,
1338 .disable = &omap2_dflt_clk_disable,
1339 .is_enabled = &omap2_dflt_clk_is_enabled,
1340 .recalc_rate = &omap2_clksel_recalc,
1341 .get_parent = &omap2_clksel_find_parent_index,
1342};
1343
1344DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
1345 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
1346 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
1347 auxclk_src_ck_parents, auxclk_src_ck_ops);
1348
1349DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
1350 OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1351 0x0, NULL);
1352
1353DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
1354 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
1355 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
1356 auxclk_src_ck_parents, auxclk_src_ck_ops);
1357
1358DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
1359 OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1360 0x0, NULL);
1361
1362DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
1363 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
1364 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
1365 auxclk_src_ck_parents, auxclk_src_ck_ops);
1366
1367DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
1368 OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1369 0x0, NULL);
1370
1371DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
1372 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
1373 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
1374 auxclk_src_ck_parents, auxclk_src_ck_ops);
1375
1376DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
1377 OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1378 0x0, NULL);
1379
1380DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
1381 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
1382 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
1383 auxclk_src_ck_parents, auxclk_src_ck_ops);
1384
1385DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
1386 OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1387 0x0, NULL);
1388
1389DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
1390 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
1391 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
1392 auxclk_src_ck_parents, auxclk_src_ck_ops);
1393
1394DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
1395 OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1396 0x0, NULL);
1397
1398static const char *auxclkreq_ck_parents[] = {
1399 "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
1400 "auxclk5_ck",
1401};
1402
1403DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
1404 OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1405 0x0, NULL);
1406
1407DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
1408 OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1409 0x0, NULL);
1410
1411DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
1412 OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1413 0x0, NULL);
1414
1415DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
1416 OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1417 0x0, NULL);
1418
1419DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
1420 OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1421 0x0, NULL);
1422
1423DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1424 OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1425 0x0, NULL);
1426
1427/*
1428 * clocks specific to omap4460
1429 */
1430static struct omap_clk omap446x_clks[] = {
1431 CLK(NULL, "div_ts_ck", &div_ts_ck),
1432 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk),
1433};
1434
1435/*
1436 * clocks specific to omap4430
1437 */
1438static struct omap_clk omap443x_clks[] = {
1439 CLK(NULL, "bandgap_fclk", &bandgap_fclk),
1440};
1441
1442/*
1443 * clocks common to omap44xx
1444 */
1445static struct omap_clk omap44xx_clks[] = {
1446 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck),
1447 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck),
1448 CLK(NULL, "pad_clks_ck", &pad_clks_ck),
1449 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck),
1450 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck),
1451 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk),
1452 CLK(NULL, "slimbus_clk", &slimbus_clk),
1453 CLK(NULL, "sys_32k_ck", &sys_32k_ck),
1454 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck),
1455 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck),
1456 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck),
1457 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
1458 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
1459 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck),
1460 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck),
1461 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
1462 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck),
1463 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck),
1464 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck),
1465 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck),
1466 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck),
1467 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck),
1468 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck),
1469 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck),
1470 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck),
1471 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck),
1472 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk),
1473 CLK(NULL, "abe_clk", &abe_clk),
1474 CLK(NULL, "aess_fclk", &aess_fclk),
1475 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck),
1476 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck),
1477 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
1478 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
1479 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck),
1480 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck),
1481 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck),
1482 CLK(NULL, "ddrphy_ck", &ddrphy_ck),
1483 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck),
1484 CLK(NULL, "div_core_ck", &div_core_ck),
1485 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk),
1486 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk),
1487 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck),
1488 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck),
1489 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck),
1490 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck),
1491 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck),
1492 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck),
1493 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck),
1494 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck),
1495 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck),
1496 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck),
1497 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
1498 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
1499 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck),
1500 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck),
1501 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
1502 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
1503 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck),
1504 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck),
1505 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck),
1506 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck),
1507 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck),
1508 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck),
1509 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck),
1510 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck),
1511 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck),
1512 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck),
1513 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck),
1514 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck),
1515 CLK(NULL, "func_12m_fclk", &func_12m_fclk),
1516 CLK(NULL, "func_24m_clk", &func_24m_clk),
1517 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk),
1518 CLK(NULL, "func_48m_fclk", &func_48m_fclk),
1519 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk),
1520 CLK(NULL, "func_64m_fclk", &func_64m_fclk),
1521 CLK(NULL, "func_96m_fclk", &func_96m_fclk),
1522 CLK(NULL, "init_60m_fclk", &init_60m_fclk),
1523 CLK(NULL, "l3_div_ck", &l3_div_ck),
1524 CLK(NULL, "l4_div_ck", &l4_div_ck),
1525 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck),
1526 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck),
1527 CLK("smp_twd", NULL, &mpu_periphclk),
1528 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk),
1529 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk),
1530 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk),
1531 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck),
1532 CLK(NULL, "aes1_fck", &aes1_fck),
1533 CLK(NULL, "aes2_fck", &aes2_fck),
1534 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck),
1535 CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk),
1536 CLK(NULL, "dss_sys_clk", &dss_sys_clk),
1537 CLK(NULL, "dss_tv_clk", &dss_tv_clk),
1538 CLK(NULL, "dss_dss_clk", &dss_dss_clk),
1539 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk),
1540 CLK(NULL, "dss_fck", &dss_fck),
1541 CLK("omapdss_dss", "ick", &dss_fck),
1542 CLK(NULL, "fdif_fck", &fdif_fck),
1543 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
1544 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
1545 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
1546 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk),
1547 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk),
1548 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk),
1549 CLK(NULL, "sgx_clk_mux", &sgx_clk_mux),
1550 CLK(NULL, "hsi_fck", &hsi_fck),
1551 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk),
1552 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck),
1553 CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk),
1554 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck),
1555 CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk),
1556 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck),
1557 CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk),
1558 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck),
1559 CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk),
1560 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck),
1561 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk),
1562 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk),
1563 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk),
1564 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m),
1565 CLK(NULL, "sha2md5_fck", &sha2md5_fck),
1566 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1),
1567 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0),
1568 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2),
1569 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk),
1570 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1),
1571 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0),
1572 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk),
1573 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck),
1574 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck),
1575 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck),
1576 CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux),
1577 CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux),
1578 CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux),
1579 CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux),
1580 CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux),
1581 CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux),
1582 CLK(NULL, "timer5_sync_mux", &timer5_sync_mux),
1583 CLK(NULL, "timer6_sync_mux", &timer6_sync_mux),
1584 CLK(NULL, "timer7_sync_mux", &timer7_sync_mux),
1585 CLK(NULL, "timer8_sync_mux", &timer8_sync_mux),
1586 CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux),
1587 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck),
1588 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck),
1589 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk),
1590 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk),
1591 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk),
1592 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk),
1593 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk),
1594 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk),
1595 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk),
1596 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk),
1597 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk),
1598 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk),
1599 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck),
1600 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck),
1601 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk),
1602 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk),
1603 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick),
1604 CLK("musb-omap2430", "ick", &usb_otg_hs_ick),
1605 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k),
1606 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk),
1607 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk),
1608 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk),
1609 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick),
1610 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick),
1611 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick),
1612 CLK(NULL, "usim_ck", &usim_ck),
1613 CLK(NULL, "usim_fclk", &usim_fclk),
1614 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck),
1615 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck),
1616 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
1617 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
1618 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck),
1619 CLK(NULL, "auxclk0_ck", &auxclk0_ck),
1620 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck),
1621 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck),
1622 CLK(NULL, "auxclk1_ck", &auxclk1_ck),
1623 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck),
1624 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck),
1625 CLK(NULL, "auxclk2_ck", &auxclk2_ck),
1626 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck),
1627 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck),
1628 CLK(NULL, "auxclk3_ck", &auxclk3_ck),
1629 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck),
1630 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck),
1631 CLK(NULL, "auxclk4_ck", &auxclk4_ck),
1632 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck),
1633 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
1634 CLK(NULL, "auxclk5_ck", &auxclk5_ck),
1635 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
1636 CLK("50000000.gpmc", "fck", &dummy_ck),
1637 CLK("omap_i2c.1", "ick", &dummy_ck),
1638 CLK("omap_i2c.2", "ick", &dummy_ck),
1639 CLK("omap_i2c.3", "ick", &dummy_ck),
1640 CLK("omap_i2c.4", "ick", &dummy_ck),
1641 CLK(NULL, "mailboxes_ick", &dummy_ck),
1642 CLK("omap_hsmmc.0", "ick", &dummy_ck),
1643 CLK("omap_hsmmc.1", "ick", &dummy_ck),
1644 CLK("omap_hsmmc.2", "ick", &dummy_ck),
1645 CLK("omap_hsmmc.3", "ick", &dummy_ck),
1646 CLK("omap_hsmmc.4", "ick", &dummy_ck),
1647 CLK("omap-mcbsp.1", "ick", &dummy_ck),
1648 CLK("omap-mcbsp.2", "ick", &dummy_ck),
1649 CLK("omap-mcbsp.3", "ick", &dummy_ck),
1650 CLK("omap-mcbsp.4", "ick", &dummy_ck),
1651 CLK("omap2_mcspi.1", "ick", &dummy_ck),
1652 CLK("omap2_mcspi.2", "ick", &dummy_ck),
1653 CLK("omap2_mcspi.3", "ick", &dummy_ck),
1654 CLK("omap2_mcspi.4", "ick", &dummy_ck),
1655 CLK(NULL, "uart1_ick", &dummy_ck),
1656 CLK(NULL, "uart2_ick", &dummy_ck),
1657 CLK(NULL, "uart3_ick", &dummy_ck),
1658 CLK(NULL, "uart4_ick", &dummy_ck),
1659 CLK("usbhs_omap", "usbhost_ick", &dummy_ck),
1660 CLK("usbhs_omap", "usbtll_fck", &dummy_ck),
1661 CLK("usbhs_tll", "usbtll_fck", &dummy_ck),
1662 CLK("omap_wdt", "ick", &dummy_ck),
1663 CLK(NULL, "timer_32k_ck", &sys_32k_ck),
1664 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
1665 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck),
1666 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck),
1667 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck),
1668 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck),
1669 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck),
1670 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck),
1671 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck),
1672 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck),
1673 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck),
1674 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck),
1675 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck),
1676 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck),
1677 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck),
1678 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck),
1679 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck),
1680 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck),
1681 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck),
1682 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck),
1683 CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck),
1684 CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck),
1685 CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck),
1686 CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck),
1687 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck),
1688};
1689
1690int __init omap4xxx_clk_init(void)
1691{
1692 int rc;
1693
1694 if (cpu_is_omap443x()) {
1695 cpu_mask = RATE_IN_4430;
1696 omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
1697 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1698 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
1699 omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
1700 if (cpu_is_omap447x())
1701 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1702 } else {
1703 return 0;
1704 }
1705
1706 omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
1707
1708 omap2_clk_disable_autoidle_all();
1709
1710 /*
1711 * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
1712 * when its in bypass. So always lock USB before ABE DPLL.
1713 */
1714 /*
1715 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1716 * domain can transition to retention state when not in use.
1717 */
1718 rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1719 if (rc)
1720 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1721
1722 /*
1723 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
1724 * state when turning the ABE clock domain. Workaround this by
1725 * locking the ABE DPLL on boot.
1726 * Lock the ABE DPLL in any case to avoid issues with audio.
1727 */
1728 rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
1729 if (!rc)
1730 rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
1731 if (rc)
1732 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
1733
1734 return 0;
1735}
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 0ec9f6fdf046..7ee26108ac0d 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
97{ 97{
98 u32 v; 98 u32 v;
99 99
100 v = __raw_readl(clk->clksel_reg); 100 v = omap2_clk_readl(clk, clk->clksel_reg);
101 v &= ~clk->clksel_mask; 101 v &= ~clk->clksel_mask;
102 v |= field_val << __ffs(clk->clksel_mask); 102 v |= field_val << __ffs(clk->clksel_mask);
103 __raw_writel(v, clk->clksel_reg); 103 omap2_clk_writel(v, clk, clk->clksel_reg);
104 104
105 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 105 v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */
106} 106}
107 107
108/** 108/**
@@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk)
204 if (!clk->clksel || !clk->clksel_mask) 204 if (!clk->clksel || !clk->clksel_mask)
205 return 0; 205 return 0;
206 206
207 v = __raw_readl(clk->clksel_reg); 207 v = omap2_clk_readl(clk, clk->clksel_reg);
208 v &= clk->clksel_mask; 208 v &= clk->clksel_mask;
209 v >>= __ffs(clk->clksel_mask); 209 v >>= __ffs(clk->clksel_mask);
210 210
@@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
320 WARN((!clk->clksel || !clk->clksel_mask), 320 WARN((!clk->clksel || !clk->clksel_mask),
321 "clock: %s: attempt to call on a non-clksel clock", clk_name); 321 "clock: %s: attempt to call on a non-clksel clock", clk_name);
322 322
323 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 323 r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask;
324 r >>= __ffs(clk->clksel_mask); 324 r >>= __ffs(clk->clksel_mask);
325 325
326 for (clks = clk->clksel; clks->parent && !found; clks++) { 326 for (clks = clk->clksel; clks->parent && !found; clks++) {
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230f8948..47f9562ca7aa 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
196 if (!dd) 196 if (!dd)
197 return -EINVAL; 197 return -EINVAL;
198 198
199 v = __raw_readl(dd->control_reg); 199 v = omap2_clk_readl(clk, dd->control_reg);
200 v &= dd->enable_mask; 200 v &= dd->enable_mask;
201 v >>= __ffs(dd->enable_mask); 201 v >>= __ffs(dd->enable_mask);
202 202
@@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
243 return 0; 243 return 0;
244 244
245 /* Return bypass rate if DPLL is bypassed */ 245 /* Return bypass rate if DPLL is bypassed */
246 v = __raw_readl(dd->control_reg); 246 v = omap2_clk_readl(clk, dd->control_reg);
247 v &= dd->enable_mask; 247 v &= dd->enable_mask;
248 v >>= __ffs(dd->enable_mask); 248 v >>= __ffs(dd->enable_mask);
249 249
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
262 return __clk_get_rate(dd->clk_bypass); 262 return __clk_get_rate(dd->clk_bypass);
263 } 263 }
264 264
265 v = __raw_readl(dd->mult_div1_reg); 265 v = omap2_clk_readl(clk, dd->mult_div1_reg);
266 dpll_mult = v & dd->mult_mask; 266 dpll_mult = v & dd->mult_mask;
267 dpll_mult >>= __ffs(dd->mult_mask); 267 dpll_mult >>= __ffs(dd->mult_mask);
268 dpll_div = v & dd->div1_mask; 268 dpll_div = v & dd->div1_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index f10eb03ce3e2..333f0a666171 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -25,25 +25,29 @@
25/* XXX */ 25/* XXX */
26void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) 26void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
27{ 27{
28 u32 v, r; 28 u32 v;
29 void __iomem *r;
29 30
30 r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); 31 r = (__force void __iomem *)
32 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
31 33
32 v = __raw_readl((__force void __iomem *)r); 34 v = omap2_clk_readl(clk, r);
33 v |= (1 << clk->enable_bit); 35 v |= (1 << clk->enable_bit);
34 __raw_writel(v, (__force void __iomem *)r); 36 omap2_clk_writel(v, clk, r);
35} 37}
36 38
37/* XXX */ 39/* XXX */
38void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) 40void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
39{ 41{
40 u32 v, r; 42 u32 v;
43 void __iomem *r;
41 44
42 r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); 45 r = (__force void __iomem *)
46 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
43 47
44 v = __raw_readl((__force void __iomem *)r); 48 v = omap2_clk_readl(clk, r);
45 v &= ~(1 << clk->enable_bit); 49 v &= ~(1 << clk->enable_bit);
46 __raw_writel(v, (__force void __iomem *)r); 50 omap2_clk_writel(v, clk, r);
47} 51}
48 52
49/* Public data */ 53/* Public data */
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c7c5d31e9082..591581a66532 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,7 +26,6 @@
26#include <linux/clk-private.h> 26#include <linux/clk-private.h>
27#include <asm/cpu.h> 27#include <asm/cpu.h>
28 28
29
30#include <trace/events/power.h> 29#include <trace/events/power.h>
31 30
32#include "soc.h" 31#include "soc.h"
@@ -56,6 +55,31 @@ u16 cpu_mask;
56static bool clkdm_control = true; 55static bool clkdm_control = true;
57 56
58static LIST_HEAD(clk_hw_omap_clocks); 57static LIST_HEAD(clk_hw_omap_clocks);
58void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
59
60void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
61{
62 if (clk->flags & MEMMAP_ADDRESSING) {
63 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
64 writel_relaxed(val, clk_memmaps[r->index] + r->offset);
65 } else {
66 writel_relaxed(val, reg);
67 }
68}
69
70u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
71{
72 u32 val;
73
74 if (clk->flags & MEMMAP_ADDRESSING) {
75 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
76 val = readl_relaxed(clk_memmaps[r->index] + r->offset);
77 } else {
78 val = readl_relaxed(reg);
79 }
80
81 return val;
82}
59 83
60/* 84/*
61 * Used for clocks that have the same value as the parent clock, 85 * Used for clocks that have the same value as the parent clock,
@@ -87,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
87 111
88/** 112/**
89 * _wait_idlest_generic - wait for a module to leave the idle state 113 * _wait_idlest_generic - wait for a module to leave the idle state
114 * @clk: module clock to wait for (needed for register offsets)
90 * @reg: virtual address of module IDLEST register 115 * @reg: virtual address of module IDLEST register
91 * @mask: value to mask against to determine if the module is active 116 * @mask: value to mask against to determine if the module is active
92 * @idlest: idle state indicator (0 or 1) for the clock 117 * @idlest: idle state indicator (0 or 1) for the clock
@@ -98,14 +123,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
98 * elapsed. XXX Deprecated - should be moved into drivers for the 123 * elapsed. XXX Deprecated - should be moved into drivers for the
99 * individual IP block that the IDLEST register exists in. 124 * individual IP block that the IDLEST register exists in.
100 */ 125 */
101static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest, 126static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
102 const char *name) 127 u32 mask, u8 idlest, const char *name)
103{ 128{
104 int i = 0, ena = 0; 129 int i = 0, ena = 0;
105 130
106 ena = (idlest) ? 0 : mask; 131 ena = (idlest) ? 0 : mask;
107 132
108 omap_test_timeout(((__raw_readl(reg) & mask) == ena), 133 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),
109 MAX_MODULE_ENABLE_WAIT, i); 134 MAX_MODULE_ENABLE_WAIT, i);
110 135
111 if (i < MAX_MODULE_ENABLE_WAIT) 136 if (i < MAX_MODULE_ENABLE_WAIT)
@@ -138,7 +163,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
138 /* Not all modules have multiple clocks that their IDLEST depends on */ 163 /* Not all modules have multiple clocks that their IDLEST depends on */
139 if (clk->ops->find_companion) { 164 if (clk->ops->find_companion) {
140 clk->ops->find_companion(clk, &companion_reg, &other_bit); 165 clk->ops->find_companion(clk, &companion_reg, &other_bit);
141 if (!(__raw_readl(companion_reg) & (1 << other_bit))) 166 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))
142 return; 167 return;
143 } 168 }
144 169
@@ -146,8 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
146 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); 171 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
147 if (r) { 172 if (r) {
148 /* IDLEST register not in the CM module */ 173 /* IDLEST register not in the CM module */
149 _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val, 174 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
150 __clk_get_name(clk->hw.clk)); 175 idlest_val, __clk_get_name(clk->hw.clk));
151 } else { 176 } else {
152 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 177 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
153 }; 178 };
@@ -309,13 +334,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
309 } 334 }
310 335
311 /* FIXME should not have INVERT_ENABLE bit here */ 336 /* FIXME should not have INVERT_ENABLE bit here */
312 v = __raw_readl(clk->enable_reg); 337 v = omap2_clk_readl(clk, clk->enable_reg);
313 if (clk->flags & INVERT_ENABLE) 338 if (clk->flags & INVERT_ENABLE)
314 v &= ~(1 << clk->enable_bit); 339 v &= ~(1 << clk->enable_bit);
315 else 340 else
316 v |= (1 << clk->enable_bit); 341 v |= (1 << clk->enable_bit);
317 __raw_writel(v, clk->enable_reg); 342 omap2_clk_writel(v, clk, clk->enable_reg);
318 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 343 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
319 344
320 if (clk->ops && clk->ops->find_idlest) 345 if (clk->ops && clk->ops->find_idlest)
321 _omap2_module_wait_ready(clk); 346 _omap2_module_wait_ready(clk);
@@ -353,12 +378,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
353 return; 378 return;
354 } 379 }
355 380
356 v = __raw_readl(clk->enable_reg); 381 v = omap2_clk_readl(clk, clk->enable_reg);
357 if (clk->flags & INVERT_ENABLE) 382 if (clk->flags & INVERT_ENABLE)
358 v |= (1 << clk->enable_bit); 383 v |= (1 << clk->enable_bit);
359 else 384 else
360 v &= ~(1 << clk->enable_bit); 385 v &= ~(1 << clk->enable_bit);
361 __raw_writel(v, clk->enable_reg); 386 omap2_clk_writel(v, clk, clk->enable_reg);
362 /* No OCP barrier needed here since it is a disable operation */ 387 /* No OCP barrier needed here since it is a disable operation */
363 388
364 if (clkdm_control && clk->clkdm) 389 if (clkdm_control && clk->clkdm)
@@ -454,7 +479,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
454 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 479 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
455 u32 v; 480 u32 v;
456 481
457 v = __raw_readl(clk->enable_reg); 482 v = omap2_clk_readl(clk, clk->enable_reg);
458 483
459 if (clk->flags & INVERT_ENABLE) 484 if (clk->flags & INVERT_ENABLE)
460 v ^= BIT(clk->enable_bit); 485 v ^= BIT(clk->enable_bit);
@@ -520,6 +545,9 @@ int omap2_clk_enable_autoidle_all(void)
520 list_for_each_entry(c, &clk_hw_omap_clocks, node) 545 list_for_each_entry(c, &clk_hw_omap_clocks, node)
521 if (c->ops && c->ops->allow_idle) 546 if (c->ops && c->ops->allow_idle)
522 c->ops->allow_idle(c); 547 c->ops->allow_idle(c);
548
549 of_ti_clk_allow_autoidle_all();
550
523 return 0; 551 return 0;
524} 552}
525 553
@@ -539,6 +567,9 @@ int omap2_clk_disable_autoidle_all(void)
539 list_for_each_entry(c, &clk_hw_omap_clocks, node) 567 list_for_each_entry(c, &clk_hw_omap_clocks, node)
540 if (c->ops && c->ops->deny_idle) 568 if (c->ops && c->ops->deny_idle)
541 c->ops->deny_idle(c); 569 c->ops->deny_idle(c);
570
571 of_ti_clk_deny_autoidle_all();
572
542 return 0; 573 return 0;
543} 574}
544 575
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 82916cc82c92..bda767a9dea8 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
21 21
22#include <linux/clkdev.h> 22#include <linux/clkdev.h>
23#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
24#include <linux/clk/ti.h>
24 25
25struct omap_clk { 26struct omap_clk {
26 u16 cpu; 27 u16 cpu;
@@ -37,7 +38,6 @@ struct omap_clk {
37 } 38 }
38 39
39struct clockdomain; 40struct clockdomain;
40#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
41 41
42#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \ 42#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
43 static struct clk _name = { \ 43 static struct clk _name = { \
@@ -178,141 +178,6 @@ struct clksel {
178 const struct clksel_rate *rates; 178 const struct clksel_rate *rates;
179}; 179};
180 180
181/**
182 * struct dpll_data - DPLL registers and integration data
183 * @mult_div1_reg: register containing the DPLL M and N bitfields
184 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
185 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
186 * @clk_bypass: struct clk pointer to the clock's bypass clock input
187 * @clk_ref: struct clk pointer to the clock's reference clock input
188 * @control_reg: register containing the DPLL mode bitfield
189 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
190 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
191 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
192 * @last_rounded_m4xen: cache of the last M4X result of
193 * omap4_dpll_regm4xen_round_rate()
194 * @last_rounded_lpmode: cache of the last lpmode result of
195 * omap4_dpll_lpmode_recalc()
196 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
197 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
198 * @min_divider: minimum valid non-bypass divider value (actual)
199 * @max_divider: maximum valid non-bypass divider value (actual)
200 * @modes: possible values of @enable_mask
201 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
202 * @idlest_reg: register containing the DPLL idle status bitfield
203 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
204 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
205 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
206 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
207 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
208 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
209 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
210 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
211 * @flags: DPLL type/features (see below)
212 *
213 * Possible values for @flags:
214 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
215 *
216 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
217 *
218 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
219 * correct to only have one @clk_bypass pointer.
220 *
221 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
222 * @last_rounded_n) should be separated from the runtime-fixed fields
223 * and placed into a different structure, so that the runtime-fixed data
224 * can be placed into read-only space.
225 */
226struct dpll_data {
227 void __iomem *mult_div1_reg;
228 u32 mult_mask;
229 u32 div1_mask;
230 struct clk *clk_bypass;
231 struct clk *clk_ref;
232 void __iomem *control_reg;
233 u32 enable_mask;
234 unsigned long last_rounded_rate;
235 u16 last_rounded_m;
236 u8 last_rounded_m4xen;
237 u8 last_rounded_lpmode;
238 u16 max_multiplier;
239 u8 last_rounded_n;
240 u8 min_divider;
241 u16 max_divider;
242 u8 modes;
243 void __iomem *autoidle_reg;
244 void __iomem *idlest_reg;
245 u32 autoidle_mask;
246 u32 freqsel_mask;
247 u32 idlest_mask;
248 u32 dco_mask;
249 u32 sddiv_mask;
250 u32 lpmode_mask;
251 u32 m4xen_mask;
252 u8 auto_recal_bit;
253 u8 recal_en_bit;
254 u8 recal_st_bit;
255 u8 flags;
256};
257
258/*
259 * struct clk.flags possibilities
260 *
261 * XXX document the rest of the clock flags here
262 *
263 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
264 * bits share the same register. This flag allows the
265 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
266 * should be used. This is a temporary solution - a better approach
267 * would be to associate clock type-specific data with the clock,
268 * similar to the struct dpll_data approach.
269 */
270#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
271#define CLOCK_IDLE_CONTROL (1 << 1)
272#define CLOCK_NO_IDLE_PARENT (1 << 2)
273#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
274#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
275#define CLOCK_CLKOUTX2 (1 << 5)
276
277/**
278 * struct clk_hw_omap - OMAP struct clk
279 * @node: list_head connecting this clock into the full clock list
280 * @enable_reg: register to write to enable the clock (see @enable_bit)
281 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
282 * @flags: see "struct clk.flags possibilities" above
283 * @clksel_reg: for clksel clks, register va containing src/divisor select
284 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
285 * @clksel: for clksel clks, pointer to struct clksel for this clock
286 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
287 * @clkdm_name: clockdomain name that this clock is contained in
288 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
289 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
290 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
291 *
292 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
293 * clock code converted to use clksel.
294 *
295 */
296
297struct clk_hw_omap_ops;
298
299struct clk_hw_omap {
300 struct clk_hw hw;
301 struct list_head node;
302 unsigned long fixed_rate;
303 u8 fixed_div;
304 void __iomem *enable_reg;
305 u8 enable_bit;
306 u8 flags;
307 void __iomem *clksel_reg;
308 u32 clksel_mask;
309 const struct clksel *clksel;
310 struct dpll_data *dpll_data;
311 const char *clkdm_name;
312 struct clockdomain *clkdm;
313 const struct clk_hw_omap_ops *ops;
314};
315
316struct clk_hw_omap_ops { 181struct clk_hw_omap_ops {
317 void (*find_idlest)(struct clk_hw_omap *oclk, 182 void (*find_idlest)(struct clk_hw_omap *oclk,
318 void __iomem **idlest_reg, 183 void __iomem **idlest_reg,
@@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
348#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 213#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
349#define OMAP4XXX_EN_DPLL_LOCKED 0x7 214#define OMAP4XXX_EN_DPLL_LOCKED 0x7
350 215
351/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
352#define DPLL_LOW_POWER_STOP 0x1
353#define DPLL_LOW_POWER_BYPASS 0x5
354#define DPLL_LOCKED 0x7
355
356/* DPLL Type and DCO Selection Flags */
357#define DPLL_J_TYPE 0x1
358
359long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
360 unsigned long *parent_rate);
361unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
362int omap3_noncore_dpll_enable(struct clk_hw *hw);
363void omap3_noncore_dpll_disable(struct clk_hw *hw);
364int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
365 unsigned long parent_rate);
366u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); 216u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
367void omap3_dpll_allow_idle(struct clk_hw_omap *clk); 217void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
368void omap3_dpll_deny_idle(struct clk_hw_omap *clk); 218void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
369unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
370 unsigned long parent_rate);
371int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk); 219int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
372void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk); 220void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
373void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk); 221void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
374unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
375 unsigned long parent_rate);
376long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
377 unsigned long target_rate,
378 unsigned long *parent_rate);
379 222
380void omap2_init_clk_clkdm(struct clk_hw *clk);
381void __init omap2_clk_disable_clkdm_control(void); 223void __init omap2_clk_disable_clkdm_control(void);
382 224
383/* clkt_clksel.c public functions */ 225/* clkt_clksel.c public functions */
@@ -396,29 +238,25 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
396extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 238extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
397extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 239extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
398 240
399u8 omap2_init_dpll_parent(struct clk_hw *hw);
400unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk); 241unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
401 242
402int omap2_dflt_clk_enable(struct clk_hw *hw);
403void omap2_dflt_clk_disable(struct clk_hw *hw);
404int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
405void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 243void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
406 void __iomem **other_reg, 244 void __iomem **other_reg,
407 u8 *other_bit); 245 u8 *other_bit);
408void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 246void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
409 void __iomem **idlest_reg, 247 void __iomem **idlest_reg,
410 u8 *idlest_bit, u8 *idlest_val); 248 u8 *idlest_bit, u8 *idlest_val);
411void omap2_init_clk_hw_omap_clocks(struct clk *clk);
412int omap2_clk_enable_autoidle_all(void); 249int omap2_clk_enable_autoidle_all(void);
413int omap2_clk_disable_autoidle_all(void);
414int omap2_clk_allow_idle(struct clk *clk); 250int omap2_clk_allow_idle(struct clk *clk);
415int omap2_clk_deny_idle(struct clk *clk); 251int omap2_clk_deny_idle(struct clk *clk);
416void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
417int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name); 252int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
418void omap2_clk_print_new_rates(const char *hfclkin_ck_name, 253void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
419 const char *core_ck_name, 254 const char *core_ck_name,
420 const char *mpu_ck_name); 255 const char *mpu_ck_name);
421 256
257u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
258void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
259
422extern u16 cpu_mask; 260extern u16 cpu_mask;
423 261
424extern const struct clkops clkops_omap2_dflt_wait; 262extern const struct clkops clkops_omap2_dflt_wait;
@@ -433,19 +271,12 @@ extern const struct clksel_rate gfx_l3_rates[];
433extern const struct clksel_rate dsp_ick_rates[]; 271extern const struct clksel_rate dsp_ick_rates[];
434extern struct clk dummy_ck; 272extern struct clk dummy_ck;
435 273
436extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
437extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 274extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
438extern const struct clk_hw_omap_ops clkhwops_wait; 275extern const struct clk_hw_omap_ops clkhwops_wait;
439extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
440extern const struct clk_hw_omap_ops clkhwops_iclk;
441extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait; 276extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
442extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
443extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 277extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
444extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
445extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
446extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait; 278extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
447extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 279extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
448extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
449extern const struct clk_hw_omap_ops clkhwops_apll54; 280extern const struct clk_hw_omap_ops clkhwops_apll54;
450extern const struct clk_hw_omap_ops clkhwops_apll96; 281extern const struct clk_hw_omap_ops clkhwops_apll96;
451extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll; 282extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
@@ -460,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[];
460extern const struct clksel_rate div_1_4_rates[]; 291extern const struct clksel_rate div_1_4_rates[];
461extern const struct clksel_rate div31_1to31_rates[]; 292extern const struct clksel_rate div31_1to31_rates[];
462 293
294extern void __iomem *clk_memmaps[];
295
463extern int am33xx_clk_init(void); 296extern int am33xx_clk_init(void);
464 297
465extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); 298extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index bbd6a3f717e6..91ccb962e09e 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -43,6 +43,7 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
43 struct clk_divider *parent; 43 struct clk_divider *parent;
44 struct clk_hw *parent_hw; 44 struct clk_hw *parent_hw;
45 u32 dummy_v, orig_v; 45 u32 dummy_v, orig_v;
46 struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk);
46 int ret; 47 int ret;
47 48
48 /* Clear PWRDN bit of HSDIVIDER */ 49 /* Clear PWRDN bit of HSDIVIDER */
@@ -53,15 +54,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
53 54
54 /* Restore the dividers */ 55 /* Restore the dividers */
55 if (!ret) { 56 if (!ret) {
56 orig_v = __raw_readl(parent->reg); 57 orig_v = omap2_clk_readl(omap_clk, parent->reg);
57 dummy_v = orig_v; 58 dummy_v = orig_v;
58 59
59 /* Write any other value different from the Read value */ 60 /* Write any other value different from the Read value */
60 dummy_v ^= (1 << parent->shift); 61 dummy_v ^= (1 << parent->shift);
61 __raw_writel(dummy_v, parent->reg); 62 omap2_clk_writel(dummy_v, omap_clk, parent->reg);
62 63
63 /* Write the original divider */ 64 /* Write the original divider */
64 __raw_writel(orig_v, parent->reg); 65 omap2_clk_writel(orig_v, omap_clk, parent->reg);
65 } 66 }
66 67
67 return ret; 68 return ret;
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8cd4b0a882ae..78d9f562e3ce 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,11 +9,8 @@
9#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
10 10
11int omap3xxx_clk_init(void); 11int omap3xxx_clk_init(void);
12int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
13 unsigned long parent_rate);
14int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate, 12int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
15 unsigned long parent_rate); 13 unsigned long parent_rate);
16void omap3_clk_lock_dpll5(void);
17 14
18extern struct clk *sdrc_ick_p; 15extern struct clk *sdrc_ick_p;
19extern struct clk *arm_fck_p; 16extern struct clk *arm_fck_p;
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 72bb41b3fd25..f338177e6900 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -10,5 +10,6 @@ struct ads7846_platform_data;
10 10
11void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, 11void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
12 struct ads7846_platform_data *board_pdata); 12 struct ads7846_platform_data *board_pdata);
13void *n8x0_legacy_init(void);
13 14
14#endif /* __OMAP_COMMON_BOARD_DEVICES__ */ 15#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index e30ef6797c63..a6aae300542c 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -62,11 +62,17 @@ static inline int omap3_pm_init(void)
62 62
63#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) 63#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
64int omap4_pm_init(void); 64int omap4_pm_init(void);
65int omap4_pm_init_early(void);
65#else 66#else
66static inline int omap4_pm_init(void) 67static inline int omap4_pm_init(void)
67{ 68{
68 return 0; 69 return 0;
69} 70}
71
72static inline int omap4_pm_init_early(void)
73{
74 return 0;
75}
70#endif 76#endif
71 77
72#ifdef CONFIG_OMAP_MUX 78#ifdef CONFIG_OMAP_MUX
@@ -236,6 +242,7 @@ static inline void __iomem *omap4_get_scu_base(void)
236 242
237extern void __init gic_init_irq(void); 243extern void __init gic_init_irq(void);
238extern void gic_dist_disable(void); 244extern void gic_dist_disable(void);
245extern void gic_dist_enable(void);
239extern bool gic_dist_disabled(void); 246extern bool gic_dist_disabled(void);
240extern void gic_timer_retrigger(void); 247extern void gic_timer_retrigger(void);
241extern void omap_smc1(u32 fn, u32 arg); 248extern void omap_smc1(u32 fn, u32 arg);
@@ -293,6 +300,7 @@ static inline void omap4_cpu_resume(void)
293#endif 300#endif
294 301
295void pdata_quirks_init(struct of_device_id *); 302void pdata_quirks_init(struct of_device_id *);
303void omap_auxdata_legacy_init(struct device *dev);
296void omap_pcs_legacy_init(int irq, void (*rearm)(void)); 304void omap_pcs_legacy_init(int irq, void (*rearm)(void));
297 305
298struct omap_sdrc_params; 306struct omap_sdrc_params;
@@ -305,7 +313,7 @@ struct omap_hwmod;
305extern int omap_dss_reset(struct omap_hwmod *); 313extern int omap_dss_reset(struct omap_hwmod *);
306 314
307/* SoC specific clock initializer */ 315/* SoC specific clock initializer */
308extern int (*omap_clk_init)(void); 316int omap_clk_init(void);
309 317
310#endif /* __ASSEMBLER__ */ 318#endif /* __ASSEMBLER__ */
311#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ 319#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 4c8982ae9529..01fc710c8181 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -23,6 +23,8 @@
23#include "prm.h" 23#include "prm.h"
24#include "clockdomain.h" 24#include "clockdomain.h"
25 25
26#define MAX_CPUS 2
27
26/* Machine specific information */ 28/* Machine specific information */
27struct idle_statedata { 29struct idle_statedata {
28 u32 cpu_state; 30 u32 cpu_state;
@@ -48,11 +50,11 @@ static struct idle_statedata omap4_idle_data[] = {
48 }, 50 },
49}; 51};
50 52
51static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS]; 53static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
52static struct clockdomain *cpu_clkdm[NR_CPUS]; 54static struct clockdomain *cpu_clkdm[MAX_CPUS];
53 55
54static atomic_t abort_barrier; 56static atomic_t abort_barrier;
55static bool cpu_done[NR_CPUS]; 57static bool cpu_done[MAX_CPUS];
56static struct idle_statedata *state_ptr = &omap4_idle_data[0]; 58static struct idle_statedata *state_ptr = &omap4_idle_data[0];
57 59
58/* Private functions */ 60/* Private functions */
@@ -80,6 +82,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
80 int index) 82 int index)
81{ 83{
82 struct idle_statedata *cx = state_ptr + index; 84 struct idle_statedata *cx = state_ptr + index;
85 u32 mpuss_can_lose_context = 0;
83 86
84 /* 87 /*
85 * CPU0 has to wait and stay ON until CPU1 is OFF state. 88 * CPU0 has to wait and stay ON until CPU1 is OFF state.
@@ -104,6 +107,9 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
104 } 107 }
105 } 108 }
106 109
110 mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
111 (cx->mpu_logic_state == PWRDM_POWER_OFF);
112
107 /* 113 /*
108 * Call idle CPU PM enter notifier chain so that 114 * Call idle CPU PM enter notifier chain so that
109 * VFP and per CPU interrupt context is saved. 115 * VFP and per CPU interrupt context is saved.
@@ -118,9 +124,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
118 * Call idle CPU cluster PM enter notifier chain 124 * Call idle CPU cluster PM enter notifier chain
119 * to save GIC and wakeupgen context. 125 * to save GIC and wakeupgen context.
120 */ 126 */
121 if ((cx->mpu_state == PWRDM_POWER_RET) && 127 if (mpuss_can_lose_context)
122 (cx->mpu_logic_state == PWRDM_POWER_OFF)) 128 cpu_cluster_pm_enter();
123 cpu_cluster_pm_enter();
124 } 129 }
125 130
126 omap4_enter_lowpower(dev->cpu, cx->cpu_state); 131 omap4_enter_lowpower(dev->cpu, cx->cpu_state);
@@ -128,9 +133,23 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
128 133
129 /* Wakeup CPU1 only if it is not offlined */ 134 /* Wakeup CPU1 only if it is not offlined */
130 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) { 135 if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
136
137 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
138 mpuss_can_lose_context)
139 gic_dist_disable();
140
131 clkdm_wakeup(cpu_clkdm[1]); 141 clkdm_wakeup(cpu_clkdm[1]);
132 omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON); 142 omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
133 clkdm_allow_idle(cpu_clkdm[1]); 143 clkdm_allow_idle(cpu_clkdm[1]);
144
145 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
146 mpuss_can_lose_context) {
147 while (gic_dist_disabled()) {
148 udelay(1);
149 cpu_relax();
150 }
151 gic_timer_retrigger();
152 }
134 } 153 }
135 154
136 /* 155 /*
@@ -143,8 +162,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
143 * Call idle CPU cluster PM exit notifier chain 162 * Call idle CPU cluster PM exit notifier chain
144 * to restore GIC and wakeupgen context. 163 * to restore GIC and wakeupgen context.
145 */ 164 */
146 if (dev->cpu == 0 && (cx->mpu_state == PWRDM_POWER_RET) && 165 if (dev->cpu == 0 && mpuss_can_lose_context)
147 (cx->mpu_logic_state == PWRDM_POWER_OFF))
148 cpu_cluster_pm_exit(); 166 cpu_cluster_pm_exit();
149 167
150fail: 168fail:
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3a0296cfcace..3c418ea54bbe 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -50,10 +50,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
50 50
51 dd = clk->dpll_data; 51 dd = clk->dpll_data;
52 52
53 v = __raw_readl(dd->control_reg); 53 v = omap2_clk_readl(clk, dd->control_reg);
54 v &= ~dd->enable_mask; 54 v &= ~dd->enable_mask;
55 v |= clken_bits << __ffs(dd->enable_mask); 55 v |= clken_bits << __ffs(dd->enable_mask);
56 __raw_writel(v, dd->control_reg); 56 omap2_clk_writel(v, clk, dd->control_reg);
57} 57}
58 58
59/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ 59/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -69,8 +69,8 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
69 69
70 state <<= __ffs(dd->idlest_mask); 70 state <<= __ffs(dd->idlest_mask);
71 71
72 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && 72 while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)
73 i < MAX_DPLL_WAIT_TRIES) { 73 != state) && i < MAX_DPLL_WAIT_TRIES) {
74 i++; 74 i++;
75 udelay(1); 75 udelay(1);
76 } 76 }
@@ -147,7 +147,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
147 state <<= __ffs(dd->idlest_mask); 147 state <<= __ffs(dd->idlest_mask);
148 148
149 /* Check if already locked */ 149 /* Check if already locked */
150 if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state) 150 if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)
151 goto done; 151 goto done;
152 152
153 ai = omap3_dpll_autoidle_read(clk); 153 ai = omap3_dpll_autoidle_read(clk);
@@ -311,14 +311,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
311 * only since freqsel field is no longer present on other devices. 311 * only since freqsel field is no longer present on other devices.
312 */ 312 */
313 if (cpu_is_omap343x()) { 313 if (cpu_is_omap343x()) {
314 v = __raw_readl(dd->control_reg); 314 v = omap2_clk_readl(clk, dd->control_reg);
315 v &= ~dd->freqsel_mask; 315 v &= ~dd->freqsel_mask;
316 v |= freqsel << __ffs(dd->freqsel_mask); 316 v |= freqsel << __ffs(dd->freqsel_mask);
317 __raw_writel(v, dd->control_reg); 317 omap2_clk_writel(v, clk, dd->control_reg);
318 } 318 }
319 319
320 /* Set DPLL multiplier, divider */ 320 /* Set DPLL multiplier, divider */
321 v = __raw_readl(dd->mult_div1_reg); 321 v = omap2_clk_readl(clk, dd->mult_div1_reg);
322 v &= ~(dd->mult_mask | dd->div1_mask); 322 v &= ~(dd->mult_mask | dd->div1_mask);
323 v |= dd->last_rounded_m << __ffs(dd->mult_mask); 323 v |= dd->last_rounded_m << __ffs(dd->mult_mask);
324 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); 324 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
@@ -336,11 +336,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
336 v |= sd_div << __ffs(dd->sddiv_mask); 336 v |= sd_div << __ffs(dd->sddiv_mask);
337 } 337 }
338 338
339 __raw_writel(v, dd->mult_div1_reg); 339 omap2_clk_writel(v, clk, dd->mult_div1_reg);
340 340
341 /* Set 4X multiplier and low-power mode */ 341 /* Set 4X multiplier and low-power mode */
342 if (dd->m4xen_mask || dd->lpmode_mask) { 342 if (dd->m4xen_mask || dd->lpmode_mask) {
343 v = __raw_readl(dd->control_reg); 343 v = omap2_clk_readl(clk, dd->control_reg);
344 344
345 if (dd->m4xen_mask) { 345 if (dd->m4xen_mask) {
346 if (dd->last_rounded_m4xen) 346 if (dd->last_rounded_m4xen)
@@ -356,7 +356,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
356 v &= ~dd->lpmode_mask; 356 v &= ~dd->lpmode_mask;
357 } 357 }
358 358
359 __raw_writel(v, dd->control_reg); 359 omap2_clk_writel(v, clk, dd->control_reg);
360 } 360 }
361 361
362 /* We let the clock framework set the other output dividers later */ 362 /* We let the clock framework set the other output dividers later */
@@ -554,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
554 if (!dd->autoidle_reg) 554 if (!dd->autoidle_reg)
555 return -EINVAL; 555 return -EINVAL;
556 556
557 v = __raw_readl(dd->autoidle_reg); 557 v = omap2_clk_readl(clk, dd->autoidle_reg);
558 v &= dd->autoidle_mask; 558 v &= dd->autoidle_mask;
559 v >>= __ffs(dd->autoidle_mask); 559 v >>= __ffs(dd->autoidle_mask);
560 560
@@ -588,10 +588,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
588 * by writing 0x5 instead of 0x1. Add some mechanism to 588 * by writing 0x5 instead of 0x1. Add some mechanism to
589 * optionally enter this mode. 589 * optionally enter this mode.
590 */ 590 */
591 v = __raw_readl(dd->autoidle_reg); 591 v = omap2_clk_readl(clk, dd->autoidle_reg);
592 v &= ~dd->autoidle_mask; 592 v &= ~dd->autoidle_mask;
593 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); 593 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
594 __raw_writel(v, dd->autoidle_reg); 594 omap2_clk_writel(v, clk, dd->autoidle_reg);
595 595
596} 596}
597 597
@@ -614,28 +614,18 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
614 if (!dd->autoidle_reg) 614 if (!dd->autoidle_reg)
615 return; 615 return;
616 616
617 v = __raw_readl(dd->autoidle_reg); 617 v = omap2_clk_readl(clk, dd->autoidle_reg);
618 v &= ~dd->autoidle_mask; 618 v &= ~dd->autoidle_mask;
619 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); 619 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
620 __raw_writel(v, dd->autoidle_reg); 620 omap2_clk_writel(v, clk, dd->autoidle_reg);
621 621
622} 622}
623 623
624/* Clock control for DPLL outputs */ 624/* Clock control for DPLL outputs */
625 625
626/** 626/* Find the parent DPLL for the given clkoutx2 clock */
627 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate 627static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
628 * @clk: DPLL output struct clk
629 *
630 * Using parent clock DPLL data, look up DPLL state. If locked, set our
631 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
632 */
633unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
634 unsigned long parent_rate)
635{ 628{
636 const struct dpll_data *dd;
637 unsigned long rate;
638 u32 v;
639 struct clk_hw_omap *pclk = NULL; 629 struct clk_hw_omap *pclk = NULL;
640 struct clk *parent; 630 struct clk *parent;
641 631
@@ -653,14 +643,40 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
653 /* clk does not have a DPLL as a parent? error in the clock data */ 643 /* clk does not have a DPLL as a parent? error in the clock data */
654 if (!pclk) { 644 if (!pclk) {
655 WARN_ON(1); 645 WARN_ON(1);
656 return 0; 646 return NULL;
657 } 647 }
658 648
649 return pclk;
650}
651
652/**
653 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
654 * @clk: DPLL output struct clk
655 *
656 * Using parent clock DPLL data, look up DPLL state. If locked, set our
657 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
658 */
659unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
660 unsigned long parent_rate)
661{
662 const struct dpll_data *dd;
663 unsigned long rate;
664 u32 v;
665 struct clk_hw_omap *pclk = NULL;
666
667 if (!parent_rate)
668 return 0;
669
670 pclk = omap3_find_clkoutx2_dpll(hw);
671
672 if (!pclk)
673 return 0;
674
659 dd = pclk->dpll_data; 675 dd = pclk->dpll_data;
660 676
661 WARN_ON(!dd->enable_mask); 677 WARN_ON(!dd->enable_mask);
662 678
663 v = __raw_readl(dd->control_reg) & dd->enable_mask; 679 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
664 v >>= __ffs(dd->enable_mask); 680 v >>= __ffs(dd->enable_mask);
665 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) 681 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
666 rate = parent_rate; 682 rate = parent_rate;
@@ -669,6 +685,55 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
669 return rate; 685 return rate;
670} 686}
671 687
688int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
689 unsigned long parent_rate)
690{
691 return 0;
692}
693
694long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
695 unsigned long *prate)
696{
697 const struct dpll_data *dd;
698 u32 v;
699 struct clk_hw_omap *pclk = NULL;
700
701 if (!*prate)
702 return 0;
703
704 pclk = omap3_find_clkoutx2_dpll(hw);
705
706 if (!pclk)
707 return 0;
708
709 dd = pclk->dpll_data;
710
711 /* TYPE J does not have a clkoutx2 */
712 if (dd->flags & DPLL_J_TYPE) {
713 *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate);
714 return *prate;
715 }
716
717 WARN_ON(!dd->enable_mask);
718
719 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
720 v >>= __ffs(dd->enable_mask);
721
722 /* If in bypass, the rate is fixed to the bypass rate*/
723 if (v != OMAP3XXX_EN_DPLL_LOCKED)
724 return *prate;
725
726 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
727 unsigned long best_parent;
728
729 best_parent = (rate / 2);
730 *prate = __clk_round_rate(__clk_get_parent(hw->clk),
731 best_parent);
732 }
733
734 return *prate * 2;
735}
736
672/* OMAP3/4 non-CORE DPLL clkops */ 737/* OMAP3/4 non-CORE DPLL clkops */
673const struct clk_hw_omap_ops clkhwops_omap3_dpll = { 738const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
674 .allow_idle = omap3_dpll_allow_idle, 739 .allow_idle = omap3_dpll_allow_idle,
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index d28b0f726715..52f9438b92f2 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
42 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : 42 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
43 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; 43 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
44 44
45 v = __raw_readl(clk->clksel_reg); 45 v = omap2_clk_readl(clk, clk->clksel_reg);
46 v &= mask; 46 v &= mask;
47 v >>= __ffs(mask); 47 v >>= __ffs(mask);
48 48
@@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
61 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : 61 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
62 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; 62 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
63 63
64 v = __raw_readl(clk->clksel_reg); 64 v = omap2_clk_readl(clk, clk->clksel_reg);
65 /* Clear the bit to allow gatectrl */ 65 /* Clear the bit to allow gatectrl */
66 v &= ~mask; 66 v &= ~mask;
67 __raw_writel(v, clk->clksel_reg); 67 omap2_clk_writel(v, clk, clk->clksel_reg);
68} 68}
69 69
70void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) 70void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
@@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
79 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : 79 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
80 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; 80 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
81 81
82 v = __raw_readl(clk->clksel_reg); 82 v = omap2_clk_readl(clk, clk->clksel_reg);
83 /* Set the bit to deny gatectrl */ 83 /* Set the bit to deny gatectrl */
84 v |= mask; 84 v |= mask;
85 __raw_writel(v, clk->clksel_reg); 85 omap2_clk_writel(v, clk, clk->clksel_reg);
86} 86}
87 87
88const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { 88const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
@@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
140 rate = omap2_get_dpll_rate(clk); 140 rate = omap2_get_dpll_rate(clk);
141 141
142 /* regm4xen adds a multiplier of 4 to DPLL calculations */ 142 /* regm4xen adds a multiplier of 4 to DPLL calculations */
143 v = __raw_readl(dd->control_reg); 143 v = omap2_clk_readl(clk, dd->control_reg);
144 if (v & OMAP4430_DPLL_REGM4XEN_MASK) 144 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
145 rate *= OMAP4430_REGM4XEN_MULT; 145 rate *= OMAP4430_REGM4XEN_MULT;
146 146
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 662c7fd633cc..174caecc3186 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -65,6 +65,22 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
65 return 1; 65 return 1;
66} 66}
67 67
68/* This function will go away once the device-tree convertion is complete */
69static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data,
70 struct gpmc_settings *s)
71{
72 /* Enable RD PIN Monitoring Reg */
73 if (gpmc_nand_data->dev_ready) {
74 s->wait_on_read = true;
75 s->wait_on_write = true;
76 }
77
78 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
79 s->device_width = GPMC_DEVWIDTH_16BIT;
80 else
81 s->device_width = GPMC_DEVWIDTH_8BIT;
82}
83
68int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, 84int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
69 struct gpmc_timings *gpmc_t) 85 struct gpmc_timings *gpmc_t)
70{ 86{
@@ -98,32 +114,22 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
98 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 114 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
99 return err; 115 return err;
100 } 116 }
117 }
101 118
102 if (gpmc_nand_data->of_node) { 119 if (gpmc_nand_data->of_node)
103 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); 120 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
104 } else { 121 else
105 /* Enable RD PIN Monitoring Reg */ 122 gpmc_set_legacy(gpmc_nand_data, &s);
106 if (gpmc_nand_data->dev_ready) {
107 s.wait_on_read = true;
108 s.wait_on_write = true;
109 }
110 }
111
112 s.device_nand = true;
113 123
114 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) 124 s.device_nand = true;
115 s.device_width = GPMC_DEVWIDTH_16BIT;
116 else
117 s.device_width = GPMC_DEVWIDTH_8BIT;
118 125
119 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); 126 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
120 if (err < 0) 127 if (err < 0)
121 goto out_free_cs; 128 goto out_free_cs;
122 129
123 err = gpmc_configure(GPMC_CONFIG_WP, 0); 130 err = gpmc_configure(GPMC_CONFIG_WP, 0);
124 if (err < 0) 131 if (err < 0)
125 goto out_free_cs; 132 goto out_free_cs;
126 }
127 133
128 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); 134 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
129 135
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index d24926e6340f..ab43755364f5 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1339,7 +1339,7 @@ static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1339 of_property_read_bool(np, "gpmc,time-para-granularity"); 1339 of_property_read_bool(np, "gpmc,time-para-granularity");
1340} 1340}
1341 1341
1342#ifdef CONFIG_MTD_NAND 1342#if IS_ENABLED(CONFIG_MTD_NAND)
1343 1343
1344static const char * const nand_xfer_types[] = { 1344static const char * const nand_xfer_types[] = {
1345 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", 1345 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
@@ -1429,7 +1429,7 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
1429} 1429}
1430#endif 1430#endif
1431 1431
1432#ifdef CONFIG_MTD_ONENAND 1432#if IS_ENABLED(CONFIG_MTD_ONENAND)
1433static int gpmc_probe_onenand_child(struct platform_device *pdev, 1433static int gpmc_probe_onenand_child(struct platform_device *pdev,
1434 struct device_node *child) 1434 struct device_node *child)
1435{ 1435{
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index cd22262a2cc0..af432b191255 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,10 +55,10 @@
55#include "prm44xx.h" 55#include "prm44xx.h"
56 56
57/* 57/*
58 * omap_clk_init: points to a function that does the SoC-specific 58 * omap_clk_soc_init: points to a function that does the SoC-specific
59 * clock initializations 59 * clock initializations
60 */ 60 */
61int (*omap_clk_init)(void); 61static int (*omap_clk_soc_init)(void);
62 62
63/* 63/*
64 * The machine specific code may provide the extra mapping besides the 64 * The machine specific code may provide the extra mapping besides the
@@ -179,15 +179,6 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
179 .length = L4_EMU_34XX_SIZE, 179 .length = L4_EMU_34XX_SIZE,
180 .type = MT_DEVICE 180 .type = MT_DEVICE
181 }, 181 },
182#if defined(CONFIG_DEBUG_LL) && \
183 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
184 {
185 .virtual = ZOOM_UART_VIRT,
186 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
187 .length = SZ_1M,
188 .type = MT_DEVICE
189 },
190#endif
191}; 182};
192#endif 183#endif
193 184
@@ -244,7 +235,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
244 .virtual = OMAP4_SRAM_VA, 235 .virtual = OMAP4_SRAM_VA,
245 .pfn = __phys_to_pfn(OMAP4_SRAM_PA), 236 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
246 .length = PAGE_SIZE, 237 .length = PAGE_SIZE,
247 .type = MT_MEMORY_SO, 238 .type = MT_MEMORY_RW_SO,
248 }, 239 },
249#endif 240#endif
250 241
@@ -282,7 +273,7 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
282 .virtual = OMAP4_SRAM_VA, 273 .virtual = OMAP4_SRAM_VA,
283 .pfn = __phys_to_pfn(OMAP4_SRAM_PA), 274 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
284 .length = PAGE_SIZE, 275 .length = PAGE_SIZE,
285 .type = MT_MEMORY_SO, 276 .type = MT_MEMORY_RW_SO,
286 }, 277 },
287#endif 278#endif
288}; 279};
@@ -419,7 +410,7 @@ void __init omap2420_init_early(void)
419 omap242x_clockdomains_init(); 410 omap242x_clockdomains_init();
420 omap2420_hwmod_init(); 411 omap2420_hwmod_init();
421 omap_hwmod_init_postsetup(); 412 omap_hwmod_init_postsetup();
422 omap_clk_init = omap2420_clk_init; 413 omap_clk_soc_init = omap2420_clk_init;
423} 414}
424 415
425void __init omap2420_init_late(void) 416void __init omap2420_init_late(void)
@@ -448,7 +439,7 @@ void __init omap2430_init_early(void)
448 omap243x_clockdomains_init(); 439 omap243x_clockdomains_init();
449 omap2430_hwmod_init(); 440 omap2430_hwmod_init();
450 omap_hwmod_init_postsetup(); 441 omap_hwmod_init_postsetup();
451 omap_clk_init = omap2430_clk_init; 442 omap_clk_soc_init = omap2430_clk_init;
452} 443}
453 444
454void __init omap2430_init_late(void) 445void __init omap2430_init_late(void)
@@ -482,27 +473,35 @@ void __init omap3_init_early(void)
482 omap3xxx_clockdomains_init(); 473 omap3xxx_clockdomains_init();
483 omap3xxx_hwmod_init(); 474 omap3xxx_hwmod_init();
484 omap_hwmod_init_postsetup(); 475 omap_hwmod_init_postsetup();
485 omap_clk_init = omap3xxx_clk_init; 476 omap_clk_soc_init = omap3xxx_clk_init;
486} 477}
487 478
488void __init omap3430_init_early(void) 479void __init omap3430_init_early(void)
489{ 480{
490 omap3_init_early(); 481 omap3_init_early();
482 if (of_have_populated_dt())
483 omap_clk_soc_init = omap3430_dt_clk_init;
491} 484}
492 485
493void __init omap35xx_init_early(void) 486void __init omap35xx_init_early(void)
494{ 487{
495 omap3_init_early(); 488 omap3_init_early();
489 if (of_have_populated_dt())
490 omap_clk_soc_init = omap3430_dt_clk_init;
496} 491}
497 492
498void __init omap3630_init_early(void) 493void __init omap3630_init_early(void)
499{ 494{
500 omap3_init_early(); 495 omap3_init_early();
496 if (of_have_populated_dt())
497 omap_clk_soc_init = omap3630_dt_clk_init;
501} 498}
502 499
503void __init am35xx_init_early(void) 500void __init am35xx_init_early(void)
504{ 501{
505 omap3_init_early(); 502 omap3_init_early();
503 if (of_have_populated_dt())
504 omap_clk_soc_init = am35xx_dt_clk_init;
506} 505}
507 506
508void __init ti81xx_init_early(void) 507void __init ti81xx_init_early(void)
@@ -520,7 +519,10 @@ void __init ti81xx_init_early(void)
520 omap3xxx_clockdomains_init(); 519 omap3xxx_clockdomains_init();
521 omap3xxx_hwmod_init(); 520 omap3xxx_hwmod_init();
522 omap_hwmod_init_postsetup(); 521 omap_hwmod_init_postsetup();
523 omap_clk_init = omap3xxx_clk_init; 522 if (of_have_populated_dt())
523 omap_clk_soc_init = ti81xx_dt_clk_init;
524 else
525 omap_clk_soc_init = omap3xxx_clk_init;
524} 526}
525 527
526void __init omap3_init_late(void) 528void __init omap3_init_late(void)
@@ -581,7 +583,7 @@ void __init am33xx_init_early(void)
581 am33xx_clockdomains_init(); 583 am33xx_clockdomains_init();
582 am33xx_hwmod_init(); 584 am33xx_hwmod_init();
583 omap_hwmod_init_postsetup(); 585 omap_hwmod_init_postsetup();
584 omap_clk_init = am33xx_clk_init; 586 omap_clk_soc_init = am33xx_dt_clk_init;
585} 587}
586 588
587void __init am33xx_init_late(void) 589void __init am33xx_init_late(void)
@@ -606,6 +608,7 @@ void __init am43xx_init_early(void)
606 am43xx_clockdomains_init(); 608 am43xx_clockdomains_init();
607 am43xx_hwmod_init(); 609 am43xx_hwmod_init();
608 omap_hwmod_init_postsetup(); 610 omap_hwmod_init_postsetup();
611 omap_clk_soc_init = am43xx_dt_clk_init;
609} 612}
610 613
611void __init am43xx_init_late(void) 614void __init am43xx_init_late(void)
@@ -629,13 +632,14 @@ void __init omap4430_init_early(void)
629 omap_cm_base_init(); 632 omap_cm_base_init();
630 omap4xxx_check_revision(); 633 omap4xxx_check_revision();
631 omap4xxx_check_features(); 634 omap4xxx_check_features();
635 omap4_pm_init_early();
632 omap44xx_prm_init(); 636 omap44xx_prm_init();
633 omap44xx_voltagedomains_init(); 637 omap44xx_voltagedomains_init();
634 omap44xx_powerdomains_init(); 638 omap44xx_powerdomains_init();
635 omap44xx_clockdomains_init(); 639 omap44xx_clockdomains_init();
636 omap44xx_hwmod_init(); 640 omap44xx_hwmod_init();
637 omap_hwmod_init_postsetup(); 641 omap_hwmod_init_postsetup();
638 omap_clk_init = omap4xxx_clk_init; 642 omap_clk_soc_init = omap4xxx_dt_clk_init;
639} 643}
640 644
641void __init omap4430_init_late(void) 645void __init omap4430_init_late(void)
@@ -666,6 +670,7 @@ void __init omap5_init_early(void)
666 omap54xx_clockdomains_init(); 670 omap54xx_clockdomains_init();
667 omap54xx_hwmod_init(); 671 omap54xx_hwmod_init();
668 omap_hwmod_init_postsetup(); 672 omap_hwmod_init_postsetup();
673 omap_clk_soc_init = omap5xxx_dt_clk_init;
669} 674}
670 675
671void __init omap5_init_late(void) 676void __init omap5_init_late(void)
@@ -691,6 +696,7 @@ void __init dra7xx_init_early(void)
691 dra7xx_clockdomains_init(); 696 dra7xx_clockdomains_init();
692 dra7xx_hwmod_init(); 697 dra7xx_hwmod_init();
693 omap_hwmod_init_postsetup(); 698 omap_hwmod_init_postsetup();
699 omap_clk_soc_init = dra7xx_dt_clk_init;
694} 700}
695 701
696void __init dra7xx_init_late(void) 702void __init dra7xx_init_late(void)
@@ -710,3 +716,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
710 _omap2_init_reprogram_sdrc(); 716 _omap2_init_reprogram_sdrc();
711 } 717 }
712} 718}
719
720int __init omap_clk_init(void)
721{
722 int ret = 0;
723
724 if (!omap_clk_soc_init)
725 return 0;
726
727 ret = of_prcm_init();
728 if (!ret)
729 ret = omap_clk_soc_init();
730
731 return ret;
732}
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index c52d8b4a3e91..828e0db3d943 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -88,72 +88,3 @@ int omap_msdi_reset(struct omap_hwmod *oh)
88 88
89 return 0; 89 return 0;
90} 90}
91
92#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
93
94static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
95 *mmc_controller)
96{
97 if ((mmc_controller->slots[0].switch_pin > 0) && \
98 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
99 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
100 OMAP_PIN_INPUT_PULLUP);
101 if ((mmc_controller->slots[0].gpio_wp > 0) && \
102 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
103 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
104 OMAP_PIN_INPUT_PULLUP);
105
106 omap_mux_init_signal("sdmmc_cmd", 0);
107 omap_mux_init_signal("sdmmc_clki", 0);
108 omap_mux_init_signal("sdmmc_clko", 0);
109 omap_mux_init_signal("sdmmc_dat0", 0);
110 omap_mux_init_signal("sdmmc_dat_dir0", 0);
111 omap_mux_init_signal("sdmmc_cmd_dir", 0);
112 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
113 omap_mux_init_signal("sdmmc_dat1", 0);
114 omap_mux_init_signal("sdmmc_dat2", 0);
115 omap_mux_init_signal("sdmmc_dat3", 0);
116 omap_mux_init_signal("sdmmc_dat_dir1", 0);
117 omap_mux_init_signal("sdmmc_dat_dir2", 0);
118 omap_mux_init_signal("sdmmc_dat_dir3", 0);
119 }
120
121 /*
122 * Use internal loop-back in MMC/SDIO Module Input Clock
123 * selection
124 */
125 if (mmc_controller->slots[0].internal_clock) {
126 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
127 v |= (1 << 24);
128 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
129 }
130}
131
132void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
133{
134 struct platform_device *pdev;
135 struct omap_hwmod *oh;
136 int id = 0;
137 char *oh_name = "msdi1";
138 char *dev_name = "mmci-omap";
139
140 if (!mmc_data[0]) {
141 pr_err("%s fails: Incomplete platform data\n", __func__);
142 return;
143 }
144
145 omap242x_mmc_mux(mmc_data[0]);
146
147 oh = omap_hwmod_lookup(oh_name);
148 if (!oh) {
149 pr_err("Could not look up %s\n", oh_name);
150 return;
151 }
152 pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
153 sizeof(struct omap_mmc_platform_data));
154 if (IS_ERR(pdev))
155 WARN(1, "Can'd build omap_device for %s:%s.\n",
156 dev_name, oh->name);
157}
158
159#endif
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 16f78a990d04..a722330d4d53 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -7,8 +7,6 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9 9
10#include "mux2420.h"
11#include "mux2430.h"
12#include "mux34xx.h" 10#include "mux34xx.h"
13 11
14#define OMAP_MUX_TERMINATOR 0xffff 12#define OMAP_MUX_TERMINATOR 0xffff
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
deleted file mode 100644
index cf6de0971c6c..000000000000
--- a/arch/arm/mach-omap2/mux2420.c
+++ /dev/null
@@ -1,690 +0,0 @@
1/*
2 * Copyright (C) 2010 Nokia
3 * Copyright (C) 2010 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP2420_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap2420
42 */
43static struct omap_mux __initdata omap2420_muxmodes[] = {
44 _OMAP2420_MUXENTRY(CAM_D0, 54,
45 "cam_d0", "hw_dbg2", "sti_dout", "gpio_54",
46 NULL, NULL, "etk_d2", NULL),
47 _OMAP2420_MUXENTRY(CAM_D1, 53,
48 "cam_d1", "hw_dbg3", "sti_din", "gpio_53",
49 NULL, NULL, "etk_d3", NULL),
50 _OMAP2420_MUXENTRY(CAM_D2, 52,
51 "cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52",
52 NULL, NULL, "etk_d4", NULL),
53 _OMAP2420_MUXENTRY(CAM_D3, 51,
54 "cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51",
55 NULL, NULL, "etk_d5", NULL),
56 _OMAP2420_MUXENTRY(CAM_D4, 50,
57 "cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50",
58 NULL, NULL, "etk_d6", NULL),
59 _OMAP2420_MUXENTRY(CAM_D5, 49,
60 "cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49",
61 NULL, NULL, "etk_d7", NULL),
62 _OMAP2420_MUXENTRY(CAM_D6, 0,
63 "cam_d6", "hw_dbg8", NULL, NULL,
64 NULL, NULL, "etk_d8", NULL),
65 _OMAP2420_MUXENTRY(CAM_D7, 0,
66 "cam_d7", "hw_dbg9", NULL, NULL,
67 NULL, NULL, "etk_d9", NULL),
68 _OMAP2420_MUXENTRY(CAM_D8, 54,
69 "cam_d8", "hw_dbg10", NULL, "gpio_54",
70 NULL, NULL, "etk_d10", NULL),
71 _OMAP2420_MUXENTRY(CAM_D9, 53,
72 "cam_d9", "hw_dbg11", NULL, "gpio_53",
73 NULL, NULL, "etk_d11", NULL),
74 _OMAP2420_MUXENTRY(CAM_HS, 55,
75 "cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55",
76 NULL, NULL, "etk_d1", NULL),
77 _OMAP2420_MUXENTRY(CAM_LCLK, 57,
78 "cam_lclk", NULL, "mcbsp_clks", "gpio_57",
79 NULL, NULL, "etk_c1", NULL),
80 _OMAP2420_MUXENTRY(CAM_VS, 56,
81 "cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56",
82 NULL, NULL, "etk_d0", NULL),
83 _OMAP2420_MUXENTRY(CAM_XCLK, 0,
84 "cam_xclk", NULL, "sti_clk", NULL,
85 NULL, NULL, "etk_c2", NULL),
86 _OMAP2420_MUXENTRY(DSS_ACBIAS, 48,
87 "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
88 NULL, NULL, NULL, NULL),
89 _OMAP2420_MUXENTRY(DSS_DATA10, 40,
90 "dss_data10", NULL, NULL, "gpio_40",
91 NULL, NULL, NULL, NULL),
92 _OMAP2420_MUXENTRY(DSS_DATA11, 41,
93 "dss_data11", NULL, NULL, "gpio_41",
94 NULL, NULL, NULL, NULL),
95 _OMAP2420_MUXENTRY(DSS_DATA12, 42,
96 "dss_data12", NULL, NULL, "gpio_42",
97 NULL, NULL, NULL, NULL),
98 _OMAP2420_MUXENTRY(DSS_DATA13, 43,
99 "dss_data13", NULL, NULL, "gpio_43",
100 NULL, NULL, NULL, NULL),
101 _OMAP2420_MUXENTRY(DSS_DATA14, 44,
102 "dss_data14", NULL, NULL, "gpio_44",
103 NULL, NULL, NULL, NULL),
104 _OMAP2420_MUXENTRY(DSS_DATA15, 45,
105 "dss_data15", NULL, NULL, "gpio_45",
106 NULL, NULL, NULL, NULL),
107 _OMAP2420_MUXENTRY(DSS_DATA16, 46,
108 "dss_data16", NULL, NULL, "gpio_46",
109 NULL, NULL, NULL, NULL),
110 _OMAP2420_MUXENTRY(DSS_DATA17, 47,
111 "dss_data17", NULL, NULL, "gpio_47",
112 NULL, NULL, NULL, NULL),
113 _OMAP2420_MUXENTRY(DSS_DATA8, 38,
114 "dss_data8", NULL, NULL, "gpio_38",
115 NULL, NULL, NULL, NULL),
116 _OMAP2420_MUXENTRY(DSS_DATA9, 39,
117 "dss_data9", NULL, NULL, "gpio_39",
118 NULL, NULL, NULL, NULL),
119 _OMAP2420_MUXENTRY(EAC_AC_DIN, 115,
120 "eac_ac_din", "mcbsp2_dr", NULL, "gpio_115",
121 NULL, NULL, NULL, NULL),
122 _OMAP2420_MUXENTRY(EAC_AC_DOUT, 116,
123 "eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116",
124 NULL, NULL, NULL, NULL),
125 _OMAP2420_MUXENTRY(EAC_AC_FS, 114,
126 "eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114",
127 NULL, NULL, NULL, NULL),
128 _OMAP2420_MUXENTRY(EAC_AC_MCLK, 117,
129 "eac_ac_mclk", NULL, NULL, "gpio_117",
130 NULL, NULL, NULL, NULL),
131 _OMAP2420_MUXENTRY(EAC_AC_RST, 118,
132 "eac_ac_rst", "eac_bt_din", NULL, "gpio_118",
133 NULL, NULL, NULL, NULL),
134 _OMAP2420_MUXENTRY(EAC_AC_SCLK, 113,
135 "eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113",
136 NULL, NULL, NULL, NULL),
137 _OMAP2420_MUXENTRY(EAC_BT_DIN, 73,
138 "eac_bt_din", NULL, NULL, "gpio_73",
139 NULL, NULL, "etk_d9", NULL),
140 _OMAP2420_MUXENTRY(EAC_BT_DOUT, 74,
141 "eac_bt_dout", NULL, "sti_clk", "gpio_74",
142 NULL, NULL, "etk_d8", NULL),
143 _OMAP2420_MUXENTRY(EAC_BT_FS, 72,
144 "eac_bt_fs", NULL, NULL, "gpio_72",
145 NULL, NULL, "etk_d10", NULL),
146 _OMAP2420_MUXENTRY(EAC_BT_SCLK, 71,
147 "eac_bt_sclk", NULL, NULL, "gpio_71",
148 NULL, NULL, "etk_d11", NULL),
149 _OMAP2420_MUXENTRY(GPIO_119, 119,
150 "gpio_119", NULL, "sti_din", "gpio_119",
151 NULL, "sys_boot0", "etk_d12", NULL),
152 _OMAP2420_MUXENTRY(GPIO_120, 120,
153 "gpio_120", NULL, "sti_dout", "gpio_120",
154 "cam_d9", "sys_boot1", "etk_d13", NULL),
155 _OMAP2420_MUXENTRY(GPIO_121, 121,
156 "gpio_121", NULL, NULL, "gpio_121",
157 "jtag_emu2", "sys_boot2", "etk_d14", NULL),
158 _OMAP2420_MUXENTRY(GPIO_122, 122,
159 "gpio_122", NULL, NULL, "gpio_122",
160 "jtag_emu3", "sys_boot3", "etk_d15", NULL),
161 _OMAP2420_MUXENTRY(GPIO_124, 124,
162 "gpio_124", NULL, NULL, "gpio_124",
163 NULL, "sys_boot5", NULL, NULL),
164 _OMAP2420_MUXENTRY(GPIO_125, 125,
165 "gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125",
166 NULL, NULL, NULL, NULL),
167 _OMAP2420_MUXENTRY(GPIO_36, 36,
168 "gpio_36", NULL, NULL, "gpio_36",
169 NULL, "sys_boot4", NULL, NULL),
170 _OMAP2420_MUXENTRY(GPIO_62, 62,
171 "gpio_62", "uart1_rx", "usb1_dat", "gpio_62",
172 NULL, NULL, NULL, NULL),
173 _OMAP2420_MUXENTRY(GPIO_6, 6,
174 "gpio_6", "tv_detpulse", NULL, "gpio_6",
175 NULL, NULL, NULL, NULL),
176 _OMAP2420_MUXENTRY(GPMC_A10, 3,
177 "gpmc_a10", NULL, "sys_ndmareq5", "gpio_3",
178 NULL, NULL, NULL, NULL),
179 _OMAP2420_MUXENTRY(GPMC_A1, 12,
180 "gpmc_a1", "dss_data18", NULL, "gpio_12",
181 NULL, NULL, NULL, NULL),
182 _OMAP2420_MUXENTRY(GPMC_A2, 11,
183 "gpmc_a2", "dss_data19", NULL, "gpio_11",
184 NULL, NULL, NULL, NULL),
185 _OMAP2420_MUXENTRY(GPMC_A3, 10,
186 "gpmc_a3", "dss_data20", NULL, "gpio_10",
187 NULL, NULL, NULL, NULL),
188 _OMAP2420_MUXENTRY(GPMC_A4, 9,
189 "gpmc_a4", "dss_data21", NULL, "gpio_9",
190 NULL, NULL, NULL, NULL),
191 _OMAP2420_MUXENTRY(GPMC_A5, 8,
192 "gpmc_a5", "dss_data22", NULL, "gpio_8",
193 NULL, NULL, NULL, NULL),
194 _OMAP2420_MUXENTRY(GPMC_A6, 7,
195 "gpmc_a6", "dss_data23", NULL, "gpio_7",
196 NULL, NULL, NULL, NULL),
197 _OMAP2420_MUXENTRY(GPMC_A7, 6,
198 "gpmc_a7", NULL, "sys_ndmareq2", "gpio_6",
199 NULL, NULL, NULL, NULL),
200 _OMAP2420_MUXENTRY(GPMC_A8, 5,
201 "gpmc_a8", NULL, "sys_ndmareq3", "gpio_5",
202 NULL, NULL, NULL, NULL),
203 _OMAP2420_MUXENTRY(GPMC_A9, 4,
204 "gpmc_a9", NULL, "sys_ndmareq4", "gpio_4",
205 NULL, NULL, NULL, NULL),
206 _OMAP2420_MUXENTRY(GPMC_CLK, 21,
207 "gpmc_clk", NULL, NULL, "gpio_21",
208 NULL, NULL, NULL, NULL),
209 _OMAP2420_MUXENTRY(GPMC_D10, 18,
210 "gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18",
211 NULL, NULL, NULL, NULL),
212 _OMAP2420_MUXENTRY(GPMC_D11, 17,
213 "gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17",
214 NULL, NULL, NULL, NULL),
215 _OMAP2420_MUXENTRY(GPMC_D12, 16,
216 "gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16",
217 NULL, NULL, NULL, NULL),
218 _OMAP2420_MUXENTRY(GPMC_D13, 15,
219 "gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15",
220 NULL, NULL, NULL, NULL),
221 _OMAP2420_MUXENTRY(GPMC_D14, 14,
222 "gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14",
223 NULL, NULL, NULL, NULL),
224 _OMAP2420_MUXENTRY(GPMC_D15, 13,
225 "gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13",
226 NULL, NULL, NULL, NULL),
227 _OMAP2420_MUXENTRY(GPMC_D8, 20,
228 "gpmc_d8", NULL, NULL, "gpio_20",
229 NULL, NULL, NULL, NULL),
230 _OMAP2420_MUXENTRY(GPMC_D9, 19,
231 "gpmc_d9", "ssi2_wake", NULL, "gpio_19",
232 NULL, NULL, NULL, NULL),
233 _OMAP2420_MUXENTRY(GPMC_NBE0, 29,
234 "gpmc_nbe0", NULL, NULL, "gpio_29",
235 NULL, NULL, NULL, NULL),
236 _OMAP2420_MUXENTRY(GPMC_NBE1, 30,
237 "gpmc_nbe1", NULL, NULL, "gpio_30",
238 NULL, NULL, NULL, NULL),
239 _OMAP2420_MUXENTRY(GPMC_NCS1, 22,
240 "gpmc_ncs1", NULL, NULL, "gpio_22",
241 NULL, NULL, NULL, NULL),
242 _OMAP2420_MUXENTRY(GPMC_NCS2, 23,
243 "gpmc_ncs2", NULL, NULL, "gpio_23",
244 NULL, NULL, NULL, NULL),
245 _OMAP2420_MUXENTRY(GPMC_NCS3, 24,
246 "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
247 NULL, NULL, NULL, NULL),
248 _OMAP2420_MUXENTRY(GPMC_NCS4, 25,
249 "gpmc_ncs4", NULL, NULL, "gpio_25",
250 NULL, NULL, NULL, NULL),
251 _OMAP2420_MUXENTRY(GPMC_NCS5, 26,
252 "gpmc_ncs5", NULL, NULL, "gpio_26",
253 NULL, NULL, NULL, NULL),
254 _OMAP2420_MUXENTRY(GPMC_NCS6, 27,
255 "gpmc_ncs6", NULL, NULL, "gpio_27",
256 NULL, NULL, NULL, NULL),
257 _OMAP2420_MUXENTRY(GPMC_NCS7, 28,
258 "gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL,
259 NULL, NULL, NULL, NULL),
260 _OMAP2420_MUXENTRY(GPMC_NWP, 31,
261 "gpmc_nwp", NULL, NULL, "gpio_31",
262 NULL, NULL, NULL, NULL),
263 _OMAP2420_MUXENTRY(GPMC_WAIT1, 33,
264 "gpmc_wait1", NULL, NULL, "gpio_33",
265 NULL, NULL, NULL, NULL),
266 _OMAP2420_MUXENTRY(GPMC_WAIT2, 34,
267 "gpmc_wait2", NULL, NULL, "gpio_34",
268 NULL, NULL, NULL, NULL),
269 _OMAP2420_MUXENTRY(GPMC_WAIT3, 35,
270 "gpmc_wait3", NULL, NULL, "gpio_35",
271 NULL, NULL, NULL, NULL),
272 _OMAP2420_MUXENTRY(HDQ_SIO, 101,
273 "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
274 NULL, NULL, NULL, NULL),
275 _OMAP2420_MUXENTRY(I2C2_SCL, 99,
276 "i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99",
277 NULL, NULL, NULL, NULL),
278 _OMAP2420_MUXENTRY(I2C2_SDA, 100,
279 "i2c2_sda", NULL, "spi2_ncs1", "gpio_100",
280 NULL, NULL, NULL, NULL),
281 _OMAP2420_MUXENTRY(JTAG_EMU0, 127,
282 "jtag_emu0", NULL, NULL, "gpio_127",
283 NULL, NULL, NULL, NULL),
284 _OMAP2420_MUXENTRY(JTAG_EMU1, 126,
285 "jtag_emu1", NULL, NULL, "gpio_126",
286 NULL, NULL, NULL, NULL),
287 _OMAP2420_MUXENTRY(MCBSP1_CLKR, 92,
288 "mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92",
289 NULL, NULL, NULL, NULL),
290 _OMAP2420_MUXENTRY(MCBSP1_CLKX, 98,
291 "mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98",
292 NULL, NULL, NULL, NULL),
293 _OMAP2420_MUXENTRY(MCBSP1_DR, 95,
294 "mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95",
295 NULL, NULL, NULL, NULL),
296 _OMAP2420_MUXENTRY(MCBSP1_DX, 94,
297 "mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94",
298 NULL, NULL, NULL, NULL),
299 _OMAP2420_MUXENTRY(MCBSP1_FSR, 93,
300 "mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93",
301 "spi2_ncs1", NULL, NULL, NULL),
302 _OMAP2420_MUXENTRY(MCBSP1_FSX, 97,
303 "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
304 NULL, NULL, NULL, NULL),
305 _OMAP2420_MUXENTRY(MCBSP2_CLKX, 12,
306 "mcbsp2_clkx", NULL, "dss_data23", "gpio_12",
307 NULL, NULL, NULL, NULL),
308 _OMAP2420_MUXENTRY(MCBSP2_DR, 11,
309 "mcbsp2_dr", NULL, "dss_data22", "gpio_11",
310 NULL, NULL, NULL, NULL),
311 _OMAP2420_MUXENTRY(MCBSP_CLKS, 96,
312 "mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96",
313 NULL, NULL, NULL, NULL),
314 _OMAP2420_MUXENTRY(MMC_CLKI, 59,
315 "sdmmc_clki", "ms_clki", NULL, "gpio_59",
316 NULL, NULL, NULL, NULL),
317 _OMAP2420_MUXENTRY(MMC_CLKO, 0,
318 "sdmmc_clko", "ms_clko", NULL, NULL,
319 NULL, NULL, NULL, NULL),
320 _OMAP2420_MUXENTRY(MMC_CMD_DIR, 8,
321 "sdmmc_cmd_dir", NULL, NULL, "gpio_8",
322 NULL, NULL, NULL, NULL),
323 _OMAP2420_MUXENTRY(MMC_CMD, 0,
324 "sdmmc_cmd", "ms_bs", NULL, NULL,
325 NULL, NULL, NULL, NULL),
326 _OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7,
327 "sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7",
328 NULL, NULL, NULL, NULL),
329 _OMAP2420_MUXENTRY(MMC_DAT0, 0,
330 "sdmmc_dat0", "ms_dat0", NULL, NULL,
331 NULL, NULL, NULL, NULL),
332 _OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78,
333 "sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78",
334 NULL, NULL, NULL, NULL),
335 _OMAP2420_MUXENTRY(MMC_DAT1, 75,
336 "sdmmc_dat1", "ms_dat1", NULL, "gpio_75",
337 NULL, NULL, NULL, NULL),
338 _OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79,
339 "sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79",
340 NULL, NULL, NULL, NULL),
341 _OMAP2420_MUXENTRY(MMC_DAT2, 76,
342 "sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76",
343 NULL, NULL, NULL, NULL),
344 _OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80,
345 "sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80",
346 NULL, NULL, NULL, NULL),
347 _OMAP2420_MUXENTRY(MMC_DAT3, 77,
348 "sdmmc_dat3", "ms_dat3", NULL, "gpio_77",
349 NULL, NULL, NULL, NULL),
350 _OMAP2420_MUXENTRY(SDRC_A12, 2,
351 "sdrc_a12", NULL, NULL, "gpio_2",
352 NULL, NULL, NULL, NULL),
353 _OMAP2420_MUXENTRY(SDRC_A13, 1,
354 "sdrc_a13", NULL, NULL, "gpio_1",
355 NULL, NULL, NULL, NULL),
356 _OMAP2420_MUXENTRY(SDRC_A14, 0,
357 "sdrc_a14", NULL, NULL, "gpio_0",
358 NULL, NULL, NULL, NULL),
359 _OMAP2420_MUXENTRY(SDRC_CKE1, 38,
360 "sdrc_cke1", NULL, NULL, "gpio_38",
361 NULL, NULL, NULL, NULL),
362 _OMAP2420_MUXENTRY(SDRC_NCS1, 37,
363 "sdrc_ncs1", NULL, NULL, "gpio_37",
364 NULL, NULL, NULL, NULL),
365 _OMAP2420_MUXENTRY(SPI1_CLK, 81,
366 "spi1_clk", NULL, NULL, "gpio_81",
367 NULL, NULL, NULL, NULL),
368 _OMAP2420_MUXENTRY(SPI1_NCS0, 84,
369 "spi1_ncs0", NULL, NULL, "gpio_84",
370 NULL, NULL, NULL, NULL),
371 _OMAP2420_MUXENTRY(SPI1_NCS1, 85,
372 "spi1_ncs1", NULL, NULL, "gpio_85",
373 NULL, NULL, NULL, NULL),
374 _OMAP2420_MUXENTRY(SPI1_NCS2, 86,
375 "spi1_ncs2", NULL, NULL, "gpio_86",
376 NULL, NULL, NULL, NULL),
377 _OMAP2420_MUXENTRY(SPI1_NCS3, 87,
378 "spi1_ncs3", NULL, NULL, "gpio_87",
379 NULL, NULL, NULL, NULL),
380 _OMAP2420_MUXENTRY(SPI1_SIMO, 82,
381 "spi1_simo", NULL, NULL, "gpio_82",
382 NULL, NULL, NULL, NULL),
383 _OMAP2420_MUXENTRY(SPI1_SOMI, 83,
384 "spi1_somi", NULL, NULL, "gpio_83",
385 NULL, NULL, NULL, NULL),
386 _OMAP2420_MUXENTRY(SPI2_CLK, 88,
387 "spi2_clk", NULL, NULL, "gpio_88",
388 NULL, NULL, NULL, NULL),
389 _OMAP2420_MUXENTRY(SPI2_NCS0, 91,
390 "spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91",
391 NULL, NULL, NULL, NULL),
392 _OMAP2420_MUXENTRY(SPI2_SIMO, 89,
393 "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
394 NULL, NULL, NULL, NULL),
395 _OMAP2420_MUXENTRY(SPI2_SOMI, 90,
396 "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
397 NULL, NULL, NULL, NULL),
398 _OMAP2420_MUXENTRY(SSI1_DAT_RX, 63,
399 "ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63",
400 NULL, NULL, NULL, NULL),
401 _OMAP2420_MUXENTRY(SSI1_DAT_TX, 59,
402 "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
403 NULL, NULL, NULL, NULL),
404 _OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64,
405 "ssi1_flag_rx", "eac_md_din", NULL, "gpio_64",
406 NULL, NULL, NULL, NULL),
407 _OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25,
408 "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25",
409 NULL, NULL, NULL, NULL),
410 _OMAP2420_MUXENTRY(SSI1_RDY_RX, 65,
411 "ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65",
412 NULL, NULL, NULL, NULL),
413 _OMAP2420_MUXENTRY(SSI1_RDY_TX, 61,
414 "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
415 NULL, NULL, NULL, NULL),
416 _OMAP2420_MUXENTRY(SSI1_WAKE, 66,
417 "ssi1_wake", "eac_md_fs", NULL, "gpio_66",
418 NULL, NULL, NULL, NULL),
419 _OMAP2420_MUXENTRY(SYS_CLKOUT, 123,
420 "sys_clkout", NULL, NULL, "gpio_123",
421 NULL, NULL, NULL, NULL),
422 _OMAP2420_MUXENTRY(SYS_CLKREQ, 52,
423 "sys_clkreq", NULL, NULL, "gpio_52",
424 NULL, NULL, NULL, NULL),
425 _OMAP2420_MUXENTRY(SYS_NIRQ, 60,
426 "sys_nirq", NULL, NULL, "gpio_60",
427 NULL, NULL, NULL, NULL),
428 _OMAP2420_MUXENTRY(UART1_CTS, 32,
429 "uart1_cts", NULL, "dss_data18", "gpio_32",
430 NULL, NULL, NULL, NULL),
431 _OMAP2420_MUXENTRY(UART1_RTS, 8,
432 "uart1_rts", NULL, "dss_data19", "gpio_8",
433 NULL, NULL, NULL, NULL),
434 _OMAP2420_MUXENTRY(UART1_RX, 10,
435 "uart1_rx", NULL, "dss_data21", "gpio_10",
436 NULL, NULL, NULL, NULL),
437 _OMAP2420_MUXENTRY(UART1_TX, 9,
438 "uart1_tx", NULL, "dss_data20", "gpio_9",
439 NULL, NULL, NULL, NULL),
440 _OMAP2420_MUXENTRY(UART2_CTS, 67,
441 "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
442 NULL, NULL, NULL, NULL),
443 _OMAP2420_MUXENTRY(UART2_RTS, 68,
444 "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
445 NULL, NULL, NULL, NULL),
446 _OMAP2420_MUXENTRY(UART2_RX, 70,
447 "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
448 NULL, NULL, NULL, NULL),
449 _OMAP2420_MUXENTRY(UART2_TX, 69,
450 "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
451 NULL, NULL, NULL, NULL),
452 _OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102,
453 "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
454 NULL, NULL, NULL, NULL),
455 _OMAP2420_MUXENTRY(UART3_RTS_SD, 103,
456 "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
457 NULL, NULL, NULL, NULL),
458 _OMAP2420_MUXENTRY(UART3_RX_IRRX, 105,
459 "uart3_rx_irrx", NULL, NULL, "gpio_105",
460 NULL, NULL, NULL, NULL),
461 _OMAP2420_MUXENTRY(UART3_TX_IRTX, 104,
462 "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
463 NULL, NULL, NULL, NULL),
464 _OMAP2420_MUXENTRY(USB0_DAT, 112,
465 "usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112",
466 "uart2_tx", NULL, NULL, NULL),
467 _OMAP2420_MUXENTRY(USB0_PUEN, 106,
468 "usb0_puen", "mcbsp2_dx", NULL, "gpio_106",
469 NULL, NULL, NULL, NULL),
470 _OMAP2420_MUXENTRY(USB0_RCV, 109,
471 "usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109",
472 "uart2_cts", NULL, NULL, NULL),
473 _OMAP2420_MUXENTRY(USB0_SE0, 111,
474 "usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111",
475 "uart2_rx", NULL, NULL, NULL),
476 _OMAP2420_MUXENTRY(USB0_TXEN, 110,
477 "usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110",
478 NULL, NULL, NULL, NULL),
479 _OMAP2420_MUXENTRY(USB0_VM, 108,
480 "usb0_vm", "mcbsp2_clkx", NULL, "gpio_108",
481 "uart2_rx", NULL, NULL, NULL),
482 _OMAP2420_MUXENTRY(USB0_VP, 107,
483 "usb0_vp", "mcbsp2_dr", NULL, "gpio_107",
484 NULL, NULL, NULL, NULL),
485 _OMAP2420_MUXENTRY(VLYNQ_CLK, 13,
486 "vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13",
487 NULL, NULL, NULL, NULL),
488 _OMAP2420_MUXENTRY(VLYNQ_NLA, 58,
489 "vlynq_nla", NULL, NULL, "gpio_58",
490 "cam_d6", NULL, NULL, NULL),
491 _OMAP2420_MUXENTRY(VLYNQ_RX0, 15,
492 "vlynq_rx0", "usb2_tllse0", NULL, "gpio_15",
493 "cam_d7", NULL, NULL, NULL),
494 _OMAP2420_MUXENTRY(VLYNQ_RX1, 14,
495 "vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14",
496 "cam_d8", NULL, NULL, NULL),
497 _OMAP2420_MUXENTRY(VLYNQ_TX0, 17,
498 "vlynq_tx0", "usb2_txen", NULL, "gpio_17",
499 NULL, NULL, NULL, NULL),
500 _OMAP2420_MUXENTRY(VLYNQ_TX1, 16,
501 "vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16",
502 NULL, NULL, NULL, NULL),
503 { .reg_offset = OMAP_MUX_TERMINATOR },
504};
505
506/*
507 * Balls for 447-pin POP package
508 */
509#ifdef CONFIG_DEBUG_FS
510static struct omap_ball __initdata omap2420_pop_ball[] = {
511 _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
512 _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
513 _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
514 _OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL),
515 _OMAP2420_BALLENTRY(CAM_D4, "v2", NULL),
516 _OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL),
517 _OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL),
518 _OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL),
519 _OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL),
520 _OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL),
521 _OMAP2420_BALLENTRY(CAM_HS, "v4", NULL),
522 _OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL),
523 _OMAP2420_BALLENTRY(CAM_VS, "p7", NULL),
524 _OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL),
525 _OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL),
526 _OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL),
527 _OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL),
528 _OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL),
529 _OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL),
530 _OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL),
531 _OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL),
532 _OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL),
533 _OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL),
534 _OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL),
535 _OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL),
536 _OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL),
537 _OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL),
538 _OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL),
539 _OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL),
540 _OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL),
541 _OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL),
542 _OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL),
543 _OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL),
544 _OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL),
545 _OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL),
546 _OMAP2420_BALLENTRY(GPIO_119, "af6", NULL),
547 _OMAP2420_BALLENTRY(GPIO_120, "af4", NULL),
548 _OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL),
549 _OMAP2420_BALLENTRY(GPIO_122, "w3", NULL),
550 _OMAP2420_BALLENTRY(GPIO_124, "y19", NULL),
551 _OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL),
552 _OMAP2420_BALLENTRY(GPIO_36, "y18", NULL),
553 _OMAP2420_BALLENTRY(GPIO_6, "d6", NULL),
554 _OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL),
555 _OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL),
556 _OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL),
557 _OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL),
558 _OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL),
559 _OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL),
560 _OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL),
561 _OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL),
562 _OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL),
563 _OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL),
564 _OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL),
565 _OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"),
566 _OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"),
567 _OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"),
568 _OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"),
569 _OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"),
570 _OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"),
571 _OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"),
572 _OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"),
573 _OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"),
574 _OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"),
575 _OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL),
576 _OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"),
577 _OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL),
578 _OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL),
579 _OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL),
580 _OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL),
581 _OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL),
582 _OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL),
583 _OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"),
584 _OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"),
585 _OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL),
586 _OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL),
587 _OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL),
588 _OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL),
589 _OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL),
590 _OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL),
591 _OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL),
592 _OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL),
593 _OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL),
594 _OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL),
595 _OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL),
596 _OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL),
597 _OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL),
598 _OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL),
599 _OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL),
600 _OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL),
601 _OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL),
602 _OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL),
603 _OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL),
604 _OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL),
605 _OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL),
606 _OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL),
607 _OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL),
608 _OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL),
609 _OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL),
610 _OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL),
611 _OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL),
612 _OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL),
613 _OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"),
614 _OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"),
615 _OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"),
616 _OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"),
617 _OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"),
618 _OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL),
619 _OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL),
620 _OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL),
621 _OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL),
622 _OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL),
623 _OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL),
624 _OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL),
625 _OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL),
626 _OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL),
627 _OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL),
628 _OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL),
629 _OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL),
630 _OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL),
631 _OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL),
632 _OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL),
633 _OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL),
634 _OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL),
635 _OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL),
636 _OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL),
637 _OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL),
638 _OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL),
639 _OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL),
640 _OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL),
641 _OMAP2420_BALLENTRY(UART1_RX, "t20", NULL),
642 _OMAP2420_BALLENTRY(UART1_TX, "h12", NULL),
643 _OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL),
644 _OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL),
645 _OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL),
646 _OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL),
647 _OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL),
648 _OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL),
649 _OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
650 _OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
651 _OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL),
652 _OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL),
653 _OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL),
654 _OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL),
655 _OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL),
656 _OMAP2420_BALLENTRY(USB0_VM, "n23", NULL),
657 _OMAP2420_BALLENTRY(USB0_VP, "m23", NULL),
658 _OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL),
659 _OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL),
660 _OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL),
661 _OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL),
662 _OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL),
663 _OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL),
664 { .reg_offset = OMAP_MUX_TERMINATOR },
665};
666#else
667#define omap2420_pop_ball NULL
668#endif
669
670int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
671{
672 struct omap_ball *package_balls = NULL;
673
674 switch (flags & OMAP_PACKAGE_MASK) {
675 case OMAP_PACKAGE_ZAC:
676 package_balls = omap2420_pop_ball;
677 break;
678 case OMAP_PACKAGE_ZAF:
679 /* REVISIT: Please add data */
680 default:
681 pr_warning("%s: No ball data available for omap2420 package\n",
682 __func__);
683 }
684
685 return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
686 OMAP2420_CONTROL_PADCONF_MUX_PBASE,
687 OMAP2420_CONTROL_PADCONF_MUX_SIZE,
688 omap2420_muxmodes, NULL, board_subset,
689 package_balls);
690}
diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h
deleted file mode 100644
index 0f555aa847b5..000000000000
--- a/arch/arm/mach-omap2/mux2420.h
+++ /dev/null
@@ -1,282 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP2420_CONTROL_PADCONF_MUX_PBASE 0x48000030LU
11
12#define OMAP2420_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x48000030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 8-bits wide.
24 */
25#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET 0x000
26#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET 0x001
27#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET 0x002
28#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x003
29#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x004
30#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET 0x005
31#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET 0x006
32#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET 0x007
33#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET 0x008
34#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET 0x009
35#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET 0x00a
36#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET 0x00b
37#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET 0x00c
38#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET 0x00d
39#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET 0x00e
40#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET 0x00f
41#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET 0x010
42#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET 0x021
43#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET 0x022
44#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET 0x023
45#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET 0x024
46#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET 0x025
47#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET 0x026
48#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET 0x027
49#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET 0x028
50#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET 0x029
51#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02a
52#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02b
53#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET 0x02c
54#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET 0x02d
55#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET 0x02e
56#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET 0x02f
57#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET 0x030
58#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET 0x031
59#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET 0x032
60#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET 0x033
61#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET 0x034
62#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET 0x035
63#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET 0x036
64#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET 0x037
65#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET 0x038
66#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET 0x039
67#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET 0x03a
68#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET 0x03b
69#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET 0x03c
70#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET 0x03d
71#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET 0x03e
72#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET 0x03f
73#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET 0x040
74#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET 0x041
75#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET 0x042
76#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET 0x043
77#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET 0x044
78#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET 0x045
79#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET 0x046
80#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET 0x047
81#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET 0x048
82#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET 0x049
83#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
84#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET 0x04b
85#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET 0x04c
86#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET 0x04d
87#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET 0x04e
88#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET 0x04f
89#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET 0x050
90#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET 0x051
91#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET 0x052
92#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET 0x053
93#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET 0x054
94#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET 0x055
95#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET 0x056
96#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET 0x057
97#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET 0x058
98#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET 0x059
99#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05a
100#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x05b
101#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x05c
102#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x05d
103#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x05e
104#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x05f
105#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x060
106#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x061
107#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x062
108#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x063
109#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET 0x064
110#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x065
111#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x066
112#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET 0x067
113#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x068
114#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x069
115#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x06a
116#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x06b
117#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x06c
118#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x06d
119#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x06e
120#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x06f
121#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x070
122#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x071
123#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x072
124#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x073
125#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x074
126#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x075
127#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x076
128#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x077
129#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x078
130#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x079
131#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x07a
132#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x07f
133#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x080
134#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x081
135#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x082
136#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x083
137#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x084
138#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x085
139#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x086
140#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x087
141#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x088
142#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x089
143#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x08a
144#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x08b
145#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x08c
146#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x08d
147#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x08e
148#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x08f
149#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x090
150#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x091
151#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x092
152#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x093
153#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x094
154#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET 0x095
155#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET 0x096
156#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET 0x097
157#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET 0x098
158#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x099
159#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x09a
160#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET 0x09b
161#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x09c
162#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x09d
163#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x09e
164#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET 0x09f
165#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a0
166#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a1
167#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a2
168#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a3
169#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a4
170#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET 0x0a5
171#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET 0x0a6
172#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET 0x0a7
173#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET 0x0a8
174#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET 0x0a9
175#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET 0x0aa
176#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0ab
177#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0ac
178#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0ad
179#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0ae
180#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0af
181#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET 0x0b0
182#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0b1
183#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0b2
184#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0b3
185#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0b4
186#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET 0x0b5
187#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET 0x0b6
188#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET 0x0b7
189#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET 0x0b8
190#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET 0x0b9
191#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET 0x0ba
192#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0bb
193#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0bc
194#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET 0x0bd
195#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET 0x0be
196#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET 0x0bf
197#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET 0x0c0
198#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET 0x0c1
199#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET 0x0c2
200#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET 0x0c3
201#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET 0x0c4
202#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET 0x0c5
203#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET 0x0c6
204#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET 0x0c7
205#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET 0x0c8
206#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET 0x0c9
207#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET 0x0ca
208#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET 0x0cb
209#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET 0x0cc
210#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET 0x0cd
211#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET 0x0ce
212#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0cf
213#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0d0
214#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0d1
215#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET 0x0d2
216#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET 0x0d3
217#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET 0x0d4
218#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET 0x0d5
219#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0d6
220#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0d7
221#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0d8
222#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET 0x0d9
223#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0da
224#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0db
225#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0dc
226#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0dd
227#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0de
228#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0df
229#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0e0
230#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0e1
231#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0e2
232#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0e3
233#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0e4
234#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0e5
235#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0e6
236#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0e7
237#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0e8
238#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0e9
239#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET 0x0ea
240#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET 0x0eb
241#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET 0x0ec
242#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET 0x0ed
243#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET 0x0ee
244#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET 0x0ef
245#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET 0x0f0
246#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET 0x0f1
247#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET 0x0f2
248#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET 0x0f3
249#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET 0x0f4
250#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET 0x0f5
251#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET 0x0f6
252#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET 0x0f7
253#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET 0x0f8
254#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET 0x0f9
255#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x0fa
256#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x0fb
257#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x0fc
258#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET 0x0fd
259#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET 0x0fe
260#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET 0x0ff
261#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET 0x100
262#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET 0x101
263#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET 0x102
264#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x103
265#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x104
266#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET 0x105
267#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x106
268#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x107
269#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET 0x108
270#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET 0x109
271#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET 0x10a
272#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x10b
273#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x10c
274#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x10d
275#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x10e
276#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x10f
277#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x110
278#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x111
279#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x112
280
281#define OMAP2420_CONTROL_PADCONF_MUX_SIZE \
282 (OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1)
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
deleted file mode 100644
index 4185f92553db..000000000000
--- a/arch/arm/mach-omap2/mux2430.c
+++ /dev/null
@@ -1,793 +0,0 @@
1/*
2 * Copyright (C) 2010 Nokia
3 * Copyright (C) 2010 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "mux.h"
14
15#ifdef CONFIG_OMAP_MUX
16
17#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
18{ \
19 .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \
20 .gpio = (g), \
21 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
22}
23
24#else
25
26#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
27{ \
28 .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \
29 .gpio = (g), \
30}
31
32#endif
33
34#define _OMAP2430_BALLENTRY(M0, bb, bt) \
35{ \
36 .reg_offset = (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET), \
37 .balls = { bb, bt }, \
38}
39
40/*
41 * Superset of all mux modes for omap2430
42 */
43static struct omap_mux __initdata omap2430_muxmodes[] = {
44 _OMAP2430_MUXENTRY(CAM_D0, 133,
45 "cam_d0", "hw_dbg0", "sti_dout", "gpio_133",
46 NULL, NULL, "etk_d2", "safe_mode"),
47 _OMAP2430_MUXENTRY(CAM_D10, 146,
48 "cam_d10", NULL, NULL, "gpio_146",
49 NULL, NULL, "etk_d12", "safe_mode"),
50 _OMAP2430_MUXENTRY(CAM_D11, 145,
51 "cam_d11", NULL, NULL, "gpio_145",
52 NULL, NULL, "etk_d13", "safe_mode"),
53 _OMAP2430_MUXENTRY(CAM_D1, 132,
54 "cam_d1", "hw_dbg1", "sti_din", "gpio_132",
55 NULL, NULL, "etk_d3", "safe_mode"),
56 _OMAP2430_MUXENTRY(CAM_D2, 129,
57 "cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129",
58 NULL, NULL, "etk_d4", "safe_mode"),
59 _OMAP2430_MUXENTRY(CAM_D3, 128,
60 "cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128",
61 NULL, NULL, "etk_d5", "safe_mode"),
62 _OMAP2430_MUXENTRY(CAM_D4, 143,
63 "cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143",
64 NULL, NULL, "etk_d6", "safe_mode"),
65 _OMAP2430_MUXENTRY(CAM_D5, 112,
66 "cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112",
67 NULL, NULL, "etk_d7", "safe_mode"),
68 _OMAP2430_MUXENTRY(CAM_D6, 137,
69 "cam_d6", "hw_dbg6", NULL, "gpio_137",
70 NULL, NULL, "etk_d8", "safe_mode"),
71 _OMAP2430_MUXENTRY(CAM_D7, 136,
72 "cam_d7", "hw_dbg7", NULL, "gpio_136",
73 NULL, NULL, "etk_d9", "safe_mode"),
74 _OMAP2430_MUXENTRY(CAM_D8, 135,
75 "cam_d8", "hw_dbg8", NULL, "gpio_135",
76 NULL, NULL, "etk_d10", "safe_mode"),
77 _OMAP2430_MUXENTRY(CAM_D9, 134,
78 "cam_d9", "hw_dbg9", NULL, "gpio_134",
79 NULL, NULL, "etk_d11", "safe_mode"),
80 _OMAP2430_MUXENTRY(CAM_HS, 11,
81 "cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11",
82 NULL, NULL, "etk_d1", "safe_mode"),
83 _OMAP2430_MUXENTRY(CAM_LCLK, 0,
84 "cam_lclk", NULL, "mcbsp_clks", NULL,
85 NULL, NULL, "etk_c1", "safe_mode"),
86 _OMAP2430_MUXENTRY(CAM_VS, 12,
87 "cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12",
88 NULL, NULL, "etk_d0", "safe_mode"),
89 _OMAP2430_MUXENTRY(CAM_XCLK, 0,
90 "cam_xclk", NULL, "sti_clk", NULL,
91 NULL, NULL, "etk_c2", NULL),
92 _OMAP2430_MUXENTRY(DSS_ACBIAS, 48,
93 "dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
94 NULL, NULL, NULL, "safe_mode"),
95 _OMAP2430_MUXENTRY(DSS_DATA0, 40,
96 "dss_data0", "uart1_cts", NULL, "gpio_40",
97 NULL, NULL, NULL, "safe_mode"),
98 _OMAP2430_MUXENTRY(DSS_DATA10, 128,
99 "dss_data10", "sdi_data1n", NULL, "gpio_128",
100 NULL, NULL, NULL, "safe_mode"),
101 _OMAP2430_MUXENTRY(DSS_DATA11, 129,
102 "dss_data11", "sdi_data1p", NULL, "gpio_129",
103 NULL, NULL, NULL, "safe_mode"),
104 _OMAP2430_MUXENTRY(DSS_DATA12, 130,
105 "dss_data12", "sdi_data2n", NULL, "gpio_130",
106 NULL, NULL, NULL, "safe_mode"),
107 _OMAP2430_MUXENTRY(DSS_DATA13, 131,
108 "dss_data13", "sdi_data2p", NULL, "gpio_131",
109 NULL, NULL, NULL, "safe_mode"),
110 _OMAP2430_MUXENTRY(DSS_DATA14, 132,
111 "dss_data14", "sdi_data3n", NULL, "gpio_132",
112 NULL, NULL, NULL, "safe_mode"),
113 _OMAP2430_MUXENTRY(DSS_DATA15, 133,
114 "dss_data15", "sdi_data3p", NULL, "gpio_133",
115 NULL, NULL, NULL, "safe_mode"),
116 _OMAP2430_MUXENTRY(DSS_DATA16, 46,
117 "dss_data16", NULL, NULL, "gpio_46",
118 NULL, NULL, NULL, "safe_mode"),
119 _OMAP2430_MUXENTRY(DSS_DATA17, 47,
120 "dss_data17", NULL, NULL, "gpio_47",
121 NULL, NULL, NULL, "safe_mode"),
122 _OMAP2430_MUXENTRY(DSS_DATA1, 41,
123 "dss_data1", "uart1_rts", NULL, "gpio_41",
124 NULL, NULL, NULL, "safe_mode"),
125 _OMAP2430_MUXENTRY(DSS_DATA2, 42,
126 "dss_data2", "uart1_tx", NULL, "gpio_42",
127 NULL, NULL, NULL, "safe_mode"),
128 _OMAP2430_MUXENTRY(DSS_DATA3, 43,
129 "dss_data3", "uart1_rx", NULL, "gpio_43",
130 NULL, NULL, NULL, "safe_mode"),
131 _OMAP2430_MUXENTRY(DSS_DATA4, 44,
132 "dss_data4", "uart3_rx_irrx", NULL, "gpio_44",
133 NULL, NULL, NULL, "safe_mode"),
134 _OMAP2430_MUXENTRY(DSS_DATA5, 45,
135 "dss_data5", "uart3_tx_irtx", NULL, "gpio_45",
136 NULL, NULL, NULL, "safe_mode"),
137 _OMAP2430_MUXENTRY(DSS_DATA6, 144,
138 "dss_data6", NULL, NULL, "gpio_144",
139 NULL, NULL, NULL, "safe_mode"),
140 _OMAP2430_MUXENTRY(DSS_DATA7, 147,
141 "dss_data7", NULL, NULL, "gpio_147",
142 NULL, NULL, NULL, "safe_mode"),
143 _OMAP2430_MUXENTRY(DSS_DATA8, 38,
144 "dss_data8", NULL, NULL, "gpio_38",
145 NULL, NULL, NULL, "safe_mode"),
146 _OMAP2430_MUXENTRY(DSS_DATA9, 39,
147 "dss_data9", NULL, NULL, "gpio_39",
148 NULL, NULL, NULL, "safe_mode"),
149 _OMAP2430_MUXENTRY(DSS_HSYNC, 110,
150 "dss_hsync", NULL, NULL, "gpio_110",
151 NULL, NULL, NULL, "safe_mode"),
152 _OMAP2430_MUXENTRY(GPIO_113, 113,
153 "gpio_113", "mcbsp2_clkx", NULL, "gpio_113",
154 NULL, NULL, NULL, "safe_mode"),
155 _OMAP2430_MUXENTRY(GPIO_114, 114,
156 "gpio_114", "mcbsp2_fsx", NULL, "gpio_114",
157 NULL, NULL, NULL, "safe_mode"),
158 _OMAP2430_MUXENTRY(GPIO_115, 115,
159 "gpio_115", "mcbsp2_dr", NULL, "gpio_115",
160 NULL, NULL, NULL, "safe_mode"),
161 _OMAP2430_MUXENTRY(GPIO_116, 116,
162 "gpio_116", "mcbsp2_dx", NULL, "gpio_116",
163 NULL, NULL, NULL, "safe_mode"),
164 _OMAP2430_MUXENTRY(GPIO_128, 128,
165 "gpio_128", NULL, "sti_din", "gpio_128",
166 NULL, "sys_boot0", NULL, "safe_mode"),
167 _OMAP2430_MUXENTRY(GPIO_129, 129,
168 "gpio_129", NULL, "sti_dout", "gpio_129",
169 NULL, "sys_boot1", NULL, "safe_mode"),
170 _OMAP2430_MUXENTRY(GPIO_130, 130,
171 "gpio_130", NULL, NULL, "gpio_130",
172 "jtag_emu2", "sys_boot2", NULL, "safe_mode"),
173 _OMAP2430_MUXENTRY(GPIO_131, 131,
174 "gpio_131", NULL, NULL, "gpio_131",
175 "jtag_emu3", "sys_boot3", NULL, "safe_mode"),
176 _OMAP2430_MUXENTRY(GPIO_132, 132,
177 "gpio_132", NULL, NULL, "gpio_132",
178 NULL, "sys_boot4", NULL, "safe_mode"),
179 _OMAP2430_MUXENTRY(GPIO_133, 133,
180 "gpio_133", NULL, NULL, "gpio_133",
181 NULL, "sys_boot5", NULL, "safe_mode"),
182 _OMAP2430_MUXENTRY(GPIO_134, 134,
183 "gpio_134", "ccp_datn", NULL, "gpio_134",
184 NULL, NULL, NULL, "safe_mode"),
185 _OMAP2430_MUXENTRY(GPIO_135, 135,
186 "gpio_135", "ccp_datp", NULL, "gpio_135",
187 NULL, NULL, NULL, "safe_mode"),
188 _OMAP2430_MUXENTRY(GPIO_136, 136,
189 "gpio_136", "ccp_clkn", NULL, "gpio_136",
190 NULL, NULL, NULL, "safe_mode"),
191 _OMAP2430_MUXENTRY(GPIO_137, 137,
192 "gpio_137", "ccp_clkp", NULL, "gpio_137",
193 NULL, NULL, NULL, "safe_mode"),
194 _OMAP2430_MUXENTRY(GPIO_138, 138,
195 "gpio_138", "spi3_clk", NULL, "gpio_138",
196 NULL, NULL, NULL, "safe_mode"),
197 _OMAP2430_MUXENTRY(GPIO_139, 139,
198 "gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139",
199 NULL, NULL, NULL, "safe_mode"),
200 _OMAP2430_MUXENTRY(GPIO_140, 140,
201 "gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140",
202 NULL, NULL, "etk_d14", "safe_mode"),
203 _OMAP2430_MUXENTRY(GPIO_141, 141,
204 "gpio_141", "spi3_somi", NULL, "gpio_141",
205 NULL, NULL, NULL, "safe_mode"),
206 _OMAP2430_MUXENTRY(GPIO_142, 142,
207 "gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142",
208 NULL, NULL, "etk_d15", "safe_mode"),
209 _OMAP2430_MUXENTRY(GPIO_148, 148,
210 "gpio_148", "mcbsp5_fsx", NULL, "gpio_148",
211 NULL, NULL, NULL, "safe_mode"),
212 _OMAP2430_MUXENTRY(GPIO_149, 149,
213 "gpio_149", "mcbsp5_dx", NULL, "gpio_149",
214 NULL, NULL, NULL, "safe_mode"),
215 _OMAP2430_MUXENTRY(GPIO_150, 150,
216 "gpio_150", "mcbsp5_dr", NULL, "gpio_150",
217 NULL, NULL, NULL, "safe_mode"),
218 _OMAP2430_MUXENTRY(GPIO_151, 151,
219 "gpio_151", "sys_pwrok", NULL, "gpio_151",
220 NULL, NULL, NULL, "safe_mode"),
221 _OMAP2430_MUXENTRY(GPIO_152, 152,
222 "gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152",
223 NULL, NULL, NULL, "safe_mode"),
224 _OMAP2430_MUXENTRY(GPIO_153, 153,
225 "gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153",
226 NULL, NULL, NULL, "safe_mode"),
227 _OMAP2430_MUXENTRY(GPIO_154, 154,
228 "gpio_154", "mcbsp5_clkx", NULL, "gpio_154",
229 NULL, NULL, NULL, "safe_mode"),
230 _OMAP2430_MUXENTRY(GPIO_63, 63,
231 "gpio_63", "mcbsp4_clkx", NULL, "gpio_63",
232 NULL, NULL, NULL, "safe_mode"),
233 _OMAP2430_MUXENTRY(GPIO_78, 78,
234 "gpio_78", NULL, "uart2_rts", "gpio_78",
235 "uart3_rts_sd", NULL, NULL, "safe_mode"),
236 _OMAP2430_MUXENTRY(GPIO_79, 79,
237 "gpio_79", "secure_indicator", "uart2_tx", "gpio_79",
238 "uart3_tx_irtx", NULL, NULL, "safe_mode"),
239 _OMAP2430_MUXENTRY(GPIO_7, 7,
240 "gpio_7", NULL, "uart2_cts", "gpio_7",
241 "uart3_cts_rctx", NULL, NULL, "safe_mode"),
242 _OMAP2430_MUXENTRY(GPIO_80, 80,
243 "gpio_80", NULL, "uart2_rx", "gpio_80",
244 "uart3_rx_irrx", NULL, NULL, "safe_mode"),
245 _OMAP2430_MUXENTRY(GPMC_A10, 3,
246 "gpmc_a10", NULL, "sys_ndmareq0", "gpio_3",
247 NULL, NULL, NULL, "safe_mode"),
248 _OMAP2430_MUXENTRY(GPMC_A1, 31,
249 "gpmc_a1", NULL, NULL, "gpio_31",
250 NULL, NULL, NULL, "safe_mode"),
251 _OMAP2430_MUXENTRY(GPMC_A2, 30,
252 "gpmc_a2", NULL, NULL, "gpio_30",
253 NULL, NULL, NULL, "safe_mode"),
254 _OMAP2430_MUXENTRY(GPMC_A3, 29,
255 "gpmc_a3", NULL, NULL, "gpio_29",
256 NULL, NULL, NULL, "safe_mode"),
257 _OMAP2430_MUXENTRY(GPMC_A4, 49,
258 "gpmc_a4", NULL, NULL, "gpio_49",
259 NULL, NULL, NULL, "safe_mode"),
260 _OMAP2430_MUXENTRY(GPMC_A5, 53,
261 "gpmc_a5", NULL, NULL, "gpio_53",
262 NULL, NULL, NULL, "safe_mode"),
263 _OMAP2430_MUXENTRY(GPMC_A6, 52,
264 "gpmc_a6", NULL, NULL, "gpio_52",
265 NULL, NULL, NULL, "safe_mode"),
266 _OMAP2430_MUXENTRY(GPMC_A7, 6,
267 "gpmc_a7", NULL, NULL, "gpio_6",
268 NULL, NULL, NULL, "safe_mode"),
269 _OMAP2430_MUXENTRY(GPMC_A8, 5,
270 "gpmc_a8", NULL, NULL, "gpio_5",
271 NULL, NULL, NULL, "safe_mode"),
272 _OMAP2430_MUXENTRY(GPMC_A9, 4,
273 "gpmc_a9", NULL, "sys_ndmareq1", "gpio_4",
274 NULL, NULL, NULL, "safe_mode"),
275 _OMAP2430_MUXENTRY(GPMC_CLK, 21,
276 "gpmc_clk", NULL, NULL, "gpio_21",
277 NULL, NULL, NULL, "safe_mode"),
278 _OMAP2430_MUXENTRY(GPMC_D10, 18,
279 "gpmc_d10", NULL, NULL, "gpio_18",
280 NULL, NULL, NULL, "safe_mode"),
281 _OMAP2430_MUXENTRY(GPMC_D11, 57,
282 "gpmc_d11", NULL, NULL, "gpio_57",
283 NULL, NULL, NULL, "safe_mode"),
284 _OMAP2430_MUXENTRY(GPMC_D12, 77,
285 "gpmc_d12", NULL, NULL, "gpio_77",
286 NULL, NULL, NULL, "safe_mode"),
287 _OMAP2430_MUXENTRY(GPMC_D13, 76,
288 "gpmc_d13", NULL, NULL, "gpio_76",
289 NULL, NULL, NULL, "safe_mode"),
290 _OMAP2430_MUXENTRY(GPMC_D14, 55,
291 "gpmc_d14", NULL, NULL, "gpio_55",
292 NULL, NULL, NULL, "safe_mode"),
293 _OMAP2430_MUXENTRY(GPMC_D15, 54,
294 "gpmc_d15", NULL, NULL, "gpio_54",
295 NULL, NULL, NULL, "safe_mode"),
296 _OMAP2430_MUXENTRY(GPMC_D8, 20,
297 "gpmc_d8", NULL, NULL, "gpio_20",
298 NULL, NULL, NULL, "safe_mode"),
299 _OMAP2430_MUXENTRY(GPMC_D9, 19,
300 "gpmc_d9", NULL, NULL, "gpio_19",
301 NULL, NULL, NULL, "safe_mode"),
302 _OMAP2430_MUXENTRY(GPMC_NCS1, 22,
303 "gpmc_ncs1", NULL, NULL, "gpio_22",
304 NULL, NULL, NULL, "safe_mode"),
305 _OMAP2430_MUXENTRY(GPMC_NCS2, 23,
306 "gpmc_ncs2", NULL, NULL, "gpio_23",
307 NULL, NULL, NULL, "safe_mode"),
308 _OMAP2430_MUXENTRY(GPMC_NCS3, 24,
309 "gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
310 NULL, NULL, NULL, "safe_mode"),
311 _OMAP2430_MUXENTRY(GPMC_NCS4, 25,
312 "gpmc_ncs4", NULL, NULL, "gpio_25",
313 NULL, NULL, NULL, "safe_mode"),
314 _OMAP2430_MUXENTRY(GPMC_NCS5, 26,
315 "gpmc_ncs5", NULL, NULL, "gpio_26",
316 NULL, NULL, NULL, "safe_mode"),
317 _OMAP2430_MUXENTRY(GPMC_NCS6, 27,
318 "gpmc_ncs6", NULL, NULL, "gpio_27",
319 NULL, NULL, NULL, "safe_mode"),
320 _OMAP2430_MUXENTRY(GPMC_NCS7, 28,
321 "gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28",
322 NULL, NULL, NULL, "safe_mode"),
323 _OMAP2430_MUXENTRY(GPMC_WAIT1, 33,
324 "gpmc_wait1", NULL, NULL, "gpio_33",
325 NULL, NULL, NULL, "safe_mode"),
326 _OMAP2430_MUXENTRY(GPMC_WAIT2, 34,
327 "gpmc_wait2", NULL, NULL, "gpio_34",
328 NULL, NULL, NULL, "safe_mode"),
329 _OMAP2430_MUXENTRY(GPMC_WAIT3, 35,
330 "gpmc_wait3", NULL, NULL, "gpio_35",
331 NULL, NULL, NULL, "safe_mode"),
332 _OMAP2430_MUXENTRY(HDQ_SIO, 101,
333 "hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
334 "uart3_rx_irrx", NULL, NULL, "safe_mode"),
335 _OMAP2430_MUXENTRY(I2C1_SCL, 50,
336 "i2c1_scl", NULL, NULL, "gpio_50",
337 NULL, NULL, NULL, "safe_mode"),
338 _OMAP2430_MUXENTRY(I2C1_SDA, 51,
339 "i2c1_sda", NULL, NULL, "gpio_51",
340 NULL, NULL, NULL, "safe_mode"),
341 _OMAP2430_MUXENTRY(I2C2_SCL, 99,
342 "i2c2_scl", NULL, NULL, "gpio_99",
343 NULL, NULL, NULL, "safe_mode"),
344 _OMAP2430_MUXENTRY(I2C2_SDA, 100,
345 "i2c2_sda", NULL, NULL, "gpio_100",
346 NULL, NULL, NULL, "safe_mode"),
347 _OMAP2430_MUXENTRY(JTAG_EMU0, 127,
348 "jtag_emu0", "secure_indicator", NULL, "gpio_127",
349 NULL, NULL, NULL, "safe_mode"),
350 _OMAP2430_MUXENTRY(JTAG_EMU1, 126,
351 "jtag_emu1", NULL, NULL, "gpio_126",
352 NULL, NULL, NULL, "safe_mode"),
353 _OMAP2430_MUXENTRY(MCBSP1_CLKR, 92,
354 "mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92",
355 NULL, NULL, NULL, "safe_mode"),
356 _OMAP2430_MUXENTRY(MCBSP1_CLKX, 98,
357 "mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98",
358 NULL, NULL, NULL, "safe_mode"),
359 _OMAP2430_MUXENTRY(MCBSP1_DR, 95,
360 "mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95",
361 NULL, NULL, NULL, "safe_mode"),
362 _OMAP2430_MUXENTRY(MCBSP1_DX, 94,
363 "mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94",
364 NULL, NULL, NULL, "safe_mode"),
365 _OMAP2430_MUXENTRY(MCBSP1_FSR, 93,
366 "mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93",
367 "spi2_cs1", NULL, NULL, "safe_mode"),
368 _OMAP2430_MUXENTRY(MCBSP1_FSX, 97,
369 "mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
370 NULL, NULL, NULL, "safe_mode"),
371 _OMAP2430_MUXENTRY(MCBSP2_CLKX, 147,
372 "mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147",
373 NULL, NULL, NULL, "safe_mode"),
374 _OMAP2430_MUXENTRY(MCBSP2_DR, 144,
375 "mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144",
376 NULL, NULL, NULL, "safe_mode"),
377 _OMAP2430_MUXENTRY(MCBSP3_CLKX, 71,
378 "mcbsp3_clkx", NULL, NULL, "gpio_71",
379 NULL, NULL, NULL, "safe_mode"),
380 _OMAP2430_MUXENTRY(MCBSP3_DR, 73,
381 "mcbsp3_dr", NULL, NULL, "gpio_73",
382 NULL, NULL, NULL, "safe_mode"),
383 _OMAP2430_MUXENTRY(MCBSP3_DX, 74,
384 "mcbsp3_dx", NULL, "sti_clk", "gpio_74",
385 NULL, NULL, NULL, "safe_mode"),
386 _OMAP2430_MUXENTRY(MCBSP3_FSX, 72,
387 "mcbsp3_fsx", NULL, NULL, "gpio_72",
388 NULL, NULL, NULL, "safe_mode"),
389 _OMAP2430_MUXENTRY(MCBSP_CLKS, 96,
390 "mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96",
391 NULL, NULL, NULL, "safe_mode"),
392 _OMAP2430_MUXENTRY(SDMMC1_CLKO, 0,
393 "sdmmc1_clko", "ms_clko", NULL, NULL,
394 NULL, "hw_dbg9", "hw_dbg3", "safe_mode"),
395 _OMAP2430_MUXENTRY(SDMMC1_CMD, 0,
396 "sdmmc1_cmd", "ms_bs", NULL, NULL,
397 NULL, "hw_dbg8", "hw_dbg2", "safe_mode"),
398 _OMAP2430_MUXENTRY(SDMMC1_DAT0, 0,
399 "sdmmc1_dat0", "ms_dat0", NULL, NULL,
400 NULL, "hw_dbg7", "hw_dbg1", "safe_mode"),
401 _OMAP2430_MUXENTRY(SDMMC1_DAT1, 75,
402 "sdmmc1_dat1", "ms_dat1", NULL, "gpio_75",
403 NULL, "hw_dbg6", "hw_dbg0", "safe_mode"),
404 _OMAP2430_MUXENTRY(SDMMC1_DAT2, 0,
405 "sdmmc1_dat2", "ms_dat2", NULL, NULL,
406 NULL, "hw_dbg5", "hw_dbg10", "safe_mode"),
407 _OMAP2430_MUXENTRY(SDMMC1_DAT3, 0,
408 "sdmmc1_dat3", "ms_dat3", NULL, NULL,
409 NULL, "hw_dbg4", "hw_dbg11", "safe_mode"),
410 _OMAP2430_MUXENTRY(SDMMC2_CLKO, 13,
411 "sdmmc2_clko", NULL, NULL, "gpio_13",
412 NULL, "spi3_clk", NULL, "safe_mode"),
413 _OMAP2430_MUXENTRY(SDMMC2_CMD, 15,
414 "sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15",
415 NULL, "spi3_simo", NULL, "safe_mode"),
416 _OMAP2430_MUXENTRY(SDMMC2_DAT0, 16,
417 "sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16",
418 NULL, "spi3_somi", NULL, "safe_mode"),
419 _OMAP2430_MUXENTRY(SDMMC2_DAT1, 58,
420 "sdmmc2_dat1", "usb2_txen", NULL, "gpio_58",
421 NULL, NULL, NULL, "safe_mode"),
422 _OMAP2430_MUXENTRY(SDMMC2_DAT2, 17,
423 "sdmmc2_dat2", "usb2_dat", NULL, "gpio_17",
424 NULL, "spi3_cs1", NULL, "safe_mode"),
425 _OMAP2430_MUXENTRY(SDMMC2_DAT3, 14,
426 "sdmmc2_dat3", "usb2_se0", NULL, "gpio_14",
427 NULL, "spi3_cs0", NULL, "safe_mode"),
428 _OMAP2430_MUXENTRY(SDRC_A12, 2,
429 "sdrc_a12", NULL, NULL, "gpio_2",
430 NULL, NULL, NULL, "safe_mode"),
431 _OMAP2430_MUXENTRY(SDRC_A13, 1,
432 "sdrc_a13", NULL, NULL, "gpio_1",
433 NULL, NULL, NULL, "safe_mode"),
434 _OMAP2430_MUXENTRY(SDRC_A14, 0,
435 "sdrc_a14", NULL, NULL, "gpio_0",
436 NULL, NULL, NULL, "safe_mode"),
437 _OMAP2430_MUXENTRY(SDRC_CKE1, 36,
438 "sdrc_cke1", NULL, NULL, "gpio_36",
439 NULL, NULL, NULL, "safe_mode"),
440 _OMAP2430_MUXENTRY(SDRC_NCS1, 37,
441 "sdrc_ncs1", NULL, NULL, "gpio_37",
442 NULL, NULL, NULL, "safe_mode"),
443 _OMAP2430_MUXENTRY(SPI1_CLK, 81,
444 "spi1_clk", NULL, NULL, "gpio_81",
445 NULL, NULL, NULL, "safe_mode"),
446 _OMAP2430_MUXENTRY(SPI1_CS0, 84,
447 "spi1_cs0", NULL, NULL, "gpio_84",
448 NULL, NULL, NULL, "safe_mode"),
449 _OMAP2430_MUXENTRY(SPI1_CS1, 85,
450 "spi1_cs1", NULL, NULL, "gpio_85",
451 NULL, NULL, NULL, "safe_mode"),
452 _OMAP2430_MUXENTRY(SPI1_CS2, 86,
453 "spi1_cs2", NULL, NULL, "gpio_86",
454 NULL, NULL, NULL, "safe_mode"),
455 _OMAP2430_MUXENTRY(SPI1_CS3, 87,
456 "spi1_cs3", "spi2_cs1", NULL, "gpio_87",
457 NULL, NULL, NULL, "safe_mode"),
458 _OMAP2430_MUXENTRY(SPI1_SIMO, 82,
459 "spi1_simo", NULL, NULL, "gpio_82",
460 NULL, NULL, NULL, "safe_mode"),
461 _OMAP2430_MUXENTRY(SPI1_SOMI, 83,
462 "spi1_somi", NULL, NULL, "gpio_83",
463 NULL, NULL, NULL, "safe_mode"),
464 _OMAP2430_MUXENTRY(SPI2_CLK, 88,
465 "spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88",
466 NULL, NULL, NULL, "safe_mode"),
467 _OMAP2430_MUXENTRY(SPI2_CS0, 91,
468 "spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91",
469 NULL, NULL, NULL, "safe_mode"),
470 _OMAP2430_MUXENTRY(SPI2_SIMO, 89,
471 "spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
472 NULL, NULL, NULL, "safe_mode"),
473 _OMAP2430_MUXENTRY(SPI2_SOMI, 90,
474 "spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
475 NULL, NULL, NULL, "safe_mode"),
476 _OMAP2430_MUXENTRY(SSI1_DAT_RX, 62,
477 "ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62",
478 NULL, NULL, NULL, "safe_mode"),
479 _OMAP2430_MUXENTRY(SSI1_DAT_TX, 59,
480 "ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
481 NULL, NULL, NULL, "safe_mode"),
482 _OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64,
483 "ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64",
484 NULL, NULL, NULL, "safe_mode"),
485 _OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60,
486 "ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60",
487 NULL, NULL, NULL, "safe_mode"),
488 _OMAP2430_MUXENTRY(SSI1_RDY_RX, 65,
489 "ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65",
490 NULL, NULL, NULL, "safe_mode"),
491 _OMAP2430_MUXENTRY(SSI1_RDY_TX, 61,
492 "ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
493 NULL, NULL, NULL, "safe_mode"),
494 _OMAP2430_MUXENTRY(SSI1_WAKE, 66,
495 "ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66",
496 NULL, NULL, NULL, "safe_mode"),
497 _OMAP2430_MUXENTRY(SYS_CLKOUT, 111,
498 "sys_clkout", NULL, NULL, "gpio_111",
499 NULL, NULL, NULL, "safe_mode"),
500 _OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118,
501 "sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118",
502 NULL, NULL, NULL, "safe_mode"),
503 _OMAP2430_MUXENTRY(SYS_NIRQ0, 56,
504 "sys_nirq0", NULL, NULL, "gpio_56",
505 NULL, NULL, NULL, "safe_mode"),
506 _OMAP2430_MUXENTRY(SYS_NIRQ1, 125,
507 "sys_nirq1", NULL, "sys_ndmareq5", "gpio_125",
508 NULL, NULL, NULL, "safe_mode"),
509 _OMAP2430_MUXENTRY(UART1_CTS, 32,
510 "uart1_cts", "sdi_vsync", "dss_data18", "gpio_32",
511 "mcbsp5_clkx", NULL, NULL, "safe_mode"),
512 _OMAP2430_MUXENTRY(UART1_RTS, 8,
513 "uart1_rts", "sdi_hsync", "dss_data19", "gpio_8",
514 "mcbsp5_fsx", NULL, NULL, "safe_mode"),
515 _OMAP2430_MUXENTRY(UART1_RX, 10,
516 "uart1_rx", "sdi_stp", "dss_data21", "gpio_10",
517 "mcbsp5_dr", NULL, NULL, "safe_mode"),
518 _OMAP2430_MUXENTRY(UART1_TX, 9,
519 "uart1_tx", "sdi_den", "dss_data20", "gpio_9",
520 "mcbsp5_dx", NULL, NULL, "safe_mode"),
521 _OMAP2430_MUXENTRY(UART2_CTS, 67,
522 "uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
523 NULL, NULL, NULL, "safe_mode"),
524 _OMAP2430_MUXENTRY(UART2_RTS, 68,
525 "uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
526 NULL, NULL, NULL, "safe_mode"),
527 _OMAP2430_MUXENTRY(UART2_RX, 70,
528 "uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
529 NULL, NULL, NULL, "safe_mode"),
530 _OMAP2430_MUXENTRY(UART2_TX, 69,
531 "uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
532 NULL, NULL, NULL, "safe_mode"),
533 _OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102,
534 "uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
535 NULL, NULL, NULL, "safe_mode"),
536 _OMAP2430_MUXENTRY(UART3_RTS_SD, 103,
537 "uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
538 NULL, NULL, NULL, "safe_mode"),
539 _OMAP2430_MUXENTRY(UART3_RX_IRRX, 105,
540 "uart3_rx_irrx", NULL, NULL, "gpio_105",
541 NULL, NULL, NULL, "safe_mode"),
542 _OMAP2430_MUXENTRY(UART3_TX_IRTX, 104,
543 "uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
544 NULL, NULL, NULL, "safe_mode"),
545 _OMAP2430_MUXENTRY(USB0HS_CLK, 120,
546 "usb0hs_clk", NULL, NULL, "gpio_120",
547 NULL, NULL, NULL, "safe_mode"),
548 _OMAP2430_MUXENTRY(USB0HS_DATA0, 0,
549 "usb0hs_data0", "uart3_tx_irtx", NULL, NULL,
550 "usb0_txen", NULL, NULL, "safe_mode"),
551 _OMAP2430_MUXENTRY(USB0HS_DATA1, 0,
552 "usb0hs_data1", "uart3_rx_irrx", NULL, NULL,
553 "usb0_dat", NULL, NULL, "safe_mode"),
554 _OMAP2430_MUXENTRY(USB0HS_DATA2, 0,
555 "usb0hs_data2", "uart3_rts_sd", NULL, NULL,
556 "usb0_se0", NULL, NULL, "safe_mode"),
557 _OMAP2430_MUXENTRY(USB0HS_DATA3, 106,
558 "usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106",
559 "usb0_puen", NULL, NULL, "safe_mode"),
560 _OMAP2430_MUXENTRY(USB0HS_DATA4, 107,
561 "usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107",
562 "usb0_vp", NULL, NULL, "safe_mode"),
563 _OMAP2430_MUXENTRY(USB0HS_DATA5, 108,
564 "usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108",
565 "usb0_vm", NULL, NULL, "safe_mode"),
566 _OMAP2430_MUXENTRY(USB0HS_DATA6, 109,
567 "usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109",
568 "usb0_rcv", NULL, NULL, "safe_mode"),
569 _OMAP2430_MUXENTRY(USB0HS_DATA7, 124,
570 "usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124",
571 NULL, NULL, NULL, "safe_mode"),
572 _OMAP2430_MUXENTRY(USB0HS_DIR, 121,
573 "usb0hs_dir", NULL, NULL, "gpio_121",
574 NULL, NULL, NULL, "safe_mode"),
575 _OMAP2430_MUXENTRY(USB0HS_NXT, 123,
576 "usb0hs_nxt", NULL, NULL, "gpio_123",
577 NULL, NULL, NULL, "safe_mode"),
578 _OMAP2430_MUXENTRY(USB0HS_STP, 122,
579 "usb0hs_stp", NULL, NULL, "gpio_122",
580 NULL, NULL, NULL, "safe_mode"),
581 { .reg_offset = OMAP_MUX_TERMINATOR },
582};
583
584/*
585 * Balls for POP package
586 * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom)
587 */
588#ifdef CONFIG_DEBUG_FS
589static struct omap_ball __initdata omap2430_pop_ball[] = {
590 _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL),
591 _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL),
592 _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL),
593 _OMAP2430_BALLENTRY(CAM_D11, "w3", NULL),
594 _OMAP2430_BALLENTRY(CAM_D2, "r2", NULL),
595 _OMAP2430_BALLENTRY(CAM_D3, "u3", NULL),
596 _OMAP2430_BALLENTRY(CAM_D4, "u2", NULL),
597 _OMAP2430_BALLENTRY(CAM_D5, "v1", NULL),
598 _OMAP2430_BALLENTRY(CAM_D6, "t3", NULL),
599 _OMAP2430_BALLENTRY(CAM_D7, "r3", NULL),
600 _OMAP2430_BALLENTRY(CAM_D8, "u7", NULL),
601 _OMAP2430_BALLENTRY(CAM_D9, "t7", NULL),
602 _OMAP2430_BALLENTRY(CAM_HS, "p2", NULL),
603 _OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL),
604 _OMAP2430_BALLENTRY(CAM_VS, "n2", NULL),
605 _OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL),
606 _OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL),
607 _OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL),
608 _OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL),
609 _OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL),
610 _OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL),
611 _OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL),
612 _OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL),
613 _OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL),
614 _OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL),
615 _OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL),
616 _OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL),
617 _OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL),
618 _OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL),
619 _OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL),
620 _OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL),
621 _OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL),
622 _OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL),
623 _OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL),
624 _OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL),
625 _OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL),
626 _OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL),
627 _OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL),
628 _OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL),
629 _OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL),
630 _OMAP2430_BALLENTRY(GPIO_128, "p1", NULL),
631 _OMAP2430_BALLENTRY(GPIO_129, "r1", NULL),
632 _OMAP2430_BALLENTRY(GPIO_130, "p7", NULL),
633 _OMAP2430_BALLENTRY(GPIO_131, "l8", NULL),
634 _OMAP2430_BALLENTRY(GPIO_132, "w24", NULL),
635 _OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL),
636 _OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL),
637 _OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL),
638 _OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL),
639 _OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL),
640 _OMAP2430_BALLENTRY(GPIO_138, "y12", NULL),
641 _OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL),
642 _OMAP2430_BALLENTRY(GPIO_140, "l7", NULL),
643 _OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL),
644 _OMAP2430_BALLENTRY(GPIO_142, "m3", NULL),
645 _OMAP2430_BALLENTRY(GPIO_148, "af12", NULL),
646 _OMAP2430_BALLENTRY(GPIO_149, "k7", NULL),
647 _OMAP2430_BALLENTRY(GPIO_150, "m1", NULL),
648 _OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL),
649 _OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL),
650 _OMAP2430_BALLENTRY(GPIO_153, "u24", NULL),
651 _OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL),
652 _OMAP2430_BALLENTRY(GPIO_63, "n3", NULL),
653 _OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL),
654 _OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL),
655 _OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL),
656 _OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL),
657 _OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL),
658 _OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL),
659 _OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL),
660 _OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL),
661 _OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL),
662 _OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL),
663 _OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL),
664 _OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL),
665 _OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL),
666 _OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL),
667 _OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"),
668 _OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"),
669 _OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"),
670 _OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"),
671 _OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"),
672 _OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"),
673 _OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"),
674 _OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"),
675 _OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"),
676 _OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"),
677 _OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL),
678 _OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL),
679 _OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL),
680 _OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL),
681 _OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL),
682 _OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL),
683 _OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"),
684 _OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL),
685 _OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL),
686 _OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL),
687 _OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL),
688 _OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL),
689 _OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL),
690 _OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL),
691 _OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL),
692 _OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL),
693 _OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL),
694 _OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL),
695 _OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL),
696 _OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL),
697 _OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL),
698 _OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL),
699 _OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL),
700 _OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL),
701 _OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL),
702 _OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL),
703 _OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL),
704 _OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL),
705 _OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL),
706 _OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL),
707 _OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL),
708 _OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL),
709 _OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL),
710 _OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL),
711 _OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL),
712 _OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL),
713 _OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL),
714 _OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL),
715 _OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL),
716 _OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL),
717 _OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL),
718 _OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"),
719 _OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"),
720 _OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"),
721 _OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"),
722 _OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"),
723 _OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL),
724 _OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL),
725 _OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL),
726 _OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL),
727 _OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL),
728 _OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL),
729 _OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL),
730 _OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL),
731 _OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL),
732 _OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL),
733 _OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL),
734 _OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL),
735 _OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL),
736 _OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL),
737 _OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL),
738 _OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL),
739 _OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL),
740 _OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL),
741 _OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL),
742 _OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL),
743 _OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL),
744 _OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL),
745 _OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL),
746 _OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL),
747 _OMAP2430_BALLENTRY(UART1_RX, "n24", NULL),
748 _OMAP2430_BALLENTRY(UART1_TX, "r24", NULL),
749 _OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL),
750 _OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL),
751 _OMAP2430_BALLENTRY(UART2_RX, "t24", NULL),
752 _OMAP2430_BALLENTRY(UART2_TX, "u20", NULL),
753 _OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL),
754 _OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL),
755 _OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL),
756 _OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL),
757 _OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL),
758 _OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL),
759 _OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL),
760 _OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL),
761 _OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL),
762 _OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL),
763 _OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL),
764 _OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL),
765 _OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL),
766 _OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL),
767 _OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL),
768 _OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL),
769 { .reg_offset = OMAP_MUX_TERMINATOR },
770};
771#else
772#define omap2430_pop_ball NULL
773#endif
774
775int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
776{
777 struct omap_ball *package_balls = NULL;
778
779 switch (flags & OMAP_PACKAGE_MASK) {
780 case OMAP_PACKAGE_ZAC:
781 package_balls = omap2430_pop_ball;
782 break;
783 default:
784 pr_warning("%s: No ball data available for omap2420 package\n",
785 __func__);
786 }
787
788 return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
789 OMAP2430_CONTROL_PADCONF_MUX_PBASE,
790 OMAP2430_CONTROL_PADCONF_MUX_SIZE,
791 omap2430_muxmodes, NULL, board_subset,
792 package_balls);
793}
diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h
deleted file mode 100644
index 9fd93149ebd9..000000000000
--- a/arch/arm/mach-omap2/mux2430.h
+++ /dev/null
@@ -1,370 +0,0 @@
1/*
2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#define OMAP2430_CONTROL_PADCONF_MUX_PBASE 0x49002030LU
11
12#define OMAP2430_MUX(mode0, mux_value) \
13{ \
14 .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \
15 .value = (mux_value), \
16}
17
18/*
19 * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing
20 *
21 * Extracted from the TRM. Add 0x49002030 to these values to get the
22 * absolute addresses. The name in the macro is the mode-0 name of
23 * the pin. NOTE: These registers are 8-bits wide.
24 *
25 * Note that these defines use SDMMC instead of MMC for compatibility
26 * with signal names used in 3630.
27 */
28#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x000
29#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x001
30#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x002
31#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x003
32#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x004
33#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x005
34#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x006
35#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x007
36#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x008
37#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x009
38#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET 0x00a
39#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x00b
40#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x00c
41#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x00d
42#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x00e
43#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x00f
44#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x010
45#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x011
46#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x012
47#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x013
48#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x014
49#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x015
50#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x016
51#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x017
52#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x018
53#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x019
54#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x01a
55#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x01b
56#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x01c
57#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x01d
58#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x01e
59#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x01f
60#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x020
61#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x021
62#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x022
63#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x023
64#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET 0x024
65#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET 0x025
66#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET 0x026
67#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x027
68#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x028
69#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET 0x029
70#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET 0x02a
71#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET 0x02b
72#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET 0x02c
73#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET 0x02d
74#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET 0x02e
75#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET 0x02f
76#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET 0x030
77#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET 0x031
78#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET 0x032
79#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET 0x033
80#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET 0x034
81#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET 0x035
82#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET 0x036
83#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET 0x037
84#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
85#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET 0x039
86#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET 0x03a
87#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET 0x03b
88#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET 0x03c
89#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET 0x03d
90#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET 0x03e
91#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET 0x03f
92#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET 0x040
93#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET 0x041
94#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET 0x042
95#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET 0x043
96#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET 0x044
97#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET 0x045
98#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET 0x046
99#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET 0x047
100#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET 0x048
101#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET 0x049
102#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET 0x04a
103#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET 0x04b
104#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET 0x04c
105#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET 0x04d
106#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET 0x04e
107#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET 0x04f
108#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET 0x050
109#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET 0x051
110#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET 0x052
111#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET 0x053
112#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET 0x054
113#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET 0x055
114#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET 0x056
115#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET 0x057
116#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET 0x058
117#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET 0x059
118#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET 0x05a
119#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET 0x05b
120#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET 0x05c
121#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET 0x05d
122#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET 0x05e
123#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET 0x05f
124#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET 0x060
125#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET 0x061
126#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET 0x062
127#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET 0x063
128#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET 0x064
129#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET 0x065
130#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET 0x066
131#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET 0x067
132#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET 0x068
133#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET 0x069
134#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET 0x06a
135#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET 0x06b
136#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET 0x06c
137#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET 0x06d
138#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET 0x06e
139#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x06f
140#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x070
141#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x071
142#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x072
143#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x073
144#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x074
145#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x075
146#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x076
147#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x077
148#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x078
149#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x079
150#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x07a
151#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x07b
152#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x07c
153#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x07d
154#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x07e
155#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x07f
156#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x080
157#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET 0x081
158#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET 0x082
159#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET 0x083
160#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET 0x084
161#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x085
162#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x086
163#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x087
164#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x088
165#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x089
166#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x08a
167#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET 0x08b
168#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x08c
169#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET 0x08d
170#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET 0x08e
171#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET 0x08f
172#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET 0x090
173#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET 0x091
174#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET 0x092
175#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET 0x093
176#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET 0x094
177#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET 0x095
178#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET 0x096
179#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET 0x097
180#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x098
181#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET 0x099
182#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET 0x09a
183#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET 0x09b
184#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x09c
185#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x09d
186#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x09e
187#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x09f
188#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0x0a0
189#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET 0x0a1
190#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x0a2
191#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET 0x0a3
192#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET 0x0a4
193#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET 0x0a5
194#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET 0x0a6
195#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET 0x0a7
196#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET 0x0a8
197#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET 0x0a9
198#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET 0x0aa
199#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ab
200#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET 0x0ac
201#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET 0x0ad
202#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET 0x0ae
203#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET 0x0af
204#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET 0x0b0
205#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET 0x0b1
206#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET 0x0b2
207#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET 0x0b3
208#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET 0x0b4
209#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET 0x0b5
210#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET 0x0b6
211#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET 0x0b7
212#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET 0x0b8
213#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET 0x0b9
214#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET 0x0ba
215#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET 0x0bb
216#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET 0x0bc
217#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET 0x0bd
218#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET 0x0be
219#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET 0x0bf
220#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET 0x0c0
221#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET 0x0c1
222#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET 0x0c2
223#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET 0x0c3
224#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x0c4
225#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x0c5
226#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x0c6
227#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x0c7
228#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x0c8
229#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET 0x0c9
230#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x0ca
231#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x0cb
232#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x0cc
233#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x0cd
234#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x0ce
235#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET 0x0cf
236#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET 0x0d0
237#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET 0x0d1
238#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET 0x0d2
239#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x0d3
240#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x0d4
241#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x0d5
242#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x0d6
243#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET 0x0d7
244#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET 0x0d8
245#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET 0x0d9
246#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET 0x0da
247#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET 0x0db
248#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET 0x0dc
249#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET 0x0dd
250#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET 0x0de
251#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET 0x0df
252#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET 0x0e0
253#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET 0x0e1
254#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET 0x0e2
255#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET 0x0e3
256#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET 0x0e4
257#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET 0x0e5
258#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET 0x0e6
259#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET 0x0e7
260#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET 0x0e8
261#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET 0x0e9
262#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x0ea
263#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x0eb
264#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x0ec
265#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x0ed
266#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x0ee
267#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x0ef
268#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x0f0
269#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x0f1
270#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x0f2
271#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x0f3
272#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x0f4
273#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x0f5
274#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x0f6
275#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x0f7
276#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x0f8
277#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x0f9
278#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET 0x0fa
279#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET 0x0fb
280#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET 0x0fc
281#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET 0x0fd
282#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET 0x0fe
283#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET 0x0ff
284#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET 0x100
285#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET 0x101
286#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET 0x102
287#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET 0x103
288#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET 0x104
289#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET 0x105
290#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET 0x106
291#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET 0x107
292#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET 0x108
293#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET 0x109
294#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET 0x10a
295#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET 0x10b
296#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET 0x10c
297#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET 0x10d
298#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET 0x10e
299#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET 0x10f
300#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET 0x110
301#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET 0x111
302#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET 0x112
303#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET 0x113
304#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET 0x114
305#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET 0x115
306#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET 0x116
307#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET 0x117
308#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET 0x118
309#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET 0x119
310#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET 0x11a
311#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET 0x11b
312#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET 0x11c
313#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET 0x11d
314#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET 0x11e
315#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET 0x11f
316#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET 0x120
317#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET 0x121
318#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET 0x122
319#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET 0x123
320#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET 0x124
321#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET 0x125
322#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET 0x126
323#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET 0x127
324#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET 0x128
325#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET 0x129
326#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET 0x12a
327#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET 0x12b
328#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET 0x12c
329#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET 0x12d
330#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET 0x12e
331#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET 0x12f
332#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET 0x130
333#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET 0x131
334#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET 0x132
335#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET 0x133
336#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET 0x134
337#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET 0x135
338#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET 0x136
339#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET 0x137
340#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET 0x138
341#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET 0x139
342#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET 0x13a
343#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET 0x13b
344#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET 0x13c
345#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET 0x13d
346#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET 0x13e
347#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET 0x13f
348#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET 0x140
349#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET 0x141
350#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET 0x142
351#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET 0x143
352#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET 0x144
353#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET 0x145
354#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET 0x146
355#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET 0x147
356#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET 0x148
357#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET 0x149
358#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET 0x14a
359#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET 0x14b
360#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET 0x14c
361#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET 0x14d
362#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET 0x14e
363#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET 0x14f
364#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET 0x150
365#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET 0x151
366#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET 0x152
367#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET 0x153
368
369#define OMAP2430_CONTROL_PADCONF_MUX_SIZE \
370 (OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index f991016e2a6a..667915d236f3 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -271,6 +271,9 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
271 else 271 else
272 omap_pm_ops.finish_suspend(save_state); 272 omap_pm_ops.finish_suspend(save_state);
273 273
274 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
275 gic_dist_enable();
276
274 /* 277 /*
275 * Restore the CPUx power state to ON otherwise CPUx 278 * Restore the CPUx power state to ON otherwise CPUx
276 * power domain can transitions to programmed low power 279 * power domain can transitions to programmed low power
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 75e95d4fb448..17550aa39d0f 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -39,8 +39,6 @@
39 39
40#define OMAP5_CORE_COUNT 0x2 40#define OMAP5_CORE_COUNT 0x2
41 41
42u16 pm44xx_errata;
43
44/* SCU base address */ 42/* SCU base address */
45static void __iomem *scu_base; 43static void __iomem *scu_base;
46 44
@@ -217,10 +215,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
217 if (scu_base) 215 if (scu_base)
218 scu_enable(scu_base); 216 scu_enable(scu_base);
219 217
220 if (cpu_is_omap446x()) { 218 if (cpu_is_omap446x())
221 startup_addr = omap4460_secondary_startup; 219 startup_addr = omap4460_secondary_startup;
222 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
223 }
224 220
225 /* 221 /*
226 * Write the address of secondary startup routine into the 222 * Write the address of secondary startup routine into the
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index b39efd46abf9..6cd3f3772ecf 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -87,7 +87,7 @@ void __init omap_barriers_init(void)
87 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA; 87 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
88 dram_io_desc[0].pfn = __phys_to_pfn(paddr); 88 dram_io_desc[0].pfn = __phys_to_pfn(paddr);
89 dram_io_desc[0].length = size; 89 dram_io_desc[0].length = size;
90 dram_io_desc[0].type = MT_MEMORY_SO; 90 dram_io_desc[0].type = MT_MEMORY_RW_SO;
91 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc)); 91 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
92 dram_sync = (void __iomem *) dram_io_desc[0].virtual; 92 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
93 sram_sync = (void __iomem *) OMAP4_SRAM_VA; 93 sram_sync = (void __iomem *) OMAP4_SRAM_VA;
@@ -127,6 +127,12 @@ void gic_dist_disable(void)
127 __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL); 127 __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
128} 128}
129 129
130void gic_dist_enable(void)
131{
132 if (gic_dist_base_addr)
133 __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
134}
135
130bool gic_dist_disabled(void) 136bool gic_dist_disabled(void)
131{ 137{
132 return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); 138 return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
@@ -162,6 +168,7 @@ void __iomem *omap4_get_l2cache_base(void)
162 168
163static void omap4_l2x0_disable(void) 169static void omap4_l2x0_disable(void)
164{ 170{
171 outer_flush_all();
165 /* Disable PL310 L2 Cache controller */ 172 /* Disable PL310 L2 Cache controller */
166 omap_smc1(0x102, 0x0); 173 omap_smc1(0x102, 0x0);
167} 174}
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index e0a398cf28d8..01ef59def44b 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -36,6 +36,7 @@
36#include <linux/of.h> 36#include <linux/of.h>
37#include <linux/notifier.h> 37#include <linux/notifier.h>
38 38
39#include "common.h"
39#include "soc.h" 40#include "soc.h"
40#include "omap_device.h" 41#include "omap_device.h"
41#include "omap_hwmod.h" 42#include "omap_hwmod.h"
@@ -204,6 +205,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
204 case BUS_NOTIFY_ADD_DEVICE: 205 case BUS_NOTIFY_ADD_DEVICE:
205 if (pdev->dev.of_node) 206 if (pdev->dev.of_node)
206 omap_device_build_from_dt(pdev); 207 omap_device_build_from_dt(pdev);
208 omap_auxdata_legacy_init(dev);
207 /* fall through */ 209 /* fall through */
208 default: 210 default:
209 od = to_omap_device(pdev); 211 od = to_omap_device(pdev);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 8a1b5e0bad40..1f33f5db10d5 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -686,6 +686,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
686 if (oh->clkdm) { 686 if (oh->clkdm) {
687 return oh->clkdm; 687 return oh->clkdm;
688 } else if (oh->_clk) { 688 } else if (oh->_clk) {
689 if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
690 return NULL;
689 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); 691 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
690 return clk->clkdm; 692 return clk->clkdm;
691 } 693 }
@@ -1576,7 +1578,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
1576 if (!oh->clkdm) { 1578 if (!oh->clkdm) {
1577 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", 1579 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
1578 oh->name, oh->clkdm_name); 1580 oh->name, oh->clkdm_name);
1579 return -EINVAL; 1581 return 0;
1580 } 1582 }
1581 1583
1582 pr_debug("omap_hwmod: %s: associated to clkdm %s\n", 1584 pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -1945,29 +1947,31 @@ static int _ocp_softreset(struct omap_hwmod *oh)
1945 goto dis_opt_clks; 1947 goto dis_opt_clks;
1946 1948
1947 _write_sysconfig(v, oh); 1949 _write_sysconfig(v, oh);
1948 ret = _clear_softreset(oh, &v);
1949 if (ret)
1950 goto dis_opt_clks;
1951
1952 _write_sysconfig(v, oh);
1953 1950
1954 if (oh->class->sysc->srst_udelay) 1951 if (oh->class->sysc->srst_udelay)
1955 udelay(oh->class->sysc->srst_udelay); 1952 udelay(oh->class->sysc->srst_udelay);
1956 1953
1957 c = _wait_softreset_complete(oh); 1954 c = _wait_softreset_complete(oh);
1958 if (c == MAX_MODULE_SOFTRESET_WAIT) 1955 if (c == MAX_MODULE_SOFTRESET_WAIT) {
1959 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", 1956 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1960 oh->name, MAX_MODULE_SOFTRESET_WAIT); 1957 oh->name, MAX_MODULE_SOFTRESET_WAIT);
1961 else 1958 ret = -ETIMEDOUT;
1959 goto dis_opt_clks;
1960 } else {
1962 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); 1961 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
1962 }
1963
1964 ret = _clear_softreset(oh, &v);
1965 if (ret)
1966 goto dis_opt_clks;
1967
1968 _write_sysconfig(v, oh);
1963 1969
1964 /* 1970 /*
1965 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from 1971 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
1966 * _wait_target_ready() or _reset() 1972 * _wait_target_ready() or _reset()
1967 */ 1973 */
1968 1974
1969 ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
1970
1971dis_opt_clks: 1975dis_opt_clks:
1972 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) 1976 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1973 _disable_optional_clocks(oh); 1977 _disable_optional_clocks(oh);
@@ -2791,9 +2795,7 @@ static int __init _alloc_links(struct omap_hwmod_link **ml,
2791 sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; 2795 sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
2792 2796
2793 *sl = NULL; 2797 *sl = NULL;
2794 *ml = alloc_bootmem(sz); 2798 *ml = memblock_virt_alloc(sz, 0);
2795
2796 memset(*ml, 0, sz);
2797 2799
2798 *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); 2800 *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
2799 2801
@@ -2912,9 +2914,7 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
2912 pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", 2914 pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
2913 __func__, sz, max_ls); 2915 __func__, sz, max_ls);
2914 2916
2915 linkspace = alloc_bootmem(sz); 2917 linkspace = memblock_virt_alloc(sz, 0);
2916
2917 memset(linkspace, 0, sz);
2918 2918
2919 return 0; 2919 return 0;
2920} 2920}
@@ -4235,6 +4235,7 @@ void __init omap_hwmod_init(void)
4235 soc_ops.assert_hardreset = _omap2_assert_hardreset; 4235 soc_ops.assert_hardreset = _omap2_assert_hardreset;
4236 soc_ops.deassert_hardreset = _omap2_deassert_hardreset; 4236 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
4237 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; 4237 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
4238 soc_ops.init_clkdm = _init_clkdm;
4238 } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { 4239 } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
4239 soc_ops.enable_module = _omap4_enable_module; 4240 soc_ops.enable_module = _omap4_enable_module;
4240 soc_ops.disable_module = _omap4_disable_module; 4241 soc_ops.disable_module = _omap4_disable_module;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index d8b9d60f854f..2f15979c2e9c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -108,8 +108,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
108/* I2C1 */ 108/* I2C1 */
109static struct omap_hwmod omap2420_i2c1_hwmod = { 109static struct omap_hwmod omap2420_i2c1_hwmod = {
110 .name = "i2c1", 110 .name = "i2c1",
111 .mpu_irqs = omap2_i2c1_mpu_irqs,
112 .sdma_reqs = omap2_i2c1_sdma_reqs,
113 .main_clk = "i2c1_fck", 111 .main_clk = "i2c1_fck",
114 .prcm = { 112 .prcm = {
115 .omap2 = { 113 .omap2 = {
@@ -133,8 +131,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
133/* I2C2 */ 131/* I2C2 */
134static struct omap_hwmod omap2420_i2c2_hwmod = { 132static struct omap_hwmod omap2420_i2c2_hwmod = {
135 .name = "i2c2", 133 .name = "i2c2",
136 .mpu_irqs = omap2_i2c2_mpu_irqs,
137 .sdma_reqs = omap2_i2c2_sdma_reqs,
138 .main_clk = "i2c2_fck", 134 .main_clk = "i2c2_fck",
139 .prcm = { 135 .prcm = {
140 .omap2 = { 136 .omap2 = {
@@ -179,16 +175,9 @@ static struct omap_mbox_pdata omap2420_mailbox_attrs = {
179 .info = omap2420_mailbox_info, 175 .info = omap2420_mailbox_info,
180}; 176};
181 177
182static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
183 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
184 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
185 { .irq = -1 },
186};
187
188static struct omap_hwmod omap2420_mailbox_hwmod = { 178static struct omap_hwmod omap2420_mailbox_hwmod = {
189 .name = "mailbox", 179 .name = "mailbox",
190 .class = &omap2xxx_mailbox_hwmod_class, 180 .class = &omap2xxx_mailbox_hwmod_class,
191 .mpu_irqs = omap2420_mailbox_irqs,
192 .main_clk = "mailboxes_ick", 181 .main_clk = "mailboxes_ick",
193 .prcm = { 182 .prcm = {
194 .omap2 = { 183 .omap2 = {
@@ -217,17 +206,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
217}; 206};
218 207
219/* mcbsp1 */ 208/* mcbsp1 */
220static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
221 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
222 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
223 { .irq = -1 },
224};
225
226static struct omap_hwmod omap2420_mcbsp1_hwmod = { 209static struct omap_hwmod omap2420_mcbsp1_hwmod = {
227 .name = "mcbsp1", 210 .name = "mcbsp1",
228 .class = &omap2420_mcbsp_hwmod_class, 211 .class = &omap2420_mcbsp_hwmod_class,
229 .mpu_irqs = omap2420_mcbsp1_irqs,
230 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
231 .main_clk = "mcbsp1_fck", 212 .main_clk = "mcbsp1_fck",
232 .prcm = { 213 .prcm = {
233 .omap2 = { 214 .omap2 = {
@@ -243,17 +224,9 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
243}; 224};
244 225
245/* mcbsp2 */ 226/* mcbsp2 */
246static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
247 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
248 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
249 { .irq = -1 },
250};
251
252static struct omap_hwmod omap2420_mcbsp2_hwmod = { 227static struct omap_hwmod omap2420_mcbsp2_hwmod = {
253 .name = "mcbsp2", 228 .name = "mcbsp2",
254 .class = &omap2420_mcbsp_hwmod_class, 229 .class = &omap2420_mcbsp_hwmod_class,
255 .mpu_irqs = omap2420_mcbsp2_irqs,
256 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
257 .main_clk = "mcbsp2_fck", 230 .main_clk = "mcbsp2_fck",
258 .prcm = { 231 .prcm = {
259 .omap2 = { 232 .omap2 = {
@@ -283,22 +256,9 @@ static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
283}; 256};
284 257
285/* msdi1 */ 258/* msdi1 */
286static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
287 { .irq = 83 + OMAP_INTC_START, },
288 { .irq = -1 },
289};
290
291static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
292 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
293 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
294 { .dma_req = -1 }
295};
296
297static struct omap_hwmod omap2420_msdi1_hwmod = { 259static struct omap_hwmod omap2420_msdi1_hwmod = {
298 .name = "msdi1", 260 .name = "msdi1",
299 .class = &omap2420_msdi_hwmod_class, 261 .class = &omap2420_msdi_hwmod_class,
300 .mpu_irqs = omap2420_msdi1_irqs,
301 .sdma_reqs = omap2420_msdi1_sdma_reqs,
302 .main_clk = "mmc_fck", 262 .main_clk = "mmc_fck",
303 .prcm = { 263 .prcm = {
304 .omap2 = { 264 .omap2 = {
@@ -315,7 +275,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = {
315/* HDQ1W/1-wire */ 275/* HDQ1W/1-wire */
316static struct omap_hwmod omap2420_hdq1w_hwmod = { 276static struct omap_hwmod omap2420_hdq1w_hwmod = {
317 .name = "hdq1w", 277 .name = "hdq1w",
318 .mpu_irqs = omap2_hdq1w_mpu_irqs,
319 .main_clk = "hdq_fck", 278 .main_clk = "hdq_fck",
320 .prcm = { 279 .prcm = {
321 .omap2 = { 280 .omap2 = {
@@ -338,7 +297,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
338 .master = &omap2xxx_l4_core_hwmod, 297 .master = &omap2xxx_l4_core_hwmod,
339 .slave = &omap2420_i2c1_hwmod, 298 .slave = &omap2420_i2c1_hwmod,
340 .clk = "i2c1_ick", 299 .clk = "i2c1_ick",
341 .addr = omap2_i2c1_addr_space,
342 .user = OCP_USER_MPU | OCP_USER_SDMA, 300 .user = OCP_USER_MPU | OCP_USER_SDMA,
343}; 301};
344 302
@@ -347,7 +305,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
347 .master = &omap2xxx_l4_core_hwmod, 305 .master = &omap2xxx_l4_core_hwmod,
348 .slave = &omap2420_i2c2_hwmod, 306 .slave = &omap2420_i2c2_hwmod,
349 .clk = "i2c2_ick", 307 .clk = "i2c2_ick",
350 .addr = omap2_i2c2_addr_space,
351 .user = OCP_USER_MPU | OCP_USER_SDMA, 308 .user = OCP_USER_MPU | OCP_USER_SDMA,
352}; 309};
353 310
@@ -367,111 +324,51 @@ static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
367 .user = OCP_USER_MPU | OCP_USER_SDMA, 324 .user = OCP_USER_MPU | OCP_USER_SDMA,
368}; 325};
369 326
370static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
371 {
372 .pa_start = 0x48028000,
373 .pa_end = 0x48028000 + SZ_1K - 1,
374 .flags = ADDR_TYPE_RT
375 },
376 { }
377};
378
379/* l4_wkup -> timer1 */ 327/* l4_wkup -> timer1 */
380static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { 328static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
381 .master = &omap2xxx_l4_wkup_hwmod, 329 .master = &omap2xxx_l4_wkup_hwmod,
382 .slave = &omap2xxx_timer1_hwmod, 330 .slave = &omap2xxx_timer1_hwmod,
383 .clk = "gpt1_ick", 331 .clk = "gpt1_ick",
384 .addr = omap2420_timer1_addrs,
385 .user = OCP_USER_MPU | OCP_USER_SDMA, 332 .user = OCP_USER_MPU | OCP_USER_SDMA,
386}; 333};
387 334
388/* l4_wkup -> wd_timer2 */ 335/* l4_wkup -> wd_timer2 */
389static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
390 {
391 .pa_start = 0x48022000,
392 .pa_end = 0x4802207f,
393 .flags = ADDR_TYPE_RT
394 },
395 { }
396};
397
398static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 336static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
399 .master = &omap2xxx_l4_wkup_hwmod, 337 .master = &omap2xxx_l4_wkup_hwmod,
400 .slave = &omap2xxx_wd_timer2_hwmod, 338 .slave = &omap2xxx_wd_timer2_hwmod,
401 .clk = "mpu_wdt_ick", 339 .clk = "mpu_wdt_ick",
402 .addr = omap2420_wd_timer2_addrs,
403 .user = OCP_USER_MPU | OCP_USER_SDMA, 340 .user = OCP_USER_MPU | OCP_USER_SDMA,
404}; 341};
405 342
406/* l4_wkup -> gpio1 */ 343/* l4_wkup -> gpio1 */
407static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
408 {
409 .pa_start = 0x48018000,
410 .pa_end = 0x480181ff,
411 .flags = ADDR_TYPE_RT
412 },
413 { }
414};
415
416static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 344static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
417 .master = &omap2xxx_l4_wkup_hwmod, 345 .master = &omap2xxx_l4_wkup_hwmod,
418 .slave = &omap2xxx_gpio1_hwmod, 346 .slave = &omap2xxx_gpio1_hwmod,
419 .clk = "gpios_ick", 347 .clk = "gpios_ick",
420 .addr = omap2420_gpio1_addr_space,
421 .user = OCP_USER_MPU | OCP_USER_SDMA, 348 .user = OCP_USER_MPU | OCP_USER_SDMA,
422}; 349};
423 350
424/* l4_wkup -> gpio2 */ 351/* l4_wkup -> gpio2 */
425static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
426 {
427 .pa_start = 0x4801a000,
428 .pa_end = 0x4801a1ff,
429 .flags = ADDR_TYPE_RT
430 },
431 { }
432};
433
434static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 352static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
435 .master = &omap2xxx_l4_wkup_hwmod, 353 .master = &omap2xxx_l4_wkup_hwmod,
436 .slave = &omap2xxx_gpio2_hwmod, 354 .slave = &omap2xxx_gpio2_hwmod,
437 .clk = "gpios_ick", 355 .clk = "gpios_ick",
438 .addr = omap2420_gpio2_addr_space,
439 .user = OCP_USER_MPU | OCP_USER_SDMA, 356 .user = OCP_USER_MPU | OCP_USER_SDMA,
440}; 357};
441 358
442/* l4_wkup -> gpio3 */ 359/* l4_wkup -> gpio3 */
443static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
444 {
445 .pa_start = 0x4801c000,
446 .pa_end = 0x4801c1ff,
447 .flags = ADDR_TYPE_RT
448 },
449 { }
450};
451
452static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 360static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
453 .master = &omap2xxx_l4_wkup_hwmod, 361 .master = &omap2xxx_l4_wkup_hwmod,
454 .slave = &omap2xxx_gpio3_hwmod, 362 .slave = &omap2xxx_gpio3_hwmod,
455 .clk = "gpios_ick", 363 .clk = "gpios_ick",
456 .addr = omap2420_gpio3_addr_space,
457 .user = OCP_USER_MPU | OCP_USER_SDMA, 364 .user = OCP_USER_MPU | OCP_USER_SDMA,
458}; 365};
459 366
460/* l4_wkup -> gpio4 */ 367/* l4_wkup -> gpio4 */
461static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
462 {
463 .pa_start = 0x4801e000,
464 .pa_end = 0x4801e1ff,
465 .flags = ADDR_TYPE_RT
466 },
467 { }
468};
469
470static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 368static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
471 .master = &omap2xxx_l4_wkup_hwmod, 369 .master = &omap2xxx_l4_wkup_hwmod,
472 .slave = &omap2xxx_gpio4_hwmod, 370 .slave = &omap2xxx_gpio4_hwmod,
473 .clk = "gpios_ick", 371 .clk = "gpios_ick",
474 .addr = omap2420_gpio4_addr_space,
475 .user = OCP_USER_MPU | OCP_USER_SDMA, 372 .user = OCP_USER_MPU | OCP_USER_SDMA,
476}; 373};
477 374
@@ -496,7 +393,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
496static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 393static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
497 .master = &omap2xxx_l4_core_hwmod, 394 .master = &omap2xxx_l4_core_hwmod,
498 .slave = &omap2420_mailbox_hwmod, 395 .slave = &omap2420_mailbox_hwmod,
499 .addr = omap2_mailbox_addrs,
500 .user = OCP_USER_MPU | OCP_USER_SDMA, 396 .user = OCP_USER_MPU | OCP_USER_SDMA,
501}; 397};
502 398
@@ -505,7 +401,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
505 .master = &omap2xxx_l4_core_hwmod, 401 .master = &omap2xxx_l4_core_hwmod,
506 .slave = &omap2420_mcbsp1_hwmod, 402 .slave = &omap2420_mcbsp1_hwmod,
507 .clk = "mcbsp1_ick", 403 .clk = "mcbsp1_ick",
508 .addr = omap2_mcbsp1_addrs,
509 .user = OCP_USER_MPU | OCP_USER_SDMA, 404 .user = OCP_USER_MPU | OCP_USER_SDMA,
510}; 405};
511 406
@@ -514,25 +409,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
514 .master = &omap2xxx_l4_core_hwmod, 409 .master = &omap2xxx_l4_core_hwmod,
515 .slave = &omap2420_mcbsp2_hwmod, 410 .slave = &omap2420_mcbsp2_hwmod,
516 .clk = "mcbsp2_ick", 411 .clk = "mcbsp2_ick",
517 .addr = omap2xxx_mcbsp2_addrs,
518 .user = OCP_USER_MPU | OCP_USER_SDMA, 412 .user = OCP_USER_MPU | OCP_USER_SDMA,
519}; 413};
520 414
521static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
522 {
523 .pa_start = 0x4809c000,
524 .pa_end = 0x4809c000 + SZ_128 - 1,
525 .flags = ADDR_TYPE_RT,
526 },
527 { }
528};
529
530/* l4_core -> msdi1 */ 415/* l4_core -> msdi1 */
531static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = { 416static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
532 .master = &omap2xxx_l4_core_hwmod, 417 .master = &omap2xxx_l4_core_hwmod,
533 .slave = &omap2420_msdi1_hwmod, 418 .slave = &omap2420_msdi1_hwmod,
534 .clk = "mmc_ick", 419 .clk = "mmc_ick",
535 .addr = omap2420_msdi1_addrs,
536 .user = OCP_USER_MPU | OCP_USER_SDMA, 420 .user = OCP_USER_MPU | OCP_USER_SDMA,
537}; 421};
538 422
@@ -541,36 +425,16 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
541 .master = &omap2xxx_l4_core_hwmod, 425 .master = &omap2xxx_l4_core_hwmod,
542 .slave = &omap2420_hdq1w_hwmod, 426 .slave = &omap2420_hdq1w_hwmod,
543 .clk = "hdq_ick", 427 .clk = "hdq_ick",
544 .addr = omap2_hdq1w_addr_space,
545 .user = OCP_USER_MPU | OCP_USER_SDMA, 428 .user = OCP_USER_MPU | OCP_USER_SDMA,
546 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 429 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
547}; 430};
548 431
549 432
550/* l4_wkup -> 32ksync_counter */ 433/* l4_wkup -> 32ksync_counter */
551static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
552 {
553 .pa_start = 0x48004000,
554 .pa_end = 0x4800401f,
555 .flags = ADDR_TYPE_RT
556 },
557 { }
558};
559
560static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
561 {
562 .pa_start = 0x6800a000,
563 .pa_end = 0x6800afff,
564 .flags = ADDR_TYPE_RT
565 },
566 { }
567};
568
569static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = { 434static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
570 .master = &omap2xxx_l4_wkup_hwmod, 435 .master = &omap2xxx_l4_wkup_hwmod,
571 .slave = &omap2xxx_counter_32k_hwmod, 436 .slave = &omap2xxx_counter_32k_hwmod,
572 .clk = "sync_32k_ick", 437 .clk = "sync_32k_ick",
573 .addr = omap2420_counter_32k_addrs,
574 .user = OCP_USER_MPU | OCP_USER_SDMA, 438 .user = OCP_USER_MPU | OCP_USER_SDMA,
575}; 439};
576 440
@@ -578,7 +442,6 @@ static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
578 .master = &omap2xxx_l3_main_hwmod, 442 .master = &omap2xxx_l3_main_hwmod,
579 .slave = &omap2xxx_gpmc_hwmod, 443 .slave = &omap2xxx_gpmc_hwmod,
580 .clk = "core_l3_ck", 444 .clk = "core_l3_ck",
581 .addr = omap2420_gpmc_addrs,
582 .user = OCP_USER_MPU | OCP_USER_SDMA, 445 .user = OCP_USER_MPU | OCP_USER_SDMA,
583}; 446};
584 447
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 5b9083461dc5..6d1b60902179 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -86,8 +86,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
86static struct omap_hwmod omap2430_i2c1_hwmod = { 86static struct omap_hwmod omap2430_i2c1_hwmod = {
87 .name = "i2c1", 87 .name = "i2c1",
88 .flags = HWMOD_16BIT_REG, 88 .flags = HWMOD_16BIT_REG,
89 .mpu_irqs = omap2_i2c1_mpu_irqs,
90 .sdma_reqs = omap2_i2c1_sdma_reqs,
91 .main_clk = "i2chs1_fck", 89 .main_clk = "i2chs1_fck",
92 .prcm = { 90 .prcm = {
93 .omap2 = { 91 .omap2 = {
@@ -114,8 +112,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
114static struct omap_hwmod omap2430_i2c2_hwmod = { 112static struct omap_hwmod omap2430_i2c2_hwmod = {
115 .name = "i2c2", 113 .name = "i2c2",
116 .flags = HWMOD_16BIT_REG, 114 .flags = HWMOD_16BIT_REG,
117 .mpu_irqs = omap2_i2c2_mpu_irqs,
118 .sdma_reqs = omap2_i2c2_sdma_reqs,
119 .main_clk = "i2chs2_fck", 115 .main_clk = "i2chs2_fck",
120 .prcm = { 116 .prcm = {
121 .omap2 = { 117 .omap2 = {
@@ -131,15 +127,9 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
131}; 127};
132 128
133/* gpio5 */ 129/* gpio5 */
134static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
135 { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
136 { .irq = -1 },
137};
138
139static struct omap_hwmod omap2430_gpio5_hwmod = { 130static struct omap_hwmod omap2430_gpio5_hwmod = {
140 .name = "gpio5", 131 .name = "gpio5",
141 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 132 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
142 .mpu_irqs = omap243x_gpio5_irqs,
143 .main_clk = "gpio5_fck", 133 .main_clk = "gpio5_fck",
144 .prcm = { 134 .prcm = {
145 .omap2 = { 135 .omap2 = {
@@ -182,15 +172,9 @@ static struct omap_mbox_pdata omap2430_mailbox_attrs = {
182 .info = omap2430_mailbox_info, 172 .info = omap2430_mailbox_info,
183}; 173};
184 174
185static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
186 { .irq = 26 + OMAP_INTC_START, },
187 { .irq = -1 },
188};
189
190static struct omap_hwmod omap2430_mailbox_hwmod = { 175static struct omap_hwmod omap2430_mailbox_hwmod = {
191 .name = "mailbox", 176 .name = "mailbox",
192 .class = &omap2xxx_mailbox_hwmod_class, 177 .class = &omap2xxx_mailbox_hwmod_class,
193 .mpu_irqs = omap2430_mailbox_irqs,
194 .main_clk = "mailboxes_ick", 178 .main_clk = "mailboxes_ick",
195 .prcm = { 179 .prcm = {
196 .omap2 = { 180 .omap2 = {
@@ -205,27 +189,12 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
205}; 189};
206 190
207/* mcspi3 */ 191/* mcspi3 */
208static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
209 { .irq = 91 + OMAP_INTC_START, },
210 { .irq = -1 },
211};
212
213static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
214 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
215 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
216 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
217 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
218 { .dma_req = -1 }
219};
220
221static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 192static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
222 .num_chipselect = 2, 193 .num_chipselect = 2,
223}; 194};
224 195
225static struct omap_hwmod omap2430_mcspi3_hwmod = { 196static struct omap_hwmod omap2430_mcspi3_hwmod = {
226 .name = "mcspi3", 197 .name = "mcspi3",
227 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
228 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
229 .main_clk = "mcspi3_fck", 198 .main_clk = "mcspi3_fck",
230 .prcm = { 199 .prcm = {
231 .omap2 = { 200 .omap2 = {
@@ -259,16 +228,8 @@ static struct omap_hwmod_class usbotg_class = {
259}; 228};
260 229
261/* usb_otg_hs */ 230/* usb_otg_hs */
262static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
263
264 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
265 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
266 { .irq = -1 },
267};
268
269static struct omap_hwmod omap2430_usbhsotg_hwmod = { 231static struct omap_hwmod omap2430_usbhsotg_hwmod = {
270 .name = "usb_otg_hs", 232 .name = "usb_otg_hs",
271 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
272 .main_clk = "usbhs_ick", 233 .main_clk = "usbhs_ick",
273 .prcm = { 234 .prcm = {
274 .omap2 = { 235 .omap2 = {
@@ -313,19 +274,9 @@ static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
313}; 274};
314 275
315/* mcbsp1 */ 276/* mcbsp1 */
316static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
317 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
318 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
319 { .name = "ovr", .irq = 61 + OMAP_INTC_START, },
320 { .name = "common", .irq = 64 + OMAP_INTC_START, },
321 { .irq = -1 },
322};
323
324static struct omap_hwmod omap2430_mcbsp1_hwmod = { 277static struct omap_hwmod omap2430_mcbsp1_hwmod = {
325 .name = "mcbsp1", 278 .name = "mcbsp1",
326 .class = &omap2430_mcbsp_hwmod_class, 279 .class = &omap2430_mcbsp_hwmod_class,
327 .mpu_irqs = omap2430_mcbsp1_irqs,
328 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
329 .main_clk = "mcbsp1_fck", 280 .main_clk = "mcbsp1_fck",
330 .prcm = { 281 .prcm = {
331 .omap2 = { 282 .omap2 = {
@@ -341,18 +292,9 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
341}; 292};
342 293
343/* mcbsp2 */ 294/* mcbsp2 */
344static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
345 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
346 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
347 { .name = "common", .irq = 16 + OMAP_INTC_START, },
348 { .irq = -1 },
349};
350
351static struct omap_hwmod omap2430_mcbsp2_hwmod = { 295static struct omap_hwmod omap2430_mcbsp2_hwmod = {
352 .name = "mcbsp2", 296 .name = "mcbsp2",
353 .class = &omap2430_mcbsp_hwmod_class, 297 .class = &omap2430_mcbsp_hwmod_class,
354 .mpu_irqs = omap2430_mcbsp2_irqs,
355 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
356 .main_clk = "mcbsp2_fck", 298 .main_clk = "mcbsp2_fck",
357 .prcm = { 299 .prcm = {
358 .omap2 = { 300 .omap2 = {
@@ -368,18 +310,9 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
368}; 310};
369 311
370/* mcbsp3 */ 312/* mcbsp3 */
371static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
372 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
373 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
374 { .name = "common", .irq = 17 + OMAP_INTC_START, },
375 { .irq = -1 },
376};
377
378static struct omap_hwmod omap2430_mcbsp3_hwmod = { 313static struct omap_hwmod omap2430_mcbsp3_hwmod = {
379 .name = "mcbsp3", 314 .name = "mcbsp3",
380 .class = &omap2430_mcbsp_hwmod_class, 315 .class = &omap2430_mcbsp_hwmod_class,
381 .mpu_irqs = omap2430_mcbsp3_irqs,
382 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
383 .main_clk = "mcbsp3_fck", 316 .main_clk = "mcbsp3_fck",
384 .prcm = { 317 .prcm = {
385 .omap2 = { 318 .omap2 = {
@@ -395,24 +328,9 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
395}; 328};
396 329
397/* mcbsp4 */ 330/* mcbsp4 */
398static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
399 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
400 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
401 { .name = "common", .irq = 18 + OMAP_INTC_START, },
402 { .irq = -1 },
403};
404
405static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
406 { .name = "rx", .dma_req = 20 },
407 { .name = "tx", .dma_req = 19 },
408 { .dma_req = -1 }
409};
410
411static struct omap_hwmod omap2430_mcbsp4_hwmod = { 331static struct omap_hwmod omap2430_mcbsp4_hwmod = {
412 .name = "mcbsp4", 332 .name = "mcbsp4",
413 .class = &omap2430_mcbsp_hwmod_class, 333 .class = &omap2430_mcbsp_hwmod_class,
414 .mpu_irqs = omap2430_mcbsp4_irqs,
415 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
416 .main_clk = "mcbsp4_fck", 334 .main_clk = "mcbsp4_fck",
417 .prcm = { 335 .prcm = {
418 .omap2 = { 336 .omap2 = {
@@ -428,24 +346,9 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
428}; 346};
429 347
430/* mcbsp5 */ 348/* mcbsp5 */
431static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
432 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
433 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
434 { .name = "common", .irq = 19 + OMAP_INTC_START, },
435 { .irq = -1 },
436};
437
438static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
439 { .name = "rx", .dma_req = 22 },
440 { .name = "tx", .dma_req = 21 },
441 { .dma_req = -1 }
442};
443
444static struct omap_hwmod omap2430_mcbsp5_hwmod = { 349static struct omap_hwmod omap2430_mcbsp5_hwmod = {
445 .name = "mcbsp5", 350 .name = "mcbsp5",
446 .class = &omap2430_mcbsp_hwmod_class, 351 .class = &omap2430_mcbsp_hwmod_class,
447 .mpu_irqs = omap2430_mcbsp5_irqs,
448 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
449 .main_clk = "mcbsp5_fck", 352 .main_clk = "mcbsp5_fck",
450 .prcm = { 353 .prcm = {
451 .omap2 = { 354 .omap2 = {
@@ -478,17 +381,6 @@ static struct omap_hwmod_class omap2430_mmc_class = {
478}; 381};
479 382
480/* MMC/SD/SDIO1 */ 383/* MMC/SD/SDIO1 */
481static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
482 { .irq = 83 + OMAP_INTC_START, },
483 { .irq = -1 },
484};
485
486static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
487 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
488 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
489 { .dma_req = -1 }
490};
491
492static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 384static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
493 { .role = "dbck", .clk = "mmchsdb1_fck" }, 385 { .role = "dbck", .clk = "mmchsdb1_fck" },
494}; 386};
@@ -500,8 +392,6 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
500static struct omap_hwmod omap2430_mmc1_hwmod = { 392static struct omap_hwmod omap2430_mmc1_hwmod = {
501 .name = "mmc1", 393 .name = "mmc1",
502 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 394 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
503 .mpu_irqs = omap2430_mmc1_mpu_irqs,
504 .sdma_reqs = omap2430_mmc1_sdma_reqs,
505 .opt_clks = omap2430_mmc1_opt_clks, 395 .opt_clks = omap2430_mmc1_opt_clks,
506 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 396 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
507 .main_clk = "mmchs1_fck", 397 .main_clk = "mmchs1_fck",
@@ -519,17 +409,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
519}; 409};
520 410
521/* MMC/SD/SDIO2 */ 411/* MMC/SD/SDIO2 */
522static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
523 { .irq = 86 + OMAP_INTC_START, },
524 { .irq = -1 },
525};
526
527static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
528 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
529 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
530 { .dma_req = -1 }
531};
532
533static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 412static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
534 { .role = "dbck", .clk = "mmchsdb2_fck" }, 413 { .role = "dbck", .clk = "mmchsdb2_fck" },
535}; 414};
@@ -537,8 +416,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
537static struct omap_hwmod omap2430_mmc2_hwmod = { 416static struct omap_hwmod omap2430_mmc2_hwmod = {
538 .name = "mmc2", 417 .name = "mmc2",
539 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 418 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
540 .mpu_irqs = omap2430_mmc2_mpu_irqs,
541 .sdma_reqs = omap2430_mmc2_sdma_reqs,
542 .opt_clks = omap2430_mmc2_opt_clks, 419 .opt_clks = omap2430_mmc2_opt_clks,
543 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 420 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
544 .main_clk = "mmchs2_fck", 421 .main_clk = "mmchs2_fck",
@@ -557,7 +434,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
557/* HDQ1W/1-wire */ 434/* HDQ1W/1-wire */
558static struct omap_hwmod omap2430_hdq1w_hwmod = { 435static struct omap_hwmod omap2430_hdq1w_hwmod = {
559 .name = "hdq1w", 436 .name = "hdq1w",
560 .mpu_irqs = omap2_hdq1w_mpu_irqs,
561 .main_clk = "hdq_fck", 437 .main_clk = "hdq_fck",
562 .prcm = { 438 .prcm = {
563 .omap2 = { 439 .omap2 = {
@@ -589,7 +465,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
589 .master = &omap2xxx_l4_core_hwmod, 465 .master = &omap2xxx_l4_core_hwmod,
590 .slave = &omap2430_i2c1_hwmod, 466 .slave = &omap2430_i2c1_hwmod,
591 .clk = "i2c1_ick", 467 .clk = "i2c1_ick",
592 .addr = omap2_i2c1_addr_space,
593 .user = OCP_USER_MPU | OCP_USER_SDMA, 468 .user = OCP_USER_MPU | OCP_USER_SDMA,
594}; 469};
595 470
@@ -598,25 +473,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
598 .master = &omap2xxx_l4_core_hwmod, 473 .master = &omap2xxx_l4_core_hwmod,
599 .slave = &omap2430_i2c2_hwmod, 474 .slave = &omap2430_i2c2_hwmod,
600 .clk = "i2c2_ick", 475 .clk = "i2c2_ick",
601 .addr = omap2_i2c2_addr_space,
602 .user = OCP_USER_MPU | OCP_USER_SDMA, 476 .user = OCP_USER_MPU | OCP_USER_SDMA,
603}; 477};
604 478
605static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
606 {
607 .pa_start = OMAP243X_HS_BASE,
608 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
609 .flags = ADDR_TYPE_RT
610 },
611 { }
612};
613
614/* l4_core ->usbhsotg interface */ 479/* l4_core ->usbhsotg interface */
615static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 480static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
616 .master = &omap2xxx_l4_core_hwmod, 481 .master = &omap2xxx_l4_core_hwmod,
617 .slave = &omap2430_usbhsotg_hwmod, 482 .slave = &omap2430_usbhsotg_hwmod,
618 .clk = "usb_l4_ick", 483 .clk = "usb_l4_ick",
619 .addr = omap2430_usbhsotg_addrs,
620 .user = OCP_USER_MPU, 484 .user = OCP_USER_MPU,
621}; 485};
622 486
@@ -625,7 +489,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
625 .master = &omap2xxx_l4_core_hwmod, 489 .master = &omap2xxx_l4_core_hwmod,
626 .slave = &omap2430_mmc1_hwmod, 490 .slave = &omap2430_mmc1_hwmod,
627 .clk = "mmchs1_ick", 491 .clk = "mmchs1_ick",
628 .addr = omap2430_mmc1_addr_space,
629 .user = OCP_USER_MPU | OCP_USER_SDMA, 492 .user = OCP_USER_MPU | OCP_USER_SDMA,
630}; 493};
631 494
@@ -634,7 +497,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
634 .master = &omap2xxx_l4_core_hwmod, 497 .master = &omap2xxx_l4_core_hwmod,
635 .slave = &omap2430_mmc2_hwmod, 498 .slave = &omap2430_mmc2_hwmod,
636 .clk = "mmchs2_ick", 499 .clk = "mmchs2_ick",
637 .addr = omap2430_mmc2_addr_space,
638 .user = OCP_USER_MPU | OCP_USER_SDMA, 500 .user = OCP_USER_MPU | OCP_USER_SDMA,
639}; 501};
640 502
@@ -643,7 +505,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
643 .master = &omap2xxx_l4_core_hwmod, 505 .master = &omap2xxx_l4_core_hwmod,
644 .slave = &omap2430_mcspi3_hwmod, 506 .slave = &omap2430_mcspi3_hwmod,
645 .clk = "mcspi3_ick", 507 .clk = "mcspi3_ick",
646 .addr = omap2430_mcspi3_addr_space,
647 .user = OCP_USER_MPU | OCP_USER_SDMA, 508 .user = OCP_USER_MPU | OCP_USER_SDMA,
648}; 509};
649 510
@@ -655,129 +516,59 @@ static struct omap_hwmod_ocp_if omap2430_l3__iva = {
655 .user = OCP_USER_MPU | OCP_USER_SDMA, 516 .user = OCP_USER_MPU | OCP_USER_SDMA,
656}; 517};
657 518
658static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
659 {
660 .pa_start = 0x49018000,
661 .pa_end = 0x49018000 + SZ_1K - 1,
662 .flags = ADDR_TYPE_RT
663 },
664 { }
665};
666
667/* l4_wkup -> timer1 */ 519/* l4_wkup -> timer1 */
668static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 520static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
669 .master = &omap2xxx_l4_wkup_hwmod, 521 .master = &omap2xxx_l4_wkup_hwmod,
670 .slave = &omap2xxx_timer1_hwmod, 522 .slave = &omap2xxx_timer1_hwmod,
671 .clk = "gpt1_ick", 523 .clk = "gpt1_ick",
672 .addr = omap2430_timer1_addrs,
673 .user = OCP_USER_MPU | OCP_USER_SDMA, 524 .user = OCP_USER_MPU | OCP_USER_SDMA,
674}; 525};
675 526
676/* l4_wkup -> wd_timer2 */ 527/* l4_wkup -> wd_timer2 */
677static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
678 {
679 .pa_start = 0x49016000,
680 .pa_end = 0x4901607f,
681 .flags = ADDR_TYPE_RT
682 },
683 { }
684};
685
686static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 528static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
687 .master = &omap2xxx_l4_wkup_hwmod, 529 .master = &omap2xxx_l4_wkup_hwmod,
688 .slave = &omap2xxx_wd_timer2_hwmod, 530 .slave = &omap2xxx_wd_timer2_hwmod,
689 .clk = "mpu_wdt_ick", 531 .clk = "mpu_wdt_ick",
690 .addr = omap2430_wd_timer2_addrs,
691 .user = OCP_USER_MPU | OCP_USER_SDMA, 532 .user = OCP_USER_MPU | OCP_USER_SDMA,
692}; 533};
693 534
694/* l4_wkup -> gpio1 */ 535/* l4_wkup -> gpio1 */
695static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
696 {
697 .pa_start = 0x4900C000,
698 .pa_end = 0x4900C1ff,
699 .flags = ADDR_TYPE_RT
700 },
701 { }
702};
703
704static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 536static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
705 .master = &omap2xxx_l4_wkup_hwmod, 537 .master = &omap2xxx_l4_wkup_hwmod,
706 .slave = &omap2xxx_gpio1_hwmod, 538 .slave = &omap2xxx_gpio1_hwmod,
707 .clk = "gpios_ick", 539 .clk = "gpios_ick",
708 .addr = omap2430_gpio1_addr_space,
709 .user = OCP_USER_MPU | OCP_USER_SDMA, 540 .user = OCP_USER_MPU | OCP_USER_SDMA,
710}; 541};
711 542
712/* l4_wkup -> gpio2 */ 543/* l4_wkup -> gpio2 */
713static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
714 {
715 .pa_start = 0x4900E000,
716 .pa_end = 0x4900E1ff,
717 .flags = ADDR_TYPE_RT
718 },
719 { }
720};
721
722static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 544static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
723 .master = &omap2xxx_l4_wkup_hwmod, 545 .master = &omap2xxx_l4_wkup_hwmod,
724 .slave = &omap2xxx_gpio2_hwmod, 546 .slave = &omap2xxx_gpio2_hwmod,
725 .clk = "gpios_ick", 547 .clk = "gpios_ick",
726 .addr = omap2430_gpio2_addr_space,
727 .user = OCP_USER_MPU | OCP_USER_SDMA, 548 .user = OCP_USER_MPU | OCP_USER_SDMA,
728}; 549};
729 550
730/* l4_wkup -> gpio3 */ 551/* l4_wkup -> gpio3 */
731static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
732 {
733 .pa_start = 0x49010000,
734 .pa_end = 0x490101ff,
735 .flags = ADDR_TYPE_RT
736 },
737 { }
738};
739
740static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 552static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
741 .master = &omap2xxx_l4_wkup_hwmod, 553 .master = &omap2xxx_l4_wkup_hwmod,
742 .slave = &omap2xxx_gpio3_hwmod, 554 .slave = &omap2xxx_gpio3_hwmod,
743 .clk = "gpios_ick", 555 .clk = "gpios_ick",
744 .addr = omap2430_gpio3_addr_space,
745 .user = OCP_USER_MPU | OCP_USER_SDMA, 556 .user = OCP_USER_MPU | OCP_USER_SDMA,
746}; 557};
747 558
748/* l4_wkup -> gpio4 */ 559/* l4_wkup -> gpio4 */
749static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
750 {
751 .pa_start = 0x49012000,
752 .pa_end = 0x490121ff,
753 .flags = ADDR_TYPE_RT
754 },
755 { }
756};
757
758static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 560static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
759 .master = &omap2xxx_l4_wkup_hwmod, 561 .master = &omap2xxx_l4_wkup_hwmod,
760 .slave = &omap2xxx_gpio4_hwmod, 562 .slave = &omap2xxx_gpio4_hwmod,
761 .clk = "gpios_ick", 563 .clk = "gpios_ick",
762 .addr = omap2430_gpio4_addr_space,
763 .user = OCP_USER_MPU | OCP_USER_SDMA, 564 .user = OCP_USER_MPU | OCP_USER_SDMA,
764}; 565};
765 566
766/* l4_core -> gpio5 */ 567/* l4_core -> gpio5 */
767static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
768 {
769 .pa_start = 0x480B6000,
770 .pa_end = 0x480B61ff,
771 .flags = ADDR_TYPE_RT
772 },
773 { }
774};
775
776static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 568static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
777 .master = &omap2xxx_l4_core_hwmod, 569 .master = &omap2xxx_l4_core_hwmod,
778 .slave = &omap2430_gpio5_hwmod, 570 .slave = &omap2430_gpio5_hwmod,
779 .clk = "gpio5_ick", 571 .clk = "gpio5_ick",
780 .addr = omap2430_gpio5_addr_space,
781 .user = OCP_USER_MPU | OCP_USER_SDMA, 572 .user = OCP_USER_MPU | OCP_USER_SDMA,
782}; 573};
783 574
@@ -802,7 +593,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
802static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 593static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
803 .master = &omap2xxx_l4_core_hwmod, 594 .master = &omap2xxx_l4_core_hwmod,
804 .slave = &omap2430_mailbox_hwmod, 595 .slave = &omap2430_mailbox_hwmod,
805 .addr = omap2_mailbox_addrs,
806 .user = OCP_USER_MPU | OCP_USER_SDMA, 596 .user = OCP_USER_MPU | OCP_USER_SDMA,
807}; 597};
808 598
@@ -811,7 +601,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
811 .master = &omap2xxx_l4_core_hwmod, 601 .master = &omap2xxx_l4_core_hwmod,
812 .slave = &omap2430_mcbsp1_hwmod, 602 .slave = &omap2430_mcbsp1_hwmod,
813 .clk = "mcbsp1_ick", 603 .clk = "mcbsp1_ick",
814 .addr = omap2_mcbsp1_addrs,
815 .user = OCP_USER_MPU | OCP_USER_SDMA, 604 .user = OCP_USER_MPU | OCP_USER_SDMA,
816}; 605};
817 606
@@ -820,64 +609,30 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
820 .master = &omap2xxx_l4_core_hwmod, 609 .master = &omap2xxx_l4_core_hwmod,
821 .slave = &omap2430_mcbsp2_hwmod, 610 .slave = &omap2430_mcbsp2_hwmod,
822 .clk = "mcbsp2_ick", 611 .clk = "mcbsp2_ick",
823 .addr = omap2xxx_mcbsp2_addrs,
824 .user = OCP_USER_MPU | OCP_USER_SDMA, 612 .user = OCP_USER_MPU | OCP_USER_SDMA,
825}; 613};
826 614
827static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
828 {
829 .name = "mpu",
830 .pa_start = 0x4808C000,
831 .pa_end = 0x4808C0ff,
832 .flags = ADDR_TYPE_RT
833 },
834 { }
835};
836
837/* l4_core -> mcbsp3 */ 615/* l4_core -> mcbsp3 */
838static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { 616static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
839 .master = &omap2xxx_l4_core_hwmod, 617 .master = &omap2xxx_l4_core_hwmod,
840 .slave = &omap2430_mcbsp3_hwmod, 618 .slave = &omap2430_mcbsp3_hwmod,
841 .clk = "mcbsp3_ick", 619 .clk = "mcbsp3_ick",
842 .addr = omap2430_mcbsp3_addrs,
843 .user = OCP_USER_MPU | OCP_USER_SDMA, 620 .user = OCP_USER_MPU | OCP_USER_SDMA,
844}; 621};
845 622
846static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
847 {
848 .name = "mpu",
849 .pa_start = 0x4808E000,
850 .pa_end = 0x4808E0ff,
851 .flags = ADDR_TYPE_RT
852 },
853 { }
854};
855
856/* l4_core -> mcbsp4 */ 623/* l4_core -> mcbsp4 */
857static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { 624static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
858 .master = &omap2xxx_l4_core_hwmod, 625 .master = &omap2xxx_l4_core_hwmod,
859 .slave = &omap2430_mcbsp4_hwmod, 626 .slave = &omap2430_mcbsp4_hwmod,
860 .clk = "mcbsp4_ick", 627 .clk = "mcbsp4_ick",
861 .addr = omap2430_mcbsp4_addrs,
862 .user = OCP_USER_MPU | OCP_USER_SDMA, 628 .user = OCP_USER_MPU | OCP_USER_SDMA,
863}; 629};
864 630
865static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
866 {
867 .name = "mpu",
868 .pa_start = 0x48096000,
869 .pa_end = 0x480960ff,
870 .flags = ADDR_TYPE_RT
871 },
872 { }
873};
874
875/* l4_core -> mcbsp5 */ 631/* l4_core -> mcbsp5 */
876static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { 632static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
877 .master = &omap2xxx_l4_core_hwmod, 633 .master = &omap2xxx_l4_core_hwmod,
878 .slave = &omap2430_mcbsp5_hwmod, 634 .slave = &omap2430_mcbsp5_hwmod,
879 .clk = "mcbsp5_ick", 635 .clk = "mcbsp5_ick",
880 .addr = omap2430_mcbsp5_addrs,
881 .user = OCP_USER_MPU | OCP_USER_SDMA, 636 .user = OCP_USER_MPU | OCP_USER_SDMA,
882}; 637};
883 638
@@ -886,35 +641,15 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
886 .master = &omap2xxx_l4_core_hwmod, 641 .master = &omap2xxx_l4_core_hwmod,
887 .slave = &omap2430_hdq1w_hwmod, 642 .slave = &omap2430_hdq1w_hwmod,
888 .clk = "hdq_ick", 643 .clk = "hdq_ick",
889 .addr = omap2_hdq1w_addr_space,
890 .user = OCP_USER_MPU | OCP_USER_SDMA, 644 .user = OCP_USER_MPU | OCP_USER_SDMA,
891 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 645 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
892}; 646};
893 647
894/* l4_wkup -> 32ksync_counter */ 648/* l4_wkup -> 32ksync_counter */
895static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
896 {
897 .pa_start = 0x49020000,
898 .pa_end = 0x4902001f,
899 .flags = ADDR_TYPE_RT
900 },
901 { }
902};
903
904static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
905 {
906 .pa_start = 0x6e000000,
907 .pa_end = 0x6e000fff,
908 .flags = ADDR_TYPE_RT
909 },
910 { }
911};
912
913static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { 649static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
914 .master = &omap2xxx_l4_wkup_hwmod, 650 .master = &omap2xxx_l4_wkup_hwmod,
915 .slave = &omap2xxx_counter_32k_hwmod, 651 .slave = &omap2xxx_counter_32k_hwmod,
916 .clk = "sync_32k_ick", 652 .clk = "sync_32k_ick",
917 .addr = omap2430_counter_32k_addrs,
918 .user = OCP_USER_MPU | OCP_USER_SDMA, 653 .user = OCP_USER_MPU | OCP_USER_SDMA,
919}; 654};
920 655
@@ -922,7 +657,6 @@ static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
922 .master = &omap2xxx_l3_main_hwmod, 657 .master = &omap2xxx_l3_main_hwmod,
923 .slave = &omap2xxx_gpmc_hwmod, 658 .slave = &omap2xxx_gpmc_hwmod,
924 .clk = "core_l3_ck", 659 .clk = "core_l3_ck",
925 .addr = omap2430_gpmc_addrs,
926 .user = OCP_USER_MPU | OCP_USER_SDMA, 660 .user = OCP_USER_MPU | OCP_USER_SDMA,
927}; 661};
928 662
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 5fd40d4a989e..656861c29d5c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -20,142 +20,6 @@
20 20
21#include "omap_hwmod_common_data.h" 21#include "omap_hwmod_common_data.h"
22 22
23static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
24 {
25 .pa_start = OMAP2_UART1_BASE,
26 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
27 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
28 },
29 { }
30};
31
32static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
33 {
34 .pa_start = OMAP2_UART2_BASE,
35 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
36 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
37 },
38 { }
39};
40
41static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
42 {
43 .pa_start = OMAP2_UART3_BASE,
44 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
45 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
46 },
47 { }
48};
49
50static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
51 {
52 .pa_start = 0x4802a000,
53 .pa_end = 0x4802a000 + SZ_1K - 1,
54 .flags = ADDR_TYPE_RT
55 },
56 { }
57};
58
59static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
60 {
61 .pa_start = 0x48078000,
62 .pa_end = 0x48078000 + SZ_1K - 1,
63 .flags = ADDR_TYPE_RT
64 },
65 { }
66};
67
68static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
69 {
70 .pa_start = 0x4807a000,
71 .pa_end = 0x4807a000 + SZ_1K - 1,
72 .flags = ADDR_TYPE_RT
73 },
74 { }
75};
76
77static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
78 {
79 .pa_start = 0x4807c000,
80 .pa_end = 0x4807c000 + SZ_1K - 1,
81 .flags = ADDR_TYPE_RT
82 },
83 { }
84};
85
86static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
87 {
88 .pa_start = 0x4807e000,
89 .pa_end = 0x4807e000 + SZ_1K - 1,
90 .flags = ADDR_TYPE_RT
91 },
92 { }
93};
94
95static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
96 {
97 .pa_start = 0x48080000,
98 .pa_end = 0x48080000 + SZ_1K - 1,
99 .flags = ADDR_TYPE_RT
100 },
101 { }
102};
103
104static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
105 {
106 .pa_start = 0x48082000,
107 .pa_end = 0x48082000 + SZ_1K - 1,
108 .flags = ADDR_TYPE_RT
109 },
110 { }
111};
112
113static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
114 {
115 .pa_start = 0x48084000,
116 .pa_end = 0x48084000 + SZ_1K - 1,
117 .flags = ADDR_TYPE_RT
118 },
119 { }
120};
121
122struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
123 {
124 .name = "mpu",
125 .pa_start = 0x48076000,
126 .pa_end = 0x480760ff,
127 .flags = ADDR_TYPE_RT
128 },
129 { }
130};
131
132static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
133 {
134 .pa_start = 0x480a0000,
135 .pa_end = 0x480a004f,
136 .flags = ADDR_TYPE_RT
137 },
138 { }
139};
140
141static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
142 {
143 .pa_start = 0x480a4000,
144 .pa_end = 0x480a4000 + 0x64 - 1,
145 .flags = ADDR_TYPE_RT
146 },
147 { }
148};
149
150static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
151 {
152 .pa_start = 0x480a6000,
153 .pa_end = 0x480a6000 + 0x50 - 1,
154 .flags = ADDR_TYPE_RT
155 },
156 { }
157};
158
159/* 23/*
160 * Common interconnect data 24 * Common interconnect data
161 */ 25 */
@@ -182,7 +46,7 @@ struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
182 .omap2 = { 46 .omap2 = {
183 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, 47 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
184 .flags = OMAP_FIREWALL_L3, 48 .flags = OMAP_FIREWALL_L3,
185 } 49 },
186 }, 50 },
187 .user = OCP_USER_MPU | OCP_USER_SDMA, 51 .user = OCP_USER_MPU | OCP_USER_SDMA,
188}; 52};
@@ -199,7 +63,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
199 .master = &omap2xxx_l4_core_hwmod, 63 .master = &omap2xxx_l4_core_hwmod,
200 .slave = &omap2xxx_uart1_hwmod, 64 .slave = &omap2xxx_uart1_hwmod,
201 .clk = "uart1_ick", 65 .clk = "uart1_ick",
202 .addr = omap2xxx_uart1_addr_space,
203 .user = OCP_USER_MPU | OCP_USER_SDMA, 66 .user = OCP_USER_MPU | OCP_USER_SDMA,
204}; 67};
205 68
@@ -208,7 +71,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
208 .master = &omap2xxx_l4_core_hwmod, 71 .master = &omap2xxx_l4_core_hwmod,
209 .slave = &omap2xxx_uart2_hwmod, 72 .slave = &omap2xxx_uart2_hwmod,
210 .clk = "uart2_ick", 73 .clk = "uart2_ick",
211 .addr = omap2xxx_uart2_addr_space,
212 .user = OCP_USER_MPU | OCP_USER_SDMA, 74 .user = OCP_USER_MPU | OCP_USER_SDMA,
213}; 75};
214 76
@@ -217,7 +79,6 @@ struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
217 .master = &omap2xxx_l4_core_hwmod, 79 .master = &omap2xxx_l4_core_hwmod,
218 .slave = &omap2xxx_uart3_hwmod, 80 .slave = &omap2xxx_uart3_hwmod,
219 .clk = "uart3_ick", 81 .clk = "uart3_ick",
220 .addr = omap2xxx_uart3_addr_space,
221 .user = OCP_USER_MPU | OCP_USER_SDMA, 82 .user = OCP_USER_MPU | OCP_USER_SDMA,
222}; 83};
223 84
@@ -226,7 +87,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
226 .master = &omap2xxx_l4_core_hwmod, 87 .master = &omap2xxx_l4_core_hwmod,
227 .slave = &omap2xxx_mcspi1_hwmod, 88 .slave = &omap2xxx_mcspi1_hwmod,
228 .clk = "mcspi1_ick", 89 .clk = "mcspi1_ick",
229 .addr = omap2_mcspi1_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA, 90 .user = OCP_USER_MPU | OCP_USER_SDMA,
231}; 91};
232 92
@@ -235,7 +95,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
235 .master = &omap2xxx_l4_core_hwmod, 95 .master = &omap2xxx_l4_core_hwmod,
236 .slave = &omap2xxx_mcspi2_hwmod, 96 .slave = &omap2xxx_mcspi2_hwmod,
237 .clk = "mcspi2_ick", 97 .clk = "mcspi2_ick",
238 .addr = omap2_mcspi2_addr_space,
239 .user = OCP_USER_MPU | OCP_USER_SDMA, 98 .user = OCP_USER_MPU | OCP_USER_SDMA,
240}; 99};
241 100
@@ -244,7 +103,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
244 .master = &omap2xxx_l4_core_hwmod, 103 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2xxx_timer2_hwmod, 104 .slave = &omap2xxx_timer2_hwmod,
246 .clk = "gpt2_ick", 105 .clk = "gpt2_ick",
247 .addr = omap2xxx_timer2_addrs,
248 .user = OCP_USER_MPU | OCP_USER_SDMA, 106 .user = OCP_USER_MPU | OCP_USER_SDMA,
249}; 107};
250 108
@@ -253,7 +111,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
253 .master = &omap2xxx_l4_core_hwmod, 111 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2xxx_timer3_hwmod, 112 .slave = &omap2xxx_timer3_hwmod,
255 .clk = "gpt3_ick", 113 .clk = "gpt3_ick",
256 .addr = omap2xxx_timer3_addrs,
257 .user = OCP_USER_MPU | OCP_USER_SDMA, 114 .user = OCP_USER_MPU | OCP_USER_SDMA,
258}; 115};
259 116
@@ -262,7 +119,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
262 .master = &omap2xxx_l4_core_hwmod, 119 .master = &omap2xxx_l4_core_hwmod,
263 .slave = &omap2xxx_timer4_hwmod, 120 .slave = &omap2xxx_timer4_hwmod,
264 .clk = "gpt4_ick", 121 .clk = "gpt4_ick",
265 .addr = omap2xxx_timer4_addrs,
266 .user = OCP_USER_MPU | OCP_USER_SDMA, 122 .user = OCP_USER_MPU | OCP_USER_SDMA,
267}; 123};
268 124
@@ -271,7 +127,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
271 .master = &omap2xxx_l4_core_hwmod, 127 .master = &omap2xxx_l4_core_hwmod,
272 .slave = &omap2xxx_timer5_hwmod, 128 .slave = &omap2xxx_timer5_hwmod,
273 .clk = "gpt5_ick", 129 .clk = "gpt5_ick",
274 .addr = omap2xxx_timer5_addrs,
275 .user = OCP_USER_MPU | OCP_USER_SDMA, 130 .user = OCP_USER_MPU | OCP_USER_SDMA,
276}; 131};
277 132
@@ -280,7 +135,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
280 .master = &omap2xxx_l4_core_hwmod, 135 .master = &omap2xxx_l4_core_hwmod,
281 .slave = &omap2xxx_timer6_hwmod, 136 .slave = &omap2xxx_timer6_hwmod,
282 .clk = "gpt6_ick", 137 .clk = "gpt6_ick",
283 .addr = omap2xxx_timer6_addrs,
284 .user = OCP_USER_MPU | OCP_USER_SDMA, 138 .user = OCP_USER_MPU | OCP_USER_SDMA,
285}; 139};
286 140
@@ -289,7 +143,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
289 .master = &omap2xxx_l4_core_hwmod, 143 .master = &omap2xxx_l4_core_hwmod,
290 .slave = &omap2xxx_timer7_hwmod, 144 .slave = &omap2xxx_timer7_hwmod,
291 .clk = "gpt7_ick", 145 .clk = "gpt7_ick",
292 .addr = omap2xxx_timer7_addrs,
293 .user = OCP_USER_MPU | OCP_USER_SDMA, 146 .user = OCP_USER_MPU | OCP_USER_SDMA,
294}; 147};
295 148
@@ -298,7 +151,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
298 .master = &omap2xxx_l4_core_hwmod, 151 .master = &omap2xxx_l4_core_hwmod,
299 .slave = &omap2xxx_timer8_hwmod, 152 .slave = &omap2xxx_timer8_hwmod,
300 .clk = "gpt8_ick", 153 .clk = "gpt8_ick",
301 .addr = omap2xxx_timer8_addrs,
302 .user = OCP_USER_MPU | OCP_USER_SDMA, 154 .user = OCP_USER_MPU | OCP_USER_SDMA,
303}; 155};
304 156
@@ -307,7 +159,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
307 .master = &omap2xxx_l4_core_hwmod, 159 .master = &omap2xxx_l4_core_hwmod,
308 .slave = &omap2xxx_timer9_hwmod, 160 .slave = &omap2xxx_timer9_hwmod,
309 .clk = "gpt9_ick", 161 .clk = "gpt9_ick",
310 .addr = omap2xxx_timer9_addrs,
311 .user = OCP_USER_MPU | OCP_USER_SDMA, 162 .user = OCP_USER_MPU | OCP_USER_SDMA,
312}; 163};
313 164
@@ -316,7 +167,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
316 .master = &omap2xxx_l4_core_hwmod, 167 .master = &omap2xxx_l4_core_hwmod,
317 .slave = &omap2xxx_timer10_hwmod, 168 .slave = &omap2xxx_timer10_hwmod,
318 .clk = "gpt10_ick", 169 .clk = "gpt10_ick",
319 .addr = omap2_timer10_addrs,
320 .user = OCP_USER_MPU | OCP_USER_SDMA, 170 .user = OCP_USER_MPU | OCP_USER_SDMA,
321}; 171};
322 172
@@ -325,7 +175,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
325 .master = &omap2xxx_l4_core_hwmod, 175 .master = &omap2xxx_l4_core_hwmod,
326 .slave = &omap2xxx_timer11_hwmod, 176 .slave = &omap2xxx_timer11_hwmod,
327 .clk = "gpt11_ick", 177 .clk = "gpt11_ick",
328 .addr = omap2_timer11_addrs,
329 .user = OCP_USER_MPU | OCP_USER_SDMA, 178 .user = OCP_USER_MPU | OCP_USER_SDMA,
330}; 179};
331 180
@@ -334,7 +183,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
334 .master = &omap2xxx_l4_core_hwmod, 183 .master = &omap2xxx_l4_core_hwmod,
335 .slave = &omap2xxx_timer12_hwmod, 184 .slave = &omap2xxx_timer12_hwmod,
336 .clk = "gpt12_ick", 185 .clk = "gpt12_ick",
337 .addr = omap2xxx_timer12_addrs,
338 .user = OCP_USER_MPU | OCP_USER_SDMA, 186 .user = OCP_USER_MPU | OCP_USER_SDMA,
339}; 187};
340 188
@@ -348,7 +196,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
348 .omap2 = { 196 .omap2 = {
349 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 197 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
350 .flags = OMAP_FIREWALL_L4, 198 .flags = OMAP_FIREWALL_L4,
351 } 199 },
352 }, 200 },
353 .user = OCP_USER_MPU | OCP_USER_SDMA, 201 .user = OCP_USER_MPU | OCP_USER_SDMA,
354}; 202};
@@ -363,7 +211,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
363 .omap2 = { 211 .omap2 = {
364 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 212 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
365 .flags = OMAP_FIREWALL_L4, 213 .flags = OMAP_FIREWALL_L4,
366 } 214 },
367 }, 215 },
368 .user = OCP_USER_MPU | OCP_USER_SDMA, 216 .user = OCP_USER_MPU | OCP_USER_SDMA,
369}; 217};
@@ -378,7 +226,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
378 .omap2 = { 226 .omap2 = {
379 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 227 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
380 .flags = OMAP_FIREWALL_L4, 228 .flags = OMAP_FIREWALL_L4,
381 } 229 },
382 }, 230 },
383 .user = OCP_USER_MPU | OCP_USER_SDMA, 231 .user = OCP_USER_MPU | OCP_USER_SDMA,
384}; 232};
@@ -393,7 +241,7 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
393 .omap2 = { 241 .omap2 = {
394 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 242 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
395 .flags = OMAP_FIREWALL_L4, 243 .flags = OMAP_FIREWALL_L4,
396 } 244 },
397 }, 245 },
398 .flags = OCPIF_SWSUP_IDLE, 246 .flags = OCPIF_SWSUP_IDLE,
399 .user = OCP_USER_MPU | OCP_USER_SDMA, 247 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -404,7 +252,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
404 .master = &omap2xxx_l4_core_hwmod, 252 .master = &omap2xxx_l4_core_hwmod,
405 .slave = &omap2xxx_rng_hwmod, 253 .slave = &omap2xxx_rng_hwmod,
406 .clk = "rng_ick", 254 .clk = "rng_ick",
407 .addr = omap2_rng_addr_space,
408 .user = OCP_USER_MPU | OCP_USER_SDMA, 255 .user = OCP_USER_MPU | OCP_USER_SDMA,
409}; 256};
410 257
@@ -413,7 +260,6 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
413 .master = &omap2xxx_l4_core_hwmod, 260 .master = &omap2xxx_l4_core_hwmod,
414 .slave = &omap2xxx_sham_hwmod, 261 .slave = &omap2xxx_sham_hwmod,
415 .clk = "sha_ick", 262 .clk = "sha_ick",
416 .addr = omap2xxx_sham_addrs,
417 .user = OCP_USER_MPU | OCP_USER_SDMA, 263 .user = OCP_USER_MPU | OCP_USER_SDMA,
418}; 264};
419 265
@@ -422,6 +268,5 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
422 .master = &omap2xxx_l4_core_hwmod, 268 .master = &omap2xxx_l4_core_hwmod,
423 .slave = &omap2xxx_aes_hwmod, 269 .slave = &omap2xxx_aes_hwmod,
424 .clk = "aes_ick", 270 .clk = "aes_ick",
425 .addr = omap2xxx_aes_addrs,
426 .user = OCP_USER_MPU | OCP_USER_SDMA, 271 .user = OCP_USER_MPU | OCP_USER_SDMA,
427}; 272};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index d23c77fadb31..8821b9d6bae4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -20,14 +20,9 @@
20#include "prm-regbits-24xx.h" 20#include "prm-regbits-24xx.h"
21#include "wd_timer.h" 21#include "wd_timer.h"
22 22
23struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
24 { .irq = 48 + OMAP_INTC_START, },
25 { .irq = -1 },
26};
27
28struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { 23struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
29 { .name = "dispc", .dma_req = 5 }, 24 { .name = "dispc", .dma_req = 5 },
30 { .dma_req = -1 } 25 { .dma_req = -1, },
31}; 26};
32 27
33/* 28/*
@@ -219,14 +214,8 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
219}; 214};
220 215
221/* MPU */ 216/* MPU */
222static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
223 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
224 { .irq = -1 }
225};
226
227struct omap_hwmod omap2xxx_mpu_hwmod = { 217struct omap_hwmod omap2xxx_mpu_hwmod = {
228 .name = "mpu", 218 .name = "mpu",
229 .mpu_irqs = omap2xxx_mpu_irqs,
230 .class = &mpu_hwmod_class, 219 .class = &mpu_hwmod_class,
231 .main_clk = "mpu_ck", 220 .main_clk = "mpu_ck",
232}; 221};
@@ -256,7 +245,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
256 245
257struct omap_hwmod omap2xxx_timer1_hwmod = { 246struct omap_hwmod omap2xxx_timer1_hwmod = {
258 .name = "timer1", 247 .name = "timer1",
259 .mpu_irqs = omap2_timer1_mpu_irqs,
260 .main_clk = "gpt1_fck", 248 .main_clk = "gpt1_fck",
261 .prcm = { 249 .prcm = {
262 .omap2 = { 250 .omap2 = {
@@ -276,7 +264,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
276 264
277struct omap_hwmod omap2xxx_timer2_hwmod = { 265struct omap_hwmod omap2xxx_timer2_hwmod = {
278 .name = "timer2", 266 .name = "timer2",
279 .mpu_irqs = omap2_timer2_mpu_irqs,
280 .main_clk = "gpt2_fck", 267 .main_clk = "gpt2_fck",
281 .prcm = { 268 .prcm = {
282 .omap2 = { 269 .omap2 = {
@@ -295,7 +282,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
295 282
296struct omap_hwmod omap2xxx_timer3_hwmod = { 283struct omap_hwmod omap2xxx_timer3_hwmod = {
297 .name = "timer3", 284 .name = "timer3",
298 .mpu_irqs = omap2_timer3_mpu_irqs,
299 .main_clk = "gpt3_fck", 285 .main_clk = "gpt3_fck",
300 .prcm = { 286 .prcm = {
301 .omap2 = { 287 .omap2 = {
@@ -314,7 +300,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
314 300
315struct omap_hwmod omap2xxx_timer4_hwmod = { 301struct omap_hwmod omap2xxx_timer4_hwmod = {
316 .name = "timer4", 302 .name = "timer4",
317 .mpu_irqs = omap2_timer4_mpu_irqs,
318 .main_clk = "gpt4_fck", 303 .main_clk = "gpt4_fck",
319 .prcm = { 304 .prcm = {
320 .omap2 = { 305 .omap2 = {
@@ -333,7 +318,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
333 318
334struct omap_hwmod omap2xxx_timer5_hwmod = { 319struct omap_hwmod omap2xxx_timer5_hwmod = {
335 .name = "timer5", 320 .name = "timer5",
336 .mpu_irqs = omap2_timer5_mpu_irqs,
337 .main_clk = "gpt5_fck", 321 .main_clk = "gpt5_fck",
338 .prcm = { 322 .prcm = {
339 .omap2 = { 323 .omap2 = {
@@ -353,7 +337,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
353 337
354struct omap_hwmod omap2xxx_timer6_hwmod = { 338struct omap_hwmod omap2xxx_timer6_hwmod = {
355 .name = "timer6", 339 .name = "timer6",
356 .mpu_irqs = omap2_timer6_mpu_irqs,
357 .main_clk = "gpt6_fck", 340 .main_clk = "gpt6_fck",
358 .prcm = { 341 .prcm = {
359 .omap2 = { 342 .omap2 = {
@@ -373,7 +356,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
373 356
374struct omap_hwmod omap2xxx_timer7_hwmod = { 357struct omap_hwmod omap2xxx_timer7_hwmod = {
375 .name = "timer7", 358 .name = "timer7",
376 .mpu_irqs = omap2_timer7_mpu_irqs,
377 .main_clk = "gpt7_fck", 359 .main_clk = "gpt7_fck",
378 .prcm = { 360 .prcm = {
379 .omap2 = { 361 .omap2 = {
@@ -393,7 +375,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
393 375
394struct omap_hwmod omap2xxx_timer8_hwmod = { 376struct omap_hwmod omap2xxx_timer8_hwmod = {
395 .name = "timer8", 377 .name = "timer8",
396 .mpu_irqs = omap2_timer8_mpu_irqs,
397 .main_clk = "gpt8_fck", 378 .main_clk = "gpt8_fck",
398 .prcm = { 379 .prcm = {
399 .omap2 = { 380 .omap2 = {
@@ -413,7 +394,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
413 394
414struct omap_hwmod omap2xxx_timer9_hwmod = { 395struct omap_hwmod omap2xxx_timer9_hwmod = {
415 .name = "timer9", 396 .name = "timer9",
416 .mpu_irqs = omap2_timer9_mpu_irqs,
417 .main_clk = "gpt9_fck", 397 .main_clk = "gpt9_fck",
418 .prcm = { 398 .prcm = {
419 .omap2 = { 399 .omap2 = {
@@ -433,7 +413,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
433 413
434struct omap_hwmod omap2xxx_timer10_hwmod = { 414struct omap_hwmod omap2xxx_timer10_hwmod = {
435 .name = "timer10", 415 .name = "timer10",
436 .mpu_irqs = omap2_timer10_mpu_irqs,
437 .main_clk = "gpt10_fck", 416 .main_clk = "gpt10_fck",
438 .prcm = { 417 .prcm = {
439 .omap2 = { 418 .omap2 = {
@@ -453,7 +432,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
453 432
454struct omap_hwmod omap2xxx_timer11_hwmod = { 433struct omap_hwmod omap2xxx_timer11_hwmod = {
455 .name = "timer11", 434 .name = "timer11",
456 .mpu_irqs = omap2_timer11_mpu_irqs,
457 .main_clk = "gpt11_fck", 435 .main_clk = "gpt11_fck",
458 .prcm = { 436 .prcm = {
459 .omap2 = { 437 .omap2 = {
@@ -473,7 +451,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
473 451
474struct omap_hwmod omap2xxx_timer12_hwmod = { 452struct omap_hwmod omap2xxx_timer12_hwmod = {
475 .name = "timer12", 453 .name = "timer12",
476 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
477 .main_clk = "gpt12_fck", 454 .main_clk = "gpt12_fck",
478 .prcm = { 455 .prcm = {
479 .omap2 = { 456 .omap2 = {
@@ -509,8 +486,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
509 486
510struct omap_hwmod omap2xxx_uart1_hwmod = { 487struct omap_hwmod omap2xxx_uart1_hwmod = {
511 .name = "uart1", 488 .name = "uart1",
512 .mpu_irqs = omap2_uart1_mpu_irqs,
513 .sdma_reqs = omap2_uart1_sdma_reqs,
514 .main_clk = "uart1_fck", 489 .main_clk = "uart1_fck",
515 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 490 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
516 .prcm = { 491 .prcm = {
@@ -529,8 +504,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
529 504
530struct omap_hwmod omap2xxx_uart2_hwmod = { 505struct omap_hwmod omap2xxx_uart2_hwmod = {
531 .name = "uart2", 506 .name = "uart2",
532 .mpu_irqs = omap2_uart2_mpu_irqs,
533 .sdma_reqs = omap2_uart2_sdma_reqs,
534 .main_clk = "uart2_fck", 507 .main_clk = "uart2_fck",
535 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 508 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
536 .prcm = { 509 .prcm = {
@@ -549,8 +522,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
549 522
550struct omap_hwmod omap2xxx_uart3_hwmod = { 523struct omap_hwmod omap2xxx_uart3_hwmod = {
551 .name = "uart3", 524 .name = "uart3",
552 .mpu_irqs = omap2_uart3_mpu_irqs,
553 .sdma_reqs = omap2_uart3_sdma_reqs,
554 .main_clk = "uart3_fck", 525 .main_clk = "uart3_fck",
555 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 526 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
556 .prcm = { 527 .prcm = {
@@ -610,7 +581,7 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
610 }, 581 },
611 }, 582 },
612 .flags = HWMOD_NO_IDLEST, 583 .flags = HWMOD_NO_IDLEST,
613 .dev_attr = &omap2_3_dss_dispc_dev_attr 584 .dev_attr = &omap2_3_dss_dispc_dev_attr,
614}; 585};
615 586
616static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 587static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
@@ -657,7 +628,6 @@ struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
657struct omap_hwmod omap2xxx_gpio1_hwmod = { 628struct omap_hwmod omap2xxx_gpio1_hwmod = {
658 .name = "gpio1", 629 .name = "gpio1",
659 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 630 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
660 .mpu_irqs = omap2_gpio1_irqs,
661 .main_clk = "gpios_fck", 631 .main_clk = "gpios_fck",
662 .prcm = { 632 .prcm = {
663 .omap2 = { 633 .omap2 = {
@@ -676,7 +646,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = {
676struct omap_hwmod omap2xxx_gpio2_hwmod = { 646struct omap_hwmod omap2xxx_gpio2_hwmod = {
677 .name = "gpio2", 647 .name = "gpio2",
678 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
679 .mpu_irqs = omap2_gpio2_irqs,
680 .main_clk = "gpios_fck", 649 .main_clk = "gpios_fck",
681 .prcm = { 650 .prcm = {
682 .omap2 = { 651 .omap2 = {
@@ -695,7 +664,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = {
695struct omap_hwmod omap2xxx_gpio3_hwmod = { 664struct omap_hwmod omap2xxx_gpio3_hwmod = {
696 .name = "gpio3", 665 .name = "gpio3",
697 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
698 .mpu_irqs = omap2_gpio3_irqs,
699 .main_clk = "gpios_fck", 667 .main_clk = "gpios_fck",
700 .prcm = { 668 .prcm = {
701 .omap2 = { 669 .omap2 = {
@@ -714,7 +682,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = {
714struct omap_hwmod omap2xxx_gpio4_hwmod = { 682struct omap_hwmod omap2xxx_gpio4_hwmod = {
715 .name = "gpio4", 683 .name = "gpio4",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 684 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .mpu_irqs = omap2_gpio4_irqs,
718 .main_clk = "gpios_fck", 685 .main_clk = "gpios_fck",
719 .prcm = { 686 .prcm = {
720 .omap2 = { 687 .omap2 = {
@@ -736,8 +703,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
736 703
737struct omap_hwmod omap2xxx_mcspi1_hwmod = { 704struct omap_hwmod omap2xxx_mcspi1_hwmod = {
738 .name = "mcspi1", 705 .name = "mcspi1",
739 .mpu_irqs = omap2_mcspi1_mpu_irqs,
740 .sdma_reqs = omap2_mcspi1_sdma_reqs,
741 .main_clk = "mcspi1_fck", 706 .main_clk = "mcspi1_fck",
742 .prcm = { 707 .prcm = {
743 .omap2 = { 708 .omap2 = {
@@ -759,8 +724,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
759 724
760struct omap_hwmod omap2xxx_mcspi2_hwmod = { 725struct omap_hwmod omap2xxx_mcspi2_hwmod = {
761 .name = "mcspi2", 726 .name = "mcspi2",
762 .mpu_irqs = omap2_mcspi2_mpu_irqs,
763 .sdma_reqs = omap2_mcspi2_sdma_reqs,
764 .main_clk = "mcspi2_fck", 727 .main_clk = "mcspi2_fck",
765 .prcm = { 728 .prcm = {
766 .omap2 = { 729 .omap2 = {
@@ -795,15 +758,9 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
795}; 758};
796 759
797/* gpmc */ 760/* gpmc */
798static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
799 { .irq = 20 + OMAP_INTC_START, },
800 { .irq = -1 }
801};
802
803struct omap_hwmod omap2xxx_gpmc_hwmod = { 761struct omap_hwmod omap2xxx_gpmc_hwmod = {
804 .name = "gpmc", 762 .name = "gpmc",
805 .class = &omap2xxx_gpmc_hwmod_class, 763 .class = &omap2xxx_gpmc_hwmod_class,
806 .mpu_irqs = omap2xxx_gpmc_irqs,
807 .main_clk = "gpmc_fck", 764 .main_clk = "gpmc_fck",
808 /* 765 /*
809 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP 766 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
@@ -840,14 +797,8 @@ static struct omap_hwmod_class omap2_rng_hwmod_class = {
840 .sysc = &omap2_rng_sysc, 797 .sysc = &omap2_rng_sysc,
841}; 798};
842 799
843static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
844 { .irq = 52 + OMAP_INTC_START, },
845 { .irq = -1 }
846};
847
848struct omap_hwmod omap2xxx_rng_hwmod = { 800struct omap_hwmod omap2xxx_rng_hwmod = {
849 .name = "rng", 801 .name = "rng",
850 .mpu_irqs = omap2_rng_mpu_irqs,
851 .main_clk = "l4_ck", 802 .main_clk = "l4_ck",
852 .prcm = { 803 .prcm = {
853 .omap2 = { 804 .omap2 = {
@@ -884,20 +835,8 @@ static struct omap_hwmod_class omap2xxx_sham_class = {
884 .sysc = &omap2_sham_sysc, 835 .sysc = &omap2_sham_sysc,
885}; 836};
886 837
887static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
888 { .irq = 51 + OMAP_INTC_START, },
889 { .irq = -1 }
890};
891
892static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
893 { .name = "rx", .dma_req = 13 },
894 { .dma_req = -1 }
895};
896
897struct omap_hwmod omap2xxx_sham_hwmod = { 838struct omap_hwmod omap2xxx_sham_hwmod = {
898 .name = "sham", 839 .name = "sham",
899 .mpu_irqs = omap2_sham_mpu_irqs,
900 .sdma_reqs = omap2_sham_sdma_chs,
901 .main_clk = "l4_ck", 840 .main_clk = "l4_ck",
902 .prcm = { 841 .prcm = {
903 .omap2 = { 842 .omap2 = {
@@ -927,15 +866,8 @@ static struct omap_hwmod_class omap2xxx_aes_class = {
927 .sysc = &omap2_aes_sysc, 866 .sysc = &omap2_aes_sysc,
928}; 867};
929 868
930static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
931 { .name = "tx", .dma_req = 9 },
932 { .name = "rx", .dma_req = 10 },
933 { .dma_req = -1 }
934};
935
936struct omap_hwmod omap2xxx_aes_hwmod = { 869struct omap_hwmod omap2xxx_aes_hwmod = {
937 .name = "aes", 870 .name = "aes",
938 .sdma_reqs = omap2_aes_sdma_chs,
939 .main_clk = "l4_ck", 871 .main_clk = "l4_ck",
940 .prcm = { 872 .prcm = {
941 .omap2 = { 873 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 18f333c440db..810c205d668b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1365,11 +1365,10 @@ static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1365 .rev_offs = 0x0000, 1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010, 1366 .sysc_offs = 0x0010,
1367 .syss_offs = 0x0014, 1367 .syss_offs = 0x0014,
1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1369 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 1369 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1370 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1370 SYSS_HAS_RESET_STATUS),
1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1372 SIDLE_SMART_WKUP),
1373 .sysc_fields = &omap_hwmod_sysc_type1, 1372 .sysc_fields = &omap_hwmod_sysc_type1,
1374}; 1373};
1375 1374
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 6e04ff7065e1..2c38c6b0ee03 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -18,9 +18,6 @@
18#include "common.h" 18#include "common.h"
19#include "display.h" 19#include "display.h"
20 20
21/* Common address space across OMAP2xxx */
22extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
23
24/* Common address space across OMAP2xxx/3xxx */ 21/* Common address space across OMAP2xxx/3xxx */
25extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[]; 22extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
26extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[]; 23extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
@@ -41,8 +38,6 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
41extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[]; 38extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
42 39
43/* Common IP block data across OMAP2xxx */ 40/* Common IP block data across OMAP2xxx */
44extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
45extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
46extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr; 41extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
47extern struct omap_hwmod omap2xxx_l3_main_hwmod; 42extern struct omap_hwmod omap2xxx_l3_main_hwmod;
48extern struct omap_hwmod omap2xxx_l4_core_hwmod; 43extern struct omap_hwmod omap2xxx_l4_core_hwmod;
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 39f020c982e8..c33e07e2f0d4 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -8,6 +8,7 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/davinci_emac.h>
11#include <linux/gpio.h> 12#include <linux/gpio.h>
12#include <linux/init.h> 13#include <linux/init.h>
13#include <linux/kernel.h> 14#include <linux/kernel.h>
@@ -16,16 +17,22 @@
16 17
17#include <linux/platform_data/pinctrl-single.h> 18#include <linux/platform_data/pinctrl-single.h>
18 19
20#include "am35xx.h"
19#include "common.h" 21#include "common.h"
20#include "common-board-devices.h" 22#include "common-board-devices.h"
21#include "dss-common.h" 23#include "dss-common.h"
22#include "control.h" 24#include "control.h"
25#include "omap-secure.h"
26#include "soc.h"
23 27
24struct pdata_init { 28struct pdata_init {
25 const char *compatible; 29 const char *compatible;
26 void (*fn)(void); 30 void (*fn)(void);
27}; 31};
28 32
33struct of_dev_auxdata omap_auxdata_lookup[];
34static struct twl4030_gpio_platform_data twl_gpio_auxdata;
35
29/* 36/*
30 * Create alias for USB host PHY clock. 37 * Create alias for USB host PHY clock.
31 * Remove this when clock phandle can be provided via DT 38 * Remove this when clock phandle can be provided via DT
@@ -68,6 +75,15 @@ static inline void legacy_init_wl12xx(unsigned ref_clock,
68} 75}
69#endif 76#endif
70 77
78#ifdef CONFIG_MACH_NOKIA_N8X0
79static void __init omap2420_n8x0_legacy_init(void)
80{
81 omap_auxdata_lookup[0].platform_data = n8x0_legacy_init();
82}
83#else
84#define omap2420_n8x0_legacy_init NULL
85#endif
86
71#ifdef CONFIG_ARCH_OMAP3 87#ifdef CONFIG_ARCH_OMAP3
72static void __init hsmmc2_internal_input_clk(void) 88static void __init hsmmc2_internal_input_clk(void)
73{ 89{
@@ -78,6 +94,33 @@ static void __init hsmmc2_internal_input_clk(void)
78 omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1); 94 omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
79} 95}
80 96
97static int omap3_sbc_t3730_twl_callback(struct device *dev,
98 unsigned gpio,
99 unsigned ngpio)
100{
101 int res;
102
103 res = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH,
104 "wlan rst");
105 if (res)
106 return res;
107
108 gpio_export(gpio, 0);
109
110 return 0;
111}
112
113static void __init omap3_sbc_t3730_twl_init(void)
114{
115 twl_gpio_auxdata.setup = omap3_sbc_t3730_twl_callback;
116}
117
118static void __init omap3_sbc_t3730_legacy_init(void)
119{
120 legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 136);
121 omap_ads7846_init(1, 57, 0, NULL);
122}
123
81static void __init omap3_igep0020_legacy_init(void) 124static void __init omap3_igep0020_legacy_init(void)
82{ 125{
83 omap3_igep2_display_init_of(); 126 omap3_igep2_display_init_of();
@@ -92,6 +135,58 @@ static void __init omap3_zoom_legacy_init(void)
92{ 135{
93 legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162); 136 legacy_init_wl12xx(WL12XX_REFCLOCK_26, 0, 162);
94} 137}
138
139static void am35xx_enable_emac_int(void)
140{
141 u32 v;
142
143 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
144 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
145 AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
146 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
147 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
148}
149
150static void am35xx_disable_emac_int(void)
151{
152 u32 v;
153
154 v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
155 v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
156 omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
157 omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
158}
159
160static struct emac_platform_data am35xx_emac_pdata = {
161 .interrupt_enable = am35xx_enable_emac_int,
162 .interrupt_disable = am35xx_disable_emac_int,
163};
164
165static void __init am3517_evm_legacy_init(void)
166{
167 u32 v;
168
169 v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
170 v &= ~AM35XX_CPGMACSS_SW_RST;
171 omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
172 omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
173}
174
175static void __init nokia_n900_legacy_init(void)
176{
177 hsmmc2_internal_input_clk();
178
179 if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
180 if (IS_ENABLED(CONFIG_ARM_ERRATA_430973)) {
181 pr_info("RX-51: Enabling ARM errata 430973 workaround\n");
182 /* set IBE to 1 */
183 rx51_secure_update_aux_cr(BIT(6), 0);
184 } else {
185 pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n");
186 pr_warning("Thumb binaries may crash randomly without this workaround\n");
187 }
188 }
189}
95#endif /* CONFIG_ARCH_OMAP3 */ 190#endif /* CONFIG_ARCH_OMAP3 */
96 191
97#ifdef CONFIG_ARCH_OMAP4 192#ifdef CONFIG_ARCH_OMAP4
@@ -125,10 +220,49 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void))
125 pcs_pdata.rearm = rearm; 220 pcs_pdata.rearm = rearm;
126} 221}
127 222
223/*
224 * GPIOs for TWL are initialized by the I2C bus and need custom
225 * handing until DSS has device tree bindings.
226 */
227void omap_auxdata_legacy_init(struct device *dev)
228{
229 if (dev->platform_data)
230 return;
231
232 if (strcmp("twl4030-gpio", dev_name(dev)))
233 return;
234
235 dev->platform_data = &twl_gpio_auxdata;
236}
237
238/*
239 * Few boards still need auxdata populated before we populate
240 * the dev entries in of_platform_populate().
241 */
242static struct pdata_init auxdata_quirks[] __initdata = {
243#ifdef CONFIG_SOC_OMAP2420
244 { "nokia,n800", omap2420_n8x0_legacy_init, },
245 { "nokia,n810", omap2420_n8x0_legacy_init, },
246 { "nokia,n810-wimax", omap2420_n8x0_legacy_init, },
247#endif
248#ifdef CONFIG_ARCH_OMAP3
249 { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_twl_init, },
250#endif
251 { /* sentinel */ },
252};
253
128struct of_dev_auxdata omap_auxdata_lookup[] __initdata = { 254struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
255#ifdef CONFIG_MACH_NOKIA_N8X0
256 OF_DEV_AUXDATA("ti,omap2420-mmc", 0x4809c000, "mmci-omap.0", NULL),
257#endif
129#ifdef CONFIG_ARCH_OMAP3 258#ifdef CONFIG_ARCH_OMAP3
130 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata), 259 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002030, "48002030.pinmux", &pcs_pdata),
260 OF_DEV_AUXDATA("ti,omap3-padconf", 0x480025a0, "480025a0.pinmux", &pcs_pdata),
131 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), 261 OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata),
262 /* Only on am3517 */
263 OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
264 OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
265 &am35xx_emac_pdata),
132#endif 266#endif
133#ifdef CONFIG_ARCH_OMAP4 267#ifdef CONFIG_ARCH_OMAP4
134 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), 268 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata),
@@ -137,14 +271,20 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
137 { /* sentinel */ }, 271 { /* sentinel */ },
138}; 272};
139 273
274/*
275 * Few boards still need to initialize some legacy devices with
276 * platform data until the drivers support device tree.
277 */
140static struct pdata_init pdata_quirks[] __initdata = { 278static struct pdata_init pdata_quirks[] __initdata = {
141#ifdef CONFIG_ARCH_OMAP3 279#ifdef CONFIG_ARCH_OMAP3
142 { "nokia,omap3-n900", hsmmc2_internal_input_clk, }, 280 { "compulab,omap3-sbc-t3730", omap3_sbc_t3730_legacy_init, },
281 { "nokia,omap3-n900", nokia_n900_legacy_init, },
143 { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, 282 { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
144 { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, 283 { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
145 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, 284 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
146 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, 285 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
147 { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, 286 { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
287 { "ti,am3517-evm", am3517_evm_legacy_init, },
148#endif 288#endif
149#ifdef CONFIG_ARCH_OMAP4 289#ifdef CONFIG_ARCH_OMAP4
150 { "ti,omap4-sdp", omap4_sdp_legacy_init, }, 290 { "ti,omap4-sdp", omap4_sdp_legacy_init, },
@@ -156,14 +296,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
156 { /* sentinel */ }, 296 { /* sentinel */ },
157}; 297};
158 298
159void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table) 299static void pdata_quirks_check(struct pdata_init *quirks)
160{ 300{
161 struct pdata_init *quirks = pdata_quirks;
162
163 omap_sdrc_init(NULL, NULL);
164 of_platform_populate(NULL, omap_dt_match_table,
165 omap_auxdata_lookup, NULL);
166
167 while (quirks->compatible) { 301 while (quirks->compatible) {
168 if (of_machine_is_compatible(quirks->compatible)) { 302 if (of_machine_is_compatible(quirks->compatible)) {
169 if (quirks->fn) 303 if (quirks->fn)
@@ -173,3 +307,12 @@ void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
173 quirks++; 307 quirks++;
174 } 308 }
175} 309}
310
311void __init pdata_quirks_init(struct of_device_id *omap_dt_match_table)
312{
313 omap_sdrc_init(NULL, NULL);
314 pdata_quirks_check(auxdata_quirks);
315 of_platform_populate(NULL, omap_dt_match_table,
316 omap_auxdata_lookup, NULL);
317 pdata_quirks_check(pdata_quirks);
318}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 82f0698933d8..eefb30cfcabd 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -24,6 +24,8 @@
24#include "powerdomain.h" 24#include "powerdomain.h"
25#include "pm.h" 25#include "pm.h"
26 26
27u16 pm44xx_errata;
28
27struct power_state { 29struct power_state {
28 struct powerdomain *pwrdm; 30 struct powerdomain *pwrdm;
29 u32 next_state; 31 u32 next_state;
@@ -199,6 +201,19 @@ static inline int omap4_init_static_deps(void)
199} 201}
200 202
201/** 203/**
204 * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
205 *
206 * Initializes basic stuff for power management functionality.
207 */
208int __init omap4_pm_init_early(void)
209{
210 if (cpu_is_omap446x())
211 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
212
213 return 0;
214}
215
216/**
202 * omap4_pm_init - Init routine for OMAP4+ devices 217 * omap4_pm_init - Init routine for OMAP4+ devices
203 * 218 *
204 * Initializes all powerdomain and clockdomain target states 219 * Initializes all powerdomain and clockdomain target states
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6667cf..623db40fdbbd 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
18# ifndef __ASSEMBLER__ 18# ifndef __ASSEMBLER__
19extern void __iomem *prm_base; 19extern void __iomem *prm_base;
20extern void omap2_set_globals_prm(void __iomem *prm); 20extern void omap2_set_globals_prm(void __iomem *prm);
21int of_prcm_init(void);
21# endif 22# endif
22 23
23 24
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index a2e1174ad1b6..b4c4ab9c8044 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,6 +23,10 @@
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/clk-provider.h>
29#include <linux/clk/ti.h>
26 30
27#include "soc.h" 31#include "soc.h"
28#include "prm2xxx_3xxx.h" 32#include "prm2xxx_3xxx.h"
@@ -30,6 +34,7 @@
30#include "prm3xxx.h" 34#include "prm3xxx.h"
31#include "prm44xx.h" 35#include "prm44xx.h"
32#include "common.h" 36#include "common.h"
37#include "clock.h"
33 38
34/* 39/*
35 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs 40 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
464 469
465 return 0; 470 return 0;
466} 471}
472
473static struct of_device_id omap_prcm_dt_match_table[] = {
474 { .compatible = "ti,am3-prcm" },
475 { .compatible = "ti,am3-scrm" },
476 { .compatible = "ti,am4-prcm" },
477 { .compatible = "ti,am4-scrm" },
478 { .compatible = "ti,omap3-prm" },
479 { .compatible = "ti,omap3-cm" },
480 { .compatible = "ti,omap3-scrm" },
481 { .compatible = "ti,omap4-cm1" },
482 { .compatible = "ti,omap4-prm" },
483 { .compatible = "ti,omap4-cm2" },
484 { .compatible = "ti,omap4-scrm" },
485 { .compatible = "ti,omap5-prm" },
486 { .compatible = "ti,omap5-cm-core-aon" },
487 { .compatible = "ti,omap5-scrm" },
488 { .compatible = "ti,omap5-cm-core" },
489 { .compatible = "ti,dra7-prm" },
490 { .compatible = "ti,dra7-cm-core-aon" },
491 { .compatible = "ti,dra7-cm-core" },
492 { }
493};
494
495static struct clk_hw_omap memmap_dummy_ck = {
496 .flags = MEMMAP_ADDRESSING,
497};
498
499static u32 prm_clk_readl(void __iomem *reg)
500{
501 return omap2_clk_readl(&memmap_dummy_ck, reg);
502}
503
504static void prm_clk_writel(u32 val, void __iomem *reg)
505{
506 omap2_clk_writel(val, &memmap_dummy_ck, reg);
507}
508
509static struct ti_clk_ll_ops omap_clk_ll_ops = {
510 .clk_readl = prm_clk_readl,
511 .clk_writel = prm_clk_writel,
512};
513
514int __init of_prcm_init(void)
515{
516 struct device_node *np;
517 void __iomem *mem;
518 int memmap_index = 0;
519
520 ti_clk_ll_ops = &omap_clk_ll_ops;
521
522 for_each_matching_node(np, omap_prcm_dt_match_table) {
523 mem = of_iomap(np, 0);
524 clk_memmaps[memmap_index] = mem;
525 ti_dt_clk_init_provider(np, memmap_index);
526 memmap_index++;
527 }
528
529 ti_dt_clockdomains_setup();
530
531 return 0;
532}
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 6334b96b4097..280f3c58abe5 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -183,11 +183,11 @@ void omap4_prminst_global_warm_sw_reset(void)
183 OMAP4_PRM_RSTCTRL_OFFSET); 183 OMAP4_PRM_RSTCTRL_OFFSET);
184 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; 184 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
185 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, 185 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
186 OMAP4430_PRM_DEVICE_INST, 186 dev_inst,
187 OMAP4_PRM_RSTCTRL_OFFSET); 187 OMAP4_PRM_RSTCTRL_OFFSET);
188 188
189 /* OCP barrier */ 189 /* OCP barrier */
190 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 190 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
191 OMAP4430_PRM_DEVICE_INST, 191 dev_inst,
192 OMAP4_PRM_RSTCTRL_OFFSET); 192 OMAP4_PRM_RSTCTRL_OFFSET);
193} 193}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 3ca81e0ada5e..74044aaf438b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -379,7 +379,7 @@ static struct clocksource clocksource_gpt = {
379 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 379 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
380}; 380};
381 381
382static u32 notrace dmtimer_read_sched_clock(void) 382static u64 notrace dmtimer_read_sched_clock(void)
383{ 383{
384 if (clksrc.reserved) 384 if (clksrc.reserved)
385 return __omap_dm_timer_read_counter(&clksrc, 385 return __omap_dm_timer_read_counter(&clksrc,
@@ -471,7 +471,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
471 __omap_dm_timer_load_start(&clksrc, 471 __omap_dm_timer_load_start(&clksrc,
472 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 472 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
473 OMAP_TIMER_NONPOSTED); 473 OMAP_TIMER_NONPOSTED);
474 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 474 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
475 475
476 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 476 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
477 pr_err("Could not register clocksource %s\n", 477 pr_err("Could not register clocksource %s\n",
@@ -570,8 +570,7 @@ static inline void __init realtime_counter_init(void)
570 clksrc_nr, clksrc_src, clksrc_prop) \ 570 clksrc_nr, clksrc_src, clksrc_prop) \
571void __init omap##name##_gptimer_timer_init(void) \ 571void __init omap##name##_gptimer_timer_init(void) \
572{ \ 572{ \
573 if (omap_clk_init) \ 573 omap_clk_init(); \
574 omap_clk_init(); \
575 omap_dmtimer_init(); \ 574 omap_dmtimer_init(); \
576 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 575 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
577 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ 576 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
@@ -582,8 +581,7 @@ void __init omap##name##_gptimer_timer_init(void) \
582 clksrc_nr, clksrc_src, clksrc_prop) \ 581 clksrc_nr, clksrc_src, clksrc_prop) \
583void __init omap##name##_sync32k_timer_init(void) \ 582void __init omap##name##_sync32k_timer_init(void) \
584{ \ 583{ \
585 if (omap_clk_init) \ 584 omap_clk_init(); \
586 omap_clk_init(); \
587 omap_dmtimer_init(); \ 585 omap_dmtimer_init(); \
588 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ 586 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
589 /* Enable the use of clocksource="gp_timer" kernel parameter */ \ 587 /* Enable the use of clocksource="gp_timer" kernel parameter */ \
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-10 23:30:21 -0400