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-rw-r--r--arch/arm/mach-omap2/Kconfig2
-rw-r--r--arch/arm/mach-omap2/Makefile7
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c26
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c105
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c7
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c111
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c6
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c29
-rw-r--r--arch/arm/mach-omap2/board-apollon.c4
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c33
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c5
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c16
-rw-r--r--arch/arm/mach-omap2/board-flash.c34
-rw-r--r--arch/arm/mach-omap2/board-flash.h4
-rw-r--r--arch/arm/mach-omap2/board-generic.c4
-rw-r--r--arch/arm/mach-omap2/board-h4.c5
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c26
-rw-r--r--arch/arm/mach-omap2/board-igep0030.c6
-rw-r--r--arch/arm/mach-omap2/board-ldp.c27
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c14
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c238
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c20
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c30
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c11
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c83
-rw-r--r--arch/arm/mach-omap2/board-overo.c8
-rw-r--r--arch/arm/mach-omap2/board-rm680.c2
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c61
-rw-r--r--arch/arm/mach-omap2/board-rx51-video.c15
-rw-r--r--arch/arm/mach-omap2/board-rx51.c6
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c4
-rw-r--r--arch/arm/mach-omap2/board-zoom-display.c15
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c6
-rw-r--r--arch/arm/mach-omap2/board-zoom.c5
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c2
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c2
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c12
-rw-r--r--arch/arm/mach-omap2/clock2xxx.h4
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c12
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c20
-rw-r--r--arch/arm/mach-omap2/clockdomain.c28
-rw-r--r--arch/arm/mach-omap2/clockdomain.h12
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c60
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c394
-rw-r--r--arch/arm/mach-omap2/cm44xx.h1
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c21
-rw-r--r--arch/arm/mach-omap2/cminst44xx.h6
-rw-r--r--arch/arm/mach-omap2/devices.c486
-rw-r--r--arch/arm/mach-omap2/display.c45
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c7
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c113
-rw-r--r--arch/arm/mach-omap2/gpmc.c56
-rw-r--r--arch/arm/mach-omap2/hsmmc.c421
-rw-r--r--arch/arm/mach-omap2/id.c31
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/mach-omap2/iommu2.c33
-rw-r--r--arch/arm/mach-omap2/mailbox.c74
-rw-r--r--arch/arm/mach-omap2/mcbsp.c231
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c233
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c839
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c1182
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c1442
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c67
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c253
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h132
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c314
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h338
-rw-r--r--arch/arm/mach-omap2/pm-debug.c8
-rw-r--r--arch/arm/mach-omap2/powerdomain.c43
-rw-r--r--arch/arm/mach-omap2/powerdomain.h18
-rw-r--r--arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c9
-rw-r--r--arch/arm/mach-omap2/powerdomains2xxx_data.c18
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c38
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c88
-rw-r--r--arch/arm/mach-omap2/prcm-common.h8
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h4
-rw-r--r--arch/arm/mach-omap2/serial.c2
-rw-r--r--arch/arm/mach-omap2/smartreflex.c4
-rw-r--r--arch/arm/mach-omap2/timer-gp.c20
81 files changed, 6732 insertions, 1380 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 9b4e78fe3d1c..b9d8a7b2a862 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -310,6 +310,7 @@ config MACH_OMAP_4430SDP
310 depends on ARCH_OMAP4 310 depends on ARCH_OMAP4
311 select OMAP_PACKAGE_CBL 311 select OMAP_PACKAGE_CBL
312 select OMAP_PACKAGE_CBS 312 select OMAP_PACKAGE_CBS
313 select REGULATOR_FIXED_VOLTAGE
313 314
314config MACH_OMAP4_PANDA 315config MACH_OMAP4_PANDA
315 bool "OMAP4 Panda Board" 316 bool "OMAP4 Panda Board"
@@ -317,6 +318,7 @@ config MACH_OMAP4_PANDA
317 depends on ARCH_OMAP4 318 depends on ARCH_OMAP4
318 select OMAP_PACKAGE_CBL 319 select OMAP_PACKAGE_CBL
319 select OMAP_PACKAGE_CBS 320 select OMAP_PACKAGE_CBS
321 select REGULATOR_FIXED_VOLTAGE
320 322
321config OMAP3_EMU 323config OMAP3_EMU
322 bool "OMAP3 debugging peripherals" 324 bool "OMAP3 debugging peripherals"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index c5b1be9b7328..534d89a60dd9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -141,6 +141,10 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
141# EMU peripherals 141# EMU peripherals
142obj-$(CONFIG_OMAP3_EMU) += emu.o 142obj-$(CONFIG_OMAP3_EMU) += emu.o
143 143
144# L3 interconnect
145obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
146obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
147
144obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 148obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
145mailbox_mach-objs := mailbox.o 149mailbox_mach-objs := mailbox.o
146 150
@@ -251,3 +255,6 @@ obj-y += $(smc91x-m) $(smc91x-y)
251smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o 255smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
252obj-y += $(smsc911x-m) $(smsc911x-y) 256obj-y += $(smsc911x-m) $(smsc911x-y)
253obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o 257obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
258
259disp-$(CONFIG_OMAP2_DSS) := display.o
260obj-y += $(disp-m) $(disp-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index ec74c0f2051c..1fa6bb896f41 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -22,6 +22,7 @@
22#include <linux/mmc/host.h> 22#include <linux/mmc/host.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/i2c/twl.h> 24#include <linux/i2c/twl.h>
25#include <linux/regulator/machine.h>
25#include <linux/err.h> 26#include <linux/err.h>
26#include <linux/clk.h> 27#include <linux/clk.h>
27#include <linux/io.h> 28#include <linux/io.h>
@@ -141,12 +142,29 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
141 142
142static void __init omap_2430sdp_init_early(void) 143static void __init omap_2430sdp_init_early(void)
143{ 144{
144 omap_board_config = sdp2430_config;
145 omap_board_config_size = ARRAY_SIZE(sdp2430_config);
146 omap2_init_common_infrastructure(); 145 omap2_init_common_infrastructure();
147 omap2_init_common_devices(NULL, NULL); 146 omap2_init_common_devices(NULL, NULL);
148} 147}
149 148
149static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
150 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
151};
152
153/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
154static struct regulator_init_data sdp2430_vmmc1 = {
155 .constraints = {
156 .min_uV = 1850000,
157 .max_uV = 3150000,
158 .valid_modes_mask = REGULATOR_MODE_NORMAL
159 | REGULATOR_MODE_STANDBY,
160 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
161 | REGULATOR_CHANGE_MODE
162 | REGULATOR_CHANGE_STATUS,
163 },
164 .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies),
165 .consumer_supplies = &sdp2430_vmmc1_supplies[0],
166};
167
150static struct twl4030_gpio_platform_data sdp2430_gpio_data = { 168static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
151 .gpio_base = OMAP_MAX_GPIO_LINES, 169 .gpio_base = OMAP_MAX_GPIO_LINES,
152 .irq_base = TWL4030_GPIO_IRQ_BASE, 170 .irq_base = TWL4030_GPIO_IRQ_BASE,
@@ -159,6 +177,7 @@ static struct twl4030_platform_data sdp2430_twldata = {
159 177
160 /* platform_data for children goes here */ 178 /* platform_data for children goes here */
161 .gpio = &sdp2430_gpio_data, 179 .gpio = &sdp2430_gpio_data,
180 .vmmc1 = &sdp2430_vmmc1,
162}; 181};
163 182
164static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = { 183static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
@@ -225,6 +244,9 @@ static void __init omap_2430sdp_init(void)
225 244
226 omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); 245 omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
227 246
247 omap_board_config = sdp2430_config;
248 omap_board_config_size = ARRAY_SIZE(sdp2430_config);
249
228 omap2430_i2c_init(); 250 omap2430_i2c_init();
229 251
230 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); 252 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 31085883199e..5464bec156ad 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -307,31 +307,14 @@ static struct omap_dss_board_info sdp3430_dss_data = {
307 .default_device = &sdp3430_lcd_device, 307 .default_device = &sdp3430_lcd_device,
308}; 308};
309 309
310static struct platform_device sdp3430_dss_device = { 310static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
311 .name = "omapdss", 311 REGULATOR_SUPPLY("vdda_dac", "omapdss");
312 .id = -1,
313 .dev = {
314 .platform_data = &sdp3430_dss_data,
315 },
316};
317
318static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
319 .supply = "vdda_dac",
320 .dev = &sdp3430_dss_device.dev,
321};
322
323static struct platform_device *sdp3430_devices[] __initdata = {
324 &sdp3430_dss_device,
325};
326 312
327static struct omap_board_config_kernel sdp3430_config[] __initdata = { 313static struct omap_board_config_kernel sdp3430_config[] __initdata = {
328}; 314};
329 315
330static void __init omap_3430sdp_init_early(void) 316static void __init omap_3430sdp_init_early(void)
331{ 317{
332 omap_board_config = sdp3430_config;
333 omap_board_config_size = ARRAY_SIZE(sdp3430_config);
334 omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
335 omap2_init_common_infrastructure(); 318 omap2_init_common_infrastructure();
336 omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); 319 omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
337} 320}
@@ -369,18 +352,6 @@ static struct omap2_hsmmc_info mmc[] = {
369 {} /* Terminator */ 352 {} /* Terminator */
370}; 353};
371 354
372static struct regulator_consumer_supply sdp3430_vmmc1_supply = {
373 .supply = "vmmc",
374};
375
376static struct regulator_consumer_supply sdp3430_vsim_supply = {
377 .supply = "vmmc_aux",
378};
379
380static struct regulator_consumer_supply sdp3430_vmmc2_supply = {
381 .supply = "vmmc",
382};
383
384static int sdp3430_twl_gpio_setup(struct device *dev, 355static int sdp3430_twl_gpio_setup(struct device *dev,
385 unsigned gpio, unsigned ngpio) 356 unsigned gpio, unsigned ngpio)
386{ 357{
@@ -391,13 +362,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
391 mmc[1].gpio_cd = gpio + 1; 362 mmc[1].gpio_cd = gpio + 1;
392 omap2_hsmmc_init(mmc); 363 omap2_hsmmc_init(mmc);
393 364
394 /* link regulators to MMC adapters ... we "know" the
395 * regulators will be set up only *after* we return.
396 */
397 sdp3430_vmmc1_supply.dev = mmc[0].dev;
398 sdp3430_vsim_supply.dev = mmc[0].dev;
399 sdp3430_vmmc2_supply.dev = mmc[1].dev;
400
401 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ 365 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
402 gpio_request(gpio + 7, "sub_lcd_en_bkl"); 366 gpio_request(gpio + 7, "sub_lcd_en_bkl");
403 gpio_direction_output(gpio + 7, 0); 367 gpio_direction_output(gpio + 7, 0);
@@ -426,6 +390,34 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = {
426 .irq_line = 1, 390 .irq_line = 1,
427}; 391};
428 392
393/* regulator consumer mappings */
394
395/* ads7846 on SPI */
396static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
397 REGULATOR_SUPPLY("vcc", "spi1.0"),
398};
399
400static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
401 REGULATOR_SUPPLY("vdda_dac", "omapdss"),
402};
403
404/* VPLL2 for digital video outputs */
405static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
406 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
407};
408
409static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
410 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
411};
412
413static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
414 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
415};
416
417static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
418 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
419};
420
429/* 421/*
430 * Apply all the fixed voltages since most versions of U-Boot 422 * Apply all the fixed voltages since most versions of U-Boot
431 * don't bother with that initialization. 423 * don't bother with that initialization.
@@ -468,6 +460,8 @@ static struct regulator_init_data sdp3430_vaux3 = {
468 .valid_ops_mask = REGULATOR_CHANGE_MODE 460 .valid_ops_mask = REGULATOR_CHANGE_MODE
469 | REGULATOR_CHANGE_STATUS, 461 | REGULATOR_CHANGE_STATUS,
470 }, 462 },
463 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
464 .consumer_supplies = sdp3430_vaux3_supplies,
471}; 465};
472 466
473/* VAUX4 for OMAP VDD_CSI2 (camera) */ 467/* VAUX4 for OMAP VDD_CSI2 (camera) */
@@ -494,8 +488,8 @@ static struct regulator_init_data sdp3430_vmmc1 = {
494 | REGULATOR_CHANGE_MODE 488 | REGULATOR_CHANGE_MODE
495 | REGULATOR_CHANGE_STATUS, 489 | REGULATOR_CHANGE_STATUS,
496 }, 490 },
497 .num_consumer_supplies = 1, 491 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
498 .consumer_supplies = &sdp3430_vmmc1_supply, 492 .consumer_supplies = sdp3430_vmmc1_supplies,
499}; 493};
500 494
501/* VMMC2 for MMC2 card */ 495/* VMMC2 for MMC2 card */
@@ -509,8 +503,8 @@ static struct regulator_init_data sdp3430_vmmc2 = {
509 .valid_ops_mask = REGULATOR_CHANGE_MODE 503 .valid_ops_mask = REGULATOR_CHANGE_MODE
510 | REGULATOR_CHANGE_STATUS, 504 | REGULATOR_CHANGE_STATUS,
511 }, 505 },
512 .num_consumer_supplies = 1, 506 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
513 .consumer_supplies = &sdp3430_vmmc2_supply, 507 .consumer_supplies = sdp3430_vmmc2_supplies,
514}; 508};
515 509
516/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ 510/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -524,8 +518,8 @@ static struct regulator_init_data sdp3430_vsim = {
524 | REGULATOR_CHANGE_MODE 518 | REGULATOR_CHANGE_MODE
525 | REGULATOR_CHANGE_STATUS, 519 | REGULATOR_CHANGE_STATUS,
526 }, 520 },
527 .num_consumer_supplies = 1, 521 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
528 .consumer_supplies = &sdp3430_vsim_supply, 522 .consumer_supplies = sdp3430_vsim_supplies,
529}; 523};
530 524
531/* VDAC for DSS driving S-Video */ 525/* VDAC for DSS driving S-Video */
@@ -539,16 +533,8 @@ static struct regulator_init_data sdp3430_vdac = {
539 .valid_ops_mask = REGULATOR_CHANGE_MODE 533 .valid_ops_mask = REGULATOR_CHANGE_MODE
540 | REGULATOR_CHANGE_STATUS, 534 | REGULATOR_CHANGE_STATUS,
541 }, 535 },
542 .num_consumer_supplies = 1, 536 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
543 .consumer_supplies = &sdp3430_vdda_dac_supply, 537 .consumer_supplies = sdp3430_vdda_dac_supplies,
544};
545
546/* VPLL2 for digital video outputs */
547static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
548 {
549 .supply = "vdds_dsi",
550 .dev = &sdp3430_dss_device.dev,
551 }
552}; 538};
553 539
554static struct regulator_init_data sdp3430_vpll2 = { 540static struct regulator_init_data sdp3430_vpll2 = {
@@ -566,9 +552,7 @@ static struct regulator_init_data sdp3430_vpll2 = {
566 .consumer_supplies = sdp3430_vpll2_supplies, 552 .consumer_supplies = sdp3430_vpll2_supplies,
567}; 553};
568 554
569static struct twl4030_codec_audio_data sdp3430_audio = { 555static struct twl4030_codec_audio_data sdp3430_audio;
570 .audio_mclk = 26000000,
571};
572 556
573static struct twl4030_codec_data sdp3430_codec = { 557static struct twl4030_codec_data sdp3430_codec = {
574 .audio_mclk = 26000000, 558 .audio_mclk = 26000000,
@@ -799,8 +783,11 @@ static struct omap_musb_board_data musb_board_data = {
799static void __init omap_3430sdp_init(void) 783static void __init omap_3430sdp_init(void)
800{ 784{
801 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 785 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
786 omap_board_config = sdp3430_config;
787 omap_board_config_size = ARRAY_SIZE(sdp3430_config);
788 omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
802 omap3430_i2c_init(); 789 omap3430_i2c_init();
803 platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); 790 omap_display_init(&sdp3430_dss_data);
804 if (omap_rev() > OMAP3430_REV_ES1_0) 791 if (omap_rev() > OMAP3430_REV_ES1_0)
805 ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2; 792 ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
806 else 793 else
@@ -812,7 +799,7 @@ static void __init omap_3430sdp_init(void)
812 omap_serial_init(); 799 omap_serial_init();
813 usb_musb_init(&musb_board_data); 800 usb_musb_init(&musb_board_data);
814 board_smc91x_init(); 801 board_smc91x_init();
815 board_flash_init(sdp_flash_partitions, chip_sel_3430); 802 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
816 sdp3430_display_init(); 803 sdp3430_display_init();
817 enable_board_wakeup_source(); 804 enable_board_wakeup_source();
818 usb_ehci_init(&ehci_pdata); 805 usb_ehci_init(&ehci_pdata);
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 16538757291a..c4e22b32e47f 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -11,6 +11,7 @@
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <linux/input.h> 12#include <linux/input.h>
13#include <linux/gpio.h> 13#include <linux/gpio.h>
14#include <linux/mtd/nand.h>
14 15
15#include <asm/mach-types.h> 16#include <asm/mach-types.h>
16#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
@@ -71,8 +72,6 @@ static struct omap_board_config_kernel sdp_config[] __initdata = {
71 72
72static void __init omap_sdp_init_early(void) 73static void __init omap_sdp_init_early(void)
73{ 74{
74 omap_board_config = sdp_config;
75 omap_board_config_size = ARRAY_SIZE(sdp_config);
76 omap2_init_common_infrastructure(); 75 omap2_init_common_infrastructure();
77 omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, 76 omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
78 h8mbx00u0mer0em_sdrc_params); 77 h8mbx00u0mer0em_sdrc_params);
@@ -205,10 +204,12 @@ static struct flash_partitions sdp_flash_partitions[] = {
205static void __init omap_sdp_init(void) 204static void __init omap_sdp_init(void)
206{ 205{
207 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); 206 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
207 omap_board_config = sdp_config;
208 omap_board_config_size = ARRAY_SIZE(sdp_config);
208 zoom_peripherals_init(); 209 zoom_peripherals_init();
209 zoom_display_init(); 210 zoom_display_init();
210 board_smc91x_init(); 211 board_smc91x_init();
211 board_flash_init(sdp_flash_partitions, chip_sel_sdp); 212 board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
212 enable_board_wakeup_source(); 213 enable_board_wakeup_source();
213 usb_ehci_init(&ehci_pdata); 214 usb_ehci_init(&ehci_pdata);
214} 215}
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index bf8268438d00..85805d432e38 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -35,6 +35,7 @@
35#include <plat/common.h> 35#include <plat/common.h>
36#include <plat/usb.h> 36#include <plat/usb.h>
37#include <plat/mmc.h> 37#include <plat/mmc.h>
38#include <plat/omap4-keypad.h>
38 39
39#include "mux.h" 40#include "mux.h"
40#include "hsmmc.h" 41#include "hsmmc.h"
@@ -47,6 +48,90 @@
47#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 48#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
48#define OMAP4_SFH7741_ENABLE_GPIO 188 49#define OMAP4_SFH7741_ENABLE_GPIO 188
49 50
51static const int sdp4430_keymap[] = {
52 KEY(0, 0, KEY_E),
53 KEY(0, 1, KEY_R),
54 KEY(0, 2, KEY_T),
55 KEY(0, 3, KEY_HOME),
56 KEY(0, 4, KEY_F5),
57 KEY(0, 5, KEY_UNKNOWN),
58 KEY(0, 6, KEY_I),
59 KEY(0, 7, KEY_LEFTSHIFT),
60
61 KEY(1, 0, KEY_D),
62 KEY(1, 1, KEY_F),
63 KEY(1, 2, KEY_G),
64 KEY(1, 3, KEY_SEND),
65 KEY(1, 4, KEY_F6),
66 KEY(1, 5, KEY_UNKNOWN),
67 KEY(1, 6, KEY_K),
68 KEY(1, 7, KEY_ENTER),
69
70 KEY(2, 0, KEY_X),
71 KEY(2, 1, KEY_C),
72 KEY(2, 2, KEY_V),
73 KEY(2, 3, KEY_END),
74 KEY(2, 4, KEY_F7),
75 KEY(2, 5, KEY_UNKNOWN),
76 KEY(2, 6, KEY_DOT),
77 KEY(2, 7, KEY_CAPSLOCK),
78
79 KEY(3, 0, KEY_Z),
80 KEY(3, 1, KEY_KPPLUS),
81 KEY(3, 2, KEY_B),
82 KEY(3, 3, KEY_F1),
83 KEY(3, 4, KEY_F8),
84 KEY(3, 5, KEY_UNKNOWN),
85 KEY(3, 6, KEY_O),
86 KEY(3, 7, KEY_SPACE),
87
88 KEY(4, 0, KEY_W),
89 KEY(4, 1, KEY_Y),
90 KEY(4, 2, KEY_U),
91 KEY(4, 3, KEY_F2),
92 KEY(4, 4, KEY_VOLUMEUP),
93 KEY(4, 5, KEY_UNKNOWN),
94 KEY(4, 6, KEY_L),
95 KEY(4, 7, KEY_LEFT),
96
97 KEY(5, 0, KEY_S),
98 KEY(5, 1, KEY_H),
99 KEY(5, 2, KEY_J),
100 KEY(5, 3, KEY_F3),
101 KEY(5, 4, KEY_F9),
102 KEY(5, 5, KEY_VOLUMEDOWN),
103 KEY(5, 6, KEY_M),
104 KEY(5, 7, KEY_RIGHT),
105
106 KEY(6, 0, KEY_Q),
107 KEY(6, 1, KEY_A),
108 KEY(6, 2, KEY_N),
109 KEY(6, 3, KEY_BACK),
110 KEY(6, 4, KEY_BACKSPACE),
111 KEY(6, 5, KEY_UNKNOWN),
112 KEY(6, 6, KEY_P),
113 KEY(6, 7, KEY_UP),
114
115 KEY(7, 0, KEY_PROG1),
116 KEY(7, 1, KEY_PROG2),
117 KEY(7, 2, KEY_PROG3),
118 KEY(7, 3, KEY_PROG4),
119 KEY(7, 4, KEY_F4),
120 KEY(7, 5, KEY_UNKNOWN),
121 KEY(7, 6, KEY_OK),
122 KEY(7, 7, KEY_DOWN),
123};
124
125static struct matrix_keymap_data sdp4430_keymap_data = {
126 .keymap = sdp4430_keymap,
127 .keymap_size = ARRAY_SIZE(sdp4430_keymap),
128};
129
130static struct omap4_keypad_platform_data sdp4430_keypad_data = {
131 .keymap_data = &sdp4430_keymap_data,
132 .rows = 8,
133 .cols = 8,
134};
50static struct gpio_led sdp4430_gpio_leds[] = { 135static struct gpio_led sdp4430_gpio_leds[] = {
51 { 136 {
52 .name = "omap4:green:debug0", 137 .name = "omap4:green:debug0",
@@ -240,8 +325,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
240 325
241static void __init omap_4430sdp_init_early(void) 326static void __init omap_4430sdp_init_early(void)
242{ 327{
243 omap_board_config = sdp4430_config;
244 omap_board_config_size = ARRAY_SIZE(sdp4430_config);
245 omap2_init_common_infrastructure(); 328 omap2_init_common_infrastructure();
246 omap2_init_common_devices(NULL, NULL); 329 omap2_init_common_devices(NULL, NULL);
247#ifdef CONFIG_OMAP_32K_TIMER 330#ifdef CONFIG_OMAP_32K_TIMER
@@ -264,11 +347,6 @@ static struct twl4030_usb_data omap4_usbphy_data = {
264 347
265static struct omap2_hsmmc_info mmc[] = { 348static struct omap2_hsmmc_info mmc[] = {
266 { 349 {
267 .mmc = 1,
268 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
269 .gpio_wp = -EINVAL,
270 },
271 {
272 .mmc = 2, 350 .mmc = 2,
273 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 351 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
274 .gpio_cd = -EINVAL, 352 .gpio_cd = -EINVAL,
@@ -276,19 +354,24 @@ static struct omap2_hsmmc_info mmc[] = {
276 .nonremovable = true, 354 .nonremovable = true,
277 .ocr_mask = MMC_VDD_29_30, 355 .ocr_mask = MMC_VDD_29_30,
278 }, 356 },
357 {
358 .mmc = 1,
359 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
360 .gpio_wp = -EINVAL,
361 },
279 {} /* Terminator */ 362 {} /* Terminator */
280}; 363};
281 364
282static struct regulator_consumer_supply sdp4430_vaux_supply[] = { 365static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
283 { 366 {
284 .supply = "vmmc", 367 .supply = "vmmc",
285 .dev_name = "mmci-omap-hs.1", 368 .dev_name = "omap_hsmmc.1",
286 }, 369 },
287}; 370};
288static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { 371static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
289 { 372 {
290 .supply = "vmmc", 373 .supply = "vmmc",
291 .dev_name = "mmci-omap-hs.0", 374 .dev_name = "omap_hsmmc.0",
292 }, 375 },
293}; 376};
294 377
@@ -422,7 +505,6 @@ static struct regulator_init_data sdp4430_vana = {
422 .constraints = { 505 .constraints = {
423 .min_uV = 2100000, 506 .min_uV = 2100000,
424 .max_uV = 2100000, 507 .max_uV = 2100000,
425 .apply_uV = true,
426 .valid_modes_mask = REGULATOR_MODE_NORMAL 508 .valid_modes_mask = REGULATOR_MODE_NORMAL
427 | REGULATOR_MODE_STANDBY, 509 | REGULATOR_MODE_STANDBY,
428 .valid_ops_mask = REGULATOR_CHANGE_MODE 510 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -434,7 +516,6 @@ static struct regulator_init_data sdp4430_vcxio = {
434 .constraints = { 516 .constraints = {
435 .min_uV = 1800000, 517 .min_uV = 1800000,
436 .max_uV = 1800000, 518 .max_uV = 1800000,
437 .apply_uV = true,
438 .valid_modes_mask = REGULATOR_MODE_NORMAL 519 .valid_modes_mask = REGULATOR_MODE_NORMAL
439 | REGULATOR_MODE_STANDBY, 520 | REGULATOR_MODE_STANDBY,
440 .valid_ops_mask = REGULATOR_CHANGE_MODE 521 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -446,7 +527,6 @@ static struct regulator_init_data sdp4430_vdac = {
446 .constraints = { 527 .constraints = {
447 .min_uV = 1800000, 528 .min_uV = 1800000,
448 .max_uV = 1800000, 529 .max_uV = 1800000,
449 .apply_uV = true,
450 .valid_modes_mask = REGULATOR_MODE_NORMAL 530 .valid_modes_mask = REGULATOR_MODE_NORMAL
451 | REGULATOR_MODE_STANDBY, 531 | REGULATOR_MODE_STANDBY,
452 .valid_ops_mask = REGULATOR_CHANGE_MODE 532 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -558,6 +638,9 @@ static void __init omap_4430sdp_init(void)
558 package = OMAP_PACKAGE_CBL; 638 package = OMAP_PACKAGE_CBL;
559 omap4_mux_init(board_mux, package); 639 omap4_mux_init(board_mux, package);
560 640
641 omap_board_config = sdp4430_config;
642 omap_board_config_size = ARRAY_SIZE(sdp4430_config);
643
561 omap4_i2c_init(); 644 omap4_i2c_init();
562 omap_sfh7741prox_init(); 645 omap_sfh7741prox_init();
563 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); 646 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
@@ -574,6 +657,10 @@ static void __init omap_4430sdp_init(void)
574 spi_register_board_info(sdp4430_spi_board_info, 657 spi_register_board_info(sdp4430_spi_board_info,
575 ARRAY_SIZE(sdp4430_spi_board_info)); 658 ARRAY_SIZE(sdp4430_spi_board_info));
576 } 659 }
660
661 status = omap4_keyboard_init(&sdp4430_keypad_data);
662 if (status)
663 pr_err("Keypad initialization failed: %d\n", status);
577} 664}
578 665
579static void __init omap_4430sdp_map_io(void) 666static void __init omap_4430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index ae3a83d47dab..f53bbb2c3478 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -51,9 +51,6 @@ static struct omap_board_mux board_mux[] __initdata = {
51 51
52static void __init am3517_crane_init_early(void) 52static void __init am3517_crane_init_early(void)
53{ 53{
54 omap_board_config = am3517_crane_config;
55 omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
56
57 omap2_init_common_infrastructure(); 54 omap2_init_common_infrastructure();
58 omap2_init_common_devices(NULL, NULL); 55 omap2_init_common_devices(NULL, NULL);
59} 56}
@@ -76,6 +73,9 @@ static void __init am3517_crane_init(void)
76 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 73 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
77 omap_serial_init(); 74 omap_serial_init();
78 75
76 omap_board_config = am3517_crane_config;
77 omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
78
79 /* Configure GPIO for EHCI port */ 79 /* Configure GPIO for EHCI port */
80 if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { 80 if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
81 pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", 81 pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 8532d6e0d53a..77541cf59bd4 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -200,6 +200,9 @@ static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
200}; 200};
201static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = { 201static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
202 { 202 {
203 I2C_BOARD_INFO("tlv320aic23", 0x1A),
204 },
205 {
203 I2C_BOARD_INFO("tca6416", 0x21), 206 I2C_BOARD_INFO("tca6416", 0x21),
204 .platform_data = &am3517evm_gpio_expander_info_0, 207 .platform_data = &am3517evm_gpio_expander_info_0,
205 }, 208 },
@@ -378,28 +381,11 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
378 .default_device = &am3517_evm_lcd_device, 381 .default_device = &am3517_evm_lcd_device,
379}; 382};
380 383
381static struct platform_device am3517_evm_dss_device = {
382 .name = "omapdss",
383 .id = -1,
384 .dev = {
385 .platform_data = &am3517_evm_dss_data,
386 },
387};
388
389/* 384/*
390 * Board initialization 385 * Board initialization
391 */ 386 */
392static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
393};
394
395static struct platform_device *am3517_evm_devices[] __initdata = {
396 &am3517_evm_dss_device,
397};
398
399static void __init am3517_evm_init_early(void) 387static void __init am3517_evm_init_early(void)
400{ 388{
401 omap_board_config = am3517_evm_config;
402 omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
403 omap2_init_common_infrastructure(); 389 omap2_init_common_infrastructure();
404 omap2_init_common_devices(NULL, NULL); 390 omap2_init_common_devices(NULL, NULL);
405} 391}
@@ -493,14 +479,17 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
493 platform_device_register(&am3517_hecc_device); 479 platform_device_register(&am3517_hecc_device);
494} 480}
495 481
482static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
483};
484
496static void __init am3517_evm_init(void) 485static void __init am3517_evm_init(void)
497{ 486{
487 omap_board_config = am3517_evm_config;
488 omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
498 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 489 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
499 490
500 am3517_evm_i2c_init(); 491 am3517_evm_i2c_init();
501 platform_add_devices(am3517_evm_devices, 492 omap_display_init(&am3517_evm_dss_data);
502 ARRAY_SIZE(am3517_evm_devices));
503
504 omap_serial_init(); 493 omap_serial_init();
505 494
506 /* Configure GPIO for EHCI port */ 495 /* Configure GPIO for EHCI port */
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 4ef4aad4e719..f4f8374a0298 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -276,8 +276,6 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
276 276
277static void __init omap_apollon_init_early(void) 277static void __init omap_apollon_init_early(void)
278{ 278{
279 omap_board_config = apollon_config;
280 omap_board_config_size = ARRAY_SIZE(apollon_config);
281 omap2_init_common_infrastructure(); 279 omap2_init_common_infrastructure();
282 omap2_init_common_devices(NULL, NULL); 280 omap2_init_common_devices(NULL, NULL);
283} 281}
@@ -319,6 +317,8 @@ static void __init omap_apollon_init(void)
319 u32 v; 317 u32 v;
320 318
321 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); 319 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
320 omap_board_config = apollon_config;
321 omap_board_config_size = ARRAY_SIZE(apollon_config);
322 322
323 apollon_init_smc91x(); 323 apollon_init_smc91x();
324 apollon_led_init(); 324 apollon_led_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 9e4de92a5798..27bea540ccbb 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -401,14 +401,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
401 .default_device = &cm_t35_dvi_device, 401 .default_device = &cm_t35_dvi_device,
402}; 402};
403 403
404static struct platform_device cm_t35_dss_device = {
405 .name = "omapdss",
406 .id = -1,
407 .dev = {
408 .platform_data = &cm_t35_dss_data,
409 },
410};
411
412static struct omap2_mcspi_device_config tdo24m_mcspi_config = { 404static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
413 .turbo_mode = 0, 405 .turbo_mode = 0,
414 .single_channel = 1, /* 0: slave, 1: master */ 406 .single_channel = 1, /* 0: slave, 1: master */
@@ -468,7 +460,7 @@ static void __init cm_t35_init_display(void)
468 msleep(50); 460 msleep(50);
469 gpio_set_value(lcd_en_gpio, 1); 461 gpio_set_value(lcd_en_gpio, 1);
470 462
471 err = platform_device_register(&cm_t35_dss_device); 463 err = omap_display_init(&cm_t35_dss_data);
472 if (err) { 464 if (err) {
473 pr_err("CM-T35: failed to register DSS device\n"); 465 pr_err("CM-T35: failed to register DSS device\n");
474 goto err_dev_reg; 466 goto err_dev_reg;
@@ -495,15 +487,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
495 .supply = "vmmc_aux", 487 .supply = "vmmc_aux",
496}; 488};
497 489
498static struct regulator_consumer_supply cm_t35_vdac_supply = { 490static struct regulator_consumer_supply cm_t35_vdac_supply =
499 .supply = "vdda_dac", 491 REGULATOR_SUPPLY("vdda_dac", "omapdss");
500 .dev = &cm_t35_dss_device.dev,
501};
502 492
503static struct regulator_consumer_supply cm_t35_vdvi_supply = { 493static struct regulator_consumer_supply cm_t35_vdvi_supply =
504 .supply = "vdvi", 494 REGULATOR_SUPPLY("vdvi", "omapdss");
505 .dev = &cm_t35_dss_device.dev,
506};
507 495
508/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ 496/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
509static struct regulator_init_data cm_t35_vmmc1 = { 497static struct regulator_init_data cm_t35_vmmc1 = {
@@ -680,14 +668,8 @@ static void __init cm_t35_init_i2c(void)
680 ARRAY_SIZE(cm_t35_i2c_boardinfo)); 668 ARRAY_SIZE(cm_t35_i2c_boardinfo));
681} 669}
682 670
683static struct omap_board_config_kernel cm_t35_config[] __initdata = {
684};
685
686static void __init cm_t35_init_early(void) 671static void __init cm_t35_init_early(void)
687{ 672{
688 omap_board_config = cm_t35_config;
689 omap_board_config_size = ARRAY_SIZE(cm_t35_config);
690
691 omap2_init_common_infrastructure(); 673 omap2_init_common_infrastructure();
692 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, 674 omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
693 mt46h32m32lf6_sdrc_params); 675 mt46h32m32lf6_sdrc_params);
@@ -797,8 +779,13 @@ static struct omap_musb_board_data musb_board_data = {
797 .power = 100, 779 .power = 100,
798}; 780};
799 781
782static struct omap_board_config_kernel cm_t35_config[] __initdata = {
783};
784
800static void __init cm_t35_init(void) 785static void __init cm_t35_init(void)
801{ 786{
787 omap_board_config = cm_t35_config;
788 omap_board_config_size = ARRAY_SIZE(cm_t35_config);
802 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); 789 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
803 omap_serial_init(); 790 omap_serial_init();
804 cm_t35_init_i2c(); 791 cm_t35_init_i2c();
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 38bef6d004c9..9da6e8240e8b 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -256,9 +256,6 @@ static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
256 256
257static void __init cm_t3517_init_early(void) 257static void __init cm_t3517_init_early(void)
258{ 258{
259 omap_board_config = cm_t3517_config;
260 omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
261
262 omap2_init_common_infrastructure(); 259 omap2_init_common_infrastructure();
263 omap2_init_common_devices(NULL, NULL); 260 omap2_init_common_devices(NULL, NULL);
264} 261}
@@ -293,6 +290,8 @@ static void __init cm_t3517_init(void)
293{ 290{
294 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 291 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
295 omap_serial_init(); 292 omap_serial_init();
293 omap_board_config = cm_t3517_config;
294 omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
296 cm_t3517_init_leds(); 295 cm_t3517_init_leds();
297 cm_t3517_init_nand(); 296 cm_t3517_init_nand();
298 cm_t3517_init_rtc(); 297 cm_t3517_init_rtc();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index af742887e834..728f27c5bcb1 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -140,7 +140,7 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
140} 140}
141 141
142static struct regulator_consumer_supply devkit8000_vmmc1_supply = 142static struct regulator_consumer_supply devkit8000_vmmc1_supply =
143 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 143 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
144 144
145 145
146/* ads7846 on SPI */ 146/* ads7846 on SPI */
@@ -195,14 +195,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
195 .default_device = &devkit8000_lcd_device, 195 .default_device = &devkit8000_lcd_device,
196}; 196};
197 197
198static struct platform_device devkit8000_dss_device = {
199 .name = "omapdss",
200 .id = -1,
201 .dev = {
202 .platform_data = &devkit8000_dss_data,
203 },
204};
205
206static struct regulator_consumer_supply devkit8000_vdda_dac_supply = 198static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
207 REGULATOR_SUPPLY("vdda_dac", "omapdss"); 199 REGULATOR_SUPPLY("vdda_dac", "omapdss");
208 200
@@ -350,9 +342,7 @@ static struct twl4030_usb_data devkit8000_usb_data = {
350 .usb_mode = T2_USB_MODE_ULPI, 342 .usb_mode = T2_USB_MODE_ULPI,
351}; 343};
352 344
353static struct twl4030_codec_audio_data devkit8000_audio_data = { 345static struct twl4030_codec_audio_data devkit8000_audio_data;
354 .audio_mclk = 26000000,
355};
356 346
357static struct twl4030_codec_data devkit8000_codec_data = { 347static struct twl4030_codec_data devkit8000_codec_data = {
358 .audio_mclk = 26000000, 348 .audio_mclk = 26000000,
@@ -579,7 +569,6 @@ static void __init omap_dm9000_init(void)
579} 569}
580 570
581static struct platform_device *devkit8000_devices[] __initdata = { 571static struct platform_device *devkit8000_devices[] __initdata = {
582 &devkit8000_dss_device,
583 &leds_gpio, 572 &leds_gpio,
584 &keys_gpio, 573 &keys_gpio,
585 &omap_dm9000_dev, 574 &omap_dm9000_dev,
@@ -801,6 +790,7 @@ static void __init devkit8000_init(void)
801 platform_add_devices(devkit8000_devices, 790 platform_add_devices(devkit8000_devices,
802 ARRAY_SIZE(devkit8000_devices)); 791 ARRAY_SIZE(devkit8000_devices));
803 792
793 omap_display_init(&devkit8000_dss_data);
804 spi_register_board_info(devkit8000_spi_board_info, 794 spi_register_board_info(devkit8000_spi_board_info,
805 ARRAY_SIZE(devkit8000_spi_board_info)); 795 ARRAY_SIZE(devkit8000_spi_board_info));
806 796
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index fd38c05bb47f..729892fdcf2e 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * board-sdp-flash.c 2 * board-flash.c
3 * Modified from mach-omap2/board-3430sdp-flash.c 3 * Modified from mach-omap2/board-3430sdp-flash.c
4 * 4 *
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009 Nokia Corporation
@@ -16,6 +16,7 @@
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h> 17#include <linux/mtd/physmap.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <plat/irqs.h>
19 20
20#include <plat/gpmc.h> 21#include <plat/gpmc.h>
21#include <plat/nand.h> 22#include <plat/nand.h>
@@ -73,11 +74,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
73 + FLASH_SIZE_SDPV1 - 1; 74 + FLASH_SIZE_SDPV1 - 1;
74 } 75 }
75 if (err < 0) { 76 if (err < 0) {
76 printk(KERN_ERR "NOR: Can't request GPMC CS\n"); 77 pr_err("NOR: Can't request GPMC CS\n");
77 return; 78 return;
78 } 79 }
79 if (platform_device_register(&board_nor_device) < 0) 80 if (platform_device_register(&board_nor_device) < 0)
80 printk(KERN_ERR "Unable to register NOR device\n"); 81 pr_err("Unable to register NOR device\n");
81} 82}
82 83
83#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ 84#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
@@ -139,17 +140,21 @@ static struct omap_nand_platform_data board_nand_data = {
139}; 140};
140 141
141void 142void
142__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) 143__init board_nand_init(struct mtd_partition *nand_parts,
144 u8 nr_parts, u8 cs, int nand_type)
143{ 145{
144 board_nand_data.cs = cs; 146 board_nand_data.cs = cs;
145 board_nand_data.parts = nand_parts; 147 board_nand_data.parts = nand_parts;
146 board_nand_data.nr_parts = nr_parts; 148 board_nand_data.nr_parts = nr_parts;
149 board_nand_data.devsize = nand_type;
147 150
151 board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
152 board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
148 gpmc_nand_init(&board_nand_data); 153 gpmc_nand_init(&board_nand_data);
149} 154}
150#else 155#else
151void 156void
152__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) 157__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
153{ 158{
154} 159}
155#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ 160#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -189,12 +194,12 @@ unmap:
189} 194}
190 195
191/** 196/**
192 * sdp3430_flash_init - Identify devices connected to GPMC and register. 197 * board_flash_init - Identify devices connected to GPMC and register.
193 * 198 *
194 * @return - void. 199 * @return - void.
195 */ 200 */
196void board_flash_init(struct flash_partitions partition_info[], 201void board_flash_init(struct flash_partitions partition_info[],
197 char chip_sel_board[][GPMC_CS_NUM]) 202 char chip_sel_board[][GPMC_CS_NUM], int nand_type)
198{ 203{
199 u8 cs = 0; 204 u8 cs = 0;
200 u8 norcs = GPMC_CS_NUM + 1; 205 u8 norcs = GPMC_CS_NUM + 1;
@@ -208,7 +213,7 @@ void board_flash_init(struct flash_partitions partition_info[],
208 */ 213 */
209 idx = get_gpmc0_type(); 214 idx = get_gpmc0_type();
210 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { 215 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
211 printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); 216 pr_err("%s: Invalid chip select: %d\n", __func__, cs);
212 return; 217 return;
213 } 218 }
214 config_sel = (unsigned char *)(chip_sel_board[idx]); 219 config_sel = (unsigned char *)(chip_sel_board[idx]);
@@ -232,23 +237,20 @@ void board_flash_init(struct flash_partitions partition_info[],
232 } 237 }
233 238
234 if (norcs > GPMC_CS_NUM) 239 if (norcs > GPMC_CS_NUM)
235 printk(KERN_INFO "NOR: Unable to find configuration " 240 pr_err("NOR: Unable to find configuration in GPMC\n");
236 "in GPMC\n");
237 else 241 else
238 board_nor_init(partition_info[0].parts, 242 board_nor_init(partition_info[0].parts,
239 partition_info[0].nr_parts, norcs); 243 partition_info[0].nr_parts, norcs);
240 244
241 if (onenandcs > GPMC_CS_NUM) 245 if (onenandcs > GPMC_CS_NUM)
242 printk(KERN_INFO "OneNAND: Unable to find configuration " 246 pr_err("OneNAND: Unable to find configuration in GPMC\n");
243 "in GPMC\n");
244 else 247 else
245 board_onenand_init(partition_info[1].parts, 248 board_onenand_init(partition_info[1].parts,
246 partition_info[1].nr_parts, onenandcs); 249 partition_info[1].nr_parts, onenandcs);
247 250
248 if (nandcs > GPMC_CS_NUM) 251 if (nandcs > GPMC_CS_NUM)
249 printk(KERN_INFO "NAND: Unable to find configuration " 252 pr_err("NAND: Unable to find configuration in GPMC\n");
250 "in GPMC\n");
251 else 253 else
252 board_nand_init(partition_info[2].parts, 254 board_nand_init(partition_info[2].parts,
253 partition_info[2].nr_parts, nandcs); 255 partition_info[2].nr_parts, nandcs, nand_type);
254} 256}
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index 69befe00dd2f..c240a3f8d163 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -25,6 +25,6 @@ struct flash_partitions {
25}; 25};
26 26
27extern void board_flash_init(struct flash_partitions [], 27extern void board_flash_init(struct flash_partitions [],
28 char chip_sel[][GPMC_CS_NUM]); 28 char chip_sel[][GPMC_CS_NUM], int nand_type);
29extern void board_nand_init(struct mtd_partition *nand_parts, 29extern void board_nand_init(struct mtd_partition *nand_parts,
30 u8 nr_parts, u8 cs); 30 u8 nr_parts, u8 cs, int nand_type);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 682da9251db6..73e3c31e8508 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -35,8 +35,6 @@ static struct omap_board_config_kernel generic_config[] = {
35 35
36static void __init omap_generic_init_early(void) 36static void __init omap_generic_init_early(void)
37{ 37{
38 omap_board_config = generic_config;
39 omap_board_config_size = ARRAY_SIZE(generic_config);
40 omap2_init_common_infrastructure(); 38 omap2_init_common_infrastructure();
41 omap2_init_common_devices(NULL, NULL); 39 omap2_init_common_devices(NULL, NULL);
42} 40}
@@ -44,6 +42,8 @@ static void __init omap_generic_init_early(void)
44static void __init omap_generic_init(void) 42static void __init omap_generic_init(void)
45{ 43{
46 omap_serial_init(); 44 omap_serial_init();
45 omap_board_config = generic_config;
46 omap_board_config_size = ARRAY_SIZE(generic_config);
47} 47}
48 48
49static void __init omap_generic_map_io(void) 49static void __init omap_generic_map_io(void)
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f6a3872f72fa..7e6bf4fa1535 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -292,8 +292,6 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
292 292
293static void __init omap_h4_init_early(void) 293static void __init omap_h4_init_early(void)
294{ 294{
295 omap_board_config = h4_config;
296 omap_board_config_size = ARRAY_SIZE(h4_config);
297 omap2_init_common_infrastructure(); 295 omap2_init_common_infrastructure();
298 omap2_init_common_devices(NULL, NULL); 296 omap2_init_common_devices(NULL, NULL);
299} 297}
@@ -334,6 +332,9 @@ static void __init omap_h4_init(void)
334{ 332{
335 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); 333 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
336 334
335 omap_board_config = h4_config;
336 omap_board_config_size = ARRAY_SIZE(h4_config);
337
337 /* 338 /*
338 * Make sure the serial ports are muxed on at this point. 339 * Make sure the serial ports are muxed on at this point.
339 * You have to mux them off in device drivers later on 340 * You have to mux them off in device drivers later on
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index dd0b1ac3b662..c4b3c1c47ec6 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -250,7 +250,7 @@ static inline void __init igep2_init_smsc911x(void) { }
250#endif 250#endif
251 251
252static struct regulator_consumer_supply igep2_vmmc1_supply = 252static struct regulator_consumer_supply igep2_vmmc1_supply =
253 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 253 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
254 254
255/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 255/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
256static struct regulator_init_data igep2_vmmc1 = { 256static struct regulator_init_data igep2_vmmc1 = {
@@ -268,7 +268,7 @@ static struct regulator_init_data igep2_vmmc1 = {
268}; 268};
269 269
270static struct regulator_consumer_supply igep2_vio_supply = 270static struct regulator_consumer_supply igep2_vio_supply =
271 REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); 271 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
272 272
273static struct regulator_init_data igep2_vio = { 273static struct regulator_init_data igep2_vio = {
274 .constraints = { 274 .constraints = {
@@ -286,7 +286,7 @@ static struct regulator_init_data igep2_vio = {
286}; 286};
287 287
288static struct regulator_consumer_supply igep2_vmmc2_supply = 288static struct regulator_consumer_supply igep2_vmmc2_supply =
289 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 289 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
290 290
291static struct regulator_init_data igep2_vmmc2 = { 291static struct regulator_init_data igep2_vmmc2 = {
292 .constraints = { 292 .constraints = {
@@ -485,18 +485,8 @@ static struct omap_dss_board_info igep2_dss_data = {
485 .default_device = &igep2_dvi_device, 485 .default_device = &igep2_dvi_device,
486}; 486};
487 487
488static struct platform_device igep2_dss_device = { 488static struct regulator_consumer_supply igep2_vpll2_supply =
489 .name = "omapdss", 489 REGULATOR_SUPPLY("vdds_dsi", "omapdss");
490 .id = -1,
491 .dev = {
492 .platform_data = &igep2_dss_data,
493 },
494};
495
496static struct regulator_consumer_supply igep2_vpll2_supply = {
497 .supply = "vdds_dsi",
498 .dev = &igep2_dss_device.dev,
499};
500 490
501static struct regulator_init_data igep2_vpll2 = { 491static struct regulator_init_data igep2_vpll2 = {
502 .constraints = { 492 .constraints = {
@@ -521,7 +511,6 @@ static void __init igep2_display_init(void)
521} 511}
522 512
523static struct platform_device *igep2_devices[] __initdata = { 513static struct platform_device *igep2_devices[] __initdata = {
524 &igep2_dss_device,
525 &igep2_vwlan_device, 514 &igep2_vwlan_device,
526}; 515};
527 516
@@ -532,9 +521,7 @@ static void __init igep2_init_early(void)
532 m65kxxxxam_sdrc_params); 521 m65kxxxxam_sdrc_params);
533} 522}
534 523
535static struct twl4030_codec_audio_data igep2_audio_data = { 524static struct twl4030_codec_audio_data igep2_audio_data;
536 .audio_mclk = 26000000,
537};
538 525
539static struct twl4030_codec_data igep2_codec_data = { 526static struct twl4030_codec_data igep2_codec_data = {
540 .audio_mclk = 26000000, 527 .audio_mclk = 26000000,
@@ -696,6 +683,7 @@ static void __init igep2_init(void)
696 /* Register I2C busses and drivers */ 683 /* Register I2C busses and drivers */
697 igep2_i2c_init(); 684 igep2_i2c_init();
698 platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); 685 platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
686 omap_display_init(&igep2_dss_data);
699 omap_serial_init(); 687 omap_serial_init();
700 usb_musb_init(&musb_board_data); 688 usb_musb_init(&musb_board_data);
701 usb_ehci_init(&ehci_pdata); 689 usb_ehci_init(&ehci_pdata);
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index d75028e48f5d..4273d0672ef6 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -142,7 +142,7 @@ static void __init igep3_flash_init(void) {}
142#endif 142#endif
143 143
144static struct regulator_consumer_supply igep3_vmmc1_supply = 144static struct regulator_consumer_supply igep3_vmmc1_supply =
145 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 145 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
146 146
147/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 147/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
148static struct regulator_init_data igep3_vmmc1 = { 148static struct regulator_init_data igep3_vmmc1 = {
@@ -160,7 +160,7 @@ static struct regulator_init_data igep3_vmmc1 = {
160}; 160};
161 161
162static struct regulator_consumer_supply igep3_vio_supply = 162static struct regulator_consumer_supply igep3_vio_supply =
163 REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); 163 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
164 164
165static struct regulator_init_data igep3_vio = { 165static struct regulator_init_data igep3_vio = {
166 .constraints = { 166 .constraints = {
@@ -178,7 +178,7 @@ static struct regulator_init_data igep3_vio = {
178}; 178};
179 179
180static struct regulator_consumer_supply igep3_vmmc2_supply = 180static struct regulator_consumer_supply igep3_vmmc2_supply =
181 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 181 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
182 182
183static struct regulator_init_data igep3_vmmc2 = { 183static struct regulator_init_data igep3_vmmc2 = {
184 .constraints = { 184 .constraints = {
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8eb2cb7cbc7..e2ba77957a8c 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -290,8 +290,6 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
290 290
291static void __init omap_ldp_init_early(void) 291static void __init omap_ldp_init_early(void)
292{ 292{
293 omap_board_config = ldp_config;
294 omap_board_config_size = ARRAY_SIZE(ldp_config);
295 omap2_init_common_infrastructure(); 293 omap2_init_common_infrastructure();
296 omap2_init_common_devices(NULL, NULL); 294 omap2_init_common_devices(NULL, NULL);
297} 295}
@@ -329,6 +327,26 @@ static struct regulator_init_data ldp_vmmc1 = {
329 .consumer_supplies = &ldp_vmmc1_supply, 327 .consumer_supplies = &ldp_vmmc1_supply,
330}; 328};
331 329
330/* ads7846 on SPI */
331static struct regulator_consumer_supply ldp_vaux1_supplies[] = {
332 REGULATOR_SUPPLY("vcc", "spi1.0"),
333};
334
335/* VAUX1 */
336static struct regulator_init_data ldp_vaux1 = {
337 .constraints = {
338 .min_uV = 3000000,
339 .max_uV = 3000000,
340 .apply_uV = true,
341 .valid_modes_mask = REGULATOR_MODE_NORMAL
342 | REGULATOR_MODE_STANDBY,
343 .valid_ops_mask = REGULATOR_CHANGE_MODE
344 | REGULATOR_CHANGE_STATUS,
345 },
346 .num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies),
347 .consumer_supplies = ldp_vaux1_supplies,
348};
349
332static struct twl4030_platform_data ldp_twldata = { 350static struct twl4030_platform_data ldp_twldata = {
333 .irq_base = TWL4030_IRQ_BASE, 351 .irq_base = TWL4030_IRQ_BASE,
334 .irq_end = TWL4030_IRQ_END, 352 .irq_end = TWL4030_IRQ_END,
@@ -337,6 +355,7 @@ static struct twl4030_platform_data ldp_twldata = {
337 .madc = &ldp_madc_data, 355 .madc = &ldp_madc_data,
338 .usb = &ldp_usb_data, 356 .usb = &ldp_usb_data,
339 .vmmc1 = &ldp_vmmc1, 357 .vmmc1 = &ldp_vmmc1,
358 .vaux1 = &ldp_vaux1,
340 .gpio = &ldp_gpio_data, 359 .gpio = &ldp_gpio_data,
341 .keypad = &ldp_kp_twl4030_data, 360 .keypad = &ldp_kp_twl4030_data,
342}; 361};
@@ -422,6 +441,8 @@ static struct mtd_partition ldp_nand_partitions[] = {
422static void __init omap_ldp_init(void) 441static void __init omap_ldp_init(void)
423{ 442{
424 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 443 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
444 omap_board_config = ldp_config;
445 omap_board_config_size = ARRAY_SIZE(ldp_config);
425 ldp_init_smsc911x(); 446 ldp_init_smsc911x();
426 omap_i2c_init(); 447 omap_i2c_init();
427 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); 448 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
@@ -433,7 +454,7 @@ static void __init omap_ldp_init(void)
433 omap_serial_init(); 454 omap_serial_init();
434 usb_musb_init(&musb_board_data); 455 usb_musb_init(&musb_board_data);
435 board_nand_init(ldp_nand_partitions, 456 board_nand_init(ldp_nand_partitions,
436 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); 457 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
437 458
438 omap2_hsmmc_init(mmc); 459 omap2_hsmmc_init(mmc);
439 /* link regulators to MMC adapters */ 460 /* link regulators to MMC adapters */
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index b36cbd21e2d0..e710cd9e079b 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -536,7 +536,7 @@ static void __init n8x0_mmc_init(void)
536 } 536 }
537 537
538 mmc_data[0] = &mmc1_data; 538 mmc_data[0] = &mmc1_data;
539 omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC); 539 omap242x_init_mmc(mmc_data);
540} 540}
541#else 541#else
542 542
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 19bcd004d604..b6752ac5b97e 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -228,14 +228,6 @@ static struct omap_dss_board_info beagle_dss_data = {
228 .default_device = &beagle_dvi_device, 228 .default_device = &beagle_dvi_device,
229}; 229};
230 230
231static struct platform_device beagle_dss_device = {
232 .name = "omapdss",
233 .id = -1,
234 .dev = {
235 .platform_data = &beagle_dss_data,
236 },
237};
238
239static struct regulator_consumer_supply beagle_vdac_supply = 231static struct regulator_consumer_supply beagle_vdac_supply =
240 REGULATOR_SUPPLY("vdda_dac", "omapdss"); 232 REGULATOR_SUPPLY("vdda_dac", "omapdss");
241 233
@@ -435,9 +427,7 @@ static struct twl4030_usb_data beagle_usb_data = {
435 .usb_mode = T2_USB_MODE_ULPI, 427 .usb_mode = T2_USB_MODE_ULPI,
436}; 428};
437 429
438static struct twl4030_codec_audio_data beagle_audio_data = { 430static struct twl4030_codec_audio_data beagle_audio_data;
439 .audio_mclk = 26000000,
440};
441 431
442static struct twl4030_codec_data beagle_codec_data = { 432static struct twl4030_codec_data beagle_codec_data = {
443 .audio_mclk = 26000000, 433 .audio_mclk = 26000000,
@@ -554,7 +544,6 @@ static void __init omap3_beagle_init_irq(void)
554static struct platform_device *omap3_beagle_devices[] __initdata = { 544static struct platform_device *omap3_beagle_devices[] __initdata = {
555 &leds_gpio, 545 &leds_gpio,
556 &keys_gpio, 546 &keys_gpio,
557 &beagle_dss_device,
558}; 547};
559 548
560static void __init omap3beagle_flash_init(void) 549static void __init omap3beagle_flash_init(void)
@@ -621,6 +610,7 @@ static void __init omap3_beagle_init(void)
621 omap3_beagle_i2c_init(); 610 omap3_beagle_i2c_init();
622 platform_add_devices(omap3_beagle_devices, 611 platform_add_devices(omap3_beagle_devices,
623 ARRAY_SIZE(omap3_beagle_devices)); 612 ARRAY_SIZE(omap3_beagle_devices));
613 omap_display_init(&beagle_dss_data);
624 omap_serial_init(); 614 omap_serial_init();
625 615
626 omap_mux_init_gpio(170, OMAP_PIN_INPUT); 616 omap_mux_init_gpio(170, OMAP_PIN_INPUT);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c2a0fca4aa53..b65848c59e1d 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -30,6 +30,8 @@
30#include <linux/usb/otg.h> 30#include <linux/usb/otg.h>
31#include <linux/smsc911x.h> 31#include <linux/smsc911x.h>
32 32
33#include <linux/wl12xx.h>
34#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h> 35#include <linux/regulator/machine.h>
34#include <linux/mmc/host.h> 36#include <linux/mmc/host.h>
35 37
@@ -58,6 +60,13 @@
58#define OMAP3EVM_ETHR_ID_REV 0x50 60#define OMAP3EVM_ETHR_ID_REV 0x50
59#define OMAP3EVM_ETHR_GPIO_IRQ 176 61#define OMAP3EVM_ETHR_GPIO_IRQ 176
60#define OMAP3EVM_SMSC911X_CS 5 62#define OMAP3EVM_SMSC911X_CS 5
63/*
64 * Eth Reset signal
65 * 64 = Generation 1 (<=RevD)
66 * 7 = Generation 2 (>=RevE)
67 */
68#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64
69#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7
61 70
62static u8 omap3_evm_version; 71static u8 omap3_evm_version;
63 72
@@ -124,10 +133,15 @@ static struct platform_device omap3evm_smsc911x_device = {
124 133
125static inline void __init omap3evm_init_smsc911x(void) 134static inline void __init omap3evm_init_smsc911x(void)
126{ 135{
127 int eth_cs; 136 int eth_cs, eth_rst;
128 struct clk *l3ck; 137 struct clk *l3ck;
129 unsigned int rate; 138 unsigned int rate;
130 139
140 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
141 eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST;
142 else
143 eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST;
144
131 eth_cs = OMAP3EVM_SMSC911X_CS; 145 eth_cs = OMAP3EVM_SMSC911X_CS;
132 146
133 l3ck = clk_get(NULL, "l3_ck"); 147 l3ck = clk_get(NULL, "l3_ck");
@@ -136,6 +150,27 @@ static inline void __init omap3evm_init_smsc911x(void)
136 else 150 else
137 rate = clk_get_rate(l3ck); 151 rate = clk_get_rate(l3ck);
138 152
153 /* Configure ethernet controller reset gpio */
154 if (cpu_is_omap3430()) {
155 if (gpio_request(eth_rst, "SMSC911x gpio") < 0) {
156 pr_err(KERN_ERR "Failed to request %d for smsc911x\n",
157 eth_rst);
158 return;
159 }
160
161 if (gpio_direction_output(eth_rst, 1) < 0) {
162 pr_err(KERN_ERR "Failed to set direction of %d for" \
163 " smsc911x\n", eth_rst);
164 return;
165 }
166 /* reset pulse to ethernet controller*/
167 usleep_range(150, 220);
168 gpio_set_value(eth_rst, 0);
169 usleep_range(150, 220);
170 gpio_set_value(eth_rst, 1);
171 usleep_range(1, 2);
172 }
173
139 if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) { 174 if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) {
140 printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", 175 printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
141 OMAP3EVM_ETHR_GPIO_IRQ); 176 OMAP3EVM_ETHR_GPIO_IRQ);
@@ -235,9 +270,9 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
235 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0); 270 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
236 271
237 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) 272 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
238 gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); 273 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
239 else 274 else
240 gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); 275 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
241 276
242 lcd_enabled = 1; 277 lcd_enabled = 1;
243 return 0; 278 return 0;
@@ -248,9 +283,9 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
248 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); 283 gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
249 284
250 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) 285 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
251 gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); 286 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
252 else 287 else
253 gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); 288 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
254 289
255 lcd_enabled = 0; 290 lcd_enabled = 0;
256} 291}
@@ -289,7 +324,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
289 return -EINVAL; 324 return -EINVAL;
290 } 325 }
291 326
292 gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); 327 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
293 328
294 dvi_enabled = 1; 329 dvi_enabled = 1;
295 return 0; 330 return 0;
@@ -297,7 +332,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
297 332
298static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) 333static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
299{ 334{
300 gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); 335 gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
301 336
302 dvi_enabled = 0; 337 dvi_enabled = 0;
303} 338}
@@ -328,14 +363,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
328 .default_device = &omap3_evm_lcd_device, 363 .default_device = &omap3_evm_lcd_device,
329}; 364};
330 365
331static struct platform_device omap3_evm_dss_device = {
332 .name = "omapdss",
333 .id = -1,
334 .dev = {
335 .platform_data = &omap3_evm_dss_data,
336 },
337};
338
339static struct regulator_consumer_supply omap3evm_vmmc1_supply = { 366static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
340 .supply = "vmmc", 367 .supply = "vmmc",
341}; 368};
@@ -381,6 +408,16 @@ static struct omap2_hsmmc_info mmc[] = {
381 .gpio_cd = -EINVAL, 408 .gpio_cd = -EINVAL,
382 .gpio_wp = 63, 409 .gpio_wp = 63,
383 }, 410 },
411#ifdef CONFIG_WL12XX_PLATFORM_DATA
412 {
413 .name = "wl1271",
414 .mmc = 2,
415 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
416 .gpio_wp = -EINVAL,
417 .gpio_cd = -EINVAL,
418 .nonremovable = true,
419 },
420#endif
384 {} /* Terminator */ 421 {} /* Terminator */
385}; 422};
386 423
@@ -411,6 +448,8 @@ static struct platform_device leds_gpio = {
411static int omap3evm_twl_gpio_setup(struct device *dev, 448static int omap3evm_twl_gpio_setup(struct device *dev,
412 unsigned gpio, unsigned ngpio) 449 unsigned gpio, unsigned ngpio)
413{ 450{
451 int r;
452
414 /* gpio + 0 is "mmc0_cd" (input/IRQ) */ 453 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
415 omap_mux_init_gpio(63, OMAP_PIN_INPUT); 454 omap_mux_init_gpio(63, OMAP_PIN_INPUT);
416 mmc[0].gpio_cd = gpio + 0; 455 mmc[0].gpio_cd = gpio + 0;
@@ -426,8 +465,12 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
426 */ 465 */
427 466
428 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ 467 /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
429 gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); 468 r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
430 gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); 469 if (!r)
470 r = gpio_direction_output(gpio + TWL4030_GPIO_MAX,
471 (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0);
472 if (r)
473 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
431 474
432 /* gpio + 7 == DVI Enable */ 475 /* gpio + 7 == DVI Enable */
433 gpio_request(gpio + 7, "EN_DVI"); 476 gpio_request(gpio + 7, "EN_DVI");
@@ -491,19 +534,15 @@ static struct twl4030_madc_platform_data omap3evm_madc_data = {
491 .irq_line = 1, 534 .irq_line = 1,
492}; 535};
493 536
494static struct twl4030_codec_audio_data omap3evm_audio_data = { 537static struct twl4030_codec_audio_data omap3evm_audio_data;
495 .audio_mclk = 26000000,
496};
497 538
498static struct twl4030_codec_data omap3evm_codec_data = { 539static struct twl4030_codec_data omap3evm_codec_data = {
499 .audio_mclk = 26000000, 540 .audio_mclk = 26000000,
500 .audio = &omap3evm_audio_data, 541 .audio = &omap3evm_audio_data,
501}; 542};
502 543
503static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = { 544static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
504 .supply = "vdda_dac", 545 REGULATOR_SUPPLY("vdda_dac", "omapdss");
505 .dev = &omap3_evm_dss_device.dev,
506};
507 546
508/* VDAC for DSS driving S-Video */ 547/* VDAC for DSS driving S-Video */
509static struct regulator_init_data omap3_evm_vdac = { 548static struct regulator_init_data omap3_evm_vdac = {
@@ -538,6 +577,66 @@ static struct regulator_init_data omap3_evm_vpll2 = {
538 .consumer_supplies = &omap3_evm_vpll2_supply, 577 .consumer_supplies = &omap3_evm_vpll2_supply,
539}; 578};
540 579
580/* ads7846 on SPI */
581static struct regulator_consumer_supply omap3evm_vio_supply =
582 REGULATOR_SUPPLY("vcc", "spi1.0");
583
584/* VIO for ads7846 */
585static struct regulator_init_data omap3evm_vio = {
586 .constraints = {
587 .min_uV = 1800000,
588 .max_uV = 1800000,
589 .apply_uV = true,
590 .valid_modes_mask = REGULATOR_MODE_NORMAL
591 | REGULATOR_MODE_STANDBY,
592 .valid_ops_mask = REGULATOR_CHANGE_MODE
593 | REGULATOR_CHANGE_STATUS,
594 },
595 .num_consumer_supplies = 1,
596 .consumer_supplies = &omap3evm_vio_supply,
597};
598
599#ifdef CONFIG_WL12XX_PLATFORM_DATA
600
601#define OMAP3EVM_WLAN_PMENA_GPIO (150)
602#define OMAP3EVM_WLAN_IRQ_GPIO (149)
603
604static struct regulator_consumer_supply omap3evm_vmmc2_supply =
605 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
606
607/* VMMC2 for driving the WL12xx module */
608static struct regulator_init_data omap3evm_vmmc2 = {
609 .constraints = {
610 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
611 },
612 .num_consumer_supplies = 1,
613 .consumer_supplies = &omap3evm_vmmc2_supply,
614};
615
616static struct fixed_voltage_config omap3evm_vwlan = {
617 .supply_name = "vwl1271",
618 .microvolts = 1800000, /* 1.80V */
619 .gpio = OMAP3EVM_WLAN_PMENA_GPIO,
620 .startup_delay = 70000, /* 70ms */
621 .enable_high = 1,
622 .enabled_at_boot = 0,
623 .init_data = &omap3evm_vmmc2,
624};
625
626static struct platform_device omap3evm_wlan_regulator = {
627 .name = "reg-fixed-voltage",
628 .id = 1,
629 .dev = {
630 .platform_data = &omap3evm_vwlan,
631 },
632};
633
634struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
635 .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
636 .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
637};
638#endif
639
541static struct twl4030_platform_data omap3evm_twldata = { 640static struct twl4030_platform_data omap3evm_twldata = {
542 .irq_base = TWL4030_IRQ_BASE, 641 .irq_base = TWL4030_IRQ_BASE,
543 .irq_end = TWL4030_IRQ_END, 642 .irq_end = TWL4030_IRQ_END,
@@ -550,6 +649,7 @@ static struct twl4030_platform_data omap3evm_twldata = {
550 .codec = &omap3evm_codec_data, 649 .codec = &omap3evm_codec_data,
551 .vdac = &omap3_evm_vdac, 650 .vdac = &omap3_evm_vdac,
552 .vpll2 = &omap3_evm_vpll2, 651 .vpll2 = &omap3_evm_vpll2,
652 .vio = &omap3evm_vio,
553}; 653};
554 654
555static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { 655static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
@@ -627,16 +727,10 @@ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
627 727
628static void __init omap3_evm_init_early(void) 728static void __init omap3_evm_init_early(void)
629{ 729{
630 omap_board_config = omap3_evm_config;
631 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
632 omap2_init_common_infrastructure(); 730 omap2_init_common_infrastructure();
633 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); 731 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
634} 732}
635 733
636static struct platform_device *omap3_evm_devices[] __initdata = {
637 &omap3_evm_dss_device,
638};
639
640static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { 734static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
641 735
642 .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, 736 .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
@@ -651,14 +745,76 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
651}; 745};
652 746
653#ifdef CONFIG_OMAP_MUX 747#ifdef CONFIG_OMAP_MUX
654static struct omap_board_mux board_mux[] __initdata = { 748static struct omap_board_mux omap35x_board_mux[] __initdata = {
655 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | 749 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
656 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | 750 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
657 OMAP_PIN_OFF_WAKEUPENABLE), 751 OMAP_PIN_OFF_WAKEUPENABLE),
658 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | 752 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
659 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), 753 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
754 OMAP_PIN_OFF_WAKEUPENABLE),
755 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
756 OMAP_PIN_OFF_NONE),
757 OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
758 OMAP_PIN_OFF_NONE),
759#ifdef CONFIG_WL12XX_PLATFORM_DATA
760 /* WLAN IRQ - GPIO 149 */
761 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
762
763 /* WLAN POWER ENABLE - GPIO 150 */
764 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
765
766 /* MMC2 SDIO pin muxes for WL12xx */
767 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
768 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
769 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
770 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
771 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
772 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
773#endif
660 { .reg_offset = OMAP_MUX_TERMINATOR }, 774 { .reg_offset = OMAP_MUX_TERMINATOR },
661}; 775};
776
777static struct omap_board_mux omap36x_board_mux[] __initdata = {
778 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
779 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
780 OMAP_PIN_OFF_WAKEUPENABLE),
781 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
782 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
783 OMAP_PIN_OFF_WAKEUPENABLE),
784 /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
785 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
786 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
787 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
788 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
789 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
790 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
791 OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
792 OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
793 OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
794 OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
795 OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
796 OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
797#ifdef CONFIG_WL12XX_PLATFORM_DATA
798 /* WLAN IRQ - GPIO 149 */
799 OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
800
801 /* WLAN POWER ENABLE - GPIO 150 */
802 OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
803
804 /* MMC2 SDIO pin muxes for WL12xx */
805 OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
806 OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
807 OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
808 OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
809 OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
810 OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
811#endif
812
813 { .reg_offset = OMAP_MUX_TERMINATOR },
814};
815#else
816#define omap35x_board_mux NULL
817#define omap36x_board_mux NULL
662#endif 818#endif
663 819
664static struct omap_musb_board_data musb_board_data = { 820static struct omap_musb_board_data musb_board_data = {
@@ -670,11 +826,18 @@ static struct omap_musb_board_data musb_board_data = {
670static void __init omap3_evm_init(void) 826static void __init omap3_evm_init(void)
671{ 827{
672 omap3_evm_get_revision(); 828 omap3_evm_get_revision();
673 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 829
830 if (cpu_is_omap3630())
831 omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
832 else
833 omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
834
835 omap_board_config = omap3_evm_config;
836 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
674 837
675 omap3_evm_i2c_init(); 838 omap3_evm_i2c_init();
676 839
677 platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices)); 840 omap_display_init(&omap3_evm_dss_data);
678 841
679 spi_register_board_info(omap3evm_spi_board_info, 842 spi_register_board_info(omap3evm_spi_board_info,
680 ARRAY_SIZE(omap3evm_spi_board_info)); 843 ARRAY_SIZE(omap3evm_spi_board_info));
@@ -714,6 +877,13 @@ static void __init omap3_evm_init(void)
714 ads7846_dev_init(); 877 ads7846_dev_init();
715 omap3evm_init_smsc911x(); 878 omap3evm_init_smsc911x();
716 omap3_evm_display_init(); 879 omap3_evm_display_init();
880
881#ifdef CONFIG_WL12XX_PLATFORM_DATA
882 /* WL12xx WLAN Init */
883 if (wl12xx_set_platform_data(&omap3evm_wlan_data))
884 pr_err("error setting wl12xx data\n");
885 platform_device_register(&omap3evm_wlan_regulator);
886#endif
717} 887}
718 888
719MACHINE_START(OMAP3EVM, "OMAP3 EVM") 889MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index b91f74ce3a9f..5386a8190ea1 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -253,14 +253,6 @@ static struct omap_dss_board_info pandora_dss_data = {
253 .default_device = &pandora_lcd_device, 253 .default_device = &pandora_lcd_device,
254}; 254};
255 255
256static struct platform_device pandora_dss_device = {
257 .name = "omapdss",
258 .id = -1,
259 .dev = {
260 .platform_data = &pandora_dss_data,
261 },
262};
263
264static void pandora_wl1251_init_card(struct mmc_card *card) 256static void pandora_wl1251_init_card(struct mmc_card *card)
265{ 257{
266 /* 258 /*
@@ -341,13 +333,13 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
341}; 333};
342 334
343static struct regulator_consumer_supply pandora_vmmc1_supply = 335static struct regulator_consumer_supply pandora_vmmc1_supply =
344 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 336 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
345 337
346static struct regulator_consumer_supply pandora_vmmc2_supply = 338static struct regulator_consumer_supply pandora_vmmc2_supply =
347 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 339 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
348 340
349static struct regulator_consumer_supply pandora_vmmc3_supply = 341static struct regulator_consumer_supply pandora_vmmc3_supply =
350 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2"); 342 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
351 343
352static struct regulator_consumer_supply pandora_vdda_dac_supply = 344static struct regulator_consumer_supply pandora_vdda_dac_supply =
353 REGULATOR_SUPPLY("vdda_dac", "omapdss"); 345 REGULATOR_SUPPLY("vdda_dac", "omapdss");
@@ -524,9 +516,7 @@ static struct twl4030_usb_data omap3pandora_usb_data = {
524 .usb_mode = T2_USB_MODE_ULPI, 516 .usb_mode = T2_USB_MODE_ULPI,
525}; 517};
526 518
527static struct twl4030_codec_audio_data omap3pandora_audio_data = { 519static struct twl4030_codec_audio_data omap3pandora_audio_data;
528 .audio_mclk = 26000000,
529};
530 520
531static struct twl4030_codec_data omap3pandora_codec_data = { 521static struct twl4030_codec_data omap3pandora_codec_data = {
532 .audio_mclk = 26000000, 522 .audio_mclk = 26000000,
@@ -676,7 +666,6 @@ fail:
676static struct platform_device *omap3pandora_devices[] __initdata = { 666static struct platform_device *omap3pandora_devices[] __initdata = {
677 &pandora_leds_gpio, 667 &pandora_leds_gpio,
678 &pandora_keys_gpio, 668 &pandora_keys_gpio,
679 &pandora_dss_device,
680 &pandora_vwlan_device, 669 &pandora_vwlan_device,
681}; 670};
682 671
@@ -711,6 +700,7 @@ static void __init omap3pandora_init(void)
711 pandora_wl1251_init(); 700 pandora_wl1251_init();
712 platform_add_devices(omap3pandora_devices, 701 platform_add_devices(omap3pandora_devices,
713 ARRAY_SIZE(omap3pandora_devices)); 702 ARRAY_SIZE(omap3pandora_devices));
703 omap_display_init(&pandora_dss_data);
714 omap_serial_init(); 704 omap_serial_init();
715 spi_register_board_info(omap3pandora_spi_board_info, 705 spi_register_board_info(omap3pandora_spi_board_info,
716 ARRAY_SIZE(omap3pandora_spi_board_info)); 706 ARRAY_SIZE(omap3pandora_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 5d1ccef69164..15ede8b49815 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -240,14 +240,6 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
240 .default_device = &omap3_stalker_dvi_device, 240 .default_device = &omap3_stalker_dvi_device,
241}; 241};
242 242
243static struct platform_device omap3_stalker_dss_device = {
244 .name = "omapdss",
245 .id = -1,
246 .dev = {
247 .platform_data = &omap3_stalker_dss_data,
248 },
249};
250
251static struct regulator_consumer_supply omap3stalker_vmmc1_supply = { 243static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
252 .supply = "vmmc", 244 .supply = "vmmc",
253}; 245};
@@ -439,19 +431,15 @@ static struct twl4030_madc_platform_data omap3stalker_madc_data = {
439 .irq_line = 1, 431 .irq_line = 1,
440}; 432};
441 433
442static struct twl4030_codec_audio_data omap3stalker_audio_data = { 434static struct twl4030_codec_audio_data omap3stalker_audio_data;
443 .audio_mclk = 26000000,
444};
445 435
446static struct twl4030_codec_data omap3stalker_codec_data = { 436static struct twl4030_codec_data omap3stalker_codec_data = {
447 .audio_mclk = 26000000, 437 .audio_mclk = 26000000,
448 .audio = &omap3stalker_audio_data, 438 .audio = &omap3stalker_audio_data,
449}; 439};
450 440
451static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = { 441static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
452 .supply = "vdda_dac", 442 REGULATOR_SUPPLY("vdda_dac", "omapdss");
453 .dev = &omap3_stalker_dss_device.dev,
454};
455 443
456/* VDAC for DSS driving S-Video */ 444/* VDAC for DSS driving S-Video */
457static struct regulator_init_data omap3_stalker_vdac = { 445static struct regulator_init_data omap3_stalker_vdac = {
@@ -469,10 +457,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
469}; 457};
470 458
471/* VPLL2 for digital video outputs */ 459/* VPLL2 for digital video outputs */
472static struct regulator_consumer_supply omap3_stalker_vpll2_supply = { 460static struct regulator_consumer_supply omap3_stalker_vpll2_supply =
473 .supply = "vdds_dsi", 461 REGULATOR_SUPPLY("vdds_dsi", "omapdss");
474 .dev = &omap3_stalker_lcd_device.dev,
475};
476 462
477static struct regulator_init_data omap3_stalker_vpll2 = { 463static struct regulator_init_data omap3_stalker_vpll2 = {
478 .constraints = { 464 .constraints = {
@@ -593,8 +579,6 @@ static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
593 579
594static void __init omap3_stalker_init_early(void) 580static void __init omap3_stalker_init_early(void)
595{ 581{
596 omap_board_config = omap3_stalker_config;
597 omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
598 omap2_init_common_infrastructure(); 582 omap2_init_common_infrastructure();
599 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); 583 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
600} 584}
@@ -608,7 +592,6 @@ static void __init omap3_stalker_init_irq(void)
608} 592}
609 593
610static struct platform_device *omap3_stalker_devices[] __initdata = { 594static struct platform_device *omap3_stalker_devices[] __initdata = {
611 &omap3_stalker_dss_device,
612 &keys_gpio, 595 &keys_gpio,
613}; 596};
614 597
@@ -642,12 +625,15 @@ static struct omap_musb_board_data musb_board_data = {
642static void __init omap3_stalker_init(void) 625static void __init omap3_stalker_init(void)
643{ 626{
644 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); 627 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
628 omap_board_config = omap3_stalker_config;
629 omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
645 630
646 omap3_stalker_i2c_init(); 631 omap3_stalker_i2c_init();
647 632
648 platform_add_devices(omap3_stalker_devices, 633 platform_add_devices(omap3_stalker_devices,
649 ARRAY_SIZE(omap3_stalker_devices)); 634 ARRAY_SIZE(omap3_stalker_devices));
650 635
636 omap_display_init(&omap3_stalker_dss_data);
651 spi_register_board_info(omap3stalker_spi_board_info, 637 spi_register_board_info(omap3stalker_spi_board_info,
652 ARRAY_SIZE(omap3stalker_spi_board_info)); 638 ARRAY_SIZE(omap3stalker_spi_board_info));
653 639
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 6a60f79dcccb..5554f5814aa4 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -252,9 +252,7 @@ static struct twl4030_usb_data touchbook_usb_data = {
252 .usb_mode = T2_USB_MODE_ULPI, 252 .usb_mode = T2_USB_MODE_ULPI,
253}; 253};
254 254
255static struct twl4030_codec_audio_data touchbook_audio_data = { 255static struct twl4030_codec_audio_data touchbook_audio_data;
256 .audio_mclk = 26000000,
257};
258 256
259static struct twl4030_codec_data touchbook_codec_data = { 257static struct twl4030_codec_data touchbook_codec_data = {
260 .audio_mclk = 26000000, 258 .audio_mclk = 26000000,
@@ -417,9 +415,6 @@ static struct omap_board_mux board_mux[] __initdata = {
417 415
418static void __init omap3_touchbook_init_early(void) 416static void __init omap3_touchbook_init_early(void)
419{ 417{
420 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
421 omap_board_config = omap3_touchbook_config;
422 omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
423 omap2_init_common_infrastructure(); 418 omap2_init_common_infrastructure();
424 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, 419 omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
425 mt46h32m32lf6_sdrc_params); 420 mt46h32m32lf6_sdrc_params);
@@ -514,6 +509,10 @@ static struct omap_musb_board_data musb_board_data = {
514 509
515static void __init omap3_touchbook_init(void) 510static void __init omap3_touchbook_init(void)
516{ 511{
512 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
513 omap_board_config = omap3_touchbook_config;
514 omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
515
517 pm_power_off = omap3_touchbook_poweroff; 516 pm_power_off = omap3_touchbook_poweroff;
518 517
519 omap3_touchbook_i2c_init(); 518 omap3_touchbook_i2c_init();
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index fca5b9e80c18..a94ce07be72f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -26,6 +26,8 @@
26#include <linux/usb/otg.h> 26#include <linux/usb/otg.h>
27#include <linux/i2c/twl.h> 27#include <linux/i2c/twl.h>
28#include <linux/regulator/machine.h> 28#include <linux/regulator/machine.h>
29#include <linux/regulator/fixed.h>
30#include <linux/wl12xx.h>
29 31
30#include <mach/hardware.h> 32#include <mach/hardware.h>
31#include <mach/omap4-common.h> 33#include <mach/omap4-common.h>
@@ -45,6 +47,18 @@
45 47
46#define GPIO_HUB_POWER 1 48#define GPIO_HUB_POWER 1
47#define GPIO_HUB_NRESET 62 49#define GPIO_HUB_NRESET 62
50#define GPIO_WIFI_PMENA 43
51#define GPIO_WIFI_IRQ 53
52
53/* wl127x BT, FM, GPS connectivity chip */
54static int wl1271_gpios[] = {46, -1, -1};
55static struct platform_device wl1271_device = {
56 .name = "kim",
57 .id = -1,
58 .dev = {
59 .platform_data = &wl1271_gpios,
60 },
61};
48 62
49static struct gpio_led gpio_leds[] = { 63static struct gpio_led gpio_leds[] = {
50 { 64 {
@@ -74,6 +88,7 @@ static struct platform_device leds_gpio = {
74 88
75static struct platform_device *panda_devices[] __initdata = { 89static struct platform_device *panda_devices[] __initdata = {
76 &leds_gpio, 90 &leds_gpio,
91 &wl1271_device,
77}; 92};
78 93
79static void __init omap4_panda_init_early(void) 94static void __init omap4_panda_init_early(void)
@@ -161,16 +176,62 @@ static struct omap2_hsmmc_info mmc[] = {
161 .gpio_wp = -EINVAL, 176 .gpio_wp = -EINVAL,
162 .gpio_cd = -EINVAL, 177 .gpio_cd = -EINVAL,
163 }, 178 },
179 {
180 .name = "wl1271",
181 .mmc = 5,
182 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
183 .gpio_wp = -EINVAL,
184 .gpio_cd = -EINVAL,
185 .ocr_mask = MMC_VDD_165_195,
186 .nonremovable = true,
187 },
164 {} /* Terminator */ 188 {} /* Terminator */
165}; 189};
166 190
167static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { 191static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
168 { 192 {
169 .supply = "vmmc", 193 .supply = "vmmc",
170 .dev_name = "mmci-omap-hs.0", 194 .dev_name = "omap_hsmmc.0",
195 },
196};
197
198static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
199 .supply = "vmmc",
200 .dev_name = "omap_hsmmc.4",
201};
202
203static struct regulator_init_data panda_vmmc5 = {
204 .constraints = {
205 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
206 },
207 .num_consumer_supplies = 1,
208 .consumer_supplies = &omap4_panda_vmmc5_supply,
209};
210
211static struct fixed_voltage_config panda_vwlan = {
212 .supply_name = "vwl1271",
213 .microvolts = 1800000, /* 1.8V */
214 .gpio = GPIO_WIFI_PMENA,
215 .startup_delay = 70000, /* 70msec */
216 .enable_high = 1,
217 .enabled_at_boot = 0,
218 .init_data = &panda_vmmc5,
219};
220
221static struct platform_device omap_vwlan_device = {
222 .name = "reg-fixed-voltage",
223 .id = 1,
224 .dev = {
225 .platform_data = &panda_vwlan,
171 }, 226 },
172}; 227};
173 228
229struct wl12xx_platform_data omap_panda_wlan_data __initdata = {
230 .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
231 /* PANDA ref clock is 38.4 MHz */
232 .board_ref_clock = 2,
233};
234
174static int omap4_twl6030_hsmmc_late_init(struct device *dev) 235static int omap4_twl6030_hsmmc_late_init(struct device *dev)
175{ 236{
176 int ret = 0; 237 int ret = 0;
@@ -304,7 +365,6 @@ static struct regulator_init_data omap4_panda_vana = {
304 .constraints = { 365 .constraints = {
305 .min_uV = 2100000, 366 .min_uV = 2100000,
306 .max_uV = 2100000, 367 .max_uV = 2100000,
307 .apply_uV = true,
308 .valid_modes_mask = REGULATOR_MODE_NORMAL 368 .valid_modes_mask = REGULATOR_MODE_NORMAL
309 | REGULATOR_MODE_STANDBY, 369 | REGULATOR_MODE_STANDBY,
310 .valid_ops_mask = REGULATOR_CHANGE_MODE 370 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -316,7 +376,6 @@ static struct regulator_init_data omap4_panda_vcxio = {
316 .constraints = { 376 .constraints = {
317 .min_uV = 1800000, 377 .min_uV = 1800000,
318 .max_uV = 1800000, 378 .max_uV = 1800000,
319 .apply_uV = true,
320 .valid_modes_mask = REGULATOR_MODE_NORMAL 379 .valid_modes_mask = REGULATOR_MODE_NORMAL
321 | REGULATOR_MODE_STANDBY, 380 | REGULATOR_MODE_STANDBY,
322 .valid_ops_mask = REGULATOR_CHANGE_MODE 381 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -328,7 +387,6 @@ static struct regulator_init_data omap4_panda_vdac = {
328 .constraints = { 387 .constraints = {
329 .min_uV = 1800000, 388 .min_uV = 1800000,
330 .max_uV = 1800000, 389 .max_uV = 1800000,
331 .apply_uV = true,
332 .valid_modes_mask = REGULATOR_MODE_NORMAL 390 .valid_modes_mask = REGULATOR_MODE_NORMAL
333 | REGULATOR_MODE_STANDBY, 391 | REGULATOR_MODE_STANDBY,
334 .valid_ops_mask = REGULATOR_CHANGE_MODE 392 .valid_ops_mask = REGULATOR_CHANGE_MODE
@@ -390,6 +448,19 @@ static int __init omap4_panda_i2c_init(void)
390 448
391#ifdef CONFIG_OMAP_MUX 449#ifdef CONFIG_OMAP_MUX
392static struct omap_board_mux board_mux[] __initdata = { 450static struct omap_board_mux board_mux[] __initdata = {
451 /* WLAN IRQ - GPIO 53 */
452 OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
453 /* WLAN POWER ENABLE - GPIO 43 */
454 OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
455 /* WLAN SDIO: MMC5 CMD */
456 OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
457 /* WLAN SDIO: MMC5 CLK */
458 OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
459 /* WLAN SDIO: MMC5 DAT[0-3] */
460 OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
461 OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
462 OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
463 OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
393 { .reg_offset = OMAP_MUX_TERMINATOR }, 464 { .reg_offset = OMAP_MUX_TERMINATOR },
394}; 465};
395#else 466#else
@@ -404,8 +475,12 @@ static void __init omap4_panda_init(void)
404 package = OMAP_PACKAGE_CBL; 475 package = OMAP_PACKAGE_CBL;
405 omap4_mux_init(board_mux, package); 476 omap4_mux_init(board_mux, package);
406 477
478 if (wl12xx_set_platform_data(&omap_panda_wlan_data))
479 pr_err("error setting wl12xx data\n");
480
407 omap4_panda_i2c_init(); 481 omap4_panda_i2c_init();
408 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); 482 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
483 platform_device_register(&omap_vwlan_device);
409 omap_serial_init(); 484 omap_serial_init();
410 omap4_twl6030_hsmmc_init(mmc); 485 omap4_twl6030_hsmmc_init(mmc);
411 omap4_ehci_init(); 486 omap4_ehci_init();
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index a33ec0edec13..60f8db31763c 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -358,9 +358,7 @@ static struct regulator_init_data overo_vmmc1 = {
358 .consumer_supplies = &overo_vmmc1_supply, 358 .consumer_supplies = &overo_vmmc1_supply,
359}; 359};
360 360
361static struct twl4030_codec_audio_data overo_audio_data = { 361static struct twl4030_codec_audio_data overo_audio_data;
362 .audio_mclk = 26000000,
363};
364 362
365static struct twl4030_codec_data overo_codec_data = { 363static struct twl4030_codec_data overo_codec_data = {
366 .audio_mclk = 26000000, 364 .audio_mclk = 26000000,
@@ -411,8 +409,6 @@ static struct omap_board_config_kernel overo_config[] __initdata = {
411 409
412static void __init overo_init_early(void) 410static void __init overo_init_early(void)
413{ 411{
414 omap_board_config = overo_config;
415 omap_board_config_size = ARRAY_SIZE(overo_config);
416 omap2_init_common_infrastructure(); 412 omap2_init_common_infrastructure();
417 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, 413 omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
418 mt46h32m32lf6_sdrc_params); 414 mt46h32m32lf6_sdrc_params);
@@ -448,6 +444,8 @@ static struct omap_musb_board_data musb_board_data = {
448static void __init overo_init(void) 444static void __init overo_init(void)
449{ 445{
450 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 446 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
447 omap_board_config = overo_config;
448 omap_board_config_size = ARRAY_SIZE(overo_config);
451 overo_i2c_init(); 449 overo_i2c_init();
452 platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); 450 platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
453 omap_serial_init(); 451 omap_serial_init();
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index bdebcb7328e6..2af8b05e786d 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -33,7 +33,7 @@
33#include "sdram-nokia.h" 33#include "sdram-nokia.h"
34 34
35static struct regulator_consumer_supply rm680_vemmc_consumers[] = { 35static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
36 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), 36 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
37}; 37};
38 38
39/* Fixed regulator for internal eMMC */ 39/* Fixed regulator for internal eMMC */
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index e75e240cad67..5f1900c532ec 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -36,6 +36,8 @@
36 36
37#include <sound/tlv320aic3x.h> 37#include <sound/tlv320aic3x.h>
38#include <sound/tpa6130a2-plat.h> 38#include <sound/tpa6130a2-plat.h>
39#include <media/radio-si4713.h>
40#include <media/si4713.h>
39 41
40#include <../drivers/staging/iio/light/tsl2563.h> 42#include <../drivers/staging/iio/light/tsl2563.h>
41 43
@@ -47,6 +49,8 @@
47 49
48#define RX51_WL1251_POWER_GPIO 87 50#define RX51_WL1251_POWER_GPIO 87
49#define RX51_WL1251_IRQ_GPIO 42 51#define RX51_WL1251_IRQ_GPIO 42
52#define RX51_FMTX_RESET_GPIO 163
53#define RX51_FMTX_IRQ 53
50 54
51/* list all spi devices here */ 55/* list all spi devices here */
52enum { 56enum {
@@ -331,13 +335,13 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
331}; 335};
332 336
333static struct regulator_consumer_supply rx51_vmmc1_supply = 337static struct regulator_consumer_supply rx51_vmmc1_supply =
334 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 338 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
335 339
336static struct regulator_consumer_supply rx51_vaux3_supply = 340static struct regulator_consumer_supply rx51_vaux3_supply =
337 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 341 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
338 342
339static struct regulator_consumer_supply rx51_vsim_supply = 343static struct regulator_consumer_supply rx51_vsim_supply =
340 REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); 344 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
341 345
342static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { 346static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
343 /* tlv320aic3x analog supplies */ 347 /* tlv320aic3x analog supplies */
@@ -348,7 +352,7 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
348 /* tpa6130a2 */ 352 /* tpa6130a2 */
349 REGULATOR_SUPPLY("Vdd", "2-0060"), 353 REGULATOR_SUPPLY("Vdd", "2-0060"),
350 /* Keep vmmc as last item. It is not iterated for newer boards */ 354 /* Keep vmmc as last item. It is not iterated for newer boards */
351 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), 355 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
352}; 356};
353 357
354static struct regulator_consumer_supply rx51_vio_supplies[] = { 358static struct regulator_consumer_supply rx51_vio_supplies[] = {
@@ -357,10 +361,14 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
357 REGULATOR_SUPPLY("DVDD", "2-0018"), 361 REGULATOR_SUPPLY("DVDD", "2-0018"),
358 REGULATOR_SUPPLY("IOVDD", "2-0019"), 362 REGULATOR_SUPPLY("IOVDD", "2-0019"),
359 REGULATOR_SUPPLY("DVDD", "2-0019"), 363 REGULATOR_SUPPLY("DVDD", "2-0019"),
364 /* Si4713 IO supply */
365 REGULATOR_SUPPLY("vio", "2-0063"),
360}; 366};
361 367
362static struct regulator_consumer_supply rx51_vaux1_consumers[] = { 368static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
363 REGULATOR_SUPPLY("vdds_sdi", "omapdss"), 369 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
370 /* Si4713 supply */
371 REGULATOR_SUPPLY("vdd", "2-0063"),
364}; 372};
365 373
366static struct regulator_consumer_supply rx51_vdac_supply[] = { 374static struct regulator_consumer_supply rx51_vdac_supply[] = {
@@ -511,6 +519,41 @@ static struct regulator_init_data rx51_vio = {
511 .consumer_supplies = rx51_vio_supplies, 519 .consumer_supplies = rx51_vio_supplies,
512}; 520};
513 521
522static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
523 .gpio_reset = RX51_FMTX_RESET_GPIO,
524};
525
526static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
527 I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
528 .platform_data = &rx51_si4713_i2c_data,
529};
530
531static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
532 .i2c_bus = 2,
533 .subdev_board_info = &rx51_si4713_board_info,
534};
535
536static struct platform_device rx51_si4713_dev __initdata_or_module = {
537 .name = "radio-si4713",
538 .id = -1,
539 .dev = {
540 .platform_data = &rx51_si4713_data,
541 },
542};
543
544static __init void rx51_init_si4713(void)
545{
546 int err;
547
548 err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
549 if (err) {
550 printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
551 return;
552 }
553 rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
554 platform_device_register(&rx51_si4713_dev);
555}
556
514static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) 557static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
515{ 558{
516 /* FIXME this gpio setup is just a placeholder for now */ 559 /* FIXME this gpio setup is just a placeholder for now */
@@ -699,6 +742,14 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
699 .resource_config = twl4030_rconfig, 742 .resource_config = twl4030_rconfig,
700}; 743};
701 744
745struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
746 .coexist = 0,
747};
748
749struct twl4030_codec_data rx51_codec_data __initdata = {
750 .audio_mclk = 26000000,
751 .vibra = &rx51_vibra_data,
752};
702 753
703static struct twl4030_platform_data rx51_twldata __initdata = { 754static struct twl4030_platform_data rx51_twldata __initdata = {
704 .irq_base = TWL4030_IRQ_BASE, 755 .irq_base = TWL4030_IRQ_BASE,
@@ -710,6 +761,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
710 .madc = &rx51_madc_data, 761 .madc = &rx51_madc_data,
711 .usb = &rx51_usb_data, 762 .usb = &rx51_usb_data,
712 .power = &rx51_t2scripts_data, 763 .power = &rx51_t2scripts_data,
764 .codec = &rx51_codec_data,
713 765
714 .vaux1 = &rx51_vaux1, 766 .vaux1 = &rx51_vaux1,
715 .vaux2 = &rx51_vaux2, 767 .vaux2 = &rx51_vaux2,
@@ -921,6 +973,7 @@ void __init rx51_peripherals_init(void)
921 board_smc91x_init(); 973 board_smc91x_init();
922 rx51_add_gpio_keys(); 974 rx51_add_gpio_keys();
923 rx51_init_wl1251(); 975 rx51_init_wl1251();
976 rx51_init_si4713();
924 spi_register_board_info(rx51_peripherals_spi_board_info, 977 spi_register_board_info(rx51_peripherals_spi_board_info,
925 ARRAY_SIZE(rx51_peripherals_spi_board_info)); 978 ARRAY_SIZE(rx51_peripherals_spi_board_info));
926 979
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index acd670054d9a..89a66db8b77d 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -66,18 +66,6 @@ static struct omap_dss_board_info rx51_dss_board_info = {
66 .default_device = &rx51_lcd_device, 66 .default_device = &rx51_lcd_device,
67}; 67};
68 68
69struct platform_device rx51_display_device = {
70 .name = "omapdss",
71 .id = -1,
72 .dev = {
73 .platform_data = &rx51_dss_board_info,
74 },
75};
76
77static struct platform_device *rx51_video_devices[] __initdata = {
78 &rx51_display_device,
79};
80
81static int __init rx51_video_init(void) 69static int __init rx51_video_init(void)
82{ 70{
83 if (!machine_is_nokia_rx51()) 71 if (!machine_is_nokia_rx51())
@@ -95,8 +83,7 @@ static int __init rx51_video_init(void)
95 83
96 gpio_direction_output(RX51_LCD_RESET_GPIO, 1); 84 gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
97 85
98 platform_add_devices(rx51_video_devices, 86 omap_display_init(&rx51_dss_board_info);
99 ARRAY_SIZE(rx51_video_devices));
100 return 0; 87 return 0;
101} 88}
102 89
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 3cf72fe6d75b..e964895b80e8 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -102,9 +102,6 @@ static void __init rx51_init_early(void)
102{ 102{
103 struct omap_sdrc_params *sdrc_params; 103 struct omap_sdrc_params *sdrc_params;
104 104
105 omap_board_config = rx51_config;
106 omap_board_config_size = ARRAY_SIZE(rx51_config);
107 omap3_pm_init_cpuidle(rx51_cpuidle_params);
108 omap2_init_common_infrastructure(); 105 omap2_init_common_infrastructure();
109 sdrc_params = nokia_get_sdram_timings(); 106 sdrc_params = nokia_get_sdram_timings();
110 omap2_init_common_devices(sdrc_params, sdrc_params); 107 omap2_init_common_devices(sdrc_params, sdrc_params);
@@ -127,6 +124,9 @@ static struct omap_musb_board_data musb_board_data = {
127static void __init rx51_init(void) 124static void __init rx51_init(void)
128{ 125{
129 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 126 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
127 omap_board_config = rx51_config;
128 omap_board_config_size = ARRAY_SIZE(rx51_config);
129 omap3_pm_init_cpuidle(rx51_cpuidle_params);
130 omap_serial_init(); 130 omap_serial_init();
131 usb_musb_init(&musb_board_data); 131 usb_musb_init(&musb_board_data);
132 rx51_peripherals_init(); 132 rx51_peripherals_init();
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index f2b097190e07..09fa7bfff8d6 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -29,8 +29,6 @@ static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
29 29
30static void __init ti8168_init_early(void) 30static void __init ti8168_init_early(void)
31{ 31{
32 omap_board_config = ti8168_evm_config;
33 omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
34 omap2_init_common_infrastructure(); 32 omap2_init_common_infrastructure();
35 omap2_init_common_devices(NULL, NULL); 33 omap2_init_common_devices(NULL, NULL);
36} 34}
@@ -43,6 +41,8 @@ static void __init ti8168_evm_init_irq(void)
43static void __init ti8168_evm_init(void) 41static void __init ti8168_evm_init(void)
44{ 42{
45 omap_serial_init(); 43 omap_serial_init();
44 omap_board_config = ti8168_evm_config;
45 omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
46} 46}
47 47
48static void __init ti8168_evm_map_io(void) 48static void __init ti8168_evm_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 6bcd43657aed..37b84c2b850f 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -130,14 +130,6 @@ static struct omap_dss_board_info zoom_dss_data = {
130 .default_device = &zoom_lcd_device, 130 .default_device = &zoom_lcd_device,
131}; 131};
132 132
133static struct platform_device zoom_dss_device = {
134 .name = "omapdss",
135 .id = -1,
136 .dev = {
137 .platform_data = &zoom_dss_data,
138 },
139};
140
141static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { 133static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
142 .turbo_mode = 1, 134 .turbo_mode = 1,
143 .single_channel = 1, /* 0: slave, 1: master */ 135 .single_channel = 1, /* 0: slave, 1: master */
@@ -153,14 +145,9 @@ static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
153 }, 145 },
154}; 146};
155 147
156static struct platform_device *zoom_display_devices[] __initdata = {
157 &zoom_dss_device,
158};
159
160void __init zoom_display_init(void) 148void __init zoom_display_init(void)
161{ 149{
162 platform_add_devices(zoom_display_devices, 150 omap_display_init(&zoom_dss_data);
163 ARRAY_SIZE(zoom_display_devices));
164 spi_register_board_info(nec_8048_spi_board_info, 151 spi_register_board_info(nec_8048_spi_board_info,
165 ARRAY_SIZE(nec_8048_spi_board_info)); 152 ARRAY_SIZE(nec_8048_spi_board_info));
166 zoom_lcd_panel_init(); 153 zoom_lcd_panel_init();
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index e0e040f34c68..448ab60195d5 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -118,7 +118,7 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = {
118 118
119static struct regulator_consumer_supply zoom_vmmc3_supply = { 119static struct regulator_consumer_supply zoom_vmmc3_supply = {
120 .supply = "vmmc", 120 .supply = "vmmc",
121 .dev_name = "mmci-omap-hs.2", 121 .dev_name = "omap_hsmmc.2",
122}; 122};
123 123
124/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 124/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@@ -322,9 +322,7 @@ static struct twl4030_madc_platform_data zoom_madc_data = {
322 .irq_line = 1, 322 .irq_line = 1,
323}; 323};
324 324
325static struct twl4030_codec_audio_data zoom_audio_data = { 325static struct twl4030_codec_audio_data zoom_audio_data;
326 .audio_mclk = 26000000,
327};
328 326
329static struct twl4030_codec_data zoom_codec_data = { 327static struct twl4030_codec_data zoom_codec_data = {
330 .audio_mclk = 26000000, 328 .audio_mclk = 26000000,
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 85d4170f30ab..7e3f1595d77b 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -16,6 +16,7 @@
16#include <linux/input.h> 16#include <linux/input.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/i2c/twl.h> 18#include <linux/i2c/twl.h>
19#include <linux/mtd/nand.h>
19 20
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
@@ -124,8 +125,8 @@ static void __init omap_zoom_init(void)
124 usb_ehci_init(&ehci_pdata); 125 usb_ehci_init(&ehci_pdata);
125 } 126 }
126 127
127 board_nand_init(zoom_nand_partitions, 128 board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
128 ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); 129 ZOOM_NAND_CS, NAND_BUSWIDTH_16);
129 zoom_debugboard_init(); 130 zoom_debugboard_init();
130 zoom_peripherals_init(); 131 zoom_peripherals_init();
131 zoom_display_init(); 132 zoom_display_init();
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index a781cd6795a4..e25364de028a 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
97 u32 *field_val) 97 u32 *field_val)
98{ 98{
99 const struct clksel *clks; 99 const struct clksel *clks;
100 const struct clksel_rate *clkr, *max_clkr; 100 const struct clksel_rate *clkr, *max_clkr = NULL;
101 u8 max_div = 0; 101 u8 max_div = 0;
102 102
103 clks = _get_clksel_by_parent(clk, src_clk); 103 clks = _get_clksel_by_parent(clk, src_clk);
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 17735e7f47b1..bcffee001bfa 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -77,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
77 dd = clk->dpll_data; 77 dd = clk->dpll_data;
78 78
79 /* DPLL divider must result in a valid jitter correction val */ 79 /* DPLL divider must result in a valid jitter correction val */
80 fint = clk->parent->rate / (n + 1); 80 fint = clk->parent->rate / n;
81 if (fint < DPLL_FINT_BAND1_MIN) { 81 if (fint < DPLL_FINT_BAND1_MIN) {
82 82
83 pr_debug("rejecting n=%d due to Fint failure, " 83 pr_debug("rejecting n=%d due to Fint failure, "
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 5c2a075fd82c..bba018331a71 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1989,15 +1989,15 @@ static struct omap_clk omap2430_clks[] = {
1989 CLK(NULL, "pka_ick", &pka_ick, CK_243X), 1989 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1990 CLK(NULL, "usb_fck", &usb_fck, CK_243X), 1990 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1991 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), 1991 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
1992 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), 1992 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
1993 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), 1993 CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X),
1994 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), 1994 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
1995 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), 1995 CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X),
1996 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), 1996 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1997 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), 1997 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), 1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
1999 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), 1999 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2000 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), 2000 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2001}; 2001};
2002 2002
2003/* 2003/*
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index cc5c8d422c5b..cb6df8ca9e4a 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -23,13 +23,13 @@ void omap2xxx_clk_prepare_for_reboot(void);
23#ifdef CONFIG_SOC_OMAP2420 23#ifdef CONFIG_SOC_OMAP2420
24int omap2420_clk_init(void); 24int omap2420_clk_init(void);
25#else 25#else
26#define omap2420_clk_init() 0 26#define omap2420_clk_init() do { } while(0)
27#endif 27#endif
28 28
29#ifdef CONFIG_SOC_OMAP2430 29#ifdef CONFIG_SOC_OMAP2430
30int omap2430_clk_init(void); 30int omap2430_clk_init(void);
31#else 31#else
32#define omap2430_clk_init() 0 32#define omap2430_clk_init() do { } while(0)
33#endif 33#endif
34 34
35extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; 35extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 3dbeb3a5813d..d905ecc7989a 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3289,10 +3289,10 @@ static struct omap_clk omap3xxx_clks[] = {
3289 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), 3289 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3290 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), 3290 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3291 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3291 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3292 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3292 CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3293 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), 3293 CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
3294 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), 3294 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3295 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), 3295 CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
3296 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), 3296 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
3297 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), 3297 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
3298 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), 3298 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
@@ -3322,13 +3322,13 @@ static struct omap_clk omap3xxx_clks[] = {
3322 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3322 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3323 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3323 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3324 CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3324 CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3325 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3325 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3326 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), 3326 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3327 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), 3327 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3328 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), 3328 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3329 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), 3329 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3330 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), 3330 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3331 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), 3331 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3332 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), 3332 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3333 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3333 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3334 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3334 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 279534240fc3..f1fedb71ae08 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3166,11 +3166,11 @@ static struct omap_clk omap44xx_clks[] = {
3166 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 3166 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
3167 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 3167 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
3168 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), 3168 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
3169 CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), 3169 CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X),
3170 CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), 3170 CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X),
3171 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), 3171 CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X),
3172 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), 3172 CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X),
3173 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), 3173 CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X),
3174 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), 3174 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3175 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), 3175 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3176 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), 3176 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
@@ -3253,11 +3253,11 @@ static struct omap_clk omap44xx_clks[] = {
3253 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 3253 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3254 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 3254 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3255 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), 3255 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3256 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), 3256 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3257 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), 3257 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3258 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), 3258 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
3259 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), 3259 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
3260 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), 3260 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
3261 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 3261 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
3262 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 3262 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
3263 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 3263 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 70d242007e0b..ab878545bd9b 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -173,7 +173,7 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
173{ 173{
174 struct clkdm_autodep *autodep; 174 struct clkdm_autodep *autodep;
175 175
176 if (!autodeps) 176 if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
177 return; 177 return;
178 178
179 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { 179 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@@ -207,7 +207,7 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
207{ 207{
208 struct clkdm_autodep *autodep; 208 struct clkdm_autodep *autodep;
209 209
210 if (!autodeps) 210 if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
211 return; 211 return;
212 212
213 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { 213 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@@ -400,12 +400,6 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
400 struct clkdm_dep *cd; 400 struct clkdm_dep *cd;
401 int ret = 0; 401 int ret = 0;
402 402
403 if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
404 pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
405 clkdm1->name, clkdm2->name, __func__);
406 return -EINVAL;
407 }
408
409 if (!clkdm1 || !clkdm2) 403 if (!clkdm1 || !clkdm2)
410 return -EINVAL; 404 return -EINVAL;
411 405
@@ -447,12 +441,6 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
447 struct clkdm_dep *cd; 441 struct clkdm_dep *cd;
448 int ret = 0; 442 int ret = 0;
449 443
450 if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
451 pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
452 clkdm1->name, clkdm2->name, __func__);
453 return -EINVAL;
454 }
455
456 if (!clkdm1 || !clkdm2) 444 if (!clkdm1 || !clkdm2)
457 return -EINVAL; 445 return -EINVAL;
458 446
@@ -501,12 +489,6 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
501 if (!clkdm1 || !clkdm2) 489 if (!clkdm1 || !clkdm2)
502 return -EINVAL; 490 return -EINVAL;
503 491
504 if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
505 pr_err("clockdomain: %s/%s: %s: not yet implemented\n",
506 clkdm1->name, clkdm2->name, __func__);
507 return -EINVAL;
508 }
509
510 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); 492 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
511 if (IS_ERR(cd)) 493 if (IS_ERR(cd))
512 ret = PTR_ERR(cd); 494 ret = PTR_ERR(cd);
@@ -536,12 +518,6 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
536 */ 518 */
537int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) 519int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
538{ 520{
539 if (!cpu_is_omap24xx() && !cpu_is_omap34xx()) {
540 pr_err("clockdomain: %s: %s: not yet implemented\n",
541 clkdm->name, __func__);
542 return -EINVAL;
543 }
544
545 if (!clkdm) 521 if (!clkdm)
546 return -EINVAL; 522 return -EINVAL;
547 523
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index de52f059f9e2..85b3dce65640 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -4,7 +4,7 @@
4 * OMAP2/3 clockdomain framework functions 4 * OMAP2/3 clockdomain framework functions
5 * 5 *
6 * Copyright (C) 2008 Texas Instruments, Inc. 6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008-2010 Nokia Corporation 7 * Copyright (C) 2008-2011 Nokia Corporation
8 * 8 *
9 * Paul Walmsley 9 * Paul Walmsley
10 * 10 *
@@ -22,11 +22,19 @@
22#include <plat/clock.h> 22#include <plat/clock.h>
23#include <plat/cpu.h> 23#include <plat/cpu.h>
24 24
25/* Clockdomain capability flags */ 25/*
26 * Clockdomain flags
27 *
28 * XXX Document CLKDM_CAN_* flags
29 *
30 * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
31 * clockdomain. (Currently, this applies to OMAP3 clockdomains only.)
32 */
26#define CLKDM_CAN_FORCE_SLEEP (1 << 0) 33#define CLKDM_CAN_FORCE_SLEEP (1 << 0)
27#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) 34#define CLKDM_CAN_FORCE_WAKEUP (1 << 1)
28#define CLKDM_CAN_ENABLE_AUTO (1 << 2) 35#define CLKDM_CAN_ENABLE_AUTO (1 << 2)
29#define CLKDM_CAN_DISABLE_AUTO (1 << 3) 36#define CLKDM_CAN_DISABLE_AUTO (1 << 3)
37#define CLKDM_NO_AUTODEPS (1 << 4)
30 38
31#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) 39#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
32#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) 40#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index c0ccc4701646..a1a4ecd26544 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -12,8 +12,60 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15#include <linux/kernel.h>
15#include "clockdomain.h" 16#include "clockdomain.h"
16#include "cminst44xx.h" 17#include "cminst44xx.h"
18#include "cm44xx.h"
19
20static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
21 struct clockdomain *clkdm2)
22{
23 omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
24 clkdm1->prcm_partition,
25 clkdm1->cm_inst, clkdm1->clkdm_offs +
26 OMAP4_CM_STATICDEP);
27 return 0;
28}
29
30static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
31 struct clockdomain *clkdm2)
32{
33 omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
34 clkdm1->prcm_partition,
35 clkdm1->cm_inst, clkdm1->clkdm_offs +
36 OMAP4_CM_STATICDEP);
37 return 0;
38}
39
40static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
41 struct clockdomain *clkdm2)
42{
43 return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
44 clkdm1->cm_inst, clkdm1->clkdm_offs +
45 OMAP4_CM_STATICDEP,
46 (1 << clkdm2->dep_bit));
47}
48
49static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
50{
51 struct clkdm_dep *cd;
52 u32 mask = 0;
53
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!omap_chip_is(cd->omap_chip))
56 continue;
57 if (!cd->clkdm)
58 continue; /* only happens if data is erroneous */
59
60 mask |= 1 << cd->clkdm->dep_bit;
61 atomic_set(&cd->wkdep_usecount, 0);
62 }
63
64 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
65 clkdm->cm_inst, clkdm->clkdm_offs +
66 OMAP4_CM_STATICDEP);
67 return 0;
68}
17 69
18static int omap4_clkdm_sleep(struct clockdomain *clkdm) 70static int omap4_clkdm_sleep(struct clockdomain *clkdm)
19{ 71{
@@ -68,6 +120,14 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
68} 120}
69 121
70struct clkdm_ops omap4_clkdm_operations = { 122struct clkdm_ops omap4_clkdm_operations = {
123 .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
124 .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
125 .clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
126 .clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
127 .clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
128 .clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
129 .clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep,
130 .clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
71 .clkdm_sleep = omap4_clkdm_sleep, 131 .clkdm_sleep = omap4_clkdm_sleep,
72 .clkdm_wakeup = omap4_clkdm_wakeup, 132 .clkdm_wakeup = omap4_clkdm_wakeup,
73 .clkdm_allow_idle = omap4_clkdm_allow_idle, 133 .clkdm_allow_idle = omap4_clkdm_allow_idle,
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index eea6f8e40289..a607ec196e8b 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -18,11 +18,6 @@
18 * published by the Free Software Foundation. 18 * published by the Free Software Foundation.
19 */ 19 */
20 20
21/*
22 * To-Do List
23 * -> Populate the Sleep/Wakeup dependencies for the domains
24 */
25
26#include <linux/kernel.h> 21#include <linux/kernel.h>
27#include <linux/io.h> 22#include <linux/io.h>
28 23
@@ -35,6 +30,355 @@
35#include "prcm44xx.h" 30#include "prcm44xx.h"
36#include "prcm_mpu44xx.h" 31#include "prcm_mpu44xx.h"
37 32
33/* Static Dependencies for OMAP4 Clock Domains */
34
35static struct clkdm_dep ducati_wkup_sleep_deps[] = {
36 {
37 .clkdm_name = "abe_clkdm",
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
39 },
40 {
41 .clkdm_name = "ivahd_clkdm",
42 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
43 },
44 {
45 .clkdm_name = "l3_1_clkdm",
46 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
47 },
48 {
49 .clkdm_name = "l3_2_clkdm",
50 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
51 },
52 {
53 .clkdm_name = "l3_dss_clkdm",
54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
55 },
56 {
57 .clkdm_name = "l3_emif_clkdm",
58 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
59 },
60 {
61 .clkdm_name = "l3_gfx_clkdm",
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
63 },
64 {
65 .clkdm_name = "l3_init_clkdm",
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
67 },
68 {
69 .clkdm_name = "l4_cfg_clkdm",
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
71 },
72 {
73 .clkdm_name = "l4_per_clkdm",
74 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
75 },
76 {
77 .clkdm_name = "l4_secure_clkdm",
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
79 },
80 {
81 .clkdm_name = "l4_wkup_clkdm",
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
83 },
84 {
85 .clkdm_name = "tesla_clkdm",
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
87 },
88 { NULL },
89};
90
91static struct clkdm_dep iss_wkup_sleep_deps[] = {
92 {
93 .clkdm_name = "ivahd_clkdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
95 },
96 {
97 .clkdm_name = "l3_1_clkdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
99 },
100 {
101 .clkdm_name = "l3_emif_clkdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
103 },
104 { NULL },
105};
106
107static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
108 {
109 .clkdm_name = "l3_1_clkdm",
110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
111 },
112 {
113 .clkdm_name = "l3_emif_clkdm",
114 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
115 },
116 { NULL },
117};
118
119static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
120 {
121 .clkdm_name = "abe_clkdm",
122 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
123 },
124 {
125 .clkdm_name = "ivahd_clkdm",
126 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
127 },
128 {
129 .clkdm_name = "l3_1_clkdm",
130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
131 },
132 {
133 .clkdm_name = "l3_2_clkdm",
134 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
135 },
136 {
137 .clkdm_name = "l3_emif_clkdm",
138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
139 },
140 {
141 .clkdm_name = "l3_init_clkdm",
142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
143 },
144 {
145 .clkdm_name = "l4_cfg_clkdm",
146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
147 },
148 {
149 .clkdm_name = "l4_per_clkdm",
150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
151 },
152 { NULL },
153};
154
155static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
156 {
157 .clkdm_name = "abe_clkdm",
158 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
159 },
160 {
161 .clkdm_name = "ducati_clkdm",
162 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
163 },
164 {
165 .clkdm_name = "ivahd_clkdm",
166 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
167 },
168 {
169 .clkdm_name = "l3_1_clkdm",
170 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
171 },
172 {
173 .clkdm_name = "l3_dss_clkdm",
174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
175 },
176 {
177 .clkdm_name = "l3_emif_clkdm",
178 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
179 },
180 {
181 .clkdm_name = "l3_init_clkdm",
182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
183 },
184 {
185 .clkdm_name = "l4_cfg_clkdm",
186 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
187 },
188 {
189 .clkdm_name = "l4_per_clkdm",
190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
191 },
192 {
193 .clkdm_name = "l4_secure_clkdm",
194 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
195 },
196 {
197 .clkdm_name = "l4_wkup_clkdm",
198 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
199 },
200 { NULL },
201};
202
203static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
204 {
205 .clkdm_name = "ivahd_clkdm",
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
207 },
208 {
209 .clkdm_name = "l3_2_clkdm",
210 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
211 },
212 {
213 .clkdm_name = "l3_emif_clkdm",
214 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
215 },
216 { NULL },
217};
218
219static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
220 {
221 .clkdm_name = "ivahd_clkdm",
222 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
223 },
224 {
225 .clkdm_name = "l3_1_clkdm",
226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
227 },
228 {
229 .clkdm_name = "l3_emif_clkdm",
230 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
231 },
232 { NULL },
233};
234
235static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
236 {
237 .clkdm_name = "abe_clkdm",
238 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
239 },
240 {
241 .clkdm_name = "ivahd_clkdm",
242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
243 },
244 {
245 .clkdm_name = "l3_emif_clkdm",
246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
247 },
248 {
249 .clkdm_name = "l4_cfg_clkdm",
250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
251 },
252 {
253 .clkdm_name = "l4_per_clkdm",
254 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
255 },
256 {
257 .clkdm_name = "l4_secure_clkdm",
258 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
259 },
260 {
261 .clkdm_name = "l4_wkup_clkdm",
262 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
263 },
264 { NULL },
265};
266
267static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
268 {
269 .clkdm_name = "l3_1_clkdm",
270 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
271 },
272 {
273 .clkdm_name = "l3_emif_clkdm",
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
275 },
276 {
277 .clkdm_name = "l4_per_clkdm",
278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
279 },
280 { NULL },
281};
282
283static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
284 {
285 .clkdm_name = "abe_clkdm",
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
287 },
288 {
289 .clkdm_name = "ducati_clkdm",
290 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
291 },
292 {
293 .clkdm_name = "ivahd_clkdm",
294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
295 },
296 {
297 .clkdm_name = "l3_1_clkdm",
298 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
299 },
300 {
301 .clkdm_name = "l3_2_clkdm",
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
303 },
304 {
305 .clkdm_name = "l3_dss_clkdm",
306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
307 },
308 {
309 .clkdm_name = "l3_emif_clkdm",
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
311 },
312 {
313 .clkdm_name = "l3_gfx_clkdm",
314 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
315 },
316 {
317 .clkdm_name = "l3_init_clkdm",
318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
319 },
320 {
321 .clkdm_name = "l4_cfg_clkdm",
322 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
323 },
324 {
325 .clkdm_name = "l4_per_clkdm",
326 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
327 },
328 {
329 .clkdm_name = "l4_secure_clkdm",
330 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
331 },
332 {
333 .clkdm_name = "l4_wkup_clkdm",
334 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
335 },
336 {
337 .clkdm_name = "tesla_clkdm",
338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
339 },
340 { NULL },
341};
342
343static struct clkdm_dep tesla_wkup_sleep_deps[] = {
344 {
345 .clkdm_name = "abe_clkdm",
346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
347 },
348 {
349 .clkdm_name = "ivahd_clkdm",
350 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
351 },
352 {
353 .clkdm_name = "l3_1_clkdm",
354 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
355 },
356 {
357 .clkdm_name = "l3_2_clkdm",
358 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
359 },
360 {
361 .clkdm_name = "l3_emif_clkdm",
362 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
363 },
364 {
365 .clkdm_name = "l3_init_clkdm",
366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
367 },
368 {
369 .clkdm_name = "l4_cfg_clkdm",
370 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
371 },
372 {
373 .clkdm_name = "l4_per_clkdm",
374 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
375 },
376 {
377 .clkdm_name = "l4_wkup_clkdm",
378 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
379 },
380 { NULL },
381};
38 382
39static struct clockdomain l4_cefuse_44xx_clkdm = { 383static struct clockdomain l4_cefuse_44xx_clkdm = {
40 .name = "l4_cefuse_clkdm", 384 .name = "l4_cefuse_clkdm",
@@ -52,6 +396,7 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
52 .prcm_partition = OMAP4430_CM2_PARTITION, 396 .prcm_partition = OMAP4430_CM2_PARTITION,
53 .cm_inst = OMAP4430_CM2_CORE_INST, 397 .cm_inst = OMAP4430_CM2_CORE_INST,
54 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, 398 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
399 .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
55 .flags = CLKDM_CAN_HWSUP, 400 .flags = CLKDM_CAN_HWSUP,
56 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 401 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
57}; 402};
@@ -62,6 +407,9 @@ static struct clockdomain tesla_44xx_clkdm = {
62 .prcm_partition = OMAP4430_CM1_PARTITION, 407 .prcm_partition = OMAP4430_CM1_PARTITION,
63 .cm_inst = OMAP4430_CM1_TESLA_INST, 408 .cm_inst = OMAP4430_CM1_TESLA_INST,
64 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, 409 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
410 .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
411 .wkdep_srcs = tesla_wkup_sleep_deps,
412 .sleepdep_srcs = tesla_wkup_sleep_deps,
65 .flags = CLKDM_CAN_HWSUP_SWSUP, 413 .flags = CLKDM_CAN_HWSUP_SWSUP,
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 414 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
67}; 415};
@@ -72,6 +420,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
72 .prcm_partition = OMAP4430_CM2_PARTITION, 420 .prcm_partition = OMAP4430_CM2_PARTITION,
73 .cm_inst = OMAP4430_CM2_GFX_INST, 421 .cm_inst = OMAP4430_CM2_GFX_INST,
74 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, 422 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
423 .dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
424 .wkdep_srcs = l3_gfx_wkup_sleep_deps,
425 .sleepdep_srcs = l3_gfx_wkup_sleep_deps,
75 .flags = CLKDM_CAN_HWSUP_SWSUP, 426 .flags = CLKDM_CAN_HWSUP_SWSUP,
76 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 427 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
77}; 428};
@@ -82,6 +433,9 @@ static struct clockdomain ivahd_44xx_clkdm = {
82 .prcm_partition = OMAP4430_CM2_PARTITION, 433 .prcm_partition = OMAP4430_CM2_PARTITION,
83 .cm_inst = OMAP4430_CM2_IVAHD_INST, 434 .cm_inst = OMAP4430_CM2_IVAHD_INST,
84 .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, 435 .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
436 .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
437 .wkdep_srcs = ivahd_wkup_sleep_deps,
438 .sleepdep_srcs = ivahd_wkup_sleep_deps,
85 .flags = CLKDM_CAN_HWSUP_SWSUP, 439 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 440 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
87}; 441};
@@ -92,6 +446,9 @@ static struct clockdomain l4_secure_44xx_clkdm = {
92 .prcm_partition = OMAP4430_CM2_PARTITION, 446 .prcm_partition = OMAP4430_CM2_PARTITION,
93 .cm_inst = OMAP4430_CM2_L4PER_INST, 447 .cm_inst = OMAP4430_CM2_L4PER_INST,
94 .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, 448 .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
449 .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
450 .wkdep_srcs = l4_secure_wkup_sleep_deps,
451 .sleepdep_srcs = l4_secure_wkup_sleep_deps,
95 .flags = CLKDM_CAN_HWSUP_SWSUP, 452 .flags = CLKDM_CAN_HWSUP_SWSUP,
96 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 453 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
97}; 454};
@@ -102,6 +459,7 @@ static struct clockdomain l4_per_44xx_clkdm = {
102 .prcm_partition = OMAP4430_CM2_PARTITION, 459 .prcm_partition = OMAP4430_CM2_PARTITION,
103 .cm_inst = OMAP4430_CM2_L4PER_INST, 460 .cm_inst = OMAP4430_CM2_L4PER_INST,
104 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, 461 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
462 .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
105 .flags = CLKDM_CAN_HWSUP_SWSUP, 463 .flags = CLKDM_CAN_HWSUP_SWSUP,
106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 464 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
107}; 465};
@@ -112,6 +470,7 @@ static struct clockdomain abe_44xx_clkdm = {
112 .prcm_partition = OMAP4430_CM1_PARTITION, 470 .prcm_partition = OMAP4430_CM1_PARTITION,
113 .cm_inst = OMAP4430_CM1_ABE_INST, 471 .cm_inst = OMAP4430_CM1_ABE_INST,
114 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, 472 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
473 .dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
115 .flags = CLKDM_CAN_HWSUP_SWSUP, 474 .flags = CLKDM_CAN_HWSUP_SWSUP,
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 475 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
117}; 476};
@@ -131,6 +490,9 @@ static struct clockdomain l3_init_44xx_clkdm = {
131 .prcm_partition = OMAP4430_CM2_PARTITION, 490 .prcm_partition = OMAP4430_CM2_PARTITION,
132 .cm_inst = OMAP4430_CM2_L3INIT_INST, 491 .cm_inst = OMAP4430_CM2_L3INIT_INST,
133 .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, 492 .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
493 .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
494 .wkdep_srcs = l3_init_wkup_sleep_deps,
495 .sleepdep_srcs = l3_init_wkup_sleep_deps,
134 .flags = CLKDM_CAN_HWSUP_SWSUP, 496 .flags = CLKDM_CAN_HWSUP_SWSUP,
135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
136}; 498};
@@ -141,6 +503,8 @@ static struct clockdomain mpuss_44xx_clkdm = {
141 .prcm_partition = OMAP4430_CM1_PARTITION, 503 .prcm_partition = OMAP4430_CM1_PARTITION,
142 .cm_inst = OMAP4430_CM1_MPU_INST, 504 .cm_inst = OMAP4430_CM1_MPU_INST,
143 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, 505 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
506 .wkdep_srcs = mpuss_wkup_sleep_deps,
507 .sleepdep_srcs = mpuss_wkup_sleep_deps,
144 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 508 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
145 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
146}; 510};
@@ -150,7 +514,7 @@ static struct clockdomain mpu0_44xx_clkdm = {
150 .pwrdm = { .name = "cpu0_pwrdm" }, 514 .pwrdm = { .name = "cpu0_pwrdm" },
151 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, 515 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
152 .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, 516 .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
153 .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS, 517 .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
154 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 518 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
155 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 519 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
156}; 520};
@@ -160,7 +524,7 @@ static struct clockdomain mpu1_44xx_clkdm = {
160 .pwrdm = { .name = "cpu1_pwrdm" }, 524 .pwrdm = { .name = "cpu1_pwrdm" },
161 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, 525 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
162 .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, 526 .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
163 .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS, 527 .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
164 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 528 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 529 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
166}; 530};
@@ -171,6 +535,7 @@ static struct clockdomain l3_emif_44xx_clkdm = {
171 .prcm_partition = OMAP4430_CM2_PARTITION, 535 .prcm_partition = OMAP4430_CM2_PARTITION,
172 .cm_inst = OMAP4430_CM2_CORE_INST, 536 .cm_inst = OMAP4430_CM2_CORE_INST,
173 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, 537 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
538 .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
174 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 539 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
175 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 540 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
176}; 541};
@@ -191,6 +556,9 @@ static struct clockdomain ducati_44xx_clkdm = {
191 .prcm_partition = OMAP4430_CM2_PARTITION, 556 .prcm_partition = OMAP4430_CM2_PARTITION,
192 .cm_inst = OMAP4430_CM2_CORE_INST, 557 .cm_inst = OMAP4430_CM2_CORE_INST,
193 .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, 558 .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
559 .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
560 .wkdep_srcs = ducati_wkup_sleep_deps,
561 .sleepdep_srcs = ducati_wkup_sleep_deps,
194 .flags = CLKDM_CAN_HWSUP_SWSUP, 562 .flags = CLKDM_CAN_HWSUP_SWSUP,
195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
196}; 564};
@@ -201,6 +569,7 @@ static struct clockdomain l3_2_44xx_clkdm = {
201 .prcm_partition = OMAP4430_CM2_PARTITION, 569 .prcm_partition = OMAP4430_CM2_PARTITION,
202 .cm_inst = OMAP4430_CM2_CORE_INST, 570 .cm_inst = OMAP4430_CM2_CORE_INST,
203 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, 571 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
572 .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
204 .flags = CLKDM_CAN_HWSUP, 573 .flags = CLKDM_CAN_HWSUP,
205 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
206}; 575};
@@ -211,6 +580,7 @@ static struct clockdomain l3_1_44xx_clkdm = {
211 .prcm_partition = OMAP4430_CM2_PARTITION, 580 .prcm_partition = OMAP4430_CM2_PARTITION,
212 .cm_inst = OMAP4430_CM2_CORE_INST, 581 .cm_inst = OMAP4430_CM2_CORE_INST,
213 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, 582 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
583 .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
214 .flags = CLKDM_CAN_HWSUP, 584 .flags = CLKDM_CAN_HWSUP,
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 585 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
216}; 586};
@@ -221,6 +591,8 @@ static struct clockdomain l3_d2d_44xx_clkdm = {
221 .prcm_partition = OMAP4430_CM2_PARTITION, 591 .prcm_partition = OMAP4430_CM2_PARTITION,
222 .cm_inst = OMAP4430_CM2_CORE_INST, 592 .cm_inst = OMAP4430_CM2_CORE_INST,
223 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, 593 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
594 .wkdep_srcs = l3_d2d_wkup_sleep_deps,
595 .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
224 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 596 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
225 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 597 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
226}; 598};
@@ -231,6 +603,8 @@ static struct clockdomain iss_44xx_clkdm = {
231 .prcm_partition = OMAP4430_CM2_PARTITION, 603 .prcm_partition = OMAP4430_CM2_PARTITION,
232 .cm_inst = OMAP4430_CM2_CAM_INST, 604 .cm_inst = OMAP4430_CM2_CAM_INST,
233 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, 605 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
606 .wkdep_srcs = iss_wkup_sleep_deps,
607 .sleepdep_srcs = iss_wkup_sleep_deps,
234 .flags = CLKDM_CAN_HWSUP_SWSUP, 608 .flags = CLKDM_CAN_HWSUP_SWSUP,
235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
236}; 610};
@@ -241,6 +615,9 @@ static struct clockdomain l3_dss_44xx_clkdm = {
241 .prcm_partition = OMAP4430_CM2_PARTITION, 615 .prcm_partition = OMAP4430_CM2_PARTITION,
242 .cm_inst = OMAP4430_CM2_DSS_INST, 616 .cm_inst = OMAP4430_CM2_DSS_INST,
243 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, 617 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
618 .dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
619 .wkdep_srcs = l3_dss_wkup_sleep_deps,
620 .sleepdep_srcs = l3_dss_wkup_sleep_deps,
244 .flags = CLKDM_CAN_HWSUP_SWSUP, 621 .flags = CLKDM_CAN_HWSUP_SWSUP,
245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 622 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
246}; 623};
@@ -251,6 +628,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
251 .prcm_partition = OMAP4430_PRM_PARTITION, 628 .prcm_partition = OMAP4430_PRM_PARTITION,
252 .cm_inst = OMAP4430_PRM_WKUP_CM_INST, 629 .cm_inst = OMAP4430_PRM_WKUP_CM_INST,
253 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, 630 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
631 .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
254 .flags = CLKDM_CAN_HWSUP, 632 .flags = CLKDM_CAN_HWSUP,
255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 633 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
256}; 634};
@@ -271,6 +649,8 @@ static struct clockdomain l3_dma_44xx_clkdm = {
271 .prcm_partition = OMAP4430_CM2_PARTITION, 649 .prcm_partition = OMAP4430_CM2_PARTITION,
272 .cm_inst = OMAP4430_CM2_CORE_INST, 650 .cm_inst = OMAP4430_CM2_CORE_INST,
273 .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, 651 .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
652 .wkdep_srcs = l3_dma_wkup_sleep_deps,
653 .sleepdep_srcs = l3_dma_wkup_sleep_deps,
274 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 654 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
275 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
276}; 656};
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 48fc3f426fbd..0b87ec82b41c 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -21,6 +21,7 @@
21#include "cm.h" 21#include "cm.h"
22 22
23#define OMAP4_CM_CLKSTCTRL 0x0000 23#define OMAP4_CM_CLKSTCTRL 0x0000
24#define OMAP4_CM_STATICDEP 0x0004
24 25
25/* Function prototypes */ 26/* Function prototypes */
26# ifndef __ASSEMBLER__ 27# ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index c04bbbea17a5..a482bfa0a954 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -73,6 +73,27 @@ u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
73 return v; 73 return v;
74} 74}
75 75
76u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
77{
78 return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
79}
80
81u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
82{
83 return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
84}
85
86u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
87{
88 u32 v;
89
90 v = omap4_cminst_read_inst_reg(part, inst, idx);
91 v &= mask;
92 v >>= __ffs(mask);
93
94 return v;
95}
96
76/* 97/*
77 * 98 *
78 */ 99 */
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index a6abd0a8cb82..2b32c181a2ee 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -25,6 +25,12 @@ extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
25extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); 25extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
26extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, 26extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
27 s16 inst, s16 idx); 27 s16 inst, s16 idx);
28extern u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst,
29 s16 idx);
30extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
31 s16 idx);
32extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
33 u32 mask);
28 34
29extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); 35extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
30 36
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 71f099b85e7c..0d2d6a9c303c 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -31,10 +31,75 @@
31#include <plat/dma.h> 31#include <plat/dma.h>
32#include <plat/omap_hwmod.h> 32#include <plat/omap_hwmod.h>
33#include <plat/omap_device.h> 33#include <plat/omap_device.h>
34#include <plat/omap4-keypad.h>
34 35
35#include "mux.h" 36#include "mux.h"
36#include "control.h" 37#include "control.h"
37 38
39#define L3_MODULES_MAX_LEN 12
40#define L3_MODULES 3
41
42static int __init omap3_l3_init(void)
43{
44 int l;
45 struct omap_hwmod *oh;
46 struct omap_device *od;
47 char oh_name[L3_MODULES_MAX_LEN];
48
49 /*
50 * To avoid code running on other OMAPs in
51 * multi-omap builds
52 */
53 if (!(cpu_is_omap34xx()))
54 return -ENODEV;
55
56 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
57
58 oh = omap_hwmod_lookup(oh_name);
59
60 if (!oh)
61 pr_err("could not look up %s\n", oh_name);
62
63 od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
64 NULL, 0, 0);
65
66 WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
67
68 return PTR_ERR(od);
69}
70postcore_initcall(omap3_l3_init);
71
72static int __init omap4_l3_init(void)
73{
74 int l, i;
75 struct omap_hwmod *oh[3];
76 struct omap_device *od;
77 char oh_name[L3_MODULES_MAX_LEN];
78
79 /*
80 * To avoid code running on other OMAPs in
81 * multi-omap builds
82 */
83 if (!(cpu_is_omap44xx()))
84 return -ENODEV;
85
86 for (i = 0; i < L3_MODULES; i++) {
87 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
88
89 oh[i] = omap_hwmod_lookup(oh_name);
90 if (!(oh[i]))
91 pr_err("could not look up %s\n", oh_name);
92 }
93
94 od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
95 0, NULL, 0, 0);
96
97 WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
98
99 return PTR_ERR(od);
100}
101postcore_initcall(omap4_l3_init);
102
38#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 103#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
39 104
40static struct resource cam_resources[] = { 105static struct resource cam_resources[] = {
@@ -142,96 +207,70 @@ static inline void omap_init_camera(void)
142} 207}
143#endif 208#endif
144 209
145#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 210struct omap_device_pm_latency omap_keyboard_latency[] = {
146
147#define MBOX_REG_SIZE 0x120
148
149#ifdef CONFIG_ARCH_OMAP2
150static struct resource omap2_mbox_resources[] = {
151 { 211 {
152 .start = OMAP24XX_MAILBOX_BASE, 212 .deactivate_func = omap_device_idle_hwmods,
153 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, 213 .activate_func = omap_device_enable_hwmods,
154 .flags = IORESOURCE_MEM, 214 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
155 },
156 {
157 .start = INT_24XX_MAIL_U0_MPU,
158 .flags = IORESOURCE_IRQ,
159 .name = "dsp",
160 },
161 {
162 .start = INT_24XX_MAIL_U3_MPU,
163 .flags = IORESOURCE_IRQ,
164 .name = "iva",
165 }, 215 },
166}; 216};
167static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
168#else
169#define omap2_mbox_resources NULL
170#define omap2_mbox_resources_sz 0
171#endif
172 217
173#ifdef CONFIG_ARCH_OMAP3 218int __init omap4_keyboard_init(struct omap4_keypad_platform_data
174static struct resource omap3_mbox_resources[] = { 219 *sdp4430_keypad_data)
175 { 220{
176 .start = OMAP34XX_MAILBOX_BASE, 221 struct omap_device *od;
177 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, 222 struct omap_hwmod *oh;
178 .flags = IORESOURCE_MEM, 223 struct omap4_keypad_platform_data *keypad_data;
179 }, 224 unsigned int id = -1;
180 { 225 char *oh_name = "kbd";
181 .start = INT_24XX_MAIL_U0_MPU, 226 char *name = "omap4-keypad";
182 .flags = IORESOURCE_IRQ,
183 .name = "dsp",
184 },
185};
186static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
187#else
188#define omap3_mbox_resources NULL
189#define omap3_mbox_resources_sz 0
190#endif
191 227
192#ifdef CONFIG_ARCH_OMAP4 228 oh = omap_hwmod_lookup(oh_name);
229 if (!oh) {
230 pr_err("Could not look up %s\n", oh_name);
231 return -ENODEV;
232 }
193 233
194#define OMAP4_MBOX_REG_SIZE 0x130 234 keypad_data = sdp4430_keypad_data;
195static struct resource omap4_mbox_resources[] = {
196 {
197 .start = OMAP44XX_MAILBOX_BASE,
198 .end = OMAP44XX_MAILBOX_BASE +
199 OMAP4_MBOX_REG_SIZE - 1,
200 .flags = IORESOURCE_MEM,
201 },
202 {
203 .start = OMAP44XX_IRQ_MAIL_U0,
204 .flags = IORESOURCE_IRQ,
205 .name = "mbox",
206 },
207};
208static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
209#else
210#define omap4_mbox_resources NULL
211#define omap4_mbox_resources_sz 0
212#endif
213 235
214static struct platform_device mbox_device = { 236 od = omap_device_build(name, id, oh, keypad_data,
215 .name = "omap-mailbox", 237 sizeof(struct omap4_keypad_platform_data),
216 .id = -1, 238 omap_keyboard_latency,
239 ARRAY_SIZE(omap_keyboard_latency), 0);
240
241 if (IS_ERR(od)) {
242 WARN(1, "Cant build omap_device for %s:%s.\n",
243 name, oh->name);
244 return PTR_ERR(od);
245 }
246
247 return 0;
248}
249
250#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
251static struct omap_device_pm_latency mbox_latencies[] = {
252 [0] = {
253 .activate_func = omap_device_enable_hwmods,
254 .deactivate_func = omap_device_idle_hwmods,
255 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
256 },
217}; 257};
218 258
219static inline void omap_init_mbox(void) 259static inline void omap_init_mbox(void)
220{ 260{
221 if (cpu_is_omap24xx()) { 261 struct omap_hwmod *oh;
222 mbox_device.resource = omap2_mbox_resources; 262 struct omap_device *od;
223 mbox_device.num_resources = omap2_mbox_resources_sz; 263
224 } else if (cpu_is_omap34xx()) { 264 oh = omap_hwmod_lookup("mailbox");
225 mbox_device.resource = omap3_mbox_resources; 265 if (!oh) {
226 mbox_device.num_resources = omap3_mbox_resources_sz; 266 pr_err("%s: unable to find hwmod\n", __func__);
227 } else if (cpu_is_omap44xx()) {
228 mbox_device.resource = omap4_mbox_resources;
229 mbox_device.num_resources = omap4_mbox_resources_sz;
230 } else {
231 pr_err("%s: platform not supported\n", __func__);
232 return; 267 return;
233 } 268 }
234 platform_device_register(&mbox_device); 269
270 od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
271 mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
272 WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
273 __func__, PTR_ERR(od));
235} 274}
236#else 275#else
237static inline void omap_init_mbox(void) { } 276static inline void omap_init_mbox(void) { }
@@ -503,117 +542,10 @@ static inline void omap_init_aes(void) { }
503 542
504/*-------------------------------------------------------------------------*/ 543/*-------------------------------------------------------------------------*/
505 544
506#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 545#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
507
508#define MMCHS_SYSCONFIG 0x0010
509#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
510#define MMCHS_SYSSTATUS 0x0014
511#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
512
513static struct platform_device dummy_pdev = {
514 .dev = {
515 .bus = &platform_bus_type,
516 },
517};
518
519/**
520 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
521 *
522 * Ensure that each MMC controller is fully reset. Controllers
523 * left in an unknown state (by bootloader) may prevent retention
524 * or OFF-mode. This is especially important in cases where the
525 * MMC driver is not enabled, _or_ built as a module.
526 *
527 * In order for reset to work, interface, functional and debounce
528 * clocks must be enabled. The debounce clock comes from func_32k_clk
529 * and is not under SW control, so we only enable i- and f-clocks.
530 **/
531static void __init omap_hsmmc_reset(void)
532{
533 u32 i, nr_controllers;
534 struct clk *iclk, *fclk;
535
536 if (cpu_is_omap242x())
537 return;
538
539 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
540 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
541
542 for (i = 0; i < nr_controllers; i++) {
543 u32 v, base = 0;
544 struct device *dev = &dummy_pdev.dev;
545
546 switch (i) {
547 case 0:
548 base = OMAP2_MMC1_BASE;
549 break;
550 case 1:
551 base = OMAP2_MMC2_BASE;
552 break;
553 case 2:
554 base = OMAP3_MMC3_BASE;
555 break;
556 case 3:
557 if (!cpu_is_omap44xx())
558 return;
559 base = OMAP4_MMC4_BASE;
560 break;
561 case 4:
562 if (!cpu_is_omap44xx())
563 return;
564 base = OMAP4_MMC5_BASE;
565 break;
566 }
567
568 if (cpu_is_omap44xx())
569 base += OMAP4_MMC_REG_OFFSET;
570
571 dummy_pdev.id = i;
572 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
573 iclk = clk_get(dev, "ick");
574 if (IS_ERR(iclk))
575 goto err1;
576 if (clk_enable(iclk))
577 goto err2;
578
579 fclk = clk_get(dev, "fck");
580 if (IS_ERR(fclk))
581 goto err3;
582 if (clk_enable(fclk))
583 goto err4;
584
585 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
586 v = omap_readl(base + MMCHS_SYSSTATUS);
587 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
588 MMCHS_SYSSTATUS_RESETDONE))
589 cpu_relax();
590
591 clk_disable(fclk);
592 clk_put(fclk);
593 clk_disable(iclk);
594 clk_put(iclk);
595 }
596 return;
597
598err4:
599 clk_put(fclk);
600err3:
601 clk_disable(iclk);
602err2:
603 clk_put(iclk);
604err1:
605 printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
606 "cannot reset.\n", __func__, i);
607}
608#else
609static inline void omap_hsmmc_reset(void) {}
610#endif
611
612#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
613 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
614 546
615static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, 547static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
616 int controller_nr) 548 *mmc_controller)
617{ 549{
618 if ((mmc_controller->slots[0].switch_pin > 0) && \ 550 if ((mmc_controller->slots[0].switch_pin > 0) && \
619 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) 551 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
@@ -624,163 +556,44 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
624 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, 556 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
625 OMAP_PIN_INPUT_PULLUP); 557 OMAP_PIN_INPUT_PULLUP);
626 558
627 if (cpu_is_omap2420() && controller_nr == 0) { 559 omap_mux_init_signal("sdmmc_cmd", 0);
628 omap_mux_init_signal("sdmmc_cmd", 0); 560 omap_mux_init_signal("sdmmc_clki", 0);
629 omap_mux_init_signal("sdmmc_clki", 0); 561 omap_mux_init_signal("sdmmc_clko", 0);
630 omap_mux_init_signal("sdmmc_clko", 0); 562 omap_mux_init_signal("sdmmc_dat0", 0);
631 omap_mux_init_signal("sdmmc_dat0", 0); 563 omap_mux_init_signal("sdmmc_dat_dir0", 0);
632 omap_mux_init_signal("sdmmc_dat_dir0", 0); 564 omap_mux_init_signal("sdmmc_cmd_dir", 0);
633 omap_mux_init_signal("sdmmc_cmd_dir", 0); 565 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
634 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { 566 omap_mux_init_signal("sdmmc_dat1", 0);
635 omap_mux_init_signal("sdmmc_dat1", 0); 567 omap_mux_init_signal("sdmmc_dat2", 0);
636 omap_mux_init_signal("sdmmc_dat2", 0); 568 omap_mux_init_signal("sdmmc_dat3", 0);
637 omap_mux_init_signal("sdmmc_dat3", 0); 569 omap_mux_init_signal("sdmmc_dat_dir1", 0);
638 omap_mux_init_signal("sdmmc_dat_dir1", 0); 570 omap_mux_init_signal("sdmmc_dat_dir2", 0);
639 omap_mux_init_signal("sdmmc_dat_dir2", 0); 571 omap_mux_init_signal("sdmmc_dat_dir3", 0);
640 omap_mux_init_signal("sdmmc_dat_dir3", 0);
641 }
642
643 /*
644 * Use internal loop-back in MMC/SDIO Module Input Clock
645 * selection
646 */
647 if (mmc_controller->slots[0].internal_clock) {
648 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
649 v |= (1 << 24);
650 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
651 }
652 } 572 }
653 573
654 if (cpu_is_omap34xx()) { 574 /*
655 if (controller_nr == 0) { 575 * Use internal loop-back in MMC/SDIO Module Input Clock
656 omap_mux_init_signal("sdmmc1_clk", 576 * selection
657 OMAP_PIN_INPUT_PULLUP); 577 */
658 omap_mux_init_signal("sdmmc1_cmd", 578 if (mmc_controller->slots[0].internal_clock) {
659 OMAP_PIN_INPUT_PULLUP); 579 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
660 omap_mux_init_signal("sdmmc1_dat0", 580 v |= (1 << 24);
661 OMAP_PIN_INPUT_PULLUP); 581 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
662 if (mmc_controller->slots[0].caps &
663 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
664 omap_mux_init_signal("sdmmc1_dat1",
665 OMAP_PIN_INPUT_PULLUP);
666 omap_mux_init_signal("sdmmc1_dat2",
667 OMAP_PIN_INPUT_PULLUP);
668 omap_mux_init_signal("sdmmc1_dat3",
669 OMAP_PIN_INPUT_PULLUP);
670 }
671 if (mmc_controller->slots[0].caps &
672 MMC_CAP_8_BIT_DATA) {
673 omap_mux_init_signal("sdmmc1_dat4",
674 OMAP_PIN_INPUT_PULLUP);
675 omap_mux_init_signal("sdmmc1_dat5",
676 OMAP_PIN_INPUT_PULLUP);
677 omap_mux_init_signal("sdmmc1_dat6",
678 OMAP_PIN_INPUT_PULLUP);
679 omap_mux_init_signal("sdmmc1_dat7",
680 OMAP_PIN_INPUT_PULLUP);
681 }
682 }
683 if (controller_nr == 1) {
684 /* MMC2 */
685 omap_mux_init_signal("sdmmc2_clk",
686 OMAP_PIN_INPUT_PULLUP);
687 omap_mux_init_signal("sdmmc2_cmd",
688 OMAP_PIN_INPUT_PULLUP);
689 omap_mux_init_signal("sdmmc2_dat0",
690 OMAP_PIN_INPUT_PULLUP);
691
692 /*
693 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
694 * in the board-*.c files
695 */
696 if (mmc_controller->slots[0].caps &
697 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
698 omap_mux_init_signal("sdmmc2_dat1",
699 OMAP_PIN_INPUT_PULLUP);
700 omap_mux_init_signal("sdmmc2_dat2",
701 OMAP_PIN_INPUT_PULLUP);
702 omap_mux_init_signal("sdmmc2_dat3",
703 OMAP_PIN_INPUT_PULLUP);
704 }
705 if (mmc_controller->slots[0].caps &
706 MMC_CAP_8_BIT_DATA) {
707 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
708 OMAP_PIN_INPUT_PULLUP);
709 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
710 OMAP_PIN_INPUT_PULLUP);
711 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
712 OMAP_PIN_INPUT_PULLUP);
713 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
714 OMAP_PIN_INPUT_PULLUP);
715 }
716 }
717
718 /*
719 * For MMC3 the pins need to be muxed in the board-*.c files
720 */
721 } 582 }
722} 583}
723 584
724void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 585void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
725 int nr_controllers)
726{ 586{
727 int i; 587 char *name = "mmci-omap";
728 char *name;
729
730 for (i = 0; i < nr_controllers; i++) {
731 unsigned long base, size;
732 unsigned int irq = 0;
733 588
734 if (!mmc_data[i]) 589 if (!mmc_data[0]) {
735 continue; 590 pr_err("%s fails: Incomplete platform data\n", __func__);
736 591 return;
737 omap2_mmc_mux(mmc_data[i], i); 592 }
738 593
739 switch (i) { 594 omap242x_mmc_mux(mmc_data[0]);
740 case 0: 595 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
741 base = OMAP2_MMC1_BASE; 596 INT_24XX_MMC_IRQ, mmc_data[0]);
742 irq = INT_24XX_MMC_IRQ;
743 break;
744 case 1:
745 base = OMAP2_MMC2_BASE;
746 irq = INT_24XX_MMC2_IRQ;
747 break;
748 case 2:
749 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
750 return;
751 base = OMAP3_MMC3_BASE;
752 irq = INT_34XX_MMC3_IRQ;
753 break;
754 case 3:
755 if (!cpu_is_omap44xx())
756 return;
757 base = OMAP4_MMC4_BASE;
758 irq = OMAP44XX_IRQ_MMC4;
759 break;
760 case 4:
761 if (!cpu_is_omap44xx())
762 return;
763 base = OMAP4_MMC5_BASE;
764 irq = OMAP44XX_IRQ_MMC5;
765 break;
766 default:
767 continue;
768 }
769
770 if (cpu_is_omap2420()) {
771 size = OMAP2420_MMC_SIZE;
772 name = "mmci-omap";
773 } else if (cpu_is_omap44xx()) {
774 if (i < 3)
775 irq += OMAP44XX_IRQ_GIC_START;
776 size = OMAP4_HSMMC_SIZE;
777 name = "mmci-omap-hs";
778 } else {
779 size = OMAP3_HSMMC_SIZE;
780 name = "mmci-omap-hs";
781 }
782 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
783 };
784} 597}
785 598
786#endif 599#endif
@@ -854,7 +667,6 @@ static int __init omap2_init_devices(void)
854 * please keep these calls, and their implementations above, 667 * please keep these calls, and their implementations above,
855 * in alphabetical order so they're easier to sort through. 668 * in alphabetical order so they're easier to sort through.
856 */ 669 */
857 omap_hsmmc_reset();
858 omap_init_audio(); 670 omap_init_audio();
859 omap_init_camera(); 671 omap_init_camera();
860 omap_init_mbox(); 672 omap_init_mbox();
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
new file mode 100644
index 000000000000..b18db84b0349
--- /dev/null
+++ b/arch/arm/mach-omap2/display.c
@@ -0,0 +1,45 @@
1/*
2 * OMAP2plus display device setup / initialization.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
6 * Sumit Semwal
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24
25#include <plat/display.h>
26
27static struct platform_device omap_display_device = {
28 .name = "omapdss",
29 .id = -1,
30 .dev = {
31 .platform_data = NULL,
32 },
33};
34
35int __init omap_display_init(struct omap_dss_board_info *board_data)
36{
37 int r = 0;
38 omap_display_device.dev.platform_data = board_data;
39
40 r = platform_device_register(&omap_display_device);
41 if (r < 0)
42 printk(KERN_ERR "Unable to register OMAP-Display device\n");
43
44 return r;
45}
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 2bb29c160702..c1791d08ae56 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,6 +12,7 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/mtd/nand.h>
15 16
16#include <asm/mach/flash.h> 17#include <asm/mach/flash.h>
17 18
@@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void)
69 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); 70 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
70 71
71 /* Configure GPMC */ 72 /* Configure GPMC */
72 gpmc_cs_configure(gpmc_nand_data->cs, 73 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
73 GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); 74 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
75 else
76 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
74 gpmc_cs_configure(gpmc_nand_data->cs, 77 gpmc_cs_configure(gpmc_nand_data->cs,
75 GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); 78 GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
76 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); 79 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 3a7d25fb00ef..d776ded9830d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
94} 94}
95 95
96static void set_onenand_cfg(void __iomem *onenand_base, int latency, 96static void set_onenand_cfg(void __iomem *onenand_base, int latency,
97 int sync_read, int sync_write, int hf) 97 int sync_read, int sync_write, int hf, int vhf)
98{ 98{
99 u32 reg; 99 u32 reg;
100 100
@@ -114,12 +114,57 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
114 reg |= ONENAND_SYS_CFG1_HF; 114 reg |= ONENAND_SYS_CFG1_HF;
115 else 115 else
116 reg &= ~ONENAND_SYS_CFG1_HF; 116 reg &= ~ONENAND_SYS_CFG1_HF;
117 if (vhf)
118 reg |= ONENAND_SYS_CFG1_VHF;
119 else
120 reg &= ~ONENAND_SYS_CFG1_VHF;
117 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); 121 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
118} 122}
119 123
124static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
125 void __iomem *onenand_base, bool *clk_dep)
126{
127 u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
128 int freq = 0;
129
130 if (cfg->get_freq) {
131 struct onenand_freq_info fi;
132
133 fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
134 fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
135 fi.ver_id = ver;
136 freq = cfg->get_freq(&fi, clk_dep);
137 if (freq)
138 return freq;
139 }
140
141 switch ((ver >> 4) & 0xf) {
142 case 0:
143 freq = 40;
144 break;
145 case 1:
146 freq = 54;
147 break;
148 case 2:
149 freq = 66;
150 break;
151 case 3:
152 freq = 83;
153 break;
154 case 4:
155 freq = 104;
156 break;
157 default:
158 freq = 54;
159 break;
160 }
161
162 return freq;
163}
164
120static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, 165static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
121 void __iomem *onenand_base, 166 void __iomem *onenand_base,
122 int freq) 167 int *freq_ptr)
123{ 168{
124 struct gpmc_timings t; 169 struct gpmc_timings t;
125 const int t_cer = 15; 170 const int t_cer = 15;
@@ -130,10 +175,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
130 const int t_wph = 30; 175 const int t_wph = 30;
131 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 176 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
132 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; 177 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
133 int first_time = 0, hf = 0, sync_read = 0, sync_write = 0; 178 int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
134 int err, ticks_cez; 179 int err, ticks_cez;
135 int cs = cfg->cs; 180 int cs = cfg->cs, freq = *freq_ptr;
136 u32 reg; 181 u32 reg;
182 bool clk_dep = false;
137 183
138 if (cfg->flags & ONENAND_SYNC_READ) { 184 if (cfg->flags & ONENAND_SYNC_READ) {
139 sync_read = 1; 185 sync_read = 1;
@@ -148,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
148 err = omap2_onenand_set_async_mode(cs, onenand_base); 194 err = omap2_onenand_set_async_mode(cs, onenand_base);
149 if (err) 195 if (err)
150 return err; 196 return err;
151 reg = readw(onenand_base + ONENAND_REG_VERSION_ID); 197 freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
152 switch ((reg >> 4) & 0xf) {
153 case 0:
154 freq = 40;
155 break;
156 case 1:
157 freq = 54;
158 break;
159 case 2:
160 freq = 66;
161 break;
162 case 3:
163 freq = 83;
164 break;
165 case 4:
166 freq = 104;
167 break;
168 default:
169 freq = 54;
170 break;
171 }
172 first_time = 1; 198 first_time = 1;
173 } 199 }
174 200
@@ -180,7 +206,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
180 t_avdh = 2; 206 t_avdh = 2;
181 t_ach = 3; 207 t_ach = 3;
182 t_aavdh = 6; 208 t_aavdh = 6;
183 t_rdyo = 9; 209 t_rdyo = 6;
184 break; 210 break;
185 case 83: 211 case 83:
186 min_gpmc_clk_period = 12000; /* 83 MHz */ 212 min_gpmc_clk_period = 12000; /* 83 MHz */
@@ -217,16 +243,36 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
217 gpmc_clk_ns = gpmc_ticks_to_ns(div); 243 gpmc_clk_ns = gpmc_ticks_to_ns(div);
218 if (gpmc_clk_ns < 15) /* >66Mhz */ 244 if (gpmc_clk_ns < 15) /* >66Mhz */
219 hf = 1; 245 hf = 1;
220 if (hf) 246 if (gpmc_clk_ns < 12) /* >83Mhz */
247 vhf = 1;
248 if (vhf)
249 latency = 8;
250 else if (hf)
221 latency = 6; 251 latency = 6;
222 else if (gpmc_clk_ns >= 25) /* 40 MHz*/ 252 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
223 latency = 3; 253 latency = 3;
224 else 254 else
225 latency = 4; 255 latency = 4;
226 256
257 if (clk_dep) {
258 if (gpmc_clk_ns < 12) { /* >83Mhz */
259 t_ces = 3;
260 t_avds = 4;
261 } else if (gpmc_clk_ns < 15) { /* >66Mhz */
262 t_ces = 5;
263 t_avds = 4;
264 } else if (gpmc_clk_ns < 25) { /* >40Mhz */
265 t_ces = 6;
266 t_avds = 5;
267 } else {
268 t_ces = 7;
269 t_avds = 7;
270 }
271 }
272
227 if (first_time) 273 if (first_time)
228 set_onenand_cfg(onenand_base, latency, 274 set_onenand_cfg(onenand_base, latency,
229 sync_read, sync_write, hf); 275 sync_read, sync_write, hf, vhf);
230 276
231 if (div == 1) { 277 if (div == 1) {
232 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); 278 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -264,6 +310,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
264 /* Read */ 310 /* Read */
265 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh)); 311 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
266 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach)); 312 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
313 /* Force at least 1 clk between AVD High to OE Low */
314 if (t.oe_on <= t.adv_rd_off)
315 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
267 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div); 316 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
268 t.oe_off = t.access + gpmc_round_ns_to_ticks(1); 317 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
269 t.cs_rd_off = t.oe_off; 318 t.cs_rd_off = t.oe_off;
@@ -317,18 +366,20 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
317 if (err) 366 if (err)
318 return err; 367 return err;
319 368
320 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf); 369 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
370
371 *freq_ptr = freq;
321 372
322 return 0; 373 return 0;
323} 374}
324 375
325static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) 376static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
326{ 377{
327 struct device *dev = &gpmc_onenand_device.dev; 378 struct device *dev = &gpmc_onenand_device.dev;
328 379
329 /* Set sync timings in GPMC */ 380 /* Set sync timings in GPMC */
330 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, 381 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
331 freq) < 0) { 382 freq_ptr) < 0) {
332 dev_err(dev, "Unable to set synchronous mode\n"); 383 dev_err(dev, "Unable to set synchronous mode\n");
333 return -EINVAL; 384 return -EINVAL;
334 } 385 }
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1b7b3e7d02f7..674174365f78 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,6 +14,7 @@
14 */ 14 */
15#undef DEBUG 15#undef DEBUG
16 16
17#include <linux/irq.h>
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/init.h> 19#include <linux/init.h>
19#include <linux/err.h> 20#include <linux/err.h>
@@ -22,6 +23,7 @@
22#include <linux/spinlock.h> 23#include <linux/spinlock.h>
23#include <linux/io.h> 24#include <linux/io.h>
24#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/interrupt.h>
25 27
26#include <asm/mach-types.h> 28#include <asm/mach-types.h>
27#include <plat/gpmc.h> 29#include <plat/gpmc.h>
@@ -58,7 +60,6 @@
58#define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 60#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
59#define GPMC_SECTION_SHIFT 28 /* 128 MB */ 61#define GPMC_SECTION_SHIFT 28 /* 128 MB */
60 62
61#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
62#define CS_NUM_SHIFT 24 63#define CS_NUM_SHIFT 24
63#define ENABLE_PREFETCH (0x1 << 7) 64#define ENABLE_PREFETCH (0x1 << 7)
64#define DMA_MPU_MODE 2 65#define DMA_MPU_MODE 2
@@ -100,6 +101,8 @@ static void __iomem *gpmc_base;
100 101
101static struct clk *gpmc_l3_clk; 102static struct clk *gpmc_l3_clk;
102 103
104static irqreturn_t gpmc_handle_irq(int irq, void *dev);
105
103static void gpmc_write_reg(int idx, u32 val) 106static void gpmc_write_reg(int idx, u32 val)
104{ 107{
105 __raw_writel(val, gpmc_base + idx); 108 __raw_writel(val, gpmc_base + idx);
@@ -497,6 +500,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
497 u32 regval = 0; 500 u32 regval = 0;
498 501
499 switch (cmd) { 502 switch (cmd) {
503 case GPMC_ENABLE_IRQ:
504 gpmc_write_reg(GPMC_IRQENABLE, wval);
505 break;
506
500 case GPMC_SET_IRQ_STATUS: 507 case GPMC_SET_IRQ_STATUS:
501 gpmc_write_reg(GPMC_IRQSTATUS, wval); 508 gpmc_write_reg(GPMC_IRQSTATUS, wval);
502 break; 509 break;
@@ -598,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
598/** 605/**
599 * gpmc_prefetch_enable - configures and starts prefetch transfer 606 * gpmc_prefetch_enable - configures and starts prefetch transfer
600 * @cs: cs (chip select) number 607 * @cs: cs (chip select) number
608 * @fifo_th: fifo threshold to be used for read/ write
601 * @dma_mode: dma mode enable (1) or disable (0) 609 * @dma_mode: dma mode enable (1) or disable (0)
602 * @u32_count: number of bytes to be transferred 610 * @u32_count: number of bytes to be transferred
603 * @is_write: prefetch read(0) or write post(1) mode 611 * @is_write: prefetch read(0) or write post(1) mode
604 */ 612 */
605int gpmc_prefetch_enable(int cs, int dma_mode, 613int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
606 unsigned int u32_count, int is_write) 614 unsigned int u32_count, int is_write)
607{ 615{
608 616
609 if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { 617 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
618 pr_err("gpmc: fifo threshold is not supported\n");
619 return -1;
620 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
610 /* Set the amount of bytes to be prefetched */ 621 /* Set the amount of bytes to be prefetched */
611 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); 622 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
612 623
@@ -614,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
614 * enable the engine. Set which cs is has requested for. 625 * enable the engine. Set which cs is has requested for.
615 */ 626 */
616 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | 627 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
617 PREFETCH_FIFOTHRESHOLD | 628 PREFETCH_FIFOTHRESHOLD(fifo_th) |
618 ENABLE_PREFETCH | 629 ENABLE_PREFETCH |
619 (dma_mode << DMA_MPU_MODE) | 630 (dma_mode << DMA_MPU_MODE) |
620 (0x1 & is_write))); 631 (0x1 & is_write)));
@@ -678,9 +689,10 @@ static void __init gpmc_mem_init(void)
678 } 689 }
679} 690}
680 691
681void __init gpmc_init(void) 692static int __init gpmc_init(void)
682{ 693{
683 u32 l; 694 u32 l, irq;
695 int cs, ret = -EINVAL;
684 char *ck = NULL; 696 char *ck = NULL;
685 697
686 if (cpu_is_omap24xx()) { 698 if (cpu_is_omap24xx()) {
@@ -698,7 +710,7 @@ void __init gpmc_init(void)
698 } 710 }
699 711
700 if (WARN_ON(!ck)) 712 if (WARN_ON(!ck))
701 return; 713 return ret;
702 714
703 gpmc_l3_clk = clk_get(NULL, ck); 715 gpmc_l3_clk = clk_get(NULL, ck);
704 if (IS_ERR(gpmc_l3_clk)) { 716 if (IS_ERR(gpmc_l3_clk)) {
@@ -723,6 +735,36 @@ void __init gpmc_init(void)
723 l |= (0x02 << 3) | (1 << 0); 735 l |= (0x02 << 3) | (1 << 0);
724 gpmc_write_reg(GPMC_SYSCONFIG, l); 736 gpmc_write_reg(GPMC_SYSCONFIG, l);
725 gpmc_mem_init(); 737 gpmc_mem_init();
738
739 /* initalize the irq_chained */
740 irq = OMAP_GPMC_IRQ_BASE;
741 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
742 set_irq_handler(irq, handle_simple_irq);
743 set_irq_flags(irq, IRQF_VALID);
744 irq++;
745 }
746
747 ret = request_irq(INT_34XX_GPMC_IRQ,
748 gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
749 if (ret)
750 pr_err("gpmc: irq-%d could not claim: err %d\n",
751 INT_34XX_GPMC_IRQ, ret);
752 return ret;
753}
754postcore_initcall(gpmc_init);
755
756static irqreturn_t gpmc_handle_irq(int irq, void *dev)
757{
758 u8 cs;
759
760 if (irq != INT_34XX_GPMC_IRQ)
761 return IRQ_HANDLED;
762 /* check cs to invoke the irq */
763 cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
764 if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
765 generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
766
767 return IRQ_HANDLED;
726} 768}
727 769
728#ifdef CONFIG_ARCH_OMAP3 770#ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 34272e4863fd..137e1a5f3d85 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -16,7 +16,10 @@
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <plat/mmc.h> 17#include <plat/mmc.h>
18#include <plat/omap-pm.h> 18#include <plat/omap-pm.h>
19#include <plat/mux.h>
20#include <plat/omap_device.h>
19 21
22#include "mux.h"
20#include "hsmmc.h" 23#include "hsmmc.h"
21#include "control.h" 24#include "control.h"
22 25
@@ -28,10 +31,6 @@ static u16 control_mmc1;
28 31
29#define HSMMC_NAME_LEN 9 32#define HSMMC_NAME_LEN 9
30 33
31static struct hsmmc_controller {
32 char name[HSMMC_NAME_LEN + 1];
33} hsmmc[OMAP34XX_NR_MMC];
34
35#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 34#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
36 35
37static int hsmmc_get_context_loss(struct device *dev) 36static int hsmmc_get_context_loss(struct device *dev)
@@ -204,174 +203,312 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
204 return 0; 203 return 0;
205} 204}
206 205
207static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; 206static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
208 207 int controller_nr)
209void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
210{ 208{
211 struct omap2_hsmmc_info *c; 209 if ((mmc_controller->slots[0].switch_pin > 0) && \
212 int nr_hsmmc = ARRAY_SIZE(hsmmc_data); 210 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
213 int i; 211 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
214 u32 reg; 212 OMAP_PIN_INPUT_PULLUP);
215 213 if ((mmc_controller->slots[0].gpio_wp > 0) && \
216 if (!cpu_is_omap44xx()) { 214 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
217 if (cpu_is_omap2430()) { 215 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
218 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 216 OMAP_PIN_INPUT_PULLUP);
219 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; 217 if (cpu_is_omap34xx()) {
220 } else { 218 if (controller_nr == 0) {
221 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; 219 omap_mux_init_signal("sdmmc1_clk",
222 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; 220 OMAP_PIN_INPUT_PULLUP);
223 } 221 omap_mux_init_signal("sdmmc1_cmd",
224 } else { 222 OMAP_PIN_INPUT_PULLUP);
225 control_pbias_offset = 223 omap_mux_init_signal("sdmmc1_dat0",
226 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; 224 OMAP_PIN_INPUT_PULLUP);
227 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; 225 if (mmc_controller->slots[0].caps &
228 reg = omap4_ctrl_pad_readl(control_mmc1); 226 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
229 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | 227 omap_mux_init_signal("sdmmc1_dat1",
230 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); 228 OMAP_PIN_INPUT_PULLUP);
231 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | 229 omap_mux_init_signal("sdmmc1_dat2",
232 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); 230 OMAP_PIN_INPUT_PULLUP);
233 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| 231 omap_mux_init_signal("sdmmc1_dat3",
234 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | 232 OMAP_PIN_INPUT_PULLUP);
235 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); 233 }
236 omap4_ctrl_pad_writel(reg, control_mmc1); 234 if (mmc_controller->slots[0].caps &
237 } 235 MMC_CAP_8_BIT_DATA) {
238 236 omap_mux_init_signal("sdmmc1_dat4",
239 for (c = controllers; c->mmc; c++) { 237 OMAP_PIN_INPUT_PULLUP);
240 struct hsmmc_controller *hc = hsmmc + c->mmc - 1; 238 omap_mux_init_signal("sdmmc1_dat5",
241 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; 239 OMAP_PIN_INPUT_PULLUP);
242 240 omap_mux_init_signal("sdmmc1_dat6",
243 if (!c->mmc || c->mmc > nr_hsmmc) { 241 OMAP_PIN_INPUT_PULLUP);
244 pr_debug("MMC%d: no such controller\n", c->mmc); 242 omap_mux_init_signal("sdmmc1_dat7",
245 continue; 243 OMAP_PIN_INPUT_PULLUP);
246 } 244 }
247 if (mmc) {
248 pr_debug("MMC%d: already configured\n", c->mmc);
249 continue;
250 } 245 }
251 246 if (controller_nr == 1) {
252 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), 247 /* MMC2 */
253 GFP_KERNEL); 248 omap_mux_init_signal("sdmmc2_clk",
254 if (!mmc) { 249 OMAP_PIN_INPUT_PULLUP);
255 pr_err("Cannot allocate memory for mmc device!\n"); 250 omap_mux_init_signal("sdmmc2_cmd",
256 goto done; 251 OMAP_PIN_INPUT_PULLUP);
252 omap_mux_init_signal("sdmmc2_dat0",
253 OMAP_PIN_INPUT_PULLUP);
254
255 /*
256 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
257 * need to be muxed in the board-*.c files
258 */
259 if (mmc_controller->slots[0].caps &
260 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
261 omap_mux_init_signal("sdmmc2_dat1",
262 OMAP_PIN_INPUT_PULLUP);
263 omap_mux_init_signal("sdmmc2_dat2",
264 OMAP_PIN_INPUT_PULLUP);
265 omap_mux_init_signal("sdmmc2_dat3",
266 OMAP_PIN_INPUT_PULLUP);
267 }
268 if (mmc_controller->slots[0].caps &
269 MMC_CAP_8_BIT_DATA) {
270 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
271 OMAP_PIN_INPUT_PULLUP);
272 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
273 OMAP_PIN_INPUT_PULLUP);
274 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
275 OMAP_PIN_INPUT_PULLUP);
276 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
277 OMAP_PIN_INPUT_PULLUP);
278 }
257 } 279 }
258 280
259 if (c->name) 281 /*
260 strncpy(hc->name, c->name, HSMMC_NAME_LEN); 282 * For MMC3 the pins need to be muxed in the board-*.c files
261 else 283 */
262 snprintf(hc->name, ARRAY_SIZE(hc->name), 284 }
263 "mmc%islot%i", c->mmc, 1); 285}
264 mmc->slots[0].name = hc->name;
265 mmc->nr_slots = 1;
266 mmc->slots[0].caps = c->caps;
267 mmc->slots[0].internal_clock = !c->ext_clock;
268 mmc->dma_mask = 0xffffffff;
269 if (cpu_is_omap44xx())
270 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
271 else
272 mmc->reg_offset = 0;
273 286
274 mmc->get_context_loss_count = hsmmc_get_context_loss; 287static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
288 struct omap_mmc_platform_data *mmc)
289{
290 char *hc_name;
275 291
276 mmc->slots[0].switch_pin = c->gpio_cd; 292 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
277 mmc->slots[0].gpio_wp = c->gpio_wp; 293 if (!hc_name) {
294 pr_err("Cannot allocate memory for controller slot name\n");
295 kfree(hc_name);
296 return -ENOMEM;
297 }
278 298
279 mmc->slots[0].remux = c->remux; 299 if (c->name)
280 mmc->slots[0].init_card = c->init_card; 300 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
301 else
302 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
303 c->mmc, 1);
304 mmc->slots[0].name = hc_name;
305 mmc->nr_slots = 1;
306 mmc->slots[0].caps = c->caps;
307 mmc->slots[0].internal_clock = !c->ext_clock;
308 mmc->dma_mask = 0xffffffff;
309 if (cpu_is_omap44xx())
310 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
311 else
312 mmc->reg_offset = 0;
281 313
282 if (c->cover_only) 314 mmc->get_context_loss_count = hsmmc_get_context_loss;
283 mmc->slots[0].cover = 1;
284 315
285 if (c->nonremovable) 316 mmc->slots[0].switch_pin = c->gpio_cd;
286 mmc->slots[0].nonremovable = 1; 317 mmc->slots[0].gpio_wp = c->gpio_wp;
287 318
288 if (c->power_saving) 319 mmc->slots[0].remux = c->remux;
289 mmc->slots[0].power_saving = 1; 320 mmc->slots[0].init_card = c->init_card;
290 321
291 if (c->no_off) 322 if (c->cover_only)
292 mmc->slots[0].no_off = 1; 323 mmc->slots[0].cover = 1;
293 324
294 if (c->vcc_aux_disable_is_sleep) 325 if (c->nonremovable)
295 mmc->slots[0].vcc_aux_disable_is_sleep = 1; 326 mmc->slots[0].nonremovable = 1;
296 327
297 /* NOTE: MMC slots should have a Vcc regulator set up. 328 if (c->power_saving)
298 * This may be from a TWL4030-family chip, another 329 mmc->slots[0].power_saving = 1;
299 * controllable regulator, or a fixed supply.
300 *
301 * temporary HACK: ocr_mask instead of fixed supply
302 */
303 mmc->slots[0].ocr_mask = c->ocr_mask;
304 330
305 if (cpu_is_omap3517() || cpu_is_omap3505()) 331 if (c->no_off)
306 mmc->slots[0].set_power = nop_mmc_set_power; 332 mmc->slots[0].no_off = 1;
307 else
308 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
309 333
310 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) 334 if (c->vcc_aux_disable_is_sleep)
311 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 335 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
312 336
313 switch (c->mmc) { 337 /*
314 case 1: 338 * NOTE: MMC slots should have a Vcc regulator set up.
315 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 339 * This may be from a TWL4030-family chip, another
316 /* on-chip level shifting via PBIAS0/PBIAS1 */ 340 * controllable regulator, or a fixed supply.
317 if (cpu_is_omap44xx()) { 341 *
318 mmc->slots[0].before_set_reg = 342 * temporary HACK: ocr_mask instead of fixed supply
343 */
344 mmc->slots[0].ocr_mask = c->ocr_mask;
345
346 if (cpu_is_omap3517() || cpu_is_omap3505())
347 mmc->slots[0].set_power = nop_mmc_set_power;
348 else
349 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
350
351 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
352 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
353
354 switch (c->mmc) {
355 case 1:
356 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
357 /* on-chip level shifting via PBIAS0/PBIAS1 */
358 if (cpu_is_omap44xx()) {
359 mmc->slots[0].before_set_reg =
319 omap4_hsmmc1_before_set_reg; 360 omap4_hsmmc1_before_set_reg;
320 mmc->slots[0].after_set_reg = 361 mmc->slots[0].after_set_reg =
321 omap4_hsmmc1_after_set_reg; 362 omap4_hsmmc1_after_set_reg;
322 } else { 363 } else {
323 mmc->slots[0].before_set_reg = 364 mmc->slots[0].before_set_reg =
324 omap_hsmmc1_before_set_reg; 365 omap_hsmmc1_before_set_reg;
325 mmc->slots[0].after_set_reg = 366 mmc->slots[0].after_set_reg =
326 omap_hsmmc1_after_set_reg; 367 omap_hsmmc1_after_set_reg;
327 }
328 } 368 }
369 }
329 370
330 /* Omap3630 HSMMC1 supports only 4-bit */ 371 /* OMAP3630 HSMMC1 supports only 4-bit */
331 if (cpu_is_omap3630() && 372 if (cpu_is_omap3630() &&
332 (c->caps & MMC_CAP_8_BIT_DATA)) { 373 (c->caps & MMC_CAP_8_BIT_DATA)) {
333 c->caps &= ~MMC_CAP_8_BIT_DATA; 374 c->caps &= ~MMC_CAP_8_BIT_DATA;
334 c->caps |= MMC_CAP_4_BIT_DATA; 375 c->caps |= MMC_CAP_4_BIT_DATA;
335 mmc->slots[0].caps = c->caps; 376 mmc->slots[0].caps = c->caps;
336 } 377 }
337 break; 378 break;
338 case 2: 379 case 2:
339 if (c->ext_clock) 380 if (c->ext_clock)
340 c->transceiver = 1; 381 c->transceiver = 1;
341 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { 382 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
342 c->caps &= ~MMC_CAP_8_BIT_DATA; 383 c->caps &= ~MMC_CAP_8_BIT_DATA;
343 c->caps |= MMC_CAP_4_BIT_DATA; 384 c->caps |= MMC_CAP_4_BIT_DATA;
344 }
345 /* FALLTHROUGH */
346 case 3:
347 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
348 /* off-chip level shifting, or none */
349 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
350 mmc->slots[0].after_set_reg = NULL;
351 }
352 break;
353 default:
354 pr_err("MMC%d configuration not supported!\n", c->mmc);
355 kfree(mmc);
356 continue;
357 } 385 }
358 hsmmc_data[c->mmc - 1] = mmc; 386 /* FALLTHROUGH */
387 case 3:
388 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
389 /* off-chip level shifting, or none */
390 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
391 mmc->slots[0].after_set_reg = NULL;
392 }
393 break;
394 case 4:
395 case 5:
396 mmc->slots[0].before_set_reg = NULL;
397 mmc->slots[0].after_set_reg = NULL;
398 break;
399 default:
400 pr_err("MMC%d configuration not supported!\n", c->mmc);
401 kfree(hc_name);
402 return -ENODEV;
403 }
404 return 0;
405}
406
407static struct omap_device_pm_latency omap_hsmmc_latency[] = {
408 [0] = {
409 .deactivate_func = omap_device_idle_hwmods,
410 .activate_func = omap_device_enable_hwmods,
411 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
412 },
413 /*
414 * XXX There should also be an entry here to power off/on the
415 * MMC regulators/PBIAS cells, etc.
416 */
417};
418
419#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
420
421void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
422{
423 struct omap_hwmod *oh;
424 struct omap_device *od;
425 struct omap_device_pm_latency *ohl;
426 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
427 struct omap_mmc_platform_data *mmc_data;
428 struct omap_mmc_dev_attr *mmc_dev_attr;
429 char *name;
430 int l;
431 int ohl_cnt = 0;
432
433 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
434 if (!mmc_data) {
435 pr_err("Cannot allocate memory for mmc device!\n");
436 goto done;
359 } 437 }
360 438
361 omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); 439 if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
440 pr_err("%s fails!\n", __func__);
441 goto done;
442 }
443 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
444
445 name = "omap_hsmmc";
446 ohl = omap_hsmmc_latency;
447 ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
448
449 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
450 "mmc%d", ctrl_nr);
451 WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
452 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
453 oh = omap_hwmod_lookup(oh_name);
454 if (!oh) {
455 pr_err("Could not look up %s\n", oh_name);
456 kfree(mmc_data->slots[0].name);
457 goto done;
458 }
362 459
363 /* pass the device nodes back to board setup code */ 460 if (oh->dev_attr != NULL) {
364 for (c = controllers; c->mmc; c++) { 461 mmc_dev_attr = oh->dev_attr;
365 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; 462 mmc_data->controller_flags = mmc_dev_attr->flags;
463 }
366 464
367 if (!c->mmc || c->mmc > nr_hsmmc) 465 od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
368 continue; 466 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
369 c->dev = mmc->dev; 467 if (IS_ERR(od)) {
468 WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
469 kfree(mmc_data->slots[0].name);
470 goto done;
370 } 471 }
472 /*
473 * return device handle to board setup code
474 * required to populate for regulator framework structure
475 */
476 hsmmcinfo->dev = &od->pdev.dev;
371 477
372done: 478done:
373 for (i = 0; i < nr_hsmmc; i++) 479 kfree(mmc_data);
374 kfree(hsmmc_data[i]); 480}
481
482void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
483{
484 u32 reg;
485
486 if (!cpu_is_omap44xx()) {
487 if (cpu_is_omap2430()) {
488 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
489 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
490 } else {
491 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
492 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
493 }
494 } else {
495 control_pbias_offset =
496 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
497 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
498 reg = omap4_ctrl_pad_readl(control_mmc1);
499 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
500 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
501 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
502 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
503 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
504 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
505 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
506 omap4_ctrl_pad_writel(reg, control_mmc1);
507 }
508
509 for (; controllers->mmc; controllers++)
510 omap_init_hsmmc(controllers, controllers->mmc);
511
375} 512}
376 513
377#endif 514#endif
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 5c25f1b55235..3168b17bc264 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -6,7 +6,7 @@
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com> 7 * Written by Tony Lindgren <tony@atomide.com>
8 * 8 *
9 * Copyright (C) 2009 Texas Instruments 9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
@@ -328,7 +328,7 @@ static void __init omap4_check_revision(void)
328 */ 328 */
329 idcode = read_tap_reg(OMAP_TAP_IDCODE); 329 idcode = read_tap_reg(OMAP_TAP_IDCODE);
330 hawkeye = (idcode >> 12) & 0xffff; 330 hawkeye = (idcode >> 12) & 0xffff;
331 rev = (idcode >> 28) & 0xff; 331 rev = (idcode >> 28) & 0xf;
332 332
333 /* 333 /*
334 * Few initial ES2.0 samples IDCODE is same as ES1.0 334 * Few initial ES2.0 samples IDCODE is same as ES1.0
@@ -347,22 +347,31 @@ static void __init omap4_check_revision(void)
347 omap_chip.oc |= CHIP_IS_OMAP4430ES1; 347 omap_chip.oc |= CHIP_IS_OMAP4430ES1;
348 break; 348 break;
349 case 1: 349 case 1:
350 default:
350 omap_revision = OMAP4430_REV_ES2_0; 351 omap_revision = OMAP4430_REV_ES2_0;
351 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 352 omap_chip.oc |= CHIP_IS_OMAP4430ES2;
353 }
354 break;
355 case 0xb95c:
356 switch (rev) {
357 case 3:
358 omap_revision = OMAP4430_REV_ES2_1;
359 omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
352 break; 360 break;
361 case 4:
353 default: 362 default:
354 omap_revision = OMAP4430_REV_ES2_0; 363 omap_revision = OMAP4430_REV_ES2_2;
355 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 364 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
356 } 365 }
357 break; 366 break;
358 default: 367 default:
359 /* Unknown default to latest silicon rev as default*/ 368 /* Unknown default to latest silicon rev as default */
360 omap_revision = OMAP4430_REV_ES2_0; 369 omap_revision = OMAP4430_REV_ES2_2;
361 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 370 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
362 } 371 }
363 372
364 pr_info("OMAP%04x ES%d.0\n", 373 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
365 omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); 374 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
366} 375}
367 376
368#define OMAP3_SHOW_FEATURE(feat) \ 377#define OMAP3_SHOW_FEATURE(feat) \
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 03f71ec3cd82..441e79d043a7 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -30,7 +30,6 @@
30 30
31#include <plat/sram.h> 31#include <plat/sram.h>
32#include <plat/sdrc.h> 32#include <plat/sdrc.h>
33#include <plat/gpmc.h>
34#include <plat/serial.h> 33#include <plat/serial.h>
35 34
36#include "clock2xxx.h" 35#include "clock2xxx.h"
@@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
422 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 421 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
423 _omap2_init_reprogram_sdrc(); 422 _omap2_init_reprogram_sdrc();
424 } 423 }
425 gpmc_init();
426 424
427 omap_irq_base_init(); 425 omap_irq_base_init();
428} 426}
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 14ee686b6492..adb083e41acd 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -145,35 +145,32 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on)
145 145
146static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) 146static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
147{ 147{
148 int i;
149 u32 stat, da; 148 u32 stat, da;
150 const char *err_msg[] = { 149 u32 errs = 0;
151 "tlb miss",
152 "translation fault",
153 "emulation miss",
154 "table walk fault",
155 "multi hit fault",
156 };
157 150
158 stat = iommu_read_reg(obj, MMU_IRQSTATUS); 151 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
159 stat &= MMU_IRQ_MASK; 152 stat &= MMU_IRQ_MASK;
160 if (!stat) 153 if (!stat) {
154 *ra = 0;
161 return 0; 155 return 0;
156 }
162 157
163 da = iommu_read_reg(obj, MMU_FAULT_AD); 158 da = iommu_read_reg(obj, MMU_FAULT_AD);
164 *ra = da; 159 *ra = da;
165 160
166 dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); 161 if (stat & MMU_IRQ_TLBMISS)
167 162 errs |= OMAP_IOMMU_ERR_TLB_MISS;
168 for (i = 0; i < ARRAY_SIZE(err_msg); i++) { 163 if (stat & MMU_IRQ_TRANSLATIONFAULT)
169 if (stat & (1 << i)) 164 errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
170 printk("%s ", err_msg[i]); 165 if (stat & MMU_IRQ_EMUMISS)
171 } 166 errs |= OMAP_IOMMU_ERR_EMU_MISS;
172 printk("\n"); 167 if (stat & MMU_IRQ_TABLEWALKFAULT)
173 168 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
169 if (stat & MMU_IRQ_MULTIHITFAULT)
170 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
174 iommu_write_reg(obj, stat, MMU_IRQSTATUS); 171 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
175 172
176 return stat; 173 return errs;
177} 174}
178 175
179static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) 176static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 29b9dc3917af..6e15e3d7c65e 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,12 +14,11 @@
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/pm_runtime.h>
17#include <plat/mailbox.h> 18#include <plat/mailbox.h>
18#include <mach/irqs.h> 19#include <mach/irqs.h>
19 20
20#define MAILBOX_REVISION 0x000 21#define MAILBOX_REVISION 0x000
21#define MAILBOX_SYSCONFIG 0x010
22#define MAILBOX_SYSSTATUS 0x014
23#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) 22#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
24#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) 23#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
25#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) 24#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
@@ -33,17 +32,6 @@
33#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) 32#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
34#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) 33#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
35 34
36/* SYSCONFIG: register bit definition */
37#define AUTOIDLE (1 << 0)
38#define SOFTRESET (1 << 1)
39#define SMARTIDLE (2 << 3)
40#define OMAP4_SOFTRESET (1 << 0)
41#define OMAP4_NOIDLE (1 << 2)
42#define OMAP4_SMARTIDLE (2 << 2)
43
44/* SYSSTATUS: register bit definition */
45#define RESETDONE (1 << 0)
46
47#define MBOX_REG_SIZE 0x120 35#define MBOX_REG_SIZE 0x120
48 36
49#define OMAP4_MBOX_REG_SIZE 0x130 37#define OMAP4_MBOX_REG_SIZE 0x130
@@ -70,8 +58,6 @@ struct omap_mbox2_priv {
70 unsigned long irqdisable; 58 unsigned long irqdisable;
71}; 59};
72 60
73static struct clk *mbox_ick_handle;
74
75static void omap2_mbox_enable_irq(struct omap_mbox *mbox, 61static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
76 omap_mbox_type_t irq); 62 omap_mbox_type_t irq);
77 63
@@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
89static int omap2_mbox_startup(struct omap_mbox *mbox) 75static int omap2_mbox_startup(struct omap_mbox *mbox)
90{ 76{
91 u32 l; 77 u32 l;
92 unsigned long timeout;
93 78
94 mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); 79 pm_runtime_enable(mbox->dev->parent);
95 if (IS_ERR(mbox_ick_handle)) { 80 pm_runtime_get_sync(mbox->dev->parent);
96 printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
97 PTR_ERR(mbox_ick_handle));
98 return PTR_ERR(mbox_ick_handle);
99 }
100 clk_enable(mbox_ick_handle);
101
102 if (cpu_is_omap44xx()) {
103 mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
104 timeout = jiffies + msecs_to_jiffies(20);
105 do {
106 l = mbox_read_reg(MAILBOX_SYSCONFIG);
107 if (!(l & OMAP4_SOFTRESET))
108 break;
109 } while (!time_after(jiffies, timeout));
110
111 if (l & OMAP4_SOFTRESET) {
112 pr_err("Can't take mailbox out of reset\n");
113 return -ENODEV;
114 }
115 } else {
116 mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
117 timeout = jiffies + msecs_to_jiffies(20);
118 do {
119 l = mbox_read_reg(MAILBOX_SYSSTATUS);
120 if (l & RESETDONE)
121 break;
122 } while (!time_after(jiffies, timeout));
123
124 if (!(l & RESETDONE)) {
125 pr_err("Can't take mailbox out of reset\n");
126 return -ENODEV;
127 }
128 }
129 81
130 l = mbox_read_reg(MAILBOX_REVISION); 82 l = mbox_read_reg(MAILBOX_REVISION);
131 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); 83 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
132 84
133 if (cpu_is_omap44xx())
134 l = OMAP4_SMARTIDLE;
135 else
136 l = SMARTIDLE | AUTOIDLE;
137 mbox_write_reg(l, MAILBOX_SYSCONFIG);
138
139 omap2_mbox_enable_irq(mbox, IRQ_RX); 85 omap2_mbox_enable_irq(mbox, IRQ_RX);
140 86
141 return 0; 87 return 0;
@@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
143 89
144static void omap2_mbox_shutdown(struct omap_mbox *mbox) 90static void omap2_mbox_shutdown(struct omap_mbox *mbox)
145{ 91{
146 clk_disable(mbox_ick_handle); 92 pm_runtime_put_sync(mbox->dev->parent);
147 clk_put(mbox_ick_handle); 93 pm_runtime_disable(mbox->dev->parent);
148 mbox_ick_handle = NULL;
149} 94}
150 95
151/* Mailbox FIFO handle functions */ 96/* Mailbox FIFO handle functions */
@@ -334,7 +279,7 @@ static struct omap_mbox mbox_iva_info = {
334 .priv = &omap2_mbox_iva_priv, 279 .priv = &omap2_mbox_iva_priv,
335}; 280};
336 281
337struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL }; 282struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
338#endif 283#endif
339 284
340#if defined(CONFIG_ARCH_OMAP4) 285#if defined(CONFIG_ARCH_OMAP4)
@@ -398,14 +343,14 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
398 else if (cpu_is_omap34xx()) { 343 else if (cpu_is_omap34xx()) {
399 list = omap3_mboxes; 344 list = omap3_mboxes;
400 345
401 list[0]->irq = platform_get_irq_byname(pdev, "dsp"); 346 list[0]->irq = platform_get_irq(pdev, 0);
402 } 347 }
403#endif 348#endif
404#if defined(CONFIG_ARCH_OMAP2) 349#if defined(CONFIG_ARCH_OMAP2)
405 else if (cpu_is_omap2430()) { 350 else if (cpu_is_omap2430()) {
406 list = omap2_mboxes; 351 list = omap2_mboxes;
407 352
408 list[0]->irq = platform_get_irq_byname(pdev, "dsp"); 353 list[0]->irq = platform_get_irq(pdev, 0);
409 } else if (cpu_is_omap2420()) { 354 } else if (cpu_is_omap2420()) {
410 list = omap2_mboxes; 355 list = omap2_mboxes;
411 356
@@ -417,8 +362,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
417 else if (cpu_is_omap44xx()) { 362 else if (cpu_is_omap44xx()) {
418 list = omap4_mboxes; 363 list = omap4_mboxes;
419 364
420 list[0]->irq = list[1]->irq = 365 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
421 platform_get_irq_byname(pdev, "mbox");
422 } 366 }
423#endif 367#endif
424 else { 368 else {
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 0526b758bdcc..565b9064a328 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -22,10 +22,11 @@
22#include <plat/dma.h> 22#include <plat/dma.h>
23#include <plat/cpu.h> 23#include <plat/cpu.h>
24#include <plat/mcbsp.h> 24#include <plat/mcbsp.h>
25#include <plat/omap_device.h>
26#include <linux/pm_runtime.h>
25 27
26#include "control.h" 28#include "control.h"
27 29
28
29/* McBSP internal signal muxing functions */ 30/* McBSP internal signal muxing functions */
30 31
31void omap2_mcbsp1_mux_clkr_src(u8 mux) 32void omap2_mcbsp1_mux_clkr_src(u8 mux)
@@ -83,7 +84,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
83 return -EINVAL; 84 return -EINVAL;
84 } 85 }
85 86
86 clk_disable(mcbsp->fclk); 87 pm_runtime_put_sync(mcbsp->dev);
87 88
88 r = clk_set_parent(mcbsp->fclk, fck_src); 89 r = clk_set_parent(mcbsp->fclk, fck_src);
89 if (IS_ERR_VALUE(r)) { 90 if (IS_ERR_VALUE(r)) {
@@ -93,7 +94,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
93 return -EINVAL; 94 return -EINVAL;
94 } 95 }
95 96
96 clk_enable(mcbsp->fclk); 97 pm_runtime_get_sync(mcbsp->dev);
97 98
98 clk_put(fck_src); 99 clk_put(fck_src);
99 100
@@ -101,196 +102,70 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
101} 102}
102EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); 103EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
103 104
104 105struct omap_device_pm_latency omap2_mcbsp_latency[] = {
105/* Platform data */
106
107#ifdef CONFIG_SOC_OMAP2420
108static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
109 { 106 {
110 .phys_base = OMAP24XX_MCBSP1_BASE, 107 .deactivate_func = omap_device_idle_hwmods,
111 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 108 .activate_func = omap_device_enable_hwmods,
112 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 109 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
113 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
114 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
115 },
116 {
117 .phys_base = OMAP24XX_MCBSP2_BASE,
118 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
119 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
120 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
121 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
122 }, 110 },
123}; 111};
124#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
125#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
126#else
127#define omap2420_mcbsp_pdata NULL
128#define OMAP2420_MCBSP_PDATA_SZ 0
129#define OMAP2420_MCBSP_REG_NUM 0
130#endif
131 112
132#ifdef CONFIG_SOC_OMAP2430 113static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
133static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { 114{
134 { 115 int id, count = 1;
135 .phys_base = OMAP24XX_MCBSP1_BASE, 116 char *name = "omap-mcbsp";
136 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 117 struct omap_hwmod *oh_device[2];
137 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 118 struct omap_mcbsp_platform_data *pdata = NULL;
138 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 119 struct omap_device *od;
139 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
140 },
141 {
142 .phys_base = OMAP24XX_MCBSP2_BASE,
143 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
144 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
145 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
146 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
147 },
148 {
149 .phys_base = OMAP2430_MCBSP3_BASE,
150 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
151 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
152 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
153 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
154 },
155 {
156 .phys_base = OMAP2430_MCBSP4_BASE,
157 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
158 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
159 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
160 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
161 },
162 {
163 .phys_base = OMAP2430_MCBSP5_BASE,
164 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
165 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
166 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
167 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
168 },
169};
170#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
171#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
172#else
173#define omap2430_mcbsp_pdata NULL
174#define OMAP2430_MCBSP_PDATA_SZ 0
175#define OMAP2430_MCBSP_REG_NUM 0
176#endif
177 120
178#ifdef CONFIG_ARCH_OMAP3 121 sscanf(oh->name, "mcbsp%d", &id);
179static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
180 {
181 .phys_base = OMAP34XX_MCBSP1_BASE,
182 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
183 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
184 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
185 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
186 .buffer_size = 0x80, /* The FIFO has 128 locations */
187 },
188 {
189 .phys_base = OMAP34XX_MCBSP2_BASE,
190 .phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
191 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
192 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
193 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
194 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
195 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
196 },
197 {
198 .phys_base = OMAP34XX_MCBSP3_BASE,
199 .phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
200 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
201 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
202 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
203 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
204 .buffer_size = 0x80, /* The FIFO has 128 locations */
205 },
206 {
207 .phys_base = OMAP34XX_MCBSP4_BASE,
208 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
209 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
210 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
211 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
212 .buffer_size = 0x80, /* The FIFO has 128 locations */
213 },
214 {
215 .phys_base = OMAP34XX_MCBSP5_BASE,
216 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
217 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
218 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
219 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
220 .buffer_size = 0x80, /* The FIFO has 128 locations */
221 },
222};
223#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
224#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
225#else
226#define omap34xx_mcbsp_pdata NULL
227#define OMAP34XX_MCBSP_PDATA_SZ 0
228#define OMAP34XX_MCBSP_REG_NUM 0
229#endif
230 122
231static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { 123 pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
232 { 124 if (!pdata) {
233 .phys_base = OMAP44XX_MCBSP1_BASE, 125 pr_err("%s: No memory for mcbsp\n", __func__);
234 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, 126 return -ENOMEM;
235 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, 127 }
236 .tx_irq = OMAP44XX_IRQ_MCBSP1, 128
237 }, 129 pdata->mcbsp_config_type = oh->class->rev;
238 { 130
239 .phys_base = OMAP44XX_MCBSP2_BASE, 131 if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
240 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, 132 if (id == 2)
241 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, 133 /* The FIFO has 1024 + 256 locations */
242 .tx_irq = OMAP44XX_IRQ_MCBSP2, 134 pdata->buffer_size = 0x500;
243 }, 135 else
244 { 136 /* The FIFO has 128 locations */
245 .phys_base = OMAP44XX_MCBSP3_BASE, 137 pdata->buffer_size = 0x80;
246 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, 138 }
247 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, 139
248 .tx_irq = OMAP44XX_IRQ_MCBSP3, 140 oh_device[0] = oh;
249 }, 141
250 { 142 if (oh->dev_attr) {
251 .phys_base = OMAP44XX_MCBSP4_BASE, 143 oh_device[1] = omap_hwmod_lookup((
252 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, 144 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
253 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, 145 count++;
254 .tx_irq = OMAP44XX_IRQ_MCBSP4, 146 }
255 }, 147 od = omap_device_build_ss(name, id, oh_device, count, pdata,
256}; 148 sizeof(*pdata), omap2_mcbsp_latency,
257#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) 149 ARRAY_SIZE(omap2_mcbsp_latency), false);
258#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 150 kfree(pdata);
151 if (IS_ERR(od)) {
152 pr_err("%s: Cant build omap_device for %s:%s.\n", __func__,
153 name, oh->name);
154 return PTR_ERR(od);
155 }
156 omap_mcbsp_count++;
157 return 0;
158}
259 159
260static int __init omap2_mcbsp_init(void) 160static int __init omap2_mcbsp_init(void)
261{ 161{
262 if (cpu_is_omap2420()) { 162 omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
263 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
264 omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
265 } else if (cpu_is_omap2430()) {
266 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
267 omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
268 } else if (cpu_is_omap34xx()) {
269 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
270 omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
271 } else if (cpu_is_omap44xx()) {
272 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
273 omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
274 }
275 163
276 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 164 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
277 GFP_KERNEL); 165 GFP_KERNEL);
278 if (!mcbsp_ptr) 166 if (!mcbsp_ptr)
279 return -ENOMEM; 167 return -ENOMEM;
280 168
281 if (cpu_is_omap2420())
282 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
283 OMAP2420_MCBSP_PDATA_SZ);
284 if (cpu_is_omap2430())
285 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
286 OMAP2430_MCBSP_PDATA_SZ);
287 if (cpu_is_omap34xx())
288 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
289 OMAP34XX_MCBSP_PDATA_SZ);
290 if (cpu_is_omap44xx())
291 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
292 OMAP44XX_MCBSP_PDATA_SZ);
293
294 return omap_mcbsp_init(); 169 return omap_mcbsp_init();
295} 170}
296arch_initcall(omap2_mcbsp_init); 171arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 98148b6c36e9..6c84659cf846 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -605,7 +605,7 @@ static void __init omap_mux_dbg_create_entry(
605 list_for_each_entry(e, &partition->muxmodes, node) { 605 list_for_each_entry(e, &partition->muxmodes, node) {
606 struct omap_mux *m = &e->mux; 606 struct omap_mux *m = &e->mux;
607 607
608 (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, 608 (void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
609 m, &omap_mux_dbg_signal_fops); 609 m, &omap_mux_dbg_signal_fops);
610 } 610 }
611} 611}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9e89a58711b7..e39772beaedd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod implementation for OMAP2/3/4 2 * omap_hwmod implementation for OMAP2/3/4
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * 5 *
6 * Paul Walmsley, Benoît Cousson, Kevin Hilman 6 * Paul Walmsley, Benoît Cousson, Kevin Hilman
7 * 7 *
@@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list);
162/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ 162/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
163static struct omap_hwmod *mpu_oh; 163static struct omap_hwmod *mpu_oh;
164 164
165/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */
166static u8 inited;
167
168 165
169/* Private functions */ 166/* Private functions */
170 167
@@ -460,14 +457,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
460 * will be accessed by a particular initiator (e.g., if a module will 457 * will be accessed by a particular initiator (e.g., if a module will
461 * be accessed by the IVA, there should be a sleepdep between the IVA 458 * be accessed by the IVA, there should be a sleepdep between the IVA
462 * initiator and the module). Only applies to modules in smart-idle 459 * initiator and the module). Only applies to modules in smart-idle
463 * mode. Returns -EINVAL upon error or passes along 460 * mode. If the clockdomain is marked as not needing autodeps, return
464 * clkdm_add_sleepdep() value upon success. 461 * 0 without doing anything. Otherwise, returns -EINVAL upon error or
462 * passes along clkdm_add_sleepdep() value upon success.
465 */ 463 */
466static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) 464static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
467{ 465{
468 if (!oh->_clk) 466 if (!oh->_clk)
469 return -EINVAL; 467 return -EINVAL;
470 468
469 if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
470 return 0;
471
471 return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); 472 return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
472} 473}
473 474
@@ -480,14 +481,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
480 * be accessed by a particular initiator (e.g., if a module will not 481 * be accessed by a particular initiator (e.g., if a module will not
481 * be accessed by the IVA, there should be no sleepdep between the IVA 482 * be accessed by the IVA, there should be no sleepdep between the IVA
482 * initiator and the module). Only applies to modules in smart-idle 483 * initiator and the module). Only applies to modules in smart-idle
483 * mode. Returns -EINVAL upon error or passes along 484 * mode. If the clockdomain is marked as not needing autodeps, return
484 * clkdm_del_sleepdep() value upon success. 485 * 0 without doing anything. Returns -EINVAL upon error or passes
486 * along clkdm_del_sleepdep() value upon success.
485 */ 487 */
486static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) 488static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
487{ 489{
488 if (!oh->_clk) 490 if (!oh->_clk)
489 return -EINVAL; 491 return -EINVAL;
490 492
493 if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
494 return 0;
495
491 return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); 496 return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
492} 497}
493 498
@@ -904,18 +909,16 @@ static struct omap_hwmod *_lookup(const char *name)
904 * @oh: struct omap_hwmod * 909 * @oh: struct omap_hwmod *
905 * @data: not used; pass NULL 910 * @data: not used; pass NULL
906 * 911 *
907 * Called by omap_hwmod_late_init() (after omap2_clk_init()). 912 * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
908 * Resolves all clock names embedded in the hwmod. Returns -EINVAL if 913 * Resolves all clock names embedded in the hwmod. Returns 0 on
909 * the omap_hwmod has not yet been registered or if the clocks have 914 * success, or a negative error code on failure.
910 * already been initialized, 0 on success, or a non-zero error on
911 * failure.
912 */ 915 */
913static int _init_clocks(struct omap_hwmod *oh, void *data) 916static int _init_clocks(struct omap_hwmod *oh, void *data)
914{ 917{
915 int ret = 0; 918 int ret = 0;
916 919
917 if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) 920 if (oh->_state != _HWMOD_STATE_REGISTERED)
918 return -EINVAL; 921 return 0;
919 922
920 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); 923 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
921 924
@@ -1288,6 +1291,42 @@ static int _idle(struct omap_hwmod *oh)
1288} 1291}
1289 1292
1290/** 1293/**
1294 * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
1295 * @oh: struct omap_hwmod *
1296 * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
1297 *
1298 * Sets the IP block's OCP autoidle bit in hardware, and updates our
1299 * local copy. Intended to be used by drivers that require
1300 * direct manipulation of the AUTOIDLE bits.
1301 * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
1302 * along the return value from _set_module_autoidle().
1303 *
1304 * Any users of this function should be scrutinized carefully.
1305 */
1306int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
1307{
1308 u32 v;
1309 int retval = 0;
1310 unsigned long flags;
1311
1312 if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
1313 return -EINVAL;
1314
1315 spin_lock_irqsave(&oh->_lock, flags);
1316
1317 v = oh->_sysc_cache;
1318
1319 retval = _set_module_autoidle(oh, autoidle, &v);
1320
1321 if (!retval)
1322 _write_sysconfig(v, oh);
1323
1324 spin_unlock_irqrestore(&oh->_lock, flags);
1325
1326 return retval;
1327}
1328
1329/**
1291 * _shutdown - shutdown an omap_hwmod 1330 * _shutdown - shutdown an omap_hwmod
1292 * @oh: struct omap_hwmod * 1331 * @oh: struct omap_hwmod *
1293 * 1332 *
@@ -1354,14 +1393,16 @@ static int _shutdown(struct omap_hwmod *oh)
1354 * @oh: struct omap_hwmod * 1393 * @oh: struct omap_hwmod *
1355 * 1394 *
1356 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh 1395 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
1357 * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the 1396 * OCP_SYSCONFIG register. Returns 0.
1358 * wrong state or returns 0.
1359 */ 1397 */
1360static int _setup(struct omap_hwmod *oh, void *data) 1398static int _setup(struct omap_hwmod *oh, void *data)
1361{ 1399{
1362 int i, r; 1400 int i, r;
1363 u8 postsetup_state; 1401 u8 postsetup_state;
1364 1402
1403 if (oh->_state != _HWMOD_STATE_CLKS_INITED)
1404 return 0;
1405
1365 /* Set iclk autoidle mode */ 1406 /* Set iclk autoidle mode */
1366 if (oh->slaves_cnt > 0) { 1407 if (oh->slaves_cnt > 0) {
1367 for (i = 0; i < oh->slaves_cnt; i++) { 1408 for (i = 0; i < oh->slaves_cnt; i++) {
@@ -1455,7 +1496,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
1455 */ 1496 */
1456static int __init _register(struct omap_hwmod *oh) 1497static int __init _register(struct omap_hwmod *oh)
1457{ 1498{
1458 int ret, ms_id; 1499 int ms_id;
1459 1500
1460 if (!oh || !oh->name || !oh->class || !oh->class->name || 1501 if (!oh || !oh->name || !oh->class || !oh->class->name ||
1461 (oh->_state != _HWMOD_STATE_UNKNOWN)) 1502 (oh->_state != _HWMOD_STATE_UNKNOWN))
@@ -1478,9 +1519,14 @@ static int __init _register(struct omap_hwmod *oh)
1478 1519
1479 oh->_state = _HWMOD_STATE_REGISTERED; 1520 oh->_state = _HWMOD_STATE_REGISTERED;
1480 1521
1481 ret = 0; 1522 /*
1523 * XXX Rather than doing a strcmp(), this should test a flag
1524 * set in the hwmod data, inserted by the autogenerator code.
1525 */
1526 if (!strcmp(oh->name, MPU_INITIATOR_NAME))
1527 mpu_oh = oh;
1482 1528
1483 return ret; 1529 return 0;
1484} 1530}
1485 1531
1486 1532
@@ -1583,38 +1629,30 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
1583 return ret; 1629 return ret;
1584} 1630}
1585 1631
1586
1587/** 1632/**
1588 * omap_hwmod_init - init omap_hwmod code and register hwmods 1633 * omap_hwmod_register - register an array of hwmods
1589 * @ohs: pointer to an array of omap_hwmods to register 1634 * @ohs: pointer to an array of omap_hwmods to register
1590 * 1635 *
1591 * Intended to be called early in boot before the clock framework is 1636 * Intended to be called early in boot before the clock framework is
1592 * initialized. If @ohs is not null, will register all omap_hwmods 1637 * initialized. If @ohs is not null, will register all omap_hwmods
1593 * listed in @ohs that are valid for this chip. Returns -EINVAL if 1638 * listed in @ohs that are valid for this chip. Returns 0.
1594 * omap_hwmod_init() has already been called or 0 otherwise.
1595 */ 1639 */
1596int __init omap_hwmod_init(struct omap_hwmod **ohs) 1640int __init omap_hwmod_register(struct omap_hwmod **ohs)
1597{ 1641{
1598 struct omap_hwmod *oh; 1642 int r, i;
1599 int r;
1600
1601 if (inited)
1602 return -EINVAL;
1603
1604 inited = 1;
1605 1643
1606 if (!ohs) 1644 if (!ohs)
1607 return 0; 1645 return 0;
1608 1646
1609 oh = *ohs; 1647 i = 0;
1610 while (oh) { 1648 do {
1611 if (omap_chip_is(oh->omap_chip)) { 1649 if (!omap_chip_is(ohs[i]->omap_chip))
1612 r = _register(oh); 1650 continue;
1613 WARN(r, "omap_hwmod: %s: _register returned " 1651
1614 "%d\n", oh->name, r); 1652 r = _register(ohs[i]);
1615 } 1653 WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
1616 oh = *++ohs; 1654 r);
1617 } 1655 } while (ohs[++i]);
1618 1656
1619 return 0; 1657 return 0;
1620} 1658}
@@ -1622,12 +1660,14 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs)
1622/* 1660/*
1623 * _populate_mpu_rt_base - populate the virtual address for a hwmod 1661 * _populate_mpu_rt_base - populate the virtual address for a hwmod
1624 * 1662 *
1625 * Must be called only from omap_hwmod_late_init so ioremap works properly. 1663 * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
1626 * Assumes the caller takes care of locking if needed. 1664 * Assumes the caller takes care of locking if needed.
1627 *
1628 */ 1665 */
1629static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) 1666static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
1630{ 1667{
1668 if (oh->_state != _HWMOD_STATE_REGISTERED)
1669 return 0;
1670
1631 if (oh->_int_flags & _HWMOD_NO_MPU_PORT) 1671 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1632 return 0; 1672 return 0;
1633 1673
@@ -1640,31 +1680,81 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
1640} 1680}
1641 1681
1642/** 1682/**
1643 * omap_hwmod_late_init - do some post-clock framework initialization 1683 * omap_hwmod_setup_one - set up a single hwmod
1684 * @oh_name: const char * name of the already-registered hwmod to set up
1685 *
1686 * Must be called after omap2_clk_init(). Resolves the struct clk
1687 * names to struct clk pointers for each registered omap_hwmod. Also
1688 * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon
1689 * success.
1690 */
1691int __init omap_hwmod_setup_one(const char *oh_name)
1692{
1693 struct omap_hwmod *oh;
1694 int r;
1695
1696 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
1697
1698 if (!mpu_oh) {
1699 pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
1700 oh_name, MPU_INITIATOR_NAME);
1701 return -EINVAL;
1702 }
1703
1704 oh = _lookup(oh_name);
1705 if (!oh) {
1706 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
1707 return -EINVAL;
1708 }
1709
1710 if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
1711 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
1712
1713 r = _populate_mpu_rt_base(oh, NULL);
1714 if (IS_ERR_VALUE(r)) {
1715 WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
1716 return -EINVAL;
1717 }
1718
1719 r = _init_clocks(oh, NULL);
1720 if (IS_ERR_VALUE(r)) {
1721 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
1722 return -EINVAL;
1723 }
1724
1725 _setup(oh, NULL);
1726
1727 return 0;
1728}
1729
1730/**
1731 * omap_hwmod_setup - do some post-clock framework initialization
1644 * 1732 *
1645 * Must be called after omap2_clk_init(). Resolves the struct clk names 1733 * Must be called after omap2_clk_init(). Resolves the struct clk names
1646 * to struct clk pointers for each registered omap_hwmod. Also calls 1734 * to struct clk pointers for each registered omap_hwmod. Also calls
1647 * _setup() on each hwmod. Returns 0. 1735 * _setup() on each hwmod. Returns 0 upon success.
1648 */ 1736 */
1649static int __init omap_hwmod_late_init(void) 1737static int __init omap_hwmod_setup_all(void)
1650{ 1738{
1651 int r; 1739 int r;
1652 1740
1741 if (!mpu_oh) {
1742 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
1743 __func__, MPU_INITIATOR_NAME);
1744 return -EINVAL;
1745 }
1746
1653 r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); 1747 r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
1654 1748
1655 /* XXX check return value */
1656 r = omap_hwmod_for_each(_init_clocks, NULL); 1749 r = omap_hwmod_for_each(_init_clocks, NULL);
1657 WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); 1750 WARN(IS_ERR_VALUE(r),
1658 1751 "omap_hwmod: %s: _init_clocks failed\n", __func__);
1659 mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
1660 WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
1661 MPU_INITIATOR_NAME);
1662 1752
1663 omap_hwmod_for_each(_setup, NULL); 1753 omap_hwmod_for_each(_setup, NULL);
1664 1754
1665 return 0; 1755 return 0;
1666} 1756}
1667core_initcall(omap_hwmod_late_init); 1757core_initcall(omap_hwmod_setup_all);
1668 1758
1669/** 1759/**
1670 * omap_hwmod_enable - enable an omap_hwmod 1760 * omap_hwmod_enable - enable an omap_hwmod
@@ -1883,6 +1973,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1883 os = oh->slaves[i]; 1973 os = oh->slaves[i];
1884 1974
1885 for (j = 0; j < os->addr_cnt; j++) { 1975 for (j = 0; j < os->addr_cnt; j++) {
1976 (res + r)->name = (os->addr + j)->name;
1886 (res + r)->start = (os->addr + j)->pa_start; 1977 (res + r)->start = (os->addr + j)->pa_start;
1887 (res + r)->end = (os->addr + j)->pa_end; 1978 (res + r)->end = (os->addr + j)->pa_end;
1888 (res + r)->flags = IORESOURCE_MEM; 1979 (res + r)->flags = IORESOURCE_MEM;
@@ -2183,11 +2274,11 @@ int omap_hwmod_for_each_by_class(const char *classname,
2183 * @oh: struct omap_hwmod * 2274 * @oh: struct omap_hwmod *
2184 * @state: state that _setup() should leave the hwmod in 2275 * @state: state that _setup() should leave the hwmod in
2185 * 2276 *
2186 * Sets the hwmod state that @oh will enter at the end of _setup() (called by 2277 * Sets the hwmod state that @oh will enter at the end of _setup()
2187 * omap_hwmod_late_init()). Only valid to call between calls to 2278 * (called by omap_hwmod_setup_*()). Only valid to call between
2188 * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or 2279 * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns
2189 * -EINVAL if there is a problem with the arguments or if the hwmod is 2280 * 0 upon success or -EINVAL if there is a problem with the arguments
2190 * in the wrong state. 2281 * or if the hwmod is in the wrong state.
2191 */ 2282 */
2192int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) 2283int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
2193{ 2284{
@@ -2239,3 +2330,29 @@ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
2239 2330
2240 return ret; 2331 return ret;
2241} 2332}
2333
2334/**
2335 * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
2336 * @oh: struct omap_hwmod *
2337 *
2338 * Prevent the hwmod @oh from being reset during the setup process.
2339 * Intended for use by board-*.c files on boards with devices that
2340 * cannot tolerate being reset. Must be called before the hwmod has
2341 * been set up. Returns 0 upon success or negative error code upon
2342 * failure.
2343 */
2344int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
2345{
2346 if (!oh)
2347 return -EINVAL;
2348
2349 if (oh->_state != _HWMOD_STATE_REGISTERED) {
2350 pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
2351 oh->name);
2352 return -EINVAL;
2353 }
2354
2355 oh->flags |= HWMOD_INIT_NO_RESET;
2356
2357 return 0;
2358}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index f323c6bb22de..61e58bd27aec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -19,6 +19,7 @@
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcspi.h> 21#include <plat/mcspi.h>
22#include <plat/dmtimer.h>
22#include <plat/l3_2xxx.h> 23#include <plat/l3_2xxx.h>
23#include <plat/l4_2xxx.h> 24#include <plat/l4_2xxx.h>
24 25
@@ -109,6 +110,8 @@ static struct omap_hwmod omap2420_uart2_hwmod;
109static struct omap_hwmod omap2420_uart3_hwmod; 110static struct omap_hwmod omap2420_uart3_hwmod;
110static struct omap_hwmod omap2420_i2c1_hwmod; 111static struct omap_hwmod omap2420_i2c1_hwmod;
111static struct omap_hwmod omap2420_i2c2_hwmod; 112static struct omap_hwmod omap2420_i2c2_hwmod;
113static struct omap_hwmod omap2420_mcbsp1_hwmod;
114static struct omap_hwmod omap2420_mcbsp2_hwmod;
112 115
113/* l4 core -> mcspi1 interface */ 116/* l4 core -> mcspi1 interface */
114static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { 117static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
@@ -337,6 +340,625 @@ static struct omap_hwmod omap2420_iva_hwmod = {
337 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 340 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
338}; 341};
339 342
343/* Timer Common */
344static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
345 .rev_offs = 0x0000,
346 .sysc_offs = 0x0010,
347 .syss_offs = 0x0014,
348 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
349 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
350 SYSC_HAS_AUTOIDLE),
351 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
352 .sysc_fields = &omap_hwmod_sysc_type1,
353};
354
355static struct omap_hwmod_class omap2420_timer_hwmod_class = {
356 .name = "timer",
357 .sysc = &omap2420_timer_sysc,
358 .rev = OMAP_TIMER_IP_VERSION_1,
359};
360
361/* timer1 */
362static struct omap_hwmod omap2420_timer1_hwmod;
363static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
364 { .irq = 37, },
365};
366
367static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
368 {
369 .pa_start = 0x48028000,
370 .pa_end = 0x48028000 + SZ_1K - 1,
371 .flags = ADDR_TYPE_RT
372 },
373};
374
375/* l4_wkup -> timer1 */
376static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
377 .master = &omap2420_l4_wkup_hwmod,
378 .slave = &omap2420_timer1_hwmod,
379 .clk = "gpt1_ick",
380 .addr = omap2420_timer1_addrs,
381 .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
382 .user = OCP_USER_MPU | OCP_USER_SDMA,
383};
384
385/* timer1 slave port */
386static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
387 &omap2420_l4_wkup__timer1,
388};
389
390/* timer1 hwmod */
391static struct omap_hwmod omap2420_timer1_hwmod = {
392 .name = "timer1",
393 .mpu_irqs = omap2420_timer1_mpu_irqs,
394 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
395 .main_clk = "gpt1_fck",
396 .prcm = {
397 .omap2 = {
398 .prcm_reg_id = 1,
399 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
400 .module_offs = WKUP_MOD,
401 .idlest_reg_id = 1,
402 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
403 },
404 },
405 .slaves = omap2420_timer1_slaves,
406 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
407 .class = &omap2420_timer_hwmod_class,
408 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
409};
410
411/* timer2 */
412static struct omap_hwmod omap2420_timer2_hwmod;
413static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
414 { .irq = 38, },
415};
416
417static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
418 {
419 .pa_start = 0x4802a000,
420 .pa_end = 0x4802a000 + SZ_1K - 1,
421 .flags = ADDR_TYPE_RT
422 },
423};
424
425/* l4_core -> timer2 */
426static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
427 .master = &omap2420_l4_core_hwmod,
428 .slave = &omap2420_timer2_hwmod,
429 .clk = "gpt2_ick",
430 .addr = omap2420_timer2_addrs,
431 .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
432 .user = OCP_USER_MPU | OCP_USER_SDMA,
433};
434
435/* timer2 slave port */
436static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
437 &omap2420_l4_core__timer2,
438};
439
440/* timer2 hwmod */
441static struct omap_hwmod omap2420_timer2_hwmod = {
442 .name = "timer2",
443 .mpu_irqs = omap2420_timer2_mpu_irqs,
444 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
445 .main_clk = "gpt2_fck",
446 .prcm = {
447 .omap2 = {
448 .prcm_reg_id = 1,
449 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
450 .module_offs = CORE_MOD,
451 .idlest_reg_id = 1,
452 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
453 },
454 },
455 .slaves = omap2420_timer2_slaves,
456 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
457 .class = &omap2420_timer_hwmod_class,
458 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
459};
460
461/* timer3 */
462static struct omap_hwmod omap2420_timer3_hwmod;
463static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
464 { .irq = 39, },
465};
466
467static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
468 {
469 .pa_start = 0x48078000,
470 .pa_end = 0x48078000 + SZ_1K - 1,
471 .flags = ADDR_TYPE_RT
472 },
473};
474
475/* l4_core -> timer3 */
476static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
477 .master = &omap2420_l4_core_hwmod,
478 .slave = &omap2420_timer3_hwmod,
479 .clk = "gpt3_ick",
480 .addr = omap2420_timer3_addrs,
481 .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
482 .user = OCP_USER_MPU | OCP_USER_SDMA,
483};
484
485/* timer3 slave port */
486static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
487 &omap2420_l4_core__timer3,
488};
489
490/* timer3 hwmod */
491static struct omap_hwmod omap2420_timer3_hwmod = {
492 .name = "timer3",
493 .mpu_irqs = omap2420_timer3_mpu_irqs,
494 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
495 .main_clk = "gpt3_fck",
496 .prcm = {
497 .omap2 = {
498 .prcm_reg_id = 1,
499 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
500 .module_offs = CORE_MOD,
501 .idlest_reg_id = 1,
502 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
503 },
504 },
505 .slaves = omap2420_timer3_slaves,
506 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
507 .class = &omap2420_timer_hwmod_class,
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
509};
510
511/* timer4 */
512static struct omap_hwmod omap2420_timer4_hwmod;
513static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
514 { .irq = 40, },
515};
516
517static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
518 {
519 .pa_start = 0x4807a000,
520 .pa_end = 0x4807a000 + SZ_1K - 1,
521 .flags = ADDR_TYPE_RT
522 },
523};
524
525/* l4_core -> timer4 */
526static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
527 .master = &omap2420_l4_core_hwmod,
528 .slave = &omap2420_timer4_hwmod,
529 .clk = "gpt4_ick",
530 .addr = omap2420_timer4_addrs,
531 .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
532 .user = OCP_USER_MPU | OCP_USER_SDMA,
533};
534
535/* timer4 slave port */
536static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
537 &omap2420_l4_core__timer4,
538};
539
540/* timer4 hwmod */
541static struct omap_hwmod omap2420_timer4_hwmod = {
542 .name = "timer4",
543 .mpu_irqs = omap2420_timer4_mpu_irqs,
544 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
545 .main_clk = "gpt4_fck",
546 .prcm = {
547 .omap2 = {
548 .prcm_reg_id = 1,
549 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
550 .module_offs = CORE_MOD,
551 .idlest_reg_id = 1,
552 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
553 },
554 },
555 .slaves = omap2420_timer4_slaves,
556 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
557 .class = &omap2420_timer_hwmod_class,
558 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
559};
560
561/* timer5 */
562static struct omap_hwmod omap2420_timer5_hwmod;
563static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
564 { .irq = 41, },
565};
566
567static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
568 {
569 .pa_start = 0x4807c000,
570 .pa_end = 0x4807c000 + SZ_1K - 1,
571 .flags = ADDR_TYPE_RT
572 },
573};
574
575/* l4_core -> timer5 */
576static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
577 .master = &omap2420_l4_core_hwmod,
578 .slave = &omap2420_timer5_hwmod,
579 .clk = "gpt5_ick",
580 .addr = omap2420_timer5_addrs,
581 .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
582 .user = OCP_USER_MPU | OCP_USER_SDMA,
583};
584
585/* timer5 slave port */
586static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
587 &omap2420_l4_core__timer5,
588};
589
590/* timer5 hwmod */
591static struct omap_hwmod omap2420_timer5_hwmod = {
592 .name = "timer5",
593 .mpu_irqs = omap2420_timer5_mpu_irqs,
594 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
595 .main_clk = "gpt5_fck",
596 .prcm = {
597 .omap2 = {
598 .prcm_reg_id = 1,
599 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
600 .module_offs = CORE_MOD,
601 .idlest_reg_id = 1,
602 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
603 },
604 },
605 .slaves = omap2420_timer5_slaves,
606 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
607 .class = &omap2420_timer_hwmod_class,
608 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
609};
610
611
612/* timer6 */
613static struct omap_hwmod omap2420_timer6_hwmod;
614static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
615 { .irq = 42, },
616};
617
618static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
619 {
620 .pa_start = 0x4807e000,
621 .pa_end = 0x4807e000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624};
625
626/* l4_core -> timer6 */
627static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
628 .master = &omap2420_l4_core_hwmod,
629 .slave = &omap2420_timer6_hwmod,
630 .clk = "gpt6_ick",
631 .addr = omap2420_timer6_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
634};
635
636/* timer6 slave port */
637static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
638 &omap2420_l4_core__timer6,
639};
640
641/* timer6 hwmod */
642static struct omap_hwmod omap2420_timer6_hwmod = {
643 .name = "timer6",
644 .mpu_irqs = omap2420_timer6_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
646 .main_clk = "gpt6_fck",
647 .prcm = {
648 .omap2 = {
649 .prcm_reg_id = 1,
650 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
651 .module_offs = CORE_MOD,
652 .idlest_reg_id = 1,
653 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
654 },
655 },
656 .slaves = omap2420_timer6_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
658 .class = &omap2420_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
660};
661
662/* timer7 */
663static struct omap_hwmod omap2420_timer7_hwmod;
664static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
665 { .irq = 43, },
666};
667
668static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
669 {
670 .pa_start = 0x48080000,
671 .pa_end = 0x48080000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674};
675
676/* l4_core -> timer7 */
677static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
678 .master = &omap2420_l4_core_hwmod,
679 .slave = &omap2420_timer7_hwmod,
680 .clk = "gpt7_ick",
681 .addr = omap2420_timer7_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
684};
685
686/* timer7 slave port */
687static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
688 &omap2420_l4_core__timer7,
689};
690
691/* timer7 hwmod */
692static struct omap_hwmod omap2420_timer7_hwmod = {
693 .name = "timer7",
694 .mpu_irqs = omap2420_timer7_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
696 .main_clk = "gpt7_fck",
697 .prcm = {
698 .omap2 = {
699 .prcm_reg_id = 1,
700 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
701 .module_offs = CORE_MOD,
702 .idlest_reg_id = 1,
703 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
704 },
705 },
706 .slaves = omap2420_timer7_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
708 .class = &omap2420_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
710};
711
712/* timer8 */
713static struct omap_hwmod omap2420_timer8_hwmod;
714static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
715 { .irq = 44, },
716};
717
718static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
719 {
720 .pa_start = 0x48082000,
721 .pa_end = 0x48082000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724};
725
726/* l4_core -> timer8 */
727static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
728 .master = &omap2420_l4_core_hwmod,
729 .slave = &omap2420_timer8_hwmod,
730 .clk = "gpt8_ick",
731 .addr = omap2420_timer8_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA,
734};
735
736/* timer8 slave port */
737static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
738 &omap2420_l4_core__timer8,
739};
740
741/* timer8 hwmod */
742static struct omap_hwmod omap2420_timer8_hwmod = {
743 .name = "timer8",
744 .mpu_irqs = omap2420_timer8_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
746 .main_clk = "gpt8_fck",
747 .prcm = {
748 .omap2 = {
749 .prcm_reg_id = 1,
750 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
751 .module_offs = CORE_MOD,
752 .idlest_reg_id = 1,
753 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
754 },
755 },
756 .slaves = omap2420_timer8_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
758 .class = &omap2420_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
760};
761
762/* timer9 */
763static struct omap_hwmod omap2420_timer9_hwmod;
764static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
765 { .irq = 45, },
766};
767
768static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
769 {
770 .pa_start = 0x48084000,
771 .pa_end = 0x48084000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774};
775
776/* l4_core -> timer9 */
777static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
778 .master = &omap2420_l4_core_hwmod,
779 .slave = &omap2420_timer9_hwmod,
780 .clk = "gpt9_ick",
781 .addr = omap2420_timer9_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA,
784};
785
786/* timer9 slave port */
787static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
788 &omap2420_l4_core__timer9,
789};
790
791/* timer9 hwmod */
792static struct omap_hwmod omap2420_timer9_hwmod = {
793 .name = "timer9",
794 .mpu_irqs = omap2420_timer9_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
796 .main_clk = "gpt9_fck",
797 .prcm = {
798 .omap2 = {
799 .prcm_reg_id = 1,
800 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
801 .module_offs = CORE_MOD,
802 .idlest_reg_id = 1,
803 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
804 },
805 },
806 .slaves = omap2420_timer9_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
808 .class = &omap2420_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
810};
811
812/* timer10 */
813static struct omap_hwmod omap2420_timer10_hwmod;
814static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
815 { .irq = 46, },
816};
817
818static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
819 {
820 .pa_start = 0x48086000,
821 .pa_end = 0x48086000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824};
825
826/* l4_core -> timer10 */
827static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
828 .master = &omap2420_l4_core_hwmod,
829 .slave = &omap2420_timer10_hwmod,
830 .clk = "gpt10_ick",
831 .addr = omap2420_timer10_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA,
834};
835
836/* timer10 slave port */
837static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
838 &omap2420_l4_core__timer10,
839};
840
841/* timer10 hwmod */
842static struct omap_hwmod omap2420_timer10_hwmod = {
843 .name = "timer10",
844 .mpu_irqs = omap2420_timer10_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
846 .main_clk = "gpt10_fck",
847 .prcm = {
848 .omap2 = {
849 .prcm_reg_id = 1,
850 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
851 .module_offs = CORE_MOD,
852 .idlest_reg_id = 1,
853 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
854 },
855 },
856 .slaves = omap2420_timer10_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
858 .class = &omap2420_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
860};
861
862/* timer11 */
863static struct omap_hwmod omap2420_timer11_hwmod;
864static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
865 { .irq = 47, },
866};
867
868static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
869 {
870 .pa_start = 0x48088000,
871 .pa_end = 0x48088000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874};
875
876/* l4_core -> timer11 */
877static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
878 .master = &omap2420_l4_core_hwmod,
879 .slave = &omap2420_timer11_hwmod,
880 .clk = "gpt11_ick",
881 .addr = omap2420_timer11_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA,
884};
885
886/* timer11 slave port */
887static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
888 &omap2420_l4_core__timer11,
889};
890
891/* timer11 hwmod */
892static struct omap_hwmod omap2420_timer11_hwmod = {
893 .name = "timer11",
894 .mpu_irqs = omap2420_timer11_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
896 .main_clk = "gpt11_fck",
897 .prcm = {
898 .omap2 = {
899 .prcm_reg_id = 1,
900 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
901 .module_offs = CORE_MOD,
902 .idlest_reg_id = 1,
903 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
904 },
905 },
906 .slaves = omap2420_timer11_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
908 .class = &omap2420_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
910};
911
912/* timer12 */
913static struct omap_hwmod omap2420_timer12_hwmod;
914static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
915 { .irq = 48, },
916};
917
918static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
919 {
920 .pa_start = 0x4808a000,
921 .pa_end = 0x4808a000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924};
925
926/* l4_core -> timer12 */
927static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
928 .master = &omap2420_l4_core_hwmod,
929 .slave = &omap2420_timer12_hwmod,
930 .clk = "gpt12_ick",
931 .addr = omap2420_timer12_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA,
934};
935
936/* timer12 slave port */
937static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
938 &omap2420_l4_core__timer12,
939};
940
941/* timer12 hwmod */
942static struct omap_hwmod omap2420_timer12_hwmod = {
943 .name = "timer12",
944 .mpu_irqs = omap2420_timer12_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
946 .main_clk = "gpt12_fck",
947 .prcm = {
948 .omap2 = {
949 .prcm_reg_id = 1,
950 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
951 .module_offs = CORE_MOD,
952 .idlest_reg_id = 1,
953 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
954 },
955 },
956 .slaves = omap2420_timer12_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
958 .class = &omap2420_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
960};
961
340/* l4_wkup -> wd_timer2 */ 962/* l4_wkup -> wd_timer2 */
341static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { 963static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
342 { 964 {
@@ -788,6 +1410,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
788 .flags = OMAP_FIREWALL_L4, 1410 .flags = OMAP_FIREWALL_L4,
789 } 1411 }
790 }, 1412 },
1413 .flags = OCPIF_SWSUP_IDLE,
791 .user = OCP_USER_MPU | OCP_USER_SDMA, 1414 .user = OCP_USER_MPU | OCP_USER_SDMA,
792}; 1415};
793 1416
@@ -1208,6 +1831,76 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
1208}; 1831};
1209 1832
1210/* 1833/*
1834 * 'mailbox' class
1835 * mailbox module allowing communication between the on-chip processors
1836 * using a queued mailbox-interrupt mechanism.
1837 */
1838
1839static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1840 .rev_offs = 0x000,
1841 .sysc_offs = 0x010,
1842 .syss_offs = 0x014,
1843 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1844 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1845 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1846 .sysc_fields = &omap_hwmod_sysc_type1,
1847};
1848
1849static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1850 .name = "mailbox",
1851 .sysc = &omap2420_mailbox_sysc,
1852};
1853
1854/* mailbox */
1855static struct omap_hwmod omap2420_mailbox_hwmod;
1856static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1857 { .name = "dsp", .irq = 26 },
1858 { .name = "iva", .irq = 34 },
1859};
1860
1861static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
1862 {
1863 .pa_start = 0x48094000,
1864 .pa_end = 0x480941ff,
1865 .flags = ADDR_TYPE_RT,
1866 },
1867};
1868
1869/* l4_core -> mailbox */
1870static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1871 .master = &omap2420_l4_core_hwmod,
1872 .slave = &omap2420_mailbox_hwmod,
1873 .addr = omap2420_mailbox_addrs,
1874 .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
1875 .user = OCP_USER_MPU | OCP_USER_SDMA,
1876};
1877
1878/* mailbox slave ports */
1879static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1880 &omap2420_l4_core__mailbox,
1881};
1882
1883static struct omap_hwmod omap2420_mailbox_hwmod = {
1884 .name = "mailbox",
1885 .class = &omap2420_mailbox_hwmod_class,
1886 .mpu_irqs = omap2420_mailbox_irqs,
1887 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
1888 .main_clk = "mailboxes_ick",
1889 .prcm = {
1890 .omap2 = {
1891 .prcm_reg_id = 1,
1892 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1893 .module_offs = CORE_MOD,
1894 .idlest_reg_id = 1,
1895 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1896 },
1897 },
1898 .slaves = omap2420_mailbox_slaves,
1899 .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
1900 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1901};
1902
1903/*
1211 * 'mcspi' class 1904 * 'mcspi' class
1212 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1905 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1213 * bus 1906 * bus
@@ -1320,12 +2013,149 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
1320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 2013 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1321}; 2014};
1322 2015
2016/*
2017 * 'mcbsp' class
2018 * multi channel buffered serial port controller
2019 */
2020
2021static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
2022 .name = "mcbsp",
2023};
2024
2025/* mcbsp1 */
2026static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
2027 { .name = "tx", .irq = 59 },
2028 { .name = "rx", .irq = 60 },
2029};
2030
2031static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
2032 { .name = "rx", .dma_req = 32 },
2033 { .name = "tx", .dma_req = 31 },
2034};
2035
2036static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
2037 {
2038 .name = "mpu",
2039 .pa_start = 0x48074000,
2040 .pa_end = 0x480740ff,
2041 .flags = ADDR_TYPE_RT
2042 },
2043};
2044
2045/* l4_core -> mcbsp1 */
2046static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
2047 .master = &omap2420_l4_core_hwmod,
2048 .slave = &omap2420_mcbsp1_hwmod,
2049 .clk = "mcbsp1_ick",
2050 .addr = omap2420_mcbsp1_addrs,
2051 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
2052 .user = OCP_USER_MPU | OCP_USER_SDMA,
2053};
2054
2055/* mcbsp1 slave ports */
2056static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
2057 &omap2420_l4_core__mcbsp1,
2058};
2059
2060static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2061 .name = "mcbsp1",
2062 .class = &omap2420_mcbsp_hwmod_class,
2063 .mpu_irqs = omap2420_mcbsp1_irqs,
2064 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs),
2065 .sdma_reqs = omap2420_mcbsp1_sdma_chs,
2066 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
2067 .main_clk = "mcbsp1_fck",
2068 .prcm = {
2069 .omap2 = {
2070 .prcm_reg_id = 1,
2071 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2072 .module_offs = CORE_MOD,
2073 .idlest_reg_id = 1,
2074 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2075 },
2076 },
2077 .slaves = omap2420_mcbsp1_slaves,
2078 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
2079 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2080};
2081
2082/* mcbsp2 */
2083static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
2084 { .name = "tx", .irq = 62 },
2085 { .name = "rx", .irq = 63 },
2086};
2087
2088static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
2089 { .name = "rx", .dma_req = 34 },
2090 { .name = "tx", .dma_req = 33 },
2091};
2092
2093static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
2094 {
2095 .name = "mpu",
2096 .pa_start = 0x48076000,
2097 .pa_end = 0x480760ff,
2098 .flags = ADDR_TYPE_RT
2099 },
2100};
2101
2102/* l4_core -> mcbsp2 */
2103static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
2104 .master = &omap2420_l4_core_hwmod,
2105 .slave = &omap2420_mcbsp2_hwmod,
2106 .clk = "mcbsp2_ick",
2107 .addr = omap2420_mcbsp2_addrs,
2108 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
2109 .user = OCP_USER_MPU | OCP_USER_SDMA,
2110};
2111
2112/* mcbsp2 slave ports */
2113static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
2114 &omap2420_l4_core__mcbsp2,
2115};
2116
2117static struct omap_hwmod omap2420_mcbsp2_hwmod = {
2118 .name = "mcbsp2",
2119 .class = &omap2420_mcbsp_hwmod_class,
2120 .mpu_irqs = omap2420_mcbsp2_irqs,
2121 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs),
2122 .sdma_reqs = omap2420_mcbsp2_sdma_chs,
2123 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
2124 .main_clk = "mcbsp2_fck",
2125 .prcm = {
2126 .omap2 = {
2127 .prcm_reg_id = 1,
2128 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2129 .module_offs = CORE_MOD,
2130 .idlest_reg_id = 1,
2131 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2132 },
2133 },
2134 .slaves = omap2420_mcbsp2_slaves,
2135 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
2136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2137};
2138
1323static __initdata struct omap_hwmod *omap2420_hwmods[] = { 2139static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1324 &omap2420_l3_main_hwmod, 2140 &omap2420_l3_main_hwmod,
1325 &omap2420_l4_core_hwmod, 2141 &omap2420_l4_core_hwmod,
1326 &omap2420_l4_wkup_hwmod, 2142 &omap2420_l4_wkup_hwmod,
1327 &omap2420_mpu_hwmod, 2143 &omap2420_mpu_hwmod,
1328 &omap2420_iva_hwmod, 2144 &omap2420_iva_hwmod,
2145
2146 &omap2420_timer1_hwmod,
2147 &omap2420_timer2_hwmod,
2148 &omap2420_timer3_hwmod,
2149 &omap2420_timer4_hwmod,
2150 &omap2420_timer5_hwmod,
2151 &omap2420_timer6_hwmod,
2152 &omap2420_timer7_hwmod,
2153 &omap2420_timer8_hwmod,
2154 &omap2420_timer9_hwmod,
2155 &omap2420_timer10_hwmod,
2156 &omap2420_timer11_hwmod,
2157 &omap2420_timer12_hwmod,
2158
1329 &omap2420_wd_timer2_hwmod, 2159 &omap2420_wd_timer2_hwmod,
1330 &omap2420_uart1_hwmod, 2160 &omap2420_uart1_hwmod,
1331 &omap2420_uart2_hwmod, 2161 &omap2420_uart2_hwmod,
@@ -1348,6 +2178,13 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1348 /* dma_system class*/ 2178 /* dma_system class*/
1349 &omap2420_dma_system_hwmod, 2179 &omap2420_dma_system_hwmod,
1350 2180
2181 /* mailbox class */
2182 &omap2420_mailbox_hwmod,
2183
2184 /* mcbsp class */
2185 &omap2420_mcbsp1_hwmod,
2186 &omap2420_mcbsp2_hwmod,
2187
1351 /* mcspi class */ 2188 /* mcspi class */
1352 &omap2420_mcspi1_hwmod, 2189 &omap2420_mcspi1_hwmod,
1353 &omap2420_mcspi2_hwmod, 2190 &omap2420_mcspi2_hwmod,
@@ -1356,5 +2193,5 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1356 2193
1357int __init omap2420_hwmod_init(void) 2194int __init omap2420_hwmod_init(void)
1358{ 2195{
1359 return omap_hwmod_init(omap2420_hwmods); 2196 return omap_hwmod_register(omap2420_hwmods);
1360} 2197}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index de0015d38433..490789a6bed0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,7 +18,10 @@
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcbsp.h>
21#include <plat/mcspi.h> 22#include <plat/mcspi.h>
23#include <plat/dmtimer.h>
24#include <plat/mmc.h>
22#include <plat/l3_2xxx.h> 25#include <plat/l3_2xxx.h>
23 26
24#include "omap_hwmod_common_data.h" 27#include "omap_hwmod_common_data.h"
@@ -51,9 +54,16 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
51static struct omap_hwmod omap2430_gpio4_hwmod; 54static struct omap_hwmod omap2430_gpio4_hwmod;
52static struct omap_hwmod omap2430_gpio5_hwmod; 55static struct omap_hwmod omap2430_gpio5_hwmod;
53static struct omap_hwmod omap2430_dma_system_hwmod; 56static struct omap_hwmod omap2430_dma_system_hwmod;
57static struct omap_hwmod omap2430_mcbsp1_hwmod;
58static struct omap_hwmod omap2430_mcbsp2_hwmod;
59static struct omap_hwmod omap2430_mcbsp3_hwmod;
60static struct omap_hwmod omap2430_mcbsp4_hwmod;
61static struct omap_hwmod omap2430_mcbsp5_hwmod;
54static struct omap_hwmod omap2430_mcspi1_hwmod; 62static struct omap_hwmod omap2430_mcspi1_hwmod;
55static struct omap_hwmod omap2430_mcspi2_hwmod; 63static struct omap_hwmod omap2430_mcspi2_hwmod;
56static struct omap_hwmod omap2430_mcspi3_hwmod; 64static struct omap_hwmod omap2430_mcspi3_hwmod;
65static struct omap_hwmod omap2430_mmc1_hwmod;
66static struct omap_hwmod omap2430_mmc2_hwmod;
57 67
58/* L3 -> L4_CORE interface */ 68/* L3 -> L4_CORE interface */
59static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { 69static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -250,6 +260,42 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
250 &omap2430_l4_core__usbhsotg, 260 &omap2430_l4_core__usbhsotg,
251}; 261};
252 262
263/* L4 CORE -> MMC1 interface */
264static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
265 {
266 .pa_start = 0x4809c000,
267 .pa_end = 0x4809c1ff,
268 .flags = ADDR_TYPE_RT,
269 },
270};
271
272static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
273 .master = &omap2430_l4_core_hwmod,
274 .slave = &omap2430_mmc1_hwmod,
275 .clk = "mmchs1_ick",
276 .addr = omap2430_mmc1_addr_space,
277 .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
279};
280
281/* L4 CORE -> MMC2 interface */
282static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
283 {
284 .pa_start = 0x480b4000,
285 .pa_end = 0x480b41ff,
286 .flags = ADDR_TYPE_RT,
287 },
288};
289
290static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
291 .master = &omap2430_l4_core_hwmod,
292 .slave = &omap2430_mmc2_hwmod,
293 .addr = omap2430_mmc2_addr_space,
294 .clk = "mmchs2_ick",
295 .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space),
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297};
298
253/* Slave interfaces on the L4_CORE interconnect */ 299/* Slave interfaces on the L4_CORE interconnect */
254static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { 300static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
255 &omap2430_l3_main__l4_core, 301 &omap2430_l3_main__l4_core,
@@ -258,6 +304,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
258/* Master interfaces on the L4_CORE interconnect */ 304/* Master interfaces on the L4_CORE interconnect */
259static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { 305static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
260 &omap2430_l4_core__l4_wkup, 306 &omap2430_l4_core__l4_wkup,
307 &omap2430_l4_core__mmc1,
308 &omap2430_l4_core__mmc2,
261}; 309};
262 310
263/* L4 CORE */ 311/* L4 CORE */
@@ -393,6 +441,624 @@ static struct omap_hwmod omap2430_iva_hwmod = {
393 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
394}; 442};
395 443
444/* Timer Common */
445static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
446 .rev_offs = 0x0000,
447 .sysc_offs = 0x0010,
448 .syss_offs = 0x0014,
449 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
450 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
451 SYSC_HAS_AUTOIDLE),
452 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454};
455
456static struct omap_hwmod_class omap2430_timer_hwmod_class = {
457 .name = "timer",
458 .sysc = &omap2430_timer_sysc,
459 .rev = OMAP_TIMER_IP_VERSION_1,
460};
461
462/* timer1 */
463static struct omap_hwmod omap2430_timer1_hwmod;
464static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
465 { .irq = 37, },
466};
467
468static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
469 {
470 .pa_start = 0x49018000,
471 .pa_end = 0x49018000 + SZ_1K - 1,
472 .flags = ADDR_TYPE_RT
473 },
474};
475
476/* l4_wkup -> timer1 */
477static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
478 .master = &omap2430_l4_wkup_hwmod,
479 .slave = &omap2430_timer1_hwmod,
480 .clk = "gpt1_ick",
481 .addr = omap2430_timer1_addrs,
482 .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
483 .user = OCP_USER_MPU | OCP_USER_SDMA,
484};
485
486/* timer1 slave port */
487static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
488 &omap2430_l4_wkup__timer1,
489};
490
491/* timer1 hwmod */
492static struct omap_hwmod omap2430_timer1_hwmod = {
493 .name = "timer1",
494 .mpu_irqs = omap2430_timer1_mpu_irqs,
495 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
496 .main_clk = "gpt1_fck",
497 .prcm = {
498 .omap2 = {
499 .prcm_reg_id = 1,
500 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
501 .module_offs = WKUP_MOD,
502 .idlest_reg_id = 1,
503 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
504 },
505 },
506 .slaves = omap2430_timer1_slaves,
507 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
508 .class = &omap2430_timer_hwmod_class,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
510};
511
512/* timer2 */
513static struct omap_hwmod omap2430_timer2_hwmod;
514static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
515 { .irq = 38, },
516};
517
518static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
519 {
520 .pa_start = 0x4802a000,
521 .pa_end = 0x4802a000 + SZ_1K - 1,
522 .flags = ADDR_TYPE_RT
523 },
524};
525
526/* l4_core -> timer2 */
527static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
528 .master = &omap2430_l4_core_hwmod,
529 .slave = &omap2430_timer2_hwmod,
530 .clk = "gpt2_ick",
531 .addr = omap2430_timer2_addrs,
532 .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
533 .user = OCP_USER_MPU | OCP_USER_SDMA,
534};
535
536/* timer2 slave port */
537static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
538 &omap2430_l4_core__timer2,
539};
540
541/* timer2 hwmod */
542static struct omap_hwmod omap2430_timer2_hwmod = {
543 .name = "timer2",
544 .mpu_irqs = omap2430_timer2_mpu_irqs,
545 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
546 .main_clk = "gpt2_fck",
547 .prcm = {
548 .omap2 = {
549 .prcm_reg_id = 1,
550 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
551 .module_offs = CORE_MOD,
552 .idlest_reg_id = 1,
553 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
554 },
555 },
556 .slaves = omap2430_timer2_slaves,
557 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
558 .class = &omap2430_timer_hwmod_class,
559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
560};
561
562/* timer3 */
563static struct omap_hwmod omap2430_timer3_hwmod;
564static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
565 { .irq = 39, },
566};
567
568static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
569 {
570 .pa_start = 0x48078000,
571 .pa_end = 0x48078000 + SZ_1K - 1,
572 .flags = ADDR_TYPE_RT
573 },
574};
575
576/* l4_core -> timer3 */
577static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
578 .master = &omap2430_l4_core_hwmod,
579 .slave = &omap2430_timer3_hwmod,
580 .clk = "gpt3_ick",
581 .addr = omap2430_timer3_addrs,
582 .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
583 .user = OCP_USER_MPU | OCP_USER_SDMA,
584};
585
586/* timer3 slave port */
587static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
588 &omap2430_l4_core__timer3,
589};
590
591/* timer3 hwmod */
592static struct omap_hwmod omap2430_timer3_hwmod = {
593 .name = "timer3",
594 .mpu_irqs = omap2430_timer3_mpu_irqs,
595 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
596 .main_clk = "gpt3_fck",
597 .prcm = {
598 .omap2 = {
599 .prcm_reg_id = 1,
600 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
601 .module_offs = CORE_MOD,
602 .idlest_reg_id = 1,
603 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
604 },
605 },
606 .slaves = omap2430_timer3_slaves,
607 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
608 .class = &omap2430_timer_hwmod_class,
609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
610};
611
612/* timer4 */
613static struct omap_hwmod omap2430_timer4_hwmod;
614static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
615 { .irq = 40, },
616};
617
618static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
619 {
620 .pa_start = 0x4807a000,
621 .pa_end = 0x4807a000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624};
625
626/* l4_core -> timer4 */
627static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
628 .master = &omap2430_l4_core_hwmod,
629 .slave = &omap2430_timer4_hwmod,
630 .clk = "gpt4_ick",
631 .addr = omap2430_timer4_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA,
634};
635
636/* timer4 slave port */
637static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
638 &omap2430_l4_core__timer4,
639};
640
641/* timer4 hwmod */
642static struct omap_hwmod omap2430_timer4_hwmod = {
643 .name = "timer4",
644 .mpu_irqs = omap2430_timer4_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
646 .main_clk = "gpt4_fck",
647 .prcm = {
648 .omap2 = {
649 .prcm_reg_id = 1,
650 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
651 .module_offs = CORE_MOD,
652 .idlest_reg_id = 1,
653 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
654 },
655 },
656 .slaves = omap2430_timer4_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
658 .class = &omap2430_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
660};
661
662/* timer5 */
663static struct omap_hwmod omap2430_timer5_hwmod;
664static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
665 { .irq = 41, },
666};
667
668static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
669 {
670 .pa_start = 0x4807c000,
671 .pa_end = 0x4807c000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674};
675
676/* l4_core -> timer5 */
677static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
678 .master = &omap2430_l4_core_hwmod,
679 .slave = &omap2430_timer5_hwmod,
680 .clk = "gpt5_ick",
681 .addr = omap2430_timer5_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
684};
685
686/* timer5 slave port */
687static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
688 &omap2430_l4_core__timer5,
689};
690
691/* timer5 hwmod */
692static struct omap_hwmod omap2430_timer5_hwmod = {
693 .name = "timer5",
694 .mpu_irqs = omap2430_timer5_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
696 .main_clk = "gpt5_fck",
697 .prcm = {
698 .omap2 = {
699 .prcm_reg_id = 1,
700 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
701 .module_offs = CORE_MOD,
702 .idlest_reg_id = 1,
703 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
704 },
705 },
706 .slaves = omap2430_timer5_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
708 .class = &omap2430_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
710};
711
712/* timer6 */
713static struct omap_hwmod omap2430_timer6_hwmod;
714static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
715 { .irq = 42, },
716};
717
718static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
719 {
720 .pa_start = 0x4807e000,
721 .pa_end = 0x4807e000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724};
725
726/* l4_core -> timer6 */
727static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
728 .master = &omap2430_l4_core_hwmod,
729 .slave = &omap2430_timer6_hwmod,
730 .clk = "gpt6_ick",
731 .addr = omap2430_timer6_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA,
734};
735
736/* timer6 slave port */
737static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
738 &omap2430_l4_core__timer6,
739};
740
741/* timer6 hwmod */
742static struct omap_hwmod omap2430_timer6_hwmod = {
743 .name = "timer6",
744 .mpu_irqs = omap2430_timer6_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
746 .main_clk = "gpt6_fck",
747 .prcm = {
748 .omap2 = {
749 .prcm_reg_id = 1,
750 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
751 .module_offs = CORE_MOD,
752 .idlest_reg_id = 1,
753 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
754 },
755 },
756 .slaves = omap2430_timer6_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
758 .class = &omap2430_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
760};
761
762/* timer7 */
763static struct omap_hwmod omap2430_timer7_hwmod;
764static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
765 { .irq = 43, },
766};
767
768static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
769 {
770 .pa_start = 0x48080000,
771 .pa_end = 0x48080000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774};
775
776/* l4_core -> timer7 */
777static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
778 .master = &omap2430_l4_core_hwmod,
779 .slave = &omap2430_timer7_hwmod,
780 .clk = "gpt7_ick",
781 .addr = omap2430_timer7_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA,
784};
785
786/* timer7 slave port */
787static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
788 &omap2430_l4_core__timer7,
789};
790
791/* timer7 hwmod */
792static struct omap_hwmod omap2430_timer7_hwmod = {
793 .name = "timer7",
794 .mpu_irqs = omap2430_timer7_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
796 .main_clk = "gpt7_fck",
797 .prcm = {
798 .omap2 = {
799 .prcm_reg_id = 1,
800 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
801 .module_offs = CORE_MOD,
802 .idlest_reg_id = 1,
803 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
804 },
805 },
806 .slaves = omap2430_timer7_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
808 .class = &omap2430_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
810};
811
812/* timer8 */
813static struct omap_hwmod omap2430_timer8_hwmod;
814static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
815 { .irq = 44, },
816};
817
818static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
819 {
820 .pa_start = 0x48082000,
821 .pa_end = 0x48082000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824};
825
826/* l4_core -> timer8 */
827static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
828 .master = &omap2430_l4_core_hwmod,
829 .slave = &omap2430_timer8_hwmod,
830 .clk = "gpt8_ick",
831 .addr = omap2430_timer8_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA,
834};
835
836/* timer8 slave port */
837static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
838 &omap2430_l4_core__timer8,
839};
840
841/* timer8 hwmod */
842static struct omap_hwmod omap2430_timer8_hwmod = {
843 .name = "timer8",
844 .mpu_irqs = omap2430_timer8_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
846 .main_clk = "gpt8_fck",
847 .prcm = {
848 .omap2 = {
849 .prcm_reg_id = 1,
850 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
851 .module_offs = CORE_MOD,
852 .idlest_reg_id = 1,
853 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
854 },
855 },
856 .slaves = omap2430_timer8_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
858 .class = &omap2430_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
860};
861
862/* timer9 */
863static struct omap_hwmod omap2430_timer9_hwmod;
864static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
865 { .irq = 45, },
866};
867
868static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
869 {
870 .pa_start = 0x48084000,
871 .pa_end = 0x48084000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874};
875
876/* l4_core -> timer9 */
877static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
878 .master = &omap2430_l4_core_hwmod,
879 .slave = &omap2430_timer9_hwmod,
880 .clk = "gpt9_ick",
881 .addr = omap2430_timer9_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA,
884};
885
886/* timer9 slave port */
887static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
888 &omap2430_l4_core__timer9,
889};
890
891/* timer9 hwmod */
892static struct omap_hwmod omap2430_timer9_hwmod = {
893 .name = "timer9",
894 .mpu_irqs = omap2430_timer9_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
896 .main_clk = "gpt9_fck",
897 .prcm = {
898 .omap2 = {
899 .prcm_reg_id = 1,
900 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
901 .module_offs = CORE_MOD,
902 .idlest_reg_id = 1,
903 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
904 },
905 },
906 .slaves = omap2430_timer9_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
908 .class = &omap2430_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
910};
911
912/* timer10 */
913static struct omap_hwmod omap2430_timer10_hwmod;
914static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
915 { .irq = 46, },
916};
917
918static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
919 {
920 .pa_start = 0x48086000,
921 .pa_end = 0x48086000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924};
925
926/* l4_core -> timer10 */
927static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
928 .master = &omap2430_l4_core_hwmod,
929 .slave = &omap2430_timer10_hwmod,
930 .clk = "gpt10_ick",
931 .addr = omap2430_timer10_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA,
934};
935
936/* timer10 slave port */
937static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
938 &omap2430_l4_core__timer10,
939};
940
941/* timer10 hwmod */
942static struct omap_hwmod omap2430_timer10_hwmod = {
943 .name = "timer10",
944 .mpu_irqs = omap2430_timer10_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
946 .main_clk = "gpt10_fck",
947 .prcm = {
948 .omap2 = {
949 .prcm_reg_id = 1,
950 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
951 .module_offs = CORE_MOD,
952 .idlest_reg_id = 1,
953 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
954 },
955 },
956 .slaves = omap2430_timer10_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
958 .class = &omap2430_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
960};
961
962/* timer11 */
963static struct omap_hwmod omap2430_timer11_hwmod;
964static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
965 { .irq = 47, },
966};
967
968static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
969 {
970 .pa_start = 0x48088000,
971 .pa_end = 0x48088000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT
973 },
974};
975
976/* l4_core -> timer11 */
977static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
978 .master = &omap2430_l4_core_hwmod,
979 .slave = &omap2430_timer11_hwmod,
980 .clk = "gpt11_ick",
981 .addr = omap2430_timer11_addrs,
982 .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA,
984};
985
986/* timer11 slave port */
987static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
988 &omap2430_l4_core__timer11,
989};
990
991/* timer11 hwmod */
992static struct omap_hwmod omap2430_timer11_hwmod = {
993 .name = "timer11",
994 .mpu_irqs = omap2430_timer11_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
996 .main_clk = "gpt11_fck",
997 .prcm = {
998 .omap2 = {
999 .prcm_reg_id = 1,
1000 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
1001 .module_offs = CORE_MOD,
1002 .idlest_reg_id = 1,
1003 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
1004 },
1005 },
1006 .slaves = omap2430_timer11_slaves,
1007 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
1008 .class = &omap2430_timer_hwmod_class,
1009 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1010};
1011
1012/* timer12 */
1013static struct omap_hwmod omap2430_timer12_hwmod;
1014static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
1015 { .irq = 48, },
1016};
1017
1018static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
1019 {
1020 .pa_start = 0x4808a000,
1021 .pa_end = 0x4808a000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT
1023 },
1024};
1025
1026/* l4_core -> timer12 */
1027static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
1028 .master = &omap2430_l4_core_hwmod,
1029 .slave = &omap2430_timer12_hwmod,
1030 .clk = "gpt12_ick",
1031 .addr = omap2430_timer12_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034};
1035
1036/* timer12 slave port */
1037static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
1038 &omap2430_l4_core__timer12,
1039};
1040
1041/* timer12 hwmod */
1042static struct omap_hwmod omap2430_timer12_hwmod = {
1043 .name = "timer12",
1044 .mpu_irqs = omap2430_timer12_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
1046 .main_clk = "gpt12_fck",
1047 .prcm = {
1048 .omap2 = {
1049 .prcm_reg_id = 1,
1050 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
1051 .module_offs = CORE_MOD,
1052 .idlest_reg_id = 1,
1053 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
1054 },
1055 },
1056 .slaves = omap2430_timer12_slaves,
1057 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
1058 .class = &omap2430_timer_hwmod_class,
1059 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1060};
1061
396/* l4_wkup -> wd_timer2 */ 1062/* l4_wkup -> wd_timer2 */
397static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { 1063static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
398 { 1064 {
@@ -819,6 +1485,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
819 .clk = "dss_54m_fck", 1485 .clk = "dss_54m_fck",
820 .addr = omap2430_dss_venc_addrs, 1486 .addr = omap2430_dss_venc_addrs,
821 .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), 1487 .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
1488 .flags = OCPIF_SWSUP_IDLE,
822 .user = OCP_USER_MPU | OCP_USER_SDMA, 1489 .user = OCP_USER_MPU | OCP_USER_SDMA,
823}; 1490};
824 1491
@@ -1295,6 +1962,75 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
1295}; 1962};
1296 1963
1297/* 1964/*
1965 * 'mailbox' class
1966 * mailbox module allowing communication between the on-chip processors
1967 * using a queued mailbox-interrupt mechanism.
1968 */
1969
1970static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1971 .rev_offs = 0x000,
1972 .sysc_offs = 0x010,
1973 .syss_offs = 0x014,
1974 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1975 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1976 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1977 .sysc_fields = &omap_hwmod_sysc_type1,
1978};
1979
1980static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1981 .name = "mailbox",
1982 .sysc = &omap2430_mailbox_sysc,
1983};
1984
1985/* mailbox */
1986static struct omap_hwmod omap2430_mailbox_hwmod;
1987static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1988 { .irq = 26 },
1989};
1990
1991static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
1992 {
1993 .pa_start = 0x48094000,
1994 .pa_end = 0x480941ff,
1995 .flags = ADDR_TYPE_RT,
1996 },
1997};
1998
1999/* l4_core -> mailbox */
2000static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
2001 .master = &omap2430_l4_core_hwmod,
2002 .slave = &omap2430_mailbox_hwmod,
2003 .addr = omap2430_mailbox_addrs,
2004 .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
2005 .user = OCP_USER_MPU | OCP_USER_SDMA,
2006};
2007
2008/* mailbox slave ports */
2009static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
2010 &omap2430_l4_core__mailbox,
2011};
2012
2013static struct omap_hwmod omap2430_mailbox_hwmod = {
2014 .name = "mailbox",
2015 .class = &omap2430_mailbox_hwmod_class,
2016 .mpu_irqs = omap2430_mailbox_irqs,
2017 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
2018 .main_clk = "mailboxes_ick",
2019 .prcm = {
2020 .omap2 = {
2021 .prcm_reg_id = 1,
2022 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2023 .module_offs = CORE_MOD,
2024 .idlest_reg_id = 1,
2025 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
2026 },
2027 },
2028 .slaves = omap2430_mailbox_slaves,
2029 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
2030 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2031};
2032
2033/*
1298 * 'mcspi' class 2034 * 'mcspi' class
1299 * multichannel serial port interface (mcspi) / master/slave synchronous serial 2035 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1300 * bus 2036 * bus
@@ -1506,7 +2242,425 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
1506 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 2242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1507}; 2243};
1508 2244
2245/*
2246 * 'mcbsp' class
2247 * multi channel buffered serial port controller
2248 */
2249
2250static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
2251 .rev_offs = 0x007C,
2252 .sysc_offs = 0x008C,
2253 .sysc_flags = (SYSC_HAS_SOFTRESET),
2254 .sysc_fields = &omap_hwmod_sysc_type1,
2255};
1509 2256
2257static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
2258 .name = "mcbsp",
2259 .sysc = &omap2430_mcbsp_sysc,
2260 .rev = MCBSP_CONFIG_TYPE2,
2261};
2262
2263/* mcbsp1 */
2264static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2265 { .name = "tx", .irq = 59 },
2266 { .name = "rx", .irq = 60 },
2267 { .name = "ovr", .irq = 61 },
2268 { .name = "common", .irq = 64 },
2269};
2270
2271static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2272 { .name = "rx", .dma_req = 32 },
2273 { .name = "tx", .dma_req = 31 },
2274};
2275
2276static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
2277 {
2278 .name = "mpu",
2279 .pa_start = 0x48074000,
2280 .pa_end = 0x480740ff,
2281 .flags = ADDR_TYPE_RT
2282 },
2283};
2284
2285/* l4_core -> mcbsp1 */
2286static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2287 .master = &omap2430_l4_core_hwmod,
2288 .slave = &omap2430_mcbsp1_hwmod,
2289 .clk = "mcbsp1_ick",
2290 .addr = omap2430_mcbsp1_addrs,
2291 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
2292 .user = OCP_USER_MPU | OCP_USER_SDMA,
2293};
2294
2295/* mcbsp1 slave ports */
2296static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
2297 &omap2430_l4_core__mcbsp1,
2298};
2299
2300static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2301 .name = "mcbsp1",
2302 .class = &omap2430_mcbsp_hwmod_class,
2303 .mpu_irqs = omap2430_mcbsp1_irqs,
2304 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs),
2305 .sdma_reqs = omap2430_mcbsp1_sdma_chs,
2306 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2307 .main_clk = "mcbsp1_fck",
2308 .prcm = {
2309 .omap2 = {
2310 .prcm_reg_id = 1,
2311 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2312 .module_offs = CORE_MOD,
2313 .idlest_reg_id = 1,
2314 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2315 },
2316 },
2317 .slaves = omap2430_mcbsp1_slaves,
2318 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
2319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2320};
2321
2322/* mcbsp2 */
2323static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2324 { .name = "tx", .irq = 62 },
2325 { .name = "rx", .irq = 63 },
2326 { .name = "common", .irq = 16 },
2327};
2328
2329static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2330 { .name = "rx", .dma_req = 34 },
2331 { .name = "tx", .dma_req = 33 },
2332};
2333
2334static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
2335 {
2336 .name = "mpu",
2337 .pa_start = 0x48076000,
2338 .pa_end = 0x480760ff,
2339 .flags = ADDR_TYPE_RT
2340 },
2341};
2342
2343/* l4_core -> mcbsp2 */
2344static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2345 .master = &omap2430_l4_core_hwmod,
2346 .slave = &omap2430_mcbsp2_hwmod,
2347 .clk = "mcbsp2_ick",
2348 .addr = omap2430_mcbsp2_addrs,
2349 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
2350 .user = OCP_USER_MPU | OCP_USER_SDMA,
2351};
2352
2353/* mcbsp2 slave ports */
2354static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
2355 &omap2430_l4_core__mcbsp2,
2356};
2357
2358static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2359 .name = "mcbsp2",
2360 .class = &omap2430_mcbsp_hwmod_class,
2361 .mpu_irqs = omap2430_mcbsp2_irqs,
2362 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs),
2363 .sdma_reqs = omap2430_mcbsp2_sdma_chs,
2364 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2365 .main_clk = "mcbsp2_fck",
2366 .prcm = {
2367 .omap2 = {
2368 .prcm_reg_id = 1,
2369 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2370 .module_offs = CORE_MOD,
2371 .idlest_reg_id = 1,
2372 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2373 },
2374 },
2375 .slaves = omap2430_mcbsp2_slaves,
2376 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
2377 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2378};
2379
2380/* mcbsp3 */
2381static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2382 { .name = "tx", .irq = 89 },
2383 { .name = "rx", .irq = 90 },
2384 { .name = "common", .irq = 17 },
2385};
2386
2387static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2388 { .name = "rx", .dma_req = 18 },
2389 { .name = "tx", .dma_req = 17 },
2390};
2391
2392static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2393 {
2394 .name = "mpu",
2395 .pa_start = 0x4808C000,
2396 .pa_end = 0x4808C0ff,
2397 .flags = ADDR_TYPE_RT
2398 },
2399};
2400
2401/* l4_core -> mcbsp3 */
2402static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2403 .master = &omap2430_l4_core_hwmod,
2404 .slave = &omap2430_mcbsp3_hwmod,
2405 .clk = "mcbsp3_ick",
2406 .addr = omap2430_mcbsp3_addrs,
2407 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409};
2410
2411/* mcbsp3 slave ports */
2412static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
2413 &omap2430_l4_core__mcbsp3,
2414};
2415
2416static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2417 .name = "mcbsp3",
2418 .class = &omap2430_mcbsp_hwmod_class,
2419 .mpu_irqs = omap2430_mcbsp3_irqs,
2420 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs),
2421 .sdma_reqs = omap2430_mcbsp3_sdma_chs,
2422 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2423 .main_clk = "mcbsp3_fck",
2424 .prcm = {
2425 .omap2 = {
2426 .prcm_reg_id = 1,
2427 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
2428 .module_offs = CORE_MOD,
2429 .idlest_reg_id = 2,
2430 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
2431 },
2432 },
2433 .slaves = omap2430_mcbsp3_slaves,
2434 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
2435 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2436};
2437
2438/* mcbsp4 */
2439static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2440 { .name = "tx", .irq = 54 },
2441 { .name = "rx", .irq = 55 },
2442 { .name = "common", .irq = 18 },
2443};
2444
2445static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2446 { .name = "rx", .dma_req = 20 },
2447 { .name = "tx", .dma_req = 19 },
2448};
2449
2450static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2451 {
2452 .name = "mpu",
2453 .pa_start = 0x4808E000,
2454 .pa_end = 0x4808E0ff,
2455 .flags = ADDR_TYPE_RT
2456 },
2457};
2458
2459/* l4_core -> mcbsp4 */
2460static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2461 .master = &omap2430_l4_core_hwmod,
2462 .slave = &omap2430_mcbsp4_hwmod,
2463 .clk = "mcbsp4_ick",
2464 .addr = omap2430_mcbsp4_addrs,
2465 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
2466 .user = OCP_USER_MPU | OCP_USER_SDMA,
2467};
2468
2469/* mcbsp4 slave ports */
2470static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
2471 &omap2430_l4_core__mcbsp4,
2472};
2473
2474static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2475 .name = "mcbsp4",
2476 .class = &omap2430_mcbsp_hwmod_class,
2477 .mpu_irqs = omap2430_mcbsp4_irqs,
2478 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2479 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
2480 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2481 .main_clk = "mcbsp4_fck",
2482 .prcm = {
2483 .omap2 = {
2484 .prcm_reg_id = 1,
2485 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
2486 .module_offs = CORE_MOD,
2487 .idlest_reg_id = 2,
2488 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
2489 },
2490 },
2491 .slaves = omap2430_mcbsp4_slaves,
2492 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
2493 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2494};
2495
2496/* mcbsp5 */
2497static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2498 { .name = "tx", .irq = 81 },
2499 { .name = "rx", .irq = 82 },
2500 { .name = "common", .irq = 19 },
2501};
2502
2503static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2504 { .name = "rx", .dma_req = 22 },
2505 { .name = "tx", .dma_req = 21 },
2506};
2507
2508static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2509 {
2510 .name = "mpu",
2511 .pa_start = 0x48096000,
2512 .pa_end = 0x480960ff,
2513 .flags = ADDR_TYPE_RT
2514 },
2515};
2516
2517/* l4_core -> mcbsp5 */
2518static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2519 .master = &omap2430_l4_core_hwmod,
2520 .slave = &omap2430_mcbsp5_hwmod,
2521 .clk = "mcbsp5_ick",
2522 .addr = omap2430_mcbsp5_addrs,
2523 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
2524 .user = OCP_USER_MPU | OCP_USER_SDMA,
2525};
2526
2527/* mcbsp5 slave ports */
2528static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
2529 &omap2430_l4_core__mcbsp5,
2530};
2531
2532static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2533 .name = "mcbsp5",
2534 .class = &omap2430_mcbsp_hwmod_class,
2535 .mpu_irqs = omap2430_mcbsp5_irqs,
2536 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2537 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
2538 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2539 .main_clk = "mcbsp5_fck",
2540 .prcm = {
2541 .omap2 = {
2542 .prcm_reg_id = 1,
2543 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
2544 .module_offs = CORE_MOD,
2545 .idlest_reg_id = 2,
2546 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
2547 },
2548 },
2549 .slaves = omap2430_mcbsp5_slaves,
2550 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
2551 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2552};
2553
2554/* MMC/SD/SDIO common */
2555
2556static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
2557 .rev_offs = 0x1fc,
2558 .sysc_offs = 0x10,
2559 .syss_offs = 0x14,
2560 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2561 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2562 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2564 .sysc_fields = &omap_hwmod_sysc_type1,
2565};
2566
2567static struct omap_hwmod_class omap2430_mmc_class = {
2568 .name = "mmc",
2569 .sysc = &omap2430_mmc_sysc,
2570};
2571
2572/* MMC/SD/SDIO1 */
2573
2574static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2575 { .irq = 83 },
2576};
2577
2578static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2579 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2580 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
2581};
2582
2583static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
2584 { .role = "dbck", .clk = "mmchsdb1_fck" },
2585};
2586
2587static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
2588 &omap2430_l4_core__mmc1,
2589};
2590
2591static struct omap_mmc_dev_attr mmc1_dev_attr = {
2592 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2593};
2594
2595static struct omap_hwmod omap2430_mmc1_hwmod = {
2596 .name = "mmc1",
2597 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2598 .mpu_irqs = omap2430_mmc1_mpu_irqs,
2599 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2600 .sdma_reqs = omap2430_mmc1_sdma_reqs,
2601 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2602 .opt_clks = omap2430_mmc1_opt_clks,
2603 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2604 .main_clk = "mmchs1_fck",
2605 .prcm = {
2606 .omap2 = {
2607 .module_offs = CORE_MOD,
2608 .prcm_reg_id = 2,
2609 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
2610 .idlest_reg_id = 2,
2611 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
2612 },
2613 },
2614 .dev_attr = &mmc1_dev_attr,
2615 .slaves = omap2430_mmc1_slaves,
2616 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
2617 .class = &omap2430_mmc_class,
2618 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2619};
2620
2621/* MMC/SD/SDIO2 */
2622
2623static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2624 { .irq = 86 },
2625};
2626
2627static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2628 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2629 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
2630};
2631
2632static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
2633 { .role = "dbck", .clk = "mmchsdb2_fck" },
2634};
2635
2636static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
2637 &omap2430_l4_core__mmc2,
2638};
2639
2640static struct omap_hwmod omap2430_mmc2_hwmod = {
2641 .name = "mmc2",
2642 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2643 .mpu_irqs = omap2430_mmc2_mpu_irqs,
2644 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2645 .sdma_reqs = omap2430_mmc2_sdma_reqs,
2646 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2647 .opt_clks = omap2430_mmc2_opt_clks,
2648 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2649 .main_clk = "mmchs2_fck",
2650 .prcm = {
2651 .omap2 = {
2652 .module_offs = CORE_MOD,
2653 .prcm_reg_id = 2,
2654 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
2655 .idlest_reg_id = 2,
2656 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2657 },
2658 },
2659 .slaves = omap2430_mmc2_slaves,
2660 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
2661 .class = &omap2430_mmc_class,
2662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2663};
1510 2664
1511static __initdata struct omap_hwmod *omap2430_hwmods[] = { 2665static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1512 &omap2430_l3_main_hwmod, 2666 &omap2430_l3_main_hwmod,
@@ -1514,6 +2668,20 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1514 &omap2430_l4_wkup_hwmod, 2668 &omap2430_l4_wkup_hwmod,
1515 &omap2430_mpu_hwmod, 2669 &omap2430_mpu_hwmod,
1516 &omap2430_iva_hwmod, 2670 &omap2430_iva_hwmod,
2671
2672 &omap2430_timer1_hwmod,
2673 &omap2430_timer2_hwmod,
2674 &omap2430_timer3_hwmod,
2675 &omap2430_timer4_hwmod,
2676 &omap2430_timer5_hwmod,
2677 &omap2430_timer6_hwmod,
2678 &omap2430_timer7_hwmod,
2679 &omap2430_timer8_hwmod,
2680 &omap2430_timer9_hwmod,
2681 &omap2430_timer10_hwmod,
2682 &omap2430_timer11_hwmod,
2683 &omap2430_timer12_hwmod,
2684
1517 &omap2430_wd_timer2_hwmod, 2685 &omap2430_wd_timer2_hwmod,
1518 &omap2430_uart1_hwmod, 2686 &omap2430_uart1_hwmod,
1519 &omap2430_uart2_hwmod, 2687 &omap2430_uart2_hwmod,
@@ -1526,6 +2694,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1526 /* i2c class */ 2694 /* i2c class */
1527 &omap2430_i2c1_hwmod, 2695 &omap2430_i2c1_hwmod,
1528 &omap2430_i2c2_hwmod, 2696 &omap2430_i2c2_hwmod,
2697 &omap2430_mmc1_hwmod,
2698 &omap2430_mmc2_hwmod,
1529 2699
1530 /* gpio class */ 2700 /* gpio class */
1531 &omap2430_gpio1_hwmod, 2701 &omap2430_gpio1_hwmod,
@@ -1537,6 +2707,16 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1537 /* dma_system class*/ 2707 /* dma_system class*/
1538 &omap2430_dma_system_hwmod, 2708 &omap2430_dma_system_hwmod,
1539 2709
2710 /* mcbsp class */
2711 &omap2430_mcbsp1_hwmod,
2712 &omap2430_mcbsp2_hwmod,
2713 &omap2430_mcbsp3_hwmod,
2714 &omap2430_mcbsp4_hwmod,
2715 &omap2430_mcbsp5_hwmod,
2716
2717 /* mailbox class */
2718 &omap2430_mailbox_hwmod,
2719
1540 /* mcspi class */ 2720 /* mcspi class */
1541 &omap2430_mcspi1_hwmod, 2721 &omap2430_mcspi1_hwmod,
1542 &omap2430_mcspi2_hwmod, 2722 &omap2430_mcspi2_hwmod,
@@ -1550,5 +2730,5 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
1550 2730
1551int __init omap2430_hwmod_init(void) 2731int __init omap2430_hwmod_init(void)
1552{ 2732{
1553 return omap_hwmod_init(omap2430_hwmods); 2733 return omap_hwmod_register(omap2430_hwmods);
1554} 2734}
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index e9d001228568..2e275cbcd654 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -22,8 +22,11 @@
22#include <plat/l4_3xxx.h> 22#include <plat/l4_3xxx.h>
23#include <plat/i2c.h> 23#include <plat/i2c.h>
24#include <plat/gpio.h> 24#include <plat/gpio.h>
25#include <plat/mmc.h>
25#include <plat/smartreflex.h> 26#include <plat/smartreflex.h>
27#include <plat/mcbsp.h>
26#include <plat/mcspi.h> 28#include <plat/mcspi.h>
29#include <plat/dmtimer.h>
27 30
28#include "omap_hwmod_common_data.h" 31#include "omap_hwmod_common_data.h"
29 32
@@ -68,10 +71,21 @@ static struct omap_hwmod omap34xx_mcspi1;
68static struct omap_hwmod omap34xx_mcspi2; 71static struct omap_hwmod omap34xx_mcspi2;
69static struct omap_hwmod omap34xx_mcspi3; 72static struct omap_hwmod omap34xx_mcspi3;
70static struct omap_hwmod omap34xx_mcspi4; 73static struct omap_hwmod omap34xx_mcspi4;
74static struct omap_hwmod omap3xxx_mmc1_hwmod;
75static struct omap_hwmod omap3xxx_mmc2_hwmod;
76static struct omap_hwmod omap3xxx_mmc3_hwmod;
71static struct omap_hwmod am35xx_usbhsotg_hwmod; 77static struct omap_hwmod am35xx_usbhsotg_hwmod;
72 78
73static struct omap_hwmod omap3xxx_dma_system_hwmod; 79static struct omap_hwmod omap3xxx_dma_system_hwmod;
74 80
81static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88
75/* L3 -> L4_CORE interface */ 89/* L3 -> L4_CORE interface */
76static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 90static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
77 .master = &omap3xxx_l3_main_hwmod, 91 .master = &omap3xxx_l3_main_hwmod,
@@ -86,10 +100,26 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
86 .user = OCP_USER_MPU | OCP_USER_SDMA, 100 .user = OCP_USER_MPU | OCP_USER_SDMA,
87}; 101};
88 102
103/* L3 taret configuration and error log registers */
104static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
105 { .irq = INT_34XX_L3_DBG_IRQ },
106 { .irq = INT_34XX_L3_APP_IRQ },
107};
108
109static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
110 {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
114 },
115};
116
89/* MPU -> L3 interface */ 117/* MPU -> L3 interface */
90static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 118static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
91 .master = &omap3xxx_mpu_hwmod, 119 .master = &omap3xxx_mpu_hwmod,
92 .slave = &omap3xxx_l3_main_hwmod, 120 .slave = &omap3xxx_l3_main_hwmod,
121 .addr = omap3xxx_l3_main_addrs,
122 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
93 .user = OCP_USER_MPU, 123 .user = OCP_USER_MPU,
94}; 124};
95 125
@@ -121,6 +151,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
121static struct omap_hwmod omap3xxx_l3_main_hwmod = { 151static struct omap_hwmod omap3xxx_l3_main_hwmod = {
122 .name = "l3_main", 152 .name = "l3_main",
123 .class = &l3_hwmod_class, 153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
124 .masters = omap3xxx_l3_main_masters, 156 .masters = omap3xxx_l3_main_masters,
125 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), 157 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
126 .slaves = omap3xxx_l3_main_slaves, 158 .slaves = omap3xxx_l3_main_slaves,
@@ -158,6 +190,63 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
158 .user = OCP_USER_MPU | OCP_USER_SDMA, 190 .user = OCP_USER_MPU | OCP_USER_SDMA,
159}; 191};
160 192
193/* L4 CORE -> MMC1 interface */
194static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
195 {
196 .pa_start = 0x4809c000,
197 .pa_end = 0x4809c1ff,
198 .flags = ADDR_TYPE_RT,
199 },
200};
201
202static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
203 .master = &omap3xxx_l4_core_hwmod,
204 .slave = &omap3xxx_mmc1_hwmod,
205 .clk = "mmchs1_ick",
206 .addr = omap3xxx_mmc1_addr_space,
207 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
208 .user = OCP_USER_MPU | OCP_USER_SDMA,
209 .flags = OMAP_FIREWALL_L4
210};
211
212/* L4 CORE -> MMC2 interface */
213static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
214 {
215 .pa_start = 0x480b4000,
216 .pa_end = 0x480b41ff,
217 .flags = ADDR_TYPE_RT,
218 },
219};
220
221static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
222 .master = &omap3xxx_l4_core_hwmod,
223 .slave = &omap3xxx_mmc2_hwmod,
224 .clk = "mmchs2_ick",
225 .addr = omap3xxx_mmc2_addr_space,
226 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
227 .user = OCP_USER_MPU | OCP_USER_SDMA,
228 .flags = OMAP_FIREWALL_L4
229};
230
231/* L4 CORE -> MMC3 interface */
232static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
233 {
234 .pa_start = 0x480ad000,
235 .pa_end = 0x480ad1ff,
236 .flags = ADDR_TYPE_RT,
237 },
238};
239
240static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
241 .master = &omap3xxx_l4_core_hwmod,
242 .slave = &omap3xxx_mmc3_hwmod,
243 .clk = "mmchs3_ick",
244 .addr = omap3xxx_mmc3_addr_space,
245 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247 .flags = OMAP_FIREWALL_L4
248};
249
161/* L4 CORE -> UART1 interface */ 250/* L4 CORE -> UART1 interface */
162static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { 251static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
163 { 252 {
@@ -402,26 +491,12 @@ static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
402/* Slave interfaces on the L4_CORE interconnect */ 491/* Slave interfaces on the L4_CORE interconnect */
403static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { 492static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
404 &omap3xxx_l3_main__l4_core, 493 &omap3xxx_l3_main__l4_core,
405 &omap3_l4_core__sr1,
406 &omap3_l4_core__sr2,
407};
408
409/* Master interfaces on the L4_CORE interconnect */
410static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
411 &omap3xxx_l4_core__l4_wkup,
412 &omap3_l4_core__uart1,
413 &omap3_l4_core__uart2,
414 &omap3_l4_core__i2c1,
415 &omap3_l4_core__i2c2,
416 &omap3_l4_core__i2c3,
417}; 494};
418 495
419/* L4 CORE */ 496/* L4 CORE */
420static struct omap_hwmod omap3xxx_l4_core_hwmod = { 497static struct omap_hwmod omap3xxx_l4_core_hwmod = {
421 .name = "l4_core", 498 .name = "l4_core",
422 .class = &l4_hwmod_class, 499 .class = &l4_hwmod_class,
423 .masters = omap3xxx_l4_core_masters,
424 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters),
425 .slaves = omap3xxx_l4_core_slaves, 500 .slaves = omap3xxx_l4_core_slaves,
426 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), 501 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
427 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 502 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -433,18 +508,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
433 &omap3xxx_l3_main__l4_per, 508 &omap3xxx_l3_main__l4_per,
434}; 509};
435 510
436/* Master interfaces on the L4_PER interconnect */
437static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
438 &omap3_l4_per__uart3,
439 &omap3_l4_per__uart4,
440};
441
442/* L4 PER */ 511/* L4 PER */
443static struct omap_hwmod omap3xxx_l4_per_hwmod = { 512static struct omap_hwmod omap3xxx_l4_per_hwmod = {
444 .name = "l4_per", 513 .name = "l4_per",
445 .class = &l4_hwmod_class, 514 .class = &l4_hwmod_class,
446 .masters = omap3xxx_l4_per_masters,
447 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters),
448 .slaves = omap3xxx_l4_per_slaves, 515 .slaves = omap3xxx_l4_per_slaves,
449 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), 516 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
450 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 517 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -456,16 +523,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
456 &omap3xxx_l4_core__l4_wkup, 523 &omap3xxx_l4_core__l4_wkup,
457}; 524};
458 525
459/* Master interfaces on the L4_WKUP interconnect */
460static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
461};
462
463/* L4 WKUP */ 526/* L4 WKUP */
464static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 527static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
465 .name = "l4_wkup", 528 .name = "l4_wkup",
466 .class = &l4_hwmod_class, 529 .class = &l4_hwmod_class,
467 .masters = omap3xxx_l4_wkup_masters,
468 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
469 .slaves = omap3xxx_l4_wkup_slaves, 530 .slaves = omap3xxx_l4_wkup_slaves,
470 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), 531 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
471 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -515,6 +576,640 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
515 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
516}; 577};
517 578
579/* timer class */
580static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
581 .rev_offs = 0x0000,
582 .sysc_offs = 0x0010,
583 .syss_offs = 0x0014,
584 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
585 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
586 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
587 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
588 .sysc_fields = &omap_hwmod_sysc_type1,
589};
590
591static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
592 .name = "timer",
593 .sysc = &omap3xxx_timer_1ms_sysc,
594 .rev = OMAP_TIMER_IP_VERSION_1,
595};
596
597static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
598 .rev_offs = 0x0000,
599 .sysc_offs = 0x0010,
600 .syss_offs = 0x0014,
601 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
602 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
603 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
604 .sysc_fields = &omap_hwmod_sysc_type1,
605};
606
607static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
608 .name = "timer",
609 .sysc = &omap3xxx_timer_sysc,
610 .rev = OMAP_TIMER_IP_VERSION_1,
611};
612
613/* timer1 */
614static struct omap_hwmod omap3xxx_timer1_hwmod;
615static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
616 { .irq = 37, },
617};
618
619static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
620 {
621 .pa_start = 0x48318000,
622 .pa_end = 0x48318000 + SZ_1K - 1,
623 .flags = ADDR_TYPE_RT
624 },
625};
626
627/* l4_wkup -> timer1 */
628static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
629 .master = &omap3xxx_l4_wkup_hwmod,
630 .slave = &omap3xxx_timer1_hwmod,
631 .clk = "gpt1_ick",
632 .addr = omap3xxx_timer1_addrs,
633 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
634 .user = OCP_USER_MPU | OCP_USER_SDMA,
635};
636
637/* timer1 slave port */
638static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
639 &omap3xxx_l4_wkup__timer1,
640};
641
642/* timer1 hwmod */
643static struct omap_hwmod omap3xxx_timer1_hwmod = {
644 .name = "timer1",
645 .mpu_irqs = omap3xxx_timer1_mpu_irqs,
646 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
647 .main_clk = "gpt1_fck",
648 .prcm = {
649 .omap2 = {
650 .prcm_reg_id = 1,
651 .module_bit = OMAP3430_EN_GPT1_SHIFT,
652 .module_offs = WKUP_MOD,
653 .idlest_reg_id = 1,
654 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
655 },
656 },
657 .slaves = omap3xxx_timer1_slaves,
658 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
659 .class = &omap3xxx_timer_1ms_hwmod_class,
660 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
661};
662
663/* timer2 */
664static struct omap_hwmod omap3xxx_timer2_hwmod;
665static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
666 { .irq = 38, },
667};
668
669static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
670 {
671 .pa_start = 0x49032000,
672 .pa_end = 0x49032000 + SZ_1K - 1,
673 .flags = ADDR_TYPE_RT
674 },
675};
676
677/* l4_per -> timer2 */
678static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
679 .master = &omap3xxx_l4_per_hwmod,
680 .slave = &omap3xxx_timer2_hwmod,
681 .clk = "gpt2_ick",
682 .addr = omap3xxx_timer2_addrs,
683 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
684 .user = OCP_USER_MPU | OCP_USER_SDMA,
685};
686
687/* timer2 slave port */
688static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
689 &omap3xxx_l4_per__timer2,
690};
691
692/* timer2 hwmod */
693static struct omap_hwmod omap3xxx_timer2_hwmod = {
694 .name = "timer2",
695 .mpu_irqs = omap3xxx_timer2_mpu_irqs,
696 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
697 .main_clk = "gpt2_fck",
698 .prcm = {
699 .omap2 = {
700 .prcm_reg_id = 1,
701 .module_bit = OMAP3430_EN_GPT2_SHIFT,
702 .module_offs = OMAP3430_PER_MOD,
703 .idlest_reg_id = 1,
704 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
705 },
706 },
707 .slaves = omap3xxx_timer2_slaves,
708 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
709 .class = &omap3xxx_timer_1ms_hwmod_class,
710 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
711};
712
713/* timer3 */
714static struct omap_hwmod omap3xxx_timer3_hwmod;
715static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
716 { .irq = 39, },
717};
718
719static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
720 {
721 .pa_start = 0x49034000,
722 .pa_end = 0x49034000 + SZ_1K - 1,
723 .flags = ADDR_TYPE_RT
724 },
725};
726
727/* l4_per -> timer3 */
728static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
729 .master = &omap3xxx_l4_per_hwmod,
730 .slave = &omap3xxx_timer3_hwmod,
731 .clk = "gpt3_ick",
732 .addr = omap3xxx_timer3_addrs,
733 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
734 .user = OCP_USER_MPU | OCP_USER_SDMA,
735};
736
737/* timer3 slave port */
738static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
739 &omap3xxx_l4_per__timer3,
740};
741
742/* timer3 hwmod */
743static struct omap_hwmod omap3xxx_timer3_hwmod = {
744 .name = "timer3",
745 .mpu_irqs = omap3xxx_timer3_mpu_irqs,
746 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
747 .main_clk = "gpt3_fck",
748 .prcm = {
749 .omap2 = {
750 .prcm_reg_id = 1,
751 .module_bit = OMAP3430_EN_GPT3_SHIFT,
752 .module_offs = OMAP3430_PER_MOD,
753 .idlest_reg_id = 1,
754 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
755 },
756 },
757 .slaves = omap3xxx_timer3_slaves,
758 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
759 .class = &omap3xxx_timer_hwmod_class,
760 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
761};
762
763/* timer4 */
764static struct omap_hwmod omap3xxx_timer4_hwmod;
765static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
766 { .irq = 40, },
767};
768
769static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
770 {
771 .pa_start = 0x49036000,
772 .pa_end = 0x49036000 + SZ_1K - 1,
773 .flags = ADDR_TYPE_RT
774 },
775};
776
777/* l4_per -> timer4 */
778static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
779 .master = &omap3xxx_l4_per_hwmod,
780 .slave = &omap3xxx_timer4_hwmod,
781 .clk = "gpt4_ick",
782 .addr = omap3xxx_timer4_addrs,
783 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
784 .user = OCP_USER_MPU | OCP_USER_SDMA,
785};
786
787/* timer4 slave port */
788static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
789 &omap3xxx_l4_per__timer4,
790};
791
792/* timer4 hwmod */
793static struct omap_hwmod omap3xxx_timer4_hwmod = {
794 .name = "timer4",
795 .mpu_irqs = omap3xxx_timer4_mpu_irqs,
796 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
797 .main_clk = "gpt4_fck",
798 .prcm = {
799 .omap2 = {
800 .prcm_reg_id = 1,
801 .module_bit = OMAP3430_EN_GPT4_SHIFT,
802 .module_offs = OMAP3430_PER_MOD,
803 .idlest_reg_id = 1,
804 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
805 },
806 },
807 .slaves = omap3xxx_timer4_slaves,
808 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
809 .class = &omap3xxx_timer_hwmod_class,
810 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
811};
812
813/* timer5 */
814static struct omap_hwmod omap3xxx_timer5_hwmod;
815static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
816 { .irq = 41, },
817};
818
819static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
820 {
821 .pa_start = 0x49038000,
822 .pa_end = 0x49038000 + SZ_1K - 1,
823 .flags = ADDR_TYPE_RT
824 },
825};
826
827/* l4_per -> timer5 */
828static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
829 .master = &omap3xxx_l4_per_hwmod,
830 .slave = &omap3xxx_timer5_hwmod,
831 .clk = "gpt5_ick",
832 .addr = omap3xxx_timer5_addrs,
833 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
834 .user = OCP_USER_MPU | OCP_USER_SDMA,
835};
836
837/* timer5 slave port */
838static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
839 &omap3xxx_l4_per__timer5,
840};
841
842/* timer5 hwmod */
843static struct omap_hwmod omap3xxx_timer5_hwmod = {
844 .name = "timer5",
845 .mpu_irqs = omap3xxx_timer5_mpu_irqs,
846 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
847 .main_clk = "gpt5_fck",
848 .prcm = {
849 .omap2 = {
850 .prcm_reg_id = 1,
851 .module_bit = OMAP3430_EN_GPT5_SHIFT,
852 .module_offs = OMAP3430_PER_MOD,
853 .idlest_reg_id = 1,
854 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
855 },
856 },
857 .slaves = omap3xxx_timer5_slaves,
858 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
859 .class = &omap3xxx_timer_hwmod_class,
860 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
861};
862
863/* timer6 */
864static struct omap_hwmod omap3xxx_timer6_hwmod;
865static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
866 { .irq = 42, },
867};
868
869static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
870 {
871 .pa_start = 0x4903A000,
872 .pa_end = 0x4903A000 + SZ_1K - 1,
873 .flags = ADDR_TYPE_RT
874 },
875};
876
877/* l4_per -> timer6 */
878static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
879 .master = &omap3xxx_l4_per_hwmod,
880 .slave = &omap3xxx_timer6_hwmod,
881 .clk = "gpt6_ick",
882 .addr = omap3xxx_timer6_addrs,
883 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
884 .user = OCP_USER_MPU | OCP_USER_SDMA,
885};
886
887/* timer6 slave port */
888static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
889 &omap3xxx_l4_per__timer6,
890};
891
892/* timer6 hwmod */
893static struct omap_hwmod omap3xxx_timer6_hwmod = {
894 .name = "timer6",
895 .mpu_irqs = omap3xxx_timer6_mpu_irqs,
896 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
897 .main_clk = "gpt6_fck",
898 .prcm = {
899 .omap2 = {
900 .prcm_reg_id = 1,
901 .module_bit = OMAP3430_EN_GPT6_SHIFT,
902 .module_offs = OMAP3430_PER_MOD,
903 .idlest_reg_id = 1,
904 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
905 },
906 },
907 .slaves = omap3xxx_timer6_slaves,
908 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
909 .class = &omap3xxx_timer_hwmod_class,
910 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
911};
912
913/* timer7 */
914static struct omap_hwmod omap3xxx_timer7_hwmod;
915static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
916 { .irq = 43, },
917};
918
919static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
920 {
921 .pa_start = 0x4903C000,
922 .pa_end = 0x4903C000 + SZ_1K - 1,
923 .flags = ADDR_TYPE_RT
924 },
925};
926
927/* l4_per -> timer7 */
928static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
929 .master = &omap3xxx_l4_per_hwmod,
930 .slave = &omap3xxx_timer7_hwmod,
931 .clk = "gpt7_ick",
932 .addr = omap3xxx_timer7_addrs,
933 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
934 .user = OCP_USER_MPU | OCP_USER_SDMA,
935};
936
937/* timer7 slave port */
938static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
939 &omap3xxx_l4_per__timer7,
940};
941
942/* timer7 hwmod */
943static struct omap_hwmod omap3xxx_timer7_hwmod = {
944 .name = "timer7",
945 .mpu_irqs = omap3xxx_timer7_mpu_irqs,
946 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
947 .main_clk = "gpt7_fck",
948 .prcm = {
949 .omap2 = {
950 .prcm_reg_id = 1,
951 .module_bit = OMAP3430_EN_GPT7_SHIFT,
952 .module_offs = OMAP3430_PER_MOD,
953 .idlest_reg_id = 1,
954 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
955 },
956 },
957 .slaves = omap3xxx_timer7_slaves,
958 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
959 .class = &omap3xxx_timer_hwmod_class,
960 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
961};
962
963/* timer8 */
964static struct omap_hwmod omap3xxx_timer8_hwmod;
965static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
966 { .irq = 44, },
967};
968
969static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
970 {
971 .pa_start = 0x4903E000,
972 .pa_end = 0x4903E000 + SZ_1K - 1,
973 .flags = ADDR_TYPE_RT
974 },
975};
976
977/* l4_per -> timer8 */
978static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
979 .master = &omap3xxx_l4_per_hwmod,
980 .slave = &omap3xxx_timer8_hwmod,
981 .clk = "gpt8_ick",
982 .addr = omap3xxx_timer8_addrs,
983 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
984 .user = OCP_USER_MPU | OCP_USER_SDMA,
985};
986
987/* timer8 slave port */
988static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
989 &omap3xxx_l4_per__timer8,
990};
991
992/* timer8 hwmod */
993static struct omap_hwmod omap3xxx_timer8_hwmod = {
994 .name = "timer8",
995 .mpu_irqs = omap3xxx_timer8_mpu_irqs,
996 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
997 .main_clk = "gpt8_fck",
998 .prcm = {
999 .omap2 = {
1000 .prcm_reg_id = 1,
1001 .module_bit = OMAP3430_EN_GPT8_SHIFT,
1002 .module_offs = OMAP3430_PER_MOD,
1003 .idlest_reg_id = 1,
1004 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
1005 },
1006 },
1007 .slaves = omap3xxx_timer8_slaves,
1008 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
1009 .class = &omap3xxx_timer_hwmod_class,
1010 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1011};
1012
1013/* timer9 */
1014static struct omap_hwmod omap3xxx_timer9_hwmod;
1015static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1016 { .irq = 45, },
1017};
1018
1019static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1020 {
1021 .pa_start = 0x49040000,
1022 .pa_end = 0x49040000 + SZ_1K - 1,
1023 .flags = ADDR_TYPE_RT
1024 },
1025};
1026
1027/* l4_per -> timer9 */
1028static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1029 .master = &omap3xxx_l4_per_hwmod,
1030 .slave = &omap3xxx_timer9_hwmod,
1031 .clk = "gpt9_ick",
1032 .addr = omap3xxx_timer9_addrs,
1033 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
1034 .user = OCP_USER_MPU | OCP_USER_SDMA,
1035};
1036
1037/* timer9 slave port */
1038static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1039 &omap3xxx_l4_per__timer9,
1040};
1041
1042/* timer9 hwmod */
1043static struct omap_hwmod omap3xxx_timer9_hwmod = {
1044 .name = "timer9",
1045 .mpu_irqs = omap3xxx_timer9_mpu_irqs,
1046 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1047 .main_clk = "gpt9_fck",
1048 .prcm = {
1049 .omap2 = {
1050 .prcm_reg_id = 1,
1051 .module_bit = OMAP3430_EN_GPT9_SHIFT,
1052 .module_offs = OMAP3430_PER_MOD,
1053 .idlest_reg_id = 1,
1054 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1055 },
1056 },
1057 .slaves = omap3xxx_timer9_slaves,
1058 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1059 .class = &omap3xxx_timer_hwmod_class,
1060 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1061};
1062
1063/* timer10 */
1064static struct omap_hwmod omap3xxx_timer10_hwmod;
1065static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1066 { .irq = 46, },
1067};
1068
1069static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1070 {
1071 .pa_start = 0x48086000,
1072 .pa_end = 0x48086000 + SZ_1K - 1,
1073 .flags = ADDR_TYPE_RT
1074 },
1075};
1076
1077/* l4_core -> timer10 */
1078static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1079 .master = &omap3xxx_l4_core_hwmod,
1080 .slave = &omap3xxx_timer10_hwmod,
1081 .clk = "gpt10_ick",
1082 .addr = omap3xxx_timer10_addrs,
1083 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1084 .user = OCP_USER_MPU | OCP_USER_SDMA,
1085};
1086
1087/* timer10 slave port */
1088static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1089 &omap3xxx_l4_core__timer10,
1090};
1091
1092/* timer10 hwmod */
1093static struct omap_hwmod omap3xxx_timer10_hwmod = {
1094 .name = "timer10",
1095 .mpu_irqs = omap3xxx_timer10_mpu_irqs,
1096 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1097 .main_clk = "gpt10_fck",
1098 .prcm = {
1099 .omap2 = {
1100 .prcm_reg_id = 1,
1101 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1102 .module_offs = CORE_MOD,
1103 .idlest_reg_id = 1,
1104 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1105 },
1106 },
1107 .slaves = omap3xxx_timer10_slaves,
1108 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1109 .class = &omap3xxx_timer_1ms_hwmod_class,
1110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1111};
1112
1113/* timer11 */
1114static struct omap_hwmod omap3xxx_timer11_hwmod;
1115static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1116 { .irq = 47, },
1117};
1118
1119static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1120 {
1121 .pa_start = 0x48088000,
1122 .pa_end = 0x48088000 + SZ_1K - 1,
1123 .flags = ADDR_TYPE_RT
1124 },
1125};
1126
1127/* l4_core -> timer11 */
1128static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1129 .master = &omap3xxx_l4_core_hwmod,
1130 .slave = &omap3xxx_timer11_hwmod,
1131 .clk = "gpt11_ick",
1132 .addr = omap3xxx_timer11_addrs,
1133 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1134 .user = OCP_USER_MPU | OCP_USER_SDMA,
1135};
1136
1137/* timer11 slave port */
1138static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1139 &omap3xxx_l4_core__timer11,
1140};
1141
1142/* timer11 hwmod */
1143static struct omap_hwmod omap3xxx_timer11_hwmod = {
1144 .name = "timer11",
1145 .mpu_irqs = omap3xxx_timer11_mpu_irqs,
1146 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1147 .main_clk = "gpt11_fck",
1148 .prcm = {
1149 .omap2 = {
1150 .prcm_reg_id = 1,
1151 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1152 .module_offs = CORE_MOD,
1153 .idlest_reg_id = 1,
1154 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1155 },
1156 },
1157 .slaves = omap3xxx_timer11_slaves,
1158 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1159 .class = &omap3xxx_timer_hwmod_class,
1160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1161};
1162
1163/* timer12*/
1164static struct omap_hwmod omap3xxx_timer12_hwmod;
1165static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1166 { .irq = 95, },
1167};
1168
1169static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1170 {
1171 .pa_start = 0x48304000,
1172 .pa_end = 0x48304000 + SZ_1K - 1,
1173 .flags = ADDR_TYPE_RT
1174 },
1175};
1176
1177/* l4_core -> timer12 */
1178static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1179 .master = &omap3xxx_l4_core_hwmod,
1180 .slave = &omap3xxx_timer12_hwmod,
1181 .clk = "gpt12_ick",
1182 .addr = omap3xxx_timer12_addrs,
1183 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1184 .user = OCP_USER_MPU | OCP_USER_SDMA,
1185};
1186
1187/* timer12 slave port */
1188static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1189 &omap3xxx_l4_core__timer12,
1190};
1191
1192/* timer12 hwmod */
1193static struct omap_hwmod omap3xxx_timer12_hwmod = {
1194 .name = "timer12",
1195 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1196 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1197 .main_clk = "gpt12_fck",
1198 .prcm = {
1199 .omap2 = {
1200 .prcm_reg_id = 1,
1201 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1202 .module_offs = WKUP_MOD,
1203 .idlest_reg_id = 1,
1204 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1205 },
1206 },
1207 .slaves = omap3xxx_timer12_slaves,
1208 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1209 .class = &omap3xxx_timer_hwmod_class,
1210 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1211};
1212
518/* l4_wkup -> wd_timer2 */ 1213/* l4_wkup -> wd_timer2 */
519static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { 1214static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
520 { 1215 {
@@ -589,6 +1284,11 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
589 .slaves = omap3xxx_wd_timer2_slaves, 1284 .slaves = omap3xxx_wd_timer2_slaves,
590 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), 1285 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
591 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1287 /*
1288 * XXX: Use software supervised mode, HW supervised smartidle seems to
1289 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1290 */
1291 .flags = HWMOD_SWSUP_SIDLE,
592}; 1292};
593 1293
594/* UART common */ 1294/* UART common */
@@ -1139,6 +1839,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1139 .flags = OMAP_FIREWALL_L4, 1839 .flags = OMAP_FIREWALL_L4,
1140 } 1840 }
1141 }, 1841 },
1842 .flags = OCPIF_SWSUP_IDLE,
1142 .user = OCP_USER_MPU | OCP_USER_SDMA, 1843 .user = OCP_USER_MPU | OCP_USER_SDMA,
1143}; 1844};
1144 1845
@@ -1729,6 +2430,437 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1729 .flags = HWMOD_NO_IDLEST, 2430 .flags = HWMOD_NO_IDLEST,
1730}; 2431};
1731 2432
2433/*
2434 * 'mcbsp' class
2435 * multi channel buffered serial port controller
2436 */
2437
2438static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2439 .sysc_offs = 0x008c,
2440 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2441 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2442 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2443 .sysc_fields = &omap_hwmod_sysc_type1,
2444 .clockact = 0x2,
2445};
2446
2447static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2448 .name = "mcbsp",
2449 .sysc = &omap3xxx_mcbsp_sysc,
2450 .rev = MCBSP_CONFIG_TYPE3,
2451};
2452
2453/* mcbsp1 */
2454static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2455 { .name = "irq", .irq = 16 },
2456 { .name = "tx", .irq = 59 },
2457 { .name = "rx", .irq = 60 },
2458};
2459
2460static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2461 { .name = "rx", .dma_req = 32 },
2462 { .name = "tx", .dma_req = 31 },
2463};
2464
2465static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2466 {
2467 .name = "mpu",
2468 .pa_start = 0x48074000,
2469 .pa_end = 0x480740ff,
2470 .flags = ADDR_TYPE_RT
2471 },
2472};
2473
2474/* l4_core -> mcbsp1 */
2475static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2476 .master = &omap3xxx_l4_core_hwmod,
2477 .slave = &omap3xxx_mcbsp1_hwmod,
2478 .clk = "mcbsp1_ick",
2479 .addr = omap3xxx_mcbsp1_addrs,
2480 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2481 .user = OCP_USER_MPU | OCP_USER_SDMA,
2482};
2483
2484/* mcbsp1 slave ports */
2485static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2486 &omap3xxx_l4_core__mcbsp1,
2487};
2488
2489static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2490 .name = "mcbsp1",
2491 .class = &omap3xxx_mcbsp_hwmod_class,
2492 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2493 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2494 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2495 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2496 .main_clk = "mcbsp1_fck",
2497 .prcm = {
2498 .omap2 = {
2499 .prcm_reg_id = 1,
2500 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2501 .module_offs = CORE_MOD,
2502 .idlest_reg_id = 1,
2503 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2504 },
2505 },
2506 .slaves = omap3xxx_mcbsp1_slaves,
2507 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2509};
2510
2511/* mcbsp2 */
2512static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2513 { .name = "irq", .irq = 17 },
2514 { .name = "tx", .irq = 62 },
2515 { .name = "rx", .irq = 63 },
2516};
2517
2518static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2519 { .name = "rx", .dma_req = 34 },
2520 { .name = "tx", .dma_req = 33 },
2521};
2522
2523static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2524 {
2525 .name = "mpu",
2526 .pa_start = 0x49022000,
2527 .pa_end = 0x490220ff,
2528 .flags = ADDR_TYPE_RT
2529 },
2530};
2531
2532/* l4_per -> mcbsp2 */
2533static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2534 .master = &omap3xxx_l4_per_hwmod,
2535 .slave = &omap3xxx_mcbsp2_hwmod,
2536 .clk = "mcbsp2_ick",
2537 .addr = omap3xxx_mcbsp2_addrs,
2538 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2540};
2541
2542/* mcbsp2 slave ports */
2543static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2544 &omap3xxx_l4_per__mcbsp2,
2545};
2546
2547static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2548 .sidetone = "mcbsp2_sidetone",
2549};
2550
2551static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2552 .name = "mcbsp2",
2553 .class = &omap3xxx_mcbsp_hwmod_class,
2554 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2555 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2556 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2557 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2558 .main_clk = "mcbsp2_fck",
2559 .prcm = {
2560 .omap2 = {
2561 .prcm_reg_id = 1,
2562 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2563 .module_offs = OMAP3430_PER_MOD,
2564 .idlest_reg_id = 1,
2565 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2566 },
2567 },
2568 .slaves = omap3xxx_mcbsp2_slaves,
2569 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2570 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2571 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2572};
2573
2574/* mcbsp3 */
2575static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2576 { .name = "irq", .irq = 22 },
2577 { .name = "tx", .irq = 89 },
2578 { .name = "rx", .irq = 90 },
2579};
2580
2581static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2582 { .name = "rx", .dma_req = 18 },
2583 { .name = "tx", .dma_req = 17 },
2584};
2585
2586static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2587 {
2588 .name = "mpu",
2589 .pa_start = 0x49024000,
2590 .pa_end = 0x490240ff,
2591 .flags = ADDR_TYPE_RT
2592 },
2593};
2594
2595/* l4_per -> mcbsp3 */
2596static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2597 .master = &omap3xxx_l4_per_hwmod,
2598 .slave = &omap3xxx_mcbsp3_hwmod,
2599 .clk = "mcbsp3_ick",
2600 .addr = omap3xxx_mcbsp3_addrs,
2601 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2602 .user = OCP_USER_MPU | OCP_USER_SDMA,
2603};
2604
2605/* mcbsp3 slave ports */
2606static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2607 &omap3xxx_l4_per__mcbsp3,
2608};
2609
2610static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2611 .sidetone = "mcbsp3_sidetone",
2612};
2613
2614static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2615 .name = "mcbsp3",
2616 .class = &omap3xxx_mcbsp_hwmod_class,
2617 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2618 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2619 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2620 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2621 .main_clk = "mcbsp3_fck",
2622 .prcm = {
2623 .omap2 = {
2624 .prcm_reg_id = 1,
2625 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2626 .module_offs = OMAP3430_PER_MOD,
2627 .idlest_reg_id = 1,
2628 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2629 },
2630 },
2631 .slaves = omap3xxx_mcbsp3_slaves,
2632 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2633 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2634 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2635};
2636
2637/* mcbsp4 */
2638static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2639 { .name = "irq", .irq = 23 },
2640 { .name = "tx", .irq = 54 },
2641 { .name = "rx", .irq = 55 },
2642};
2643
2644static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2645 { .name = "rx", .dma_req = 20 },
2646 { .name = "tx", .dma_req = 19 },
2647};
2648
2649static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2650 {
2651 .name = "mpu",
2652 .pa_start = 0x49026000,
2653 .pa_end = 0x490260ff,
2654 .flags = ADDR_TYPE_RT
2655 },
2656};
2657
2658/* l4_per -> mcbsp4 */
2659static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2660 .master = &omap3xxx_l4_per_hwmod,
2661 .slave = &omap3xxx_mcbsp4_hwmod,
2662 .clk = "mcbsp4_ick",
2663 .addr = omap3xxx_mcbsp4_addrs,
2664 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2665 .user = OCP_USER_MPU | OCP_USER_SDMA,
2666};
2667
2668/* mcbsp4 slave ports */
2669static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2670 &omap3xxx_l4_per__mcbsp4,
2671};
2672
2673static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2674 .name = "mcbsp4",
2675 .class = &omap3xxx_mcbsp_hwmod_class,
2676 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2677 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2678 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2679 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2680 .main_clk = "mcbsp4_fck",
2681 .prcm = {
2682 .omap2 = {
2683 .prcm_reg_id = 1,
2684 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2685 .module_offs = OMAP3430_PER_MOD,
2686 .idlest_reg_id = 1,
2687 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2688 },
2689 },
2690 .slaves = omap3xxx_mcbsp4_slaves,
2691 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2692 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2693};
2694
2695/* mcbsp5 */
2696static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2697 { .name = "irq", .irq = 27 },
2698 { .name = "tx", .irq = 81 },
2699 { .name = "rx", .irq = 82 },
2700};
2701
2702static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2703 { .name = "rx", .dma_req = 22 },
2704 { .name = "tx", .dma_req = 21 },
2705};
2706
2707static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2708 {
2709 .name = "mpu",
2710 .pa_start = 0x48096000,
2711 .pa_end = 0x480960ff,
2712 .flags = ADDR_TYPE_RT
2713 },
2714};
2715
2716/* l4_core -> mcbsp5 */
2717static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2718 .master = &omap3xxx_l4_core_hwmod,
2719 .slave = &omap3xxx_mcbsp5_hwmod,
2720 .clk = "mcbsp5_ick",
2721 .addr = omap3xxx_mcbsp5_addrs,
2722 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2723 .user = OCP_USER_MPU | OCP_USER_SDMA,
2724};
2725
2726/* mcbsp5 slave ports */
2727static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2728 &omap3xxx_l4_core__mcbsp5,
2729};
2730
2731static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2732 .name = "mcbsp5",
2733 .class = &omap3xxx_mcbsp_hwmod_class,
2734 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2735 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2736 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2737 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2738 .main_clk = "mcbsp5_fck",
2739 .prcm = {
2740 .omap2 = {
2741 .prcm_reg_id = 1,
2742 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2743 .module_offs = CORE_MOD,
2744 .idlest_reg_id = 1,
2745 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2746 },
2747 },
2748 .slaves = omap3xxx_mcbsp5_slaves,
2749 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2750 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2751};
2752/* 'mcbsp sidetone' class */
2753
2754static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2755 .sysc_offs = 0x0010,
2756 .sysc_flags = SYSC_HAS_AUTOIDLE,
2757 .sysc_fields = &omap_hwmod_sysc_type1,
2758};
2759
2760static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2761 .name = "mcbsp_sidetone",
2762 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2763};
2764
2765/* mcbsp2_sidetone */
2766static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2767 { .name = "irq", .irq = 4 },
2768};
2769
2770static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2771 {
2772 .name = "sidetone",
2773 .pa_start = 0x49028000,
2774 .pa_end = 0x490280ff,
2775 .flags = ADDR_TYPE_RT
2776 },
2777};
2778
2779/* l4_per -> mcbsp2_sidetone */
2780static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2781 .master = &omap3xxx_l4_per_hwmod,
2782 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2783 .clk = "mcbsp2_ick",
2784 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2785 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2786 .user = OCP_USER_MPU,
2787};
2788
2789/* mcbsp2_sidetone slave ports */
2790static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2791 &omap3xxx_l4_per__mcbsp2_sidetone,
2792};
2793
2794static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2795 .name = "mcbsp2_sidetone",
2796 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2797 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2798 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2799 .main_clk = "mcbsp2_fck",
2800 .prcm = {
2801 .omap2 = {
2802 .prcm_reg_id = 1,
2803 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2804 .module_offs = OMAP3430_PER_MOD,
2805 .idlest_reg_id = 1,
2806 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2807 },
2808 },
2809 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2810 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2811 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2812};
2813
2814/* mcbsp3_sidetone */
2815static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2816 { .name = "irq", .irq = 5 },
2817};
2818
2819static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2820 {
2821 .name = "sidetone",
2822 .pa_start = 0x4902A000,
2823 .pa_end = 0x4902A0ff,
2824 .flags = ADDR_TYPE_RT
2825 },
2826};
2827
2828/* l4_per -> mcbsp3_sidetone */
2829static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2830 .master = &omap3xxx_l4_per_hwmod,
2831 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2832 .clk = "mcbsp3_ick",
2833 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2834 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2835 .user = OCP_USER_MPU,
2836};
2837
2838/* mcbsp3_sidetone slave ports */
2839static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2840 &omap3xxx_l4_per__mcbsp3_sidetone,
2841};
2842
2843static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2844 .name = "mcbsp3_sidetone",
2845 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2846 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2847 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2848 .main_clk = "mcbsp3_fck",
2849 .prcm = {
2850 .omap2 = {
2851 .prcm_reg_id = 1,
2852 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2853 .module_offs = OMAP3430_PER_MOD,
2854 .idlest_reg_id = 1,
2855 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2856 },
2857 },
2858 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2859 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2860 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2861};
2862
2863
1732/* SR common */ 2864/* SR common */
1733static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 2865static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1734 .clkact_shift = 20, 2866 .clkact_shift = 20,
@@ -1858,6 +2990,74 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
1858 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 2990 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1859}; 2991};
1860 2992
2993/*
2994 * 'mailbox' class
2995 * mailbox module allowing communication between the on-chip processors
2996 * using a queued mailbox-interrupt mechanism.
2997 */
2998
2999static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3000 .rev_offs = 0x000,
3001 .sysc_offs = 0x010,
3002 .syss_offs = 0x014,
3003 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3004 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3005 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3006 .sysc_fields = &omap_hwmod_sysc_type1,
3007};
3008
3009static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3010 .name = "mailbox",
3011 .sysc = &omap3xxx_mailbox_sysc,
3012};
3013
3014static struct omap_hwmod omap3xxx_mailbox_hwmod;
3015static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3016 { .irq = 26 },
3017};
3018
3019static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3020 {
3021 .pa_start = 0x48094000,
3022 .pa_end = 0x480941ff,
3023 .flags = ADDR_TYPE_RT,
3024 },
3025};
3026
3027/* l4_core -> mailbox */
3028static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3029 .master = &omap3xxx_l4_core_hwmod,
3030 .slave = &omap3xxx_mailbox_hwmod,
3031 .addr = omap3xxx_mailbox_addrs,
3032 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3033 .user = OCP_USER_MPU | OCP_USER_SDMA,
3034};
3035
3036/* mailbox slave ports */
3037static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3038 &omap3xxx_l4_core__mailbox,
3039};
3040
3041static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3042 .name = "mailbox",
3043 .class = &omap3xxx_mailbox_hwmod_class,
3044 .mpu_irqs = omap3xxx_mailbox_irqs,
3045 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3046 .main_clk = "mailboxes_ick",
3047 .prcm = {
3048 .omap2 = {
3049 .prcm_reg_id = 1,
3050 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3051 .module_offs = CORE_MOD,
3052 .idlest_reg_id = 1,
3053 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3054 },
3055 },
3056 .slaves = omap3xxx_mailbox_slaves,
3057 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3058 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3059};
3060
1861/* l4 core -> mcspi1 interface */ 3061/* l4 core -> mcspi1 interface */
1862static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { 3062static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
1863 { 3063 {
@@ -2212,13 +3412,181 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2212 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) 3412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
2213}; 3413};
2214 3414
3415/* MMC/SD/SDIO common */
3416
3417static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3418 .rev_offs = 0x1fc,
3419 .sysc_offs = 0x10,
3420 .syss_offs = 0x14,
3421 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3422 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3423 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3424 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3425 .sysc_fields = &omap_hwmod_sysc_type1,
3426};
3427
3428static struct omap_hwmod_class omap34xx_mmc_class = {
3429 .name = "mmc",
3430 .sysc = &omap34xx_mmc_sysc,
3431};
3432
3433/* MMC/SD/SDIO1 */
3434
3435static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3436 { .irq = 83, },
3437};
3438
3439static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3440 { .name = "tx", .dma_req = 61, },
3441 { .name = "rx", .dma_req = 62, },
3442};
3443
3444static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3445 { .role = "dbck", .clk = "omap_32k_fck", },
3446};
3447
3448static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3449 &omap3xxx_l4_core__mmc1,
3450};
3451
3452static struct omap_mmc_dev_attr mmc1_dev_attr = {
3453 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3454};
3455
3456static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3457 .name = "mmc1",
3458 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3459 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3460 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3461 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3462 .opt_clks = omap34xx_mmc1_opt_clks,
3463 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3464 .main_clk = "mmchs1_fck",
3465 .prcm = {
3466 .omap2 = {
3467 .module_offs = CORE_MOD,
3468 .prcm_reg_id = 1,
3469 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3470 .idlest_reg_id = 1,
3471 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3472 },
3473 },
3474 .dev_attr = &mmc1_dev_attr,
3475 .slaves = omap3xxx_mmc1_slaves,
3476 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3477 .class = &omap34xx_mmc_class,
3478 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3479};
3480
3481/* MMC/SD/SDIO2 */
3482
3483static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3484 { .irq = INT_24XX_MMC2_IRQ, },
3485};
3486
3487static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3488 { .name = "tx", .dma_req = 47, },
3489 { .name = "rx", .dma_req = 48, },
3490};
3491
3492static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3493 { .role = "dbck", .clk = "omap_32k_fck", },
3494};
3495
3496static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3497 &omap3xxx_l4_core__mmc2,
3498};
3499
3500static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3501 .name = "mmc2",
3502 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3503 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3504 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3505 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3506 .opt_clks = omap34xx_mmc2_opt_clks,
3507 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3508 .main_clk = "mmchs2_fck",
3509 .prcm = {
3510 .omap2 = {
3511 .module_offs = CORE_MOD,
3512 .prcm_reg_id = 1,
3513 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3514 .idlest_reg_id = 1,
3515 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3516 },
3517 },
3518 .slaves = omap3xxx_mmc2_slaves,
3519 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3520 .class = &omap34xx_mmc_class,
3521 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3522};
3523
3524/* MMC/SD/SDIO3 */
3525
3526static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3527 { .irq = 94, },
3528};
3529
3530static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3531 { .name = "tx", .dma_req = 77, },
3532 { .name = "rx", .dma_req = 78, },
3533};
3534
3535static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3536 { .role = "dbck", .clk = "omap_32k_fck", },
3537};
3538
3539static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3540 &omap3xxx_l4_core__mmc3,
3541};
3542
3543static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3544 .name = "mmc3",
3545 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3546 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3547 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3548 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3549 .opt_clks = omap34xx_mmc3_opt_clks,
3550 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3551 .main_clk = "mmchs3_fck",
3552 .prcm = {
3553 .omap2 = {
3554 .prcm_reg_id = 1,
3555 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3556 .idlest_reg_id = 1,
3557 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3558 },
3559 },
3560 .slaves = omap3xxx_mmc3_slaves,
3561 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3562 .class = &omap34xx_mmc_class,
3563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3564};
3565
2215static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 3566static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2216 &omap3xxx_l3_main_hwmod, 3567 &omap3xxx_l3_main_hwmod,
2217 &omap3xxx_l4_core_hwmod, 3568 &omap3xxx_l4_core_hwmod,
2218 &omap3xxx_l4_per_hwmod, 3569 &omap3xxx_l4_per_hwmod,
2219 &omap3xxx_l4_wkup_hwmod, 3570 &omap3xxx_l4_wkup_hwmod,
3571 &omap3xxx_mmc1_hwmod,
3572 &omap3xxx_mmc2_hwmod,
3573 &omap3xxx_mmc3_hwmod,
2220 &omap3xxx_mpu_hwmod, 3574 &omap3xxx_mpu_hwmod,
2221 &omap3xxx_iva_hwmod, 3575 &omap3xxx_iva_hwmod,
3576
3577 &omap3xxx_timer1_hwmod,
3578 &omap3xxx_timer2_hwmod,
3579 &omap3xxx_timer3_hwmod,
3580 &omap3xxx_timer4_hwmod,
3581 &omap3xxx_timer5_hwmod,
3582 &omap3xxx_timer6_hwmod,
3583 &omap3xxx_timer7_hwmod,
3584 &omap3xxx_timer8_hwmod,
3585 &omap3xxx_timer9_hwmod,
3586 &omap3xxx_timer10_hwmod,
3587 &omap3xxx_timer11_hwmod,
3588 &omap3xxx_timer12_hwmod,
3589
2222 &omap3xxx_wd_timer2_hwmod, 3590 &omap3xxx_wd_timer2_hwmod,
2223 &omap3xxx_uart1_hwmod, 3591 &omap3xxx_uart1_hwmod,
2224 &omap3xxx_uart2_hwmod, 3592 &omap3xxx_uart2_hwmod,
@@ -2253,6 +3621,18 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2253 /* dma_system class*/ 3621 /* dma_system class*/
2254 &omap3xxx_dma_system_hwmod, 3622 &omap3xxx_dma_system_hwmod,
2255 3623
3624 /* mcbsp class */
3625 &omap3xxx_mcbsp1_hwmod,
3626 &omap3xxx_mcbsp2_hwmod,
3627 &omap3xxx_mcbsp3_hwmod,
3628 &omap3xxx_mcbsp4_hwmod,
3629 &omap3xxx_mcbsp5_hwmod,
3630 &omap3xxx_mcbsp2_sidetone_hwmod,
3631 &omap3xxx_mcbsp3_sidetone_hwmod,
3632
3633 /* mailbox class */
3634 &omap3xxx_mailbox_hwmod,
3635
2256 /* mcspi class */ 3636 /* mcspi class */
2257 &omap34xx_mcspi1, 3637 &omap34xx_mcspi1,
2258 &omap34xx_mcspi2, 3638 &omap34xx_mcspi2,
@@ -2270,5 +3650,5 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2270 3650
2271int __init omap3xxx_hwmod_init(void) 3651int __init omap3xxx_hwmod_init(void)
2272{ 3652{
2273 return omap_hwmod_init(omap3xxx_hwmods); 3653 return omap_hwmod_register(omap3xxx_hwmods);
2274} 3654}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 79a860178913..3e88dd3f8ef3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -25,6 +25,8 @@
25#include <plat/gpio.h> 25#include <plat/gpio.h>
26#include <plat/dma.h> 26#include <plat/dma.h>
27#include <plat/mcspi.h> 27#include <plat/mcspi.h>
28#include <plat/mcbsp.h>
29#include <plat/mmc.h>
28 30
29#include "omap_hwmod_common_data.h" 31#include "omap_hwmod_common_data.h"
30 32
@@ -262,11 +264,27 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
262 .user = OCP_USER_MPU | OCP_USER_SDMA, 264 .user = OCP_USER_MPU | OCP_USER_SDMA,
263}; 265};
264 266
267/* L3 target configuration and error log registers */
268static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
269 { .irq = 9 + OMAP44XX_IRQ_GIC_START },
270 { .irq = 10 + OMAP44XX_IRQ_GIC_START },
271};
272
273static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
274 {
275 .pa_start = 0x44000000,
276 .pa_end = 0x44000fff,
277 .flags = ADDR_TYPE_RT,
278 },
279};
280
265/* mpu -> l3_main_1 */ 281/* mpu -> l3_main_1 */
266static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 282static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
267 .master = &omap44xx_mpu_hwmod, 283 .master = &omap44xx_mpu_hwmod,
268 .slave = &omap44xx_l3_main_1_hwmod, 284 .slave = &omap44xx_l3_main_1_hwmod,
269 .clk = "l3_div_ck", 285 .clk = "l3_div_ck",
286 .addr = omap44xx_l3_main_1_addrs,
287 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
270 .user = OCP_USER_MPU | OCP_USER_SDMA, 288 .user = OCP_USER_MPU | OCP_USER_SDMA,
271}; 289};
272 290
@@ -284,6 +302,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
284static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 302static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
285 .name = "l3_main_1", 303 .name = "l3_main_1",
286 .class = &omap44xx_l3_hwmod_class, 304 .class = &omap44xx_l3_hwmod_class,
305 .mpu_irqs = omap44xx_l3_targ_irqs,
306 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
287 .slaves = omap44xx_l3_main_1_slaves, 307 .slaves = omap44xx_l3_main_1_slaves,
288 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 308 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 309 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -330,11 +350,21 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
330 .user = OCP_USER_MPU | OCP_USER_SDMA, 350 .user = OCP_USER_MPU | OCP_USER_SDMA,
331}; 351};
332 352
353static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
354 {
355 .pa_start = 0x44800000,
356 .pa_end = 0x44801fff,
357 .flags = ADDR_TYPE_RT,
358 },
359};
360
333/* l3_main_1 -> l3_main_2 */ 361/* l3_main_1 -> l3_main_2 */
334static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { 362static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
335 .master = &omap44xx_l3_main_1_hwmod, 363 .master = &omap44xx_l3_main_1_hwmod,
336 .slave = &omap44xx_l3_main_2_hwmod, 364 .slave = &omap44xx_l3_main_2_hwmod,
337 .clk = "l3_div_ck", 365 .clk = "l3_div_ck",
366 .addr = omap44xx_l3_main_2_addrs,
367 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
338 .user = OCP_USER_MPU | OCP_USER_SDMA, 368 .user = OCP_USER_MPU | OCP_USER_SDMA,
339}; 369};
340 370
@@ -375,11 +405,21 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
375}; 405};
376 406
377/* l3_main_3 interface data */ 407/* l3_main_3 interface data */
408static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
409 {
410 .pa_start = 0x45000000,
411 .pa_end = 0x45000fff,
412 .flags = ADDR_TYPE_RT,
413 },
414};
415
378/* l3_main_1 -> l3_main_3 */ 416/* l3_main_1 -> l3_main_3 */
379static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { 417static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
380 .master = &omap44xx_l3_main_1_hwmod, 418 .master = &omap44xx_l3_main_1_hwmod,
381 .slave = &omap44xx_l3_main_3_hwmod, 419 .slave = &omap44xx_l3_main_3_hwmod,
382 .clk = "l3_div_ck", 420 .clk = "l3_div_ck",
421 .addr = omap44xx_l3_main_3_addrs,
422 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
383 .user = OCP_USER_MPU | OCP_USER_SDMA, 423 .user = OCP_USER_MPU | OCP_USER_SDMA,
384}; 424};
385 425
@@ -2737,6 +2777,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2737static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { 2777static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2738 .name = "mcbsp", 2778 .name = "mcbsp",
2739 .sysc = &omap44xx_mcbsp_sysc, 2779 .sysc = &omap44xx_mcbsp_sysc,
2780 .rev = MCBSP_CONFIG_TYPE4,
2740}; 2781};
2741 2782
2742/* mcbsp1 */ 2783/* mcbsp1 */
@@ -2752,6 +2793,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2752 2793
2753static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { 2794static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2754 { 2795 {
2796 .name = "mpu",
2755 .pa_start = 0x40122000, 2797 .pa_start = 0x40122000,
2756 .pa_end = 0x401220ff, 2798 .pa_end = 0x401220ff,
2757 .flags = ADDR_TYPE_RT 2799 .flags = ADDR_TYPE_RT
@@ -2770,6 +2812,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2770 2812
2771static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { 2813static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2772 { 2814 {
2815 .name = "dma",
2773 .pa_start = 0x49022000, 2816 .pa_start = 0x49022000,
2774 .pa_end = 0x490220ff, 2817 .pa_end = 0x490220ff,
2775 .flags = ADDR_TYPE_RT 2818 .flags = ADDR_TYPE_RT
@@ -2823,6 +2866,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2823 2866
2824static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { 2867static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2825 { 2868 {
2869 .name = "mpu",
2826 .pa_start = 0x40124000, 2870 .pa_start = 0x40124000,
2827 .pa_end = 0x401240ff, 2871 .pa_end = 0x401240ff,
2828 .flags = ADDR_TYPE_RT 2872 .flags = ADDR_TYPE_RT
@@ -2841,6 +2885,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2841 2885
2842static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { 2886static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2843 { 2887 {
2888 .name = "dma",
2844 .pa_start = 0x49024000, 2889 .pa_start = 0x49024000,
2845 .pa_end = 0x490240ff, 2890 .pa_end = 0x490240ff,
2846 .flags = ADDR_TYPE_RT 2891 .flags = ADDR_TYPE_RT
@@ -2894,6 +2939,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2894 2939
2895static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { 2940static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2896 { 2941 {
2942 .name = "mpu",
2897 .pa_start = 0x40126000, 2943 .pa_start = 0x40126000,
2898 .pa_end = 0x401260ff, 2944 .pa_end = 0x401260ff,
2899 .flags = ADDR_TYPE_RT 2945 .flags = ADDR_TYPE_RT
@@ -2912,6 +2958,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2912 2958
2913static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { 2959static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2914 { 2960 {
2961 .name = "dma",
2915 .pa_start = 0x49026000, 2962 .pa_start = 0x49026000,
2916 .pa_end = 0x490260ff, 2963 .pa_end = 0x490260ff,
2917 .flags = ADDR_TYPE_RT 2964 .flags = ADDR_TYPE_RT
@@ -3383,6 +3430,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3383}; 3430};
3384 3431
3385/* mmc1 */ 3432/* mmc1 */
3433
3386static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { 3434static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3387 { .irq = 83 + OMAP44XX_IRQ_GIC_START }, 3435 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3388}; 3436};
@@ -3420,6 +3468,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3420 &omap44xx_l4_per__mmc1, 3468 &omap44xx_l4_per__mmc1,
3421}; 3469};
3422 3470
3471/* mmc1 dev_attr */
3472static struct omap_mmc_dev_attr mmc1_dev_attr = {
3473 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3474};
3475
3423static struct omap_hwmod omap44xx_mmc1_hwmod = { 3476static struct omap_hwmod omap44xx_mmc1_hwmod = {
3424 .name = "mmc1", 3477 .name = "mmc1",
3425 .class = &omap44xx_mmc_hwmod_class, 3478 .class = &omap44xx_mmc_hwmod_class,
@@ -3433,6 +3486,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
3433 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 3486 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3434 }, 3487 },
3435 }, 3488 },
3489 .dev_attr = &mmc1_dev_attr,
3436 .slaves = omap44xx_mmc1_slaves, 3490 .slaves = omap44xx_mmc1_slaves,
3437 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), 3491 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3438 .masters = omap44xx_mmc1_masters, 3492 .masters = omap44xx_mmc1_masters,
@@ -3989,7 +4043,6 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
3989static struct omap_hwmod omap44xx_timer1_hwmod = { 4043static struct omap_hwmod omap44xx_timer1_hwmod = {
3990 .name = "timer1", 4044 .name = "timer1",
3991 .class = &omap44xx_timer_1ms_hwmod_class, 4045 .class = &omap44xx_timer_1ms_hwmod_class,
3992 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3993 .mpu_irqs = omap44xx_timer1_irqs, 4046 .mpu_irqs = omap44xx_timer1_irqs,
3994 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), 4047 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
3995 .main_clk = "timer1_fck", 4048 .main_clk = "timer1_fck",
@@ -5077,11 +5130,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5077 &omap44xx_mcspi4_hwmod, 5130 &omap44xx_mcspi4_hwmod,
5078 5131
5079 /* mmc class */ 5132 /* mmc class */
5080/* &omap44xx_mmc1_hwmod, */ 5133 &omap44xx_mmc1_hwmod,
5081/* &omap44xx_mmc2_hwmod, */ 5134 &omap44xx_mmc2_hwmod,
5082/* &omap44xx_mmc3_hwmod, */ 5135 &omap44xx_mmc3_hwmod,
5083/* &omap44xx_mmc4_hwmod, */ 5136 &omap44xx_mmc4_hwmod,
5084/* &omap44xx_mmc5_hwmod, */ 5137 &omap44xx_mmc5_hwmod,
5085 5138
5086 /* mpu class */ 5139 /* mpu class */
5087 &omap44xx_mpu_hwmod, 5140 &omap44xx_mpu_hwmod,
@@ -5125,6 +5178,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5125 5178
5126int __init omap44xx_hwmod_init(void) 5179int __init omap44xx_hwmod_init(void)
5127{ 5180{
5128 return omap_hwmod_init(omap44xx_hwmods); 5181 return omap_hwmod_register(omap44xx_hwmods);
5129} 5182}
5130 5183
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
new file mode 100644
index 000000000000..82632c24076f
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -0,0 +1,253 @@
1/*
2 * OMAP4XXX L3 Interconnect error handling driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#include <linux/init.h>
24#include <linux/io.h>
25#include <linux/platform_device.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29
30#include "omap_l3_noc.h"
31
32/*
33 * Interrupt Handler for L3 error detection.
34 * 1) Identify the L3 clockdomain partition to which the error belongs to.
35 * 2) Identify the slave where the error information is logged
36 * 3) Print the logged information.
37 * 4) Add dump stack to provide kernel trace.
38 *
39 * Two Types of errors :
40 * 1) Custom errors in L3 :
41 * Target like DMM/FW/EMIF generates SRESP=ERR error
42 * 2) Standard L3 error:
43 * - Unsupported CMD.
44 * L3 tries to access target while it is idle
45 * - OCP disconnect.
46 * - Address hole error:
47 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
48 * do not have connectivity, the error is logged in
49 * their default target which is DMM2.
50 *
51 * On High Secure devices, firewall errors are possible and those
52 * can be trapped as well. But the trapping is implemented as part
53 * secure software and hence need not be implemented here.
54 */
55static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{
57
58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j;
60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg;
62 u32 base, slave_addr, clear;
63 char *source_name;
64
65 /* Get the Type of interrupt */
66 if (irq == l3->app_irq)
67 inttype = L3_APPLICATION_ERROR;
68 else
69 inttype = L3_DEBUG_ERROR;
70
71 for (i = 0; i < L3_MODULES; i++) {
72 /*
73 * Read the regerr register of the clock domain
74 * to determine the source
75 */
76 base = (u32)l3->l3_base[i];
77 err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
78
79 /* Get the corresponding error and analyse */
80 if (err_reg) {
81 /* Identify the source from control status register */
82 for (j = 0; !(err_reg & (1 << j)); j++)
83 ;
84
85 err_src = j;
86 /* Read the stderrlog_main_source from clk domain */
87 std_err_main_addr = base + (*(l3_targ[i] + err_src));
88 std_err_main = readl(std_err_main_addr);
89
90 switch ((std_err_main & CUSTOM_ERROR)) {
91 case STANDARD_ERROR:
92 source_name =
93 l3_targ_stderrlog_main_name[i][err_src];
94
95 slave_addr = std_err_main_addr +
96 L3_SLAVE_ADDRESS_OFFSET;
97 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
98 source_name, readl(slave_addr));
99 /* clear the std error log*/
100 clear = std_err_main | CLEAR_STDERR_LOG;
101 writel(clear, std_err_main_addr);
102 break;
103
104 case CUSTOM_ERROR:
105 source_name =
106 l3_targ_stderrlog_main_name[i][err_src];
107
108 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
109 source_name);
110 /* clear the std error log*/
111 clear = std_err_main | CLEAR_STDERR_LOG;
112 writel(clear, std_err_main_addr);
113 break;
114
115 default:
116 /* Nothing to be handled here as of now */
117 break;
118 }
119 /* Error found so break the for loop */
120 break;
121 }
122 }
123 return IRQ_HANDLED;
124}
125
126static int __init omap4_l3_probe(struct platform_device *pdev)
127{
128 static struct omap4_l3 *l3;
129 struct resource *res;
130 int ret;
131 int irq;
132
133 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
134 if (!l3)
135 ret = -ENOMEM;
136
137 platform_set_drvdata(pdev, l3);
138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
139 if (!res) {
140 dev_err(&pdev->dev, "couldn't find resource 0\n");
141 ret = -ENODEV;
142 goto err1;
143 }
144
145 l3->l3_base[0] = ioremap(res->start, resource_size(res));
146 if (!(l3->l3_base[0])) {
147 dev_err(&pdev->dev, "ioremap failed\n");
148 ret = -ENOMEM;
149 goto err2;
150 }
151
152 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
153 if (!res) {
154 dev_err(&pdev->dev, "couldn't find resource 1\n");
155 ret = -ENODEV;
156 goto err3;
157 }
158
159 l3->l3_base[1] = ioremap(res->start, resource_size(res));
160 if (!(l3->l3_base[1])) {
161 dev_err(&pdev->dev, "ioremap failed\n");
162 ret = -ENOMEM;
163 goto err4;
164 }
165
166 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
167 if (!res) {
168 dev_err(&pdev->dev, "couldn't find resource 2\n");
169 ret = -ENODEV;
170 goto err5;
171 }
172
173 l3->l3_base[2] = ioremap(res->start, resource_size(res));
174 if (!(l3->l3_base[2])) {
175 dev_err(&pdev->dev, "ioremap failed\n");
176 ret = -ENOMEM;
177 goto err6;
178 }
179
180 /*
181 * Setup interrupt Handlers
182 */
183 irq = platform_get_irq(pdev, 0);
184 ret = request_irq(irq,
185 l3_interrupt_handler,
186 IRQF_DISABLED, "l3-dbg-irq", l3);
187 if (ret) {
188 pr_crit("L3: request_irq failed to register for 0x%x\n",
189 OMAP44XX_IRQ_L3_DBG);
190 goto err7;
191 }
192 l3->debug_irq = irq;
193
194 irq = platform_get_irq(pdev, 1);
195 ret = request_irq(irq,
196 l3_interrupt_handler,
197 IRQF_DISABLED, "l3-app-irq", l3);
198 if (ret) {
199 pr_crit("L3: request_irq failed to register for 0x%x\n",
200 OMAP44XX_IRQ_L3_APP);
201 goto err8;
202 }
203 l3->app_irq = irq;
204
205 goto err0;
206err8:
207err7:
208 iounmap(l3->l3_base[2]);
209err6:
210err5:
211 iounmap(l3->l3_base[1]);
212err4:
213err3:
214 iounmap(l3->l3_base[0]);
215err2:
216err1:
217 kfree(l3);
218err0:
219 return ret;
220}
221
222static int __exit omap4_l3_remove(struct platform_device *pdev)
223{
224 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
225
226 free_irq(l3->app_irq, l3);
227 free_irq(l3->debug_irq, l3);
228 iounmap(l3->l3_base[0]);
229 iounmap(l3->l3_base[1]);
230 iounmap(l3->l3_base[2]);
231 kfree(l3);
232
233 return 0;
234}
235
236static struct platform_driver omap4_l3_driver = {
237 .remove = __exit_p(omap4_l3_remove),
238 .driver = {
239 .name = "omap_l3_noc",
240 },
241};
242
243static int __init omap4_l3_init(void)
244{
245 return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
246}
247postcore_initcall_sync(omap4_l3_init);
248
249static void __exit omap4_l3_exit(void)
250{
251 platform_driver_unregister(&omap4_l3_driver);
252}
253module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
new file mode 100644
index 000000000000..359b83348aed
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -0,0 +1,132 @@
1 /*
2 * OMAP4XXX L3 Interconnect error handling driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1
39
40u32 l3_flagmux[L3_MODULES] = {
41 0x50C,
42 0x100C,
43 0X020C
44};
45
46/*
47 * L3 Target standard Error register offsets
48 */
49u32 l3_targ_stderrlog_main_clk1[] = {
50 0x148, /* DMM1 */
51 0x248, /* DMM2 */
52 0x348, /* ABE */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55};
56
57u32 l3_targ_stderrlog_main_clk2[] = {
58 0x548, /* CORTEX M3 */
59 0x348, /* DSS */
60 0x148, /* GPMC */
61 0x448, /* ISS */
62 0x748, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/
65 0x248, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */
68 0x848, /* SL2 */
69 0x1648, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */
74 0xA48, /* L4 PER1*/
75 0xB48 /* L4 PER2*/
76};
77
78u32 l3_targ_stderrlog_main_clk3[] = {
79 0x0148 /* EMUSS */
80};
81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
83 {
84 "DMM1",
85 "DMM2",
86 "ABE",
87 "L4CFG",
88 "CLK2 PWR DISC",
89 },
90 {
91 "CORTEX M3" ,
92 "DSS ",
93 "GPMC ",
94 "ISS ",
95 "IVAHD ",
96 "AES1",
97 "L4 PER0",
98 "OCMRAM ",
99 "GPMC sERROR",
100 "SGX ",
101 "SL2 ",
102 "C2C ",
103 "PWR DISC CLK1",
104 "SHA1",
105 "AES2",
106 "L4 PER3",
107 "L4 PER1",
108 "L4 PER2",
109 },
110 {
111 "EMUSS",
112 },
113};
114
115u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1,
117 l3_targ_stderrlog_main_clk2,
118 l3_targ_stderrlog_main_clk3,
119};
120
121struct omap4_l3 {
122 struct device *dev;
123 struct clk *ick;
124
125 /* memory base */
126 void __iomem *l3_base[4];
127
128 int debug_irq;
129 int app_irq;
130};
131
132#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
new file mode 100644
index 000000000000..265bff3acb9e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -0,0 +1,314 @@
1 /*
2 * OMAP3XXX L3 Interconnect Driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24
25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include "omap_l3_smx.h"
31
32static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
33{
34 return __raw_readll(base + reg);
35}
36
37static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
38{
39 __raw_writell(value, base + reg);
40}
41
42static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
43{
44 return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
45}
46
47static inline u32 omap3_l3_decode_addr(u64 error_addr)
48{
49 return error_addr & 0xffffffff;
50}
51
52static inline unsigned omap3_l3_decode_cmd(u64 error)
53{
54 return (error & 0x07) >> L3_ERROR_LOG_CMD;
55}
56
57static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
58{
59 return (error & 0xff00) >> L3_ERROR_LOG_INITID;
60}
61
62static inline unsigned omap3_l3_decode_req_info(u64 error)
63{
64 return (error >> 32) & 0xffff;
65}
66
67static char *omap3_l3_code_string(u8 code)
68{
69 switch (code) {
70 case OMAP_L3_CODE_NOERROR:
71 return "No Error";
72 case OMAP_L3_CODE_UNSUP_CMD:
73 return "Unsupported Command";
74 case OMAP_L3_CODE_ADDR_HOLE:
75 return "Address Hole";
76 case OMAP_L3_CODE_PROTECT_VIOLATION:
77 return "Protection Violation";
78 case OMAP_L3_CODE_IN_BAND_ERR:
79 return "In-band Error";
80 case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
81 return "Request Timeout Not Accepted";
82 case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
83 return "Request Timeout, no response";
84 default:
85 return "UNKNOWN error";
86 }
87}
88
89static char *omap3_l3_initiator_string(u8 initid)
90{
91 switch (initid) {
92 case OMAP_L3_LCD:
93 return "LCD";
94 case OMAP_L3_SAD2D:
95 return "SAD2D";
96 case OMAP_L3_IA_MPU_SS_1:
97 case OMAP_L3_IA_MPU_SS_2:
98 case OMAP_L3_IA_MPU_SS_3:
99 case OMAP_L3_IA_MPU_SS_4:
100 case OMAP_L3_IA_MPU_SS_5:
101 return "MPU";
102 case OMAP_L3_IA_IVA_SS_1:
103 case OMAP_L3_IA_IVA_SS_2:
104 case OMAP_L3_IA_IVA_SS_3:
105 return "IVA_SS";
106 case OMAP_L3_IA_IVA_SS_DMA_1:
107 case OMAP_L3_IA_IVA_SS_DMA_2:
108 case OMAP_L3_IA_IVA_SS_DMA_3:
109 case OMAP_L3_IA_IVA_SS_DMA_4:
110 case OMAP_L3_IA_IVA_SS_DMA_5:
111 case OMAP_L3_IA_IVA_SS_DMA_6:
112 return "IVA_SS_DMA";
113 case OMAP_L3_IA_SGX:
114 return "SGX";
115 case OMAP_L3_IA_CAM_1:
116 case OMAP_L3_IA_CAM_2:
117 case OMAP_L3_IA_CAM_3:
118 return "CAM";
119 case OMAP_L3_IA_DAP:
120 return "DAP";
121 case OMAP_L3_SDMA_WR_1:
122 case OMAP_L3_SDMA_WR_2:
123 return "SDMA_WR";
124 case OMAP_L3_SDMA_RD_1:
125 case OMAP_L3_SDMA_RD_2:
126 case OMAP_L3_SDMA_RD_3:
127 case OMAP_L3_SDMA_RD_4:
128 return "SDMA_RD";
129 case OMAP_L3_USBOTG:
130 return "USB_OTG";
131 case OMAP_L3_USBHOST:
132 return "USB_HOST";
133 default:
134 return "UNKNOWN Initiator";
135 }
136}
137
138/**
139 * omap3_l3_block_irq - handles a register block's irq
140 * @l3: struct omap3_l3 *
141 * @base: register block base address
142 * @error: L3_ERROR_LOG register of our block
143 *
144 * Called in hard-irq context. Caller should take care of locking
145 *
146 * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
147 * Analysis Sequence, we are following that sequence here, please
148 * refer to that Figure for more information on the subject.
149 */
150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
151 u64 error, int error_addr)
152{
153 u8 code = omap3_l3_decode_error_code(error);
154 u8 initid = omap3_l3_decode_initid(error);
155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr);
157
158 WARN(true, "%s Error seen by %s %s at address %x\n",
159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "",
162 address);
163
164 return IRQ_HANDLED;
165}
166
167static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
168{
169 struct omap3_l3 *l3 = _l3;
170
171 u64 status, clear;
172 u64 error;
173 u64 error_addr;
174 u64 err_source = 0;
175 void __iomem *base;
176 int int_type;
177
178 irqreturn_t ret = IRQ_NONE;
179
180 if (irq == l3->app_irq)
181 int_type = L3_APPLICATION_ERROR;
182 else
183 int_type = L3_DEBUG_ERROR;
184
185 if (!int_type) {
186 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
187 /*
188 * if we have a timeout error, there's nothing we can
189 * do besides rebooting the board. So let's BUG on any
190 * of such errors and handle the others. timeout error
191 * is severe and not expected to occur.
192 */
193 BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
194 } else {
195 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
196 /* No timeout error for debug sources */
197 }
198
199 base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source)));
200
201 /* identify the error source */
202 for (err_source = 0; !(status & (1 << err_source)); err_source++)
203 ;
204 error = omap3_l3_readll(base, L3_ERROR_LOG);
205
206 if (error) {
207 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
208
209 ret |= omap3_l3_block_irq(l3, error, error_addr);
210 }
211
212 /* Clear the status register */
213 clear = ((L3_AGENT_STATUS_CLEAR_IA << int_type) |
214 (L3_AGENT_STATUS_CLEAR_TA));
215
216 omap3_l3_writell(base, L3_AGENT_STATUS, clear);
217
218 /* clear the error log register */
219 omap3_l3_writell(base, L3_ERROR_LOG, error);
220
221 return ret;
222}
223
224static int __init omap3_l3_probe(struct platform_device *pdev)
225{
226 struct omap3_l3 *l3;
227 struct resource *res;
228 int ret;
229 int irq;
230
231 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
232 if (!l3) {
233 ret = -ENOMEM;
234 goto err0;
235 }
236
237 platform_set_drvdata(pdev, l3);
238
239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240 if (!res) {
241 dev_err(&pdev->dev, "couldn't find resource\n");
242 ret = -ENODEV;
243 goto err1;
244 }
245 l3->rt = ioremap(res->start, resource_size(res));
246 if (!(l3->rt)) {
247 dev_err(&pdev->dev, "ioremap failed\n");
248 ret = -ENOMEM;
249 goto err2;
250 }
251
252 irq = platform_get_irq(pdev, 0);
253 ret = request_irq(irq, omap3_l3_app_irq,
254 IRQF_DISABLED | IRQF_TRIGGER_RISING,
255 "l3-debug-irq", l3);
256 if (ret) {
257 dev_err(&pdev->dev, "couldn't request debug irq\n");
258 goto err3;
259 }
260 l3->debug_irq = irq;
261
262 irq = platform_get_irq(pdev, 1);
263 ret = request_irq(irq, omap3_l3_app_irq,
264 IRQF_DISABLED | IRQF_TRIGGER_RISING,
265 "l3-app-irq", l3);
266
267 if (ret) {
268 dev_err(&pdev->dev, "couldn't request app irq\n");
269 goto err4;
270 }
271
272 l3->app_irq = irq;
273 goto err0;
274
275err4:
276err3:
277 iounmap(l3->rt);
278err2:
279err1:
280 kfree(l3);
281err0:
282 return ret;
283}
284
285static int __exit omap3_l3_remove(struct platform_device *pdev)
286{
287 struct omap3_l3 *l3 = platform_get_drvdata(pdev);
288
289 free_irq(l3->app_irq, l3);
290 free_irq(l3->debug_irq, l3);
291 iounmap(l3->rt);
292 kfree(l3);
293
294 return 0;
295}
296
297static struct platform_driver omap3_l3_driver = {
298 .remove = __exit_p(omap3_l3_remove),
299 .driver = {
300 .name = "omap_l3_smx",
301 },
302};
303
304static int __init omap3_l3_init(void)
305{
306 return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
307}
308postcore_initcall_sync(omap3_l3_init);
309
310static void __exit omap3_l3_exit(void)
311{
312 platform_driver_unregister(&omap3_l3_driver);
313}
314module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
new file mode 100644
index 000000000000..ba2ed9a850cc
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -0,0 +1,338 @@
1 /*
2 * OMAP3XXX L3 Interconnect Driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26
27/* Register definitions. All 64-bit wide */
28#define L3_COMPONENT 0x000
29#define L3_CORE 0x018
30#define L3_AGENT_CONTROL 0x020
31#define L3_AGENT_STATUS 0x028
32#define L3_ERROR_LOG 0x058
33
34#define L3_ERROR_LOG_MULTI (1 << 31)
35#define L3_ERROR_LOG_SECONDARY (1 << 30)
36
37#define L3_ERROR_LOG_ADDR 0x060
38
39/* Register definitions for Sideband Interconnect */
40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510
42
43const u64 shift = 1;
44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
47#define L3_STATUS_0_MPUIA_INBAND (shift << 2)
48#define L3_STATUS_0_IVAIA_BRST (shift << 6)
49#define L3_STATUS_0_IVAIA_RSP (shift << 7)
50#define L3_STATUS_0_IVAIA_INBAND (shift << 8)
51#define L3_STATUS_0_SGXIA_BRST (shift << 9)
52#define L3_STATUS_0_SGXIA_RSP (shift << 10)
53#define L3_STATUS_0_SGXIA_MERROR (shift << 11)
54#define L3_STATUS_0_CAMIA_BRST (shift << 12)
55#define L3_STATUS_0_CAMIA_RSP (shift << 13)
56#define L3_STATUS_0_CAMIA_INBAND (shift << 14)
57#define L3_STATUS_0_DISPIA_BRST (shift << 15)
58#define L3_STATUS_0_DISPIA_RSP (shift << 16)
59#define L3_STATUS_0_DMARDIA_BRST (shift << 18)
60#define L3_STATUS_0_DMARDIA_RSP (shift << 19)
61#define L3_STATUS_0_DMAWRIA_BRST (shift << 21)
62#define L3_STATUS_0_DMAWRIA_RSP (shift << 22)
63#define L3_STATUS_0_USBOTGIA_BRST (shift << 24)
64#define L3_STATUS_0_USBOTGIA_RSP (shift << 25)
65#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26)
66#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27)
67#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28)
68#define L3_STATUS_0_SMSTA_REQ (shift << 48)
69#define L3_STATUS_0_GPMCTA_REQ (shift << 49)
70#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50)
71#define L3_STATUS_0_OCMROMTA_REQ (shift << 51)
72#define L3_STATUS_0_IVATA_REQ (shift << 54)
73#define L3_STATUS_0_SGXTA_REQ (shift << 55)
74#define L3_STATUS_0_SGXTA_SERROR (shift << 56)
75#define L3_STATUS_0_GPMCTA_SERROR (shift << 57)
76#define L3_STATUS_0_L4CORETA_REQ (shift << 58)
77#define L3_STATUS_0_L4PERTA_REQ (shift << 59)
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ)
108
109#define L3_SI_FLAG_STATUS_1 0x530
110
111#define L3_STATUS_1_MPU_DATAIA (1 << 0)
112#define L3_STATUS_1_DAPIA0 (1 << 3)
113#define L3_STATUS_1_DAPIA1 (1 << 4)
114#define L3_STATUS_1_IVAIA (1 << 6)
115
116#define L3_PM_ERROR_LOG 0x020
117#define L3_PM_CONTROL 0x028
118#define L3_PM_ERROR_CLEAR_SINGLE 0x030
119#define L3_PM_ERROR_CLEAR_MULTI 0x038
120#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n))
121#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n))
122#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n))
123#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n))
124
125/* L3 error log bit fields. Common for IA and TA */
126#define L3_ERROR_LOG_CODE 24
127#define L3_ERROR_LOG_INITID 8
128#define L3_ERROR_LOG_CMD 0
129
130/* L3 agent status bit fields. */
131#define L3_AGENT_STATUS_CLEAR_IA 0x10000000
132#define L3_AGENT_STATUS_CLEAR_TA 0x01000000
133
134#define OMAP34xx_IRQ_L3_APP 10
135#define L3_APPLICATION_ERROR 0x0
136#define L3_DEBUG_ERROR 0x1
137
138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
156 OMAP_L3_IA_IVA_SS_DMA_3 = 17,
157 OMAP_L3_IA_IVA_SS_DMA_4 = 16,
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1,
180};
181
182enum omap3_l3_code {
183 OMAP_L3_CODE_NOERROR = 0,
184 OMAP_L3_CODE_UNSUP_CMD = 1,
185 OMAP_L3_CODE_ADDR_HOLE = 2,
186 OMAP_L3_CODE_PROTECT_VIOLATION = 3,
187 OMAP_L3_CODE_IN_BAND_ERR = 4,
188 /* codes 5 and 6 are reserved */
189 OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
190 OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
191 /* codes 9 - 15 are also reserved */
192};
193
194struct omap3_l3 {
195 struct device *dev;
196 struct clk *ick;
197
198 /* memory base*/
199 void __iomem *rt;
200
201 int debug_irq;
202 int app_irq;
203
204 /* true when and inband functional error occurs */
205 unsigned inband:1;
206};
207
208/* offsets for l3 agents in order with the Flag status register */
209unsigned int __iomem omap3_l3_app_bases[] = {
210 /* MPU IA */
211 0x1400,
212 0x1400,
213 0x1400,
214 /* RESERVED */
215 0,
216 0,
217 0,
218 /* IVA 2.2 IA */
219 0x1800,
220 0x1800,
221 0x1800,
222 /* SGX IA */
223 0x1c00,
224 0x1c00,
225 /* RESERVED */
226 0,
227 /* CAMERA IA */
228 0x5800,
229 0x5800,
230 0x5800,
231 /* DISPLAY IA */
232 0x5400,
233 0x5400,
234 /* RESERVED */
235 0,
236 /*SDMA RD IA */
237 0x4c00,
238 0x4c00,
239 /* RESERVED */
240 0,
241 /* SDMA WR IA */
242 0x5000,
243 0x5000,
244 /* RESERVED */
245 0,
246 /* USB OTG IA */
247 0x4400,
248 0x4400,
249 0x4400,
250 /* USB HOST IA */
251 0x4000,
252 0x4000,
253 /* RESERVED */
254 0,
255 0,
256 0,
257 0,
258 /* SAD2D IA */
259 0x3000,
260 0x3000,
261 0x3000,
262 /* RESERVED */
263 0,
264 0,
265 0,
266 0,
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0,
275 /* SMA TA */
276 0x2000,
277 /* GPMC TA */
278 0x2400,
279 /* OCM RAM TA */
280 0x2800,
281 /* OCM ROM TA */
282 0x2C00,
283 /* L4 CORE TA */
284 0x6800,
285 /* L4 PER TA */
286 0x6c00,
287 /* IVA 2.2 TA */
288 0x6000,
289 /* SGX TA */
290 0x6400,
291 /* L4 EMU TA */
292 0x7000,
293 /* GPMC TA */
294 0x2400,
295 /* L4 CORE TA */
296 0x6800,
297 /* L4 PER TA */
298 0x6c00,
299 /* L4 EMU TA */
300 0x7000,
301 /* MAD2D TA */
302 0x3400,
303 /* RESERVED */
304 0,
305 0,
306};
307
308unsigned int __iomem omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */
310 0x1400,
311 /* RESERVED */
312 0,
313 0,
314 /* DAP IA */
315 0x5c00,
316 0x5c00,
317 /* RESERVED */
318 0,
319 /* IVA 2.2 IA */
320 0x1800,
321 /* REST RESERVED */
322};
323
324u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases,
326 omap3_l3_debug_bases,
327};
328
329/*
330 * REVISIT define __raw_readll/__raw_writell here, but move them to
331 * <asm/io.h> at some point
332 */
333#define __raw_writell(v, a) (__chk_io_ptr(a), \
334 *(volatile u64 __force *)(a) = (v))
335#define __raw_readll(a) (__chk_io_ptr(a), \
336 *(volatile u64 __force *)(a))
337
338#endif
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 125f56591fb5..a5a83b358ddd 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -637,14 +637,14 @@ static int __init pm_dbg_init(void)
637 637
638 } 638 }
639 639
640 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d, 640 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
641 &enable_off_mode, &pm_dbg_option_fops); 641 &enable_off_mode, &pm_dbg_option_fops);
642 (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d, 642 (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
643 &sleep_while_idle, &pm_dbg_option_fops); 643 &sleep_while_idle, &pm_dbg_option_fops);
644 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d, 644 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
645 &wakeup_timer_seconds, &pm_dbg_option_fops); 645 &wakeup_timer_seconds, &pm_dbg_option_fops);
646 (void) debugfs_create_file("wakeup_timer_milliseconds", 646 (void) debugfs_create_file("wakeup_timer_milliseconds",
647 S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds, 647 S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
648 &pm_dbg_option_fops); 648 &pm_dbg_option_fops);
649 pm_dbg_init_done = 1; 649 pm_dbg_init_done = 1;
650 650
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index eaed0df16699..a11be81997c5 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -2,7 +2,7 @@
2 * OMAP powerdomain control 2 * OMAP powerdomain control
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2009 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com> 8 * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
@@ -938,3 +938,44 @@ u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
938 938
939 return count; 939 return count;
940} 940}
941
942/**
943 * pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
944 * @pwrdm: struct powerdomain *
945 *
946 * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
947 * can lose either memory or logic context or if @pwrdm is invalid, or
948 * returns 0 otherwise. This function is not concerned with how the
949 * powerdomain registers are programmed (i.e., to go off or not); it's
950 * concerned with whether it's ever possible for this powerdomain to
951 * go off while some other part of the chip is active. This function
952 * assumes that every powerdomain can go to either ON or INACTIVE.
953 */
954bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
955{
956 int i;
957
958 if (IS_ERR_OR_NULL(pwrdm)) {
959 pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
960 __func__);
961 return 1;
962 }
963
964 if (pwrdm->pwrsts & PWRSTS_OFF)
965 return 1;
966
967 if (pwrdm->pwrsts & PWRSTS_RET) {
968 if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
969 return 1;
970
971 for (i = 0; i < pwrdm->banks; i++)
972 if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
973 return 1;
974 }
975
976 for (i = 0; i < pwrdm->banks; i++)
977 if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
978 return 1;
979
980 return 0;
981}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0b7a357cb38e..027f40bd235d 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -2,7 +2,7 @@
2 * OMAP2/3/4 powerdomain control 2 * OMAP2/3/4 powerdomain control
3 * 3 *
4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley 7 * Paul Walmsley
8 * 8 *
@@ -34,17 +34,14 @@
34 34
35/* Powerdomain allowable state bitfields */ 35/* Powerdomain allowable state bitfields */
36#define PWRSTS_ON (1 << PWRDM_POWER_ON) 36#define PWRSTS_ON (1 << PWRDM_POWER_ON)
37#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
38#define PWRSTS_RET (1 << PWRDM_POWER_RET)
37#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) 39#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
38#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
39 (1 << PWRDM_POWER_ON))
40 40
41#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ 41#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
42 (1 << PWRDM_POWER_RET)) 42#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
43 43#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
44#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ 44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
45 (1 << PWRDM_POWER_ON))
46
47#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
48 45
49 46
50/* Powerdomain flags */ 47/* Powerdomain flags */
@@ -211,6 +208,7 @@ int pwrdm_pre_transition(void);
211int pwrdm_post_transition(void); 208int pwrdm_post_transition(void);
212int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); 209int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
213u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm); 210u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
211bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
214 212
215extern void omap2xxx_powerdomains_init(void); 213extern void omap2xxx_powerdomains_init(void);
216extern void omap3xxx_powerdomains_init(void); 214extern void omap3xxx_powerdomains_init(void);
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 5b4dd971320a..4210c3399769 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP2/3 common powerdomain definitions 2 * OMAP2/3 common powerdomain definitions
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley, Jouni Högander 7 * Paul Walmsley, Jouni Högander
8 * 8 *
@@ -62,13 +62,13 @@ struct powerdomain gfx_omap2_pwrdm = {
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | 62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
63 CHIP_IS_OMAP3430ES1), 63 CHIP_IS_OMAP3430ES1),
64 .pwrsts = PWRSTS_OFF_RET_ON, 64 .pwrsts = PWRSTS_OFF_RET_ON,
65 .pwrsts_logic_ret = PWRDM_POWER_RET, 65 .pwrsts_logic_ret = PWRSTS_RET,
66 .banks = 1, 66 .banks = 1,
67 .pwrsts_mem_ret = { 67 .pwrsts_mem_ret = {
68 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 68 [0] = PWRSTS_RET, /* MEMRETSTATE */
69 }, 69 },
70 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
71 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 71 [0] = PWRSTS_ON, /* MEMONSTATE */
72 }, 72 },
73}; 73};
74 74
@@ -76,4 +76,5 @@ struct powerdomain wkup_omap2_pwrdm = {
76 .name = "wkup_pwrdm", 76 .name = "wkup_pwrdm",
77 .prcm_offs = WKUP_MOD, 77 .prcm_offs = WKUP_MOD,
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), 78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
79 .pwrsts = PWRSTS_ON,
79}; 80};
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 78739e10f5b9..cc389fb2005d 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP2XXX powerdomain definitions 2 * OMAP2XXX powerdomain definitions
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley, Jouni Högander 7 * Paul Walmsley, Jouni Högander
8 * 8 *
@@ -30,13 +30,13 @@ static struct powerdomain dsp_pwrdm = {
30 .prcm_offs = OMAP24XX_DSP_MOD, 30 .prcm_offs = OMAP24XX_DSP_MOD,
31 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), 31 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
32 .pwrsts = PWRSTS_OFF_RET_ON, 32 .pwrsts = PWRSTS_OFF_RET_ON,
33 .pwrsts_logic_ret = PWRDM_POWER_RET, 33 .pwrsts_logic_ret = PWRSTS_RET,
34 .banks = 1, 34 .banks = 1,
35 .pwrsts_mem_ret = { 35 .pwrsts_mem_ret = {
36 [0] = PWRDM_POWER_RET, 36 [0] = PWRSTS_RET,
37 }, 37 },
38 .pwrsts_mem_on = { 38 .pwrsts_mem_on = {
39 [0] = PWRDM_POWER_ON, 39 [0] = PWRSTS_ON,
40 }, 40 },
41}; 41};
42 42
@@ -48,10 +48,10 @@ static struct powerdomain mpu_24xx_pwrdm = {
48 .pwrsts_logic_ret = PWRSTS_OFF_RET, 48 .pwrsts_logic_ret = PWRSTS_OFF_RET,
49 .banks = 1, 49 .banks = 1,
50 .pwrsts_mem_ret = { 50 .pwrsts_mem_ret = {
51 [0] = PWRDM_POWER_RET, 51 [0] = PWRSTS_RET,
52 }, 52 },
53 .pwrsts_mem_on = { 53 .pwrsts_mem_on = {
54 [0] = PWRDM_POWER_ON, 54 [0] = PWRSTS_ON,
55 }, 55 },
56}; 56};
57 57
@@ -87,13 +87,13 @@ static struct powerdomain mdm_pwrdm = {
87 .prcm_offs = OMAP2430_MDM_MOD, 87 .prcm_offs = OMAP2430_MDM_MOD,
88 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 88 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
89 .pwrsts = PWRSTS_OFF_RET_ON, 89 .pwrsts = PWRSTS_OFF_RET_ON,
90 .pwrsts_logic_ret = PWRDM_POWER_RET, 90 .pwrsts_logic_ret = PWRSTS_RET,
91 .banks = 1, 91 .banks = 1,
92 .pwrsts_mem_ret = { 92 .pwrsts_mem_ret = {
93 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 93 [0] = PWRSTS_RET, /* MEMRETSTATE */
94 }, 94 },
95 .pwrsts_mem_on = { 95 .pwrsts_mem_on = {
96 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 96 [0] = PWRSTS_ON, /* MEMONSTATE */
97 }, 97 },
98}; 98};
99 99
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index e1bec562625b..9c9c113788b9 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP3 powerdomain definitions 2 * OMAP3 powerdomain definitions
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Paul Walmsley, Jouni Högander 7 * Paul Walmsley, Jouni Högander
8 * 8 *
@@ -47,10 +47,10 @@ static struct powerdomain iva2_pwrdm = {
47 [3] = PWRSTS_OFF_RET, 47 [3] = PWRSTS_OFF_RET,
48 }, 48 },
49 .pwrsts_mem_on = { 49 .pwrsts_mem_on = {
50 [0] = PWRDM_POWER_ON, 50 [0] = PWRSTS_ON,
51 [1] = PWRDM_POWER_ON, 51 [1] = PWRSTS_ON,
52 [2] = PWRSTS_OFF_ON, 52 [2] = PWRSTS_OFF_ON,
53 [3] = PWRDM_POWER_ON, 53 [3] = PWRSTS_ON,
54 }, 54 },
55}; 55};
56 56
@@ -128,13 +128,13 @@ static struct powerdomain dss_pwrdm = {
128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
129 .prcm_offs = OMAP3430_DSS_MOD, 129 .prcm_offs = OMAP3430_DSS_MOD,
130 .pwrsts = PWRSTS_OFF_RET_ON, 130 .pwrsts = PWRSTS_OFF_RET_ON,
131 .pwrsts_logic_ret = PWRDM_POWER_RET, 131 .pwrsts_logic_ret = PWRSTS_RET,
132 .banks = 1, 132 .banks = 1,
133 .pwrsts_mem_ret = { 133 .pwrsts_mem_ret = {
134 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 134 [0] = PWRSTS_RET, /* MEMRETSTATE */
135 }, 135 },
136 .pwrsts_mem_on = { 136 .pwrsts_mem_on = {
137 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 137 [0] = PWRSTS_ON, /* MEMONSTATE */
138 }, 138 },
139}; 139};
140 140
@@ -149,13 +149,13 @@ static struct powerdomain sgx_pwrdm = {
149 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 149 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
150 /* XXX This is accurate for 3430 SGX, but what about GFX? */ 150 /* XXX This is accurate for 3430 SGX, but what about GFX? */
151 .pwrsts = PWRSTS_OFF_ON, 151 .pwrsts = PWRSTS_OFF_ON,
152 .pwrsts_logic_ret = PWRDM_POWER_RET, 152 .pwrsts_logic_ret = PWRSTS_RET,
153 .banks = 1, 153 .banks = 1,
154 .pwrsts_mem_ret = { 154 .pwrsts_mem_ret = {
155 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 155 [0] = PWRSTS_RET, /* MEMRETSTATE */
156 }, 156 },
157 .pwrsts_mem_on = { 157 .pwrsts_mem_on = {
158 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 158 [0] = PWRSTS_ON, /* MEMONSTATE */
159 }, 159 },
160}; 160};
161 161
@@ -164,13 +164,13 @@ static struct powerdomain cam_pwrdm = {
164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 164 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
165 .prcm_offs = OMAP3430_CAM_MOD, 165 .prcm_offs = OMAP3430_CAM_MOD,
166 .pwrsts = PWRSTS_OFF_RET_ON, 166 .pwrsts = PWRSTS_OFF_RET_ON,
167 .pwrsts_logic_ret = PWRDM_POWER_RET, 167 .pwrsts_logic_ret = PWRSTS_RET,
168 .banks = 1, 168 .banks = 1,
169 .pwrsts_mem_ret = { 169 .pwrsts_mem_ret = {
170 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 170 [0] = PWRSTS_RET, /* MEMRETSTATE */
171 }, 171 },
172 .pwrsts_mem_on = { 172 .pwrsts_mem_on = {
173 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 173 [0] = PWRSTS_ON, /* MEMONSTATE */
174 }, 174 },
175}; 175};
176 176
@@ -182,10 +182,10 @@ static struct powerdomain per_pwrdm = {
182 .pwrsts_logic_ret = PWRSTS_OFF_RET, 182 .pwrsts_logic_ret = PWRSTS_OFF_RET,
183 .banks = 1, 183 .banks = 1,
184 .pwrsts_mem_ret = { 184 .pwrsts_mem_ret = {
185 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 185 [0] = PWRSTS_RET, /* MEMRETSTATE */
186 }, 186 },
187 .pwrsts_mem_on = { 187 .pwrsts_mem_on = {
188 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 188 [0] = PWRSTS_ON, /* MEMONSTATE */
189 }, 189 },
190}; 190};
191 191
@@ -200,7 +200,7 @@ static struct powerdomain neon_pwrdm = {
200 .prcm_offs = OMAP3430_NEON_MOD, 200 .prcm_offs = OMAP3430_NEON_MOD,
201 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 201 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
202 .pwrsts = PWRSTS_OFF_RET_ON, 202 .pwrsts = PWRSTS_OFF_RET_ON,
203 .pwrsts_logic_ret = PWRDM_POWER_RET, 203 .pwrsts_logic_ret = PWRSTS_RET,
204}; 204};
205 205
206static struct powerdomain usbhost_pwrdm = { 206static struct powerdomain usbhost_pwrdm = {
@@ -208,7 +208,7 @@ static struct powerdomain usbhost_pwrdm = {
208 .prcm_offs = OMAP3430ES2_USBHOST_MOD, 208 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
209 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), 209 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
210 .pwrsts = PWRSTS_OFF_RET_ON, 210 .pwrsts = PWRSTS_OFF_RET_ON,
211 .pwrsts_logic_ret = PWRDM_POWER_RET, 211 .pwrsts_logic_ret = PWRSTS_RET,
212 /* 212 /*
213 * REVISIT: Enabling usb host save and restore mechanism seems to 213 * REVISIT: Enabling usb host save and restore mechanism seems to
214 * leave the usb host domain permanently in ACTIVE mode after 214 * leave the usb host domain permanently in ACTIVE mode after
@@ -218,10 +218,10 @@ static struct powerdomain usbhost_pwrdm = {
218 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ 218 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
219 .banks = 1, 219 .banks = 1,
220 .pwrsts_mem_ret = { 220 .pwrsts_mem_ret = {
221 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 221 [0] = PWRSTS_RET, /* MEMRETSTATE */
222 }, 222 },
223 .pwrsts_mem_on = { 223 .pwrsts_mem_on = {
224 [0] = PWRDM_POWER_ON, /* MEMONSTATE */ 224 [0] = PWRSTS_ON, /* MEMONSTATE */
225 }, 225 },
226}; 226};
227 227
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 26d7641076d7..c4222c7036a5 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -2,7 +2,7 @@
2 * OMAP4 Power domains framework 2 * OMAP4 Power domains framework
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2011 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com) 8 * Benoit Cousson (b-cousson@ti.com)
@@ -40,18 +40,18 @@ static struct powerdomain core_44xx_pwrdm = {
40 .pwrsts_logic_ret = PWRSTS_OFF_RET, 40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
41 .banks = 5, 41 .banks = 5,
42 .pwrsts_mem_ret = { 42 .pwrsts_mem_ret = {
43 [0] = PWRDM_POWER_OFF, /* core_nret_bank */ 43 [0] = PWRSTS_OFF, /* core_nret_bank */
44 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 44 [1] = PWRSTS_OFF_RET, /* core_ocmram */
45 [2] = PWRDM_POWER_RET, /* core_other_bank */ 45 [2] = PWRSTS_RET, /* core_other_bank */
46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ 46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */ 47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */
48 }, 48 },
49 .pwrsts_mem_on = { 49 .pwrsts_mem_on = {
50 [0] = PWRDM_POWER_ON, /* core_nret_bank */ 50 [0] = PWRSTS_ON, /* core_nret_bank */
51 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 51 [1] = PWRSTS_OFF_RET, /* core_ocmram */
52 [2] = PWRDM_POWER_ON, /* core_other_bank */ 52 [2] = PWRSTS_ON, /* core_other_bank */
53 [3] = PWRDM_POWER_ON, /* ducati_l2ram */ 53 [3] = PWRSTS_ON, /* ducati_l2ram */
54 [4] = PWRDM_POWER_ON, /* ducati_unicache */ 54 [4] = PWRSTS_ON, /* ducati_unicache */
55 }, 55 },
56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
57}; 57};
@@ -65,10 +65,10 @@ static struct powerdomain gfx_44xx_pwrdm = {
65 .pwrsts = PWRSTS_OFF_ON, 65 .pwrsts = PWRSTS_OFF_ON,
66 .banks = 1, 66 .banks = 1,
67 .pwrsts_mem_ret = { 67 .pwrsts_mem_ret = {
68 [0] = PWRDM_POWER_OFF, /* gfx_mem */ 68 [0] = PWRSTS_OFF, /* gfx_mem */
69 }, 69 },
70 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
71 [0] = PWRDM_POWER_ON, /* gfx_mem */ 71 [0] = PWRSTS_ON, /* gfx_mem */
72 }, 72 },
73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
74}; 74};
@@ -80,15 +80,15 @@ static struct powerdomain abe_44xx_pwrdm = {
80 .prcm_partition = OMAP4430_PRM_PARTITION, 80 .prcm_partition = OMAP4430_PRM_PARTITION,
81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
82 .pwrsts = PWRSTS_OFF_RET_ON, 82 .pwrsts = PWRSTS_OFF_RET_ON,
83 .pwrsts_logic_ret = PWRDM_POWER_OFF, 83 .pwrsts_logic_ret = PWRSTS_OFF,
84 .banks = 2, 84 .banks = 2,
85 .pwrsts_mem_ret = { 85 .pwrsts_mem_ret = {
86 [0] = PWRDM_POWER_RET, /* aessmem */ 86 [0] = PWRSTS_RET, /* aessmem */
87 [1] = PWRDM_POWER_OFF, /* periphmem */ 87 [1] = PWRSTS_OFF, /* periphmem */
88 }, 88 },
89 .pwrsts_mem_on = { 89 .pwrsts_mem_on = {
90 [0] = PWRDM_POWER_ON, /* aessmem */ 90 [0] = PWRSTS_ON, /* aessmem */
91 [1] = PWRDM_POWER_ON, /* periphmem */ 91 [1] = PWRSTS_ON, /* periphmem */
92 }, 92 },
93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
94}; 94};
@@ -103,10 +103,10 @@ static struct powerdomain dss_44xx_pwrdm = {
103 .pwrsts_logic_ret = PWRSTS_OFF, 103 .pwrsts_logic_ret = PWRSTS_OFF,
104 .banks = 1, 104 .banks = 1,
105 .pwrsts_mem_ret = { 105 .pwrsts_mem_ret = {
106 [0] = PWRDM_POWER_OFF, /* dss_mem */ 106 [0] = PWRSTS_OFF, /* dss_mem */
107 }, 107 },
108 .pwrsts_mem_on = { 108 .pwrsts_mem_on = {
109 [0] = PWRDM_POWER_ON, /* dss_mem */ 109 [0] = PWRSTS_ON, /* dss_mem */
110 }, 110 },
111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
112}; 112};
@@ -121,14 +121,14 @@ static struct powerdomain tesla_44xx_pwrdm = {
121 .pwrsts_logic_ret = PWRSTS_OFF_RET, 121 .pwrsts_logic_ret = PWRSTS_OFF_RET,
122 .banks = 3, 122 .banks = 3,
123 .pwrsts_mem_ret = { 123 .pwrsts_mem_ret = {
124 [0] = PWRDM_POWER_RET, /* tesla_edma */ 124 [0] = PWRSTS_RET, /* tesla_edma */
125 [1] = PWRSTS_OFF_RET, /* tesla_l1 */ 125 [1] = PWRSTS_OFF_RET, /* tesla_l1 */
126 [2] = PWRSTS_OFF_RET, /* tesla_l2 */ 126 [2] = PWRSTS_OFF_RET, /* tesla_l2 */
127 }, 127 },
128 .pwrsts_mem_on = { 128 .pwrsts_mem_on = {
129 [0] = PWRDM_POWER_ON, /* tesla_edma */ 129 [0] = PWRSTS_ON, /* tesla_edma */
130 [1] = PWRDM_POWER_ON, /* tesla_l1 */ 130 [1] = PWRSTS_ON, /* tesla_l1 */
131 [2] = PWRDM_POWER_ON, /* tesla_l2 */ 131 [2] = PWRSTS_ON, /* tesla_l2 */
132 }, 132 },
133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
134}; 134};
@@ -142,10 +142,10 @@ static struct powerdomain wkup_44xx_pwrdm = {
142 .pwrsts = PWRSTS_ON, 142 .pwrsts = PWRSTS_ON,
143 .banks = 1, 143 .banks = 1,
144 .pwrsts_mem_ret = { 144 .pwrsts_mem_ret = {
145 [0] = PWRDM_POWER_OFF, /* wkup_bank */ 145 [0] = PWRSTS_OFF, /* wkup_bank */
146 }, 146 },
147 .pwrsts_mem_on = { 147 .pwrsts_mem_on = {
148 [0] = PWRDM_POWER_ON, /* wkup_bank */ 148 [0] = PWRSTS_ON, /* wkup_bank */
149 }, 149 },
150}; 150};
151 151
@@ -162,7 +162,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
162 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 162 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
163 }, 163 },
164 .pwrsts_mem_on = { 164 .pwrsts_mem_on = {
165 [0] = PWRDM_POWER_ON, /* cpu0_l1 */ 165 [0] = PWRSTS_ON, /* cpu0_l1 */
166 }, 166 },
167}; 167};
168 168
@@ -179,7 +179,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
179 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 179 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
180 }, 180 },
181 .pwrsts_mem_on = { 181 .pwrsts_mem_on = {
182 [0] = PWRDM_POWER_ON, /* cpu1_l1 */ 182 [0] = PWRSTS_ON, /* cpu1_l1 */
183 }, 183 },
184}; 184};
185 185
@@ -192,10 +192,10 @@ static struct powerdomain emu_44xx_pwrdm = {
192 .pwrsts = PWRSTS_OFF_ON, 192 .pwrsts = PWRSTS_OFF_ON,
193 .banks = 1, 193 .banks = 1,
194 .pwrsts_mem_ret = { 194 .pwrsts_mem_ret = {
195 [0] = PWRDM_POWER_OFF, /* emu_bank */ 195 [0] = PWRSTS_OFF, /* emu_bank */
196 }, 196 },
197 .pwrsts_mem_on = { 197 .pwrsts_mem_on = {
198 [0] = PWRDM_POWER_ON, /* emu_bank */ 198 [0] = PWRSTS_ON, /* emu_bank */
199 }, 199 },
200}; 200};
201 201
@@ -211,12 +211,12 @@ static struct powerdomain mpu_44xx_pwrdm = {
211 .pwrsts_mem_ret = { 211 .pwrsts_mem_ret = {
212 [0] = PWRSTS_OFF_RET, /* mpu_l1 */ 212 [0] = PWRSTS_OFF_RET, /* mpu_l1 */
213 [1] = PWRSTS_OFF_RET, /* mpu_l2 */ 213 [1] = PWRSTS_OFF_RET, /* mpu_l2 */
214 [2] = PWRDM_POWER_RET, /* mpu_ram */ 214 [2] = PWRSTS_RET, /* mpu_ram */
215 }, 215 },
216 .pwrsts_mem_on = { 216 .pwrsts_mem_on = {
217 [0] = PWRDM_POWER_ON, /* mpu_l1 */ 217 [0] = PWRSTS_ON, /* mpu_l1 */
218 [1] = PWRDM_POWER_ON, /* mpu_l2 */ 218 [1] = PWRSTS_ON, /* mpu_l2 */
219 [2] = PWRDM_POWER_ON, /* mpu_ram */ 219 [2] = PWRSTS_ON, /* mpu_ram */
220 }, 220 },
221}; 221};
222 222
@@ -227,19 +227,19 @@ static struct powerdomain ivahd_44xx_pwrdm = {
227 .prcm_partition = OMAP4430_PRM_PARTITION, 227 .prcm_partition = OMAP4430_PRM_PARTITION,
228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
229 .pwrsts = PWRSTS_OFF_RET_ON, 229 .pwrsts = PWRSTS_OFF_RET_ON,
230 .pwrsts_logic_ret = PWRDM_POWER_OFF, 230 .pwrsts_logic_ret = PWRSTS_OFF,
231 .banks = 4, 231 .banks = 4,
232 .pwrsts_mem_ret = { 232 .pwrsts_mem_ret = {
233 [0] = PWRDM_POWER_OFF, /* hwa_mem */ 233 [0] = PWRSTS_OFF, /* hwa_mem */
234 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 234 [1] = PWRSTS_OFF_RET, /* sl2_mem */
235 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 235 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
236 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 236 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
237 }, 237 },
238 .pwrsts_mem_on = { 238 .pwrsts_mem_on = {
239 [0] = PWRDM_POWER_ON, /* hwa_mem */ 239 [0] = PWRSTS_ON, /* hwa_mem */
240 [1] = PWRDM_POWER_ON, /* sl2_mem */ 240 [1] = PWRSTS_ON, /* sl2_mem */
241 [2] = PWRDM_POWER_ON, /* tcm1_mem */ 241 [2] = PWRSTS_ON, /* tcm1_mem */
242 [3] = PWRDM_POWER_ON, /* tcm2_mem */ 242 [3] = PWRSTS_ON, /* tcm2_mem */
243 }, 243 },
244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
245}; 245};
@@ -253,10 +253,10 @@ static struct powerdomain cam_44xx_pwrdm = {
253 .pwrsts = PWRSTS_OFF_ON, 253 .pwrsts = PWRSTS_OFF_ON,
254 .banks = 1, 254 .banks = 1,
255 .pwrsts_mem_ret = { 255 .pwrsts_mem_ret = {
256 [0] = PWRDM_POWER_OFF, /* cam_mem */ 256 [0] = PWRSTS_OFF, /* cam_mem */
257 }, 257 },
258 .pwrsts_mem_on = { 258 .pwrsts_mem_on = {
259 [0] = PWRDM_POWER_ON, /* cam_mem */ 259 [0] = PWRSTS_ON, /* cam_mem */
260 }, 260 },
261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
262}; 262};
@@ -271,10 +271,10 @@ static struct powerdomain l3init_44xx_pwrdm = {
271 .pwrsts_logic_ret = PWRSTS_OFF_RET, 271 .pwrsts_logic_ret = PWRSTS_OFF_RET,
272 .banks = 1, 272 .banks = 1,
273 .pwrsts_mem_ret = { 273 .pwrsts_mem_ret = {
274 [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ 274 [0] = PWRSTS_OFF, /* l3init_bank1 */
275 }, 275 },
276 .pwrsts_mem_on = { 276 .pwrsts_mem_on = {
277 [0] = PWRDM_POWER_ON, /* l3init_bank1 */ 277 [0] = PWRSTS_ON, /* l3init_bank1 */
278 }, 278 },
279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
280}; 280};
@@ -289,12 +289,12 @@ static struct powerdomain l4per_44xx_pwrdm = {
289 .pwrsts_logic_ret = PWRSTS_OFF_RET, 289 .pwrsts_logic_ret = PWRSTS_OFF_RET,
290 .banks = 2, 290 .banks = 2,
291 .pwrsts_mem_ret = { 291 .pwrsts_mem_ret = {
292 [0] = PWRDM_POWER_OFF, /* nonretained_bank */ 292 [0] = PWRSTS_OFF, /* nonretained_bank */
293 [1] = PWRDM_POWER_RET, /* retained_bank */ 293 [1] = PWRSTS_RET, /* retained_bank */
294 }, 294 },
295 .pwrsts_mem_on = { 295 .pwrsts_mem_on = {
296 [0] = PWRDM_POWER_ON, /* nonretained_bank */ 296 [0] = PWRSTS_ON, /* nonretained_bank */
297 [1] = PWRDM_POWER_ON, /* retained_bank */ 297 [1] = PWRSTS_ON, /* retained_bank */
298 }, 298 },
299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
300}; 300};
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 87486f559784..0363dcb0ef93 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -121,6 +121,10 @@
121#define OMAP24XX_ST_MCSPI2_MASK (1 << 18) 121#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
122#define OMAP24XX_ST_MCSPI1_SHIFT 17 122#define OMAP24XX_ST_MCSPI1_SHIFT 17
123#define OMAP24XX_ST_MCSPI1_MASK (1 << 17) 123#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
124#define OMAP24XX_ST_MCBSP2_SHIFT 16
125#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
126#define OMAP24XX_ST_MCBSP1_SHIFT 15
127#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
124#define OMAP24XX_ST_GPT12_SHIFT 14 128#define OMAP24XX_ST_GPT12_SHIFT 14
125#define OMAP24XX_ST_GPT12_MASK (1 << 14) 129#define OMAP24XX_ST_GPT12_MASK (1 << 14)
126#define OMAP24XX_ST_GPT11_SHIFT 13 130#define OMAP24XX_ST_GPT11_SHIFT 13
@@ -191,6 +195,8 @@
191#define OMAP3430_AUTOIDLE_MASK (1 << 0) 195#define OMAP3430_AUTOIDLE_MASK (1 << 0)
192 196
193/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 197/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
198#define OMAP3430_EN_MMC3_MASK (1 << 30)
199#define OMAP3430_EN_MMC3_SHIFT 30
194#define OMAP3430_EN_MMC2_MASK (1 << 25) 200#define OMAP3430_EN_MMC2_MASK (1 << 25)
195#define OMAP3430_EN_MMC2_SHIFT 25 201#define OMAP3430_EN_MMC2_SHIFT 25
196#define OMAP3430_EN_MMC1_MASK (1 << 24) 202#define OMAP3430_EN_MMC1_MASK (1 << 24)
@@ -231,6 +237,8 @@
231#define OMAP3430_EN_HSOTGUSB_SHIFT 4 237#define OMAP3430_EN_HSOTGUSB_SHIFT 4
232 238
233/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 239/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
240#define OMAP3430_ST_MMC3_SHIFT 30
241#define OMAP3430_ST_MMC3_MASK (1 << 30)
234#define OMAP3430_ST_MMC2_SHIFT 25 242#define OMAP3430_ST_MMC2_SHIFT 25
235#define OMAP3430_ST_MMC2_MASK (1 << 25) 243#define OMAP3430_ST_MMC2_MASK (1 << 25)
236#define OMAP3430_ST_MMC1_SHIFT 24 244#define OMAP3430_ST_MMC1_SHIFT 24
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 729a644ce852..d22d1b43bccd 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -38,8 +38,8 @@
38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 39
40/* PRCM_MPU clockdomain register offsets (from instance start) */ 40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000 41#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018
42#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000 42#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018
43 43
44 44
45/* 45/*
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 47eef48b8830..1ac361b7b8cb 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -680,7 +680,7 @@ static int __init omap_serial_early_init(void)
680 num_uarts++; 680 num_uarts++;
681 681
682 /* 682 /*
683 * NOTE: omap_hwmod_init() has not yet been called, 683 * NOTE: omap_hwmod_setup*() has not yet been called,
684 * so no hwmod functions will work yet. 684 * so no hwmod functions will work yet.
685 */ 685 */
686 686
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index c37e823266d3..95ac336fe3f7 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -900,7 +900,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
900 return PTR_ERR(dbg_dir); 900 return PTR_ERR(dbg_dir);
901 } 901 }
902 902
903 (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir, 903 (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
904 (void *)sr_info, &pm_sr_fops); 904 (void *)sr_info, &pm_sr_fops);
905 (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir, 905 (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
906 &sr_info->err_weight); 906 &sr_info->err_weight);
@@ -939,7 +939,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
939 strcpy(name, "volt_"); 939 strcpy(name, "volt_");
940 sprintf(volt_name, "%d", volt_data[i].volt_nominal); 940 sprintf(volt_name, "%d", volt_data[i].volt_nominal);
941 strcat(name, volt_name); 941 strcat(name, volt_name);
942 (void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir, 942 (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
943 &(sr_info->nvalue_table[i].nvalue)); 943 &(sr_info->nvalue_table[i].nvalue));
944 } 944 }
945 945
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 7b7c2683ae7b..3b9cf85f4bb9 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -39,10 +39,12 @@
39#include <asm/mach/time.h> 39#include <asm/mach/time.h>
40#include <plat/dmtimer.h> 40#include <plat/dmtimer.h>
41#include <asm/localtimer.h> 41#include <asm/localtimer.h>
42#include <asm/sched_clock.h>
43#include <plat/common.h>
44#include <plat/omap_hwmod.h>
42 45
43#include "timer-gp.h" 46#include "timer-gp.h"
44 47
45#include <plat/common.h>
46 48
47/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ 49/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
48#define MAX_GPTIMER_ID 12 50#define MAX_GPTIMER_ID 12
@@ -132,9 +134,13 @@ static void __init omap2_gp_clockevent_init(void)
132{ 134{
133 u32 tick_rate; 135 u32 tick_rate;
134 int src; 136 int src;
137 char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
135 138
136 inited = 1; 139 inited = 1;
137 140
141 sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
142 omap_hwmod_setup_one(clockevent_hwmod_name);
143
138 gptimer = omap_dm_timer_request_specific(gptimer_id); 144 gptimer = omap_dm_timer_request_specific(gptimer_id);
139 BUG_ON(gptimer == NULL); 145 BUG_ON(gptimer == NULL);
140 gptimer_wakeup = gptimer; 146 gptimer_wakeup = gptimer;
@@ -190,6 +196,7 @@ static void __init omap2_gp_clocksource_init(void)
190/* 196/*
191 * clocksource 197 * clocksource
192 */ 198 */
199static DEFINE_CLOCK_DATA(cd);
193static struct omap_dm_timer *gpt_clocksource; 200static struct omap_dm_timer *gpt_clocksource;
194static cycle_t clocksource_read_cycles(struct clocksource *cs) 201static cycle_t clocksource_read_cycles(struct clocksource *cs)
195{ 202{
@@ -204,6 +211,15 @@ static struct clocksource clocksource_gpt = {
204 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 211 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
205}; 212};
206 213
214static void notrace dmtimer_update_sched_clock(void)
215{
216 u32 cyc;
217
218 cyc = omap_dm_timer_read_counter(gpt_clocksource);
219
220 update_sched_clock(&cd, cyc, (u32)~0);
221}
222
207/* Setup free-running counter for clocksource */ 223/* Setup free-running counter for clocksource */
208static void __init omap2_gp_clocksource_init(void) 224static void __init omap2_gp_clocksource_init(void)
209{ 225{
@@ -224,6 +240,8 @@ static void __init omap2_gp_clocksource_init(void)
224 240
225 omap_dm_timer_set_load_start(gpt, 1, 0); 241 omap_dm_timer_set_load_start(gpt, 1, 0);
226 242
243 init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
244
227 if (clocksource_register_hz(&clocksource_gpt, tick_rate)) 245 if (clocksource_register_hz(&clocksource_gpt, tick_rate))
228 printk(err2, clocksource_gpt.name); 246 printk(err2, clocksource_gpt.name);
229} 247}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 14:36:53 -0500