diff options
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-24xx.h | 401 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/cm.h | 124 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/control.c | 74 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prcm-common.h | 317 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-24xx.h | 279 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm.h | 316 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/sdrc.h | 58 |
8 files changed, 1571 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index ac343ec578c2..b9313c9c7420 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -3,8 +3,8 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \ | 6 | obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \ |
| 7 | serial.o gpmc.o timer-gp.o | 7 | devices.o serial.o gpmc.o timer-gp.o |
| 8 | 8 | ||
| 9 | # Power Management | 9 | # Power Management |
| 10 | obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o | 10 | obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o |
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h new file mode 100644 index 000000000000..20ac38100678 --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
| @@ -0,0 +1,401 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP24XX Clock Management register bits | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "cm.h" | ||
| 18 | |||
| 19 | /* Bits shared between registers */ | ||
| 20 | |||
| 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | ||
| 22 | #define OMAP24XX_EN_CAM_SHIFT 31 | ||
| 23 | #define OMAP24XX_EN_CAM (1 << 31) | ||
| 24 | #define OMAP24XX_EN_WDT4_SHIFT 29 | ||
| 25 | #define OMAP24XX_EN_WDT4 (1 << 29) | ||
| 26 | #define OMAP2420_EN_WDT3_SHIFT 28 | ||
| 27 | #define OMAP2420_EN_WDT3 (1 << 28) | ||
| 28 | #define OMAP24XX_EN_MSPRO_SHIFT 27 | ||
| 29 | #define OMAP24XX_EN_MSPRO (1 << 27) | ||
| 30 | #define OMAP24XX_EN_FAC_SHIFT 25 | ||
| 31 | #define OMAP24XX_EN_FAC (1 << 25) | ||
| 32 | #define OMAP2420_EN_EAC_SHIFT 24 | ||
| 33 | #define OMAP2420_EN_EAC (1 << 24) | ||
| 34 | #define OMAP24XX_EN_HDQ_SHIFT 23 | ||
| 35 | #define OMAP24XX_EN_HDQ (1 << 23) | ||
| 36 | #define OMAP2420_EN_I2C2_SHIFT 20 | ||
| 37 | #define OMAP2420_EN_I2C2 (1 << 20) | ||
| 38 | #define OMAP2420_EN_I2C1_SHIFT 19 | ||
| 39 | #define OMAP2420_EN_I2C1 (1 << 19) | ||
| 40 | |||
| 41 | /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ | ||
| 42 | #define OMAP2430_EN_MCBSP5_SHIFT 5 | ||
| 43 | #define OMAP2430_EN_MCBSP5 (1 << 5) | ||
| 44 | #define OMAP2430_EN_MCBSP4_SHIFT 4 | ||
| 45 | #define OMAP2430_EN_MCBSP4 (1 << 4) | ||
| 46 | #define OMAP2430_EN_MCBSP3_SHIFT 3 | ||
| 47 | #define OMAP2430_EN_MCBSP3 (1 << 3) | ||
| 48 | #define OMAP24XX_EN_SSI_SHIFT 1 | ||
| 49 | #define OMAP24XX_EN_SSI (1 << 1) | ||
| 50 | |||
| 51 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | ||
| 52 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 | ||
| 53 | #define OMAP24XX_EN_MPU_WDT (1 << 3) | ||
| 54 | |||
| 55 | /* Bits specific to each register */ | ||
| 56 | |||
| 57 | /* CM_IDLEST_MPU */ | ||
| 58 | /* 2430 only */ | ||
| 59 | #define OMAP2430_ST_MPU (1 << 0) | ||
| 60 | |||
| 61 | /* CM_CLKSEL_MPU */ | ||
| 62 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 | ||
| 63 | #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) | ||
| 64 | |||
| 65 | /* CM_CLKSTCTRL_MPU */ | ||
| 66 | #define OMAP24XX_AUTOSTATE_MPU (1 << 0) | ||
| 67 | |||
| 68 | /* CM_FCLKEN1_CORE specific bits*/ | ||
| 69 | #define OMAP24XX_EN_TV_SHIFT 2 | ||
| 70 | #define OMAP24XX_EN_TV (1 << 2) | ||
| 71 | #define OMAP24XX_EN_DSS2_SHIFT 1 | ||
| 72 | #define OMAP24XX_EN_DSS2 (1 << 1) | ||
| 73 | #define OMAP24XX_EN_DSS1_SHIFT 0 | ||
| 74 | #define OMAP24XX_EN_DSS1 (1 << 0) | ||
| 75 | |||
| 76 | /* CM_FCLKEN2_CORE specific bits */ | ||
| 77 | #define OMAP2430_EN_I2CHS2_SHIFT 20 | ||
| 78 | #define OMAP2430_EN_I2CHS2 (1 << 20) | ||
| 79 | #define OMAP2430_EN_I2CHS1_SHIFT 19 | ||
| 80 | #define OMAP2430_EN_I2CHS1 (1 << 19) | ||
| 81 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 | ||
| 82 | #define OMAP2430_EN_MMCHSDB2 (1 << 17) | ||
| 83 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 | ||
| 84 | #define OMAP2430_EN_MMCHSDB1 (1 << 16) | ||
| 85 | |||
| 86 | /* CM_ICLKEN1_CORE specific bits */ | ||
| 87 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 | ||
| 88 | #define OMAP24XX_EN_MAILBOXES (1 << 30) | ||
| 89 | #define OMAP24XX_EN_DSS_SHIFT 0 | ||
| 90 | #define OMAP24XX_EN_DSS (1 << 0) | ||
| 91 | |||
| 92 | /* CM_ICLKEN2_CORE specific bits */ | ||
| 93 | |||
| 94 | /* CM_ICLKEN3_CORE */ | ||
| 95 | /* 2430 only */ | ||
| 96 | #define OMAP2430_EN_SDRC_SHIFT 2 | ||
| 97 | #define OMAP2430_EN_SDRC (1 << 2) | ||
| 98 | |||
| 99 | /* CM_ICLKEN4_CORE */ | ||
| 100 | #define OMAP24XX_EN_PKA_SHIFT 4 | ||
| 101 | #define OMAP24XX_EN_PKA (1 << 4) | ||
| 102 | #define OMAP24XX_EN_AES_SHIFT 3 | ||
| 103 | #define OMAP24XX_EN_AES (1 << 3) | ||
| 104 | #define OMAP24XX_EN_RNG_SHIFT 2 | ||
| 105 | #define OMAP24XX_EN_RNG (1 << 2) | ||
| 106 | #define OMAP24XX_EN_SHA_SHIFT 1 | ||
| 107 | #define OMAP24XX_EN_SHA (1 << 1) | ||
| 108 | #define OMAP24XX_EN_DES_SHIFT 0 | ||
| 109 | #define OMAP24XX_EN_DES (1 << 0) | ||
| 110 | |||
| 111 | /* CM_IDLEST1_CORE specific bits */ | ||
| 112 | #define OMAP24XX_ST_MAILBOXES (1 << 30) | ||
| 113 | #define OMAP24XX_ST_WDT4 (1 << 29) | ||
| 114 | #define OMAP2420_ST_WDT3 (1 << 28) | ||
| 115 | #define OMAP24XX_ST_MSPRO (1 << 27) | ||
| 116 | #define OMAP24XX_ST_FAC (1 << 25) | ||
| 117 | #define OMAP2420_ST_EAC (1 << 24) | ||
| 118 | #define OMAP24XX_ST_HDQ (1 << 23) | ||
| 119 | #define OMAP24XX_ST_I2C2 (1 << 20) | ||
| 120 | #define OMAP24XX_ST_I2C1 (1 << 19) | ||
| 121 | #define OMAP24XX_ST_MCBSP2 (1 << 16) | ||
| 122 | #define OMAP24XX_ST_MCBSP1 (1 << 15) | ||
| 123 | #define OMAP24XX_ST_DSS (1 << 0) | ||
| 124 | |||
| 125 | /* CM_IDLEST2_CORE */ | ||
| 126 | #define OMAP2430_ST_MCBSP5 (1 << 5) | ||
| 127 | #define OMAP2430_ST_MCBSP4 (1 << 4) | ||
| 128 | #define OMAP2430_ST_MCBSP3 (1 << 3) | ||
| 129 | #define OMAP24XX_ST_SSI (1 << 1) | ||
| 130 | |||
| 131 | /* CM_IDLEST3_CORE */ | ||
| 132 | /* 2430 only */ | ||
| 133 | #define OMAP2430_ST_SDRC (1 << 2) | ||
| 134 | |||
| 135 | /* CM_IDLEST4_CORE */ | ||
| 136 | #define OMAP24XX_ST_PKA (1 << 4) | ||
| 137 | #define OMAP24XX_ST_AES (1 << 3) | ||
| 138 | #define OMAP24XX_ST_RNG (1 << 2) | ||
| 139 | #define OMAP24XX_ST_SHA (1 << 1) | ||
| 140 | #define OMAP24XX_ST_DES (1 << 0) | ||
| 141 | |||
| 142 | /* CM_AUTOIDLE1_CORE */ | ||
| 143 | #define OMAP24XX_AUTO_CAM (1 << 31) | ||
| 144 | #define OMAP24XX_AUTO_MAILBOXES (1 << 30) | ||
| 145 | #define OMAP24XX_AUTO_WDT4 (1 << 29) | ||
| 146 | #define OMAP2420_AUTO_WDT3 (1 << 28) | ||
| 147 | #define OMAP24XX_AUTO_MSPRO (1 << 27) | ||
| 148 | #define OMAP2420_AUTO_MMC (1 << 26) | ||
| 149 | #define OMAP24XX_AUTO_FAC (1 << 25) | ||
| 150 | #define OMAP2420_AUTO_EAC (1 << 24) | ||
| 151 | #define OMAP24XX_AUTO_HDQ (1 << 23) | ||
| 152 | #define OMAP24XX_AUTO_UART2 (1 << 22) | ||
| 153 | #define OMAP24XX_AUTO_UART1 (1 << 21) | ||
| 154 | #define OMAP24XX_AUTO_I2C2 (1 << 20) | ||
| 155 | #define OMAP24XX_AUTO_I2C1 (1 << 19) | ||
| 156 | #define OMAP24XX_AUTO_MCSPI2 (1 << 18) | ||
| 157 | #define OMAP24XX_AUTO_MCSPI1 (1 << 17) | ||
| 158 | #define OMAP24XX_AUTO_MCBSP2 (1 << 16) | ||
| 159 | #define OMAP24XX_AUTO_MCBSP1 (1 << 15) | ||
| 160 | #define OMAP24XX_AUTO_GPT12 (1 << 14) | ||
| 161 | #define OMAP24XX_AUTO_GPT11 (1 << 13) | ||
| 162 | #define OMAP24XX_AUTO_GPT10 (1 << 12) | ||
| 163 | #define OMAP24XX_AUTO_GPT9 (1 << 11) | ||
| 164 | #define OMAP24XX_AUTO_GPT8 (1 << 10) | ||
| 165 | #define OMAP24XX_AUTO_GPT7 (1 << 9) | ||
| 166 | #define OMAP24XX_AUTO_GPT6 (1 << 8) | ||
| 167 | #define OMAP24XX_AUTO_GPT5 (1 << 7) | ||
| 168 | #define OMAP24XX_AUTO_GPT4 (1 << 6) | ||
| 169 | #define OMAP24XX_AUTO_GPT3 (1 << 5) | ||
| 170 | #define OMAP24XX_AUTO_GPT2 (1 << 4) | ||
| 171 | #define OMAP2420_AUTO_VLYNQ (1 << 3) | ||
| 172 | #define OMAP24XX_AUTO_DSS (1 << 0) | ||
| 173 | |||
| 174 | /* CM_AUTOIDLE2_CORE */ | ||
| 175 | #define OMAP2430_AUTO_MDM_INTC (1 << 11) | ||
| 176 | #define OMAP2430_AUTO_GPIO5 (1 << 10) | ||
| 177 | #define OMAP2430_AUTO_MCSPI3 (1 << 9) | ||
| 178 | #define OMAP2430_AUTO_MMCHS2 (1 << 8) | ||
| 179 | #define OMAP2430_AUTO_MMCHS1 (1 << 7) | ||
| 180 | #define OMAP2430_AUTO_USBHS (1 << 6) | ||
| 181 | #define OMAP2430_AUTO_MCBSP5 (1 << 5) | ||
| 182 | #define OMAP2430_AUTO_MCBSP4 (1 << 4) | ||
| 183 | #define OMAP2430_AUTO_MCBSP3 (1 << 3) | ||
| 184 | #define OMAP24XX_AUTO_UART3 (1 << 2) | ||
| 185 | #define OMAP24XX_AUTO_SSI (1 << 1) | ||
| 186 | #define OMAP24XX_AUTO_USB (1 << 0) | ||
| 187 | |||
| 188 | /* CM_AUTOIDLE3_CORE */ | ||
| 189 | #define OMAP24XX_AUTO_SDRC (1 << 2) | ||
| 190 | #define OMAP24XX_AUTO_GPMC (1 << 1) | ||
| 191 | #define OMAP24XX_AUTO_SDMA (1 << 0) | ||
| 192 | |||
| 193 | /* CM_AUTOIDLE4_CORE */ | ||
| 194 | #define OMAP24XX_AUTO_PKA (1 << 4) | ||
| 195 | #define OMAP24XX_AUTO_AES (1 << 3) | ||
| 196 | #define OMAP24XX_AUTO_RNG (1 << 2) | ||
| 197 | #define OMAP24XX_AUTO_SHA (1 << 1) | ||
| 198 | #define OMAP24XX_AUTO_DES (1 << 0) | ||
| 199 | |||
| 200 | /* CM_CLKSEL1_CORE */ | ||
| 201 | #define OMAP24XX_CLKSEL_USB_SHIFT 25 | ||
| 202 | #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) | ||
| 203 | #define OMAP24XX_CLKSEL_SSI_SHIFT 20 | ||
| 204 | #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) | ||
| 205 | #define OMAP2420_CLKSEL_VLYNQ_SHIFT 15 | ||
| 206 | #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) | ||
| 207 | #define OMAP24XX_CLKSEL_DSS2_SHIFT 13 | ||
| 208 | #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) | ||
| 209 | #define OMAP24XX_CLKSEL_DSS1_SHIFT 8 | ||
| 210 | #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) | ||
| 211 | #define OMAP24XX_CLKSEL_L4_SHIFT 5 | ||
| 212 | #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) | ||
| 213 | #define OMAP24XX_CLKSEL_L3_SHIFT 0 | ||
| 214 | #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) | ||
| 215 | |||
| 216 | /* CM_CLKSEL2_CORE */ | ||
| 217 | #define OMAP24XX_CLKSEL_GPT12_SHIFT 22 | ||
| 218 | #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) | ||
| 219 | #define OMAP24XX_CLKSEL_GPT11_SHIFT 20 | ||
| 220 | #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) | ||
| 221 | #define OMAP24XX_CLKSEL_GPT10_SHIFT 18 | ||
| 222 | #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) | ||
| 223 | #define OMAP24XX_CLKSEL_GPT9_SHIFT 16 | ||
| 224 | #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) | ||
| 225 | #define OMAP24XX_CLKSEL_GPT8_SHIFT 14 | ||
| 226 | #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) | ||
| 227 | #define OMAP24XX_CLKSEL_GPT7_SHIFT 12 | ||
| 228 | #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) | ||
| 229 | #define OMAP24XX_CLKSEL_GPT6_SHIFT 10 | ||
| 230 | #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) | ||
| 231 | #define OMAP24XX_CLKSEL_GPT5_SHIFT 8 | ||
| 232 | #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) | ||
| 233 | #define OMAP24XX_CLKSEL_GPT4_SHIFT 6 | ||
| 234 | #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) | ||
| 235 | #define OMAP24XX_CLKSEL_GPT3_SHIFT 4 | ||
| 236 | #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) | ||
| 237 | #define OMAP24XX_CLKSEL_GPT2_SHIFT 2 | ||
| 238 | #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) | ||
| 239 | |||
| 240 | /* CM_CLKSTCTRL_CORE */ | ||
| 241 | #define OMAP24XX_AUTOSTATE_DSS (1 << 2) | ||
| 242 | #define OMAP24XX_AUTOSTATE_L4 (1 << 1) | ||
| 243 | #define OMAP24XX_AUTOSTATE_L3 (1 << 0) | ||
| 244 | |||
| 245 | /* CM_FCLKEN_GFX */ | ||
| 246 | #define OMAP24XX_EN_3D_SHIFT 2 | ||
| 247 | #define OMAP24XX_EN_3D (1 << 2) | ||
| 248 | #define OMAP24XX_EN_2D_SHIFT 1 | ||
| 249 | #define OMAP24XX_EN_2D (1 << 1) | ||
| 250 | |||
| 251 | /* CM_ICLKEN_GFX specific bits */ | ||
| 252 | |||
| 253 | /* CM_IDLEST_GFX specific bits */ | ||
| 254 | |||
| 255 | /* CM_CLKSEL_GFX specific bits */ | ||
| 256 | |||
| 257 | /* CM_CLKSTCTRL_GFX */ | ||
| 258 | #define OMAP24XX_AUTOSTATE_GFX (1 << 0) | ||
| 259 | |||
| 260 | /* CM_FCLKEN_WKUP specific bits */ | ||
| 261 | |||
| 262 | /* CM_ICLKEN_WKUP specific bits */ | ||
| 263 | #define OMAP2430_EN_ICR_SHIFT 6 | ||
| 264 | #define OMAP2430_EN_ICR (1 << 6) | ||
| 265 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 | ||
| 266 | #define OMAP24XX_EN_OMAPCTRL (1 << 5) | ||
| 267 | #define OMAP24XX_EN_WDT1_SHIFT 4 | ||
| 268 | #define OMAP24XX_EN_WDT1 (1 << 4) | ||
| 269 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 | ||
| 270 | #define OMAP24XX_EN_32KSYNC (1 << 1) | ||
| 271 | |||
| 272 | /* CM_IDLEST_WKUP specific bits */ | ||
| 273 | #define OMAP2430_ST_ICR (1 << 6) | ||
| 274 | #define OMAP24XX_ST_OMAPCTRL (1 << 5) | ||
| 275 | #define OMAP24XX_ST_WDT1 (1 << 4) | ||
| 276 | #define OMAP24XX_ST_MPU_WDT (1 << 3) | ||
| 277 | #define OMAP24XX_ST_32KSYNC (1 << 1) | ||
| 278 | |||
| 279 | /* CM_AUTOIDLE_WKUP */ | ||
| 280 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) | ||
| 281 | #define OMAP24XX_AUTO_WDT1 (1 << 4) | ||
| 282 | #define OMAP24XX_AUTO_MPU_WDT (1 << 3) | ||
| 283 | #define OMAP24XX_AUTO_GPIOS (1 << 2) | ||
| 284 | #define OMAP24XX_AUTO_32KSYNC (1 << 1) | ||
| 285 | #define OMAP24XX_AUTO_GPT1 (1 << 0) | ||
| 286 | |||
| 287 | /* CM_CLKSEL_WKUP */ | ||
| 288 | #define OMAP24XX_CLKSEL_GPT1_SHIFT 0 | ||
| 289 | #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) | ||
| 290 | |||
| 291 | /* CM_CLKEN_PLL */ | ||
| 292 | #define OMAP24XX_EN_54M_PLL_SHIFT 6 | ||
| 293 | #define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6) | ||
| 294 | #define OMAP24XX_EN_96M_PLL_SHIFT 2 | ||
| 295 | #define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) | ||
| 296 | #define OMAP24XX_EN_DPLL_SHIFT 0 | ||
| 297 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) | ||
| 298 | |||
| 299 | /* CM_IDLEST_CKGEN */ | ||
| 300 | #define OMAP24XX_ST_54M_APLL (1 << 9) | ||
| 301 | #define OMAP24XX_ST_96M_APLL (1 << 8) | ||
| 302 | #define OMAP24XX_ST_54M_CLK (1 << 6) | ||
| 303 | #define OMAP24XX_ST_12M_CLK (1 << 5) | ||
| 304 | #define OMAP24XX_ST_48M_CLK (1 << 4) | ||
| 305 | #define OMAP24XX_ST_96M_CLK (1 << 2) | ||
| 306 | #define OMAP24XX_ST_CORE_CLK_SHIFT 0 | ||
| 307 | #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) | ||
| 308 | |||
| 309 | /* CM_AUTOIDLE_PLL */ | ||
| 310 | #define OMAP24XX_AUTO_54M_SHIFT 6 | ||
| 311 | #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) | ||
| 312 | #define OMAP24XX_AUTO_96M_SHIFT 2 | ||
| 313 | #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) | ||
| 314 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 | ||
| 315 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) | ||
| 316 | |||
| 317 | /* CM_CLKSEL1_PLL */ | ||
| 318 | #define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 | ||
| 319 | #define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28) | ||
| 320 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 | ||
| 321 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) | ||
| 322 | #define OMAP24XX_DPLL_MULT_SHIFT 12 | ||
| 323 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) | ||
| 324 | #define OMAP24XX_DPLL_DIV_SHIFT 8 | ||
| 325 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) | ||
| 326 | #define OMAP24XX_54M_SOURCE_SHIFT 5 | ||
| 327 | #define OMAP24XX_54M_SOURCE (1 << 5) | ||
| 328 | #define OMAP2430_96M_SOURCE_SHIFT 4 | ||
| 329 | #define OMAP2430_96M_SOURCE (1 << 4) | ||
| 330 | #define OMAP24XX_48M_SOURCE_SHIFT 3 | ||
| 331 | #define OMAP24XX_48M_SOURCE (1 << 3) | ||
| 332 | #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 | ||
| 333 | #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) | ||
| 334 | |||
| 335 | /* CM_CLKSEL2_PLL */ | ||
| 336 | #define OMAP24XX_CORE_CLK_SRC_SHIFT 0 | ||
| 337 | #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) | ||
| 338 | |||
| 339 | /* CM_FCLKEN_DSP */ | ||
| 340 | #define OMAP2420_EN_IVA_COP_SHIFT 10 | ||
| 341 | #define OMAP2420_EN_IVA_COP (1 << 10) | ||
| 342 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 | ||
| 343 | #define OMAP2420_EN_IVA_MPU (1 << 8) | ||
| 344 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 | ||
| 345 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0) | ||
| 346 | |||
| 347 | /* CM_ICLKEN_DSP */ | ||
| 348 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 | ||
| 349 | #define OMAP2420_EN_DSP_IPI (1 << 1) | ||
| 350 | |||
| 351 | /* CM_IDLEST_DSP */ | ||
| 352 | #define OMAP2420_ST_IVA (1 << 8) | ||
| 353 | #define OMAP2420_ST_IPI (1 << 1) | ||
| 354 | #define OMAP24XX_ST_DSP (1 << 0) | ||
| 355 | |||
| 356 | /* CM_AUTOIDLE_DSP */ | ||
| 357 | #define OMAP2420_AUTO_DSP_IPI (1 << 1) | ||
| 358 | |||
| 359 | /* CM_CLKSEL_DSP */ | ||
| 360 | #define OMAP2420_SYNC_IVA (1 << 13) | ||
| 361 | #define OMAP2420_CLKSEL_IVA_SHIFT 8 | ||
| 362 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) | ||
| 363 | #define OMAP24XX_SYNC_DSP (1 << 7) | ||
| 364 | #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 | ||
| 365 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) | ||
| 366 | #define OMAP24XX_CLKSEL_DSP_SHIFT 0 | ||
| 367 | #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) | ||
| 368 | |||
| 369 | /* CM_CLKSTCTRL_DSP */ | ||
| 370 | #define OMAP2420_AUTOSTATE_IVA (1 << 8) | ||
| 371 | #define OMAP24XX_AUTOSTATE_DSP (1 << 0) | ||
| 372 | |||
| 373 | /* CM_FCLKEN_MDM */ | ||
| 374 | /* 2430 only */ | ||
| 375 | #define OMAP2430_EN_OSC_SHIFT 1 | ||
| 376 | #define OMAP2430_EN_OSC (1 << 1) | ||
| 377 | |||
| 378 | /* CM_ICLKEN_MDM */ | ||
| 379 | /* 2430 only */ | ||
| 380 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 | ||
| 381 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0) | ||
| 382 | |||
| 383 | /* CM_IDLEST_MDM specific bits */ | ||
| 384 | /* 2430 only */ | ||
| 385 | |||
| 386 | /* CM_AUTOIDLE_MDM */ | ||
| 387 | /* 2430 only */ | ||
| 388 | #define OMAP2430_AUTO_OSC (1 << 1) | ||
| 389 | #define OMAP2430_AUTO_MDM (1 << 0) | ||
| 390 | |||
| 391 | /* CM_CLKSEL_MDM */ | ||
| 392 | /* 2430 only */ | ||
| 393 | #define OMAP2430_SYNC_MDM (1 << 4) | ||
| 394 | #define OMAP2430_CLKSEL_MDM_SHIFT 0 | ||
| 395 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) | ||
| 396 | |||
| 397 | /* CM_CLKSTCTRL_MDM */ | ||
| 398 | /* 2430 only */ | ||
| 399 | #define OMAP2430_AUTOSTATE_MDM (1 << 0) | ||
| 400 | |||
| 401 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h new file mode 100644 index 000000000000..8489f3029fed --- /dev/null +++ b/arch/arm/mach-omap2/cm.h | |||
| @@ -0,0 +1,124 @@ | |||
| 1 | #ifndef __ARCH_ASM_MACH_OMAP2_CM_H | ||
| 2 | #define __ARCH_ASM_MACH_OMAP2_CM_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2/3 Clock Management (CM) register definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "prcm-common.h" | ||
| 18 | |||
| 19 | #ifndef __ASSEMBLER__ | ||
| 20 | #define OMAP_CM_REGADDR(module, reg) \ | ||
| 21 | (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) | ||
| 22 | #else | ||
| 23 | #define OMAP2420_CM_REGADDR(module, reg) \ | ||
| 24 | IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) | ||
| 25 | #define OMAP2430_CM_REGADDR(module, reg) \ | ||
| 26 | IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) | ||
| 27 | #define OMAP34XX_CM_REGADDR(module, reg) \ | ||
| 28 | IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) | ||
| 29 | #endif | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Architecture-specific global CM registers | ||
| 33 | * Use cm_{read,write}_reg() with these registers. | ||
| 34 | * These registers appear once per CM module. | ||
| 35 | */ | ||
| 36 | |||
| 37 | #define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) | ||
| 38 | #define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) | ||
| 39 | #define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) | ||
| 40 | |||
| 41 | #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * Module specific CM registers from CM_BASE + domain offset | ||
| 45 | * Use cm_{read,write}_mod_reg() with these registers. | ||
| 46 | * These register offsets generally appear in more than one PRCM submodule. | ||
| 47 | */ | ||
| 48 | |||
| 49 | /* Common between 24xx and 34xx */ | ||
| 50 | |||
| 51 | #define CM_FCLKEN 0x0000 | ||
| 52 | #define CM_FCLKEN1 CM_FCLKEN | ||
| 53 | #define CM_CLKEN CM_FCLKEN | ||
| 54 | #define CM_ICLKEN 0x0010 | ||
| 55 | #define CM_ICLKEN1 CM_ICLKEN | ||
| 56 | #define CM_ICLKEN2 0x0014 | ||
| 57 | #define CM_ICLKEN3 0x0018 | ||
| 58 | #define CM_IDLEST 0x0020 | ||
| 59 | #define CM_IDLEST1 CM_IDLEST | ||
| 60 | #define CM_IDLEST2 0x0024 | ||
| 61 | #define CM_AUTOIDLE 0x0030 | ||
| 62 | #define CM_AUTOIDLE1 CM_AUTOIDLE | ||
| 63 | #define CM_AUTOIDLE2 0x0034 | ||
| 64 | #define CM_AUTOIDLE3 0x0038 | ||
| 65 | #define CM_CLKSEL 0x0040 | ||
| 66 | #define CM_CLKSEL1 CM_CLKSEL | ||
| 67 | #define CM_CLKSEL2 0x0044 | ||
| 68 | #define CM_CLKSTCTRL 0x0048 | ||
| 69 | |||
| 70 | |||
| 71 | /* Architecture-specific registers */ | ||
| 72 | |||
| 73 | #define OMAP24XX_CM_FCLKEN2 0x0004 | ||
| 74 | #define OMAP24XX_CM_ICLKEN4 0x001c | ||
| 75 | #define OMAP24XX_CM_AUTOIDLE4 0x003c | ||
| 76 | |||
| 77 | #define OMAP2430_CM_IDLEST3 0x0028 | ||
| 78 | |||
| 79 | #define OMAP3430_CM_CLKEN_PLL 0x0004 | ||
| 80 | #define OMAP3430ES2_CM_CLKEN2 0x0004 | ||
| 81 | #define OMAP3430ES2_CM_FCLKEN3 0x0008 | ||
| 82 | #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 | ||
| 83 | #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 | ||
| 84 | #define OMAP3430_CM_CLKSEL1 CM_CLKSEL | ||
| 85 | #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL | ||
| 86 | #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 | ||
| 87 | #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 | ||
| 88 | #define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL | ||
| 89 | #define OMAP3430_CM_CLKSTST 0x004c | ||
| 90 | #define OMAP3430ES2_CM_CLKSEL4 0x004c | ||
| 91 | #define OMAP3430ES2_CM_CLKSEL5 0x0050 | ||
| 92 | #define OMAP3430_CM_CLKSEL2_EMU 0x0050 | ||
| 93 | #define OMAP3430_CM_CLKSEL3_EMU 0x0054 | ||
| 94 | |||
| 95 | |||
| 96 | /* Clock management domain register get/set */ | ||
| 97 | |||
| 98 | #ifndef __ASSEMBLER__ | ||
| 99 | static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx) | ||
| 100 | { | ||
| 101 | __raw_writel(val, OMAP_CM_REGADDR(module, idx)); | ||
| 102 | } | ||
| 103 | |||
| 104 | static inline u32 cm_read_mod_reg(s16 module, s16 idx) | ||
| 105 | { | ||
| 106 | return __raw_readl(OMAP_CM_REGADDR(module, idx)); | ||
| 107 | } | ||
| 108 | #endif | ||
| 109 | |||
| 110 | /* CM register bits shared between 24XX and 3430 */ | ||
| 111 | |||
| 112 | /* CM_CLKSEL_GFX */ | ||
| 113 | #define OMAP_CLKSEL_GFX_SHIFT 0 | ||
| 114 | #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) | ||
| 115 | |||
| 116 | /* CM_ICLKEN_GFX */ | ||
| 117 | #define OMAP_EN_GFX_SHIFT 0 | ||
| 118 | #define OMAP_EN_GFX (1 << 0) | ||
| 119 | |||
| 120 | /* CM_IDLEST_GFX */ | ||
| 121 | #define OMAP_ST_GFX (1 << 0) | ||
| 122 | |||
| 123 | |||
| 124 | #endif | ||
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c new file mode 100644 index 000000000000..a5d86a49c213 --- /dev/null +++ b/arch/arm/mach-omap2/control.c | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2/3 System Control Module register access | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Written by Paul Walmsley | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | #undef DEBUG | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | |||
| 17 | #include <asm/io.h> | ||
| 18 | |||
| 19 | #include <asm/arch/control.h> | ||
| 20 | |||
| 21 | static u32 omap2_ctrl_base; | ||
| 22 | |||
| 23 | #define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base \ | ||
| 24 | + (reg)) | ||
| 25 | |||
| 26 | void omap_ctrl_base_set(u32 base) | ||
| 27 | { | ||
| 28 | omap2_ctrl_base = base; | ||
| 29 | } | ||
| 30 | |||
| 31 | u32 omap_ctrl_base_get(void) | ||
| 32 | { | ||
| 33 | return omap2_ctrl_base; | ||
| 34 | } | ||
| 35 | |||
| 36 | u8 omap_ctrl_readb(u16 offset) | ||
| 37 | { | ||
| 38 | return __raw_readb(OMAP_CTRL_REGADDR(offset)); | ||
| 39 | } | ||
| 40 | |||
| 41 | u16 omap_ctrl_readw(u16 offset) | ||
| 42 | { | ||
| 43 | return __raw_readw(OMAP_CTRL_REGADDR(offset)); | ||
| 44 | } | ||
| 45 | |||
| 46 | u32 omap_ctrl_readl(u16 offset) | ||
| 47 | { | ||
| 48 | return __raw_readl(OMAP_CTRL_REGADDR(offset)); | ||
| 49 | } | ||
| 50 | |||
| 51 | void omap_ctrl_writeb(u8 val, u16 offset) | ||
| 52 | { | ||
| 53 | pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val, | ||
| 54 | (u32)OMAP_CTRL_REGADDR(offset)); | ||
| 55 | |||
| 56 | __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); | ||
| 57 | } | ||
| 58 | |||
| 59 | void omap_ctrl_writew(u16 val, u16 offset) | ||
| 60 | { | ||
| 61 | pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val, | ||
| 62 | (u32)OMAP_CTRL_REGADDR(offset)); | ||
| 63 | |||
| 64 | __raw_writew(val, OMAP_CTRL_REGADDR(offset)); | ||
| 65 | } | ||
| 66 | |||
| 67 | void omap_ctrl_writel(u32 val, u16 offset) | ||
| 68 | { | ||
| 69 | pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val, | ||
| 70 | (u32)OMAP_CTRL_REGADDR(offset)); | ||
| 71 | |||
| 72 | __raw_writel(val, OMAP_CTRL_REGADDR(offset)); | ||
| 73 | } | ||
| 74 | |||
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h new file mode 100644 index 000000000000..cacb34086e35 --- /dev/null +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -0,0 +1,317 @@ | |||
| 1 | #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H | ||
| 2 | #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2/3 PRCM base and module definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | |||
| 18 | /* Module offsets from both CM_BASE & PRM_BASE */ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Offsets that are the same on 24xx and 34xx | ||
| 22 | * | ||
| 23 | * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is | ||
| 24 | * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. | ||
| 25 | */ | ||
| 26 | #define OCP_MOD 0x000 | ||
| 27 | #define MPU_MOD 0x100 | ||
| 28 | #define CORE_MOD 0x200 | ||
| 29 | #define GFX_MOD 0x300 | ||
| 30 | #define WKUP_MOD 0x400 | ||
| 31 | #define PLL_MOD 0x500 | ||
| 32 | |||
| 33 | |||
| 34 | /* Chip-specific module offsets */ | ||
| 35 | #define OMAP24XX_DSP_MOD 0x800 | ||
| 36 | |||
| 37 | #define OMAP2430_MDM_MOD 0xc00 | ||
| 38 | |||
| 39 | /* IVA2 module is < base on 3430 */ | ||
| 40 | #define OMAP3430_IVA2_MOD -0x800 | ||
| 41 | #define OMAP3430ES2_SGX_MOD GFX_MOD | ||
| 42 | #define OMAP3430_CCR_MOD PLL_MOD | ||
| 43 | #define OMAP3430_DSS_MOD 0x600 | ||
| 44 | #define OMAP3430_CAM_MOD 0x700 | ||
| 45 | #define OMAP3430_PER_MOD 0x800 | ||
| 46 | #define OMAP3430_EMU_MOD 0x900 | ||
| 47 | #define OMAP3430_GR_MOD 0xa00 | ||
| 48 | #define OMAP3430_NEON_MOD 0xb00 | ||
| 49 | #define OMAP3430ES2_USBHOST_MOD 0xc00 | ||
| 50 | |||
| 51 | |||
| 52 | /* 24XX register bits shared between CM & PRM registers */ | ||
| 53 | |||
| 54 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | ||
| 55 | #define OMAP2420_EN_MMC_SHIFT 26 | ||
| 56 | #define OMAP2420_EN_MMC (1 << 26) | ||
| 57 | #define OMAP24XX_EN_UART2_SHIFT 22 | ||
| 58 | #define OMAP24XX_EN_UART2 (1 << 22) | ||
| 59 | #define OMAP24XX_EN_UART1_SHIFT 21 | ||
| 60 | #define OMAP24XX_EN_UART1 (1 << 21) | ||
| 61 | #define OMAP24XX_EN_MCSPI2_SHIFT 18 | ||
| 62 | #define OMAP24XX_EN_MCSPI2 (1 << 18) | ||
| 63 | #define OMAP24XX_EN_MCSPI1_SHIFT 17 | ||
| 64 | #define OMAP24XX_EN_MCSPI1 (1 << 17) | ||
| 65 | #define OMAP24XX_EN_MCBSP2_SHIFT 16 | ||
| 66 | #define OMAP24XX_EN_MCBSP2 (1 << 16) | ||
| 67 | #define OMAP24XX_EN_MCBSP1_SHIFT 15 | ||
| 68 | #define OMAP24XX_EN_MCBSP1 (1 << 15) | ||
| 69 | #define OMAP24XX_EN_GPT12_SHIFT 14 | ||
| 70 | #define OMAP24XX_EN_GPT12 (1 << 14) | ||
| 71 | #define OMAP24XX_EN_GPT11_SHIFT 13 | ||
| 72 | #define OMAP24XX_EN_GPT11 (1 << 13) | ||
| 73 | #define OMAP24XX_EN_GPT10_SHIFT 12 | ||
| 74 | #define OMAP24XX_EN_GPT10 (1 << 12) | ||
| 75 | #define OMAP24XX_EN_GPT9_SHIFT 11 | ||
| 76 | #define OMAP24XX_EN_GPT9 (1 << 11) | ||
| 77 | #define OMAP24XX_EN_GPT8_SHIFT 10 | ||
| 78 | #define OMAP24XX_EN_GPT8 (1 << 10) | ||
| 79 | #define OMAP24XX_EN_GPT7_SHIFT 9 | ||
| 80 | #define OMAP24XX_EN_GPT7 (1 << 9) | ||
| 81 | #define OMAP24XX_EN_GPT6_SHIFT 8 | ||
| 82 | #define OMAP24XX_EN_GPT6 (1 << 8) | ||
| 83 | #define OMAP24XX_EN_GPT5_SHIFT 7 | ||
| 84 | #define OMAP24XX_EN_GPT5 (1 << 7) | ||
| 85 | #define OMAP24XX_EN_GPT4_SHIFT 6 | ||
| 86 | #define OMAP24XX_EN_GPT4 (1 << 6) | ||
| 87 | #define OMAP24XX_EN_GPT3_SHIFT 5 | ||
| 88 | #define OMAP24XX_EN_GPT3 (1 << 5) | ||
| 89 | #define OMAP24XX_EN_GPT2_SHIFT 4 | ||
| 90 | #define OMAP24XX_EN_GPT2 (1 << 4) | ||
| 91 | #define OMAP2420_EN_VLYNQ_SHIFT 3 | ||
| 92 | #define OMAP2420_EN_VLYNQ (1 << 3) | ||
| 93 | |||
| 94 | /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | ||
| 95 | #define OMAP2430_EN_GPIO5_SHIFT 10 | ||
| 96 | #define OMAP2430_EN_GPIO5 (1 << 10) | ||
| 97 | #define OMAP2430_EN_MCSPI3_SHIFT 9 | ||
| 98 | #define OMAP2430_EN_MCSPI3 (1 << 9) | ||
| 99 | #define OMAP2430_EN_MMCHS2_SHIFT 8 | ||
| 100 | #define OMAP2430_EN_MMCHS2 (1 << 8) | ||
| 101 | #define OMAP2430_EN_MMCHS1_SHIFT 7 | ||
| 102 | #define OMAP2430_EN_MMCHS1 (1 << 7) | ||
| 103 | #define OMAP24XX_EN_UART3_SHIFT 2 | ||
| 104 | #define OMAP24XX_EN_UART3 (1 << 2) | ||
| 105 | #define OMAP24XX_EN_USB_SHIFT 0 | ||
| 106 | #define OMAP24XX_EN_USB (1 << 0) | ||
| 107 | |||
| 108 | /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | ||
| 109 | #define OMAP2430_EN_MDM_INTC_SHIFT 11 | ||
| 110 | #define OMAP2430_EN_MDM_INTC (1 << 11) | ||
| 111 | #define OMAP2430_EN_USBHS_SHIFT 6 | ||
| 112 | #define OMAP2430_EN_USBHS (1 << 6) | ||
| 113 | |||
| 114 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ | ||
| 115 | #define OMAP2420_ST_MMC (1 << 26) | ||
| 116 | #define OMAP24XX_ST_UART2 (1 << 22) | ||
| 117 | #define OMAP24XX_ST_UART1 (1 << 21) | ||
| 118 | #define OMAP24XX_ST_MCSPI2 (1 << 18) | ||
| 119 | #define OMAP24XX_ST_MCSPI1 (1 << 17) | ||
| 120 | #define OMAP24XX_ST_GPT12 (1 << 14) | ||
| 121 | #define OMAP24XX_ST_GPT11 (1 << 13) | ||
| 122 | #define OMAP24XX_ST_GPT10 (1 << 12) | ||
| 123 | #define OMAP24XX_ST_GPT9 (1 << 11) | ||
| 124 | #define OMAP24XX_ST_GPT8 (1 << 10) | ||
| 125 | #define OMAP24XX_ST_GPT7 (1 << 9) | ||
| 126 | #define OMAP24XX_ST_GPT6 (1 << 8) | ||
| 127 | #define OMAP24XX_ST_GPT5 (1 << 7) | ||
| 128 | #define OMAP24XX_ST_GPT4 (1 << 6) | ||
| 129 | #define OMAP24XX_ST_GPT3 (1 << 5) | ||
| 130 | #define OMAP24XX_ST_GPT2 (1 << 4) | ||
| 131 | #define OMAP2420_ST_VLYNQ (1 << 3) | ||
| 132 | |||
| 133 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ | ||
| 134 | #define OMAP2430_ST_MDM_INTC (1 << 11) | ||
| 135 | #define OMAP2430_ST_GPIO5 (1 << 10) | ||
| 136 | #define OMAP2430_ST_MCSPI3 (1 << 9) | ||
| 137 | #define OMAP2430_ST_MMCHS2 (1 << 8) | ||
| 138 | #define OMAP2430_ST_MMCHS1 (1 << 7) | ||
| 139 | #define OMAP2430_ST_USBHS (1 << 6) | ||
| 140 | #define OMAP24XX_ST_UART3 (1 << 2) | ||
| 141 | #define OMAP24XX_ST_USB (1 << 0) | ||
| 142 | |||
| 143 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | ||
| 144 | #define OMAP24XX_EN_GPIOS_SHIFT 2 | ||
| 145 | #define OMAP24XX_EN_GPIOS (1 << 2) | ||
| 146 | #define OMAP24XX_EN_GPT1_SHIFT 0 | ||
| 147 | #define OMAP24XX_EN_GPT1 (1 << 0) | ||
| 148 | |||
| 149 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ | ||
| 150 | #define OMAP24XX_ST_GPIOS (1 << 2) | ||
| 151 | #define OMAP24XX_ST_GPT1 (1 << 0) | ||
| 152 | |||
| 153 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ | ||
| 154 | #define OMAP2430_ST_MDM (1 << 0) | ||
| 155 | |||
| 156 | |||
| 157 | /* 3430 register bits shared between CM & PRM registers */ | ||
| 158 | |||
| 159 | /* CM_REVISION, PRM_REVISION shared bits */ | ||
| 160 | #define OMAP3430_REV_SHIFT 0 | ||
| 161 | #define OMAP3430_REV_MASK (0xff << 0) | ||
| 162 | |||
| 163 | /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ | ||
| 164 | #define OMAP3430_AUTOIDLE (1 << 0) | ||
| 165 | |||
| 166 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | ||
| 167 | #define OMAP3430_EN_MMC2 (1 << 25) | ||
| 168 | #define OMAP3430_EN_MMC2_SHIFT 25 | ||
| 169 | #define OMAP3430_EN_MMC1 (1 << 24) | ||
| 170 | #define OMAP3430_EN_MMC1_SHIFT 24 | ||
| 171 | #define OMAP3430_EN_MCSPI4 (1 << 21) | ||
| 172 | #define OMAP3430_EN_MCSPI4_SHIFT 21 | ||
| 173 | #define OMAP3430_EN_MCSPI3 (1 << 20) | ||
| 174 | #define OMAP3430_EN_MCSPI3_SHIFT 20 | ||
| 175 | #define OMAP3430_EN_MCSPI2 (1 << 19) | ||
| 176 | #define OMAP3430_EN_MCSPI2_SHIFT 19 | ||
| 177 | #define OMAP3430_EN_MCSPI1 (1 << 18) | ||
| 178 | #define OMAP3430_EN_MCSPI1_SHIFT 18 | ||
| 179 | #define OMAP3430_EN_I2C3 (1 << 17) | ||
| 180 | #define OMAP3430_EN_I2C3_SHIFT 17 | ||
| 181 | #define OMAP3430_EN_I2C2 (1 << 16) | ||
| 182 | #define OMAP3430_EN_I2C2_SHIFT 16 | ||
| 183 | #define OMAP3430_EN_I2C1 (1 << 15) | ||
| 184 | #define OMAP3430_EN_I2C1_SHIFT 15 | ||
| 185 | #define OMAP3430_EN_UART2 (1 << 14) | ||
| 186 | #define OMAP3430_EN_UART2_SHIFT 14 | ||
| 187 | #define OMAP3430_EN_UART1 (1 << 13) | ||
| 188 | #define OMAP3430_EN_UART1_SHIFT 13 | ||
| 189 | #define OMAP3430_EN_GPT11 (1 << 12) | ||
| 190 | #define OMAP3430_EN_GPT11_SHIFT 12 | ||
| 191 | #define OMAP3430_EN_GPT10 (1 << 11) | ||
| 192 | #define OMAP3430_EN_GPT10_SHIFT 11 | ||
| 193 | #define OMAP3430_EN_MCBSP5 (1 << 10) | ||
| 194 | #define OMAP3430_EN_MCBSP5_SHIFT 10 | ||
| 195 | #define OMAP3430_EN_MCBSP1 (1 << 9) | ||
| 196 | #define OMAP3430_EN_MCBSP1_SHIFT 9 | ||
| 197 | #define OMAP3430_EN_FSHOSTUSB (1 << 5) | ||
| 198 | #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 | ||
| 199 | #define OMAP3430_EN_D2D (1 << 3) | ||
| 200 | #define OMAP3430_EN_D2D_SHIFT 3 | ||
| 201 | |||
| 202 | /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | ||
| 203 | #define OMAP3430_EN_HSOTGUSB (1 << 4) | ||
| 204 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 | ||
| 205 | |||
| 206 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ | ||
| 207 | #define OMAP3430_ST_MMC2 (1 << 25) | ||
| 208 | #define OMAP3430_ST_MMC1 (1 << 24) | ||
| 209 | #define OMAP3430_ST_MCSPI4 (1 << 21) | ||
| 210 | #define OMAP3430_ST_MCSPI3 (1 << 20) | ||
| 211 | #define OMAP3430_ST_MCSPI2 (1 << 19) | ||
| 212 | #define OMAP3430_ST_MCSPI1 (1 << 18) | ||
| 213 | #define OMAP3430_ST_I2C3 (1 << 17) | ||
| 214 | #define OMAP3430_ST_I2C2 (1 << 16) | ||
| 215 | #define OMAP3430_ST_I2C1 (1 << 15) | ||
| 216 | #define OMAP3430_ST_UART2 (1 << 14) | ||
| 217 | #define OMAP3430_ST_UART1 (1 << 13) | ||
| 218 | #define OMAP3430_ST_GPT11 (1 << 12) | ||
| 219 | #define OMAP3430_ST_GPT10 (1 << 11) | ||
| 220 | #define OMAP3430_ST_MCBSP5 (1 << 10) | ||
| 221 | #define OMAP3430_ST_MCBSP1 (1 << 9) | ||
| 222 | #define OMAP3430_ST_FSHOSTUSB (1 << 5) | ||
| 223 | #define OMAP3430_ST_HSOTGUSB (1 << 4) | ||
| 224 | #define OMAP3430_ST_D2D (1 << 3) | ||
| 225 | |||
| 226 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | ||
| 227 | #define OMAP3430_EN_GPIO1 (1 << 3) | ||
| 228 | #define OMAP3430_EN_GPIO1_SHIFT 3 | ||
| 229 | #define OMAP3430_EN_GPT1 (1 << 0) | ||
| 230 | #define OMAP3430_EN_GPT1_SHIFT 0 | ||
| 231 | |||
| 232 | /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ | ||
| 233 | #define OMAP3430_EN_SR2 (1 << 7) | ||
| 234 | #define OMAP3430_EN_SR2_SHIFT 7 | ||
| 235 | #define OMAP3430_EN_SR1 (1 << 6) | ||
| 236 | #define OMAP3430_EN_SR1_SHIFT 6 | ||
| 237 | |||
| 238 | /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | ||
| 239 | #define OMAP3430_EN_GPT12 (1 << 1) | ||
| 240 | #define OMAP3430_EN_GPT12_SHIFT 1 | ||
| 241 | |||
| 242 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ | ||
| 243 | #define OMAP3430_ST_SR2 (1 << 7) | ||
| 244 | #define OMAP3430_ST_SR1 (1 << 6) | ||
| 245 | #define OMAP3430_ST_GPIO1 (1 << 3) | ||
| 246 | #define OMAP3430_ST_GPT12 (1 << 1) | ||
| 247 | #define OMAP3430_ST_GPT1 (1 << 0) | ||
| 248 | |||
| 249 | /* | ||
| 250 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, | ||
| 251 | * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, | ||
| 252 | * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits | ||
| 253 | */ | ||
| 254 | #define OMAP3430_EN_MPU (1 << 1) | ||
| 255 | #define OMAP3430_EN_MPU_SHIFT 1 | ||
| 256 | |||
| 257 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ | ||
| 258 | #define OMAP3430_EN_GPIO6 (1 << 17) | ||
| 259 | #define OMAP3430_EN_GPIO6_SHIFT 17 | ||
| 260 | #define OMAP3430_EN_GPIO5 (1 << 16) | ||
| 261 | #define OMAP3430_EN_GPIO5_SHIFT 16 | ||
| 262 | #define OMAP3430_EN_GPIO4 (1 << 15) | ||
| 263 | #define OMAP3430_EN_GPIO4_SHIFT 15 | ||
| 264 | #define OMAP3430_EN_GPIO3 (1 << 14) | ||
| 265 | #define OMAP3430_EN_GPIO3_SHIFT 14 | ||
| 266 | #define OMAP3430_EN_GPIO2 (1 << 13) | ||
| 267 | #define OMAP3430_EN_GPIO2_SHIFT 13 | ||
| 268 | #define OMAP3430_EN_UART3 (1 << 11) | ||
| 269 | #define OMAP3430_EN_UART3_SHIFT 11 | ||
| 270 | #define OMAP3430_EN_GPT9 (1 << 10) | ||
| 271 | #define OMAP3430_EN_GPT9_SHIFT 10 | ||
| 272 | #define OMAP3430_EN_GPT8 (1 << 9) | ||
| 273 | #define OMAP3430_EN_GPT8_SHIFT 9 | ||
| 274 | #define OMAP3430_EN_GPT7 (1 << 8) | ||
| 275 | #define OMAP3430_EN_GPT7_SHIFT 8 | ||
| 276 | #define OMAP3430_EN_GPT6 (1 << 7) | ||
| 277 | #define OMAP3430_EN_GPT6_SHIFT 7 | ||
| 278 | #define OMAP3430_EN_GPT5 (1 << 6) | ||
| 279 | #define OMAP3430_EN_GPT5_SHIFT 6 | ||
| 280 | #define OMAP3430_EN_GPT4 (1 << 5) | ||
| 281 | #define OMAP3430_EN_GPT4_SHIFT 5 | ||
| 282 | #define OMAP3430_EN_GPT3 (1 << 4) | ||
| 283 | #define OMAP3430_EN_GPT3_SHIFT 4 | ||
| 284 | #define OMAP3430_EN_GPT2 (1 << 3) | ||
| 285 | #define OMAP3430_EN_GPT2_SHIFT 3 | ||
| 286 | |||
| 287 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ | ||
| 288 | /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits | ||
| 289 | * be ST_* bits instead? */ | ||
| 290 | #define OMAP3430_EN_MCBSP4 (1 << 2) | ||
| 291 | #define OMAP3430_EN_MCBSP4_SHIFT 2 | ||
| 292 | #define OMAP3430_EN_MCBSP3 (1 << 1) | ||
| 293 | #define OMAP3430_EN_MCBSP3_SHIFT 1 | ||
| 294 | #define OMAP3430_EN_MCBSP2 (1 << 0) | ||
| 295 | #define OMAP3430_EN_MCBSP2_SHIFT 0 | ||
| 296 | |||
| 297 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ | ||
| 298 | #define OMAP3430_ST_GPIO6 (1 << 17) | ||
| 299 | #define OMAP3430_ST_GPIO5 (1 << 16) | ||
| 300 | #define OMAP3430_ST_GPIO4 (1 << 15) | ||
| 301 | #define OMAP3430_ST_GPIO3 (1 << 14) | ||
| 302 | #define OMAP3430_ST_GPIO2 (1 << 13) | ||
| 303 | #define OMAP3430_ST_UART3 (1 << 11) | ||
| 304 | #define OMAP3430_ST_GPT9 (1 << 10) | ||
| 305 | #define OMAP3430_ST_GPT8 (1 << 9) | ||
| 306 | #define OMAP3430_ST_GPT7 (1 << 8) | ||
| 307 | #define OMAP3430_ST_GPT6 (1 << 7) | ||
| 308 | #define OMAP3430_ST_GPT5 (1 << 6) | ||
| 309 | #define OMAP3430_ST_GPT4 (1 << 5) | ||
| 310 | #define OMAP3430_ST_GPT3 (1 << 4) | ||
| 311 | #define OMAP3430_ST_GPT2 (1 << 3) | ||
| 312 | |||
| 313 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ | ||
| 314 | #define OMAP3430_EN_CORE (1 << 0) | ||
| 315 | |||
| 316 | #endif | ||
| 317 | |||
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h new file mode 100644 index 000000000000..c6d17a3378ec --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h | |||
| @@ -0,0 +1,279 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP24XX Power/Reset Management register bits | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "prm.h" | ||
| 18 | |||
| 19 | /* Bits shared between registers */ | ||
| 20 | |||
| 21 | /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ | ||
| 22 | #define OMAP24XX_VOLTTRANS_ST (1 << 2) | ||
| 23 | #define OMAP24XX_WKUP2_ST (1 << 1) | ||
| 24 | #define OMAP24XX_WKUP1_ST (1 << 0) | ||
| 25 | |||
| 26 | /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ | ||
| 27 | #define OMAP24XX_VOLTTRANS_EN (1 << 2) | ||
| 28 | #define OMAP24XX_WKUP2_EN (1 << 1) | ||
| 29 | #define OMAP24XX_WKUP1_EN (1 << 0) | ||
| 30 | |||
| 31 | /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ | ||
| 32 | #define OMAP24XX_EN_MPU (1 << 1) | ||
| 33 | #define OMAP24XX_EN_CORE (1 << 0) | ||
| 34 | |||
| 35 | /* | ||
| 36 | * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM | ||
| 37 | * shared bits | ||
| 38 | */ | ||
| 39 | #define OMAP24XX_MEMONSTATE_SHIFT 10 | ||
| 40 | #define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) | ||
| 41 | #define OMAP24XX_MEMRETSTATE (1 << 3) | ||
| 42 | |||
| 43 | /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ | ||
| 44 | #define OMAP24XX_FORCESTATE (1 << 18) | ||
| 45 | |||
| 46 | /* | ||
| 47 | * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, | ||
| 48 | * PM_PWSTST_MDM shared bits | ||
| 49 | */ | ||
| 50 | #define OMAP24XX_CLKACTIVITY (1 << 19) | ||
| 51 | |||
| 52 | /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ | ||
| 53 | #define OMAP24XX_LASTSTATEENTERED_SHIFT 4 | ||
| 54 | #define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4) | ||
| 55 | |||
| 56 | /* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */ | ||
| 57 | #define OMAP2430_MEMSTATEST_SHIFT 10 | ||
| 58 | #define OMAP2430_MEMSTATEST_MASK (0x3 << 10) | ||
| 59 | |||
| 60 | /* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */ | ||
| 61 | #define OMAP24XX_POWERSTATEST_SHIFT 0 | ||
| 62 | #define OMAP24XX_POWERSTATEST_MASK (0x3 << 0) | ||
| 63 | |||
| 64 | |||
| 65 | /* Bits specific to each register */ | ||
| 66 | |||
| 67 | /* PRCM_REVISION */ | ||
| 68 | #define OMAP24XX_REV_SHIFT 0 | ||
| 69 | #define OMAP24XX_REV_MASK (0xff << 0) | ||
| 70 | |||
| 71 | /* PRCM_SYSCONFIG */ | ||
| 72 | #define OMAP24XX_AUTOIDLE (1 << 0) | ||
| 73 | |||
| 74 | /* PRCM_IRQSTATUS_MPU specific bits */ | ||
| 75 | #define OMAP2430_DPLL_RECAL_ST (1 << 6) | ||
| 76 | #define OMAP24XX_TRANSITION_ST (1 << 5) | ||
| 77 | #define OMAP24XX_EVGENOFF_ST (1 << 4) | ||
| 78 | #define OMAP24XX_EVGENON_ST (1 << 3) | ||
| 79 | |||
| 80 | /* PRCM_IRQENABLE_MPU specific bits */ | ||
| 81 | #define OMAP2430_DPLL_RECAL_EN (1 << 6) | ||
| 82 | #define OMAP24XX_TRANSITION_EN (1 << 5) | ||
| 83 | #define OMAP24XX_EVGENOFF_EN (1 << 4) | ||
| 84 | #define OMAP24XX_EVGENON_EN (1 << 3) | ||
| 85 | |||
| 86 | /* PRCM_VOLTCTRL */ | ||
| 87 | #define OMAP24XX_AUTO_EXTVOLT (1 << 15) | ||
| 88 | #define OMAP24XX_FORCE_EXTVOLT (1 << 14) | ||
| 89 | #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 | ||
| 90 | #define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) | ||
| 91 | #define OMAP24XX_MEMRETCTRL (1 << 8) | ||
| 92 | #define OMAP24XX_SETRET_LEVEL_SHIFT 6 | ||
| 93 | #define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) | ||
| 94 | #define OMAP24XX_VOLT_LEVEL_SHIFT 0 | ||
| 95 | #define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0) | ||
| 96 | |||
| 97 | /* PRCM_VOLTST */ | ||
| 98 | #define OMAP24XX_ST_VOLTLEVEL_SHIFT 0 | ||
| 99 | #define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0) | ||
| 100 | |||
| 101 | /* PRCM_CLKSRC_CTRL specific bits */ | ||
| 102 | |||
| 103 | /* PRCM_CLKOUT_CTRL */ | ||
| 104 | #define OMAP2420_CLKOUT2_EN_SHIFT 15 | ||
| 105 | #define OMAP2420_CLKOUT2_EN (1 << 15) | ||
| 106 | #define OMAP2420_CLKOUT2_DIV_SHIFT 11 | ||
| 107 | #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) | ||
| 108 | #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 | ||
| 109 | #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) | ||
| 110 | #define OMAP24XX_CLKOUT_EN_SHIFT 7 | ||
| 111 | #define OMAP24XX_CLKOUT_EN (1 << 7) | ||
| 112 | #define OMAP24XX_CLKOUT_DIV_SHIFT 3 | ||
| 113 | #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) | ||
| 114 | #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 | ||
| 115 | #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) | ||
| 116 | |||
| 117 | /* PRCM_CLKEMUL_CTRL */ | ||
| 118 | #define OMAP24XX_EMULATION_EN_SHIFT 0 | ||
| 119 | #define OMAP24XX_EMULATION_EN (1 << 0) | ||
| 120 | |||
| 121 | /* PRCM_CLKCFG_CTRL */ | ||
| 122 | #define OMAP24XX_VALID_CONFIG (1 << 0) | ||
| 123 | |||
| 124 | /* PRCM_CLKCFG_STATUS */ | ||
| 125 | #define OMAP24XX_CONFIG_STATUS (1 << 0) | ||
| 126 | |||
| 127 | /* PRCM_VOLTSETUP specific bits */ | ||
| 128 | |||
| 129 | /* PRCM_CLKSSETUP specific bits */ | ||
| 130 | |||
| 131 | /* PRCM_POLCTRL */ | ||
| 132 | #define OMAP2420_CLKOUT2_POL (1 << 10) | ||
| 133 | #define OMAP24XX_CLKOUT_POL (1 << 9) | ||
| 134 | #define OMAP24XX_CLKREQ_POL (1 << 8) | ||
| 135 | #define OMAP2430_USE_POWEROK (1 << 2) | ||
| 136 | #define OMAP2430_POWEROK_POL (1 << 1) | ||
| 137 | #define OMAP24XX_EXTVOL_POL (1 << 0) | ||
| 138 | |||
| 139 | /* RM_RSTST_MPU specific bits */ | ||
| 140 | /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ | ||
| 141 | |||
| 142 | /* PM_WKDEP_MPU specific bits */ | ||
| 143 | #define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5) | ||
| 144 | #define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2) | ||
| 145 | |||
| 146 | /* PM_EVGENCTRL_MPU specific bits */ | ||
| 147 | |||
| 148 | /* PM_EVEGENONTIM_MPU specific bits */ | ||
| 149 | |||
| 150 | /* PM_EVEGENOFFTIM_MPU specific bits */ | ||
| 151 | |||
| 152 | /* PM_PWSTCTRL_MPU specific bits */ | ||
| 153 | #define OMAP2430_FORCESTATE (1 << 18) | ||
| 154 | |||
| 155 | /* PM_PWSTST_MPU specific bits */ | ||
| 156 | /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ | ||
| 157 | |||
| 158 | /* PM_WKEN1_CORE specific bits */ | ||
| 159 | |||
| 160 | /* PM_WKEN2_CORE specific bits */ | ||
| 161 | |||
| 162 | /* PM_WKST1_CORE specific bits*/ | ||
| 163 | |||
| 164 | /* PM_WKST2_CORE specific bits */ | ||
| 165 | |||
| 166 | /* PM_WKDEP_CORE specific bits*/ | ||
| 167 | #define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5) | ||
| 168 | #define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3) | ||
| 169 | #define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2) | ||
| 170 | |||
| 171 | /* PM_PWSTCTRL_CORE specific bits */ | ||
| 172 | #define OMAP24XX_MEMORYCHANGE (1 << 20) | ||
| 173 | #define OMAP24XX_MEM3ONSTATE_SHIFT 14 | ||
| 174 | #define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) | ||
| 175 | #define OMAP24XX_MEM2ONSTATE_SHIFT 12 | ||
| 176 | #define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) | ||
| 177 | #define OMAP24XX_MEM1ONSTATE_SHIFT 10 | ||
| 178 | #define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) | ||
| 179 | #define OMAP24XX_MEM3RETSTATE (1 << 5) | ||
| 180 | #define OMAP24XX_MEM2RETSTATE (1 << 4) | ||
| 181 | #define OMAP24XX_MEM1RETSTATE (1 << 3) | ||
| 182 | |||
| 183 | /* PM_PWSTST_CORE specific bits */ | ||
| 184 | #define OMAP24XX_MEM3STATEST_SHIFT 14 | ||
| 185 | #define OMAP24XX_MEM3STATEST_MASK (0x3 << 14) | ||
| 186 | #define OMAP24XX_MEM2STATEST_SHIFT 12 | ||
| 187 | #define OMAP24XX_MEM2STATEST_MASK (0x3 << 12) | ||
| 188 | #define OMAP24XX_MEM1STATEST_SHIFT 10 | ||
| 189 | #define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) | ||
| 190 | |||
| 191 | /* RM_RSTCTRL_GFX */ | ||
| 192 | #define OMAP24XX_GFX_RST (1 << 0) | ||
| 193 | |||
| 194 | /* RM_RSTST_GFX specific bits */ | ||
| 195 | #define OMAP24XX_GFX_SW_RST (1 << 4) | ||
| 196 | |||
| 197 | /* PM_PWSTCTRL_GFX specific bits */ | ||
| 198 | |||
| 199 | /* PM_WKDEP_GFX specific bits */ | ||
| 200 | /* 2430 often calls EN_WAKEUP "EN_WKUP" */ | ||
| 201 | |||
| 202 | /* RM_RSTCTRL_WKUP specific bits */ | ||
| 203 | |||
| 204 | /* RM_RSTTIME_WKUP specific bits */ | ||
| 205 | |||
| 206 | /* RM_RSTST_WKUP specific bits */ | ||
| 207 | /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ | ||
| 208 | #define OMAP24XX_EXTWMPU_RST (1 << 6) | ||
| 209 | #define OMAP24XX_SECU_WD_RST (1 << 5) | ||
| 210 | #define OMAP24XX_MPU_WD_RST (1 << 4) | ||
| 211 | #define OMAP24XX_SECU_VIOL_RST (1 << 3) | ||
| 212 | |||
| 213 | /* PM_WKEN_WKUP specific bits */ | ||
| 214 | |||
| 215 | /* PM_WKST_WKUP specific bits */ | ||
| 216 | |||
| 217 | /* RM_RSTCTRL_DSP */ | ||
| 218 | #define OMAP2420_RST_IVA (1 << 8) | ||
| 219 | #define OMAP24XX_RST2_DSP (1 << 1) | ||
| 220 | #define OMAP24XX_RST1_DSP (1 << 0) | ||
| 221 | |||
| 222 | /* RM_RSTST_DSP specific bits */ | ||
| 223 | /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ | ||
| 224 | #define OMAP2420_IVA_SW_RST (1 << 8) | ||
| 225 | #define OMAP24XX_DSP_SW_RST2 (1 << 5) | ||
| 226 | #define OMAP24XX_DSP_SW_RST1 (1 << 4) | ||
| 227 | |||
| 228 | /* PM_WKDEP_DSP specific bits */ | ||
| 229 | |||
| 230 | /* PM_PWSTCTRL_DSP specific bits */ | ||
| 231 | /* 2430 only: MEMONSTATE, MEMRETSTATE */ | ||
| 232 | #define OMAP2420_MEMIONSTATE_SHIFT 12 | ||
| 233 | #define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) | ||
| 234 | #define OMAP2420_MEMIRETSTATE (1 << 4) | ||
| 235 | |||
| 236 | /* PM_PWSTST_DSP specific bits */ | ||
| 237 | /* MEMSTATEST is 2430 only */ | ||
| 238 | #define OMAP2420_MEMISTATEST_SHIFT 12 | ||
| 239 | #define OMAP2420_MEMISTATEST_MASK (0x3 << 12) | ||
| 240 | |||
| 241 | /* PRCM_IRQSTATUS_DSP specific bits */ | ||
| 242 | |||
| 243 | /* PRCM_IRQENABLE_DSP specific bits */ | ||
| 244 | |||
| 245 | /* RM_RSTCTRL_MDM */ | ||
| 246 | /* 2430 only */ | ||
| 247 | #define OMAP2430_PWRON1_MDM (1 << 1) | ||
| 248 | #define OMAP2430_RST1_MDM (1 << 0) | ||
| 249 | |||
| 250 | /* RM_RSTST_MDM specific bits */ | ||
| 251 | /* 2430 only */ | ||
| 252 | #define OMAP2430_MDM_SECU_VIOL (1 << 6) | ||
| 253 | #define OMAP2430_MDM_SW_PWRON1 (1 << 5) | ||
| 254 | #define OMAP2430_MDM_SW_RST1 (1 << 4) | ||
| 255 | |||
| 256 | /* PM_WKEN_MDM */ | ||
| 257 | /* 2430 only */ | ||
| 258 | #define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0) | ||
| 259 | |||
| 260 | /* PM_WKST_MDM specific bits */ | ||
| 261 | /* 2430 only */ | ||
| 262 | |||
| 263 | /* PM_WKDEP_MDM specific bits */ | ||
| 264 | /* 2430 only */ | ||
| 265 | |||
| 266 | /* PM_PWSTCTRL_MDM specific bits */ | ||
| 267 | /* 2430 only */ | ||
| 268 | #define OMAP2430_KILLDOMAINWKUP (1 << 19) | ||
| 269 | |||
| 270 | /* PM_PWSTST_MDM specific bits */ | ||
| 271 | /* 2430 only */ | ||
| 272 | |||
| 273 | /* PRCM_IRQSTATUS_IVA */ | ||
| 274 | /* 2420 only */ | ||
| 275 | |||
| 276 | /* PRCM_IRQENABLE_IVA */ | ||
| 277 | /* 2420 only */ | ||
| 278 | |||
| 279 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h new file mode 100644 index 000000000000..ab7649afd891 --- /dev/null +++ b/arch/arm/mach-omap2/prm.h | |||
| @@ -0,0 +1,316 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_PRM_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2/3 Power/Reset Management (PRM) register definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include "prcm-common.h" | ||
| 18 | |||
| 19 | #ifndef __ASSEMBLER__ | ||
| 20 | #define OMAP_PRM_REGADDR(module, reg) \ | ||
| 21 | (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) | ||
| 22 | #else | ||
| 23 | #define OMAP2420_PRM_REGADDR(module, reg) \ | ||
| 24 | IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) | ||
| 25 | #define OMAP2430_PRM_REGADDR(module, reg) \ | ||
| 26 | IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) | ||
| 27 | #define OMAP34XX_PRM_REGADDR(module, reg) \ | ||
| 28 | IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) | ||
| 29 | #endif | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Architecture-specific global PRM registers | ||
| 33 | * Use prm_{read,write}_reg() with these registers. | ||
| 34 | * | ||
| 35 | * With a few exceptions, these are the register names beginning with | ||
| 36 | * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the | ||
| 37 | * IRQSTATUS and IRQENABLE bits.) | ||
| 38 | * | ||
| 39 | */ | ||
| 40 | |||
| 41 | #define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) | ||
| 42 | #define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) | ||
| 43 | |||
| 44 | #define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 45 | #define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 46 | |||
| 47 | #define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050) | ||
| 48 | #define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) | ||
| 49 | #define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) | ||
| 50 | #define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) | ||
| 51 | #define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0078) | ||
| 52 | #define OMAP24XX_PRCM_CLKCFG_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0080) | ||
| 53 | #define OMAP24XX_PRCM_CLKCFG_STATUS OMAP_PRM_REGADDR(OCP_MOD, 0x0084) | ||
| 54 | #define OMAP24XX_PRCM_VOLTSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0090) | ||
| 55 | #define OMAP24XX_PRCM_CLKSSETUP OMAP_PRM_REGADDR(OCP_MOD, 0x0094) | ||
| 56 | #define OMAP24XX_PRCM_POLCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0098) | ||
| 57 | |||
| 58 | #define OMAP3430_PRM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0004) | ||
| 59 | #define OMAP3430_PRM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0014) | ||
| 60 | |||
| 61 | #define OMAP3430_PRM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 62 | #define OMAP3430_PRM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 63 | |||
| 64 | |||
| 65 | #define OMAP3430_PRM_VC_SMPS_SA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) | ||
| 66 | #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) | ||
| 67 | #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) | ||
| 68 | #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) | ||
| 69 | #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) | ||
| 70 | #define OMAP3430_PRM_VC_CH_CONF OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) | ||
| 71 | #define OMAP3430_PRM_VC_I2C_CFG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) | ||
| 72 | #define OMAP3430_PRM_VC_BYPASS_VAL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) | ||
| 73 | #define OMAP3430_PRM_RSTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) | ||
| 74 | #define OMAP3430_PRM_RSTTIME OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) | ||
| 75 | #define OMAP3430_PRM_RSTST OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) | ||
| 76 | #define OMAP3430_PRM_VOLTCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) | ||
| 77 | #define OMAP3430_PRM_SRAM_PCHARGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) | ||
| 78 | #define OMAP3430_PRM_CLKSRC_CTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) | ||
| 79 | #define OMAP3430_PRM_VOLTSETUP1 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) | ||
| 80 | #define OMAP3430_PRM_VOLTOFFSET OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) | ||
| 81 | #define OMAP3430_PRM_CLKSETUP OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) | ||
| 82 | #define OMAP3430_PRM_POLCTRL OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) | ||
| 83 | #define OMAP3430_PRM_VOLTSETUP2 OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) | ||
| 84 | #define OMAP3430_PRM_VP1_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) | ||
| 85 | #define OMAP3430_PRM_VP1_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) | ||
| 86 | #define OMAP3430_PRM_VP1_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) | ||
| 87 | #define OMAP3430_PRM_VP1_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) | ||
| 88 | #define OMAP3430_PRM_VP1_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) | ||
| 89 | #define OMAP3430_PRM_VP1_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) | ||
| 90 | #define OMAP3430_PRM_VP2_CONFIG OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) | ||
| 91 | #define OMAP3430_PRM_VP2_VSTEPMIN OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) | ||
| 92 | #define OMAP3430_PRM_VP2_VSTEPMAX OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) | ||
| 93 | #define OMAP3430_PRM_VP2_VLIMITTO OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) | ||
| 94 | #define OMAP3430_PRM_VP2_VOLTAGE OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) | ||
| 95 | #define OMAP3430_PRM_VP2_STATUS OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) | ||
| 96 | |||
| 97 | #define OMAP3430_PRM_CLKSEL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) | ||
| 98 | #define OMAP3430_PRM_CLKOUT_CTRL OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | ||
| 99 | |||
| 100 | /* | ||
| 101 | * Module specific PRM registers from PRM_BASE + domain offset | ||
| 102 | * | ||
| 103 | * Use prm_{read,write}_mod_reg() with these registers. | ||
| 104 | * | ||
| 105 | * With a few exceptions, these are the register names beginning with | ||
| 106 | * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS | ||
| 107 | * and IRQENABLE bits.) | ||
| 108 | * | ||
| 109 | */ | ||
| 110 | |||
| 111 | /* Registers appearing on both 24xx and 34xx */ | ||
| 112 | |||
| 113 | #define RM_RSTCTRL 0x0050 | ||
| 114 | #define RM_RSTTIME 0x0054 | ||
| 115 | #define RM_RSTST 0x0058 | ||
| 116 | |||
| 117 | #define PM_WKEN 0x00a0 | ||
| 118 | #define PM_WKEN1 PM_WKEN | ||
| 119 | #define PM_WKST 0x00b0 | ||
| 120 | #define PM_WKST1 PM_WKST | ||
| 121 | #define PM_WKDEP 0x00c8 | ||
| 122 | #define PM_EVGENCTRL 0x00d4 | ||
| 123 | #define PM_EVGENONTIM 0x00d8 | ||
| 124 | #define PM_EVGENOFFTIM 0x00dc | ||
| 125 | #define PM_PWSTCTRL 0x00e0 | ||
| 126 | #define PM_PWSTST 0x00e4 | ||
| 127 | |||
| 128 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 | ||
| 129 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL | ||
| 130 | |||
| 131 | #define OMAP3430_PM_IVAGRPSEL 0x00a8 | ||
| 132 | #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL | ||
| 133 | |||
| 134 | #define OMAP3430_PM_PREPWSTST 0x00e8 | ||
| 135 | |||
| 136 | #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 | ||
| 137 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc | ||
| 138 | |||
| 139 | |||
| 140 | /* Architecture-specific registers */ | ||
| 141 | |||
| 142 | #define OMAP24XX_PM_WKEN2 0x00a4 | ||
| 143 | #define OMAP24XX_PM_WKST2 0x00b4 | ||
| 144 | |||
| 145 | #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ | ||
| 146 | #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ | ||
| 147 | #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 | ||
| 148 | #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc | ||
| 149 | |||
| 150 | #ifndef __ASSEMBLER__ | ||
| 151 | |||
| 152 | /* Power/reset management domain register get/set */ | ||
| 153 | |||
| 154 | static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx) | ||
| 155 | { | ||
| 156 | __raw_writel(val, OMAP_PRM_REGADDR(module, idx)); | ||
| 157 | } | ||
| 158 | |||
| 159 | static inline u32 prm_read_mod_reg(s16 module, s16 idx) | ||
| 160 | { | ||
| 161 | return __raw_readl(OMAP_PRM_REGADDR(module, idx)); | ||
| 162 | } | ||
| 163 | |||
| 164 | #endif | ||
| 165 | |||
| 166 | /* | ||
| 167 | * Bits common to specific registers | ||
| 168 | * | ||
| 169 | * The 3430 register and bit names are generally used, | ||
| 170 | * since they tend to make more sense | ||
| 171 | */ | ||
| 172 | |||
| 173 | /* PM_EVGENONTIM_MPU */ | ||
| 174 | /* Named PM_EVEGENONTIM_MPU on the 24XX */ | ||
| 175 | #define OMAP_ONTIMEVAL_SHIFT 0 | ||
| 176 | #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) | ||
| 177 | |||
| 178 | /* PM_EVGENOFFTIM_MPU */ | ||
| 179 | /* Named PM_EVEGENOFFTIM_MPU on the 24XX */ | ||
| 180 | #define OMAP_OFFTIMEVAL_SHIFT 0 | ||
| 181 | #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) | ||
| 182 | |||
| 183 | /* PRM_CLKSETUP and PRCM_VOLTSETUP */ | ||
| 184 | /* Named PRCM_CLKSSETUP on the 24XX */ | ||
| 185 | #define OMAP_SETUP_TIME_SHIFT 0 | ||
| 186 | #define OMAP_SETUP_TIME_MASK (0xffff << 0) | ||
| 187 | |||
| 188 | /* PRM_CLKSRC_CTRL */ | ||
| 189 | /* Named PRCM_CLKSRC_CTRL on the 24XX */ | ||
| 190 | #define OMAP_SYSCLKDIV_SHIFT 6 | ||
| 191 | #define OMAP_SYSCLKDIV_MASK (0x3 << 6) | ||
| 192 | #define OMAP_AUTOEXTCLKMODE_SHIFT 3 | ||
| 193 | #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) | ||
| 194 | #define OMAP_SYSCLKSEL_SHIFT 0 | ||
| 195 | #define OMAP_SYSCLKSEL_MASK (0x3 << 0) | ||
| 196 | |||
| 197 | /* PM_EVGENCTRL_MPU */ | ||
| 198 | #define OMAP_OFFLOADMODE_SHIFT 3 | ||
| 199 | #define OMAP_OFFLOADMODE_MASK (0x3 << 3) | ||
| 200 | #define OMAP_ONLOADMODE_SHIFT 1 | ||
| 201 | #define OMAP_ONLOADMODE_MASK (0x3 << 1) | ||
| 202 | #define OMAP_ENABLE (1 << 0) | ||
| 203 | |||
| 204 | /* PRM_RSTTIME */ | ||
| 205 | /* Named RM_RSTTIME_WKUP on the 24xx */ | ||
| 206 | #define OMAP_RSTTIME2_SHIFT 8 | ||
| 207 | #define OMAP_RSTTIME2_MASK (0x1f << 8) | ||
| 208 | #define OMAP_RSTTIME1_SHIFT 0 | ||
| 209 | #define OMAP_RSTTIME1_MASK (0xff << 0) | ||
| 210 | |||
| 211 | |||
| 212 | /* PRM_RSTCTRL */ | ||
| 213 | /* Named RM_RSTCTRL_WKUP on the 24xx */ | ||
| 214 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ | ||
| 215 | #define OMAP_RST_DPLL3 (1 << 2) | ||
| 216 | #define OMAP_RST_GS (1 << 1) | ||
| 217 | |||
| 218 | |||
| 219 | /* | ||
| 220 | * Bits common to module-shared registers | ||
| 221 | * | ||
| 222 | * Not all registers of a particular type support all of these bits - | ||
| 223 | * check TRM if you are unsure | ||
| 224 | */ | ||
| 225 | |||
| 226 | /* | ||
| 227 | * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP | ||
| 228 | * | ||
| 229 | * 2430: PM_PWSTST_MDM | ||
| 230 | * | ||
| 231 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, | ||
| 232 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, | ||
| 233 | * PM_PWSTST_NEON | ||
| 234 | */ | ||
| 235 | #define OMAP_INTRANSITION (1 << 20) | ||
| 236 | |||
| 237 | |||
| 238 | /* | ||
| 239 | * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP | ||
| 240 | * | ||
| 241 | * 2430: PM_PWSTST_MDM | ||
| 242 | * | ||
| 243 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, | ||
| 244 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, | ||
| 245 | * PM_PWSTST_NEON | ||
| 246 | */ | ||
| 247 | #define OMAP_POWERSTATEST_SHIFT 0 | ||
| 248 | #define OMAP_POWERSTATEST_MASK (0x3 << 0) | ||
| 249 | |||
| 250 | /* | ||
| 251 | * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is | ||
| 252 | * called 'COREWKUP_RST' | ||
| 253 | * | ||
| 254 | * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, | ||
| 255 | * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON | ||
| 256 | */ | ||
| 257 | #define OMAP_COREDOMAINWKUP_RST (1 << 3) | ||
| 258 | |||
| 259 | /* | ||
| 260 | * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP | ||
| 261 | * | ||
| 262 | * 2430: RM_RSTST_MDM | ||
| 263 | * | ||
| 264 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU | ||
| 265 | */ | ||
| 266 | #define OMAP_DOMAINWKUP_RST (1 << 2) | ||
| 267 | |||
| 268 | /* | ||
| 269 | * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP | ||
| 270 | * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. | ||
| 271 | * | ||
| 272 | * 2430: RM_RSTST_MDM | ||
| 273 | * | ||
| 274 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU | ||
| 275 | */ | ||
| 276 | #define OMAP_GLOBALWARM_RST (1 << 1) | ||
| 277 | #define OMAP_GLOBALCOLD_RST (1 << 0) | ||
| 278 | |||
| 279 | /* | ||
| 280 | * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP | ||
| 281 | * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" | ||
| 282 | * | ||
| 283 | * 2430: PM_WKDEP_MDM | ||
| 284 | * | ||
| 285 | * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, | ||
| 286 | * PM_WKDEP_PER | ||
| 287 | */ | ||
| 288 | #define OMAP_EN_WKUP (1 << 4) | ||
| 289 | |||
| 290 | /* | ||
| 291 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 292 | * PM_PWSTCTRL_DSP | ||
| 293 | * | ||
| 294 | * 2430: PM_PWSTCTRL_MDM | ||
| 295 | * | ||
| 296 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 297 | * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, | ||
| 298 | * PM_PWSTCTRL_NEON | ||
| 299 | */ | ||
| 300 | #define OMAP_LOGICRETSTATE (1 << 2) | ||
| 301 | |||
| 302 | /* | ||
| 303 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 304 | * PM_PWSTCTRL_DSP, PM_PWSTST_MPU | ||
| 305 | * | ||
| 306 | * 2430: PM_PWSTCTRL_MDM shared bits | ||
| 307 | * | ||
| 308 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, | ||
| 309 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, | ||
| 310 | * PM_PWSTCTRL_NEON shared bits | ||
| 311 | */ | ||
| 312 | #define OMAP_POWERSTATE_SHIFT 0 | ||
| 313 | #define OMAP_POWERSTATE_MASK (0x3 << 0) | ||
| 314 | |||
| 315 | |||
| 316 | #endif | ||
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h new file mode 100644 index 000000000000..d7f23bc9550a --- /dev/null +++ b/arch/arm/mach-omap2/sdrc.h | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_SDRC_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * OMAP2 SDRC register definitions | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 8 | * Copyright (C) 2007 Nokia Corporation | ||
| 9 | * | ||
| 10 | * Written by Paul Walmsley | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | #undef DEBUG | ||
| 17 | |||
| 18 | #include <asm/arch/sdrc.h> | ||
| 19 | |||
| 20 | #ifndef __ASSEMBLER__ | ||
| 21 | extern unsigned long omap2_sdrc_base; | ||
| 22 | extern unsigned long omap2_sms_base; | ||
| 23 | |||
| 24 | #define OMAP_SDRC_REGADDR(reg) \ | ||
| 25 | (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg)) | ||
| 26 | #define OMAP_SMS_REGADDR(reg) \ | ||
| 27 | (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg)) | ||
| 28 | |||
| 29 | /* SDRC global register get/set */ | ||
| 30 | |||
| 31 | static inline void sdrc_write_reg(u32 val, u16 reg) | ||
| 32 | { | ||
| 33 | __raw_writel(val, OMAP_SDRC_REGADDR(reg)); | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline u32 sdrc_read_reg(u16 reg) | ||
| 37 | { | ||
| 38 | return __raw_readl(OMAP_SDRC_REGADDR(reg)); | ||
| 39 | } | ||
| 40 | |||
| 41 | /* SMS global register get/set */ | ||
| 42 | |||
| 43 | static inline void sms_write_reg(u32 val, u16 reg) | ||
| 44 | { | ||
| 45 | __raw_writel(val, OMAP_SMS_REGADDR(reg)); | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline u32 sms_read_reg(u16 reg) | ||
| 49 | { | ||
| 50 | return __raw_readl(OMAP_SMS_REGADDR(reg)); | ||
| 51 | } | ||
| 52 | #else | ||
| 53 | #define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) | ||
| 54 | #define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) | ||
| 55 | #define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) | ||
| 56 | #endif /* __ASSEMBLER__ */ | ||
| 57 | |||
| 58 | #endif | ||