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-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-apollon.c2
-rw-r--r--arch/arm/mach-omap2/board-generic.c2
-rw-r--r--arch/arm/mach-omap2/board-h4.c2
-rw-r--r--arch/arm/mach-omap2/board-ldp.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c7
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c8
-rw-r--r--arch/arm/mach-omap2/board-overo.c11
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c5
-rw-r--r--arch/arm/mach-omap2/board-rx51.c6
-rw-r--r--arch/arm/mach-omap2/board-zoom2.c2
-rw-r--r--arch/arm/mach-omap2/clock.c156
-rw-r--r--arch/arm/mach-omap2/clock.h6
-rw-r--r--arch/arm/mach-omap2/clock24xx.c37
-rw-r--r--arch/arm/mach-omap2/clock24xx.h4
-rw-r--r--arch/arm/mach-omap2/clock34xx.c155
-rw-r--r--arch/arm/mach-omap2/clock34xx.h85
-rw-r--r--arch/arm/mach-omap2/cm.h6
-rw-r--r--arch/arm/mach-omap2/io.c5
-rw-r--r--arch/arm/mach-omap2/mmc-twl4030.c6
-rw-r--r--arch/arm/mach-omap2/mux.c6
-rw-r--r--arch/arm/mach-omap2/pm.h3
-rw-r--r--arch/arm/mach-omap2/pm24xx.c2
-rw-r--r--arch/arm/mach-omap2/pm34xx.c51
-rw-r--r--arch/arm/mach-omap2/prcm.c43
-rw-r--r--arch/arm/mach-omap2/sdrc.c68
-rw-r--r--arch/arm/mach-omap2/serial.c197
-rw-r--r--arch/arm/mach-omap2/sram34xx.S143
31 files changed, 773 insertions, 255 deletions
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 9c3fdcdf76c3..8ec2a132904d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
141 141
142static void __init omap_2430sdp_init_irq(void) 142static void __init omap_2430sdp_init_irq(void)
143{ 143{
144 omap2_init_common_hw(NULL); 144 omap2_init_common_hw(NULL, NULL);
145 omap_init_irq(); 145 omap_init_irq();
146 omap_gpio_init(); 146 omap_gpio_init();
147} 147}
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 496a90e4ea7a..ac262cd74503 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = {
169 169
170static void __init omap_3430sdp_init_irq(void) 170static void __init omap_3430sdp_init_irq(void)
171{ 171{
172 omap2_init_common_hw(hyb18m512160af6_sdrc_params); 172 omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
173 omap_init_irq(); 173 omap_init_irq();
174 omap_gpio_init(); 174 omap_gpio_init();
175} 175}
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 57e477bd89c6..b0c7402248f7 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
59 59
60static void __init omap_4430sdp_init_irq(void) 60static void __init omap_4430sdp_init_irq(void)
61{ 61{
62 omap2_init_common_hw(NULL); 62 omap2_init_common_hw(NULL, NULL);
63#ifdef CONFIG_OMAP_32K_TIMER 63#ifdef CONFIG_OMAP_32K_TIMER
64 omap2_gp_clockevent_set_gptimer(1); 64 omap2_gp_clockevent_set_gptimer(1);
65#endif 65#endif
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 06dfba888b0c..dcfc20d03894 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -250,7 +250,7 @@ out:
250 250
251static void __init omap_apollon_init_irq(void) 251static void __init omap_apollon_init_irq(void)
252{ 252{
253 omap2_init_common_hw(NULL); 253 omap2_init_common_hw(NULL, NULL);
254 omap_init_irq(); 254 omap_init_irq();
255 omap_gpio_init(); 255 omap_gpio_init();
256 apollon_init_smc91x(); 256 apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3492162a65c3..fd00aa03690c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
33 33
34static void __init omap_generic_init_irq(void) 34static void __init omap_generic_init_irq(void)
35{ 35{
36 omap2_init_common_hw(NULL); 36 omap2_init_common_hw(NULL, NULL);
37 omap_init_irq(); 37 omap_init_irq();
38} 38}
39 39
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index e7d017cdc438..7b1d61d5bb2c 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
270 270
271static void __init omap_h4_init_irq(void) 271static void __init omap_h4_init_irq(void)
272{ 272{
273 omap2_init_common_hw(NULL); 273 omap2_init_common_hw(NULL, NULL);
274 omap_init_irq(); 274 omap_init_irq();
275 omap_gpio_init(); 275 omap_gpio_init();
276 h4_init_flash(); 276 h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8bc0a7dcb8d..ea383f88cb1b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
270 270
271static void __init omap_ldp_init_irq(void) 271static void __init omap_ldp_init_irq(void)
272{ 272{
273 omap2_init_common_hw(NULL); 273 omap2_init_common_hw(NULL, NULL);
274 omap_init_irq(); 274 omap_init_irq();
275 omap_gpio_init(); 275 omap_gpio_init();
276 ldp_init_smsc911x(); 276 ldp_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 991ac9c38032..e00ba128cece 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void)
282 282
283static void __init omap3_beagle_init_irq(void) 283static void __init omap3_beagle_init_irq(void)
284{ 284{
285 omap2_init_common_hw(mt46h32m32lf6_sdrc_params); 285 omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
286 mt46h32m32lf6_sdrc_params);
286 omap_init_irq(); 287 omap_init_irq();
287#ifdef CONFIG_OMAP_32K_TIMER 288#ifdef CONFIG_OMAP_32K_TIMER
288 omap2_gp_clockevent_set_gptimer(12); 289 omap2_gp_clockevent_set_gptimer(12);
@@ -408,6 +409,10 @@ static void __init omap3_beagle_init(void)
408 409
409 usb_musb_init(); 410 usb_musb_init();
410 omap3beagle_flash_init(); 411 omap3beagle_flash_init();
412
413 /* Ensure SDRC pins are mux'd for self-refresh */
414 omap_cfg_reg(H16_34XX_SDRC_CKE0);
415 omap_cfg_reg(H17_34XX_SDRC_CKE1);
411} 416}
412 417
413static void __init omap3_beagle_map_io(void) 418static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index cf3dd771a678..c4b144647dc5 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -280,7 +280,7 @@ struct spi_board_info omap3evm_spi_board_info[] = {
280 280
281static void __init omap3_evm_init_irq(void) 281static void __init omap3_evm_init_irq(void)
282{ 282{
283 omap2_init_common_hw(mt46h32m32lf6_sdrc_params); 283 omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
284 omap_init_irq(); 284 omap_init_irq();
285 omap_gpio_init(); 285 omap_gpio_init();
286 omap3evm_init_smc911x(); 286 omap3evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index e32aa23ce962..864ee3d021f7 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -40,6 +40,7 @@
40#include <mach/mcspi.h> 40#include <mach/mcspi.h>
41#include <mach/usb.h> 41#include <mach/usb.h>
42#include <mach/keypad.h> 42#include <mach/keypad.h>
43#include <mach/mux.h>
43 44
44#include "sdram-micron-mt46h32m32lf-6.h" 45#include "sdram-micron-mt46h32m32lf-6.h"
45#include "mmc-twl4030.h" 46#include "mmc-twl4030.h"
@@ -310,7 +311,8 @@ static int __init omap3pandora_i2c_init(void)
310 311
311static void __init omap3pandora_init_irq(void) 312static void __init omap3pandora_init_irq(void)
312{ 313{
313 omap2_init_common_hw(mt46h32m32lf6_sdrc_params); 314 omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
315 mt46h32m32lf6_sdrc_params);
314 omap_init_irq(); 316 omap_init_irq();
315 omap_gpio_init(); 317 omap_gpio_init();
316} 318}
@@ -397,6 +399,10 @@ static void __init omap3pandora_init(void)
397 omap3pandora_ads7846_init(); 399 omap3pandora_ads7846_init();
398 pandora_keys_gpio_init(); 400 pandora_keys_gpio_init();
399 usb_musb_init(); 401 usb_musb_init();
402
403 /* Ensure SDRC pins are mux'd for self-refresh */
404 omap_cfg_reg(H16_34XX_SDRC_CKE0);
405 omap_cfg_reg(H17_34XX_SDRC_CKE1);
400} 406}
401 407
402static void __init omap3pandora_map_io(void) 408static void __init omap3pandora_map_io(void)
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index dff5528fbfb5..6bce23004aa4 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -44,6 +44,7 @@
44#include <mach/gpmc.h> 44#include <mach/gpmc.h>
45#include <mach/hardware.h> 45#include <mach/hardware.h>
46#include <mach/nand.h> 46#include <mach/nand.h>
47#include <mach/mux.h>
47#include <mach/usb.h> 48#include <mach/usb.h>
48 49
49#include "sdram-micron-mt46h32m32lf-6.h" 50#include "sdram-micron-mt46h32m32lf-6.h"
@@ -51,6 +52,7 @@
51 52
52#define OVERO_GPIO_BT_XGATE 15 53#define OVERO_GPIO_BT_XGATE 15
53#define OVERO_GPIO_W2W_NRESET 16 54#define OVERO_GPIO_W2W_NRESET 16
55#define OVERO_GPIO_PENDOWN 114
54#define OVERO_GPIO_BT_NRESET 164 56#define OVERO_GPIO_BT_NRESET 164
55#define OVERO_GPIO_USBH_CPEN 168 57#define OVERO_GPIO_USBH_CPEN 168
56#define OVERO_GPIO_USBH_NRESET 183 58#define OVERO_GPIO_USBH_NRESET 183
@@ -146,7 +148,7 @@ static struct platform_device overo_smsc911x_device = {
146 .name = "smsc911x", 148 .name = "smsc911x",
147 .id = -1, 149 .id = -1,
148 .num_resources = ARRAY_SIZE(overo_smsc911x_resources), 150 .num_resources = ARRAY_SIZE(overo_smsc911x_resources),
149 .resource = &overo_smsc911x_resources, 151 .resource = overo_smsc911x_resources,
150 .dev = { 152 .dev = {
151 .platform_data = &overo_smsc911x_config, 153 .platform_data = &overo_smsc911x_config,
152 }, 154 },
@@ -360,7 +362,8 @@ static int __init overo_i2c_init(void)
360 362
361static void __init overo_init_irq(void) 363static void __init overo_init_irq(void)
362{ 364{
363 omap2_init_common_hw(mt46h32m32lf6_sdrc_params); 365 omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
366 mt46h32m32lf6_sdrc_params);
364 omap_init_irq(); 367 omap_init_irq();
365 omap_gpio_init(); 368 omap_gpio_init();
366} 369}
@@ -395,6 +398,10 @@ static void __init overo_init(void)
395 overo_ads7846_init(); 398 overo_ads7846_init();
396 overo_init_smsc911x(); 399 overo_init_smsc911x();
397 400
401 /* Ensure SDRC pins are mux'd for self-refresh */
402 omap_cfg_reg(H16_34XX_SDRC_CKE0);
403 omap_cfg_reg(H17_34XX_SDRC_CKE1);
404
398 if ((gpio_request(OVERO_GPIO_W2W_NRESET, 405 if ((gpio_request(OVERO_GPIO_W2W_NRESET,
399 "OVERO_GPIO_W2W_NRESET") == 0) && 406 "OVERO_GPIO_W2W_NRESET") == 0) &&
400 (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) { 407 (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 9a0bf6744a05..56d931a425f7 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -278,6 +278,10 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
278 .setup = rx51_twlgpio_setup, 278 .setup = rx51_twlgpio_setup,
279}; 279};
280 280
281static struct twl4030_usb_data rx51_usb_data = {
282 .usb_mode = T2_USB_MODE_ULPI,
283};
284
281static struct twl4030_platform_data rx51_twldata = { 285static struct twl4030_platform_data rx51_twldata = {
282 .irq_base = TWL4030_IRQ_BASE, 286 .irq_base = TWL4030_IRQ_BASE,
283 .irq_end = TWL4030_IRQ_END, 287 .irq_end = TWL4030_IRQ_END,
@@ -286,6 +290,7 @@ static struct twl4030_platform_data rx51_twldata = {
286 .gpio = &rx51_gpio_data, 290 .gpio = &rx51_gpio_data,
287 .keypad = &rx51_kp_data, 291 .keypad = &rx51_kp_data,
288 .madc = &rx51_madc_data, 292 .madc = &rx51_madc_data,
293 .usb = &rx51_usb_data,
289 294
290 .vaux1 = &rx51_vaux1, 295 .vaux1 = &rx51_vaux1,
291 .vaux2 = &rx51_vaux2, 296 .vaux2 = &rx51_vaux2,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 374ff63c3eb2..1c9e07fe8266 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = {
61 61
62static void __init rx51_init_irq(void) 62static void __init rx51_init_irq(void)
63{ 63{
64 omap2_init_common_hw(NULL); 64 omap2_init_common_hw(NULL, NULL);
65 omap_init_irq(); 65 omap_init_irq();
66 omap_gpio_init(); 66 omap_gpio_init();
67} 67}
@@ -75,6 +75,10 @@ static void __init rx51_init(void)
75 omap_serial_init(); 75 omap_serial_init();
76 usb_musb_init(); 76 usb_musb_init();
77 rx51_peripherals_init(); 77 rx51_peripherals_init();
78
79 /* Ensure SDRC pins are mux'd for self-refresh */
80 omap_cfg_reg(H16_34XX_SDRC_CKE0);
81 omap_cfg_reg(H17_34XX_SDRC_CKE1);
78} 82}
79 83
80static void __init rx51_map_io(void) 84static void __init rx51_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index bcc0f7632dea..427b7b8b1237 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -25,7 +25,7 @@
25 25
26static void __init omap_zoom2_init_irq(void) 26static void __init omap_zoom2_init_irq(void)
27{ 27{
28 omap2_init_common_hw(NULL); 28 omap2_init_common_hw(NULL, NULL);
29 omap_init_irq(); 29 omap_init_irq();
30 omap_gpio_init(); 30 omap_gpio_init();
31} 31}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index b0665f161c03..456e2ad5f621 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -27,6 +27,7 @@
27#include <mach/clock.h> 27#include <mach/clock.h>
28#include <mach/clockdomain.h> 28#include <mach/clockdomain.h>
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30#include <mach/prcm.h>
30#include <asm/div64.h> 31#include <asm/div64.h>
31 32
32#include <mach/sdrc.h> 33#include <mach/sdrc.h>
@@ -38,8 +39,6 @@
38#include "cm-regbits-24xx.h" 39#include "cm-regbits-24xx.h"
39#include "cm-regbits-34xx.h" 40#include "cm-regbits-34xx.h"
40 41
41#define MAX_CLOCK_ENABLE_WAIT 100000
42
43/* DPLL rate rounding: minimum DPLL multiplier, divider values */ 42/* DPLL rate rounding: minimum DPLL multiplier, divider values */
44#define DPLL_MIN_MULTIPLIER 1 43#define DPLL_MIN_MULTIPLIER 1
45#define DPLL_MIN_DIVIDER 1 44#define DPLL_MIN_DIVIDER 1
@@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
274} 273}
275 274
276/** 275/**
277 * omap2_wait_clock_ready - wait for clock to enable 276 * omap2_clk_dflt_find_companion - find companion clock to @clk
278 * @reg: physical address of clock IDLEST register 277 * @clk: struct clk * to find the companion clock of
279 * @mask: value to mask against to determine if the clock is active 278 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
280 * @name: name of the clock (for printk) 279 * @other_bit: u8 ** to return the companion clock bit shift in
280 *
281 * Note: We don't need special code here for INVERT_ENABLE for the
282 * time being since INVERT_ENABLE only applies to clocks enabled by
283 * CM_CLKEN_PLL
281 * 284 *
282 * Returns 1 if the clock enabled in time, or 0 if it failed to enable 285 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
283 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. 286 * just a matter of XORing the bits.
287 *
288 * Some clocks don't have companion clocks. For example, modules with
289 * only an interface clock (such as MAILBOXES) don't have a companion
290 * clock. Right now, this code relies on the hardware exporting a bit
291 * in the correct companion register that indicates that the
292 * nonexistent 'companion clock' is active. Future patches will
293 * associate this type of code with per-module data structures to
294 * avoid this issue, and remove the casts. No return value.
284 */ 295 */
285int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) 296void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
297 u8 *other_bit)
286{ 298{
287 int i = 0; 299 u32 r;
288 int ena = 0;
289 300
290 /* 301 /*
291 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 302 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
292 * 34xx reverses this, just to keep us on our toes 303 * it's just a matter of XORing the bits.
293 */ 304 */
294 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) 305 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
295 ena = mask;
296 else if (cpu_mask & RATE_IN_343X)
297 ena = 0;
298
299 /* Wait for lock */
300 while (((__raw_readl(reg) & mask) != ena) &&
301 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
302 udelay(1);
303 }
304
305 if (i <= MAX_CLOCK_ENABLE_WAIT)
306 pr_debug("Clock %s stable after %d loops\n", name, i);
307 else
308 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
309 name, MAX_CLOCK_ENABLE_WAIT);
310
311
312 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
313};
314 306
307 *other_reg = (__force void __iomem *)r;
308 *other_bit = clk->enable_bit;
309}
315 310
316/* 311/**
317 * Note: We don't need special code here for INVERT_ENABLE 312 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
318 * for the time being since INVERT_ENABLE only applies to clocks enabled by 313 * @clk: struct clk * to find IDLEST info for
319 * CM_CLKEN_PLL 314 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
315 * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
316 *
317 * Return the CM_IDLEST register address and bit shift corresponding
318 * to the module that "owns" this clock. This default code assumes
319 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
320 * the IDLEST register address ID corresponds to the CM_*CLKEN
321 * register address ID (e.g., that CM_FCLKEN2 corresponds to
322 * CM_IDLEST2). This is not true for all modules. No return value.
320 */ 323 */
321static void omap2_clk_wait_ready(struct clk *clk) 324void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
325 u8 *idlest_bit)
322{ 326{
323 void __iomem *reg, *other_reg, *st_reg; 327 u32 r;
324 u32 bit;
325 328
326 /* 329 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
327 * REVISIT: This code is pretty ugly. It would be nice to generalize 330 *idlest_reg = (__force void __iomem *)r;
328 * it and pull it into struct clk itself somehow. 331 *idlest_bit = clk->enable_bit;
329 */ 332}
330 reg = clk->enable_reg;
331 333
332 /* 334/**
333 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 335 * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
334 * it's just a matter of XORing the bits. 336 * @clk: struct clk * belonging to the module
335 */ 337 *
336 other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 338 * If the necessary clocks for the OMAP hardware IP block that
339 * corresponds to clock @clk are enabled, then wait for the module to
340 * indicate readiness (i.e., to leave IDLE). This code does not
341 * belong in the clock code and will be moved in the medium term to
342 * module-dependent code. No return value.
343 */
344static void omap2_module_wait_ready(struct clk *clk)
345{
346 void __iomem *companion_reg, *idlest_reg;
347 u8 other_bit, idlest_bit;
348
349 /* Not all modules have multiple clocks that their IDLEST depends on */
350 if (clk->ops->find_companion) {
351 clk->ops->find_companion(clk, &companion_reg, &other_bit);
352 if (!(__raw_readl(companion_reg) & (1 << other_bit)))
353 return;
354 }
337 355
338 /* Check if both functional and interface clocks 356 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
339 * are running. */
340 bit = 1 << clk->enable_bit;
341 if (!(__raw_readl(other_reg) & bit))
342 return;
343 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
344 357
345 omap2_wait_clock_ready(st_reg, bit, clk->name); 358 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
346} 359}
347 360
348static int omap2_dflt_clk_enable(struct clk *clk) 361int omap2_dflt_clk_enable(struct clk *clk)
349{ 362{
350 u32 v; 363 u32 v;
351 364
352 if (unlikely(clk->enable_reg == NULL)) { 365 if (unlikely(clk->enable_reg == NULL)) {
353 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 366 pr_err("clock.c: Enable for %s without enable code\n",
354 clk->name); 367 clk->name);
355 return 0; /* REVISIT: -EINVAL */ 368 return 0; /* REVISIT: -EINVAL */
356 } 369 }
@@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk)
363 __raw_writel(v, clk->enable_reg); 376 __raw_writel(v, clk->enable_reg);
364 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 377 v = __raw_readl(clk->enable_reg); /* OCP barrier */
365 378
366 return 0; 379 if (clk->ops->find_idlest)
367} 380 omap2_module_wait_ready(clk);
368 381
369static int omap2_dflt_clk_enable_wait(struct clk *clk) 382 return 0;
370{
371 int ret;
372
373 if (!clk->enable_reg) {
374 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
375 clk->name);
376 return 0; /* REVISIT: -EINVAL */
377 }
378
379 ret = omap2_dflt_clk_enable(clk);
380 if (ret == 0)
381 omap2_clk_wait_ready(clk);
382 return ret;
383} 383}
384 384
385static void omap2_dflt_clk_disable(struct clk *clk) 385void omap2_dflt_clk_disable(struct clk *clk)
386{ 386{
387 u32 v; 387 u32 v;
388 388
@@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk)
406} 406}
407 407
408const struct clkops clkops_omap2_dflt_wait = { 408const struct clkops clkops_omap2_dflt_wait = {
409 .enable = omap2_dflt_clk_enable_wait, 409 .enable = omap2_dflt_clk_enable,
410 .disable = omap2_dflt_clk_disable, 410 .disable = omap2_dflt_clk_disable,
411 .find_companion = omap2_clk_dflt_find_companion,
412 .find_idlest = omap2_clk_dflt_find_idlest,
411}; 413};
412 414
413const struct clkops clkops_omap2_dflt = { 415const struct clkops clkops_omap2_dflt = {
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2679ddfa6424..9ae7540f8af2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,12 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
65u32 omap2_get_dpll_rate(struct clk *clk); 65u32 omap2_get_dpll_rate(struct clk *clk);
66int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); 66int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
67void omap2_clk_prepare_for_reboot(void); 67void omap2_clk_prepare_for_reboot(void);
68int omap2_dflt_clk_enable(struct clk *clk);
69void omap2_dflt_clk_disable(struct clk *clk);
70void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
71 u8 *other_bit);
72void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
73 u8 *idlest_bit);
68 74
69extern const struct clkops clkops_omap2_dflt_wait; 75extern const struct clkops clkops_omap2_dflt_wait;
70extern const struct clkops clkops_omap2_dflt; 76extern const struct clkops clkops_omap2_dflt;
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 44de0271fc2f..bc5d3ac66611 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -30,6 +30,7 @@
30 30
31#include <mach/clock.h> 31#include <mach/clock.h>
32#include <mach/sram.h> 32#include <mach/sram.h>
33#include <mach/prcm.h>
33#include <asm/div64.h> 34#include <asm/div64.h>
34#include <asm/clkdev.h> 35#include <asm/clkdev.h>
35 36
@@ -43,6 +44,18 @@
43static const struct clkops clkops_oscck; 44static const struct clkops clkops_oscck;
44static const struct clkops clkops_fixed; 45static const struct clkops clkops_fixed;
45 46
47static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
48 void __iomem **idlest_reg,
49 u8 *idlest_bit);
50
51/* 2430 I2CHS has non-standard IDLEST register */
52static const struct clkops clkops_omap2430_i2chs_wait = {
53 .enable = omap2_dflt_clk_enable,
54 .disable = omap2_dflt_clk_disable,
55 .find_idlest = omap2430_clk_i2chs_find_idlest,
56 .find_companion = omap2_clk_dflt_find_companion,
57};
58
46#include "clock24xx.h" 59#include "clock24xx.h"
47 60
48struct omap_clk { 61struct omap_clk {
@@ -240,6 +253,26 @@ static void __iomem *prcm_clksrc_ctrl;
240 *-------------------------------------------------------------------------*/ 253 *-------------------------------------------------------------------------*/
241 254
242/** 255/**
256 * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
257 * @clk: struct clk * being enabled
258 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
259 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
260 *
261 * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
262 * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
263 * passes back the correct CM_IDLEST register address for I2CHS
264 * modules. No return value.
265 */
266static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
267 void __iomem **idlest_reg,
268 u8 *idlest_bit)
269{
270 *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
271 *idlest_bit = clk->enable_bit;
272}
273
274
275/**
243 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate 276 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
244 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") 277 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
245 * 278 *
@@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk)
325 else if (clk == &apll54_ck) 358 else if (clk == &apll54_ck)
326 cval = OMAP24XX_ST_54M_APLL; 359 cval = OMAP24XX_ST_54M_APLL;
327 360
328 omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, 361 omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
329 clk->name); 362 clk->name);
330 363
331 /* 364 /*
332 * REVISIT: Should we return an error code if omap2_wait_clock_ready() 365 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 458f00cdcbea..d19cf7a7d8db 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = {
2337 2337
2338static struct clk i2chs2_fck = { 2338static struct clk i2chs2_fck = {
2339 .name = "i2c_fck", 2339 .name = "i2c_fck",
2340 .ops = &clkops_omap2_dflt_wait, 2340 .ops = &clkops_omap2430_i2chs_wait,
2341 .id = 2, 2341 .id = 2,
2342 .parent = &func_96m_ck, 2342 .parent = &func_96m_ck,
2343 .clkdm_name = "core_l4_clkdm", 2343 .clkdm_name = "core_l4_clkdm",
@@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = {
2370 2370
2371static struct clk i2chs1_fck = { 2371static struct clk i2chs1_fck = {
2372 .name = "i2c_fck", 2372 .name = "i2c_fck",
2373 .ops = &clkops_omap2_dflt_wait, 2373 .ops = &clkops_omap2430_i2chs_wait,
2374 .id = 1, 2374 .id = 1,
2375 .parent = &func_96m_ck, 2375 .parent = &func_96m_ck,
2376 .clkdm_name = "core_l4_clkdm", 2376 .clkdm_name = "core_l4_clkdm",
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 045da923e75b..cd7819cc0c9e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
2 * OMAP3-specific clock framework functions 2 * OMAP3-specific clock framework functions
3 * 3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation 5 * Copyright (C) 2007-2009 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander 8 * Testing and integration fixes by Jouni Högander
@@ -41,6 +41,37 @@
41 41
42static const struct clkops clkops_noncore_dpll_ops; 42static const struct clkops clkops_noncore_dpll_ops;
43 43
44static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
45 void __iomem **idlest_reg,
46 u8 *idlest_bit);
47static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
48 void __iomem **idlest_reg,
49 u8 *idlest_bit);
50static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
51 void __iomem **idlest_reg,
52 u8 *idlest_bit);
53
54static const struct clkops clkops_omap3430es2_ssi_wait = {
55 .enable = omap2_dflt_clk_enable,
56 .disable = omap2_dflt_clk_disable,
57 .find_idlest = omap3430es2_clk_ssi_find_idlest,
58 .find_companion = omap2_clk_dflt_find_companion,
59};
60
61static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
62 .enable = omap2_dflt_clk_enable,
63 .disable = omap2_dflt_clk_disable,
64 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
65 .find_companion = omap2_clk_dflt_find_companion,
66};
67
68static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
69 .enable = omap2_dflt_clk_enable,
70 .disable = omap2_dflt_clk_disable,
71 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
72 .find_companion = omap2_clk_dflt_find_companion,
73};
74
44#include "clock34xx.h" 75#include "clock34xx.h"
45 76
46struct omap_clk { 77struct omap_clk {
@@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = {
157 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), 188 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
158 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), 189 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
159 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), 190 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
160 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), 191 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
161 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), 192 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
193 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
194 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
162 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), 195 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
163 CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X), 196 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
197 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
164 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), 198 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
165 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), 199 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
166 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), 200 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
@@ -193,18 +227,21 @@ static struct omap_clk omap34xx_clks[] = {
193 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), 227 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
194 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), 228 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
195 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), 229 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
196 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X), 230 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
231 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
197 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), 232 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
198 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), 233 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
199 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), 234 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
200 CLK("omap_rng", "ick", &rng_ick, CK_343X), 235 CLK("omap_rng", "ick", &rng_ick, CK_343X),
201 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), 236 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
202 CLK(NULL, "des1_ick", &des1_ick, CK_343X), 237 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
203 CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X), 238 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
239 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
204 CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X), 240 CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
205 CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X), 241 CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
206 CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X), 242 CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
207 CLK("omapfb", "ick", &dss_ick, CK_343X), 243 CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
244 CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
208 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), 245 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
209 CLK(NULL, "cam_ick", &cam_ick, CK_343X), 246 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
210 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), 247 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
@@ -301,6 +338,73 @@ static struct omap_clk omap34xx_clks[] = {
301#define SDRC_MPURATE_LOOPS 96 338#define SDRC_MPURATE_LOOPS 96
302 339
303/** 340/**
341 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
342 * @clk: struct clk * being enabled
343 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
344 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
345 *
346 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
347 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
348 * @idlest_reg and @idlest_bit. No return value.
349 */
350static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
351 void __iomem **idlest_reg,
352 u8 *idlest_bit)
353{
354 u32 r;
355
356 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
357 *idlest_reg = (__force void __iomem *)r;
358 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
359}
360
361/**
362 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
363 * @clk: struct clk * being enabled
364 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
365 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
366 *
367 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
368 * target IDLEST bits. For our purposes, we are concerned with the
369 * target IDLEST bits, which exist at a different bit position than
370 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
371 * default find_idlest code assumes that they are at the same
372 * position.) No return value.
373 */
374static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
375 void __iomem **idlest_reg,
376 u8 *idlest_bit)
377{
378 u32 r;
379
380 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
381 *idlest_reg = (__force void __iomem *)r;
382 /* USBHOST_IDLE has same shift */
383 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
384}
385
386/**
387 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
388 * @clk: struct clk * being enabled
389 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
390 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
391 *
392 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
393 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
394 * @idlest_reg and @idlest_bit. No return value.
395 */
396static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
397 void __iomem **idlest_reg,
398 u8 *idlest_bit)
399{
400 u32 r;
401
402 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
403 *idlest_reg = (__force void __iomem *)r;
404 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
405}
406
407/**
304 * omap3_dpll_recalc - recalculate DPLL rate 408 * omap3_dpll_recalc - recalculate DPLL rate
305 * @clk: DPLL struct clk 409 * @clk: DPLL struct clk
306 * 410 *
@@ -725,7 +829,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
725 u32 unlock_dll = 0; 829 u32 unlock_dll = 0;
726 u32 c; 830 u32 c;
727 unsigned long validrate, sdrcrate, mpurate; 831 unsigned long validrate, sdrcrate, mpurate;
728 struct omap_sdrc_params *sp; 832 struct omap_sdrc_params *sdrc_cs0;
833 struct omap_sdrc_params *sdrc_cs1;
834 int ret;
729 835
730 if (!clk || !rate) 836 if (!clk || !rate)
731 return -EINVAL; 837 return -EINVAL;
@@ -743,8 +849,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
743 else 849 else
744 sdrcrate >>= ((clk->rate / rate) >> 1); 850 sdrcrate >>= ((clk->rate / rate) >> 1);
745 851
746 sp = omap2_sdrc_get_params(sdrcrate); 852 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
747 if (!sp) 853 if (ret)
748 return -EINVAL; 854 return -EINVAL;
749 855
750 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { 856 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
@@ -765,12 +871,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
765 871
766 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, 872 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
767 validrate); 873 validrate);
768 pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", 874 pr_debug("clock: SDRC CS0 timing params used:"
769 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); 875 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
770 876 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
771 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, 877 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
772 sp->actim_ctrlb, new_div, unlock_dll, c, 878 if (sdrc_cs1)
773 sp->mr, rate > clk->rate); 879 pr_debug("clock: SDRC CS1 timing params used: "
880 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
881 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
882 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
883
884 if (sdrc_cs1)
885 omap3_configure_core_dpll(
886 new_div, unlock_dll, c, rate > clk->rate,
887 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
888 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
889 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
890 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
891 else
892 omap3_configure_core_dpll(
893 new_div, unlock_dll, c, rate > clk->rate,
894 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
895 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
896 0, 0, 0, 0);
774 897
775 return 0; 898 return 0;
776} 899}
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index e433aec4efdd..57cc2725b923 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1568,7 +1568,7 @@ static const struct clksel ssi_ssr_clksel[] = {
1568 { .parent = NULL } 1568 { .parent = NULL }
1569}; 1569};
1570 1570
1571static struct clk ssi_ssr_fck = { 1571static struct clk ssi_ssr_fck_3430es1 = {
1572 .name = "ssi_ssr_fck", 1572 .name = "ssi_ssr_fck",
1573 .ops = &clkops_omap2_dflt, 1573 .ops = &clkops_omap2_dflt,
1574 .init = &omap2_init_clksel_parent, 1574 .init = &omap2_init_clksel_parent,
@@ -1581,10 +1581,31 @@ static struct clk ssi_ssr_fck = {
1581 .recalc = &omap2_clksel_recalc, 1581 .recalc = &omap2_clksel_recalc,
1582}; 1582};
1583 1583
1584static struct clk ssi_sst_fck = { 1584static struct clk ssi_ssr_fck_3430es2 = {
1585 .name = "ssi_ssr_fck",
1586 .ops = &clkops_omap3430es2_ssi_wait,
1587 .init = &omap2_init_clksel_parent,
1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1589 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1590 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1591 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1592 .clksel = ssi_ssr_clksel,
1593 .clkdm_name = "core_l4_clkdm",
1594 .recalc = &omap2_clksel_recalc,
1595};
1596
1597static struct clk ssi_sst_fck_3430es1 = {
1585 .name = "ssi_sst_fck", 1598 .name = "ssi_sst_fck",
1586 .ops = &clkops_null, 1599 .ops = &clkops_null,
1587 .parent = &ssi_ssr_fck, 1600 .parent = &ssi_ssr_fck_3430es1,
1601 .fixed_div = 2,
1602 .recalc = &omap2_fixed_divisor_recalc,
1603};
1604
1605static struct clk ssi_sst_fck_3430es2 = {
1606 .name = "ssi_sst_fck",
1607 .ops = &clkops_null,
1608 .parent = &ssi_ssr_fck_3430es2,
1588 .fixed_div = 2, 1609 .fixed_div = 2,
1589 .recalc = &omap2_fixed_divisor_recalc, 1610 .recalc = &omap2_fixed_divisor_recalc,
1590}; 1611};
@@ -1606,9 +1627,19 @@ static struct clk core_l3_ick = {
1606 .recalc = &followparent_recalc, 1627 .recalc = &followparent_recalc,
1607}; 1628};
1608 1629
1609static struct clk hsotgusb_ick = { 1630static struct clk hsotgusb_ick_3430es1 = {
1610 .name = "hsotgusb_ick", 1631 .name = "hsotgusb_ick",
1611 .ops = &clkops_omap2_dflt_wait, 1632 .ops = &clkops_omap2_dflt,
1633 .parent = &core_l3_ick,
1634 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1635 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1636 .clkdm_name = "core_l3_clkdm",
1637 .recalc = &followparent_recalc,
1638};
1639
1640static struct clk hsotgusb_ick_3430es2 = {
1641 .name = "hsotgusb_ick",
1642 .ops = &clkops_omap3430es2_hsotgusb_wait,
1612 .parent = &core_l3_ick, 1643 .parent = &core_l3_ick,
1613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1644 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1614 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1645 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1947,7 +1978,7 @@ static struct clk ssi_l4_ick = {
1947 .recalc = &followparent_recalc, 1978 .recalc = &followparent_recalc,
1948}; 1979};
1949 1980
1950static struct clk ssi_ick = { 1981static struct clk ssi_ick_3430es1 = {
1951 .name = "ssi_ick", 1982 .name = "ssi_ick",
1952 .ops = &clkops_omap2_dflt, 1983 .ops = &clkops_omap2_dflt,
1953 .parent = &ssi_l4_ick, 1984 .parent = &ssi_l4_ick,
@@ -1957,6 +1988,16 @@ static struct clk ssi_ick = {
1957 .recalc = &followparent_recalc, 1988 .recalc = &followparent_recalc,
1958}; 1989};
1959 1990
1991static struct clk ssi_ick_3430es2 = {
1992 .name = "ssi_ick",
1993 .ops = &clkops_omap3430es2_ssi_wait,
1994 .parent = &ssi_l4_ick,
1995 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1996 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1997 .clkdm_name = "core_l4_clkdm",
1998 .recalc = &followparent_recalc,
1999};
2000
1960/* REVISIT: Technically the TRM claims that this is CORE_CLK based, 2001/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1961 * but l4_ick makes more sense to me */ 2002 * but l4_ick makes more sense to me */
1962 2003
@@ -2024,7 +2065,7 @@ static struct clk des1_ick = {
2024}; 2065};
2025 2066
2026/* DSS */ 2067/* DSS */
2027static struct clk dss1_alwon_fck = { 2068static struct clk dss1_alwon_fck_3430es1 = {
2028 .name = "dss1_alwon_fck", 2069 .name = "dss1_alwon_fck",
2029 .ops = &clkops_omap2_dflt, 2070 .ops = &clkops_omap2_dflt,
2030 .parent = &dpll4_m4x2_ck, 2071 .parent = &dpll4_m4x2_ck,
@@ -2034,6 +2075,16 @@ static struct clk dss1_alwon_fck = {
2034 .recalc = &followparent_recalc, 2075 .recalc = &followparent_recalc,
2035}; 2076};
2036 2077
2078static struct clk dss1_alwon_fck_3430es2 = {
2079 .name = "dss1_alwon_fck",
2080 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2081 .parent = &dpll4_m4x2_ck,
2082 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2083 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2084 .clkdm_name = "dss_clkdm",
2085 .recalc = &followparent_recalc,
2086};
2087
2037static struct clk dss_tv_fck = { 2088static struct clk dss_tv_fck = {
2038 .name = "dss_tv_fck", 2089 .name = "dss_tv_fck",
2039 .ops = &clkops_omap2_dflt, 2090 .ops = &clkops_omap2_dflt,
@@ -2067,7 +2118,7 @@ static struct clk dss2_alwon_fck = {
2067 .recalc = &followparent_recalc, 2118 .recalc = &followparent_recalc,
2068}; 2119};
2069 2120
2070static struct clk dss_ick = { 2121static struct clk dss_ick_3430es1 = {
2071 /* Handles both L3 and L4 clocks */ 2122 /* Handles both L3 and L4 clocks */
2072 .name = "dss_ick", 2123 .name = "dss_ick",
2073 .ops = &clkops_omap2_dflt, 2124 .ops = &clkops_omap2_dflt,
@@ -2079,6 +2130,18 @@ static struct clk dss_ick = {
2079 .recalc = &followparent_recalc, 2130 .recalc = &followparent_recalc,
2080}; 2131};
2081 2132
2133static struct clk dss_ick_3430es2 = {
2134 /* Handles both L3 and L4 clocks */
2135 .name = "dss_ick",
2136 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2137 .parent = &l4_ick,
2138 .init = &omap2_init_clk_clkdm,
2139 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2140 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2141 .clkdm_name = "dss_clkdm",
2142 .recalc = &followparent_recalc,
2143};
2144
2082/* CAM */ 2145/* CAM */
2083 2146
2084static struct clk cam_mclk = { 2147static struct clk cam_mclk = {
@@ -2118,7 +2181,7 @@ static struct clk csi2_96m_fck = {
2118 2181
2119static struct clk usbhost_120m_fck = { 2182static struct clk usbhost_120m_fck = {
2120 .name = "usbhost_120m_fck", 2183 .name = "usbhost_120m_fck",
2121 .ops = &clkops_omap2_dflt_wait, 2184 .ops = &clkops_omap2_dflt,
2122 .parent = &dpll5_m2_ck, 2185 .parent = &dpll5_m2_ck,
2123 .init = &omap2_init_clk_clkdm, 2186 .init = &omap2_init_clk_clkdm,
2124 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2187 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2129,7 +2192,7 @@ static struct clk usbhost_120m_fck = {
2129 2192
2130static struct clk usbhost_48m_fck = { 2193static struct clk usbhost_48m_fck = {
2131 .name = "usbhost_48m_fck", 2194 .name = "usbhost_48m_fck",
2132 .ops = &clkops_omap2_dflt_wait, 2195 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2133 .parent = &omap_48m_fck, 2196 .parent = &omap_48m_fck,
2134 .init = &omap2_init_clk_clkdm, 2197 .init = &omap2_init_clk_clkdm,
2135 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2198 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2141,7 +2204,7 @@ static struct clk usbhost_48m_fck = {
2141static struct clk usbhost_ick = { 2204static struct clk usbhost_ick = {
2142 /* Handles both L3 and L4 clocks */ 2205 /* Handles both L3 and L4 clocks */
2143 .name = "usbhost_ick", 2206 .name = "usbhost_ick",
2144 .ops = &clkops_omap2_dflt_wait, 2207 .ops = &clkops_omap3430es2_dss_usbhost_wait,
2145 .parent = &l4_ick, 2208 .parent = &l4_ick,
2146 .init = &omap2_init_clk_clkdm, 2209 .init = &omap2_init_clk_clkdm,
2147 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2210 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 1d3c93bf86d3..f3c91a1ca391 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -29,9 +29,9 @@
29 * These registers appear once per CM module. 29 * These registers appear once per CM module.
30 */ 30 */
31 31
32#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) 32#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
33#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) 33#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
34#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) 34#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
35 35
36#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 36#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
37#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 37#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3a86b0f66031..e9b9bcb19b4e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void)
276 return v; 276 return v;
277} 277}
278 278
279void __init omap2_init_common_hw(struct omap_sdrc_params *sp) 279void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
280 struct omap_sdrc_params *sdrc_cs1)
280{ 281{
281 omap2_mux_init(); 282 omap2_mux_init();
282#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ 283#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
283 pwrdm_init(powerdomains_omap); 284 pwrdm_init(powerdomains_omap);
284 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); 285 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
285 omap2_clk_init(); 286 omap2_clk_init();
286 omap2_sdrc_init(sp); 287 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
287 _omap2_init_reprogram_sdrc(); 288 _omap2_init_reprogram_sdrc();
288#endif 289#endif
289 gpmc_init(); 290 gpmc_init();
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 1541fd4c8d0f..3c04c2f1b23f 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -119,6 +119,7 @@ static int twl_mmc_late_init(struct device *dev)
119 if (i != 0) 119 if (i != 0)
120 break; 120 break;
121 ret = PTR_ERR(reg); 121 ret = PTR_ERR(reg);
122 hsmmc[i].vcc = NULL;
122 goto err; 123 goto err;
123 } 124 }
124 hsmmc[i].vcc = reg; 125 hsmmc[i].vcc = reg;
@@ -165,8 +166,13 @@ done:
165static void twl_mmc_cleanup(struct device *dev) 166static void twl_mmc_cleanup(struct device *dev)
166{ 167{
167 struct omap_mmc_platform_data *mmc = dev->platform_data; 168 struct omap_mmc_platform_data *mmc = dev->platform_data;
169 int i;
168 170
169 gpio_free(mmc->slots[0].switch_pin); 171 gpio_free(mmc->slots[0].switch_pin);
172 for(i = 0; i < ARRAY_SIZE(hsmmc); i++) {
173 regulator_put(hsmmc[i].vcc);
174 regulator_put(hsmmc[i].vcc_aux);
175 }
170} 176}
171 177
172#ifdef CONFIG_PM 178#ifdef CONFIG_PM
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc883a7..43d6b92b65f2 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
486 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) 486 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
487MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, 487MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
488 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) 488 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
489
490/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
491MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
492 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
493MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
494 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
489}; 495};
490 496
491#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) 497#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f7b3baf76678..21201cd4117b 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,9 +11,6 @@
11#ifndef __ARCH_ARM_MACH_OMAP2_PM_H 11#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
12#define __ARCH_ARM_MACH_OMAP2_PM_H 12#define __ARCH_ARM_MACH_OMAP2_PM_H
13 13
14extern int omap2_pm_init(void);
15extern int omap3_pm_init(void);
16
17#ifdef CONFIG_PM_DEBUG 14#ifdef CONFIG_PM_DEBUG
18extern void omap2_pm_dump(int mode, int resume, unsigned int us); 15extern void omap2_pm_dump(int mode, int resume, unsigned int us);
19extern int omap2_pm_debug; 16extern int omap2_pm_debug;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index db1025562fb0..528dbdc26e23 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void)
470 WKUP_MOD, PM_WKEN); 470 WKUP_MOD, PM_WKEN);
471} 471}
472 472
473int __init omap2_pm_init(void) 473static int __init omap2_pm_init(void)
474{ 474{
475 u32 l; 475 u32 l;
476 476
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 841d4c5ed8be..488d595d8e4b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -39,7 +39,9 @@
39struct power_state { 39struct power_state {
40 struct powerdomain *pwrdm; 40 struct powerdomain *pwrdm;
41 u32 next_state; 41 u32 next_state;
42#ifdef CONFIG_SUSPEND
42 u32 saved_state; 43 u32 saved_state;
44#endif
43 struct list_head node; 45 struct list_head node;
44}; 46};
45 47
@@ -293,6 +295,9 @@ out:
293 local_irq_enable(); 295 local_irq_enable();
294} 296}
295 297
298#ifdef CONFIG_SUSPEND
299static suspend_state_t suspend_state;
300
296static int omap3_pm_prepare(void) 301static int omap3_pm_prepare(void)
297{ 302{
298 disable_hlt(); 303 disable_hlt();
@@ -321,7 +326,6 @@ static int omap3_pm_suspend(void)
321restore: 326restore:
322 /* Restore next_pwrsts */ 327 /* Restore next_pwrsts */
323 list_for_each_entry(pwrst, &pwrst_list, node) { 328 list_for_each_entry(pwrst, &pwrst_list, node) {
324 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
325 state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 329 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
326 if (state > pwrst->next_state) { 330 if (state > pwrst->next_state) {
327 printk(KERN_INFO "Powerdomain (%s) didn't enter " 331 printk(KERN_INFO "Powerdomain (%s) didn't enter "
@@ -329,6 +333,7 @@ restore:
329 pwrst->pwrdm->name, pwrst->next_state); 333 pwrst->pwrdm->name, pwrst->next_state);
330 ret = -1; 334 ret = -1;
331 } 335 }
336 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
332 } 337 }
333 if (ret) 338 if (ret)
334 printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 339 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -339,11 +344,11 @@ restore:
339 return ret; 344 return ret;
340} 345}
341 346
342static int omap3_pm_enter(suspend_state_t state) 347static int omap3_pm_enter(suspend_state_t unused)
343{ 348{
344 int ret = 0; 349 int ret = 0;
345 350
346 switch (state) { 351 switch (suspend_state) {
347 case PM_SUSPEND_STANDBY: 352 case PM_SUSPEND_STANDBY:
348 case PM_SUSPEND_MEM: 353 case PM_SUSPEND_MEM:
349 ret = omap3_pm_suspend(); 354 ret = omap3_pm_suspend();
@@ -360,12 +365,30 @@ static void omap3_pm_finish(void)
360 enable_hlt(); 365 enable_hlt();
361} 366}
362 367
368/* Hooks to enable / disable UART interrupts during suspend */
369static int omap3_pm_begin(suspend_state_t state)
370{
371 suspend_state = state;
372 omap_uart_enable_irqs(0);
373 return 0;
374}
375
376static void omap3_pm_end(void)
377{
378 suspend_state = PM_SUSPEND_ON;
379 omap_uart_enable_irqs(1);
380 return;
381}
382
363static struct platform_suspend_ops omap_pm_ops = { 383static struct platform_suspend_ops omap_pm_ops = {
384 .begin = omap3_pm_begin,
385 .end = omap3_pm_end,
364 .prepare = omap3_pm_prepare, 386 .prepare = omap3_pm_prepare,
365 .enter = omap3_pm_enter, 387 .enter = omap3_pm_enter,
366 .finish = omap3_pm_finish, 388 .finish = omap3_pm_finish,
367 .valid = suspend_valid_only_mem, 389 .valid = suspend_valid_only_mem,
368}; 390};
391#endif /* CONFIG_SUSPEND */
369 392
370 393
371/** 394/**
@@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void)
613 /* Clear any pending PRCM interrupts */ 636 /* Clear any pending PRCM interrupts */
614 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 637 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
615 638
639 /* Don't attach IVA interrupts */
640 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
641 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
642 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
643 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
644
645 /* Clear any pending 'reset' flags */
646 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
647 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
648 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
649 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
650 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
651 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
652 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
653
654 /* Clear any pending PRCM interrupts */
655 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
656
616 omap3_iva_idle(); 657 omap3_iva_idle();
617 omap3_d2d_idle(); 658 omap3_d2d_idle();
618} 659}
@@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
652 return 0; 693 return 0;
653} 694}
654 695
655int __init omap3_pm_init(void) 696static int __init omap3_pm_init(void)
656{ 697{
657 struct power_state *pwrst, *tmp; 698 struct power_state *pwrst, *tmp;
658 int ret; 699 int ret;
@@ -692,7 +733,9 @@ int __init omap3_pm_init(void)
692 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 733 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
693 omap34xx_cpu_suspend_sz); 734 omap34xx_cpu_suspend_sz);
694 735
736#ifdef CONFIG_SUSPEND
695 suspend_set_ops(&omap_pm_ops); 737 suspend_set_ops(&omap_pm_ops);
738#endif /* CONFIG_SUSPEND */
696 739
697 pm_idle = omap3_pm_idle; 740 pm_idle = omap3_pm_idle;
698 741
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index f945156d5585..ced555a4cd1a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,6 +17,7 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/delay.h>
20 21
21#include <mach/common.h> 22#include <mach/common.h>
22#include <mach/prcm.h> 23#include <mach/prcm.h>
@@ -28,6 +29,8 @@
28static void __iomem *prm_base; 29static void __iomem *prm_base;
29static void __iomem *cm_base; 30static void __iomem *cm_base;
30 31
32#define MAX_MODULE_ENABLE_WAIT 100000
33
31u32 omap_prcm_get_reset_sources(void) 34u32 omap_prcm_get_reset_sources(void)
32{ 35{
33 /* XXX This presumably needs modification for 34XX */ 36 /* XXX This presumably needs modification for 34XX */
@@ -120,6 +123,46 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
120} 123}
121EXPORT_SYMBOL(cm_rmw_mod_reg_bits); 124EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
122 125
126/**
127 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
128 * @reg: physical address of module IDLEST register
129 * @mask: value to mask against to determine if the module is active
130 * @name: name of the clock (for printk)
131 *
132 * Returns 1 if the module indicated readiness in time, or 0 if it
133 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
134 */
135int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
136{
137 int i = 0;
138 int ena = 0;
139
140 /*
141 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
142 * 34xx reverses this, just to keep us on our toes
143 */
144 if (cpu_is_omap24xx())
145 ena = mask;
146 else if (cpu_is_omap34xx())
147 ena = 0;
148 else
149 BUG();
150
151 /* Wait for lock */
152 while (((__raw_readl(reg) & mask) != ena) &&
153 (i++ < MAX_MODULE_ENABLE_WAIT))
154 udelay(1);
155
156 if (i < MAX_MODULE_ENABLE_WAIT)
157 pr_debug("cm: Module associated with clock %s ready after %d "
158 "loops\n", name, i);
159 else
160 pr_err("cm: Module associated with clock %s didn't enable in "
161 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
162
163 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
164};
165
123void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) 166void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
124{ 167{
125 prm_base = omap2_globals->prm; 168 prm_base = omap2_globals->prm;
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 2045441e8385..9e3bd4fa7810 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -32,7 +32,7 @@
32#include <mach/sdrc.h> 32#include <mach/sdrc.h>
33#include "sdrc.h" 33#include "sdrc.h"
34 34
35static struct omap_sdrc_params *sdrc_init_params; 35static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
36 36
37void __iomem *omap2_sdrc_base; 37void __iomem *omap2_sdrc_base;
38void __iomem *omap2_sms_base; 38void __iomem *omap2_sms_base;
@@ -45,33 +45,49 @@ void __iomem *omap2_sms_base;
45/** 45/**
46 * omap2_sdrc_get_params - return SDRC register values for a given clock rate 46 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
47 * @r: SDRC clock rate (in Hz) 47 * @r: SDRC clock rate (in Hz)
48 * @sdrc_cs0: chip select 0 ram timings **
49 * @sdrc_cs1: chip select 1 ram timings **
48 * 50 *
49 * Return pre-calculated values for the SDRC_ACTIM_CTRLA, 51 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
50 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given 52 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
51 * SDRC clock rate 'r'. These parameters control various timing 53 * structs,for a given SDRC clock rate 'r'.
52 * delays in the SDRAM controller that are expressed in terms of the 54 * These parameters control various timing delays in the SDRAM controller
53 * number of SDRC clock cycles to wait; hence the clock rate 55 * that are expressed in terms of the number of SDRC clock cycles to
54 * dependency. Note that sdrc_init_params must be sorted rate 56 * wait; hence the clock rate dependency.
55 * descending. Also assumes that both chip-selects use the same 57 *
56 * timing parameters. Returns a struct omap_sdrc_params * upon 58 * Supports 2 different timing parameters for both chip selects.
57 * success, or NULL upon failure. 59 *
60 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
61 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
62 * as sdrc_init_params_cs_0.
63 *
64 * Fills in the struct omap_sdrc_params * for each chip select.
65 * Returns 0 upon success or -1 upon failure.
58 */ 66 */
59struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r) 67int omap2_sdrc_get_params(unsigned long r,
68 struct omap_sdrc_params **sdrc_cs0,
69 struct omap_sdrc_params **sdrc_cs1)
60{ 70{
61 struct omap_sdrc_params *sp; 71 struct omap_sdrc_params *sp0, *sp1;
62 72
63 if (!sdrc_init_params) 73 if (!sdrc_init_params_cs0)
64 return NULL; 74 return -1;
65 75
66 sp = sdrc_init_params; 76 sp0 = sdrc_init_params_cs0;
77 sp1 = sdrc_init_params_cs1;
67 78
68 while (sp->rate && sp->rate != r) 79 while (sp0->rate && sp0->rate != r) {
69 sp++; 80 sp0++;
81 if (sdrc_init_params_cs1)
82 sp1++;
83 }
70 84
71 if (!sp->rate) 85 if (!sp0->rate)
72 return NULL; 86 return -1;
73 87
74 return sp; 88 *sdrc_cs0 = sp0;
89 *sdrc_cs1 = sp1;
90 return 0;
75} 91}
76 92
77 93
@@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
83 99
84/** 100/**
85 * omap2_sdrc_init - initialize SMS, SDRC devices on boot 101 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
86 * @sp: pointer to a null-terminated list of struct omap_sdrc_params 102 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
103 * Support for 2 chip selects timings
87 * 104 *
88 * Turn on smart idle modes for SDRAM scheduler and controller. 105 * Turn on smart idle modes for SDRAM scheduler and controller.
89 * Program a known-good configuration for the SDRC to deal with buggy 106 * Program a known-good configuration for the SDRC to deal with buggy
90 * bootloaders. 107 * bootloaders.
91 */ 108 */
92void __init omap2_sdrc_init(struct omap_sdrc_params *sp) 109void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
110 struct omap_sdrc_params *sdrc_cs1)
93{ 111{
94 u32 l; 112 u32 l;
95 113
@@ -103,11 +121,15 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
103 l |= (0x2 << 3); 121 l |= (0x2 << 3);
104 sdrc_write_reg(l, SDRC_SYSCONFIG); 122 sdrc_write_reg(l, SDRC_SYSCONFIG);
105 123
106 sdrc_init_params = sp; 124 sdrc_init_params_cs0 = sdrc_cs0;
125 sdrc_init_params_cs1 = sdrc_cs1;
107 126
108 /* XXX Enable SRFRONIDLEREQ here also? */ 127 /* XXX Enable SRFRONIDLEREQ here also? */
128 /*
129 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
130 * can cause random memory corruption
131 */
109 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | 132 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
110 (1 << SDRC_POWER_PWDENA_SHIFT) |
111 (1 << SDRC_POWER_PAGEPOLICY_SHIFT); 133 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
112 sdrc_write_reg(l, SDRC_POWER); 134 sdrc_write_reg(l, SDRC_POWER);
113} 135}
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b094c15bfe47..a7421a50410b 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -54,6 +54,7 @@ struct omap_uart_state {
54 54
55 struct plat_serial8250_port *p; 55 struct plat_serial8250_port *p;
56 struct list_head node; 56 struct list_head node;
57 struct platform_device pdev;
57 58
58#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 59#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
59 int context_valid; 60 int context_valid;
@@ -68,10 +69,9 @@ struct omap_uart_state {
68#endif 69#endif
69}; 70};
70 71
71static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
72static LIST_HEAD(uart_list); 72static LIST_HEAD(uart_list);
73 73
74static struct plat_serial8250_port serial_platform_data[] = { 74static struct plat_serial8250_port serial_platform_data0[] = {
75 { 75 {
76 .membase = IO_ADDRESS(OMAP_UART1_BASE), 76 .membase = IO_ADDRESS(OMAP_UART1_BASE),
77 .mapbase = OMAP_UART1_BASE, 77 .mapbase = OMAP_UART1_BASE,
@@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
81 .regshift = 2, 81 .regshift = 2,
82 .uartclk = OMAP24XX_BASE_BAUD * 16, 82 .uartclk = OMAP24XX_BASE_BAUD * 16,
83 }, { 83 }, {
84 .flags = 0
85 }
86};
87
88static struct plat_serial8250_port serial_platform_data1[] = {
89 {
84 .membase = IO_ADDRESS(OMAP_UART2_BASE), 90 .membase = IO_ADDRESS(OMAP_UART2_BASE),
85 .mapbase = OMAP_UART2_BASE, 91 .mapbase = OMAP_UART2_BASE,
86 .irq = 73, 92 .irq = 73,
@@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
89 .regshift = 2, 95 .regshift = 2,
90 .uartclk = OMAP24XX_BASE_BAUD * 16, 96 .uartclk = OMAP24XX_BASE_BAUD * 16,
91 }, { 97 }, {
98 .flags = 0
99 }
100};
101
102static struct plat_serial8250_port serial_platform_data2[] = {
103 {
92 .membase = IO_ADDRESS(OMAP_UART3_BASE), 104 .membase = IO_ADDRESS(OMAP_UART3_BASE),
93 .mapbase = OMAP_UART3_BASE, 105 .mapbase = OMAP_UART3_BASE,
94 .irq = 74, 106 .irq = 74,
@@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
217 clk_disable(uart->fck); 229 clk_disable(uart->fck);
218} 230}
219 231
232static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
233{
234 /* Set wake-enable bit */
235 if (uart->wk_en && uart->wk_mask) {
236 u32 v = __raw_readl(uart->wk_en);
237 v |= uart->wk_mask;
238 __raw_writel(v, uart->wk_en);
239 }
240
241 /* Ensure IOPAD wake-enables are set */
242 if (cpu_is_omap34xx() && uart->padconf) {
243 u16 v = omap_ctrl_readw(uart->padconf);
244 v |= OMAP3_PADCONF_WAKEUPENABLE0;
245 omap_ctrl_writew(v, uart->padconf);
246 }
247}
248
249static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
250{
251 /* Clear wake-enable bit */
252 if (uart->wk_en && uart->wk_mask) {
253 u32 v = __raw_readl(uart->wk_en);
254 v &= ~uart->wk_mask;
255 __raw_writel(v, uart->wk_en);
256 }
257
258 /* Ensure IOPAD wake-enables are cleared */
259 if (cpu_is_omap34xx() && uart->padconf) {
260 u16 v = omap_ctrl_readw(uart->padconf);
261 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
262 omap_ctrl_writew(v, uart->padconf);
263 }
264}
265
220static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, 266static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
221 int enable) 267 int enable)
222{ 268{
@@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
246 292
247static void omap_uart_allow_sleep(struct omap_uart_state *uart) 293static void omap_uart_allow_sleep(struct omap_uart_state *uart)
248{ 294{
295 if (device_may_wakeup(&uart->pdev.dev))
296 omap_uart_enable_wakeup(uart);
297 else
298 omap_uart_disable_wakeup(uart);
299
249 if (!uart->clocked) 300 if (!uart->clocked)
250 return; 301 return;
251 302
@@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num)
292 /* Check for normal UART wakeup */ 343 /* Check for normal UART wakeup */
293 if (__raw_readl(uart->wk_st) & uart->wk_mask) 344 if (__raw_readl(uart->wk_st) & uart->wk_mask)
294 omap_uart_block_sleep(uart); 345 omap_uart_block_sleep(uart);
295
296 return; 346 return;
297 } 347 }
298 } 348 }
@@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
346 return IRQ_NONE; 396 return IRQ_NONE;
347} 397}
348 398
349static u32 sleep_timeout = DEFAULT_TIMEOUT;
350
351static void omap_uart_idle_init(struct omap_uart_state *uart) 399static void omap_uart_idle_init(struct omap_uart_state *uart)
352{ 400{
353 u32 v;
354 struct plat_serial8250_port *p = uart->p; 401 struct plat_serial8250_port *p = uart->p;
355 int ret; 402 int ret;
356 403
357 uart->can_sleep = 0; 404 uart->can_sleep = 0;
358 uart->timeout = sleep_timeout; 405 uart->timeout = DEFAULT_TIMEOUT;
359 setup_timer(&uart->timer, omap_uart_idle_timer, 406 setup_timer(&uart->timer, omap_uart_idle_timer,
360 (unsigned long) uart); 407 (unsigned long) uart);
361 mod_timer(&uart->timer, jiffies + uart->timeout); 408 mod_timer(&uart->timer, jiffies + uart->timeout);
@@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
413 uart->padconf = 0; 460 uart->padconf = 0;
414 } 461 }
415 462
416 /* Set wake-enable bit */
417 if (uart->wk_en && uart->wk_mask) {
418 v = __raw_readl(uart->wk_en);
419 v |= uart->wk_mask;
420 __raw_writel(v, uart->wk_en);
421 }
422
423 /* Ensure IOPAD wake-enables are set */
424 if (cpu_is_omap34xx() && uart->padconf) {
425 u16 v;
426
427 v = omap_ctrl_readw(uart->padconf);
428 v |= OMAP3_PADCONF_WAKEUPENABLE0;
429 omap_ctrl_writew(v, uart->padconf);
430 }
431
432 p->flags |= UPF_SHARE_IRQ; 463 p->flags |= UPF_SHARE_IRQ;
433 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, 464 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
434 "serial idle", (void *)uart); 465 "serial idle", (void *)uart);
435 WARN_ON(ret); 466 WARN_ON(ret);
436} 467}
437 468
438static ssize_t sleep_timeout_show(struct kobject *kobj, 469void omap_uart_enable_irqs(int enable)
439 struct kobj_attribute *attr, 470{
471 int ret;
472 struct omap_uart_state *uart;
473
474 list_for_each_entry(uart, &uart_list, node) {
475 if (enable)
476 ret = request_irq(uart->p->irq, omap_uart_interrupt,
477 IRQF_SHARED, "serial idle", (void *)uart);
478 else
479 free_irq(uart->p->irq, (void *)uart);
480 }
481}
482
483static ssize_t sleep_timeout_show(struct device *dev,
484 struct device_attribute *attr,
440 char *buf) 485 char *buf)
441{ 486{
442 return sprintf(buf, "%u\n", sleep_timeout / HZ); 487 struct platform_device *pdev = container_of(dev,
488 struct platform_device, dev);
489 struct omap_uart_state *uart = container_of(pdev,
490 struct omap_uart_state, pdev);
491
492 return sprintf(buf, "%u\n", uart->timeout / HZ);
443} 493}
444 494
445static ssize_t sleep_timeout_store(struct kobject *kobj, 495static ssize_t sleep_timeout_store(struct device *dev,
446 struct kobj_attribute *attr, 496 struct device_attribute *attr,
447 const char *buf, size_t n) 497 const char *buf, size_t n)
448{ 498{
449 struct omap_uart_state *uart; 499 struct platform_device *pdev = container_of(dev,
500 struct platform_device, dev);
501 struct omap_uart_state *uart = container_of(pdev,
502 struct omap_uart_state, pdev);
450 unsigned int value; 503 unsigned int value;
451 504
452 if (sscanf(buf, "%u", &value) != 1) { 505 if (sscanf(buf, "%u", &value) != 1) {
453 printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); 506 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
454 return -EINVAL; 507 return -EINVAL;
455 } 508 }
456 sleep_timeout = value * HZ; 509
457 list_for_each_entry(uart, &uart_list, node) { 510 uart->timeout = value * HZ;
458 uart->timeout = sleep_timeout; 511 if (uart->timeout)
459 if (uart->timeout) 512 mod_timer(&uart->timer, jiffies + uart->timeout);
460 mod_timer(&uart->timer, jiffies + uart->timeout); 513 else
461 else 514 /* A zero value means disable timeout feature */
462 /* A zero value means disable timeout feature */ 515 omap_uart_block_sleep(uart);
463 omap_uart_block_sleep(uart); 516
464 }
465 return n; 517 return n;
466} 518}
467 519
468static struct kobj_attribute sleep_timeout_attr = 520DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
469 __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); 521#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
470
471#else 522#else
472static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} 523static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
524#define DEV_CREATE_FILE(dev, attr)
473#endif /* CONFIG_PM */ 525#endif /* CONFIG_PM */
474 526
475static struct platform_device serial_device = { 527static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
476 .name = "serial8250", 528 {
477 .id = PLAT8250_DEV_PLATFORM, 529 .pdev = {
478 .dev = { 530 .name = "serial8250",
479 .platform_data = serial_platform_data, 531 .id = PLAT8250_DEV_PLATFORM,
532 .dev = {
533 .platform_data = serial_platform_data0,
534 },
535 },
536 }, {
537 .pdev = {
538 .name = "serial8250",
539 .id = PLAT8250_DEV_PLATFORM1,
540 .dev = {
541 .platform_data = serial_platform_data1,
542 },
543 },
544 }, {
545 .pdev = {
546 .name = "serial8250",
547 .id = PLAT8250_DEV_PLATFORM2,
548 .dev = {
549 .platform_data = serial_platform_data2,
550 },
551 },
480 }, 552 },
481}; 553};
482 554
483void __init omap_serial_init(void) 555void __init omap_serial_init(void)
484{ 556{
485 int i, err; 557 int i;
486 const struct omap_uart_config *info; 558 const struct omap_uart_config *info;
487 char name[16]; 559 char name[16];
488 560
@@ -496,14 +568,12 @@ void __init omap_serial_init(void)
496 568
497 if (info == NULL) 569 if (info == NULL)
498 return; 570 return;
499 if (cpu_is_omap44xx()) {
500 for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
501 serial_platform_data[i].irq += 32;
502 }
503 571
504 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { 572 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
505 struct plat_serial8250_port *p = serial_platform_data + i;
506 struct omap_uart_state *uart = &omap_uart[i]; 573 struct omap_uart_state *uart = &omap_uart[i];
574 struct platform_device *pdev = &uart->pdev;
575 struct device *dev = &pdev->dev;
576 struct plat_serial8250_port *p = dev->platform_data;
507 577
508 if (!(info->enabled_uarts & (1 << i))) { 578 if (!(info->enabled_uarts & (1 << i))) {
509 p->membase = NULL; 579 p->membase = NULL;
@@ -531,20 +601,21 @@ void __init omap_serial_init(void)
531 uart->num = i; 601 uart->num = i;
532 p->private_data = uart; 602 p->private_data = uart;
533 uart->p = p; 603 uart->p = p;
534 list_add(&uart->node, &uart_list); 604 list_add_tail(&uart->node, &uart_list);
605
606 if (cpu_is_omap44xx())
607 p->irq += 32;
535 608
536 omap_uart_enable_clocks(uart); 609 omap_uart_enable_clocks(uart);
537 omap_uart_reset(uart); 610 omap_uart_reset(uart);
538 omap_uart_idle_init(uart); 611 omap_uart_idle_init(uart);
539 }
540
541 err = platform_device_register(&serial_device);
542
543#ifdef CONFIG_PM
544 if (!err)
545 err = sysfs_create_file(&serial_device.dev.kobj,
546 &sleep_timeout_attr.attr);
547#endif
548 612
613 if (WARN_ON(platform_device_register(pdev)))
614 continue;
615 if ((cpu_is_omap34xx() && uart->padconf) ||
616 (uart->wk_en && uart->wk_mask)) {
617 device_init_wakeup(dev, true);
618 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
619 }
620 }
549} 621}
550
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index f41f8d96ddba..82aa4a3d160c 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -36,7 +36,7 @@
36 36
37 .text 37 .text
38 38
39/* r4 parameters */ 39/* r1 parameters */
40#define SDRC_NO_UNLOCK_DLL 0x0 40#define SDRC_NO_UNLOCK_DLL 0x0
41#define SDRC_UNLOCK_DLL 0x1 41#define SDRC_UNLOCK_DLL 0x1
42 42
@@ -58,7 +58,6 @@
58 58
59/* SDRC_POWER bit settings */ 59/* SDRC_POWER bit settings */
60#define SRFRONIDLEREQ_MASK 0x40 60#define SRFRONIDLEREQ_MASK 0x40
61#define PWDENA_MASK 0x4
62 61
63/* CM_IDLEST1_CORE bit settings */ 62/* CM_IDLEST1_CORE bit settings */
64#define ST_SDRC_MASK 0x2 63#define ST_SDRC_MASK 0x2
@@ -71,41 +70,72 @@
71 70
72/* 71/*
73 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider 72 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
74 * r0 = new SDRC_RFR_CTRL register contents 73 *
75 * r1 = new SDRC_ACTIM_CTRLA register contents 74 * Params passed in registers:
76 * r2 = new SDRC_ACTIM_CTRLB register contents 75 * r0 = new M2 divider setting (only 1 and 2 supported right now)
77 * r3 = new M2 divider setting (only 1 and 2 supported right now) 76 * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
78 * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
79 * SDRC rates < 83MHz 77 * SDRC rates < 83MHz
80 * r5 = number of MPU cycles to wait for SDRC to stabilize after 78 * r2 = number of MPU cycles to wait for SDRC to stabilize after
81 * reprogramming the SDRC when switching to a slower MPU speed 79 * reprogramming the SDRC when switching to a slower MPU speed
82 * r6 = new SDRC_MR_0 register value 80 * r3 = increasing SDRC rate? (1 = yes, 0 = no)
83 * r7 = increasing SDRC rate? (1 = yes, 0 = no) 81 *
82 * Params passed via the stack. The needed params will be copied in SRAM
83 * before use by the code in SRAM (SDRAM is not accessible during SDRC
84 * reconfiguration):
85 * new SDRC_RFR_CTRL_0 register contents
86 * new SDRC_ACTIM_CTRL_A_0 register contents
87 * new SDRC_ACTIM_CTRL_B_0 register contents
88 * new SDRC_MR_0 register value
89 * new SDRC_RFR_CTRL_1 register contents
90 * new SDRC_ACTIM_CTRL_A_1 register contents
91 * new SDRC_ACTIM_CTRL_B_1 register contents
92 * new SDRC_MR_1 register value
84 * 93 *
94 * If the param SDRC_RFR_CTRL_1 is 0, the parameters
95 * are not programmed into the SDRC CS1 registers
85 */ 96 */
86ENTRY(omap3_sram_configure_core_dpll) 97ENTRY(omap3_sram_configure_core_dpll)
87 stmfd sp!, {r1-r12, lr} @ store regs to stack 98 stmfd sp!, {r1-r12, lr} @ store regs to stack
88 ldr r4, [sp, #52] @ pull extra args off the stack 99
89 ldr r5, [sp, #56] @ load extra args from the stack 100 @ pull the extra args off the stack
90 ldr r6, [sp, #60] @ load extra args from the stack 101 @ and store them in SRAM
91 ldr r7, [sp, #64] @ load extra args from the stack 102 ldr r4, [sp, #52]
103 str r4, omap_sdrc_rfr_ctrl_0_val
104 ldr r4, [sp, #56]
105 str r4, omap_sdrc_actim_ctrl_a_0_val
106 ldr r4, [sp, #60]
107 str r4, omap_sdrc_actim_ctrl_b_0_val
108 ldr r4, [sp, #64]
109 str r4, omap_sdrc_mr_0_val
110 ldr r4, [sp, #68]
111 str r4, omap_sdrc_rfr_ctrl_1_val
112 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
113 beq skip_cs1_params @ do not use cs1 params
114 ldr r4, [sp, #72]
115 str r4, omap_sdrc_actim_ctrl_a_1_val
116 ldr r4, [sp, #76]
117 str r4, omap_sdrc_actim_ctrl_b_1_val
118 ldr r4, [sp, #80]
119 str r4, omap_sdrc_mr_1_val
120skip_cs1_params:
92 dsb @ flush buffered writes to interconnect 121 dsb @ flush buffered writes to interconnect
93 cmp r7, #1 @ if increasing SDRC clk rate, 122
123 cmp r3, #1 @ if increasing SDRC clk rate,
94 bleq configure_sdrc @ program the SDRC regs early (for RFR) 124 bleq configure_sdrc @ program the SDRC regs early (for RFR)
95 cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state 125 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
96 bleq unlock_dll 126 bleq unlock_dll
97 blne lock_dll 127 blne lock_dll
98 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC 128 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
99 bl configure_core_dpll @ change the DPLL3 M2 divider 129 bl configure_core_dpll @ change the DPLL3 M2 divider
130 mov r12, r2
131 bl wait_clk_stable @ wait for SDRC to stabilize
100 bl enable_sdrc @ take SDRC out of idle 132 bl enable_sdrc @ take SDRC out of idle
101 cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change 133 cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
102 bleq wait_dll_unlock 134 bleq wait_dll_unlock
103 blne wait_dll_lock 135 blne wait_dll_lock
104 cmp r7, #1 @ if increasing SDRC clk rate, 136 cmp r3, #1 @ if increasing SDRC clk rate,
105 beq return_to_sdram @ return to SDRAM code, otherwise, 137 beq return_to_sdram @ return to SDRAM code, otherwise,
106 bl configure_sdrc @ reprogram SDRC regs now 138 bl configure_sdrc @ reprogram SDRC regs now
107 mov r12, r5
108 bl wait_clk_stable @ wait for SDRC to stabilize
109return_to_sdram: 139return_to_sdram:
110 isb @ prevent speculative exec past here 140 isb @ prevent speculative exec past here
111 mov r0, #0 @ return value 141 mov r0, #0 @ return value
@@ -113,7 +143,7 @@ return_to_sdram:
113unlock_dll: 143unlock_dll:
114 ldr r11, omap3_sdrc_dlla_ctrl 144 ldr r11, omap3_sdrc_dlla_ctrl
115 ldr r12, [r11] 145 ldr r12, [r11]
116 and r12, r12, #FIXEDDELAY_MASK 146 bic r12, r12, #FIXEDDELAY_MASK
117 orr r12, r12, #FIXEDDELAY_DEFAULT 147 orr r12, r12, #FIXEDDELAY_DEFAULT
118 orr r12, r12, #DLLIDLE_MASK 148 orr r12, r12, #DLLIDLE_MASK
119 str r12, [r11] @ (no OCP barrier needed) 149 str r12, [r11] @ (no OCP barrier needed)
@@ -129,7 +159,6 @@ sdram_in_selfrefresh:
129 ldr r12, [r11] @ read the contents of SDRC_POWER 159 ldr r12, [r11] @ read the contents of SDRC_POWER
130 mov r9, r12 @ keep a copy of SDRC_POWER bits 160 mov r9, r12 @ keep a copy of SDRC_POWER bits
131 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle 161 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
132 bic r12, r12, #PWDENA_MASK @ clear PWDENA
133 str r12, [r11] @ write back to SDRC_POWER register 162 str r12, [r11] @ write back to SDRC_POWER register
134 ldr r12, [r11] @ posted-write barrier for SDRC 163 ldr r12, [r11] @ posted-write barrier for SDRC
135idle_sdrc: 164idle_sdrc:
@@ -149,7 +178,7 @@ configure_core_dpll:
149 ldr r12, [r11] 178 ldr r12, [r11]
150 ldr r10, core_m2_mask_val @ modify m2 for core dpll 179 ldr r10, core_m2_mask_val @ modify m2 for core dpll
151 and r12, r12, r10 180 and r12, r12, r10
152 orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT 181 orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
153 str r12, [r11] 182 str r12, [r11]
154 ldr r12, [r11] @ posted-write barrier for CM 183 ldr r12, [r11] @ posted-write barrier for CM
155 bx lr 184 bx lr
@@ -187,15 +216,34 @@ wait_dll_unlock:
187 bne wait_dll_unlock 216 bne wait_dll_unlock
188 bx lr 217 bx lr
189configure_sdrc: 218configure_sdrc:
190 ldr r11, omap3_sdrc_rfr_ctrl 219 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
191 str r0, [r11] 220 ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
192 ldr r11, omap3_sdrc_actim_ctrla 221 str r12, [r11] @ store
193 str r1, [r11] 222 ldr r12, omap_sdrc_actim_ctrl_a_0_val
194 ldr r11, omap3_sdrc_actim_ctrlb 223 ldr r11, omap3_sdrc_actim_ctrl_a_0
195 str r2, [r11] 224 str r12, [r11]
225 ldr r12, omap_sdrc_actim_ctrl_b_0_val
226 ldr r11, omap3_sdrc_actim_ctrl_b_0
227 str r12, [r11]
228 ldr r12, omap_sdrc_mr_0_val
196 ldr r11, omap3_sdrc_mr_0 229 ldr r11, omap3_sdrc_mr_0
197 str r6, [r11] 230 str r12, [r11]
198 ldr r6, [r11] @ posted-write barrier for SDRC 231 ldr r12, omap_sdrc_rfr_ctrl_1_val
232 cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
233 beq skip_cs1_prog @ do not program cs1 params
234 ldr r11, omap3_sdrc_rfr_ctrl_1
235 str r12, [r11]
236 ldr r12, omap_sdrc_actim_ctrl_a_1_val
237 ldr r11, omap3_sdrc_actim_ctrl_a_1
238 str r12, [r11]
239 ldr r12, omap_sdrc_actim_ctrl_b_1_val
240 ldr r11, omap3_sdrc_actim_ctrl_b_1
241 str r12, [r11]
242 ldr r12, omap_sdrc_mr_1_val
243 ldr r11, omap3_sdrc_mr_1
244 str r12, [r11]
245skip_cs1_prog:
246 ldr r12, [r11] @ posted-write barrier for SDRC
199 bx lr 247 bx lr
200 248
201omap3_sdrc_power: 249omap3_sdrc_power:
@@ -206,14 +254,40 @@ omap3_cm_idlest1_core:
206 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) 254 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
207omap3_cm_iclken1_core: 255omap3_cm_iclken1_core:
208 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) 256 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
209omap3_sdrc_rfr_ctrl: 257
258omap3_sdrc_rfr_ctrl_0:
210 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0) 259 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
211omap3_sdrc_actim_ctrla: 260omap3_sdrc_rfr_ctrl_1:
261 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
262omap3_sdrc_actim_ctrl_a_0:
212 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) 263 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
213omap3_sdrc_actim_ctrlb: 264omap3_sdrc_actim_ctrl_a_1:
265 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
266omap3_sdrc_actim_ctrl_b_0:
214 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) 267 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
268omap3_sdrc_actim_ctrl_b_1:
269 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
215omap3_sdrc_mr_0: 270omap3_sdrc_mr_0:
216 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) 271 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
272omap3_sdrc_mr_1:
273 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
274omap_sdrc_rfr_ctrl_0_val:
275 .word 0xDEADBEEF
276omap_sdrc_rfr_ctrl_1_val:
277 .word 0xDEADBEEF
278omap_sdrc_actim_ctrl_a_0_val:
279 .word 0xDEADBEEF
280omap_sdrc_actim_ctrl_a_1_val:
281 .word 0xDEADBEEF
282omap_sdrc_actim_ctrl_b_0_val:
283 .word 0xDEADBEEF
284omap_sdrc_actim_ctrl_b_1_val:
285 .word 0xDEADBEEF
286omap_sdrc_mr_0_val:
287 .word 0xDEADBEEF
288omap_sdrc_mr_1_val:
289 .word 0xDEADBEEF
290
217omap3_sdrc_dlla_status: 291omap3_sdrc_dlla_status:
218 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 292 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
219omap3_sdrc_dlla_ctrl: 293omap3_sdrc_dlla_ctrl:
@@ -223,3 +297,4 @@ core_m2_mask_val:
223 297
224ENTRY(omap3_sram_configure_core_dpll_sz) 298ENTRY(omap3_sram_configure_core_dpll_sz)
225 .word . - omap3_sram_configure_core_dpll 299 .word . - omap3_sram_configure_core_dpll
300
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 05:46:52 -0500