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-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c4
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c4
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c6
-rw-r--r--arch/arm/mach-omap2/clockdomain.c4
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h236
-rw-r--r--arch/arm/mach-omap2/pm24xx.c107
-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h120
7 files changed, 241 insertions, 240 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 43d7246ce335..66e01acfd585 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -70,12 +70,12 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
70 70
71static int omap2_clk_apll96_enable(struct clk *clk) 71static int omap2_clk_apll96_enable(struct clk *clk)
72{ 72{
73 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL); 73 return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
74} 74}
75 75
76static int omap2_clk_apll54_enable(struct clk *clk) 76static int omap2_clk_apll54_enable(struct clk *clk)
77{ 77{
78 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL); 78 return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
79} 79}
80 80
81/* Stop APLL */ 81/* Stop APLL */
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index d932b142d0b6..1381e767ce31 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -177,7 +177,7 @@ static struct clk func_54m_ck = {
177 .clkdm_name = "wkup_clkdm", 177 .clkdm_name = "wkup_clkdm",
178 .init = &omap2_init_clksel_parent, 178 .init = &omap2_init_clksel_parent,
179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
180 .clksel_mask = OMAP24XX_54M_SOURCE, 180 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
181 .clksel = func_54m_clksel, 181 .clksel = func_54m_clksel,
182 .recalc = &omap2_clksel_recalc, 182 .recalc = &omap2_clksel_recalc,
183}; 183};
@@ -223,7 +223,7 @@ static struct clk func_48m_ck = {
223 .clkdm_name = "wkup_clkdm", 223 .clkdm_name = "wkup_clkdm",
224 .init = &omap2_init_clksel_parent, 224 .init = &omap2_init_clksel_parent,
225 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 225 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
226 .clksel_mask = OMAP24XX_48M_SOURCE, 226 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
227 .clksel = func_48m_clksel, 227 .clksel = func_48m_clksel,
228 .recalc = &omap2_clksel_recalc, 228 .recalc = &omap2_clksel_recalc,
229 .round_rate = &omap2_clksel_round_rate, 229 .round_rate = &omap2_clksel_round_rate,
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 0438b6e4f51a..1aac22709dfe 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -177,7 +177,7 @@ static struct clk func_54m_ck = {
177 .clkdm_name = "wkup_clkdm", 177 .clkdm_name = "wkup_clkdm",
178 .init = &omap2_init_clksel_parent, 178 .init = &omap2_init_clksel_parent,
179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 179 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
180 .clksel_mask = OMAP24XX_54M_SOURCE, 180 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
181 .clksel = func_54m_clksel, 181 .clksel = func_54m_clksel,
182 .recalc = &omap2_clksel_recalc, 182 .recalc = &omap2_clksel_recalc,
183}; 183};
@@ -214,7 +214,7 @@ static struct clk func_96m_ck = {
214 .clkdm_name = "wkup_clkdm", 214 .clkdm_name = "wkup_clkdm",
215 .init = &omap2_init_clksel_parent, 215 .init = &omap2_init_clksel_parent,
216 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 216 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
217 .clksel_mask = OMAP2430_96M_SOURCE, 217 .clksel_mask = OMAP2430_96M_SOURCE_MASK,
218 .clksel = func_96m_clksel, 218 .clksel = func_96m_clksel,
219 .recalc = &omap2_clksel_recalc, 219 .recalc = &omap2_clksel_recalc,
220}; 220};
@@ -244,7 +244,7 @@ static struct clk func_48m_ck = {
244 .clkdm_name = "wkup_clkdm", 244 .clkdm_name = "wkup_clkdm",
245 .init = &omap2_init_clksel_parent, 245 .init = &omap2_init_clksel_parent,
246 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 246 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
247 .clksel_mask = OMAP24XX_48M_SOURCE, 247 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
248 .clksel = func_48m_clksel, 248 .clksel = func_48m_clksel,
249 .recalc = &omap2_clksel_recalc, 249 .recalc = &omap2_clksel_recalc,
250 .round_rate = &omap2_clksel_round_rate, 250 .round_rate = &omap2_clksel_round_rate,
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6e568ec995ee..5d80cb897489 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -809,7 +809,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
809 809
810 if (cpu_is_omap24xx()) { 810 if (cpu_is_omap24xx()) {
811 811
812 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, 812 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
813 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 813 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
814 814
815 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 815 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
@@ -853,7 +853,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
853 853
854 if (cpu_is_omap24xx()) { 854 if (cpu_is_omap24xx()) {
855 855
856 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, 856 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
857 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 857 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
858 858
859 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 859 } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 297a2fe634ea..da51cc3ed7eb 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -20,43 +20,43 @@
20 20
21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22#define OMAP24XX_EN_CAM_SHIFT 31 22#define OMAP24XX_EN_CAM_SHIFT 31
23#define OMAP24XX_EN_CAM (1 << 31) 23#define OMAP24XX_EN_CAM_MASK (1 << 31)
24#define OMAP24XX_EN_WDT4_SHIFT 29 24#define OMAP24XX_EN_WDT4_SHIFT 29
25#define OMAP24XX_EN_WDT4 (1 << 29) 25#define OMAP24XX_EN_WDT4_MASK (1 << 29)
26#define OMAP2420_EN_WDT3_SHIFT 28 26#define OMAP2420_EN_WDT3_SHIFT 28
27#define OMAP2420_EN_WDT3 (1 << 28) 27#define OMAP2420_EN_WDT3_MASK (1 << 28)
28#define OMAP24XX_EN_MSPRO_SHIFT 27 28#define OMAP24XX_EN_MSPRO_SHIFT 27
29#define OMAP24XX_EN_MSPRO (1 << 27) 29#define OMAP24XX_EN_MSPRO_MASK (1 << 27)
30#define OMAP24XX_EN_FAC_SHIFT 25 30#define OMAP24XX_EN_FAC_SHIFT 25
31#define OMAP24XX_EN_FAC (1 << 25) 31#define OMAP24XX_EN_FAC_MASK (1 << 25)
32#define OMAP2420_EN_EAC_SHIFT 24 32#define OMAP2420_EN_EAC_SHIFT 24
33#define OMAP2420_EN_EAC (1 << 24) 33#define OMAP2420_EN_EAC_MASK (1 << 24)
34#define OMAP24XX_EN_HDQ_SHIFT 23 34#define OMAP24XX_EN_HDQ_SHIFT 23
35#define OMAP24XX_EN_HDQ (1 << 23) 35#define OMAP24XX_EN_HDQ_MASK (1 << 23)
36#define OMAP2420_EN_I2C2_SHIFT 20 36#define OMAP2420_EN_I2C2_SHIFT 20
37#define OMAP2420_EN_I2C2 (1 << 20) 37#define OMAP2420_EN_I2C2_MASK (1 << 20)
38#define OMAP2420_EN_I2C1_SHIFT 19 38#define OMAP2420_EN_I2C1_SHIFT 19
39#define OMAP2420_EN_I2C1 (1 << 19) 39#define OMAP2420_EN_I2C1_MASK (1 << 19)
40 40
41/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ 41/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
42#define OMAP2430_EN_MCBSP5_SHIFT 5 42#define OMAP2430_EN_MCBSP5_SHIFT 5
43#define OMAP2430_EN_MCBSP5 (1 << 5) 43#define OMAP2430_EN_MCBSP5_MASK (1 << 5)
44#define OMAP2430_EN_MCBSP4_SHIFT 4 44#define OMAP2430_EN_MCBSP4_SHIFT 4
45#define OMAP2430_EN_MCBSP4 (1 << 4) 45#define OMAP2430_EN_MCBSP4_MASK (1 << 4)
46#define OMAP2430_EN_MCBSP3_SHIFT 3 46#define OMAP2430_EN_MCBSP3_SHIFT 3
47#define OMAP2430_EN_MCBSP3 (1 << 3) 47#define OMAP2430_EN_MCBSP3_MASK (1 << 3)
48#define OMAP24XX_EN_SSI_SHIFT 1 48#define OMAP24XX_EN_SSI_SHIFT 1
49#define OMAP24XX_EN_SSI (1 << 1) 49#define OMAP24XX_EN_SSI_MASK (1 << 1)
50 50
51/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 51/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
52#define OMAP24XX_EN_MPU_WDT_SHIFT 3 52#define OMAP24XX_EN_MPU_WDT_SHIFT 3
53#define OMAP24XX_EN_MPU_WDT (1 << 3) 53#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3)
54 54
55/* Bits specific to each register */ 55/* Bits specific to each register */
56 56
57/* CM_IDLEST_MPU */ 57/* CM_IDLEST_MPU */
58/* 2430 only */ 58/* 2430 only */
59#define OMAP2430_ST_MPU (1 << 0) 59#define OMAP2430_ST_MPU_MASK (1 << 0)
60 60
61/* CM_CLKSEL_MPU */ 61/* CM_CLKSEL_MPU */
62#define OMAP24XX_CLKSEL_MPU_SHIFT 0 62#define OMAP24XX_CLKSEL_MPU_SHIFT 0
@@ -68,46 +68,46 @@
68 68
69/* CM_FCLKEN1_CORE specific bits*/ 69/* CM_FCLKEN1_CORE specific bits*/
70#define OMAP24XX_EN_TV_SHIFT 2 70#define OMAP24XX_EN_TV_SHIFT 2
71#define OMAP24XX_EN_TV (1 << 2) 71#define OMAP24XX_EN_TV_MASK (1 << 2)
72#define OMAP24XX_EN_DSS2_SHIFT 1 72#define OMAP24XX_EN_DSS2_SHIFT 1
73#define OMAP24XX_EN_DSS2 (1 << 1) 73#define OMAP24XX_EN_DSS2_MASK (1 << 1)
74#define OMAP24XX_EN_DSS1_SHIFT 0 74#define OMAP24XX_EN_DSS1_SHIFT 0
75#define OMAP24XX_EN_DSS1 (1 << 0) 75#define OMAP24XX_EN_DSS1_MASK (1 << 0)
76 76
77/* CM_FCLKEN2_CORE specific bits */ 77/* CM_FCLKEN2_CORE specific bits */
78#define OMAP2430_EN_I2CHS2_SHIFT 20 78#define OMAP2430_EN_I2CHS2_SHIFT 20
79#define OMAP2430_EN_I2CHS2 (1 << 20) 79#define OMAP2430_EN_I2CHS2_MASK (1 << 20)
80#define OMAP2430_EN_I2CHS1_SHIFT 19 80#define OMAP2430_EN_I2CHS1_SHIFT 19
81#define OMAP2430_EN_I2CHS1 (1 << 19) 81#define OMAP2430_EN_I2CHS1_MASK (1 << 19)
82#define OMAP2430_EN_MMCHSDB2_SHIFT 17 82#define OMAP2430_EN_MMCHSDB2_SHIFT 17
83#define OMAP2430_EN_MMCHSDB2 (1 << 17) 83#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17)
84#define OMAP2430_EN_MMCHSDB1_SHIFT 16 84#define OMAP2430_EN_MMCHSDB1_SHIFT 16
85#define OMAP2430_EN_MMCHSDB1 (1 << 16) 85#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16)
86 86
87/* CM_ICLKEN1_CORE specific bits */ 87/* CM_ICLKEN1_CORE specific bits */
88#define OMAP24XX_EN_MAILBOXES_SHIFT 30 88#define OMAP24XX_EN_MAILBOXES_SHIFT 30
89#define OMAP24XX_EN_MAILBOXES (1 << 30) 89#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30)
90#define OMAP24XX_EN_DSS_SHIFT 0 90#define OMAP24XX_EN_DSS_SHIFT 0
91#define OMAP24XX_EN_DSS (1 << 0) 91#define OMAP24XX_EN_DSS_MASK (1 << 0)
92 92
93/* CM_ICLKEN2_CORE specific bits */ 93/* CM_ICLKEN2_CORE specific bits */
94 94
95/* CM_ICLKEN3_CORE */ 95/* CM_ICLKEN3_CORE */
96/* 2430 only */ 96/* 2430 only */
97#define OMAP2430_EN_SDRC_SHIFT 2 97#define OMAP2430_EN_SDRC_SHIFT 2
98#define OMAP2430_EN_SDRC (1 << 2) 98#define OMAP2430_EN_SDRC_MASK (1 << 2)
99 99
100/* CM_ICLKEN4_CORE */ 100/* CM_ICLKEN4_CORE */
101#define OMAP24XX_EN_PKA_SHIFT 4 101#define OMAP24XX_EN_PKA_SHIFT 4
102#define OMAP24XX_EN_PKA (1 << 4) 102#define OMAP24XX_EN_PKA_MASK (1 << 4)
103#define OMAP24XX_EN_AES_SHIFT 3 103#define OMAP24XX_EN_AES_SHIFT 3
104#define OMAP24XX_EN_AES (1 << 3) 104#define OMAP24XX_EN_AES_MASK (1 << 3)
105#define OMAP24XX_EN_RNG_SHIFT 2 105#define OMAP24XX_EN_RNG_SHIFT 2
106#define OMAP24XX_EN_RNG (1 << 2) 106#define OMAP24XX_EN_RNG_MASK (1 << 2)
107#define OMAP24XX_EN_SHA_SHIFT 1 107#define OMAP24XX_EN_SHA_SHIFT 1
108#define OMAP24XX_EN_SHA (1 << 1) 108#define OMAP24XX_EN_SHA_MASK (1 << 1)
109#define OMAP24XX_EN_DES_SHIFT 0 109#define OMAP24XX_EN_DES_SHIFT 0
110#define OMAP24XX_EN_DES (1 << 0) 110#define OMAP24XX_EN_DES_MASK (1 << 0)
111 111
112/* CM_IDLEST1_CORE specific bits */ 112/* CM_IDLEST1_CORE specific bits */
113#define OMAP24XX_ST_MAILBOXES_SHIFT 30 113#define OMAP24XX_ST_MAILBOXES_SHIFT 30
@@ -138,9 +138,9 @@
138/* CM_IDLEST2_CORE */ 138/* CM_IDLEST2_CORE */
139#define OMAP2430_ST_MCBSP5_SHIFT 5 139#define OMAP2430_ST_MCBSP5_SHIFT 5
140#define OMAP2430_ST_MCBSP5_MASK (1 << 5) 140#define OMAP2430_ST_MCBSP5_MASK (1 << 5)
141#define OMAP2430_ST_MCBSP4_SHIFT 4 141#define OMAP2430_ST_MCBSP4_SHIFT 4
142#define OMAP2430_ST_MCBSP4_MASK (1 << 4) 142#define OMAP2430_ST_MCBSP4_MASK (1 << 4)
143#define OMAP2430_ST_MCBSP3_SHIFT 3 143#define OMAP2430_ST_MCBSP3_SHIFT 3
144#define OMAP2430_ST_MCBSP3_MASK (1 << 3) 144#define OMAP2430_ST_MCBSP3_MASK (1 << 3)
145#define OMAP24XX_ST_SSI_SHIFT 1 145#define OMAP24XX_ST_SSI_SHIFT 1
146#define OMAP24XX_ST_SSI_MASK (1 << 1) 146#define OMAP24XX_ST_SSI_MASK (1 << 1)
@@ -162,62 +162,62 @@
162#define OMAP24XX_ST_DES_MASK (1 << 0) 162#define OMAP24XX_ST_DES_MASK (1 << 0)
163 163
164/* CM_AUTOIDLE1_CORE */ 164/* CM_AUTOIDLE1_CORE */
165#define OMAP24XX_AUTO_CAM (1 << 31) 165#define OMAP24XX_AUTO_CAM_MASK (1 << 31)
166#define OMAP24XX_AUTO_MAILBOXES (1 << 30) 166#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30)
167#define OMAP24XX_AUTO_WDT4 (1 << 29) 167#define OMAP24XX_AUTO_WDT4_MASK (1 << 29)
168#define OMAP2420_AUTO_WDT3 (1 << 28) 168#define OMAP2420_AUTO_WDT3_MASK (1 << 28)
169#define OMAP24XX_AUTO_MSPRO (1 << 27) 169#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27)
170#define OMAP2420_AUTO_MMC (1 << 26) 170#define OMAP2420_AUTO_MMC_MASK (1 << 26)
171#define OMAP24XX_AUTO_FAC (1 << 25) 171#define OMAP24XX_AUTO_FAC_MASK (1 << 25)
172#define OMAP2420_AUTO_EAC (1 << 24) 172#define OMAP2420_AUTO_EAC_MASK (1 << 24)
173#define OMAP24XX_AUTO_HDQ (1 << 23) 173#define OMAP24XX_AUTO_HDQ_MASK (1 << 23)
174#define OMAP24XX_AUTO_UART2 (1 << 22) 174#define OMAP24XX_AUTO_UART2_MASK (1 << 22)
175#define OMAP24XX_AUTO_UART1 (1 << 21) 175#define OMAP24XX_AUTO_UART1_MASK (1 << 21)
176#define OMAP24XX_AUTO_I2C2 (1 << 20) 176#define OMAP24XX_AUTO_I2C2_MASK (1 << 20)
177#define OMAP24XX_AUTO_I2C1 (1 << 19) 177#define OMAP24XX_AUTO_I2C1_MASK (1 << 19)
178#define OMAP24XX_AUTO_MCSPI2 (1 << 18) 178#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18)
179#define OMAP24XX_AUTO_MCSPI1 (1 << 17) 179#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17)
180#define OMAP24XX_AUTO_MCBSP2 (1 << 16) 180#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16)
181#define OMAP24XX_AUTO_MCBSP1 (1 << 15) 181#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15)
182#define OMAP24XX_AUTO_GPT12 (1 << 14) 182#define OMAP24XX_AUTO_GPT12_MASK (1 << 14)
183#define OMAP24XX_AUTO_GPT11 (1 << 13) 183#define OMAP24XX_AUTO_GPT11_MASK (1 << 13)
184#define OMAP24XX_AUTO_GPT10 (1 << 12) 184#define OMAP24XX_AUTO_GPT10_MASK (1 << 12)
185#define OMAP24XX_AUTO_GPT9 (1 << 11) 185#define OMAP24XX_AUTO_GPT9_MASK (1 << 11)
186#define OMAP24XX_AUTO_GPT8 (1 << 10) 186#define OMAP24XX_AUTO_GPT8_MASK (1 << 10)
187#define OMAP24XX_AUTO_GPT7 (1 << 9) 187#define OMAP24XX_AUTO_GPT7_MASK (1 << 9)
188#define OMAP24XX_AUTO_GPT6 (1 << 8) 188#define OMAP24XX_AUTO_GPT6_MASK (1 << 8)
189#define OMAP24XX_AUTO_GPT5 (1 << 7) 189#define OMAP24XX_AUTO_GPT5_MASK (1 << 7)
190#define OMAP24XX_AUTO_GPT4 (1 << 6) 190#define OMAP24XX_AUTO_GPT4_MASK (1 << 6)
191#define OMAP24XX_AUTO_GPT3 (1 << 5) 191#define OMAP24XX_AUTO_GPT3_MASK (1 << 5)
192#define OMAP24XX_AUTO_GPT2 (1 << 4) 192#define OMAP24XX_AUTO_GPT2_MASK (1 << 4)
193#define OMAP2420_AUTO_VLYNQ (1 << 3) 193#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3)
194#define OMAP24XX_AUTO_DSS (1 << 0) 194#define OMAP24XX_AUTO_DSS_MASK (1 << 0)
195 195
196/* CM_AUTOIDLE2_CORE */ 196/* CM_AUTOIDLE2_CORE */
197#define OMAP2430_AUTO_MDM_INTC (1 << 11) 197#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11)
198#define OMAP2430_AUTO_GPIO5 (1 << 10) 198#define OMAP2430_AUTO_GPIO5_MASK (1 << 10)
199#define OMAP2430_AUTO_MCSPI3 (1 << 9) 199#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9)
200#define OMAP2430_AUTO_MMCHS2 (1 << 8) 200#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8)
201#define OMAP2430_AUTO_MMCHS1 (1 << 7) 201#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7)
202#define OMAP2430_AUTO_USBHS (1 << 6) 202#define OMAP2430_AUTO_USBHS_MASK (1 << 6)
203#define OMAP2430_AUTO_MCBSP5 (1 << 5) 203#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5)
204#define OMAP2430_AUTO_MCBSP4 (1 << 4) 204#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4)
205#define OMAP2430_AUTO_MCBSP3 (1 << 3) 205#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3)
206#define OMAP24XX_AUTO_UART3 (1 << 2) 206#define OMAP24XX_AUTO_UART3_MASK (1 << 2)
207#define OMAP24XX_AUTO_SSI (1 << 1) 207#define OMAP24XX_AUTO_SSI_MASK (1 << 1)
208#define OMAP24XX_AUTO_USB (1 << 0) 208#define OMAP24XX_AUTO_USB_MASK (1 << 0)
209 209
210/* CM_AUTOIDLE3_CORE */ 210/* CM_AUTOIDLE3_CORE */
211#define OMAP24XX_AUTO_SDRC (1 << 2) 211#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
212#define OMAP24XX_AUTO_GPMC (1 << 1) 212#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
213#define OMAP24XX_AUTO_SDMA (1 << 0) 213#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
214 214
215/* CM_AUTOIDLE4_CORE */ 215/* CM_AUTOIDLE4_CORE */
216#define OMAP24XX_AUTO_PKA (1 << 4) 216#define OMAP24XX_AUTO_PKA_MASK (1 << 4)
217#define OMAP24XX_AUTO_AES (1 << 3) 217#define OMAP24XX_AUTO_AES_MASK (1 << 3)
218#define OMAP24XX_AUTO_RNG (1 << 2) 218#define OMAP24XX_AUTO_RNG_MASK (1 << 2)
219#define OMAP24XX_AUTO_SHA (1 << 1) 219#define OMAP24XX_AUTO_SHA_MASK (1 << 1)
220#define OMAP24XX_AUTO_DES (1 << 0) 220#define OMAP24XX_AUTO_DES_MASK (1 << 0)
221 221
222/* CM_CLKSEL1_CORE */ 222/* CM_CLKSEL1_CORE */
223#define OMAP24XX_CLKSEL_USB_SHIFT 25 223#define OMAP24XX_CLKSEL_USB_SHIFT 25
@@ -269,9 +269,9 @@
269 269
270/* CM_FCLKEN_GFX */ 270/* CM_FCLKEN_GFX */
271#define OMAP24XX_EN_3D_SHIFT 2 271#define OMAP24XX_EN_3D_SHIFT 2
272#define OMAP24XX_EN_3D (1 << 2) 272#define OMAP24XX_EN_3D_MASK (1 << 2)
273#define OMAP24XX_EN_2D_SHIFT 1 273#define OMAP24XX_EN_2D_SHIFT 1
274#define OMAP24XX_EN_2D (1 << 1) 274#define OMAP24XX_EN_2D_MASK (1 << 1)
275 275
276/* CM_ICLKEN_GFX specific bits */ 276/* CM_ICLKEN_GFX specific bits */
277 277
@@ -287,13 +287,13 @@
287 287
288/* CM_ICLKEN_WKUP specific bits */ 288/* CM_ICLKEN_WKUP specific bits */
289#define OMAP2430_EN_ICR_SHIFT 6 289#define OMAP2430_EN_ICR_SHIFT 6
290#define OMAP2430_EN_ICR (1 << 6) 290#define OMAP2430_EN_ICR_MASK (1 << 6)
291#define OMAP24XX_EN_OMAPCTRL_SHIFT 5 291#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
292#define OMAP24XX_EN_OMAPCTRL (1 << 5) 292#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5)
293#define OMAP24XX_EN_WDT1_SHIFT 4 293#define OMAP24XX_EN_WDT1_SHIFT 4
294#define OMAP24XX_EN_WDT1 (1 << 4) 294#define OMAP24XX_EN_WDT1_MASK (1 << 4)
295#define OMAP24XX_EN_32KSYNC_SHIFT 1 295#define OMAP24XX_EN_32KSYNC_SHIFT 1
296#define OMAP24XX_EN_32KSYNC (1 << 1) 296#define OMAP24XX_EN_32KSYNC_MASK (1 << 1)
297 297
298/* CM_IDLEST_WKUP specific bits */ 298/* CM_IDLEST_WKUP specific bits */
299#define OMAP2430_ST_ICR_SHIFT 6 299#define OMAP2430_ST_ICR_SHIFT 6
@@ -308,12 +308,12 @@
308#define OMAP24XX_ST_32KSYNC_MASK (1 << 1) 308#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
309 309
310/* CM_AUTOIDLE_WKUP */ 310/* CM_AUTOIDLE_WKUP */
311#define OMAP24XX_AUTO_OMAPCTRL (1 << 5) 311#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5)
312#define OMAP24XX_AUTO_WDT1 (1 << 4) 312#define OMAP24XX_AUTO_WDT1_MASK (1 << 4)
313#define OMAP24XX_AUTO_MPU_WDT (1 << 3) 313#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3)
314#define OMAP24XX_AUTO_GPIOS (1 << 2) 314#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2)
315#define OMAP24XX_AUTO_32KSYNC (1 << 1) 315#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1)
316#define OMAP24XX_AUTO_GPT1 (1 << 0) 316#define OMAP24XX_AUTO_GPT1_MASK (1 << 0)
317 317
318/* CM_CLKSEL_WKUP */ 318/* CM_CLKSEL_WKUP */
319#define OMAP24XX_CLKSEL_GPT1_SHIFT 0 319#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
@@ -328,12 +328,12 @@
328#define OMAP24XX_EN_DPLL_MASK (0x3 << 0) 328#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
329 329
330/* CM_IDLEST_CKGEN */ 330/* CM_IDLEST_CKGEN */
331#define OMAP24XX_ST_54M_APLL (1 << 9) 331#define OMAP24XX_ST_54M_APLL_MASK (1 << 9)
332#define OMAP24XX_ST_96M_APLL (1 << 8) 332#define OMAP24XX_ST_96M_APLL_MASK (1 << 8)
333#define OMAP24XX_ST_54M_CLK (1 << 6) 333#define OMAP24XX_ST_54M_CLK_MASK (1 << 6)
334#define OMAP24XX_ST_12M_CLK (1 << 5) 334#define OMAP24XX_ST_12M_CLK_MASK (1 << 5)
335#define OMAP24XX_ST_48M_CLK (1 << 4) 335#define OMAP24XX_ST_48M_CLK_MASK (1 << 4)
336#define OMAP24XX_ST_96M_CLK (1 << 2) 336#define OMAP24XX_ST_96M_CLK_MASK (1 << 2)
337#define OMAP24XX_ST_CORE_CLK_SHIFT 0 337#define OMAP24XX_ST_CORE_CLK_SHIFT 0
338#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) 338#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
339 339
@@ -355,11 +355,11 @@
355#define OMAP24XX_DPLL_DIV_SHIFT 8 355#define OMAP24XX_DPLL_DIV_SHIFT 8
356#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) 356#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
357#define OMAP24XX_54M_SOURCE_SHIFT 5 357#define OMAP24XX_54M_SOURCE_SHIFT 5
358#define OMAP24XX_54M_SOURCE (1 << 5) 358#define OMAP24XX_54M_SOURCE_MASK (1 << 5)
359#define OMAP2430_96M_SOURCE_SHIFT 4 359#define OMAP2430_96M_SOURCE_SHIFT 4
360#define OMAP2430_96M_SOURCE (1 << 4) 360#define OMAP2430_96M_SOURCE_MASK (1 << 4)
361#define OMAP24XX_48M_SOURCE_SHIFT 3 361#define OMAP24XX_48M_SOURCE_SHIFT 3
362#define OMAP24XX_48M_SOURCE (1 << 3) 362#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
363#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 363#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
364#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) 364#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
365 365
@@ -369,29 +369,29 @@
369 369
370/* CM_FCLKEN_DSP */ 370/* CM_FCLKEN_DSP */
371#define OMAP2420_EN_IVA_COP_SHIFT 10 371#define OMAP2420_EN_IVA_COP_SHIFT 10
372#define OMAP2420_EN_IVA_COP (1 << 10) 372#define OMAP2420_EN_IVA_COP_MASK (1 << 10)
373#define OMAP2420_EN_IVA_MPU_SHIFT 8 373#define OMAP2420_EN_IVA_MPU_SHIFT 8
374#define OMAP2420_EN_IVA_MPU (1 << 8) 374#define OMAP2420_EN_IVA_MPU_MASK (1 << 8)
375#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 375#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
376#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0) 376#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0)
377 377
378/* CM_ICLKEN_DSP */ 378/* CM_ICLKEN_DSP */
379#define OMAP2420_EN_DSP_IPI_SHIFT 1 379#define OMAP2420_EN_DSP_IPI_SHIFT 1
380#define OMAP2420_EN_DSP_IPI (1 << 1) 380#define OMAP2420_EN_DSP_IPI_MASK (1 << 1)
381 381
382/* CM_IDLEST_DSP */ 382/* CM_IDLEST_DSP */
383#define OMAP2420_ST_IVA (1 << 8) 383#define OMAP2420_ST_IVA_MASK (1 << 8)
384#define OMAP2420_ST_IPI (1 << 1) 384#define OMAP2420_ST_IPI_MASK (1 << 1)
385#define OMAP24XX_ST_DSP (1 << 0) 385#define OMAP24XX_ST_DSP_MASK (1 << 0)
386 386
387/* CM_AUTOIDLE_DSP */ 387/* CM_AUTOIDLE_DSP */
388#define OMAP2420_AUTO_DSP_IPI (1 << 1) 388#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1)
389 389
390/* CM_CLKSEL_DSP */ 390/* CM_CLKSEL_DSP */
391#define OMAP2420_SYNC_IVA (1 << 13) 391#define OMAP2420_SYNC_IVA_MASK (1 << 13)
392#define OMAP2420_CLKSEL_IVA_SHIFT 8 392#define OMAP2420_CLKSEL_IVA_SHIFT 8
393#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) 393#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
394#define OMAP24XX_SYNC_DSP (1 << 7) 394#define OMAP24XX_SYNC_DSP_MASK (1 << 7)
395#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 395#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
396#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) 396#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
397#define OMAP24XX_CLKSEL_DSP_SHIFT 0 397#define OMAP24XX_CLKSEL_DSP_SHIFT 0
@@ -406,24 +406,24 @@
406/* CM_FCLKEN_MDM */ 406/* CM_FCLKEN_MDM */
407/* 2430 only */ 407/* 2430 only */
408#define OMAP2430_EN_OSC_SHIFT 1 408#define OMAP2430_EN_OSC_SHIFT 1
409#define OMAP2430_EN_OSC (1 << 1) 409#define OMAP2430_EN_OSC_MASK (1 << 1)
410 410
411/* CM_ICLKEN_MDM */ 411/* CM_ICLKEN_MDM */
412/* 2430 only */ 412/* 2430 only */
413#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 413#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
414#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0) 414#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0)
415 415
416/* CM_IDLEST_MDM specific bits */ 416/* CM_IDLEST_MDM specific bits */
417/* 2430 only */ 417/* 2430 only */
418 418
419/* CM_AUTOIDLE_MDM */ 419/* CM_AUTOIDLE_MDM */
420/* 2430 only */ 420/* 2430 only */
421#define OMAP2430_AUTO_OSC (1 << 1) 421#define OMAP2430_AUTO_OSC_MASK (1 << 1)
422#define OMAP2430_AUTO_MDM (1 << 0) 422#define OMAP2430_AUTO_MDM_MASK (1 << 0)
423 423
424/* CM_CLKSEL_MDM */ 424/* CM_CLKSEL_MDM */
425/* 2430 only */ 425/* 2430 only */
426#define OMAP2430_SYNC_MDM (1 << 4) 426#define OMAP2430_SYNC_MDM_MASK (1 << 4)
427#define OMAP2430_CLKSEL_MDM_SHIFT 0 427#define OMAP2430_CLKSEL_MDM_SHIFT 0
428#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) 428#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
429 429
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 7816c4e84a32..b8c9e900a679 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -170,7 +170,7 @@ static int omap2_i2c_active(void)
170 u32 l; 170 u32 l;
171 171
172 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 172 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
173 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1); 173 return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
174} 174}
175 175
176static int sti_console_enabled; 176static int sti_console_enabled;
@@ -183,7 +183,7 @@ static int omap2_allow_mpu_retention(void)
183 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 183 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
184 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 | 184 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
185 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 | 185 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
186 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1)) 186 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1_MASK))
187 return 0; 187 return 0;
188 /* Check for UART3. */ 188 /* Check for UART3. */
189 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 189 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
@@ -351,7 +351,7 @@ static void __init prcm_setup_regs(void)
351 struct powerdomain *pwrdm; 351 struct powerdomain *pwrdm;
352 352
353 /* Enable autoidle */ 353 /* Enable autoidle */
354 prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD, 354 prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
355 OMAP2_PRCM_SYSCONFIG_OFFSET); 355 OMAP2_PRCM_SYSCONFIG_OFFSET);
356 356
357 /* 357 /*
@@ -390,53 +390,54 @@ static void __init prcm_setup_regs(void)
390 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); 390 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
391 391
392 /* Enable clock autoidle for all domains */ 392 /* Enable clock autoidle for all domains */
393 cm_write_mod_reg(OMAP24XX_AUTO_CAM | 393 cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
394 OMAP24XX_AUTO_MAILBOXES | 394 OMAP24XX_AUTO_MAILBOXES_MASK |
395 OMAP24XX_AUTO_WDT4 | 395 OMAP24XX_AUTO_WDT4_MASK |
396 OMAP2420_AUTO_WDT3 | 396 OMAP2420_AUTO_WDT3_MASK |
397 OMAP24XX_AUTO_MSPRO | 397 OMAP24XX_AUTO_MSPRO_MASK |
398 OMAP2420_AUTO_MMC | 398 OMAP2420_AUTO_MMC_MASK |
399 OMAP24XX_AUTO_FAC | 399 OMAP24XX_AUTO_FAC_MASK |
400 OMAP2420_AUTO_EAC | 400 OMAP2420_AUTO_EAC_MASK |
401 OMAP24XX_AUTO_HDQ | 401 OMAP24XX_AUTO_HDQ_MASK |
402 OMAP24XX_AUTO_UART2 | 402 OMAP24XX_AUTO_UART2_MASK |
403 OMAP24XX_AUTO_UART1 | 403 OMAP24XX_AUTO_UART1_MASK |
404 OMAP24XX_AUTO_I2C2 | 404 OMAP24XX_AUTO_I2C2_MASK |
405 OMAP24XX_AUTO_I2C1 | 405 OMAP24XX_AUTO_I2C1_MASK |
406 OMAP24XX_AUTO_MCSPI2 | 406 OMAP24XX_AUTO_MCSPI2_MASK |
407 OMAP24XX_AUTO_MCSPI1 | 407 OMAP24XX_AUTO_MCSPI1_MASK |
408 OMAP24XX_AUTO_MCBSP2 | 408 OMAP24XX_AUTO_MCBSP2_MASK |
409 OMAP24XX_AUTO_MCBSP1 | 409 OMAP24XX_AUTO_MCBSP1_MASK |
410 OMAP24XX_AUTO_GPT12 | 410 OMAP24XX_AUTO_GPT12_MASK |
411 OMAP24XX_AUTO_GPT11 | 411 OMAP24XX_AUTO_GPT11_MASK |
412 OMAP24XX_AUTO_GPT10 | 412 OMAP24XX_AUTO_GPT10_MASK |
413 OMAP24XX_AUTO_GPT9 | 413 OMAP24XX_AUTO_GPT9_MASK |
414 OMAP24XX_AUTO_GPT8 | 414 OMAP24XX_AUTO_GPT8_MASK |
415 OMAP24XX_AUTO_GPT7 | 415 OMAP24XX_AUTO_GPT7_MASK |
416 OMAP24XX_AUTO_GPT6 | 416 OMAP24XX_AUTO_GPT6_MASK |
417 OMAP24XX_AUTO_GPT5 | 417 OMAP24XX_AUTO_GPT5_MASK |
418 OMAP24XX_AUTO_GPT4 | 418 OMAP24XX_AUTO_GPT4_MASK |
419 OMAP24XX_AUTO_GPT3 | 419 OMAP24XX_AUTO_GPT3_MASK |
420 OMAP24XX_AUTO_GPT2 | 420 OMAP24XX_AUTO_GPT2_MASK |
421 OMAP2420_AUTO_VLYNQ | 421 OMAP2420_AUTO_VLYNQ_MASK |
422 OMAP24XX_AUTO_DSS, 422 OMAP24XX_AUTO_DSS_MASK,
423 CORE_MOD, CM_AUTOIDLE1); 423 CORE_MOD, CM_AUTOIDLE1);
424 cm_write_mod_reg(OMAP24XX_AUTO_UART3 | 424 cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
425 OMAP24XX_AUTO_SSI | 425 OMAP24XX_AUTO_SSI_MASK |
426 OMAP24XX_AUTO_USB, 426 OMAP24XX_AUTO_USB_MASK,
427 CORE_MOD, CM_AUTOIDLE2); 427 CORE_MOD, CM_AUTOIDLE2);
428 cm_write_mod_reg(OMAP24XX_AUTO_SDRC | 428 cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
429 OMAP24XX_AUTO_GPMC | 429 OMAP24XX_AUTO_GPMC_MASK |
430 OMAP24XX_AUTO_SDMA, 430 OMAP24XX_AUTO_SDMA_MASK,
431 CORE_MOD, CM_AUTOIDLE3); 431 CORE_MOD, CM_AUTOIDLE3);
432 cm_write_mod_reg(OMAP24XX_AUTO_PKA | 432 cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
433 OMAP24XX_AUTO_AES | 433 OMAP24XX_AUTO_AES_MASK |
434 OMAP24XX_AUTO_RNG | 434 OMAP24XX_AUTO_RNG_MASK |
435 OMAP24XX_AUTO_SHA | 435 OMAP24XX_AUTO_SHA_MASK |
436 OMAP24XX_AUTO_DES, 436 OMAP24XX_AUTO_DES_MASK,
437 CORE_MOD, OMAP24XX_CM_AUTOIDLE4); 437 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
438 438
439 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE); 439 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
440 CM_AUTOIDLE);
440 441
441 /* Put DPLL and both APLLs into autoidle mode */ 442 /* Put DPLL and both APLLs into autoidle mode */
442 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | 443 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
@@ -444,12 +445,12 @@ static void __init prcm_setup_regs(void)
444 (0x03 << OMAP24XX_AUTO_54M_SHIFT), 445 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
445 PLL_MOD, CM_AUTOIDLE); 446 PLL_MOD, CM_AUTOIDLE);
446 447
447 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL | 448 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
448 OMAP24XX_AUTO_WDT1 | 449 OMAP24XX_AUTO_WDT1_MASK |
449 OMAP24XX_AUTO_MPU_WDT | 450 OMAP24XX_AUTO_MPU_WDT_MASK |
450 OMAP24XX_AUTO_GPIOS | 451 OMAP24XX_AUTO_GPIOS_MASK |
451 OMAP24XX_AUTO_32KSYNC | 452 OMAP24XX_AUTO_32KSYNC_MASK |
452 OMAP24XX_AUTO_GPT1, 453 OMAP24XX_AUTO_GPT1_MASK,
453 WKUP_MOD, CM_AUTOIDLE); 454 WKUP_MOD, CM_AUTOIDLE);
454 455
455 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk 456 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
@@ -460,9 +461,9 @@ static void __init prcm_setup_regs(void)
460 /* Configure automatic voltage transition */ 461 /* Configure automatic voltage transition */
461 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, 462 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
462 OMAP2_PRCM_VOLTSETUP_OFFSET); 463 OMAP2_PRCM_VOLTSETUP_OFFSET);
463 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT | 464 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
464 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | 465 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
465 OMAP24XX_MEMRETCTRL | 466 OMAP24XX_MEMRETCTRL_MASK |
466 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | 467 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
467 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), 468 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
468 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); 469 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 4002051c20b9..0b188ffa710e 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -19,14 +19,14 @@
19/* Bits shared between registers */ 19/* Bits shared between registers */
20 20
21/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ 21/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
22#define OMAP24XX_VOLTTRANS_ST (1 << 2) 22#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2)
23#define OMAP24XX_WKUP2_ST (1 << 1) 23#define OMAP24XX_WKUP2_ST_MASK (1 << 1)
24#define OMAP24XX_WKUP1_ST (1 << 0) 24#define OMAP24XX_WKUP1_ST_MASK (1 << 0)
25 25
26/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ 26/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
27#define OMAP24XX_VOLTTRANS_EN (1 << 2) 27#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2)
28#define OMAP24XX_WKUP2_EN (1 << 1) 28#define OMAP24XX_WKUP2_EN_MASK (1 << 1)
29#define OMAP24XX_WKUP1_EN (1 << 0) 29#define OMAP24XX_WKUP1_EN_MASK (1 << 0)
30 30
31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ 31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
32#define OMAP24XX_EN_MPU_SHIFT 1 32#define OMAP24XX_EN_MPU_SHIFT 1
@@ -40,16 +40,16 @@
40 */ 40 */
41#define OMAP24XX_MEMONSTATE_SHIFT 10 41#define OMAP24XX_MEMONSTATE_SHIFT 10
42#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) 42#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
43#define OMAP24XX_MEMRETSTATE (1 << 3) 43#define OMAP24XX_MEMRETSTATE_MASK (1 << 3)
44 44
45/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ 45/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
46#define OMAP24XX_FORCESTATE (1 << 18) 46#define OMAP24XX_FORCESTATE_MASK (1 << 18)
47 47
48/* 48/*
49 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, 49 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
50 * PM_PWSTST_MDM shared bits 50 * PM_PWSTST_MDM shared bits
51 */ 51 */
52#define OMAP24XX_CLKACTIVITY (1 << 19) 52#define OMAP24XX_CLKACTIVITY_MASK (1 << 19)
53 53
54/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ 54/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
55#define OMAP24XX_LASTSTATEENTERED_SHIFT 4 55#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
@@ -71,26 +71,26 @@
71#define OMAP24XX_REV_MASK (0xff << 0) 71#define OMAP24XX_REV_MASK (0xff << 0)
72 72
73/* PRCM_SYSCONFIG */ 73/* PRCM_SYSCONFIG */
74#define OMAP24XX_AUTOIDLE (1 << 0) 74#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
75 75
76/* PRCM_IRQSTATUS_MPU specific bits */ 76/* PRCM_IRQSTATUS_MPU specific bits */
77#define OMAP2430_DPLL_RECAL_ST (1 << 6) 77#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6)
78#define OMAP24XX_TRANSITION_ST (1 << 5) 78#define OMAP24XX_TRANSITION_ST_MASK (1 << 5)
79#define OMAP24XX_EVGENOFF_ST (1 << 4) 79#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4)
80#define OMAP24XX_EVGENON_ST (1 << 3) 80#define OMAP24XX_EVGENON_ST_MASK (1 << 3)
81 81
82/* PRCM_IRQENABLE_MPU specific bits */ 82/* PRCM_IRQENABLE_MPU specific bits */
83#define OMAP2430_DPLL_RECAL_EN (1 << 6) 83#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6)
84#define OMAP24XX_TRANSITION_EN (1 << 5) 84#define OMAP24XX_TRANSITION_EN_MASK (1 << 5)
85#define OMAP24XX_EVGENOFF_EN (1 << 4) 85#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4)
86#define OMAP24XX_EVGENON_EN (1 << 3) 86#define OMAP24XX_EVGENON_EN_MASK (1 << 3)
87 87
88/* PRCM_VOLTCTRL */ 88/* PRCM_VOLTCTRL */
89#define OMAP24XX_AUTO_EXTVOLT (1 << 15) 89#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
90#define OMAP24XX_FORCE_EXTVOLT (1 << 14) 90#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14)
91#define OMAP24XX_SETOFF_LEVEL_SHIFT 12 91#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
92#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) 92#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
93#define OMAP24XX_MEMRETCTRL (1 << 8) 93#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
94#define OMAP24XX_SETRET_LEVEL_SHIFT 6 94#define OMAP24XX_SETRET_LEVEL_SHIFT 6
95#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) 95#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
96#define OMAP24XX_VOLT_LEVEL_SHIFT 0 96#define OMAP24XX_VOLT_LEVEL_SHIFT 0
@@ -104,13 +104,13 @@
104 104
105/* PRCM_CLKOUT_CTRL */ 105/* PRCM_CLKOUT_CTRL */
106#define OMAP2420_CLKOUT2_EN_SHIFT 15 106#define OMAP2420_CLKOUT2_EN_SHIFT 15
107#define OMAP2420_CLKOUT2_EN (1 << 15) 107#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
108#define OMAP2420_CLKOUT2_DIV_SHIFT 11 108#define OMAP2420_CLKOUT2_DIV_SHIFT 11
109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) 109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
110#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 110#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
111#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) 111#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
112#define OMAP24XX_CLKOUT_EN_SHIFT 7 112#define OMAP24XX_CLKOUT_EN_SHIFT 7
113#define OMAP24XX_CLKOUT_EN (1 << 7) 113#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
114#define OMAP24XX_CLKOUT_DIV_SHIFT 3 114#define OMAP24XX_CLKOUT_DIV_SHIFT 3
115#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) 115#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
116#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 116#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
@@ -118,25 +118,25 @@
118 118
119/* PRCM_CLKEMUL_CTRL */ 119/* PRCM_CLKEMUL_CTRL */
120#define OMAP24XX_EMULATION_EN_SHIFT 0 120#define OMAP24XX_EMULATION_EN_SHIFT 0
121#define OMAP24XX_EMULATION_EN (1 << 0) 121#define OMAP24XX_EMULATION_EN_MASK (1 << 0)
122 122
123/* PRCM_CLKCFG_CTRL */ 123/* PRCM_CLKCFG_CTRL */
124#define OMAP24XX_VALID_CONFIG (1 << 0) 124#define OMAP24XX_VALID_CONFIG_MASK (1 << 0)
125 125
126/* PRCM_CLKCFG_STATUS */ 126/* PRCM_CLKCFG_STATUS */
127#define OMAP24XX_CONFIG_STATUS (1 << 0) 127#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0)
128 128
129/* PRCM_VOLTSETUP specific bits */ 129/* PRCM_VOLTSETUP specific bits */
130 130
131/* PRCM_CLKSSETUP specific bits */ 131/* PRCM_CLKSSETUP specific bits */
132 132
133/* PRCM_POLCTRL */ 133/* PRCM_POLCTRL */
134#define OMAP2420_CLKOUT2_POL (1 << 10) 134#define OMAP2420_CLKOUT2_POL_MASK (1 << 10)
135#define OMAP24XX_CLKOUT_POL (1 << 9) 135#define OMAP24XX_CLKOUT_POL_MASK (1 << 9)
136#define OMAP24XX_CLKREQ_POL (1 << 8) 136#define OMAP24XX_CLKREQ_POL_MASK (1 << 8)
137#define OMAP2430_USE_POWEROK (1 << 2) 137#define OMAP2430_USE_POWEROK_MASK (1 << 2)
138#define OMAP2430_POWEROK_POL (1 << 1) 138#define OMAP2430_POWEROK_POL_MASK (1 << 1)
139#define OMAP24XX_EXTVOL_POL (1 << 0) 139#define OMAP24XX_EXTVOL_POL_MASK (1 << 0)
140 140
141/* RM_RSTST_MPU specific bits */ 141/* RM_RSTST_MPU specific bits */
142/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ 142/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
@@ -154,7 +154,7 @@
154/* PM_EVEGENOFFTIM_MPU specific bits */ 154/* PM_EVEGENOFFTIM_MPU specific bits */
155 155
156/* PM_PWSTCTRL_MPU specific bits */ 156/* PM_PWSTCTRL_MPU specific bits */
157#define OMAP2430_FORCESTATE (1 << 18) 157#define OMAP2430_FORCESTATE_MASK (1 << 18)
158 158
159/* PM_PWSTST_MPU specific bits */ 159/* PM_PWSTST_MPU specific bits */
160/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ 160/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
@@ -168,21 +168,21 @@
168/* PM_WKST2_CORE specific bits */ 168/* PM_WKST2_CORE specific bits */
169 169
170/* PM_WKDEP_CORE specific bits*/ 170/* PM_WKDEP_CORE specific bits*/
171#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5) 171#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5)
172#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3) 172#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3)
173#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2) 173#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2)
174 174
175/* PM_PWSTCTRL_CORE specific bits */ 175/* PM_PWSTCTRL_CORE specific bits */
176#define OMAP24XX_MEMORYCHANGE (1 << 20) 176#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20)
177#define OMAP24XX_MEM3ONSTATE_SHIFT 14 177#define OMAP24XX_MEM3ONSTATE_SHIFT 14
178#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) 178#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
179#define OMAP24XX_MEM2ONSTATE_SHIFT 12 179#define OMAP24XX_MEM2ONSTATE_SHIFT 12
180#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) 180#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
181#define OMAP24XX_MEM1ONSTATE_SHIFT 10 181#define OMAP24XX_MEM1ONSTATE_SHIFT 10
182#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) 182#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
183#define OMAP24XX_MEM3RETSTATE (1 << 5) 183#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5)
184#define OMAP24XX_MEM2RETSTATE (1 << 4) 184#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4)
185#define OMAP24XX_MEM1RETSTATE (1 << 3) 185#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3)
186 186
187/* PM_PWSTST_CORE specific bits */ 187/* PM_PWSTST_CORE specific bits */
188#define OMAP24XX_MEM3STATEST_SHIFT 14 188#define OMAP24XX_MEM3STATEST_SHIFT 14
@@ -193,10 +193,10 @@
193#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) 193#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
194 194
195/* RM_RSTCTRL_GFX */ 195/* RM_RSTCTRL_GFX */
196#define OMAP24XX_GFX_RST (1 << 0) 196#define OMAP24XX_GFX_RST_MASK (1 << 0)
197 197
198/* RM_RSTST_GFX specific bits */ 198/* RM_RSTST_GFX specific bits */
199#define OMAP24XX_GFX_SW_RST (1 << 4) 199#define OMAP24XX_GFX_SW_RST_MASK (1 << 4)
200 200
201/* PM_PWSTCTRL_GFX specific bits */ 201/* PM_PWSTCTRL_GFX specific bits */
202 202
@@ -209,25 +209,25 @@
209 209
210/* RM_RSTST_WKUP specific bits */ 210/* RM_RSTST_WKUP specific bits */
211/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ 211/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
212#define OMAP24XX_EXTWMPU_RST (1 << 6) 212#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6)
213#define OMAP24XX_SECU_WD_RST (1 << 5) 213#define OMAP24XX_SECU_WD_RST_MASK (1 << 5)
214#define OMAP24XX_MPU_WD_RST (1 << 4) 214#define OMAP24XX_MPU_WD_RST_MASK (1 << 4)
215#define OMAP24XX_SECU_VIOL_RST (1 << 3) 215#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3)
216 216
217/* PM_WKEN_WKUP specific bits */ 217/* PM_WKEN_WKUP specific bits */
218 218
219/* PM_WKST_WKUP specific bits */ 219/* PM_WKST_WKUP specific bits */
220 220
221/* RM_RSTCTRL_DSP */ 221/* RM_RSTCTRL_DSP */
222#define OMAP2420_RST_IVA (1 << 8) 222#define OMAP2420_RST_IVA_MASK (1 << 8)
223#define OMAP24XX_RST2_DSP (1 << 1) 223#define OMAP24XX_RST2_DSP_MASK (1 << 1)
224#define OMAP24XX_RST1_DSP (1 << 0) 224#define OMAP24XX_RST1_DSP_MASK (1 << 0)
225 225
226/* RM_RSTST_DSP specific bits */ 226/* RM_RSTST_DSP specific bits */
227/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ 227/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
228#define OMAP2420_IVA_SW_RST (1 << 8) 228#define OMAP2420_IVA_SW_RST_MASK (1 << 8)
229#define OMAP24XX_DSP_SW_RST2 (1 << 5) 229#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5)
230#define OMAP24XX_DSP_SW_RST1 (1 << 4) 230#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4)
231 231
232/* PM_WKDEP_DSP specific bits */ 232/* PM_WKDEP_DSP specific bits */
233 233
@@ -235,7 +235,7 @@
235/* 2430 only: MEMONSTATE, MEMRETSTATE */ 235/* 2430 only: MEMONSTATE, MEMRETSTATE */
236#define OMAP2420_MEMIONSTATE_SHIFT 12 236#define OMAP2420_MEMIONSTATE_SHIFT 12
237#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) 237#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
238#define OMAP2420_MEMIRETSTATE (1 << 4) 238#define OMAP2420_MEMIRETSTATE_MASK (1 << 4)
239 239
240/* PM_PWSTST_DSP specific bits */ 240/* PM_PWSTST_DSP specific bits */
241/* MEMSTATEST is 2430 only */ 241/* MEMSTATEST is 2430 only */
@@ -248,18 +248,18 @@
248 248
249/* RM_RSTCTRL_MDM */ 249/* RM_RSTCTRL_MDM */
250/* 2430 only */ 250/* 2430 only */
251#define OMAP2430_PWRON1_MDM (1 << 1) 251#define OMAP2430_PWRON1_MDM_MASK (1 << 1)
252#define OMAP2430_RST1_MDM (1 << 0) 252#define OMAP2430_RST1_MDM_MASK (1 << 0)
253 253
254/* RM_RSTST_MDM specific bits */ 254/* RM_RSTST_MDM specific bits */
255/* 2430 only */ 255/* 2430 only */
256#define OMAP2430_MDM_SECU_VIOL (1 << 6) 256#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6)
257#define OMAP2430_MDM_SW_PWRON1 (1 << 5) 257#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5)
258#define OMAP2430_MDM_SW_RST1 (1 << 4) 258#define OMAP2430_MDM_SW_RST1_MASK (1 << 4)
259 259
260/* PM_WKEN_MDM */ 260/* PM_WKEN_MDM */
261/* 2430 only */ 261/* 2430 only */
262#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0) 262#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0)
263 263
264/* PM_WKST_MDM specific bits */ 264/* PM_WKST_MDM specific bits */
265/* 2430 only */ 265/* 2430 only */
@@ -269,7 +269,7 @@
269 269
270/* PM_PWSTCTRL_MDM specific bits */ 270/* PM_PWSTCTRL_MDM specific bits */
271/* 2430 only */ 271/* 2430 only */
272#define OMAP2430_KILLDOMAINWKUP (1 << 19) 272#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19)
273 273
274/* PM_PWSTST_MDM specific bits */ 274/* PM_PWSTST_MDM specific bits */
275/* 2430 only */ 275/* 2430 only */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 18:15:51 -0500