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-rw-r--r--arch/arm/mach-omap2/Kconfig11
-rw-r--r--arch/arm/mach-omap2/Makefile1
-rw-r--r--arch/arm/mach-omap2/gpmc.c5
-rw-r--r--arch/arm/mach-omap2/io.c126
-rw-r--r--arch/arm/mach-omap2/irq.c2
-rw-r--r--arch/arm/mach-omap2/memory.c14
-rw-r--r--arch/arm/mach-omap2/mux.c67
-rw-r--r--arch/arm/mach-omap2/sram34xx.S179
8 files changed, 371 insertions, 34 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7069c9d536f1..e2481e4045e7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,8 +15,17 @@ config ARCH_OMAP2430
15 bool "OMAP2430 support" 15 bool "OMAP2430 support"
16 depends on ARCH_OMAP24XX 16 depends on ARCH_OMAP24XX
17 17
18config ARCH_OMAP34XX
19 bool "OMAP34xx Based System"
20 depends on ARCH_OMAP3
21
22config ARCH_OMAP3430
23 bool "OMAP3430 support"
24 depends on ARCH_OMAP3 && ARCH_OMAP34XX
25 select ARCH_OMAP_OTG
26
18comment "OMAP Board Type" 27comment "OMAP Board Type"
19 depends on ARCH_OMAP2 28 depends on ARCH_OMAP2 || ARCH_OMAP3
20 29
21config MACH_OMAP_GENERIC 30config MACH_OMAP_GENERIC
22 bool "Generic OMAP board" 31 bool "Generic OMAP board"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 800639e7c6a4..0dc40db38119 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
12# Functions loaded to SRAM 12# Functions loaded to SRAM
13obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o 13obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o 14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
15obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
15 16
16# Power Management 17# Power Management
17ifeq ($(CONFIG_PM),y) 18ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 149bfba43cfe..375ad27479cc 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -220,6 +220,11 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
220 220
221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); 221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
222 222
223 if (cpu_is_omap34xx()) {
224 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
225 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
226 }
227
223 /* caller is expected to have initialized CONFIG1 to cover 228 /* caller is expected to have initialized CONFIG1 to cover
224 * at least sync vs async 229 * at least sync vs async
225 */ 230 */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 03c6ab1a3b1f..71a9de382d2d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -43,7 +43,9 @@
43 * The machine specific code may provide the extra mapping besides the 43 * The machine specific code may provide the extra mapping besides the
44 * default mapping provided here. 44 * default mapping provided here.
45 */ 45 */
46static struct map_desc omap2_io_desc[] __initdata = { 46
47#ifdef CONFIG_ARCH_OMAP24XX
48static struct map_desc omap24xx_io_desc[] __initdata = {
47 { 49 {
48 .virtual = L3_24XX_VIRT, 50 .virtual = L3_24XX_VIRT,
49 .pfn = __phys_to_pfn(L3_24XX_PHYS), 51 .pfn = __phys_to_pfn(L3_24XX_PHYS),
@@ -51,12 +53,39 @@ static struct map_desc omap2_io_desc[] __initdata = {
51 .type = MT_DEVICE 53 .type = MT_DEVICE
52 }, 54 },
53 { 55 {
54 .virtual = L4_24XX_VIRT, 56 .virtual = L4_24XX_VIRT,
55 .pfn = __phys_to_pfn(L4_24XX_PHYS), 57 .pfn = __phys_to_pfn(L4_24XX_PHYS),
56 .length = L4_24XX_SIZE, 58 .length = L4_24XX_SIZE,
57 .type = MT_DEVICE 59 .type = MT_DEVICE
60 },
61};
62
63#ifdef CONFIG_ARCH_OMAP2420
64static struct map_desc omap242x_io_desc[] __initdata = {
65 {
66 .virtual = DSP_MEM_24XX_VIRT,
67 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
68 .length = DSP_MEM_24XX_SIZE,
69 .type = MT_DEVICE
70 },
71 {
72 .virtual = DSP_IPI_24XX_VIRT,
73 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
74 .length = DSP_IPI_24XX_SIZE,
75 .type = MT_DEVICE
58 }, 76 },
77 {
78 .virtual = DSP_MMU_24XX_VIRT,
79 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
80 .length = DSP_MMU_24XX_SIZE,
81 .type = MT_DEVICE
82 },
83};
84
85#endif
86
59#ifdef CONFIG_ARCH_OMAP2430 87#ifdef CONFIG_ARCH_OMAP2430
88static struct map_desc omap243x_io_desc[] __initdata = {
60 { 89 {
61 .virtual = L4_WK_243X_VIRT, 90 .virtual = L4_WK_243X_VIRT,
62 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 91 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
@@ -69,30 +98,90 @@ static struct map_desc omap2_io_desc[] __initdata = {
69 .length = OMAP243X_GPMC_SIZE, 98 .length = OMAP243X_GPMC_SIZE,
70 .type = MT_DEVICE 99 .type = MT_DEVICE
71 }, 100 },
101 {
102 .virtual = OMAP243X_SDRC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
104 .length = OMAP243X_SDRC_SIZE,
105 .type = MT_DEVICE
106 },
107 {
108 .virtual = OMAP243X_SMS_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
110 .length = OMAP243X_SMS_SIZE,
111 .type = MT_DEVICE
112 },
113};
72#endif 114#endif
115#endif
116
117#ifdef CONFIG_ARCH_OMAP34XX
118static struct map_desc omap34xx_io_desc[] __initdata = {
73 { 119 {
74 .virtual = DSP_MEM_24XX_VIRT, 120 .virtual = L3_34XX_VIRT,
75 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS), 121 .pfn = __phys_to_pfn(L3_34XX_PHYS),
76 .length = DSP_MEM_24XX_SIZE, 122 .length = L3_34XX_SIZE,
77 .type = MT_DEVICE 123 .type = MT_DEVICE
78 }, 124 },
79 { 125 {
80 .virtual = DSP_IPI_24XX_VIRT, 126 .virtual = L4_34XX_VIRT,
81 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS), 127 .pfn = __phys_to_pfn(L4_34XX_PHYS),
82 .length = DSP_IPI_24XX_SIZE, 128 .length = L4_34XX_SIZE,
83 .type = MT_DEVICE 129 .type = MT_DEVICE
84 }, 130 },
85 { 131 {
86 .virtual = DSP_MMU_24XX_VIRT, 132 .virtual = L4_WK_34XX_VIRT,
87 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS), 133 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
88 .length = DSP_MMU_24XX_SIZE, 134 .length = L4_WK_34XX_SIZE,
135 .type = MT_DEVICE
136 },
137 {
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
141 .type = MT_DEVICE
142 },
143 {
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
147 .type = MT_DEVICE
148 },
149 {
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
89 .type = MT_DEVICE 153 .type = MT_DEVICE
90 } 154 },
155 {
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
159 .type = MT_DEVICE
160 },
161 {
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
165 .type = MT_DEVICE
166 },
91}; 167};
168#endif
92 169
93void __init omap2_map_common_io(void) 170void __init omap2_map_common_io(void)
94{ 171{
95 iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc)); 172#if defined(CONFIG_ARCH_OMAP2420)
173 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
174 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
175#endif
176
177#if defined(CONFIG_ARCH_OMAP2430)
178 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
179 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
180#endif
181
182#if defined(CONFIG_ARCH_OMAP34XX)
183 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
184#endif
96 185
97 /* Normally devicemaps_init() would flush caches and tlb after 186 /* Normally devicemaps_init() would flush caches and tlb after
98 * mdesc->map_io(), but we must also do it here because of the CPU 187 * mdesc->map_io(), but we must also do it here because of the CPU
@@ -112,11 +201,6 @@ void __init omap2_init_common_hw(void)
112 pwrdm_init(powerdomains_omap); 201 pwrdm_init(powerdomains_omap);
113 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); 202 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
114 omap2_clk_init(); 203 omap2_clk_init();
115/*
116 * Need to Fix this for 2430
117 */
118#ifndef CONFIG_ARCH_OMAP2430
119 omap2_init_memory(); 204 omap2_init_memory();
120#endif
121 gpmc_init(); 205 gpmc_init();
122} 206}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index c39e26dc5ee3..d354e0fe4477 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -128,6 +128,8 @@ void __init omap_init_irq(void)
128 128
129 if (cpu_is_omap24xx()) 129 if (cpu_is_omap24xx())
130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE); 130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
131 else if (cpu_is_omap34xx())
132 bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
131 133
132 omap_irq_bank_init_one(bank); 134 omap_irq_bank_init_one(bank);
133 135
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 6b49cc9cbdcb..48b01f4cebc5 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -102,6 +102,17 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
102 return prev; 102 return prev;
103} 103}
104 104
105#if !defined(CONFIG_ARCH_OMAP2)
106void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
107 u32 base_cs, u32 force_unlock)
108{
109}
110void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
111 u32 mem_type)
112{
113}
114#endif
115
105void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 116void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
106{ 117{
107 unsigned long dll_cnt; 118 unsigned long dll_cnt;
@@ -166,6 +177,9 @@ void __init omap2_init_memory(void)
166{ 177{
167 u32 l; 178 u32 l;
168 179
180 if (!cpu_is_omap2420())
181 return;
182
169 l = sms_read_reg(SMS_SYSCONFIG); 183 l = sms_read_reg(SMS_SYSCONFIG);
170 l &= ~(0x3 << 3); 184 l &= ~(0x3 << 3);
171 l |= (0x2 << 3); 185 l |= (0x2 << 3);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 6188e2f97854..5558803cd99e 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -298,13 +298,13 @@ MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
298 298
299/* TLL - HSUSB: 12-pin TLL Port 1*/ 299/* TLL - HSUSB: 12-pin TLL Port 1*/
300MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da, 300MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
301 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
302MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
303 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 301 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
302MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
303 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
304MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec, 304MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
305 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 305 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
306MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee, 306MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
307 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 307 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
308MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc, 308MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
309 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 309 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
310MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de, 310MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
@@ -324,13 +324,13 @@ MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
324 324
325/* TLL - HSUSB: 12-pin TLL Port 2*/ 325/* TLL - HSUSB: 12-pin TLL Port 2*/
326MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0, 326MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
327 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
328MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
329 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 327 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
328MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
329 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
330MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4, 330MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
331 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 331 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
332MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6, 332MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
333 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 333 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
334MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8, 334MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
335 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 335 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
336MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa, 336MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
@@ -350,13 +350,13 @@ MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
350 350
351/* TLL - HSUSB: 12-pin TLL Port 3*/ 351/* TLL - HSUSB: 12-pin TLL Port 3*/
352MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180, 352MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
353 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
354MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
355 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 353 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
354MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
355 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
356MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168, 356MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
357 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) 357 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
358MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a, 358MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
359 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) 359 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
360MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186, 360MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
361 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 361 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
362MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184, 362MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
@@ -373,6 +373,49 @@ MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
373 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 373 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
374MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172, 374MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
375 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 375 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
376
377/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
378MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
379 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
380MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
381 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
382MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
383 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
384MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
385 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
386MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
387 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
388MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
389 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
390
391/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
392MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
393 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
394MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
395 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
396MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
397 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
398MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
399 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
400MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
401 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
402MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
403 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
404
405/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
406MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
407 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
408MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
409 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
410MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
411 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
412MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
413 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
414MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
415 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
416MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
417 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
418
376}; 419};
377 420
378#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) 421#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
new file mode 100644
index 000000000000..2c7146136342
--- /dev/null
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -0,0 +1,179 @@
1/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2007
7 * Texas Instruments Inc.
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * (C) Copyright 2004
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29#include <linux/linkage.h>
30#include <asm/assembler.h>
31#include <mach/hardware.h>
32
33#include <mach/io.h>
34
35#include "sdrc.h"
36#include "cm.h"
37
38 .text
39
40/*
41 * Change frequency of core dpll
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
43 */
44ENTRY(omap3_sram_configure_core_dpll)
45 stmfd sp!, {r1-r12, lr} @ store regs to stack
46 cmp r3, #0x2
47 blne configure_sdrc
48 cmp r3, #0x2
49 blne lock_dll
50 cmp r3, #0x1
51 blne unlock_dll
52 bl sdram_in_selfrefresh @ put the SDRAM in self refresh
53 bl configure_core_dpll
54 bl enable_sdrc
55 cmp r3, #0x1
56 blne wait_dll_unlock
57 cmp r3, #0x2
58 blne wait_dll_lock
59 cmp r3, #0x1
60 blne configure_sdrc
61 mov r0, #0 @ return value
62 ldmfd sp!, {r1-r12, pc} @ restore regs and return
63unlock_dll:
64 ldr r4, omap3_sdrc_dlla_ctrl
65 ldr r5, [r4]
66 orr r5, r5, #0x4
67 str r5, [r4]
68 bx lr
69lock_dll:
70 ldr r4, omap3_sdrc_dlla_ctrl
71 ldr r5, [r4]
72 bic r5, r5, #0x4
73 str r5, [r4]
74 bx lr
75sdram_in_selfrefresh:
76 mov r5, #0x0 @ Move 0 to R5
77 mcr p15, 0, r5, c7, c10, 5 @ memory barrier
78 ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
79 ldr r5, [r4] @ read the contents of SDRC_POWER
80 orr r5, r5, #0x40 @ enable self refresh on idle req
81 str r5, [r4] @ write back to SDRC_POWER register
82 ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
83 ldr r5, [r4]
84 bic r5, r5, #0x2 @ disable iclk bit for SRDC
85 str r5, [r4]
86wait_sdrc_idle:
87 ldr r4, omap3_cm_idlest1_core
88 ldr r5, [r4]
89 and r5, r5, #0x2 @ check for SDRC idle
90 cmp r5, #2
91 bne wait_sdrc_idle
92 bx lr
93configure_core_dpll:
94 ldr r4, omap3_cm_clksel1_pll
95 ldr r5, [r4]
96 ldr r6, core_m2_mask_val @ modify m2 for core dpll
97 and r5, r5, r6
98 orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
99 str r5, [r4]
100 mov r5, #0x800 @ wait for the clock to stabilise
101 cmp r3, #2
102 bne wait_clk_stable
103 bx lr
104wait_clk_stable:
105 subs r5, r5, #1
106 bne wait_clk_stable
107 nop
108 nop
109 nop
110 nop
111 nop
112 nop
113 nop
114 nop
115 nop
116 nop
117 bx lr
118enable_sdrc:
119 ldr r4, omap3_cm_iclken1_core
120 ldr r5, [r4]
121 orr r5, r5, #0x2 @ enable iclk bit for SDRC
122 str r5, [r4]
123wait_sdrc_idle1:
124 ldr r4, omap3_cm_idlest1_core
125 ldr r5, [r4]
126 and r5, r5, #0x2
127 cmp r5, #0
128 bne wait_sdrc_idle1
129 ldr r4, omap3_sdrc_power
130 ldr r5, [r4]
131 bic r5, r5, #0x40
132 str r5, [r4]
133 bx lr
134wait_dll_lock:
135 ldr r4, omap3_sdrc_dlla_status
136 ldr r5, [r4]
137 and r5, r5, #0x4
138 cmp r5, #0x4
139 bne wait_dll_lock
140 bx lr
141wait_dll_unlock:
142 ldr r4, omap3_sdrc_dlla_status
143 ldr r5, [r4]
144 and r5, r5, #0x4
145 cmp r5, #0x0
146 bne wait_dll_unlock
147 bx lr
148configure_sdrc:
149 ldr r4, omap3_sdrc_rfr_ctrl
150 str r0, [r4]
151 ldr r4, omap3_sdrc_actim_ctrla
152 str r1, [r4]
153 ldr r4, omap3_sdrc_actim_ctrlb
154 str r2, [r4]
155 bx lr
156
157omap3_sdrc_power:
158 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
159omap3_cm_clksel1_pll:
160 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
161omap3_cm_idlest1_core:
162 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
163omap3_cm_iclken1_core:
164 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
165omap3_sdrc_rfr_ctrl:
166 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
167omap3_sdrc_actim_ctrla:
168 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
169omap3_sdrc_actim_ctrlb:
170 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
171omap3_sdrc_dlla_status:
172 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
173omap3_sdrc_dlla_ctrl:
174 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
175core_m2_mask_val:
176 .word 0x07FFFFFF
177
178ENTRY(omap3_sram_configure_core_dpll_sz)
179 .word . - omap3_sram_configure_core_dpll
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 09:19:01 -0500