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-rw-r--r--arch/arm/mach-omap2/clock.c79
-rw-r--r--arch/arm/mach-omap2/clock.h37
-rw-r--r--arch/arm/mach-omap2/memory.c102
-rw-r--r--arch/arm/mach-omap2/memory.h34
-rw-r--r--arch/arm/mach-omap2/prcm-regs.h (renamed from arch/arm/mach-omap2/prcm.h)188
-rw-r--r--arch/arm/mach-omap2/prcm.c40
6 files changed, 335 insertions, 145 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 180f675c9064..72eb4bf571ac 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -28,14 +28,14 @@
28 28
29#include <asm/arch/clock.h> 29#include <asm/arch/clock.h>
30#include <asm/arch/sram.h> 30#include <asm/arch/sram.h>
31#include <asm/arch/prcm.h>
32 31
32#include "prcm-regs.h"
33#include "memory.h"
33#include "clock.h" 34#include "clock.h"
34 35
35//#define DOWN_VARIABLE_DPLL 1 /* Experimental */ 36//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
36 37
37static struct prcm_config *curr_prcm_set; 38static struct prcm_config *curr_prcm_set;
38static struct memory_timings mem_timings;
39static u32 curr_perf_level = PRCM_FULL_SPEED; 39static u32 curr_perf_level = PRCM_FULL_SPEED;
40 40
41/*------------------------------------------------------------------------- 41/*-------------------------------------------------------------------------
@@ -54,11 +54,13 @@ static void omap2_sys_clk_recalc(struct clk * clk)
54 54
55static u32 omap2_get_dpll_rate(struct clk * tclk) 55static u32 omap2_get_dpll_rate(struct clk * tclk)
56{ 56{
57 int dpll_clk, dpll_mult, dpll_div, amult; 57 long long dpll_clk;
58 int dpll_mult, dpll_div, amult;
58 59
59 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ 60 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
60 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */ 61 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
61 dpll_clk = (tclk->parent->rate * dpll_mult) / (dpll_div + 1); 62 dpll_clk = (long long)tclk->parent->rate * dpll_mult;
63 do_div(dpll_clk, dpll_div + 1);
62 amult = CM_CLKSEL2_PLL & 0x3; 64 amult = CM_CLKSEL2_PLL & 0x3;
63 dpll_clk *= amult; 65 dpll_clk *= amult;
64 66
@@ -385,75 +387,23 @@ static u32 omap2_dll_force_needed(void)
385 return 0; 387 return 0;
386} 388}
387 389
388static void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
389{
390 unsigned long dll_cnt;
391 u32 fast_dll = 0;
392
393 mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
394
395 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
396 * In the case of 2422, its ok to use CS1 instead of CS0.
397 */
398
399#if 0 /* FIXME: Enable after 24xx cpu detection works */
400 ctype = get_cpu_type();
401 if (cpu_is_omap2422())
402 mem_timings.base_cs = 1;
403 else
404#endif
405 mem_timings.base_cs = 0;
406
407 if (mem_timings.m_type != M_DDR)
408 return;
409
410 /* With DDR we need to determine the low frequency DLL value */
411 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
412 mem_timings.dll_mode = M_UNLOCK;
413 else
414 mem_timings.dll_mode = M_LOCK;
415
416 if (mem_timings.base_cs == 0) {
417 fast_dll = SDRC_DLLA_CTRL;
418 dll_cnt = SDRC_DLLA_STATUS & 0xff00;
419 } else {
420 fast_dll = SDRC_DLLB_CTRL;
421 dll_cnt = SDRC_DLLB_STATUS & 0xff00;
422 }
423 if (force_lock_to_unlock_mode) {
424 fast_dll &= ~0xff00;
425 fast_dll |= dll_cnt; /* Current lock mode */
426 }
427 mem_timings.fast_dll_ctrl = fast_dll;
428
429 /* No disruptions, DDR will be offline & C-ABI not followed */
430 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
431 mem_timings.fast_dll_ctrl,
432 mem_timings.base_cs,
433 force_lock_to_unlock_mode);
434 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
435
436 /* Turn status into unlock ctrl */
437 mem_timings.slow_dll_ctrl |=
438 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
439
440 /* 90 degree phase for anything below 133Mhz */
441 mem_timings.slow_dll_ctrl |= (1 << 1);
442}
443
444static u32 omap2_reprogram_sdrc(u32 level, u32 force) 390static u32 omap2_reprogram_sdrc(u32 level, u32 force)
445{ 391{
392 u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
446 u32 prev = curr_perf_level, flags; 393 u32 prev = curr_perf_level, flags;
447 394
448 if ((curr_perf_level == level) && !force) 395 if ((curr_perf_level == level) && !force)
449 return prev; 396 return prev;
450 397
398 m_type = omap2_memory_get_type();
399 slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
400 fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
401
451 if (level == PRCM_HALF_SPEED) { 402 if (level == PRCM_HALF_SPEED) {
452 local_irq_save(flags); 403 local_irq_save(flags);
453 PRCM_VOLTSETUP = 0xffff; 404 PRCM_VOLTSETUP = 0xffff;
454 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED, 405 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
455 mem_timings.slow_dll_ctrl, 406 slow_dll_ctrl, m_type);
456 mem_timings.m_type);
457 curr_perf_level = PRCM_HALF_SPEED; 407 curr_perf_level = PRCM_HALF_SPEED;
458 local_irq_restore(flags); 408 local_irq_restore(flags);
459 } 409 }
@@ -461,8 +411,7 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force)
461 local_irq_save(flags); 411 local_irq_save(flags);
462 PRCM_VOLTSETUP = 0xffff; 412 PRCM_VOLTSETUP = 0xffff;
463 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED, 413 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
464 mem_timings.fast_dll_ctrl, 414 fast_dll_ctrl, m_type);
465 mem_timings.m_type);
466 curr_perf_level = PRCM_FULL_SPEED; 415 curr_perf_level = PRCM_FULL_SPEED;
467 local_irq_restore(flags); 416 local_irq_restore(flags);
468 } 417 }
@@ -650,7 +599,7 @@ static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
650 case 13: /* dss2 */ 599 case 13: /* dss2 */
651 mask = 0x1; break; 600 mask = 0x1; break;
652 case 25: /* usb */ 601 case 25: /* usb */
653 mask = 0xf; break; 602 mask = 0x7; break;
654 } 603 }
655 } 604 }
656 605
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 6cab20b1d3c1..6c78d471fab7 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -33,20 +33,6 @@ static u32 omap2_clksel_get_divisor(struct clk *clk);
33#define RATE_IN_242X (1 << 0) 33#define RATE_IN_242X (1 << 0)
34#define RATE_IN_243X (1 << 1) 34#define RATE_IN_243X (1 << 1)
35 35
36/* Memory timings */
37#define M_DDR 1
38#define M_LOCK_CTRL (1 << 2)
39#define M_UNLOCK 0
40#define M_LOCK 1
41
42struct memory_timings {
43 u32 m_type; /* ddr = 1, sdr = 0 */
44 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
45 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
46 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
47 u32 base_cs; /* base chip select to use for calculations */
48};
49
50/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 36/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
51 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
52 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM 38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
@@ -731,6 +717,16 @@ static struct clk sys_clkout2 = {
731 .recalc = &omap2_clksel_recalc, 717 .recalc = &omap2_clksel_recalc,
732}; 718};
733 719
720static struct clk emul_ck = {
721 .name = "emul_ck",
722 .parent = &func_54m_ck,
723 .flags = CLOCK_IN_OMAP242X,
724 .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
725 .enable_bit = 0,
726 .recalc = &omap2_propagate_rate,
727
728};
729
734/* 730/*
735 * MPU clock domain 731 * MPU clock domain
736 * Clocks: 732 * Clocks:
@@ -1702,7 +1698,8 @@ static struct clk hdq_fck = {
1702}; 1698};
1703 1699
1704static struct clk i2c2_ick = { 1700static struct clk i2c2_ick = {
1705 .name = "i2c2_ick", 1701 .name = "i2c_ick",
1702 .id = 2,
1706 .parent = &l4_ck, 1703 .parent = &l4_ck,
1707 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1704 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1708 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1705 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1711,7 +1708,8 @@ static struct clk i2c2_ick = {
1711}; 1708};
1712 1709
1713static struct clk i2c2_fck = { 1710static struct clk i2c2_fck = {
1714 .name = "i2c2_fck", 1711 .name = "i2c_fck",
1712 .id = 2,
1715 .parent = &func_12m_ck, 1713 .parent = &func_12m_ck,
1716 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1717 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1715 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1729,7 +1727,8 @@ static struct clk i2chs2_fck = {
1729}; 1727};
1730 1728
1731static struct clk i2c1_ick = { 1729static struct clk i2c1_ick = {
1732 .name = "i2c1_ick", 1730 .name = "i2c_ick",
1731 .id = 1,
1733 .parent = &l4_ck, 1732 .parent = &l4_ck,
1734 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1733 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1735 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1734 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1738,7 +1737,8 @@ static struct clk i2c1_ick = {
1738}; 1737};
1739 1738
1740static struct clk i2c1_fck = { 1739static struct clk i2c1_fck = {
1741 .name = "i2c1_fck", 1740 .name = "i2c_fck",
1741 .id = 1,
1742 .parent = &func_12m_ck, 1742 .parent = &func_12m_ck,
1743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1744 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1744 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1971,6 +1971,7 @@ static struct clk *onchip_clks[] = {
1971 &wdt1_osc_ck, 1971 &wdt1_osc_ck,
1972 &sys_clkout, 1972 &sys_clkout,
1973 &sys_clkout2, 1973 &sys_clkout2,
1974 &emul_ck,
1974 /* mpu domain clocks */ 1975 /* mpu domain clocks */
1975 &mpu_ck, 1976 &mpu_ck,
1976 /* dsp domain clocks */ 1977 /* dsp domain clocks */
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
new file mode 100644
index 000000000000..1d925d69fc35
--- /dev/null
+++ b/arch/arm/mach-omap2/memory.c
@@ -0,0 +1,102 @@
1/*
2 * linux/arch/arm/mach-omap2/memory.c
3 *
4 * Memory timing related functions for OMAP24XX
5 *
6 * Copyright (C) 2005 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/config.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/list.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25
26#include <asm/io.h>
27
28#include <asm/arch/clock.h>
29#include <asm/arch/sram.h>
30
31#include "prcm-regs.h"
32#include "memory.h"
33
34static struct memory_timings mem_timings;
35
36u32 omap2_memory_get_slow_dll_ctrl(void)
37{
38 return mem_timings.slow_dll_ctrl;
39}
40
41u32 omap2_memory_get_fast_dll_ctrl(void)
42{
43 return mem_timings.fast_dll_ctrl;
44}
45
46u32 omap2_memory_get_type(void)
47{
48 return mem_timings.m_type;
49}
50
51void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
52{
53 unsigned long dll_cnt;
54 u32 fast_dll = 0;
55
56 mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
57
58 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
59 * In the case of 2422, its ok to use CS1 instead of CS0.
60 */
61 if (cpu_is_omap2422())
62 mem_timings.base_cs = 1;
63 else
64 mem_timings.base_cs = 0;
65
66 if (mem_timings.m_type != M_DDR)
67 return;
68
69 /* With DDR we need to determine the low frequency DLL value */
70 if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
71 mem_timings.dll_mode = M_UNLOCK;
72 else
73 mem_timings.dll_mode = M_LOCK;
74
75 if (mem_timings.base_cs == 0) {
76 fast_dll = SDRC_DLLA_CTRL;
77 dll_cnt = SDRC_DLLA_STATUS & 0xff00;
78 } else {
79 fast_dll = SDRC_DLLB_CTRL;
80 dll_cnt = SDRC_DLLB_STATUS & 0xff00;
81 }
82 if (force_lock_to_unlock_mode) {
83 fast_dll &= ~0xff00;
84 fast_dll |= dll_cnt; /* Current lock mode */
85 }
86 /* set fast timings with DLL filter disabled */
87 mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
88
89 /* No disruptions, DDR will be offline & C-ABI not followed */
90 omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
91 mem_timings.fast_dll_ctrl,
92 mem_timings.base_cs,
93 force_lock_to_unlock_mode);
94 mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
95
96 /* Turn status into unlock ctrl */
97 mem_timings.slow_dll_ctrl |=
98 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
99
100 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
101 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
102}
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
new file mode 100644
index 000000000000..d212eea83a05
--- /dev/null
+++ b/arch/arm/mach-omap2/memory.h
@@ -0,0 +1,34 @@
1/*
2 * linux/arch/arm/mach-omap2/memory.h
3 *
4 * Interface for memory timing related functions for OMAP24XX
5 *
6 * Copyright (C) 2005 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17/* Memory timings */
18#define M_DDR 1
19#define M_LOCK_CTRL (1 << 2)
20#define M_UNLOCK 0
21#define M_LOCK 1
22
23struct memory_timings {
24 u32 m_type; /* ddr = 1, sdr = 0 */
25 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
26 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
27 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
28 u32 base_cs; /* base chip select to use for calculations */
29};
30
31extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
32extern u32 omap2_memory_get_slow_dll_ctrl(void);
33extern u32 omap2_memory_get_fast_dll_ctrl(void);
34extern u32 omap2_memory_get_type(void);
diff --git a/arch/arm/mach-omap2/prcm.h b/arch/arm/mach-omap2/prcm-regs.h
index 2eb89b936c83..22ac7be4f782 100644
--- a/arch/arm/mach-omap2/prcm.h
+++ b/arch/arm/mach-omap2/prcm-regs.h
@@ -1,5 +1,7 @@
1/* 1/*
2 * prcm.h - Access definations for use in OMAP24XX clock and power management 2 * linux/arch/arm/mach-omap2/prcm-reg.h
3 *
4 * OMAP24XX Power Reset and Clock Management (PRCM) registers
3 * 5 *
4 * Copyright (C) 2005 Texas Instruments, Inc. 6 * Copyright (C) 2005 Texas Instruments, Inc.
5 * 7 *
@@ -18,8 +20,8 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 21 */
20 22
21#ifndef __ASM_ARM_ARCH_DPM_PRCM_H 23#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
22#define __ASM_ARM_ARCH_DPM_PRCM_H 24#define __ARCH_ARM_MACH_OMAP2_PRCM_H
23 25
24/* SET_PERFORMANCE_LEVEL PARAMETERS */ 26/* SET_PERFORMANCE_LEVEL PARAMETERS */
25#define PRCM_HALF_SPEED 1 27#define PRCM_HALF_SPEED 1
@@ -159,54 +161,63 @@
159#define CM_FCLKEN_MDM PRCM_REG32(0xC00) 161#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
160#define CM_ICLKEN_MDM PRCM_REG32(0xC10) 162#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
161#define CM_IDLEST_MDM PRCM_REG32(0xC20) 163#define CM_IDLEST_MDM PRCM_REG32(0xC20)
164#define CM_AUTOIDLE_MDM PRCM_REG32(0xC30)
162#define CM_CLKSEL_MDM PRCM_REG32(0xC40) 165#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
163 166#define CM_CLKSTCTRL_MDM PRCM_REG32(0xC48)
164/* FIXME: Move to header for 2430 */ 167#define RM_RSTCTRL_MDM PRCM_REG32(0xC50)
165#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000) 168#define RM_RSTST_MDM PRCM_REG32(0xC58)
169#define PM_WKEN_MDM PRCM_REG32(0xCA0)
170#define PM_WKST_MDM PRCM_REG32(0xCB0)
171#define PM_WKDEP_MDM PRCM_REG32(0xCC8)
172#define PM_PWSTCTRL_MDM PRCM_REG32(0xCE0)
173#define PM_PWSTST_MDM PRCM_REG32(0xCE4)
174
175#define OMAP24XX_L4_IO_BASE 0x48000000
176
177#define DISP_BASE (OMAP24XX_L4_IO_BASE + 0x50000)
166#define DISP_REG32(offset) __REG32(DISP_BASE + (offset)) 178#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
167 179
168#define GPMC_BASE (OMAP24XX_GPMC_BASE) 180#define OMAP24XX_GPMC_BASE (L3_24XX_BASE + 0xa000)
169#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset)) 181#define GPMC_REG32(offset) __REG32(OMAP24XX_GPMC_BASE + (offset))
170 182
171#define GPT1_BASE (OMAP24XX_GPT1) 183/* FIXME: Move these to timer code */
184#define GPT1_BASE (0x48028000)
172#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset)) 185#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
173 186
174/* Misc sysconfig */ 187/* Misc sysconfig */
175#define DISPC_SYSCONFIG DISP_REG32(0x410) 188#define DISPC_SYSCONFIG DISP_REG32(0x410)
176#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000) 189#define SPI_BASE (OMAP24XX_L4_IO_BASE + 0x98000)
177#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10) 190#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
178#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10) 191#define MCSPI2_SYSCONFIG __REG32(SPI_BASE + 0x2000 + 0x10)
179 192#define MCSPI3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0xb8010)
180//#define DSP_MMU_SYSCONFIG 0x5A000010 193
181#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10) 194#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE + 0x2C10)
182//#define IVA_MMU_SYSCONFIG 0x5D000010 195#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE + 0x282C)
183//#define DSP_DMA_SYSCONFIG 0x00FCC02C 196#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE + 0x602C)
184#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)
185#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)
186#define GPMC_SYSCONFIG GPMC_REG32(0x010) 197#define GPMC_SYSCONFIG GPMC_REG32(0x010)
187#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010) 198#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x94010)
188#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054) 199#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6A054)
189#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054) 200#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6C054)
190#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054) 201#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE + 0x6E054)
191//#define IVA_SYSCONFIG 0x5C060010 202#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE + 0x10)
192#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10) 203#define OMAP24XX_SMS_BASE (L3_24XX_BASE + 0x8000)
193#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10) 204#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE + 0x10)
194#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010) 205#define SSI_SYSCONFIG __REG32(DISP_BASE + 0x8010)
195//#define VLYNQ_SYSCONFIG 0x67FFFE10
196 206
197/* rkw - good cannidates for PM_ to start what nm was trying */ 207/* rkw - good cannidates for PM_ to start what nm was trying */
198#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) 208#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE + 0x2A000)
199#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) 209#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE + 0x78000)
200#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) 210#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE + 0x7A000)
201#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) 211#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE + 0x7C000)
202#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) 212#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE + 0x7E000)
203#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) 213#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE + 0x80000)
204#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) 214#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE + 0x82000)
205#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) 215#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE + 0x84000)
206#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) 216#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE + 0x86000)
207#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) 217#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE + 0x88000)
208#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000) 218#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE + 0x8A000)
209 219
220/* FIXME: Move these to timer code */
210#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010) 221#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
211#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10) 222#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
212#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10) 223#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
@@ -220,12 +231,18 @@
220#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10) 231#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
221#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10) 232#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
222 233
223#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1))) 234/* FIXME: Move these to gpio code */
235#define OMAP24XX_GPIO_BASE 0x48018000
236#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE + (0x2000 * ((X) - 1)))
237
238#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1) + 0x10))
239#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2) + 0x10))
240#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3) + 0x10))
241#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4) + 0x10))
224 242
225#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10)) 243#if defined(CONFIG_ARCH_OMAP243X)
226#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10)) 244#define GPIO5_SYSCONFIG __REG32((OMAP24XX_GPIO5_BASE + 0x10))
227#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10)) 245#endif
228#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10))
229 246
230/* GP TIMER 1 */ 247/* GP TIMER 1 */
231#define GPTIMER1_TISTAT GPT1_REG32(0x014) 248#define GPTIMER1_TISTAT GPT1_REG32(0x014)
@@ -243,15 +260,15 @@
243#define GPTIMER1_TCAR2 GPT1_REG32(0x044) 260#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
244 261
245/* rkw -- base fix up please... */ 262/* rkw -- base fix up please... */
246#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018) 263#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
247 264
248/* SDRC */ 265/* SDRC */
249#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060) 266#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
250#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064) 267#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
251#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068) 268#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
252#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C) 269#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
253#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070) 270#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
254#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084) 271#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
255 272
256/* GPIO 1 */ 273/* GPIO 1 */
257#define GPIO1_BASE GPIOX_BASE(1) 274#define GPIO1_BASE GPIOX_BASE(1)
@@ -278,6 +295,8 @@
278#define GPIO2_DATAIN GPIO2_REG32(0x038) 295#define GPIO2_DATAIN GPIO2_REG32(0x038)
279#define GPIO2_OE GPIO2_REG32(0x034) 296#define GPIO2_OE GPIO2_REG32(0x034)
280#define GPIO2_DATAOUT GPIO2_REG32(0x03C) 297#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
298#define GPIO2_DEBOUNCENABLE GPIO2_REG32(0x050)
299#define GPIO2_DEBOUNCINGTIME GPIO2_REG32(0x054)
281 300
282/* GPIO 3 */ 301/* GPIO 3 */
283#define GPIO3_BASE GPIOX_BASE(3) 302#define GPIO3_BASE GPIOX_BASE(3)
@@ -294,6 +313,8 @@
294#define GPIO3_DATAOUT GPIO3_REG32(0x03C) 313#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
295#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050) 314#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
296#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054) 315#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
316#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
317#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
297 318
298/* GPIO 4 */ 319/* GPIO 4 */
299#define GPIO4_BASE GPIOX_BASE(4) 320#define GPIO4_BASE GPIOX_BASE(4)
@@ -311,10 +332,26 @@
311#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050) 332#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
312#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054) 333#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
313 334
335#if defined(CONFIG_ARCH_OMAP243X)
336/* GPIO 5 */
337#define GPIO5_REG32(offset) __REG32((OMAP24XX_GPIO5_BASE + (offset)))
338#define GPIO5_IRQENABLE1 GPIO5_REG32(0x01C)
339#define GPIO5_IRQSTATUS1 GPIO5_REG32(0x018)
340#define GPIO5_IRQENABLE2 GPIO5_REG32(0x02C)
341#define GPIO5_IRQSTATUS2 GPIO5_REG32(0x028)
342#define GPIO5_WAKEUPENABLE GPIO5_REG32(0x020)
343#define GPIO5_RISINGDETECT GPIO5_REG32(0x048)
344#define GPIO5_FALLINGDETECT GPIO5_REG32(0x04C)
345#define GPIO5_DATAIN GPIO5_REG32(0x038)
346#define GPIO5_OE GPIO5_REG32(0x034)
347#define GPIO5_DATAOUT GPIO5_REG32(0x03C)
348#define GPIO5_DEBOUNCENABLE GPIO5_REG32(0x050)
349#define GPIO5_DEBOUNCINGTIME GPIO5_REG32(0x054)
350#endif
314 351
315/* IO CONFIG */ 352/* IO CONFIG */
316#define CONTROL_BASE (OMAP24XX_CTRL_BASE) 353#define OMAP24XX_CTRL_BASE (L4_24XX_BASE)
317#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset)) 354#define CONTROL_REG32(offset) __REG32(OMAP24XX_CTRL_BASE + (offset))
318 355
319#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104) 356#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
320#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134) 357#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
@@ -322,15 +359,18 @@
322#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C) 359#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
323#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090) 360#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
324#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8) 361#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
325#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) 362#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC) /* 2420 */
326#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0) 363#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
327#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC) 364#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
365#define CONTROL_PADCONF_SYS_NIRQW0 CONTROL_REG32(0x0BC) /* 2430 */
366#define CONTROL_PADCONF_SSI1_FLAG_TX CONTROL_REG32(0x108) /* 2430 */
328 367
329/* CONTROL */ 368/* CONTROL */
330#define CONTROL_DEVCONF CONTROL_REG32(0x274) 369#define CONTROL_DEVCONF CONTROL_REG32(0x274)
370#define CONTROL_DEVCONF1 CONTROL_REG32(0x2E8)
331 371
332/* INTERRUPT CONTROLLER */ 372/* INTERRUPT CONTROLLER */
333#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000) 373#define INTC_BASE ((L4_24XX_BASE) + 0xfe000)
334#define INTC_REG32(offset) __REG32(INTC_BASE + (offset)) 374#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
335 375
336#define INTC1_U_BASE INTC_REG32(0x000) 376#define INTC1_U_BASE INTC_REG32(0x000)
@@ -348,10 +388,12 @@
348#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4) 388#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
349#define INTC_SIR_IRQ INTC_REG32(0x040) 389#define INTC_SIR_IRQ INTC_REG32(0x040)
350#define INTC_CONTROL INTC_REG32(0x048) 390#define INTC_CONTROL INTC_REG32(0x048)
351#define INTC_ILR11 INTC_REG32(0x12C) 391#define INTC_ILR11 INTC_REG32(0x12C) /* PRCM on MPU PIC */
392#define INTC_ILR30 INTC_REG32(0x178)
393#define INTC_ILR31 INTC_REG32(0x17C)
352#define INTC_ILR32 INTC_REG32(0x180) 394#define INTC_ILR32 INTC_REG32(0x180)
353#define INTC_ILR37 INTC_REG32(0x194) 395#define INTC_ILR37 INTC_REG32(0x194) /* GPIO4 on MPU PIC */
354#define INTC_SYSCONFIG INTC_REG32(0x010) 396#define INTC_SYSCONFIG INTC_REG32(0x010) /* GPT1 on MPU PIC */
355 397
356/* RAM FIREWALL */ 398/* RAM FIREWALL */
357#define RAMFW_BASE (0x68005000) 399#define RAMFW_BASE (0x68005000)
@@ -373,6 +415,24 @@
373#define GPMC_CONFIG6_0 GPMC_REG32(0x074) 415#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
374#define GPMC_CONFIG7_0 GPMC_REG32(0x078) 416#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
375 417
418/* GPMC CS1 */
419#define GPMC_CONFIG1_1 GPMC_REG32(0x090)
420#define GPMC_CONFIG2_1 GPMC_REG32(0x094)
421#define GPMC_CONFIG3_1 GPMC_REG32(0x098)
422#define GPMC_CONFIG4_1 GPMC_REG32(0x09C)
423#define GPMC_CONFIG5_1 GPMC_REG32(0x0a0)
424#define GPMC_CONFIG6_1 GPMC_REG32(0x0a4)
425#define GPMC_CONFIG7_1 GPMC_REG32(0x0a8)
426
427/* GPMC CS3 */
428#define GPMC_CONFIG1_3 GPMC_REG32(0x0F0)
429#define GPMC_CONFIG2_3 GPMC_REG32(0x0F4)
430#define GPMC_CONFIG3_3 GPMC_REG32(0x0F8)
431#define GPMC_CONFIG4_3 GPMC_REG32(0x0FC)
432#define GPMC_CONFIG5_3 GPMC_REG32(0x100)
433#define GPMC_CONFIG6_3 GPMC_REG32(0x104)
434#define GPMC_CONFIG7_3 GPMC_REG32(0x108)
435
376/* DSS */ 436/* DSS */
377#define DSS_CONTROL DISP_REG32(0x040) 437#define DSS_CONTROL DISP_REG32(0x040)
378#define DISPC_CONTROL DISP_REG32(0x440) 438#define DISPC_CONTROL DISP_REG32(0x440)
@@ -405,11 +465,15 @@
405#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8) 465#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
406#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC) 466#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
407 467
408/* Wake up define for board */ 468/* HSUSB Suspend */
409#define GPIO97 (1 << 1) 469#define HSUSB_CTRL __REG8(0x480AC001)
410#define GPIO88 (1 << 24) 470#define USBOTG_POWER __REG32(0x480AC000)
471
472/* HS MMC */
473#define MMCHS1_SYSCONFIG __REG32(0x4809C010)
474#define MMCHS2_SYSCONFIG __REG32(0x480b4010)
411 475
412#endif /* __ASSEMBLER__ */ 476#endif /* __ASSEMBLER__ */
413 477
414#endif 478#endif
415 479
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
new file mode 100644
index 000000000000..8893479dc7e0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm.c
@@ -0,0 +1,40 @@
1/*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/config.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20
21#include "prcm-regs.h"
22
23u32 omap_prcm_get_reset_sources(void)
24{
25 return RM_RSTST_WKUP & 0x7f;
26}
27EXPORT_SYMBOL(omap_prcm_get_reset_sources);
28
29/* Resets clock rates and reboots the system. Only called from system.h */
30void omap_prcm_arch_reset(char mode)
31{
32 u32 rate;
33 struct clk *vclk, *sclk;
34
35 vclk = clk_get(NULL, "virt_prcm_set");
36 sclk = clk_get(NULL, "sys_ck");
37 rate = clk_get_rate(sclk);
38 clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
39 RM_RSTCTRL_WKUP |= 2;
40}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 12:44:56 -0500