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-rw-r--r--arch/arm/mach-omap2/Kconfig4
-rw-r--r--arch/arm/mach-omap2/Makefile14
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c52
-rw-r--r--arch/arm/mach-omap2/board-apollon.c26
-rw-r--r--arch/arm/mach-omap2/board-generic.c11
-rw-r--r--arch/arm/mach-omap2/board-h4.c25
-rw-r--r--arch/arm/mach-omap2/board-ldp.c97
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c90
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c212
-rw-r--r--arch/arm/mach-omap2/board-overo.c43
-rw-r--r--arch/arm/mach-omap2/clock24xx.h9
-rw-r--r--arch/arm/mach-omap2/clock34xx.c2
-rw-r--r--arch/arm/mach-omap2/clock34xx.h46
-rw-r--r--arch/arm/mach-omap2/devices.c169
-rw-r--r--arch/arm/mach-omap2/id.c305
-rw-r--r--arch/arm/mach-omap2/irq.c39
-rw-r--r--arch/arm/mach-omap2/mmc-twl4030.c408
-rw-r--r--arch/arm/mach-omap2/mmc-twl4030.h29
-rw-r--r--arch/arm/mach-omap2/mux.c44
-rw-r--r--arch/arm/mach-omap2/timer-gp.c2
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c6
21 files changed, 1377 insertions, 256 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4832fcc7d04a..3754b79092ab 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -55,3 +55,7 @@ config MACH_OMAP_LDP
55config MACH_OVERO 55config MACH_OVERO
56 bool "Gumstix Overo board" 56 bool "Gumstix Overo board"
57 depends on ARCH_OMAP3 && ARCH_OMAP34XX 57 depends on ARCH_OMAP3 && ARCH_OMAP34XX
58
59config MACH_OMAP3_PANDORA
60 bool "OMAP3 Pandora"
61 depends on ARCH_OMAP3 && ARCH_OMAP34XX \ No newline at end of file
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index c69392372c99..bbd12bc10fdc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -27,9 +27,15 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
27# Specific board support 27# Specific board support
28obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 28obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
29obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 29obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
30obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o 30obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \
31 mmc-twl4030.o
31obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o 32obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
32obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o 33obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \
33obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o 34 mmc-twl4030.o
34obj-$(CONFIG_MACH_OVERO) += board-overo.o 35obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \
36 mmc-twl4030.o
37obj-$(CONFIG_MACH_OVERO) += board-overo.o \
38 mmc-twl4030.o
39obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \
40 mmc-twl4030.o
35 41
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 24688efaa445..83fa37211d77 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -19,6 +19,7 @@
19#include <linux/mtd/mtd.h> 19#include <linux/mtd/mtd.h>
20#include <linux/mtd/partitions.h> 20#include <linux/mtd/partitions.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/i2c/twl4030.h>
22#include <linux/err.h> 23#include <linux/err.h>
23#include <linux/clk.h> 24#include <linux/clk.h>
24#include <linux/io.h> 25#include <linux/io.h>
@@ -35,6 +36,7 @@
35#include <mach/common.h> 36#include <mach/common.h>
36#include <mach/gpmc.h> 37#include <mach/gpmc.h>
37 38
39#include "mmc-twl4030.h"
38 40
39#define SDP2430_FLASH_CS 0 41#define SDP2430_FLASH_CS 0
40#define SDP2430_SMC91X_CS 5 42#define SDP2430_SMC91X_CS 5
@@ -168,13 +170,13 @@ static inline void __init sdp2430_init_smc91x(void)
168 sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; 170 sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f;
169 udelay(100); 171 udelay(100);
170 172
171 if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) { 173 if (gpio_request(OMAP24XX_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
172 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", 174 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
173 OMAP24XX_ETHR_GPIO_IRQ); 175 OMAP24XX_ETHR_GPIO_IRQ);
174 gpmc_cs_free(eth_cs); 176 gpmc_cs_free(eth_cs);
175 goto out; 177 goto out;
176 } 178 }
177 omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); 179 gpio_direction_input(OMAP24XX_ETHR_GPIO_IRQ);
178 180
179out: 181out:
180 clk_disable(gpmc_fck); 182 clk_disable(gpmc_fck);
@@ -197,12 +199,58 @@ static struct omap_board_config_kernel sdp2430_config[] = {
197 {OMAP_TAG_UART, &sdp2430_uart_config}, 199 {OMAP_TAG_UART, &sdp2430_uart_config},
198}; 200};
199 201
202
203static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
204 .gpio_base = OMAP_MAX_GPIO_LINES,
205 .irq_base = TWL4030_GPIO_IRQ_BASE,
206 .irq_end = TWL4030_GPIO_IRQ_END,
207};
208
209static struct twl4030_platform_data sdp2430_twldata = {
210 .irq_base = TWL4030_IRQ_BASE,
211 .irq_end = TWL4030_IRQ_END,
212
213 /* platform_data for children goes here */
214 .gpio = &sdp2430_gpio_data,
215};
216
217static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
218 {
219 I2C_BOARD_INFO("twl4030", 0x48),
220 .flags = I2C_CLIENT_WAKE,
221 .irq = INT_24XX_SYS_NIRQ,
222 .platform_data = &sdp2430_twldata,
223 },
224};
225
226static int __init omap2430_i2c_init(void)
227{
228 omap_register_i2c_bus(1, 400, NULL, 0);
229 omap_register_i2c_bus(2, 2600, sdp2430_i2c_boardinfo,
230 ARRAY_SIZE(sdp2430_i2c_boardinfo));
231 return 0;
232}
233
234static struct twl4030_hsmmc_info mmc[] __initdata = {
235 {
236 .mmc = 1,
237 .wires = 4,
238 .gpio_cd = -EINVAL,
239 .gpio_wp = -EINVAL,
240 .ext_clock = 1,
241 },
242 {} /* Terminator */
243};
244
200static void __init omap_2430sdp_init(void) 245static void __init omap_2430sdp_init(void)
201{ 246{
247 omap2430_i2c_init();
248
202 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); 249 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
203 omap_board_config = sdp2430_config; 250 omap_board_config = sdp2430_config;
204 omap_board_config_size = ARRAY_SIZE(sdp2430_config); 251 omap_board_config_size = ARRAY_SIZE(sdp2430_config);
205 omap_serial_init(); 252 omap_serial_init();
253 twl4030_mmc_init(mmc);
206} 254}
207 255
208static void __init omap_2430sdp_map_io(void) 256static void __init omap_2430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 989ad152d7f8..bf1e5d32c2a3 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -236,13 +236,13 @@ static inline void __init apollon_init_smc91x(void)
236 udelay(100); 236 udelay(100);
237 237
238 omap_cfg_reg(W4__24XX_GPIO74); 238 omap_cfg_reg(W4__24XX_GPIO74);
239 if (omap_request_gpio(APOLLON_ETHR_GPIO_IRQ) < 0) { 239 if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
240 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", 240 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
241 APOLLON_ETHR_GPIO_IRQ); 241 APOLLON_ETHR_GPIO_IRQ);
242 gpmc_cs_free(APOLLON_ETH_CS); 242 gpmc_cs_free(APOLLON_ETH_CS);
243 goto out; 243 goto out;
244 } 244 }
245 omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); 245 gpio_direction_input(APOLLON_ETHR_GPIO_IRQ);
246 246
247out: 247out:
248 clk_disable(gpmc_fck); 248 clk_disable(gpmc_fck);
@@ -261,16 +261,6 @@ static struct omap_uart_config apollon_uart_config __initdata = {
261 .enabled_uarts = (1 << 0) | (0 << 1) | (0 << 2), 261 .enabled_uarts = (1 << 0) | (0 << 1) | (0 << 2),
262}; 262};
263 263
264static struct omap_mmc_config apollon_mmc_config __initdata = {
265 .mmc [0] = {
266 .enabled = 1,
267 .wire4 = 1,
268 .wp_pin = -1,
269 .power_pin = -1,
270 .switch_pin = -1,
271 },
272};
273
274static struct omap_usb_config apollon_usb_config __initdata = { 264static struct omap_usb_config apollon_usb_config __initdata = {
275 .register_dev = 1, 265 .register_dev = 1,
276 .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */ 266 .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */
@@ -284,7 +274,6 @@ static struct omap_lcd_config apollon_lcd_config __initdata = {
284 274
285static struct omap_board_config_kernel apollon_config[] = { 275static struct omap_board_config_kernel apollon_config[] = {
286 { OMAP_TAG_UART, &apollon_uart_config }, 276 { OMAP_TAG_UART, &apollon_uart_config },
287 { OMAP_TAG_MMC, &apollon_mmc_config },
288 { OMAP_TAG_USB, &apollon_usb_config }, 277 { OMAP_TAG_USB, &apollon_usb_config },
289 { OMAP_TAG_LCD, &apollon_lcd_config }, 278 { OMAP_TAG_LCD, &apollon_lcd_config },
290}; 279};
@@ -327,15 +316,15 @@ static void __init apollon_sw_init(void)
327 /* Enter SW - Y11 */ 316 /* Enter SW - Y11 */
328 omap_cfg_reg(Y11_242X_GPIO16); 317 omap_cfg_reg(Y11_242X_GPIO16);
329 omap_request_gpio(SW_ENTER_GPIO16); 318 omap_request_gpio(SW_ENTER_GPIO16);
330 omap_set_gpio_direction(SW_ENTER_GPIO16, 1); 319 gpio_direction_input(SW_ENTER_GPIO16);
331 /* Up SW - AA12 */ 320 /* Up SW - AA12 */
332 omap_cfg_reg(AA12_242X_GPIO17); 321 omap_cfg_reg(AA12_242X_GPIO17);
333 omap_request_gpio(SW_UP_GPIO17); 322 omap_request_gpio(SW_UP_GPIO17);
334 omap_set_gpio_direction(SW_UP_GPIO17, 1); 323 gpio_direction_input(SW_UP_GPIO17);
335 /* Down SW - AA8 */ 324 /* Down SW - AA8 */
336 omap_cfg_reg(AA8_242X_GPIO58); 325 omap_cfg_reg(AA8_242X_GPIO58);
337 omap_request_gpio(SW_DOWN_GPIO58); 326 omap_request_gpio(SW_DOWN_GPIO58);
338 omap_set_gpio_direction(SW_DOWN_GPIO58, 1); 327 gpio_direction_input(SW_DOWN_GPIO58);
339 328
340 set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQ_TYPE_EDGE_RISING); 329 set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQ_TYPE_EDGE_RISING);
341 if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt, 330 if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt,
@@ -359,9 +348,8 @@ static void __init apollon_usb_init(void)
359 /* USB device */ 348 /* USB device */
360 /* DEVICE_SUSPEND */ 349 /* DEVICE_SUSPEND */
361 omap_cfg_reg(P21_242X_GPIO12); 350 omap_cfg_reg(P21_242X_GPIO12);
362 omap_request_gpio(12); 351 gpio_request(12, "USB suspend");
363 omap_set_gpio_direction(12, 0); /* OUT */ 352 gpio_direction_output(12, 0);
364 omap_set_gpio_dataout(12, 0);
365} 353}
366 354
367static void __init omap_apollon_init(void) 355static void __init omap_apollon_init(void)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 9ba097868e72..3b34c20d1df4 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -41,19 +41,8 @@ static struct omap_uart_config generic_uart_config __initdata = {
41 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 41 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
42}; 42};
43 43
44static struct omap_mmc_config generic_mmc_config __initdata = {
45 .mmc [0] = {
46 .enabled = 0,
47 .wire4 = 0,
48 .wp_pin = -1,
49 .power_pin = -1,
50 .switch_pin = -1,
51 },
52};
53
54static struct omap_board_config_kernel generic_config[] = { 44static struct omap_board_config_kernel generic_config[] = {
55 { OMAP_TAG_UART, &generic_uart_config }, 45 { OMAP_TAG_UART, &generic_uart_config },
56 { OMAP_TAG_MMC, &generic_mmc_config },
57}; 46};
58 47
59static void __init omap_generic_init(void) 48static void __init omap_generic_init(void)
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 2fef2c845083..5e9b14675b1e 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -19,6 +19,7 @@
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/workqueue.h> 20#include <linux/workqueue.h>
21#include <linux/i2c.h> 21#include <linux/i2c.h>
22#include <linux/i2c/at24.h>
22#include <linux/input.h> 23#include <linux/input.h>
23#include <linux/err.h> 24#include <linux/err.h>
24#include <linux/clk.h> 25#include <linux/clk.h>
@@ -372,31 +373,33 @@ static struct omap_uart_config h4_uart_config __initdata = {
372 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 373 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
373}; 374};
374 375
375static struct omap_mmc_config h4_mmc_config __initdata = {
376 .mmc [0] = {
377 .enabled = 1,
378 .wire4 = 1,
379 .wp_pin = -1,
380 .power_pin = -1,
381 .switch_pin = -1,
382 },
383};
384
385static struct omap_lcd_config h4_lcd_config __initdata = { 376static struct omap_lcd_config h4_lcd_config __initdata = {
386 .ctrl_name = "internal", 377 .ctrl_name = "internal",
387}; 378};
388 379
389static struct omap_board_config_kernel h4_config[] = { 380static struct omap_board_config_kernel h4_config[] = {
390 { OMAP_TAG_UART, &h4_uart_config }, 381 { OMAP_TAG_UART, &h4_uart_config },
391 { OMAP_TAG_MMC, &h4_mmc_config },
392 { OMAP_TAG_LCD, &h4_lcd_config }, 382 { OMAP_TAG_LCD, &h4_lcd_config },
393}; 383};
394 384
385static struct at24_platform_data m24c01 = {
386 .byte_len = SZ_1K / 8,
387 .page_size = 16,
388};
389
395static struct i2c_board_info __initdata h4_i2c_board_info[] = { 390static struct i2c_board_info __initdata h4_i2c_board_info[] = {
396 { 391 {
397 I2C_BOARD_INFO("isp1301_omap", 0x2d), 392 I2C_BOARD_INFO("isp1301_omap", 0x2d),
398 .irq = OMAP_GPIO_IRQ(125), 393 .irq = OMAP_GPIO_IRQ(125),
399 }, 394 },
395 { /* EEPROM on mainboard */
396 I2C_BOARD_INFO("24c01", 0x52),
397 .platform_data = &m24c01,
398 },
399 { /* EEPROM on cpu card */
400 I2C_BOARD_INFO("24c01", 0x57),
401 .platform_data = &m24c01,
402 },
400}; 403};
401 404
402static void __init omap_h4_init(void) 405static void __init omap_h4_init(void)
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 1ea59986aa7a..aa6972781e4a 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -21,6 +21,7 @@
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
23#include <linux/spi/ads7846.h> 23#include <linux/spi/ads7846.h>
24#include <linux/i2c/twl4030.h>
24 25
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <asm/mach-types.h> 27#include <asm/mach-types.h>
@@ -38,11 +39,69 @@
38#include <asm/delay.h> 39#include <asm/delay.h>
39#include <mach/control.h> 40#include <mach/control.h>
40 41
42#include "mmc-twl4030.h"
43
44#define SDP3430_SMC91X_CS 3
45
46static struct resource ldp_smc911x_resources[] = {
47 [0] = {
48 .start = OMAP34XX_ETHR_START,
49 .end = OMAP34XX_ETHR_START + SZ_4K,
50 .flags = IORESOURCE_MEM,
51 },
52 [1] = {
53 .start = 0,
54 .end = 0,
55 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
56 },
57};
58
59static struct platform_device ldp_smc911x_device = {
60 .name = "smc911x",
61 .id = -1,
62 .num_resources = ARRAY_SIZE(ldp_smc911x_resources),
63 .resource = ldp_smc911x_resources,
64};
65
66static struct platform_device *ldp_devices[] __initdata = {
67 &ldp_smc911x_device,
68};
69
70static inline void __init ldp_init_smc911x(void)
71{
72 int eth_cs;
73 unsigned long cs_mem_base;
74 int eth_gpio = 0;
75
76 eth_cs = LDP_SMC911X_CS;
77
78 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
79 printk(KERN_ERR "Failed to request GPMC mem for smc911x\n");
80 return;
81 }
82
83 ldp_smc911x_resources[0].start = cs_mem_base + 0x0;
84 ldp_smc911x_resources[0].end = cs_mem_base + 0xf;
85 udelay(100);
86
87 eth_gpio = LDP_SMC911X_GPIO;
88
89 ldp_smc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
90
91 if (omap_request_gpio(eth_gpio) < 0) {
92 printk(KERN_ERR "Failed to request GPIO%d for smc911x IRQ\n",
93 eth_gpio);
94 return;
95 }
96 gpio_direction_input(eth_gpio);
97}
98
41static void __init omap_ldp_init_irq(void) 99static void __init omap_ldp_init_irq(void)
42{ 100{
43 omap2_init_common_hw(); 101 omap2_init_common_hw();
44 omap_init_irq(); 102 omap_init_irq();
45 omap_gpio_init(); 103 omap_gpio_init();
104 ldp_init_smc911x();
46} 105}
47 106
48static struct omap_uart_config ldp_uart_config __initdata = { 107static struct omap_uart_config ldp_uart_config __initdata = {
@@ -53,20 +112,56 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
53 { OMAP_TAG_UART, &ldp_uart_config }, 112 { OMAP_TAG_UART, &ldp_uart_config },
54}; 113};
55 114
115static struct twl4030_gpio_platform_data ldp_gpio_data = {
116 .gpio_base = OMAP_MAX_GPIO_LINES,
117 .irq_base = TWL4030_GPIO_IRQ_BASE,
118 .irq_end = TWL4030_GPIO_IRQ_END,
119};
120
121static struct twl4030_platform_data ldp_twldata = {
122 .irq_base = TWL4030_IRQ_BASE,
123 .irq_end = TWL4030_IRQ_END,
124
125 /* platform_data for children goes here */
126 .gpio = &ldp_gpio_data,
127};
128
129static struct i2c_board_info __initdata ldp_i2c_boardinfo[] = {
130 {
131 I2C_BOARD_INFO("twl4030", 0x48),
132 .flags = I2C_CLIENT_WAKE,
133 .irq = INT_34XX_SYS_NIRQ,
134 .platform_data = &ldp_twldata,
135 },
136};
137
56static int __init omap_i2c_init(void) 138static int __init omap_i2c_init(void)
57{ 139{
58 omap_register_i2c_bus(1, 2600, NULL, 0); 140 omap_register_i2c_bus(1, 2600, ldp_i2c_boardinfo,
141 ARRAY_SIZE(ldp_i2c_boardinfo));
59 omap_register_i2c_bus(2, 400, NULL, 0); 142 omap_register_i2c_bus(2, 400, NULL, 0);
60 omap_register_i2c_bus(3, 400, NULL, 0); 143 omap_register_i2c_bus(3, 400, NULL, 0);
61 return 0; 144 return 0;
62} 145}
63 146
147static struct twl4030_hsmmc_info mmc[] __initdata = {
148 {
149 .mmc = 1,
150 .wires = 4,
151 .gpio_cd = -EINVAL,
152 .gpio_wp = -EINVAL,
153 },
154 {} /* Terminator */
155};
156
64static void __init omap_ldp_init(void) 157static void __init omap_ldp_init(void)
65{ 158{
66 omap_i2c_init(); 159 omap_i2c_init();
160 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
67 omap_board_config = ldp_config; 161 omap_board_config = ldp_config;
68 omap_board_config_size = ARRAY_SIZE(ldp_config); 162 omap_board_config_size = ARRAY_SIZE(ldp_config);
69 omap_serial_init(); 163 omap_serial_init();
164 twl4030_mmc_init(mmc);
70} 165}
71 166
72static void __init omap_ldp_map_io(void) 167static void __init omap_ldp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index baa79674e9d5..9e5ada01b5fa 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -38,7 +38,9 @@
38#include <mach/common.h> 38#include <mach/common.h>
39#include <mach/gpmc.h> 39#include <mach/gpmc.h>
40#include <mach/nand.h> 40#include <mach/nand.h>
41#include <mach/mux.h>
41 42
43#include "mmc-twl4030.h"
42 44
43#define GPMC_CS0_BASE 0x60 45#define GPMC_CS0_BASE 0x60
44#define GPMC_CS_SIZE 0x30 46#define GPMC_CS_SIZE 0x30
@@ -103,6 +105,78 @@ static struct omap_uart_config omap3_beagle_uart_config __initdata = {
103 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 105 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
104}; 106};
105 107
108static struct twl4030_hsmmc_info mmc[] = {
109 {
110 .mmc = 1,
111 .wires = 8,
112 .gpio_wp = 29,
113 },
114 {} /* Terminator */
115};
116
117static struct gpio_led gpio_leds[];
118
119static int beagle_twl_gpio_setup(struct device *dev,
120 unsigned gpio, unsigned ngpio)
121{
122 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
123
124 /* REVISIT: need ehci-omap hooks for external VBUS
125 * power switch and overcurrent detect
126 */
127
128 gpio_request(gpio + 1, "EHCI_nOC");
129 gpio_direction_input(gpio + 1);
130
131 /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
132 gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
133 gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1);
134
135 /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
136 gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
137
138 return 0;
139}
140
141static struct twl4030_gpio_platform_data beagle_gpio_data = {
142 .gpio_base = OMAP_MAX_GPIO_LINES,
143 .irq_base = TWL4030_GPIO_IRQ_BASE,
144 .irq_end = TWL4030_GPIO_IRQ_END,
145 .use_leds = true,
146 .pullups = BIT(1),
147 .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
148 | BIT(15) | BIT(16) | BIT(17),
149 .setup = beagle_twl_gpio_setup,
150};
151
152static struct twl4030_platform_data beagle_twldata = {
153 .irq_base = TWL4030_IRQ_BASE,
154 .irq_end = TWL4030_IRQ_END,
155
156 /* platform_data for children goes here */
157 .gpio = &beagle_gpio_data,
158};
159
160static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = {
161 {
162 I2C_BOARD_INFO("twl4030", 0x48),
163 .flags = I2C_CLIENT_WAKE,
164 .irq = INT_34XX_SYS_NIRQ,
165 .platform_data = &beagle_twldata,
166 },
167};
168
169static int __init omap3_beagle_i2c_init(void)
170{
171 omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo,
172 ARRAY_SIZE(beagle_i2c_boardinfo));
173#ifdef CONFIG_I2C2_OMAP_BEAGLE
174 omap_register_i2c_bus(2, 400, NULL, 0);
175#endif
176 omap_register_i2c_bus(3, 400, NULL, 0);
177 return 0;
178}
179
106static void __init omap3_beagle_init_irq(void) 180static void __init omap3_beagle_init_irq(void)
107{ 181{
108 omap2_init_common_hw(); 182 omap2_init_common_hw();
@@ -130,6 +204,11 @@ static struct gpio_led gpio_leds[] = {
130 .default_trigger = "mmc0", 204 .default_trigger = "mmc0",
131 .gpio = 149, 205 .gpio = 149,
132 }, 206 },
207 {
208 .name = "beagleboard::pmu_stat",
209 .gpio = -EINVAL, /* gets replaced */
210 .active_low = true,
211 },
133}; 212};
134 213
135static struct gpio_led_platform_data gpio_led_info = { 214static struct gpio_led_platform_data gpio_led_info = {
@@ -218,11 +297,22 @@ static void __init omap3beagle_flash_init(void)
218 297
219static void __init omap3_beagle_init(void) 298static void __init omap3_beagle_init(void)
220{ 299{
300 omap3_beagle_i2c_init();
221 platform_add_devices(omap3_beagle_devices, 301 platform_add_devices(omap3_beagle_devices,
222 ARRAY_SIZE(omap3_beagle_devices)); 302 ARRAY_SIZE(omap3_beagle_devices));
223 omap_board_config = omap3_beagle_config; 303 omap_board_config = omap3_beagle_config;
224 omap_board_config_size = ARRAY_SIZE(omap3_beagle_config); 304 omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
225 omap_serial_init(); 305 omap_serial_init();
306
307 omap_cfg_reg(AH8_34XX_GPIO29);
308 mmc[0].gpio_cd = gpio + 0;
309 twl4030_mmc_init(mmc);
310
311 omap_cfg_reg(J25_34XX_GPIO170);
312 gpio_request(170, "DVI_nPD");
313 /* REVISIT leave DVI powered down until it's needed ... */
314 gpio_direction_output(170, true);
315
226 omap3beagle_flash_init(); 316 omap3beagle_flash_init();
227} 317}
228 318
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
new file mode 100644
index 000000000000..b3196107afdb
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -0,0 +1,212 @@
1/*
2 * board-omap3pandora.c (Pandora Handheld Console)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
16 * 02110-1301 USA
17 *
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/platform_device.h>
23
24#include <linux/spi/spi.h>
25#include <linux/spi/ads7846.h>
26#include <linux/i2c/twl4030.h>
27
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31
32#include <mach/board.h>
33#include <mach/common.h>
34#include <mach/gpio.h>
35#include <mach/hardware.h>
36#include <mach/mcspi.h>
37
38#include "mmc-twl4030.h"
39
40#define OMAP3_PANDORA_TS_GPIO 94
41
42static struct twl4030_hsmmc_info omap3pandora_mmc[] = {
43 {
44 .mmc = 1,
45 .wires = 4,
46 .gpio_cd = -EINVAL,
47 .gpio_wp = 126,
48 .ext_clock = 0,
49 },
50 {
51 .mmc = 2,
52 .wires = 4,
53 .gpio_cd = -EINVAL,
54 .gpio_wp = 127,
55 .ext_clock = 1,
56 },
57 {} /* Terminator */
58};
59
60static struct omap_uart_config omap3pandora_uart_config __initdata = {
61 .enabled_uarts = (1 << 2), /* UART3 */
62};
63
64static int omap3pandora_twl_gpio_setup(struct device *dev,
65 unsigned gpio, unsigned ngpio)
66{
67 /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */
68 omap3pandora_mmc[0].gpio_cd = gpio + 0;
69 omap3pandora_mmc[1].gpio_cd = gpio + 1;
70 twl4030_mmc_init(omap3pandora_mmc);
71
72 return 0;
73}
74
75static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
76 .gpio_base = OMAP_MAX_GPIO_LINES,
77 .irq_base = TWL4030_GPIO_IRQ_BASE,
78 .irq_end = TWL4030_GPIO_IRQ_END,
79 .setup = omap3pandora_twl_gpio_setup,
80};
81
82static struct twl4030_usb_data omap3pandora_usb_data = {
83 .usb_mode = T2_USB_MODE_ULPI,
84};
85
86static struct twl4030_platform_data omap3pandora_twldata = {
87 .irq_base = TWL4030_IRQ_BASE,
88 .irq_end = TWL4030_IRQ_END,
89 .gpio = &omap3pandora_gpio_data,
90 .usb = &omap3pandora_usb_data,
91};
92
93static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = {
94 {
95 I2C_BOARD_INFO("tps65950", 0x48),
96 .flags = I2C_CLIENT_WAKE,
97 .irq = INT_34XX_SYS_NIRQ,
98 .platform_data = &omap3pandora_twldata,
99 },
100};
101
102static int __init omap3pandora_i2c_init(void)
103{
104 omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
105 ARRAY_SIZE(omap3pandora_i2c_boardinfo));
106 /* i2c2 pins are not connected */
107 omap_register_i2c_bus(3, 400, NULL, 0);
108 return 0;
109}
110
111static void __init omap3pandora_init_irq(void)
112{
113 omap2_init_common_hw();
114 omap_init_irq();
115 omap_gpio_init();
116}
117
118static void __init omap3pandora_ads7846_init(void)
119{
120 int gpio = OMAP3_PANDORA_TS_GPIO;
121 int ret;
122
123 ret = gpio_request(gpio, "ads7846_pen_down");
124 if (ret < 0) {
125 printk(KERN_ERR "Failed to request GPIO %d for "
126 "ads7846 pen down IRQ\n", gpio);
127 return;
128 }
129
130 gpio_direction_input(gpio);
131}
132
133static int ads7846_get_pendown_state(void)
134{
135 return !gpio_get_value(OMAP3_PANDORA_TS_GPIO);
136}
137
138static struct ads7846_platform_data ads7846_config = {
139 .x_max = 0x0fff,
140 .y_max = 0x0fff,
141 .x_plate_ohms = 180,
142 .pressure_max = 255,
143 .debounce_max = 10,
144 .debounce_tol = 3,
145 .debounce_rep = 1,
146 .get_pendown_state = ads7846_get_pendown_state,
147 .keep_vref_on = 1,
148};
149
150static struct omap2_mcspi_device_config ads7846_mcspi_config = {
151 .turbo_mode = 0,
152 .single_channel = 1, /* 0: slave, 1: master */
153};
154
155static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
156 {
157 .modalias = "ads7846",
158 .bus_num = 1,
159 .chip_select = 0,
160 .max_speed_hz = 1500000,
161 .controller_data = &ads7846_mcspi_config,
162 .irq = OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO),
163 .platform_data = &ads7846_config,
164 }
165};
166
167static struct platform_device omap3pandora_lcd_device = {
168 .name = "pandora_lcd",
169 .id = -1,
170};
171
172static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
173 .ctrl_name = "internal",
174};
175
176static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
177 { OMAP_TAG_UART, &omap3pandora_uart_config },
178 { OMAP_TAG_LCD, &omap3pandora_lcd_config },
179};
180
181static struct platform_device *omap3pandora_devices[] __initdata = {
182 &omap3pandora_lcd_device,
183};
184
185static void __init omap3pandora_init(void)
186{
187 omap3pandora_i2c_init();
188 platform_add_devices(omap3pandora_devices,
189 ARRAY_SIZE(omap3pandora_devices));
190 omap_board_config = omap3pandora_config;
191 omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
192 omap_serial_init();
193 spi_register_board_info(omap3pandora_spi_board_info,
194 ARRAY_SIZE(omap3pandora_spi_board_info));
195 omap3pandora_ads7846_init();
196}
197
198static void __init omap3pandora_map_io(void)
199{
200 omap2_set_globals_343x();
201 omap2_map_common_io();
202}
203
204MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
205 .phys_io = 0x48000000,
206 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
207 .boot_params = 0x80000100,
208 .map_io = omap3pandora_map_io,
209 .init_irq = omap3pandora_init_irq,
210 .init_machine = omap3pandora_init,
211 .timer = &omap_timer,
212MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index e09aa59a399c..82b3dc557c96 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -26,6 +26,7 @@
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
29 30
30#include <linux/mtd/mtd.h> 31#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h> 32#include <linux/mtd/nand.h>
@@ -44,6 +45,8 @@
44#include <mach/hardware.h> 45#include <mach/hardware.h>
45#include <mach/nand.h> 46#include <mach/nand.h>
46 47
48#include "mmc-twl4030.h"
49
47#define NAND_BLOCK_SIZE SZ_128K 50#define NAND_BLOCK_SIZE SZ_128K
48#define GPMC_CS0_BASE 0x60 51#define GPMC_CS0_BASE 0x60
49#define GPMC_CS_SIZE 0x30 52#define GPMC_CS_SIZE 0x30
@@ -139,8 +142,31 @@ static struct omap_uart_config overo_uart_config __initdata = {
139 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), 142 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
140}; 143};
141 144
145static struct twl4030_gpio_platform_data overo_gpio_data = {
146 .gpio_base = OMAP_MAX_GPIO_LINES,
147 .irq_base = TWL4030_GPIO_IRQ_BASE,
148 .irq_end = TWL4030_GPIO_IRQ_END,
149};
150
151static struct twl4030_platform_data overo_twldata = {
152 .irq_base = TWL4030_IRQ_BASE,
153 .irq_end = TWL4030_IRQ_END,
154 .gpio = &overo_gpio_data,
155};
156
157static struct i2c_board_info __initdata overo_i2c_boardinfo[] = {
158 {
159 I2C_BOARD_INFO("twl4030", 0x48),
160 .flags = I2C_CLIENT_WAKE,
161 .irq = INT_34XX_SYS_NIRQ,
162 .platform_data = &overo_twldata,
163 },
164};
165
142static int __init overo_i2c_init(void) 166static int __init overo_i2c_init(void)
143{ 167{
168 omap_register_i2c_bus(1, 2600, overo_i2c_boardinfo,
169 ARRAY_SIZE(overo_i2c_boardinfo));
144 /* i2c2 pins are used for gpio */ 170 /* i2c2 pins are used for gpio */
145 omap_register_i2c_bus(3, 400, NULL, 0); 171 omap_register_i2c_bus(3, 400, NULL, 0);
146 return 0; 172 return 0;
@@ -171,6 +197,22 @@ static struct platform_device *overo_devices[] __initdata = {
171 &overo_lcd_device, 197 &overo_lcd_device,
172}; 198};
173 199
200static struct twl4030_hsmmc_info mmc[] __initdata = {
201 {
202 .mmc = 1,
203 .wires = 4,
204 .gpio_cd = -EINVAL,
205 .gpio_wp = -EINVAL,
206 },
207 {
208 .mmc = 2,
209 .wires = 4,
210 .gpio_cd = -EINVAL,
211 .gpio_wp = -EINVAL,
212 },
213 {} /* Terminator */
214};
215
174static void __init overo_init(void) 216static void __init overo_init(void)
175{ 217{
176 overo_i2c_init(); 218 overo_i2c_init();
@@ -178,6 +220,7 @@ static void __init overo_init(void)
178 omap_board_config = overo_config; 220 omap_board_config = overo_config;
179 omap_board_config_size = ARRAY_SIZE(overo_config); 221 omap_board_config_size = ARRAY_SIZE(overo_config);
180 omap_serial_init(); 222 omap_serial_init();
223 twl4030_mmc_init(mmc);
181 overo_flash_init(); 224 overo_flash_init();
182 225
183 if ((gpio_request(OVERO_GPIO_W2W_NRESET, 226 if ((gpio_request(OVERO_GPIO_W2W_NRESET,
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index e5fc5bf5ceeb..ad6d98d177c5 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -2522,7 +2522,6 @@ static struct clk usbhs_ick = {
2522 2522
2523static struct clk mmchs1_ick = { 2523static struct clk mmchs1_ick = {
2524 .name = "mmchs_ick", 2524 .name = "mmchs_ick",
2525 .id = 1,
2526 .parent = &l4_ck, 2525 .parent = &l4_ck,
2527 .flags = CLOCK_IN_OMAP243X, 2526 .flags = CLOCK_IN_OMAP243X,
2528 .clkdm_name = "core_l4_clkdm", 2527 .clkdm_name = "core_l4_clkdm",
@@ -2533,7 +2532,6 @@ static struct clk mmchs1_ick = {
2533 2532
2534static struct clk mmchs1_fck = { 2533static struct clk mmchs1_fck = {
2535 .name = "mmchs_fck", 2534 .name = "mmchs_fck",
2536 .id = 1,
2537 .parent = &func_96m_ck, 2535 .parent = &func_96m_ck,
2538 .flags = CLOCK_IN_OMAP243X, 2536 .flags = CLOCK_IN_OMAP243X,
2539 .clkdm_name = "core_l3_clkdm", 2537 .clkdm_name = "core_l3_clkdm",
@@ -2544,7 +2542,7 @@ static struct clk mmchs1_fck = {
2544 2542
2545static struct clk mmchs2_ick = { 2543static struct clk mmchs2_ick = {
2546 .name = "mmchs_ick", 2544 .name = "mmchs_ick",
2547 .id = 2, 2545 .id = 1,
2548 .parent = &l4_ck, 2546 .parent = &l4_ck,
2549 .flags = CLOCK_IN_OMAP243X, 2547 .flags = CLOCK_IN_OMAP243X,
2550 .clkdm_name = "core_l4_clkdm", 2548 .clkdm_name = "core_l4_clkdm",
@@ -2555,7 +2553,7 @@ static struct clk mmchs2_ick = {
2555 2553
2556static struct clk mmchs2_fck = { 2554static struct clk mmchs2_fck = {
2557 .name = "mmchs_fck", 2555 .name = "mmchs_fck",
2558 .id = 2, 2556 .id = 1,
2559 .parent = &func_96m_ck, 2557 .parent = &func_96m_ck,
2560 .flags = CLOCK_IN_OMAP243X, 2558 .flags = CLOCK_IN_OMAP243X,
2561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -2595,7 +2593,6 @@ static struct clk mdm_intc_ick = {
2595 2593
2596static struct clk mmchsdb1_fck = { 2594static struct clk mmchsdb1_fck = {
2597 .name = "mmchsdb_fck", 2595 .name = "mmchsdb_fck",
2598 .id = 1,
2599 .parent = &func_32k_ck, 2596 .parent = &func_32k_ck,
2600 .flags = CLOCK_IN_OMAP243X, 2597 .flags = CLOCK_IN_OMAP243X,
2601 .clkdm_name = "core_l4_clkdm", 2598 .clkdm_name = "core_l4_clkdm",
@@ -2606,7 +2603,7 @@ static struct clk mmchsdb1_fck = {
2606 2603
2607static struct clk mmchsdb2_fck = { 2604static struct clk mmchsdb2_fck = {
2608 .name = "mmchsdb_fck", 2605 .name = "mmchsdb_fck",
2609 .id = 2, 2606 .id = 1,
2610 .parent = &func_32k_ck, 2607 .parent = &func_32k_ck,
2611 .flags = CLOCK_IN_OMAP243X, 2608 .flags = CLOCK_IN_OMAP243X,
2612 .clkdm_name = "core_l4_clkdm", 2609 .clkdm_name = "core_l4_clkdm",
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 084e11082f80..31bb7010bd48 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -475,7 +475,7 @@ int __init omap2_clk_init(void)
475 * Update this if there are further clock changes between ES2 475 * Update this if there are further clock changes between ES2
476 * and production parts 476 * and production parts
477 */ 477 */
478 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) { 478 if (omap_rev() == OMAP3430_REV_ES1_0) {
479 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 479 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
480 cpu_clkflg |= CLOCK_IN_OMAP3430ES1; 480 cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
481 } else { 481 } else {
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c38a8a09692f..a826094d89b5 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1374,7 +1374,7 @@ static struct clk core_96m_fck = {
1374 1374
1375static struct clk mmchs3_fck = { 1375static struct clk mmchs3_fck = {
1376 .name = "mmchs_fck", 1376 .name = "mmchs_fck",
1377 .id = 3, 1377 .id = 2,
1378 .parent = &core_96m_fck, 1378 .parent = &core_96m_fck,
1379 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1379 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1380 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1380 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1385,7 +1385,7 @@ static struct clk mmchs3_fck = {
1385 1385
1386static struct clk mmchs2_fck = { 1386static struct clk mmchs2_fck = {
1387 .name = "mmchs_fck", 1387 .name = "mmchs_fck",
1388 .id = 2, 1388 .id = 1,
1389 .parent = &core_96m_fck, 1389 .parent = &core_96m_fck,
1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1391 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1406,7 +1406,6 @@ static struct clk mspro_fck = {
1406 1406
1407static struct clk mmchs1_fck = { 1407static struct clk mmchs1_fck = {
1408 .name = "mmchs_fck", 1408 .name = "mmchs_fck",
1409 .id = 1,
1410 .parent = &core_96m_fck, 1409 .parent = &core_96m_fck,
1411 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1412 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1411 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
@@ -1722,7 +1721,7 @@ static struct clk usbtll_ick = {
1722 1721
1723static struct clk mmchs3_ick = { 1722static struct clk mmchs3_ick = {
1724 .name = "mmchs_ick", 1723 .name = "mmchs_ick",
1725 .id = 3, 1724 .id = 2,
1726 .parent = &core_l4_ick, 1725 .parent = &core_l4_ick,
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1728 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1727 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1774,7 +1773,7 @@ static struct clk des2_ick = {
1774 1773
1775static struct clk mmchs2_ick = { 1774static struct clk mmchs2_ick = {
1776 .name = "mmchs_ick", 1775 .name = "mmchs_ick",
1777 .id = 2, 1776 .id = 1,
1778 .parent = &core_l4_ick, 1777 .parent = &core_l4_ick,
1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1780 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1779 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1785,7 +1784,6 @@ static struct clk mmchs2_ick = {
1785 1784
1786static struct clk mmchs1_ick = { 1785static struct clk mmchs1_ick = {
1787 .name = "mmchs_ick", 1786 .name = "mmchs_ick",
1788 .id = 1,
1789 .parent = &core_l4_ick, 1787 .parent = &core_l4_ick,
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1788 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1791 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1789 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
@@ -2280,8 +2278,8 @@ static struct clk wkup_32k_fck = {
2280 .recalc = &followparent_recalc, 2278 .recalc = &followparent_recalc,
2281}; 2279};
2282 2280
2283static struct clk gpio1_fck = { 2281static struct clk gpio1_dbck = {
2284 .name = "gpio1_fck", 2282 .name = "gpio1_dbck",
2285 .parent = &wkup_32k_fck, 2283 .parent = &wkup_32k_fck,
2286 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2284 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2287 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2285 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2527,8 +2525,8 @@ static struct clk per_32k_alwon_fck = {
2527 .recalc = &followparent_recalc, 2525 .recalc = &followparent_recalc,
2528}; 2526};
2529 2527
2530static struct clk gpio6_fck = { 2528static struct clk gpio6_dbck = {
2531 .name = "gpio6_fck", 2529 .name = "gpio6_dbck",
2532 .parent = &per_32k_alwon_fck, 2530 .parent = &per_32k_alwon_fck,
2533 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2531 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2534 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2532 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2537,8 +2535,8 @@ static struct clk gpio6_fck = {
2537 .recalc = &followparent_recalc, 2535 .recalc = &followparent_recalc,
2538}; 2536};
2539 2537
2540static struct clk gpio5_fck = { 2538static struct clk gpio5_dbck = {
2541 .name = "gpio5_fck", 2539 .name = "gpio5_dbck",
2542 .parent = &per_32k_alwon_fck, 2540 .parent = &per_32k_alwon_fck,
2543 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2541 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2544 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2542 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2547,8 +2545,8 @@ static struct clk gpio5_fck = {
2547 .recalc = &followparent_recalc, 2545 .recalc = &followparent_recalc,
2548}; 2546};
2549 2547
2550static struct clk gpio4_fck = { 2548static struct clk gpio4_dbck = {
2551 .name = "gpio4_fck", 2549 .name = "gpio4_dbck",
2552 .parent = &per_32k_alwon_fck, 2550 .parent = &per_32k_alwon_fck,
2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2551 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2554 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2552 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2557,8 +2555,8 @@ static struct clk gpio4_fck = {
2557 .recalc = &followparent_recalc, 2555 .recalc = &followparent_recalc,
2558}; 2556};
2559 2557
2560static struct clk gpio3_fck = { 2558static struct clk gpio3_dbck = {
2561 .name = "gpio3_fck", 2559 .name = "gpio3_dbck",
2562 .parent = &per_32k_alwon_fck, 2560 .parent = &per_32k_alwon_fck,
2563 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2561 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2562 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2567,8 +2565,8 @@ static struct clk gpio3_fck = {
2567 .recalc = &followparent_recalc, 2565 .recalc = &followparent_recalc,
2568}; 2566};
2569 2567
2570static struct clk gpio2_fck = { 2568static struct clk gpio2_dbck = {
2571 .name = "gpio2_fck", 2569 .name = "gpio2_dbck",
2572 .parent = &per_32k_alwon_fck, 2570 .parent = &per_32k_alwon_fck,
2573 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2571 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2574 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2572 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -3170,7 +3168,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
3170 &usim_fck, 3168 &usim_fck,
3171 &gpt1_fck, 3169 &gpt1_fck,
3172 &wkup_32k_fck, 3170 &wkup_32k_fck,
3173 &gpio1_fck, 3171 &gpio1_dbck,
3174 &wdt2_fck, 3172 &wdt2_fck,
3175 &wkup_l4_ick, 3173 &wkup_l4_ick,
3176 &usim_ick, 3174 &usim_ick,
@@ -3192,11 +3190,11 @@ static struct clk *onchip_34xx_clks[] __initdata = {
3192 &gpt8_fck, 3190 &gpt8_fck,
3193 &gpt9_fck, 3191 &gpt9_fck,
3194 &per_32k_alwon_fck, 3192 &per_32k_alwon_fck,
3195 &gpio6_fck, 3193 &gpio6_dbck,
3196 &gpio5_fck, 3194 &gpio5_dbck,
3197 &gpio4_fck, 3195 &gpio4_dbck,
3198 &gpio3_fck, 3196 &gpio3_dbck,
3199 &gpio2_fck, 3197 &gpio2_dbck,
3200 &wdt3_fck, 3198 &wdt3_fck,
3201 &per_l4_ick, 3199 &per_l4_ick,
3202 &gpio6_ick, 3200 &gpio6_ick,
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 90af2ac469aa..9d7216ff6c9f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -14,16 +14,19 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/clk.h>
17 18
18#include <mach/hardware.h> 19#include <mach/hardware.h>
19#include <asm/mach-types.h> 20#include <asm/mach-types.h>
20#include <asm/mach/map.h> 21#include <asm/mach/map.h>
21 22
23#include <mach/control.h>
22#include <mach/tc.h> 24#include <mach/tc.h>
23#include <mach/board.h> 25#include <mach/board.h>
24#include <mach/mux.h> 26#include <mach/mux.h>
25#include <mach/gpio.h> 27#include <mach/gpio.h>
26#include <mach/eac.h> 28#include <mach/eac.h>
29#include <mach/mmc.h>
27 30
28#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 31#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
29#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) 32#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
@@ -295,6 +298,171 @@ static void omap_init_sha1_md5(void)
295static inline void omap_init_sha1_md5(void) { } 298static inline void omap_init_sha1_md5(void) { }
296#endif 299#endif
297 300
301/*-------------------------------------------------------------------------*/
302
303#ifdef CONFIG_ARCH_OMAP3
304
305#define MMCHS_SYSCONFIG 0x0010
306#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
307#define MMCHS_SYSSTATUS 0x0014
308#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
309
310static struct platform_device dummy_pdev = {
311 .dev = {
312 .bus = &platform_bus_type,
313 },
314};
315
316/**
317 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
318 *
319 * Ensure that each MMC controller is fully reset. Controllers
320 * left in an unknown state (by bootloader) may prevent retention
321 * or OFF-mode. This is especially important in cases where the
322 * MMC driver is not enabled, _or_ built as a module.
323 *
324 * In order for reset to work, interface, functional and debounce
325 * clocks must be enabled. The debounce clock comes from func_32k_clk
326 * and is not under SW control, so we only enable i- and f-clocks.
327 **/
328static void __init omap_hsmmc_reset(void)
329{
330 u32 i, nr_controllers = cpu_is_omap34xx() ? OMAP34XX_NR_MMC :
331 OMAP24XX_NR_MMC;
332
333 for (i = 0; i < nr_controllers; i++) {
334 u32 v, base = 0;
335 struct clk *iclk, *fclk;
336 struct device *dev = &dummy_pdev.dev;
337
338 switch (i) {
339 case 0:
340 base = OMAP2_MMC1_BASE;
341 break;
342 case 1:
343 base = OMAP2_MMC2_BASE;
344 break;
345 case 2:
346 base = OMAP3_MMC3_BASE;
347 break;
348 }
349
350 dummy_pdev.id = i;
351 iclk = clk_get(dev, "mmchs_ick");
352 if (iclk && clk_enable(iclk))
353 iclk = NULL;
354
355 fclk = clk_get(dev, "mmchs_fck");
356 if (fclk && clk_enable(fclk))
357 fclk = NULL;
358
359 if (!iclk || !fclk) {
360 printk(KERN_WARNING
361 "%s: Unable to enable clocks for MMC%d, "
362 "cannot reset.\n", __func__, i);
363 break;
364 }
365
366 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
367 v = omap_readl(base + MMCHS_SYSSTATUS);
368 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
369 MMCHS_SYSSTATUS_RESETDONE))
370 cpu_relax();
371
372 if (fclk) {
373 clk_disable(fclk);
374 clk_put(fclk);
375 }
376 if (iclk) {
377 clk_disable(iclk);
378 clk_put(iclk);
379 }
380 }
381}
382#else
383static inline void omap_hsmmc_reset(void) {}
384#endif
385
386#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
387 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
388
389static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
390 int controller_nr)
391{
392 if (cpu_is_omap2420() && controller_nr == 0) {
393 omap_cfg_reg(H18_24XX_MMC_CMD);
394 omap_cfg_reg(H15_24XX_MMC_CLKI);
395 omap_cfg_reg(G19_24XX_MMC_CLKO);
396 omap_cfg_reg(F20_24XX_MMC_DAT0);
397 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
398 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
399 if (mmc_controller->slots[0].wires == 4) {
400 omap_cfg_reg(H14_24XX_MMC_DAT1);
401 omap_cfg_reg(E19_24XX_MMC_DAT2);
402 omap_cfg_reg(D19_24XX_MMC_DAT3);
403 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
404 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
405 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
406 }
407
408 /*
409 * Use internal loop-back in MMC/SDIO Module Input Clock
410 * selection
411 */
412 if (mmc_controller->slots[0].internal_clock) {
413 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
414 v |= (1 << 24);
415 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
416 }
417 }
418}
419
420void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
421 int nr_controllers)
422{
423 int i;
424
425 for (i = 0; i < nr_controllers; i++) {
426 unsigned long base, size;
427 unsigned int irq = 0;
428
429 if (!mmc_data[i])
430 continue;
431
432 omap2_mmc_mux(mmc_data[i], i);
433
434 switch (i) {
435 case 0:
436 base = OMAP2_MMC1_BASE;
437 irq = INT_24XX_MMC_IRQ;
438 break;
439 case 1:
440 base = OMAP2_MMC2_BASE;
441 irq = INT_24XX_MMC2_IRQ;
442 break;
443 case 2:
444 if (!cpu_is_omap34xx())
445 return;
446 base = OMAP3_MMC3_BASE;
447 irq = INT_34XX_MMC3_IRQ;
448 break;
449 default:
450 continue;
451 }
452
453 if (cpu_is_omap2420())
454 size = OMAP2420_MMC_SIZE;
455 else
456 size = HSMMC_SIZE;
457
458 omap_mmc_add(i, base, size, irq, mmc_data[i]);
459 };
460}
461
462#endif
463
464/*-------------------------------------------------------------------------*/
465
298#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) 466#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
299#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) 467#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
300#define OMAP_HDQ_BASE 0x480B2000 468#define OMAP_HDQ_BASE 0x480B2000
@@ -334,6 +502,7 @@ static int __init omap2_init_devices(void)
334 /* please keep these calls, and their implementations above, 502 /* please keep these calls, and their implementations above,
335 * in alphabetical order so they're easier to sort through. 503 * in alphabetical order so they're easier to sort through.
336 */ 504 */
505 omap_hsmmc_reset();
337 omap_init_mbox(); 506 omap_init_mbox();
338 omap_init_mcspi(); 507 omap_init_mcspi();
339 omap_hdq_init(); 508 omap_hdq_init();
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index bf45ff39a7b5..b0f8e7d62798 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -22,40 +22,15 @@
22#include <mach/control.h> 22#include <mach/control.h>
23#include <mach/cpu.h> 23#include <mach/cpu.h>
24 24
25static u32 class; 25static struct omap_chip_id omap_chip;
26static void __iomem *tap_base; 26static unsigned int omap_revision;
27static u16 tap_prod_id;
28
29#define OMAP_TAP_IDCODE 0x0204
30#define OMAP_TAP_DIE_ID_0 0x0218
31#define OMAP_TAP_DIE_ID_1 0x021C
32#define OMAP_TAP_DIE_ID_2 0x0220
33#define OMAP_TAP_DIE_ID_3 0x0224
34
35/* system_rev fields for OMAP2 processors:
36 * CPU id bits [31:16],
37 * CPU device type [15:12], (unprg,normal,POP)
38 * CPU revision [11:08]
39 * CPU class bits [07:00]
40 */
41
42struct omap_id {
43 u16 hawkeye; /* Silicon type (Hawkeye id) */
44 u8 dev; /* Device type from production_id reg */
45 u32 type; /* combined type id copied to system_rev */
46};
47 27
48/* Register values to detect the OMAP version */
49static struct omap_id omap_ids[] __initdata = {
50 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
51 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
52 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
53 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
54 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
55 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
56};
57 28
58static struct omap_chip_id omap_chip; 29unsigned int omap_rev(void)
30{
31 return omap_revision;
32}
33EXPORT_SYMBOL(omap_rev);
59 34
60/** 35/**
61 * omap_chip_is - test whether currently running OMAP matches a chip type 36 * omap_chip_is - test whether currently running OMAP matches a chip type
@@ -70,135 +45,41 @@ int omap_chip_is(struct omap_chip_id oci)
70} 45}
71EXPORT_SYMBOL(omap_chip_is); 46EXPORT_SYMBOL(omap_chip_is);
72 47
73static u32 __init read_tap_reg(int reg) 48/*----------------------------------------------------------------------------*/
74{
75 unsigned int regval = 0;
76 u32 cpuid;
77
78 /* Reading the IDCODE register on 3430 ES1 results in a
79 * data abort as the register is not exposed on the OCP
80 * Hence reading the Cortex Rev
81 */
82 cpuid = read_cpuid(CPUID_ID);
83
84 /* If the processor type is Cortex-A8 and the revision is 0x0
85 * it means its Cortex r0p0 which is 3430 ES1
86 */
87 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
88
89 if (reg == tap_prod_id) {
90 regval = 0x000F00F0;
91 goto out;
92 }
93
94 switch (reg) {
95 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
96 /* Making DevType as 0xF in ES1 to differ from ES2 */
97 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
98 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
99 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
100 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
101 }
102 } else
103 regval = __raw_readl(tap_base + reg);
104
105out:
106 return regval;
107
108}
109 49
110/* 50#define OMAP_TAP_IDCODE 0x0204
111 * _set_system_rev - set the system_rev global based on current OMAP chip type 51#define OMAP_TAP_DIE_ID_0 0x0218
112 * 52#define OMAP_TAP_DIE_ID_1 0x021C
113 * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx() 53#define OMAP_TAP_DIE_ID_2 0x0220
114 * macros. 54#define OMAP_TAP_DIE_ID_3 0x0224
115 */
116static void __init _set_system_rev(u32 type, u8 rev)
117{
118 u32 i, ctrl_status;
119
120 /*
121 * system_rev encoding is as follows
122 * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
123 * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
124 * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
125 * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
126 * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
127 * system_rev & 0x000000c0 -> IDCODE revision[6:7]
128 * system_rev & 0x0000003f -> sys_boot[0:5]
129 */
130 /* Embedding the ES revision info in type field */
131 system_rev = type;
132 /* Also add IDCODE revision info only two lower bits */
133 system_rev |= ((rev & 0x3) << 6);
134
135 /* Add in the device type and sys_boot fields (see above) */
136 if (cpu_is_omap24xx()) {
137 i = OMAP24XX_CONTROL_STATUS;
138 } else if (cpu_is_omap343x()) {
139 i = OMAP343X_CONTROL_STATUS;
140 } else {
141 printk(KERN_ERR "id: unknown CPU type\n");
142 BUG();
143 }
144 ctrl_status = omap_ctrl_readl(i);
145 system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
146 OMAP2_SYSBOOT_4_MASK |
147 OMAP2_SYSBOOT_3_MASK |
148 OMAP2_SYSBOOT_2_MASK |
149 OMAP2_SYSBOOT_1_MASK |
150 OMAP2_SYSBOOT_0_MASK));
151 system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
152}
153
154
155/*
156 * _set_omap_chip - set the omap_chip global based on OMAP chip type
157 *
158 * Build the omap_chip bits. This variable is used by powerdomain and
159 * clockdomain code to indicate whether structures are applicable for
160 * the current OMAP chip type by ANDing it against a 'platform' bitfield
161 * in the structure.
162 */
163static void __init _set_omap_chip(void)
164{
165 if (cpu_is_omap343x()) {
166
167 omap_chip.oc = CHIP_IS_OMAP3430;
168 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
169 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
170 else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
171 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
172
173 } else if (cpu_is_omap243x()) {
174
175 /* Currently only supports 2430ES2.1 and 2430-all */
176 omap_chip.oc |= CHIP_IS_OMAP2430;
177
178 } else if (cpu_is_omap242x()) {
179
180 /* Currently only supports 2420ES2.1.1 and 2420-all */
181 omap_chip.oc |= CHIP_IS_OMAP2420;
182 55
183 } else { 56#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
184 57
185 /* Current CPU not supported by this code. */ 58struct omap_id {
186 printk(KERN_WARNING "OMAP chip type code does not yet support " 59 u16 hawkeye; /* Silicon type (Hawkeye id) */
187 "this CPU type.\n"); 60 u8 dev; /* Device type from production_id reg */
188 WARN_ON(1); 61 u32 type; /* Combined type id copied to omap_revision */
62};
189 63
190 } 64/* Register values to detect the OMAP version */
65static struct omap_id omap_ids[] __initdata = {
66 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
67 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
68 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
69 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
70 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
71 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
72};
191 73
192} 74static void __iomem *tap_base;
75static u16 tap_prod_id;
193 76
194void __init omap2_check_revision(void) 77void __init omap24xx_check_revision(void)
195{ 78{
196 int i, j; 79 int i, j;
197 u32 idcode; 80 u32 idcode, prod_id;
198 u32 prod_id;
199 u16 hawkeye; 81 u16 hawkeye;
200 u8 dev_type; 82 u8 dev_type, rev;
201 u8 rev;
202 83
203 idcode = read_tap_reg(OMAP_TAP_IDCODE); 84 idcode = read_tap_reg(OMAP_TAP_IDCODE);
204 prod_id = read_tap_reg(tap_prod_id); 85 prod_id = read_tap_reg(tap_prod_id);
@@ -220,18 +101,6 @@ void __init omap2_check_revision(void)
220 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 101 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
221 prod_id, dev_type); 102 prod_id, dev_type);
222 103
223 /*
224 * Detection for 34xx ES2.0 and above can be done with just
225 * hawkeye and rev. See TRM 1.5.2 Device Identification.
226 * Note that rev cannot be used directly as ES1.0 uses value 0.
227 */
228 if (hawkeye == 0xb7ae) {
229 system_rev = 0x34300000 | ((1 + rev) << 12);
230 pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
231 _set_omap_chip();
232 return;
233 }
234
235 /* Check hawkeye ids */ 104 /* Check hawkeye ids */
236 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 105 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
237 if (hawkeye == omap_ids[i].hawkeye) 106 if (hawkeye == omap_ids[i].hawkeye)
@@ -255,23 +124,115 @@ void __init omap2_check_revision(void)
255 j = i; 124 j = i;
256 } 125 }
257 126
258 _set_system_rev(omap_ids[j].type, rev); 127 pr_info("OMAP%04x", omap_rev() >> 16);
128 if ((omap_rev() >> 8) & 0x0f)
129 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
130 pr_info("\n");
131}
259 132
260 _set_omap_chip(); 133void __init omap34xx_check_revision(void)
134{
135 u32 cpuid, idcode;
136 u16 hawkeye;
137 u8 rev;
138 char *rev_name = "ES1.0";
261 139
262 pr_info("OMAP%04x", system_rev >> 16); 140 /*
263 if ((system_rev >> 8) & 0x0f) 141 * We cannot access revision registers on ES1.0.
264 pr_info("ES%x", (system_rev >> 12) & 0xf); 142 * If the processor type is Cortex-A8 and the revision is 0x0
265 pr_info("\n"); 143 * it means its Cortex r0p0 which is 3430 ES1.0.
144 */
145 cpuid = read_cpuid(CPUID_ID);
146 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
147 omap_revision = OMAP3430_REV_ES1_0;
148 goto out;
149 }
266 150
151 /*
152 * Detection for 34xx ES2.0 and above can be done with just
153 * hawkeye and rev. See TRM 1.5.2 Device Identification.
154 * Note that rev does not map directly to our defined processor
155 * revision numbers as ES1.0 uses value 0.
156 */
157 idcode = read_tap_reg(OMAP_TAP_IDCODE);
158 hawkeye = (idcode >> 12) & 0xffff;
159 rev = (idcode >> 28) & 0xff;
160
161 if (hawkeye == 0xb7ae) {
162 switch (rev) {
163 case 0:
164 omap_revision = OMAP3430_REV_ES2_0;
165 rev_name = "ES2.0";
166 break;
167 case 2:
168 omap_revision = OMAP3430_REV_ES2_1;
169 rev_name = "ES2.1";
170 break;
171 case 3:
172 omap_revision = OMAP3430_REV_ES3_0;
173 rev_name = "ES3.0";
174 break;
175 default:
176 /* Use the latest known revision as default */
177 omap_revision = OMAP3430_REV_ES3_0;
178 rev_name = "Unknown revision\n";
179 }
180 }
181
182out:
183 pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
267} 184}
268 185
186/*
187 * Try to detect the exact revision of the omap we're running on
188 */
189void __init omap2_check_revision(void)
190{
191 /*
192 * At this point we have an idea about the processor revision set
193 * earlier with omap2_set_globals_tap().
194 */
195 if (cpu_is_omap24xx())
196 omap24xx_check_revision();
197 else if (cpu_is_omap34xx())
198 omap34xx_check_revision();
199 else
200 pr_err("OMAP revision unknown, please fix!\n");
201
202 /*
203 * OK, now we know the exact revision. Initialize omap_chip bits
204 * for powerdowmain and clockdomain code.
205 */
206 if (cpu_is_omap243x()) {
207 /* Currently only supports 2430ES2.1 and 2430-all */
208 omap_chip.oc |= CHIP_IS_OMAP2430;
209 } else if (cpu_is_omap242x()) {
210 /* Currently only supports 2420ES2.1.1 and 2420-all */
211 omap_chip.oc |= CHIP_IS_OMAP2420;
212 } else if (cpu_is_omap343x()) {
213 omap_chip.oc = CHIP_IS_OMAP3430;
214 if (omap_rev() == OMAP3430_REV_ES1_0)
215 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
216 else if (omap_rev() > OMAP3430_REV_ES1_0)
217 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
218 } else {
219 pr_err("Uninitialized omap_chip, please fix!\n");
220 }
221}
222
223/*
224 * Set up things for map_io and processor detection later on. Gets called
225 * pretty much first thing from board init. For multi-omap, this gets
226 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
227 * detect the exact revision later on in omap2_detect_revision() once map_io
228 * is done.
229 */
269void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) 230void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
270{ 231{
271 class = omap2_globals->class; 232 omap_revision = omap2_globals->class;
272 tap_base = omap2_globals->tap; 233 tap_base = omap2_globals->tap;
273 234
274 if (class == 0x3430) 235 if (cpu_is_omap34xx())
275 tap_prod_id = 0x0210; 236 tap_prod_id = 0x0210;
276 else 237 else
277 tap_prod_id = 0x0208; 238 tap_prod_id = 0x0208;
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index c40fc378a251..636e2821af7d 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -23,6 +23,7 @@
23#define INTC_REVISION 0x0000 23#define INTC_REVISION 0x0000
24#define INTC_SYSCONFIG 0x0010 24#define INTC_SYSCONFIG 0x0010
25#define INTC_SYSSTATUS 0x0014 25#define INTC_SYSSTATUS 0x0014
26#define INTC_SIR 0x0040
26#define INTC_CONTROL 0x0048 27#define INTC_CONTROL 0x0048
27#define INTC_MIR_CLEAR0 0x0088 28#define INTC_MIR_CLEAR0 0x0088
28#define INTC_MIR_SET0 0x008c 29#define INTC_MIR_SET0 0x008c
@@ -60,6 +61,30 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
60 return __raw_readl(bank->base_reg + reg); 61 return __raw_readl(bank->base_reg + reg);
61} 62}
62 63
64static int previous_irq;
65
66/*
67 * On 34xx we can get occasional spurious interrupts if the ack from
68 * an interrupt handler does not get posted before we unmask. Warn about
69 * the interrupt handlers that need to flush posted writes.
70 */
71static int omap_check_spurious(unsigned int irq)
72{
73 u32 sir, spurious;
74
75 sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
76 spurious = sir >> 6;
77
78 if (spurious > 1) {
79 printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
80 "posted write for irq %i\n",
81 irq, sir, previous_irq);
82 return spurious;
83 }
84
85 return 0;
86}
87
63/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 88/* XXX: FIQ and additional INTC support (only MPU at the moment) */
64static void omap_ack_irq(unsigned int irq) 89static void omap_ack_irq(unsigned int irq)
65{ 90{
@@ -70,6 +95,20 @@ static void omap_mask_irq(unsigned int irq)
70{ 95{
71 int offset = irq & (~(IRQ_BITS_PER_REG - 1)); 96 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
72 97
98 if (cpu_is_omap34xx()) {
99 int spurious = 0;
100
101 /*
102 * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
103 * it is the highest irq number?
104 */
105 if (irq == INT_34XX_GPT12_IRQ)
106 spurious = omap_check_spurious(irq);
107
108 if (!spurious)
109 previous_irq = irq;
110 }
111
73 irq &= (IRQ_BITS_PER_REG - 1); 112 irq &= (IRQ_BITS_PER_REG - 1);
74 113
75 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset); 114 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
new file mode 100644
index 000000000000..437f52073f6e
--- /dev/null
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -0,0 +1,408 @@
1/*
2 * linux/arch/arm/mach-omap2/mmc-twl4030.c
3 *
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/delay.h>
18#include <linux/gpio.h>
19#include <linux/i2c/twl4030.h>
20
21#include <mach/hardware.h>
22#include <mach/control.h>
23#include <mach/mmc.h>
24#include <mach/board.h>
25
26#include "mmc-twl4030.h"
27
28#if defined(CONFIG_TWL4030_CORE) && \
29 (defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
30
31#define LDO_CLR 0x00
32#define VSEL_S2_CLR 0x40
33
34#define VMMC1_DEV_GRP 0x27
35#define VMMC1_CLR 0x00
36#define VMMC1_315V 0x03
37#define VMMC1_300V 0x02
38#define VMMC1_285V 0x01
39#define VMMC1_185V 0x00
40#define VMMC1_DEDICATED 0x2A
41
42#define VMMC2_DEV_GRP 0x2B
43#define VMMC2_CLR 0x40
44#define VMMC2_315V 0x0c
45#define VMMC2_300V 0x0b
46#define VMMC2_285V 0x0a
47#define VMMC2_260V 0x08
48#define VMMC2_185V 0x06
49#define VMMC2_DEDICATED 0x2E
50
51#define VMMC_DEV_GRP_P1 0x20
52
53static u16 control_pbias_offset;
54static u16 control_devconf1_offset;
55
56#define HSMMC_NAME_LEN 9
57
58static struct twl_mmc_controller {
59 struct omap_mmc_platform_data *mmc;
60 u8 twl_vmmc_dev_grp;
61 u8 twl_mmc_dedicated;
62 char name[HSMMC_NAME_LEN];
63} hsmmc[] = {
64 {
65 .twl_vmmc_dev_grp = VMMC1_DEV_GRP,
66 .twl_mmc_dedicated = VMMC1_DEDICATED,
67 },
68 {
69 .twl_vmmc_dev_grp = VMMC2_DEV_GRP,
70 .twl_mmc_dedicated = VMMC2_DEDICATED,
71 },
72};
73
74static int twl_mmc_card_detect(int irq)
75{
76 unsigned i;
77
78 for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
79 struct omap_mmc_platform_data *mmc;
80
81 mmc = hsmmc[i].mmc;
82 if (!mmc)
83 continue;
84 if (irq != mmc->slots[0].card_detect_irq)
85 continue;
86
87 /* NOTE: assumes card detect signal is active-low */
88 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
89 }
90 return -ENOSYS;
91}
92
93static int twl_mmc_get_ro(struct device *dev, int slot)
94{
95 struct omap_mmc_platform_data *mmc = dev->platform_data;
96
97 /* NOTE: assumes write protect signal is active-high */
98 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
99}
100
101/*
102 * MMC Slot Initialization.
103 */
104static int twl_mmc_late_init(struct device *dev)
105{
106 struct omap_mmc_platform_data *mmc = dev->platform_data;
107 int ret = 0;
108 int i;
109
110 ret = gpio_request(mmc->slots[0].switch_pin, "mmc_cd");
111 if (ret)
112 goto done;
113 ret = gpio_direction_input(mmc->slots[0].switch_pin);
114 if (ret)
115 goto err;
116
117 for (i = 0; i < ARRAY_SIZE(hsmmc); i++) {
118 if (hsmmc[i].name == mmc->slots[0].name) {
119 hsmmc[i].mmc = mmc;
120 break;
121 }
122 }
123
124 return 0;
125
126err:
127 gpio_free(mmc->slots[0].switch_pin);
128done:
129 mmc->slots[0].card_detect_irq = 0;
130 mmc->slots[0].card_detect = NULL;
131
132 dev_err(dev, "err %d configuring card detect\n", ret);
133 return ret;
134}
135
136static void twl_mmc_cleanup(struct device *dev)
137{
138 struct omap_mmc_platform_data *mmc = dev->platform_data;
139
140 gpio_free(mmc->slots[0].switch_pin);
141}
142
143#ifdef CONFIG_PM
144
145static int twl_mmc_suspend(struct device *dev, int slot)
146{
147 struct omap_mmc_platform_data *mmc = dev->platform_data;
148
149 disable_irq(mmc->slots[0].card_detect_irq);
150 return 0;
151}
152
153static int twl_mmc_resume(struct device *dev, int slot)
154{
155 struct omap_mmc_platform_data *mmc = dev->platform_data;
156
157 enable_irq(mmc->slots[0].card_detect_irq);
158 return 0;
159}
160
161#else
162#define twl_mmc_suspend NULL
163#define twl_mmc_resume NULL
164#endif
165
166/*
167 * Sets the MMC voltage in twl4030
168 */
169static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd)
170{
171 int ret;
172 u8 vmmc, dev_grp_val;
173
174 switch (1 << vdd) {
175 case MMC_VDD_35_36:
176 case MMC_VDD_34_35:
177 case MMC_VDD_33_34:
178 case MMC_VDD_32_33:
179 case MMC_VDD_31_32:
180 case MMC_VDD_30_31:
181 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
182 vmmc = VMMC1_315V;
183 else
184 vmmc = VMMC2_315V;
185 break;
186 case MMC_VDD_29_30:
187 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
188 vmmc = VMMC1_315V;
189 else
190 vmmc = VMMC2_300V;
191 break;
192 case MMC_VDD_27_28:
193 case MMC_VDD_26_27:
194 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
195 vmmc = VMMC1_285V;
196 else
197 vmmc = VMMC2_285V;
198 break;
199 case MMC_VDD_25_26:
200 case MMC_VDD_24_25:
201 case MMC_VDD_23_24:
202 case MMC_VDD_22_23:
203 case MMC_VDD_21_22:
204 case MMC_VDD_20_21:
205 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
206 vmmc = VMMC1_285V;
207 else
208 vmmc = VMMC2_260V;
209 break;
210 case MMC_VDD_165_195:
211 if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP)
212 vmmc = VMMC1_185V;
213 else
214 vmmc = VMMC2_185V;
215 break;
216 default:
217 vmmc = 0;
218 break;
219 }
220
221 if (vmmc)
222 dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */
223 else
224 dev_grp_val = LDO_CLR; /* Power down */
225
226 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
227 dev_grp_val, c->twl_vmmc_dev_grp);
228 if (ret)
229 return ret;
230
231 ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
232 vmmc, c->twl_mmc_dedicated);
233
234 return ret;
235}
236
237static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
238 int vdd)
239{
240 u32 reg;
241 int ret = 0;
242 struct twl_mmc_controller *c = &hsmmc[0];
243 struct omap_mmc_platform_data *mmc = dev->platform_data;
244
245 if (power_on) {
246 if (cpu_is_omap2430()) {
247 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
248 if ((1 << vdd) >= MMC_VDD_30_31)
249 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
250 else
251 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
252 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
253 }
254
255 if (mmc->slots[0].internal_clock) {
256 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
257 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
258 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
259 }
260
261 reg = omap_ctrl_readl(control_pbias_offset);
262 reg |= OMAP2_PBIASSPEEDCTRL0;
263 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
264 omap_ctrl_writel(reg, control_pbias_offset);
265
266 ret = twl_mmc_set_voltage(c, vdd);
267
268 /* 100ms delay required for PBIAS configuration */
269 msleep(100);
270 reg = omap_ctrl_readl(control_pbias_offset);
271 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
272 if ((1 << vdd) <= MMC_VDD_165_195)
273 reg &= ~OMAP2_PBIASLITEVMODE0;
274 else
275 reg |= OMAP2_PBIASLITEVMODE0;
276 omap_ctrl_writel(reg, control_pbias_offset);
277 } else {
278 reg = omap_ctrl_readl(control_pbias_offset);
279 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
280 omap_ctrl_writel(reg, control_pbias_offset);
281
282 ret = twl_mmc_set_voltage(c, 0);
283
284 /* 100ms delay required for PBIAS configuration */
285 msleep(100);
286 reg = omap_ctrl_readl(control_pbias_offset);
287 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
288 OMAP2_PBIASLITEVMODE0);
289 omap_ctrl_writel(reg, control_pbias_offset);
290 }
291
292 return ret;
293}
294
295static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vdd)
296{
297 int ret;
298 struct twl_mmc_controller *c = &hsmmc[1];
299 struct omap_mmc_platform_data *mmc = dev->platform_data;
300
301 if (power_on) {
302 if (mmc->slots[0].internal_clock) {
303 u32 reg;
304
305 reg = omap_ctrl_readl(control_devconf1_offset);
306 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
307 omap_ctrl_writel(reg, control_devconf1_offset);
308 }
309 ret = twl_mmc_set_voltage(c, vdd);
310 } else {
311 ret = twl_mmc_set_voltage(c, 0);
312 }
313
314 return ret;
315}
316
317static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
318
319void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
320{
321 struct twl4030_hsmmc_info *c;
322 int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
323
324 if (cpu_is_omap2430()) {
325 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
326 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
327 nr_hsmmc = 2;
328 } else {
329 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
330 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
331 }
332
333 for (c = controllers; c->mmc; c++) {
334 struct twl_mmc_controller *twl = hsmmc + c->mmc - 1;
335 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
336
337 if (!c->mmc || c->mmc > nr_hsmmc) {
338 pr_debug("MMC%d: no such controller\n", c->mmc);
339 continue;
340 }
341 if (mmc) {
342 pr_debug("MMC%d: already configured\n", c->mmc);
343 continue;
344 }
345
346 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
347 if (!mmc) {
348 pr_err("Cannot allocate memory for mmc device!\n");
349 return;
350 }
351
352 sprintf(twl->name, "mmc%islot%i", c->mmc, 1);
353 mmc->slots[0].name = twl->name;
354 mmc->nr_slots = 1;
355 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
356 MMC_VDD_26_27 | MMC_VDD_27_28 |
357 MMC_VDD_29_30 |
358 MMC_VDD_30_31 | MMC_VDD_31_32;
359 mmc->slots[0].wires = c->wires;
360 mmc->slots[0].internal_clock = !c->ext_clock;
361 mmc->dma_mask = 0xffffffff;
362
363 /* note: twl4030 card detect GPIOs normally switch VMMCx ... */
364 if (gpio_is_valid(c->gpio_cd)) {
365 mmc->init = twl_mmc_late_init;
366 mmc->cleanup = twl_mmc_cleanup;
367 mmc->suspend = twl_mmc_suspend;
368 mmc->resume = twl_mmc_resume;
369
370 mmc->slots[0].switch_pin = c->gpio_cd;
371 mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd);
372 mmc->slots[0].card_detect = twl_mmc_card_detect;
373 } else
374 mmc->slots[0].switch_pin = -EINVAL;
375
376 /* write protect normally uses an OMAP gpio */
377 if (gpio_is_valid(c->gpio_wp)) {
378 gpio_request(c->gpio_wp, "mmc_wp");
379 gpio_direction_input(c->gpio_wp);
380
381 mmc->slots[0].gpio_wp = c->gpio_wp;
382 mmc->slots[0].get_ro = twl_mmc_get_ro;
383 } else
384 mmc->slots[0].gpio_wp = -EINVAL;
385
386 /* NOTE: we assume OMAP's MMC1 and MMC2 use
387 * the TWL4030's VMMC1 and VMMC2, respectively;
388 * and that OMAP's MMC3 isn't used.
389 */
390
391 switch (c->mmc) {
392 case 1:
393 mmc->slots[0].set_power = twl_mmc1_set_power;
394 break;
395 case 2:
396 mmc->slots[0].set_power = twl_mmc2_set_power;
397 break;
398 default:
399 pr_err("MMC%d configuration not supported!\n", c->mmc);
400 continue;
401 }
402 hsmmc_data[c->mmc - 1] = mmc;
403 }
404
405 omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
406}
407
408#endif
diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/mmc-twl4030.h
new file mode 100644
index 000000000000..e1c8076400ca
--- /dev/null
+++ b/arch/arm/mach-omap2/mmc-twl4030.h
@@ -0,0 +1,29 @@
1/*
2 * MMC definitions for OMAP2
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9struct twl4030_hsmmc_info {
10 u8 mmc; /* controller 1/2/3 */
11 u8 wires; /* 1/4/8 wires */
12 int gpio_cd; /* or -EINVAL */
13 int gpio_wp; /* or -EINVAL */
14 int ext_clock:1; /* use external pin for input clock */
15};
16
17#if defined(CONFIG_TWL4030_CORE) && \
18 (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
19 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE))
20
21void twl4030_mmc_init(struct twl4030_hsmmc_info *);
22
23#else
24
25static inline void twl4030_mmc_init(struct twl4030_hsmmc_info *info)
26{
27}
28
29#endif
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index b1393673d95d..dacb41f130c0 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -203,6 +203,15 @@ MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1)
203MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1) 203MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1)
204 204
205/* 2430 McBSP */ 205/* 2430 McBSP */
206MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1)
207
208MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1)
209MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1)
210MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1)
211MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1)
212MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1)
213MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1)
214
206MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1) 215MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1)
207MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1) 216MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1)
208MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1) 217MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1)
@@ -211,6 +220,31 @@ MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
211MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1) 220MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
212MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1) 221MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
213MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1) 222MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
223
224MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1)
225MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1)
226MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1)
227MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1)
228
229MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1)
230MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1)
231MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1)
232MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1)
233
234MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1)
235MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1)
236MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1)
237MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1)
238
239/* 2430 MCSPI1 */
240MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1)
241MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1)
242MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1)
243MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1)
244
245/* Touchscreen GPIO */
246MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1)
247
214}; 248};
215 249
216#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins) 250#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
@@ -417,6 +451,14 @@ MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
417MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a, 451MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
418 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 452 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
419 453
454
455/* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix.
456 * No internal pullup/pulldown without "_UP" or "_DOWN" suffix.
457 */
458MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa,
459 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
460MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
461 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
420}; 462};
421 463
422#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) 464#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
@@ -452,7 +494,7 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r
452#endif 494#endif
453 495
454#ifdef CONFIG_ARCH_OMAP24XX 496#ifdef CONFIG_ARCH_OMAP24XX
455int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) 497static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
456{ 498{
457 static DEFINE_SPINLOCK(mux_spin_lock); 499 static DEFINE_SPINLOCK(mux_spin_lock);
458 unsigned long flags; 500 unsigned long flags;
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 589393bedade..ae6036300f60 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -120,7 +120,7 @@ static void __init omap2_gp_clockevent_init(void)
120 clockevent_gpt.min_delta_ns = 120 clockevent_gpt.min_delta_ns =
121 clockevent_delta2ns(1, &clockevent_gpt); 121 clockevent_delta2ns(1, &clockevent_gpt);
122 122
123 clockevent_gpt.cpumask = cpumask_of_cpu(0); 123 clockevent_gpt.cpumask = cpumask_of(0);
124 clockevents_register_device(&clockevent_gpt); 124 clockevents_register_device(&clockevent_gpt);
125} 125}
126 126
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 10ef464d6be7..15e509013def 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -12,11 +12,11 @@
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/gpio.h>
15 16
16#include <linux/usb/musb.h> 17#include <linux/usb/musb.h>
17 18
18#include <mach/gpmc.h> 19#include <mach/gpmc.h>
19#include <mach/gpio.h>
20#include <mach/mux.h> 20#include <mach/mux.h>
21 21
22 22
@@ -292,12 +292,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
292 ); 292 );
293 293
294 /* IRQ */ 294 /* IRQ */
295 status = omap_request_gpio(irq); 295 status = gpio_request(irq, "TUSB6010 irq");
296 if (status < 0) { 296 if (status < 0) {
297 printk(error, 3, status); 297 printk(error, 3, status);
298 return status; 298 return status;
299 } 299 }
300 omap_set_gpio_direction(irq, 1); 300 gpio_direction_input(irq);
301 tusb_resources[2].start = irq + IH_GPIO_BASE; 301 tusb_resources[2].start = irq + IH_GPIO_BASE;
302 302
303 /* set up memory timings ... can speed them up later */ 303 /* set up memory timings ... can speed them up later */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 03:00:02 -0500