diff options
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 14 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock24xx.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 20 | ||||
-rw-r--r-- | arch/arm/mach-omap2/sdrc.c | 19 | ||||
-rw-r--r-- | arch/arm/mach-omap2/sram34xx.S | 129 |
5 files changed, 107 insertions, 77 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index dd37483f3d18..ba528f85749c 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -547,8 +547,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
547 | const struct clksel_rate *clkr; | 547 | const struct clksel_rate *clkr; |
548 | u32 last_div = 0; | 548 | u32 last_div = 0; |
549 | 549 | ||
550 | printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", | 550 | pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", |
551 | clk->name, target_rate); | 551 | clk->name, target_rate); |
552 | 552 | ||
553 | *new_div = 1; | 553 | *new_div = 1; |
554 | 554 | ||
@@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
562 | 562 | ||
563 | /* Sanity check */ | 563 | /* Sanity check */ |
564 | if (clkr->div <= last_div) | 564 | if (clkr->div <= last_div) |
565 | printk(KERN_ERR "clock: clksel_rate table not sorted " | 565 | pr_err("clock: clksel_rate table not sorted " |
566 | "for clock %s", clk->name); | 566 | "for clock %s", clk->name); |
567 | 567 | ||
568 | last_div = clkr->div; | 568 | last_div = clkr->div; |
@@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
574 | } | 574 | } |
575 | 575 | ||
576 | if (!clkr->div) { | 576 | if (!clkr->div) { |
577 | printk(KERN_ERR "clock: Could not find divisor for target " | 577 | pr_err("clock: Could not find divisor for target " |
578 | "rate %ld for clock %s parent %s\n", target_rate, | 578 | "rate %ld for clock %s parent %s\n", target_rate, |
579 | clk->name, clk->parent->name); | 579 | clk->name, clk->parent->name); |
580 | return ~0; | 580 | return ~0; |
@@ -582,8 +582,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
582 | 582 | ||
583 | *new_div = clkr->div; | 583 | *new_div = clkr->div; |
584 | 584 | ||
585 | printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, | 585 | pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, |
586 | (clk->parent->rate / clkr->div)); | 586 | (clk->parent->rate / clkr->div)); |
587 | 587 | ||
588 | return (clk->parent->rate / clkr->div); | 588 | return (clk->parent->rate / clkr->div); |
589 | } | 589 | } |
@@ -1035,7 +1035,7 @@ void omap2_clk_disable_unused(struct clk *clk) | |||
1035 | if ((regval32 & (1 << clk->enable_bit)) == v) | 1035 | if ((regval32 & (1 << clk->enable_bit)) == v) |
1036 | return; | 1036 | return; |
1037 | 1037 | ||
1038 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); | 1038 | printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); |
1039 | if (cpu_is_omap34xx()) { | 1039 | if (cpu_is_omap34xx()) { |
1040 | omap2_clk_enable(clk); | 1040 | omap2_clk_enable(clk); |
1041 | omap2_clk_disable(clk); | 1041 | omap2_clk_disable(clk); |
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index c442fe9f998a..44de0271fc2f 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c | |||
@@ -725,7 +725,7 @@ int __init omap2_clk_init(void) | |||
725 | clk_init(&omap2_clk_functions); | 725 | clk_init(&omap2_clk_functions); |
726 | 726 | ||
727 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) | 727 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) |
728 | clk_init_one(c->lk.clk); | 728 | clk_preinit(c->lk.clk); |
729 | 729 | ||
730 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); | 730 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
731 | propagate_rate(&osc_ck); | 731 | propagate_rate(&osc_ck); |
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index ba05aa42bd8e..62021397e5f9 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -281,6 +281,8 @@ static struct omap_clk omap34xx_clks[] = { | |||
281 | 281 | ||
282 | #define MAX_DPLL_WAIT_TRIES 1000000 | 282 | #define MAX_DPLL_WAIT_TRIES 1000000 |
283 | 283 | ||
284 | #define MIN_SDRC_DLL_LOCK_FREQ 83000000 | ||
285 | |||
284 | /** | 286 | /** |
285 | * omap3_dpll_recalc - recalculate DPLL rate | 287 | * omap3_dpll_recalc - recalculate DPLL rate |
286 | * @clk: DPLL struct clk | 288 | * @clk: DPLL struct clk |
@@ -703,6 +705,7 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | |||
703 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | 705 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) |
704 | { | 706 | { |
705 | u32 new_div = 0; | 707 | u32 new_div = 0; |
708 | u32 unlock_dll = 0; | ||
706 | unsigned long validrate, sdrcrate; | 709 | unsigned long validrate, sdrcrate; |
707 | struct omap_sdrc_params *sp; | 710 | struct omap_sdrc_params *sp; |
708 | 711 | ||
@@ -729,17 +732,22 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
729 | if (!sp) | 732 | if (!sp) |
730 | return -EINVAL; | 733 | return -EINVAL; |
731 | 734 | ||
732 | pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | 735 | if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { |
733 | validrate); | 736 | pr_debug("clock: will unlock SDRC DLL\n"); |
734 | pr_info("clock: SDRC timing params used: %08x %08x %08x\n", | 737 | unlock_dll = 1; |
735 | sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); | 738 | } |
739 | |||
740 | pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | ||
741 | validrate); | ||
742 | pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", | ||
743 | sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); | ||
736 | 744 | ||
737 | /* REVISIT: SRAM code doesn't support other M2 divisors yet */ | 745 | /* REVISIT: SRAM code doesn't support other M2 divisors yet */ |
738 | WARN_ON(new_div != 1 && new_div != 2); | 746 | WARN_ON(new_div != 1 && new_div != 2); |
739 | 747 | ||
740 | /* REVISIT: Add SDRC_MR changing to this code also */ | 748 | /* REVISIT: Add SDRC_MR changing to this code also */ |
741 | omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, | 749 | omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, |
742 | sp->actim_ctrlb, new_div); | 750 | sp->actim_ctrlb, new_div, unlock_dll); |
743 | 751 | ||
744 | return 0; | 752 | return 0; |
745 | } | 753 | } |
@@ -956,7 +964,7 @@ int __init omap2_clk_init(void) | |||
956 | clk_init(&omap2_clk_functions); | 964 | clk_init(&omap2_clk_functions); |
957 | 965 | ||
958 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | 966 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) |
959 | clk_init_one(c->lk.clk); | 967 | clk_preinit(c->lk.clk); |
960 | 968 | ||
961 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | 969 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) |
962 | if (c->cpu & cpu_clkflg) { | 970 | if (c->cpu & cpu_clkflg) { |
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 2a30060cb4b7..d62e4e10d4b0 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c | |||
@@ -37,6 +37,10 @@ static struct omap_sdrc_params *sdrc_init_params; | |||
37 | void __iomem *omap2_sdrc_base; | 37 | void __iomem *omap2_sdrc_base; |
38 | void __iomem *omap2_sms_base; | 38 | void __iomem *omap2_sms_base; |
39 | 39 | ||
40 | /* SDRC_POWER register bits */ | ||
41 | #define SDRC_POWER_EXTCLKDIS_SHIFT 3 | ||
42 | #define SDRC_POWER_PWDENA_SHIFT 2 | ||
43 | #define SDRC_POWER_PAGEPOLICY_SHIFT 0 | ||
40 | 44 | ||
41 | /** | 45 | /** |
42 | * omap2_sdrc_get_params - return SDRC register values for a given clock rate | 46 | * omap2_sdrc_get_params - return SDRC register values for a given clock rate |
@@ -74,7 +78,14 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) | |||
74 | omap2_sms_base = omap2_globals->sms; | 78 | omap2_sms_base = omap2_globals->sms; |
75 | } | 79 | } |
76 | 80 | ||
77 | /* turn on smart idle modes for SDRAM scheduler and controller */ | 81 | /** |
82 | * omap2_sdrc_init - initialize SMS, SDRC devices on boot | ||
83 | * @sp: pointer to a null-terminated list of struct omap_sdrc_params | ||
84 | * | ||
85 | * Turn on smart idle modes for SDRAM scheduler and controller. | ||
86 | * Program a known-good configuration for the SDRC to deal with buggy | ||
87 | * bootloaders. | ||
88 | */ | ||
78 | void __init omap2_sdrc_init(struct omap_sdrc_params *sp) | 89 | void __init omap2_sdrc_init(struct omap_sdrc_params *sp) |
79 | { | 90 | { |
80 | u32 l; | 91 | u32 l; |
@@ -90,4 +101,10 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp) | |||
90 | sdrc_write_reg(l, SDRC_SYSCONFIG); | 101 | sdrc_write_reg(l, SDRC_SYSCONFIG); |
91 | 102 | ||
92 | sdrc_init_params = sp; | 103 | sdrc_init_params = sp; |
104 | |||
105 | /* XXX Enable SRFRONIDLEREQ here also? */ | ||
106 | l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | | ||
107 | (1 << SDRC_POWER_PWDENA_SHIFT) | | ||
108 | (1 << SDRC_POWER_PAGEPOLICY_SHIFT); | ||
109 | sdrc_write_reg(l, SDRC_POWER); | ||
93 | } | 110 | } |
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 2c7146136342..c080c82521e1 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S | |||
@@ -40,69 +40,74 @@ | |||
40 | /* | 40 | /* |
41 | * Change frequency of core dpll | 41 | * Change frequency of core dpll |
42 | * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 | 42 | * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 |
43 | * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for | ||
44 | * SDRC rates < 83MHz | ||
43 | */ | 45 | */ |
44 | ENTRY(omap3_sram_configure_core_dpll) | 46 | ENTRY(omap3_sram_configure_core_dpll) |
45 | stmfd sp!, {r1-r12, lr} @ store regs to stack | 47 | stmfd sp!, {r1-r12, lr} @ store regs to stack |
48 | ldr r4, [sp, #52] @ pull extra args off the stack | ||
49 | dsb @ flush buffered writes to interconnect | ||
46 | cmp r3, #0x2 | 50 | cmp r3, #0x2 |
47 | blne configure_sdrc | 51 | blne configure_sdrc |
48 | cmp r3, #0x2 | 52 | cmp r4, #0x1 |
53 | bleq unlock_dll | ||
49 | blne lock_dll | 54 | blne lock_dll |
50 | cmp r3, #0x1 | ||
51 | blne unlock_dll | ||
52 | bl sdram_in_selfrefresh @ put the SDRAM in self refresh | 55 | bl sdram_in_selfrefresh @ put the SDRAM in self refresh |
53 | bl configure_core_dpll | 56 | bl configure_core_dpll |
54 | bl enable_sdrc | 57 | bl enable_sdrc |
55 | cmp r3, #0x1 | 58 | cmp r4, #0x1 |
56 | blne wait_dll_unlock | 59 | bleq wait_dll_unlock |
57 | cmp r3, #0x2 | ||
58 | blne wait_dll_lock | 60 | blne wait_dll_lock |
59 | cmp r3, #0x1 | 61 | cmp r3, #0x1 |
60 | blne configure_sdrc | 62 | blne configure_sdrc |
63 | isb @ prevent speculative exec past here | ||
61 | mov r0, #0 @ return value | 64 | mov r0, #0 @ return value |
62 | ldmfd sp!, {r1-r12, pc} @ restore regs and return | 65 | ldmfd sp!, {r1-r12, pc} @ restore regs and return |
63 | unlock_dll: | 66 | unlock_dll: |
64 | ldr r4, omap3_sdrc_dlla_ctrl | 67 | ldr r11, omap3_sdrc_dlla_ctrl |
65 | ldr r5, [r4] | 68 | ldr r12, [r11] |
66 | orr r5, r5, #0x4 | 69 | orr r12, r12, #0x4 |
67 | str r5, [r4] | 70 | str r12, [r11] @ (no OCP barrier needed) |
68 | bx lr | 71 | bx lr |
69 | lock_dll: | 72 | lock_dll: |
70 | ldr r4, omap3_sdrc_dlla_ctrl | 73 | ldr r11, omap3_sdrc_dlla_ctrl |
71 | ldr r5, [r4] | 74 | ldr r12, [r11] |
72 | bic r5, r5, #0x4 | 75 | bic r12, r12, #0x4 |
73 | str r5, [r4] | 76 | str r12, [r11] @ (no OCP barrier needed) |
74 | bx lr | 77 | bx lr |
75 | sdram_in_selfrefresh: | 78 | sdram_in_selfrefresh: |
76 | mov r5, #0x0 @ Move 0 to R5 | 79 | ldr r11, omap3_sdrc_power @ read the SDRC_POWER register |
77 | mcr p15, 0, r5, c7, c10, 5 @ memory barrier | 80 | ldr r12, [r11] @ read the contents of SDRC_POWER |
78 | ldr r4, omap3_sdrc_power @ read the SDRC_POWER register | 81 | mov r9, r12 @ keep a copy of SDRC_POWER bits |
79 | ldr r5, [r4] @ read the contents of SDRC_POWER | 82 | orr r12, r12, #0x40 @ enable self refresh on idle req |
80 | orr r5, r5, #0x40 @ enable self refresh on idle req | 83 | bic r12, r12, #0x4 @ clear PWDENA |
81 | str r5, [r4] @ write back to SDRC_POWER register | 84 | str r12, [r11] @ write back to SDRC_POWER register |
82 | ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg | 85 | ldr r12, [r11] @ posted-write barrier for SDRC |
83 | ldr r5, [r4] | 86 | ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg |
84 | bic r5, r5, #0x2 @ disable iclk bit for SRDC | 87 | ldr r12, [r11] |
85 | str r5, [r4] | 88 | bic r12, r12, #0x2 @ disable iclk bit for SDRC |
89 | str r12, [r11] | ||
86 | wait_sdrc_idle: | 90 | wait_sdrc_idle: |
87 | ldr r4, omap3_cm_idlest1_core | 91 | ldr r11, omap3_cm_idlest1_core |
88 | ldr r5, [r4] | 92 | ldr r12, [r11] |
89 | and r5, r5, #0x2 @ check for SDRC idle | 93 | and r12, r12, #0x2 @ check for SDRC idle |
90 | cmp r5, #2 | 94 | cmp r12, #2 |
91 | bne wait_sdrc_idle | 95 | bne wait_sdrc_idle |
92 | bx lr | 96 | bx lr |
93 | configure_core_dpll: | 97 | configure_core_dpll: |
94 | ldr r4, omap3_cm_clksel1_pll | 98 | ldr r11, omap3_cm_clksel1_pll |
95 | ldr r5, [r4] | 99 | ldr r12, [r11] |
96 | ldr r6, core_m2_mask_val @ modify m2 for core dpll | 100 | ldr r10, core_m2_mask_val @ modify m2 for core dpll |
97 | and r5, r5, r6 | 101 | and r12, r12, r10 |
98 | orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val | 102 | orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val |
99 | str r5, [r4] | 103 | str r12, [r11] |
100 | mov r5, #0x800 @ wait for the clock to stabilise | 104 | ldr r12, [r11] @ posted-write barrier for CM |
105 | mov r12, #0x800 @ wait for the clock to stabilise | ||
101 | cmp r3, #2 | 106 | cmp r3, #2 |
102 | bne wait_clk_stable | 107 | bne wait_clk_stable |
103 | bx lr | 108 | bx lr |
104 | wait_clk_stable: | 109 | wait_clk_stable: |
105 | subs r5, r5, #1 | 110 | subs r12, r12, #1 |
106 | bne wait_clk_stable | 111 | bne wait_clk_stable |
107 | nop | 112 | nop |
108 | nop | 113 | nop |
@@ -116,42 +121,42 @@ wait_clk_stable: | |||
116 | nop | 121 | nop |
117 | bx lr | 122 | bx lr |
118 | enable_sdrc: | 123 | enable_sdrc: |
119 | ldr r4, omap3_cm_iclken1_core | 124 | ldr r11, omap3_cm_iclken1_core |
120 | ldr r5, [r4] | 125 | ldr r12, [r11] |
121 | orr r5, r5, #0x2 @ enable iclk bit for SDRC | 126 | orr r12, r12, #0x2 @ enable iclk bit for SDRC |
122 | str r5, [r4] | 127 | str r12, [r11] |
123 | wait_sdrc_idle1: | 128 | wait_sdrc_idle1: |
124 | ldr r4, omap3_cm_idlest1_core | 129 | ldr r11, omap3_cm_idlest1_core |
125 | ldr r5, [r4] | 130 | ldr r12, [r11] |
126 | and r5, r5, #0x2 | 131 | and r12, r12, #0x2 |
127 | cmp r5, #0 | 132 | cmp r12, #0 |
128 | bne wait_sdrc_idle1 | 133 | bne wait_sdrc_idle1 |
129 | ldr r4, omap3_sdrc_power | 134 | restore_sdrc_power_val: |
130 | ldr r5, [r4] | 135 | ldr r11, omap3_sdrc_power |
131 | bic r5, r5, #0x40 | 136 | str r9, [r11] @ restore SDRC_POWER, no barrier needed |
132 | str r5, [r4] | ||
133 | bx lr | 137 | bx lr |
134 | wait_dll_lock: | 138 | wait_dll_lock: |
135 | ldr r4, omap3_sdrc_dlla_status | 139 | ldr r11, omap3_sdrc_dlla_status |
136 | ldr r5, [r4] | 140 | ldr r12, [r11] |
137 | and r5, r5, #0x4 | 141 | and r12, r12, #0x4 |
138 | cmp r5, #0x4 | 142 | cmp r12, #0x4 |
139 | bne wait_dll_lock | 143 | bne wait_dll_lock |
140 | bx lr | 144 | bx lr |
141 | wait_dll_unlock: | 145 | wait_dll_unlock: |
142 | ldr r4, omap3_sdrc_dlla_status | 146 | ldr r11, omap3_sdrc_dlla_status |
143 | ldr r5, [r4] | 147 | ldr r12, [r11] |
144 | and r5, r5, #0x4 | 148 | and r12, r12, #0x4 |
145 | cmp r5, #0x0 | 149 | cmp r12, #0x0 |
146 | bne wait_dll_unlock | 150 | bne wait_dll_unlock |
147 | bx lr | 151 | bx lr |
148 | configure_sdrc: | 152 | configure_sdrc: |
149 | ldr r4, omap3_sdrc_rfr_ctrl | 153 | ldr r11, omap3_sdrc_rfr_ctrl |
150 | str r0, [r4] | 154 | str r0, [r11] |
151 | ldr r4, omap3_sdrc_actim_ctrla | 155 | ldr r11, omap3_sdrc_actim_ctrla |
152 | str r1, [r4] | 156 | str r1, [r11] |
153 | ldr r4, omap3_sdrc_actim_ctrlb | 157 | ldr r11, omap3_sdrc_actim_ctrlb |
154 | str r2, [r4] | 158 | str r2, [r11] |
159 | ldr r2, [r11] @ posted-write barrier for SDRC | ||
155 | bx lr | 160 | bx lr |
156 | 161 | ||
157 | omap3_sdrc_power: | 162 | omap3_sdrc_power: |