aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig22
-rw-r--r--arch/arm/mach-omap2/Makefile12
-rw-r--r--arch/arm/mach-omap2/board-ldp.c86
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c244
-rw-r--r--arch/arm/mach-omap2/board-overo.c242
-rw-r--r--arch/arm/mach-omap2/clock.c64
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/clock24xx.h238
-rw-r--r--arch/arm/mach-omap2/clock34xx.c31
-rw-r--r--arch/arm/mach-omap2/clock34xx.h248
-rw-r--r--arch/arm/mach-omap2/clockdomain.c623
-rw-r--r--arch/arm/mach-omap2/clockdomains.h305
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h24
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h42
-rw-r--r--arch/arm/mach-omap2/cm.h2
-rw-r--r--arch/arm/mach-omap2/devices.c225
-rw-r--r--arch/arm/mach-omap2/gpmc.c88
-rw-r--r--arch/arm/mach-omap2/id.c39
-rw-r--r--arch/arm/mach-omap2/io.c152
-rw-r--r--arch/arm/mach-omap2/irq.c81
-rw-r--r--arch/arm/mach-omap2/mcbsp.c151
-rw-r--r--arch/arm/mach-omap2/memory.c14
-rw-r--r--arch/arm/mach-omap2/memory.h7
-rw-r--r--arch/arm/mach-omap2/mux.c245
-rw-r--r--arch/arm/mach-omap2/powerdomain.c1113
-rw-r--r--arch/arm/mach-omap2/powerdomains.h187
-rw-r--r--arch/arm/mach-omap2/powerdomains24xx.h200
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h327
-rw-r--r--arch/arm/mach-omap2/prcm-common.h3
-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h12
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h11
-rw-r--r--arch/arm/mach-omap2/prm.h5
-rw-r--r--arch/arm/mach-omap2/serial.c116
-rw-r--r--arch/arm/mach-omap2/sleep24xx.S (renamed from arch/arm/mach-omap2/sleep.S)32
-rw-r--r--arch/arm/mach-omap2/sram34xx.S179
35 files changed, 4941 insertions, 431 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7069c9d536f1..4832fcc7d04a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,8 +15,17 @@ config ARCH_OMAP2430
15 bool "OMAP2430 support" 15 bool "OMAP2430 support"
16 depends on ARCH_OMAP24XX 16 depends on ARCH_OMAP24XX
17 17
18config ARCH_OMAP34XX
19 bool "OMAP34xx Based System"
20 depends on ARCH_OMAP3
21
22config ARCH_OMAP3430
23 bool "OMAP3430 support"
24 depends on ARCH_OMAP3 && ARCH_OMAP34XX
25 select ARCH_OMAP_OTG
26
18comment "OMAP Board Type" 27comment "OMAP Board Type"
19 depends on ARCH_OMAP2 28 depends on ARCH_OMAP2 || ARCH_OMAP3
20 29
21config MACH_OMAP_GENERIC 30config MACH_OMAP_GENERIC
22 bool "Generic OMAP board" 31 bool "Generic OMAP board"
@@ -35,3 +44,14 @@ config MACH_OMAP_2430SDP
35 bool "OMAP 2430 SDP board" 44 bool "OMAP 2430 SDP board"
36 depends on ARCH_OMAP2 && ARCH_OMAP24XX 45 depends on ARCH_OMAP2 && ARCH_OMAP24XX
37 46
47config MACH_OMAP3_BEAGLE
48 bool "OMAP3 BEAGLE board"
49 depends on ARCH_OMAP3 && ARCH_OMAP34XX
50
51config MACH_OMAP_LDP
52 bool "OMAP3 LDP board"
53 depends on ARCH_OMAP3 && ARCH_OMAP34XX
54
55config MACH_OVERO
56 bool "Gumstix Overo board"
57 depends on ARCH_OMAP3 && ARCH_OMAP34XX
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 93ee990618ef..c69392372c99 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,16 +4,21 @@
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ 6obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
7 devices.o serial.o gpmc.o timer-gp.o 7 devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
8 clockdomain.o
8 9
9obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 10obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
10 11
11# Functions loaded to SRAM 12# Functions loaded to SRAM
12obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o 13obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
13obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o 14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
15obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
14 16
15# Power Management 17# Power Management
16obj-$(CONFIG_PM) += pm.o sleep.o 18ifeq ($(CONFIG_PM),y)
19obj-y += pm.o
20obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o
21endif
17 22
18# Clock framework 23# Clock framework
19obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o 24obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
@@ -24,4 +29,7 @@ obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
24obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 29obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
25obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o 30obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
26obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o 31obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
32obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
33obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
34obj-$(CONFIG_MACH_OVERO) += board-overo.o
27 35
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
new file mode 100644
index 000000000000..1ea59986aa7a
--- /dev/null
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -0,0 +1,86 @@
1/*
2 * linux/arch/arm/mach-omap2/board-ldp.c
3 *
4 * Copyright (C) 2008 Texas Instruments Inc.
5 * Nishant Kamat <nskamat@ti.com>
6 *
7 * Modified from mach-omap2/board-3430sdp.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/input.h>
19#include <linux/workqueue.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/ads7846.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <mach/board-ldp.h>
31#include <mach/mcspi.h>
32#include <mach/gpio.h>
33#include <mach/board.h>
34#include <mach/common.h>
35#include <mach/gpmc.h>
36
37#include <asm/io.h>
38#include <asm/delay.h>
39#include <mach/control.h>
40
41static void __init omap_ldp_init_irq(void)
42{
43 omap2_init_common_hw();
44 omap_init_irq();
45 omap_gpio_init();
46}
47
48static struct omap_uart_config ldp_uart_config __initdata = {
49 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
50};
51
52static struct omap_board_config_kernel ldp_config[] __initdata = {
53 { OMAP_TAG_UART, &ldp_uart_config },
54};
55
56static int __init omap_i2c_init(void)
57{
58 omap_register_i2c_bus(1, 2600, NULL, 0);
59 omap_register_i2c_bus(2, 400, NULL, 0);
60 omap_register_i2c_bus(3, 400, NULL, 0);
61 return 0;
62}
63
64static void __init omap_ldp_init(void)
65{
66 omap_i2c_init();
67 omap_board_config = ldp_config;
68 omap_board_config_size = ARRAY_SIZE(ldp_config);
69 omap_serial_init();
70}
71
72static void __init omap_ldp_map_io(void)
73{
74 omap2_set_globals_343x();
75 omap2_map_common_io();
76}
77
78MACHINE_START(OMAP_LDP, "OMAP LDP board")
79 .phys_io = 0x48000000,
80 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
81 .boot_params = 0x80000100,
82 .map_io = omap_ldp_map_io,
83 .init_irq = omap_ldp_init_irq,
84 .init_machine = omap_ldp_init,
85 .timer = &omap_timer,
86MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
new file mode 100644
index 000000000000..baa79674e9d5
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -0,0 +1,244 @@
1/*
2 * linux/arch/arm/mach-omap2/board-omap3beagle.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/leds.h>
23#include <linux/gpio.h>
24#include <linux/input.h>
25#include <linux/gpio_keys.h>
26
27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
31#include <mach/hardware.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/flash.h>
36
37#include <mach/board.h>
38#include <mach/common.h>
39#include <mach/gpmc.h>
40#include <mach/nand.h>
41
42
43#define GPMC_CS0_BASE 0x60
44#define GPMC_CS_SIZE 0x30
45
46#define NAND_BLOCK_SIZE SZ_128K
47
48static struct mtd_partition omap3beagle_nand_partitions[] = {
49 /* All the partition sizes are listed in terms of NAND block size */
50 {
51 .name = "X-Loader",
52 .offset = 0,
53 .size = 4 * NAND_BLOCK_SIZE,
54 .mask_flags = MTD_WRITEABLE, /* force read-only */
55 },
56 {
57 .name = "U-Boot",
58 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
59 .size = 15 * NAND_BLOCK_SIZE,
60 .mask_flags = MTD_WRITEABLE, /* force read-only */
61 },
62 {
63 .name = "U-Boot Env",
64 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
65 .size = 1 * NAND_BLOCK_SIZE,
66 },
67 {
68 .name = "Kernel",
69 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
70 .size = 32 * NAND_BLOCK_SIZE,
71 },
72 {
73 .name = "File System",
74 .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
75 .size = MTDPART_SIZ_FULL,
76 },
77};
78
79static struct omap_nand_platform_data omap3beagle_nand_data = {
80 .options = NAND_BUSWIDTH_16,
81 .parts = omap3beagle_nand_partitions,
82 .nr_parts = ARRAY_SIZE(omap3beagle_nand_partitions),
83 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
84 .nand_setup = NULL,
85 .dev_ready = NULL,
86};
87
88static struct resource omap3beagle_nand_resource = {
89 .flags = IORESOURCE_MEM,
90};
91
92static struct platform_device omap3beagle_nand_device = {
93 .name = "omap2-nand",
94 .id = -1,
95 .dev = {
96 .platform_data = &omap3beagle_nand_data,
97 },
98 .num_resources = 1,
99 .resource = &omap3beagle_nand_resource,
100};
101
102static struct omap_uart_config omap3_beagle_uart_config __initdata = {
103 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
104};
105
106static void __init omap3_beagle_init_irq(void)
107{
108 omap2_init_common_hw();
109 omap_init_irq();
110 omap_gpio_init();
111}
112
113static struct platform_device omap3_beagle_lcd_device = {
114 .name = "omap3beagle_lcd",
115 .id = -1,
116};
117
118static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
119 .ctrl_name = "internal",
120};
121
122static struct gpio_led gpio_leds[] = {
123 {
124 .name = "beagleboard::usr0",
125 .default_trigger = "heartbeat",
126 .gpio = 150,
127 },
128 {
129 .name = "beagleboard::usr1",
130 .default_trigger = "mmc0",
131 .gpio = 149,
132 },
133};
134
135static struct gpio_led_platform_data gpio_led_info = {
136 .leds = gpio_leds,
137 .num_leds = ARRAY_SIZE(gpio_leds),
138};
139
140static struct platform_device leds_gpio = {
141 .name = "leds-gpio",
142 .id = -1,
143 .dev = {
144 .platform_data = &gpio_led_info,
145 },
146};
147
148static struct gpio_keys_button gpio_buttons[] = {
149 {
150 .code = BTN_EXTRA,
151 .gpio = 7,
152 .desc = "user",
153 .wakeup = 1,
154 },
155};
156
157static struct gpio_keys_platform_data gpio_key_info = {
158 .buttons = gpio_buttons,
159 .nbuttons = ARRAY_SIZE(gpio_buttons),
160};
161
162static struct platform_device keys_gpio = {
163 .name = "gpio-keys",
164 .id = -1,
165 .dev = {
166 .platform_data = &gpio_key_info,
167 },
168};
169
170static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
171 { OMAP_TAG_UART, &omap3_beagle_uart_config },
172 { OMAP_TAG_LCD, &omap3_beagle_lcd_config },
173};
174
175static struct platform_device *omap3_beagle_devices[] __initdata = {
176 &omap3_beagle_lcd_device,
177 &leds_gpio,
178 &keys_gpio,
179};
180
181static void __init omap3beagle_flash_init(void)
182{
183 u8 cs = 0;
184 u8 nandcs = GPMC_CS_NUM + 1;
185
186 u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
187
188 /* find out the chip-select on which NAND exists */
189 while (cs < GPMC_CS_NUM) {
190 u32 ret = 0;
191 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
192
193 if ((ret & 0xC00) == 0x800) {
194 printk(KERN_INFO "Found NAND on CS%d\n", cs);
195 if (nandcs > GPMC_CS_NUM)
196 nandcs = cs;
197 }
198 cs++;
199 }
200
201 if (nandcs > GPMC_CS_NUM) {
202 printk(KERN_INFO "NAND: Unable to find configuration "
203 "in GPMC\n ");
204 return;
205 }
206
207 if (nandcs < GPMC_CS_NUM) {
208 omap3beagle_nand_data.cs = nandcs;
209 omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)
210 (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
211 omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
212
213 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
214 if (platform_device_register(&omap3beagle_nand_device) < 0)
215 printk(KERN_ERR "Unable to register NAND device\n");
216 }
217}
218
219static void __init omap3_beagle_init(void)
220{
221 platform_add_devices(omap3_beagle_devices,
222 ARRAY_SIZE(omap3_beagle_devices));
223 omap_board_config = omap3_beagle_config;
224 omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
225 omap_serial_init();
226 omap3beagle_flash_init();
227}
228
229static void __init omap3_beagle_map_io(void)
230{
231 omap2_set_globals_343x();
232 omap2_map_common_io();
233}
234
235MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
236 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
237 .phys_io = 0x48000000,
238 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
239 .boot_params = 0x80000100,
240 .map_io = omap3_beagle_map_io,
241 .init_irq = omap3_beagle_init_irq,
242 .init_machine = omap3_beagle_init,
243 .timer = &omap_timer,
244MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
new file mode 100644
index 000000000000..e09aa59a399c
--- /dev/null
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -0,0 +1,242 @@
1/*
2 * board-overo.c (Gumstix Overo)
3 *
4 * Initial code: Steve Sakoman <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/io.h>
27#include <linux/kernel.h>
28#include <linux/platform_device.h>
29
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/flash.h>
37#include <asm/mach/map.h>
38
39#include <mach/board-overo.h>
40#include <mach/board.h>
41#include <mach/common.h>
42#include <mach/gpio.h>
43#include <mach/gpmc.h>
44#include <mach/hardware.h>
45#include <mach/nand.h>
46
47#define NAND_BLOCK_SIZE SZ_128K
48#define GPMC_CS0_BASE 0x60
49#define GPMC_CS_SIZE 0x30
50
51static struct mtd_partition overo_nand_partitions[] = {
52 {
53 .name = "xloader",
54 .offset = 0, /* Offset = 0x00000 */
55 .size = 4 * NAND_BLOCK_SIZE,
56 .mask_flags = MTD_WRITEABLE
57 },
58 {
59 .name = "uboot",
60 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
61 .size = 14 * NAND_BLOCK_SIZE,
62 },
63 {
64 .name = "uboot environment",
65 .offset = MTDPART_OFS_APPEND, /* Offset = 0x240000 */
66 .size = 2 * NAND_BLOCK_SIZE,
67 },
68 {
69 .name = "linux",
70 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
71 .size = 32 * NAND_BLOCK_SIZE,
72 },
73 {
74 .name = "rootfs",
75 .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
76 .size = MTDPART_SIZ_FULL,
77 },
78};
79
80static struct omap_nand_platform_data overo_nand_data = {
81 .parts = overo_nand_partitions,
82 .nr_parts = ARRAY_SIZE(overo_nand_partitions),
83 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
84};
85
86static struct resource overo_nand_resource = {
87 .flags = IORESOURCE_MEM,
88};
89
90static struct platform_device overo_nand_device = {
91 .name = "omap2-nand",
92 .id = -1,
93 .dev = {
94 .platform_data = &overo_nand_data,
95 },
96 .num_resources = 1,
97 .resource = &overo_nand_resource,
98};
99
100
101static void __init overo_flash_init(void)
102{
103 u8 cs = 0;
104 u8 nandcs = GPMC_CS_NUM + 1;
105
106 u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
107
108 /* find out the chip-select on which NAND exists */
109 while (cs < GPMC_CS_NUM) {
110 u32 ret = 0;
111 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
112
113 if ((ret & 0xC00) == 0x800) {
114 printk(KERN_INFO "Found NAND on CS%d\n", cs);
115 if (nandcs > GPMC_CS_NUM)
116 nandcs = cs;
117 }
118 cs++;
119 }
120
121 if (nandcs > GPMC_CS_NUM) {
122 printk(KERN_INFO "NAND: Unable to find configuration "
123 "in GPMC\n ");
124 return;
125 }
126
127 if (nandcs < GPMC_CS_NUM) {
128 overo_nand_data.cs = nandcs;
129 overo_nand_data.gpmc_cs_baseaddr = (void *)
130 (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
131 overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
132
133 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
134 if (platform_device_register(&overo_nand_device) < 0)
135 printk(KERN_ERR "Unable to register NAND device\n");
136 }
137}
138static struct omap_uart_config overo_uart_config __initdata = {
139 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
140};
141
142static int __init overo_i2c_init(void)
143{
144 /* i2c2 pins are used for gpio */
145 omap_register_i2c_bus(3, 400, NULL, 0);
146 return 0;
147}
148
149static void __init overo_init_irq(void)
150{
151 omap2_init_common_hw();
152 omap_init_irq();
153 omap_gpio_init();
154}
155
156static struct platform_device overo_lcd_device = {
157 .name = "overo_lcd",
158 .id = -1,
159};
160
161static struct omap_lcd_config overo_lcd_config __initdata = {
162 .ctrl_name = "internal",
163};
164
165static struct omap_board_config_kernel overo_config[] __initdata = {
166 { OMAP_TAG_UART, &overo_uart_config },
167 { OMAP_TAG_LCD, &overo_lcd_config },
168};
169
170static struct platform_device *overo_devices[] __initdata = {
171 &overo_lcd_device,
172};
173
174static void __init overo_init(void)
175{
176 overo_i2c_init();
177 platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
178 omap_board_config = overo_config;
179 omap_board_config_size = ARRAY_SIZE(overo_config);
180 omap_serial_init();
181 overo_flash_init();
182
183 if ((gpio_request(OVERO_GPIO_W2W_NRESET,
184 "OVERO_GPIO_W2W_NRESET") == 0) &&
185 (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
186 gpio_export(OVERO_GPIO_W2W_NRESET, 0);
187 gpio_set_value(OVERO_GPIO_W2W_NRESET, 0);
188 udelay(10);
189 gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
190 } else {
191 printk(KERN_ERR "could not obtain gpio for "
192 "OVERO_GPIO_W2W_NRESET\n");
193 }
194
195 if ((gpio_request(OVERO_GPIO_BT_XGATE, "OVERO_GPIO_BT_XGATE") == 0) &&
196 (gpio_direction_output(OVERO_GPIO_BT_XGATE, 0) == 0))
197 gpio_export(OVERO_GPIO_BT_XGATE, 0);
198 else
199 printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_BT_XGATE\n");
200
201 if ((gpio_request(OVERO_GPIO_BT_NRESET, "OVERO_GPIO_BT_NRESET") == 0) &&
202 (gpio_direction_output(OVERO_GPIO_BT_NRESET, 1) == 0)) {
203 gpio_export(OVERO_GPIO_BT_NRESET, 0);
204 gpio_set_value(OVERO_GPIO_BT_NRESET, 0);
205 mdelay(6);
206 gpio_set_value(OVERO_GPIO_BT_NRESET, 1);
207 } else {
208 printk(KERN_ERR "could not obtain gpio for "
209 "OVERO_GPIO_BT_NRESET\n");
210 }
211
212 if ((gpio_request(OVERO_GPIO_USBH_CPEN, "OVERO_GPIO_USBH_CPEN") == 0) &&
213 (gpio_direction_output(OVERO_GPIO_USBH_CPEN, 1) == 0))
214 gpio_export(OVERO_GPIO_USBH_CPEN, 0);
215 else
216 printk(KERN_ERR "could not obtain gpio for "
217 "OVERO_GPIO_USBH_CPEN\n");
218
219 if ((gpio_request(OVERO_GPIO_USBH_NRESET,
220 "OVERO_GPIO_USBH_NRESET") == 0) &&
221 (gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0))
222 gpio_export(OVERO_GPIO_USBH_NRESET, 0);
223 else
224 printk(KERN_ERR "could not obtain gpio for "
225 "OVERO_GPIO_USBH_NRESET\n");
226}
227
228static void __init overo_map_io(void)
229{
230 omap2_set_globals_343x();
231 omap2_map_common_io();
232}
233
234MACHINE_START(OVERO, "Gumstix Overo")
235 .phys_io = 0x48000000,
236 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
237 .boot_params = 0x80000100,
238 .map_io = overo_map_io,
239 .init_irq = overo_init_irq,
240 .init_machine = overo_init,
241 .timer = &omap_timer,
242MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 97cde3d3611d..ad721e0cbf7a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -25,6 +25,7 @@
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26 26
27#include <mach/clock.h> 27#include <mach/clock.h>
28#include <mach/clockdomain.h>
28#include <mach/sram.h> 29#include <mach/sram.h>
29#include <mach/cpu.h> 30#include <mach/cpu.h>
30#include <asm/div64.h> 31#include <asm/div64.h>
@@ -61,10 +62,36 @@
61u8 cpu_mask; 62u8 cpu_mask;
62 63
63/*------------------------------------------------------------------------- 64/*-------------------------------------------------------------------------
64 * Omap2 specific clock functions 65 * OMAP2/3 specific clock functions
65 *-------------------------------------------------------------------------*/ 66 *-------------------------------------------------------------------------*/
66 67
67/** 68/**
69 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
70 * @clk: OMAP clock struct ptr to use
71 *
72 * Convert a clockdomain name stored in a struct clk 'clk' into a
73 * clockdomain pointer, and save it into the struct clk. Intended to be
74 * called during clk_register(). No return value.
75 */
76void omap2_init_clk_clkdm(struct clk *clk)
77{
78 struct clockdomain *clkdm;
79
80 if (!clk->clkdm_name)
81 return;
82
83 clkdm = clkdm_lookup(clk->clkdm_name);
84 if (clkdm) {
85 pr_debug("clock: associated clk %s to clkdm %s\n",
86 clk->name, clk->clkdm_name);
87 clk->clkdm = clkdm;
88 } else {
89 pr_debug("clock: could not associate clk %s to "
90 "clkdm %s\n", clk->name, clk->clkdm_name);
91 }
92}
93
94/**
68 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 95 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
69 * @clk: OMAP clock struct ptr to use 96 * @clk: OMAP clock struct ptr to use
70 * 97 *
@@ -250,7 +277,7 @@ int _omap2_clk_enable(struct clk *clk)
250 if (clk->enable) 277 if (clk->enable)
251 return clk->enable(clk); 278 return clk->enable(clk);
252 279
253 if (unlikely(clk->enable_reg == 0)) { 280 if (unlikely(clk->enable_reg == NULL)) {
254 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 281 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
255 clk->name); 282 clk->name);
256 return 0; /* REVISIT: -EINVAL */ 283 return 0; /* REVISIT: -EINVAL */
@@ -282,7 +309,7 @@ void _omap2_clk_disable(struct clk *clk)
282 return; 309 return;
283 } 310 }
284 311
285 if (clk->enable_reg == 0) { 312 if (clk->enable_reg == NULL) {
286 /* 313 /*
287 * 'Independent' here refers to a clock which is not 314 * 'Independent' here refers to a clock which is not
288 * controlled by its parent. 315 * controlled by its parent.
@@ -307,6 +334,9 @@ void omap2_clk_disable(struct clk *clk)
307 _omap2_clk_disable(clk); 334 _omap2_clk_disable(clk);
308 if (likely((u32)clk->parent)) 335 if (likely((u32)clk->parent))
309 omap2_clk_disable(clk->parent); 336 omap2_clk_disable(clk->parent);
337 if (clk->clkdm)
338 omap2_clkdm_clk_disable(clk->clkdm, clk);
339
310 } 340 }
311} 341}
312 342
@@ -323,11 +353,19 @@ int omap2_clk_enable(struct clk *clk)
323 return ret; 353 return ret;
324 } 354 }
325 355
356 if (clk->clkdm)
357 omap2_clkdm_clk_enable(clk->clkdm, clk);
358
326 ret = _omap2_clk_enable(clk); 359 ret = _omap2_clk_enable(clk);
327 360
328 if (unlikely(ret != 0) && clk->parent) { 361 if (unlikely(ret != 0)) {
329 omap2_clk_disable(clk->parent); 362 if (clk->clkdm)
330 clk->usecount--; 363 omap2_clkdm_clk_disable(clk->clkdm, clk);
364
365 if (clk->parent) {
366 omap2_clk_disable(clk->parent);
367 clk->usecount--;
368 }
331 } 369 }
332 } 370 }
333 371
@@ -476,7 +514,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
476/* Given a clock and a rate apply a clock specific rounding function */ 514/* Given a clock and a rate apply a clock specific rounding function */
477long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 515long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
478{ 516{
479 if (clk->round_rate != 0) 517 if (clk->round_rate != NULL)
480 return clk->round_rate(clk, rate); 518 return clk->round_rate(clk, rate);
481 519
482 if (clk->flags & RATE_FIXED) 520 if (clk->flags & RATE_FIXED)
@@ -565,7 +603,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
565 */ 603 */
566void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) 604void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
567{ 605{
568 if (unlikely((clk->clksel_reg == 0) || (clk->clksel_mask == 0))) 606 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
569 return NULL; 607 return NULL;
570 608
571 *field_mask = clk->clksel_mask; 609 *field_mask = clk->clksel_mask;
@@ -585,7 +623,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk)
585 void __iomem *div_addr; 623 void __iomem *div_addr;
586 624
587 div_addr = omap2_get_clksel(clk, &field_mask); 625 div_addr = omap2_get_clksel(clk, &field_mask);
588 if (div_addr == 0) 626 if (div_addr == NULL)
589 return 0; 627 return 0;
590 628
591 field_val = __raw_readl(div_addr) & field_mask; 629 field_val = __raw_readl(div_addr) & field_mask;
@@ -604,7 +642,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
604 return -EINVAL; 642 return -EINVAL;
605 643
606 div_addr = omap2_get_clksel(clk, &field_mask); 644 div_addr = omap2_get_clksel(clk, &field_mask);
607 if (div_addr == 0) 645 if (div_addr == NULL)
608 return -EINVAL; 646 return -EINVAL;
609 647
610 field_val = omap2_divisor_to_clksel(clk, new_div); 648 field_val = omap2_divisor_to_clksel(clk, new_div);
@@ -642,7 +680,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
642 return -EINVAL; 680 return -EINVAL;
643 681
644 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 682 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
645 if (clk->set_rate != 0) 683 if (clk->set_rate != NULL)
646 ret = clk->set_rate(clk, rate); 684 ret = clk->set_rate(clk, rate);
647 685
648 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 686 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
@@ -663,7 +701,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
663 const struct clksel_rate *clkr; 701 const struct clksel_rate *clkr;
664 702
665 *parent_div = 0; 703 *parent_div = 0;
666 *src_addr = 0; 704 *src_addr = NULL;
667 705
668 clks = omap2_get_clksel_by_parent(clk, src_clk); 706 clks = omap2_get_clksel_by_parent(clk, src_clk);
669 if (clks == NULL) 707 if (clks == NULL)
@@ -704,7 +742,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
704 742
705 field_val = omap2_clksel_get_src_field(&src_addr, new_parent, 743 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
706 &field_mask, clk, &parent_div); 744 &field_mask, clk, &parent_div);
707 if (src_addr == 0) 745 if (src_addr == NULL)
708 return -EINVAL; 746 return -EINVAL;
709 747
710 if (clk->usecount > 0) 748 if (clk->usecount > 0)
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 626e5fa93b6a..1fb330e0847d 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */ 21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000 22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23 23
24int omap2_clk_init(void);
24int omap2_clk_enable(struct clk *clk); 25int omap2_clk_enable(struct clk *clk);
25void omap2_clk_disable(struct clk *clk); 26void omap2_clk_disable(struct clk *clk);
26long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 27long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
@@ -36,6 +37,7 @@ void omap2_clk_disable_unused(struct clk *clk);
36#endif 37#endif
37 38
38void omap2_clksel_recalc(struct clk *clk); 39void omap2_clksel_recalc(struct clk *clk);
40void omap2_init_clk_clkdm(struct clk *clk);
39void omap2_init_clksel_parent(struct clk *clk); 41void omap2_init_clksel_parent(struct clk *clk);
40u32 omap2_clksel_get_divisor(struct clk *clk); 42u32 omap2_clksel_get_divisor(struct clk *clk);
41u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 43u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index be4e25554e05..242a19d86ccd 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -626,6 +626,7 @@ static struct clk func_32k_ck = {
626 .rate = 32000, 626 .rate = 32000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
629 .clkdm_name = "wkup_clkdm",
629 .recalc = &propagate_rate, 630 .recalc = &propagate_rate,
630}; 631};
631 632
@@ -634,17 +635,19 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
634 .name = "osc_ck", 635 .name = "osc_ck",
635 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
636 RATE_PROPAGATES, 637 RATE_PROPAGATES,
638 .clkdm_name = "wkup_clkdm",
637 .enable = &omap2_enable_osc_ck, 639 .enable = &omap2_enable_osc_ck,
638 .disable = &omap2_disable_osc_ck, 640 .disable = &omap2_disable_osc_ck,
639 .recalc = &omap2_osc_clk_recalc, 641 .recalc = &omap2_osc_clk_recalc,
640}; 642};
641 643
642/* With out modem likely 12MHz, with modem likely 13MHz */ 644/* Without modem likely 12MHz, with modem likely 13MHz */
643static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ 645static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
644 .name = "sys_ck", /* ~ ref_clk also */ 646 .name = "sys_ck", /* ~ ref_clk also */
645 .parent = &osc_ck, 647 .parent = &osc_ck,
646 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 648 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
647 ALWAYS_ENABLED | RATE_PROPAGATES, 649 ALWAYS_ENABLED | RATE_PROPAGATES,
650 .clkdm_name = "wkup_clkdm",
648 .recalc = &omap2_sys_clk_recalc, 651 .recalc = &omap2_sys_clk_recalc,
649}; 652};
650 653
@@ -653,6 +656,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
653 .rate = 54000000, 656 .rate = 54000000,
654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
655 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 658 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
659 .clkdm_name = "wkup_clkdm",
656 .recalc = &propagate_rate, 660 .recalc = &propagate_rate,
657}; 661};
658 662
@@ -684,6 +688,7 @@ static struct clk dpll_ck = {
684 .dpll_data = &dpll_dd, 688 .dpll_data = &dpll_dd,
685 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
686 RATE_PROPAGATES | ALWAYS_ENABLED, 690 RATE_PROPAGATES | ALWAYS_ENABLED,
691 .clkdm_name = "wkup_clkdm",
687 .recalc = &omap2_dpllcore_recalc, 692 .recalc = &omap2_dpllcore_recalc,
688 .set_rate = &omap2_reprogram_dpllcore, 693 .set_rate = &omap2_reprogram_dpllcore,
689}; 694};
@@ -694,6 +699,7 @@ static struct clk apll96_ck = {
694 .rate = 96000000, 699 .rate = 96000000,
695 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
696 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, 701 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
702 .clkdm_name = "wkup_clkdm",
697 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
698 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 704 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
699 .enable = &omap2_clk_fixed_enable, 705 .enable = &omap2_clk_fixed_enable,
@@ -707,6 +713,7 @@ static struct clk apll54_ck = {
707 .rate = 54000000, 713 .rate = 54000000,
708 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
709 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, 715 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
716 .clkdm_name = "wkup_clkdm",
710 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 717 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
711 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 718 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
712 .enable = &omap2_clk_fixed_enable, 719 .enable = &omap2_clk_fixed_enable,
@@ -741,6 +748,7 @@ static struct clk func_54m_ck = {
741 .parent = &apll54_ck, /* can also be alt_clk */ 748 .parent = &apll54_ck, /* can also be alt_clk */
742 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
743 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 750 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
751 .clkdm_name = "wkup_clkdm",
744 .init = &omap2_init_clksel_parent, 752 .init = &omap2_init_clksel_parent,
745 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
746 .clksel_mask = OMAP24XX_54M_SOURCE, 754 .clksel_mask = OMAP24XX_54M_SOURCE,
@@ -753,6 +761,7 @@ static struct clk core_ck = {
753 .parent = &dpll_ck, /* can also be 32k */ 761 .parent = &dpll_ck, /* can also be 32k */
754 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 762 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
755 ALWAYS_ENABLED | RATE_PROPAGATES, 763 ALWAYS_ENABLED | RATE_PROPAGATES,
764 .clkdm_name = "wkup_clkdm",
756 .recalc = &followparent_recalc, 765 .recalc = &followparent_recalc,
757}; 766};
758 767
@@ -779,6 +788,7 @@ static struct clk func_96m_ck = {
779 .parent = &apll96_ck, 788 .parent = &apll96_ck,
780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 789 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
781 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 790 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
791 .clkdm_name = "wkup_clkdm",
782 .init = &omap2_init_clksel_parent, 792 .init = &omap2_init_clksel_parent,
783 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 793 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
784 .clksel_mask = OMAP2430_96M_SOURCE, 794 .clksel_mask = OMAP2430_96M_SOURCE,
@@ -811,6 +821,7 @@ static struct clk func_48m_ck = {
811 .parent = &apll96_ck, /* 96M or Alt */ 821 .parent = &apll96_ck, /* 96M or Alt */
812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
813 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 823 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
824 .clkdm_name = "wkup_clkdm",
814 .init = &omap2_init_clksel_parent, 825 .init = &omap2_init_clksel_parent,
815 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
816 .clksel_mask = OMAP24XX_48M_SOURCE, 827 .clksel_mask = OMAP24XX_48M_SOURCE,
@@ -826,6 +837,7 @@ static struct clk func_12m_ck = {
826 .fixed_div = 4, 837 .fixed_div = 4,
827 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 838 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
828 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, 839 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
840 .clkdm_name = "wkup_clkdm",
829 .recalc = &omap2_fixed_divisor_recalc, 841 .recalc = &omap2_fixed_divisor_recalc,
830}; 842};
831 843
@@ -878,6 +890,7 @@ static struct clk sys_clkout_src = {
878 .parent = &func_54m_ck, 890 .parent = &func_54m_ck,
879 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 891 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
880 RATE_PROPAGATES, 892 RATE_PROPAGATES,
893 .clkdm_name = "wkup_clkdm",
881 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 894 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
882 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, 895 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
883 .init = &omap2_init_clksel_parent, 896 .init = &omap2_init_clksel_parent,
@@ -908,6 +921,7 @@ static struct clk sys_clkout = {
908 .parent = &sys_clkout_src, 921 .parent = &sys_clkout_src,
909 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
910 PARENT_CONTROLS_CLOCK, 923 PARENT_CONTROLS_CLOCK,
924 .clkdm_name = "wkup_clkdm",
911 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
912 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, 926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
913 .clksel = sys_clkout_clksel, 927 .clksel = sys_clkout_clksel,
@@ -921,6 +935,7 @@ static struct clk sys_clkout2_src = {
921 .name = "sys_clkout2_src", 935 .name = "sys_clkout2_src",
922 .parent = &func_54m_ck, 936 .parent = &func_54m_ck,
923 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, 937 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
938 .clkdm_name = "wkup_clkdm",
924 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 939 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
925 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, 940 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
926 .init = &omap2_init_clksel_parent, 941 .init = &omap2_init_clksel_parent,
@@ -942,6 +957,7 @@ static struct clk sys_clkout2 = {
942 .name = "sys_clkout2", 957 .name = "sys_clkout2",
943 .parent = &sys_clkout2_src, 958 .parent = &sys_clkout2_src,
944 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, 959 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
960 .clkdm_name = "wkup_clkdm",
945 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 961 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
946 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, 962 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
947 .clksel = sys_clkout2_clksel, 963 .clksel = sys_clkout2_clksel,
@@ -954,6 +970,7 @@ static struct clk emul_ck = {
954 .name = "emul_ck", 970 .name = "emul_ck",
955 .parent = &func_54m_ck, 971 .parent = &func_54m_ck,
956 .flags = CLOCK_IN_OMAP242X, 972 .flags = CLOCK_IN_OMAP242X,
973 .clkdm_name = "wkup_clkdm",
957 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, 974 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
958 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, 975 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
959 .recalc = &followparent_recalc, 976 .recalc = &followparent_recalc,
@@ -990,12 +1007,13 @@ static struct clk mpu_ck = { /* Control cpu */
990 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
991 ALWAYS_ENABLED | DELAYED_APP | 1008 ALWAYS_ENABLED | DELAYED_APP |
992 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1009 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1010 .clkdm_name = "mpu_clkdm",
993 .init = &omap2_init_clksel_parent, 1011 .init = &omap2_init_clksel_parent,
994 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 1012 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
995 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, 1013 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
996 .clksel = mpu_clksel, 1014 .clksel = mpu_clksel,
997 .recalc = &omap2_clksel_recalc, 1015 .recalc = &omap2_clksel_recalc,
998 .round_rate = &omap2_clksel_round_rate, 1016 .round_rate = &omap2_clksel_round_rate,
999 .set_rate = &omap2_clksel_set_rate 1017 .set_rate = &omap2_clksel_set_rate
1000}; 1018};
1001 1019
@@ -1031,6 +1049,7 @@ static struct clk dsp_fck = {
1031 .parent = &core_ck, 1049 .parent = &core_ck,
1032 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1050 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1033 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1051 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1052 .clkdm_name = "dsp_clkdm",
1034 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1035 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1054 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1036 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1055 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
@@ -1054,10 +1073,7 @@ static const struct clksel dsp_irate_ick_clksel[] = {
1054 { .parent = NULL } 1073 { .parent = NULL }
1055}; 1074};
1056 1075
1057/* 1076/* This clock does not exist as such in the TRM. */
1058 * This clock does not exist as such in the TRM, but is added to
1059 * separate source selection from XXX
1060 */
1061static struct clk dsp_irate_ick = { 1077static struct clk dsp_irate_ick = {
1062 .name = "dsp_irate_ick", 1078 .name = "dsp_irate_ick",
1063 .parent = &dsp_fck, 1079 .parent = &dsp_fck,
@@ -1089,11 +1105,17 @@ static struct clk iva2_1_ick = {
1089 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1105 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1090}; 1106};
1091 1107
1108/*
1109 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
1110 * the C54x, but which is contained in the DSP powerdomain. Does not
1111 * exist on later OMAPs.
1112 */
1092static struct clk iva1_ifck = { 1113static struct clk iva1_ifck = {
1093 .name = "iva1_ifck", 1114 .name = "iva1_ifck",
1094 .parent = &core_ck, 1115 .parent = &core_ck,
1095 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | 1116 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1096 RATE_PROPAGATES | DELAYED_APP, 1117 RATE_PROPAGATES | DELAYED_APP,
1118 .clkdm_name = "iva1_clkdm",
1097 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1119 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1098 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, 1120 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
1099 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1121 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
@@ -1109,6 +1131,7 @@ static struct clk iva1_mpu_int_ifck = {
1109 .name = "iva1_mpu_int_ifck", 1131 .name = "iva1_mpu_int_ifck",
1110 .parent = &iva1_ifck, 1132 .parent = &iva1_ifck,
1111 .flags = CLOCK_IN_OMAP242X, 1133 .flags = CLOCK_IN_OMAP242X,
1134 .clkdm_name = "iva1_clkdm",
1112 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1135 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1113 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, 1136 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1114 .fixed_div = 2, 1137 .fixed_div = 2,
@@ -1156,6 +1179,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1156 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1157 ALWAYS_ENABLED | DELAYED_APP | 1180 ALWAYS_ENABLED | DELAYED_APP |
1158 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1181 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1182 .clkdm_name = "core_l3_clkdm",
1159 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1160 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 1184 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
1161 .clksel = core_l3_clksel, 1185 .clksel = core_l3_clksel,
@@ -1177,11 +1201,13 @@ static const struct clksel usb_l4_ick_clksel[] = {
1177 { .parent = NULL }, 1201 { .parent = NULL },
1178}; 1202};
1179 1203
1204/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1180static struct clk usb_l4_ick = { /* FS-USB interface clock */ 1205static struct clk usb_l4_ick = { /* FS-USB interface clock */
1181 .name = "usb_l4_ick", 1206 .name = "usb_l4_ick",
1182 .parent = &core_l3_ck, 1207 .parent = &core_l3_ck,
1183 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1184 DELAYED_APP | CONFIG_PARTICIPANT, 1209 DELAYED_APP | CONFIG_PARTICIPANT,
1210 .clkdm_name = "core_l4_clkdm",
1185 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1186 .enable_bit = OMAP24XX_EN_USB_SHIFT, 1212 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1187 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1213 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
@@ -1193,10 +1219,42 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
1193}; 1219};
1194 1220
1195/* 1221/*
1222 * L4 clock management domain
1223 *
1224 * This domain contains lots of interface clocks from the L4 interface, some
1225 * functional clocks. Fixed APLL functional source clocks are managed in
1226 * this domain.
1227 */
1228static const struct clksel_rate l4_core_l3_rates[] = {
1229 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1230 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1231 { .div = 0 }
1232};
1233
1234static const struct clksel l4_clksel[] = {
1235 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1236 { .parent = NULL }
1237};
1238
1239static struct clk l4_ck = { /* used both as an ick and fck */
1240 .name = "l4_ck",
1241 .parent = &core_l3_ck,
1242 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1243 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1244 .clkdm_name = "core_l4_clkdm",
1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1247 .clksel = l4_clksel,
1248 .recalc = &omap2_clksel_recalc,
1249 .round_rate = &omap2_clksel_round_rate,
1250 .set_rate = &omap2_clksel_set_rate
1251};
1252
1253/*
1196 * SSI is in L3 management domain, its direct parent is core not l3, 1254 * SSI is in L3 management domain, its direct parent is core not l3,
1197 * many core power domain entities are grouped into the L3 clock 1255 * many core power domain entities are grouped into the L3 clock
1198 * domain. 1256 * domain.
1199 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK 1257 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
1200 * 1258 *
1201 * ssr = core/1/2/3/4/5, sst = 1/2 ssr. 1259 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
1202 */ 1260 */
@@ -1221,6 +1279,7 @@ static struct clk ssi_ssr_sst_fck = {
1221 .parent = &core_ck, 1279 .parent = &core_ck,
1222 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1280 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1223 DELAYED_APP, 1281 DELAYED_APP,
1282 .clkdm_name = "core_l3_clkdm",
1224 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1225 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1226 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1285 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
@@ -1231,6 +1290,7 @@ static struct clk ssi_ssr_sst_fck = {
1231 .set_rate = &omap2_clksel_set_rate 1290 .set_rate = &omap2_clksel_set_rate
1232}; 1291};
1233 1292
1293
1234/* 1294/*
1235 * GFX clock domain 1295 * GFX clock domain
1236 * Clocks: 1296 * Clocks:
@@ -1254,6 +1314,7 @@ static struct clk gfx_3d_fck = {
1254 .name = "gfx_3d_fck", 1314 .name = "gfx_3d_fck",
1255 .parent = &core_l3_ck, 1315 .parent = &core_l3_ck,
1256 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1316 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1317 .clkdm_name = "gfx_clkdm",
1257 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1318 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1258 .enable_bit = OMAP24XX_EN_3D_SHIFT, 1319 .enable_bit = OMAP24XX_EN_3D_SHIFT,
1259 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1320 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
@@ -1268,6 +1329,7 @@ static struct clk gfx_2d_fck = {
1268 .name = "gfx_2d_fck", 1329 .name = "gfx_2d_fck",
1269 .parent = &core_l3_ck, 1330 .parent = &core_l3_ck,
1270 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1332 .clkdm_name = "gfx_clkdm",
1271 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1272 .enable_bit = OMAP24XX_EN_2D_SHIFT, 1334 .enable_bit = OMAP24XX_EN_2D_SHIFT,
1273 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1335 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
@@ -1282,6 +1344,7 @@ static struct clk gfx_ick = {
1282 .name = "gfx_ick", /* From l3 */ 1344 .name = "gfx_ick", /* From l3 */
1283 .parent = &core_l3_ck, 1345 .parent = &core_l3_ck,
1284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1346 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1347 .clkdm_name = "gfx_clkdm",
1285 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1348 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1286 .enable_bit = OMAP_EN_GFX_SHIFT, 1349 .enable_bit = OMAP_EN_GFX_SHIFT,
1287 .recalc = &followparent_recalc, 1350 .recalc = &followparent_recalc,
@@ -1311,6 +1374,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
1311 .name = "mdm_ick", 1374 .name = "mdm_ick",
1312 .parent = &core_ck, 1375 .parent = &core_ck,
1313 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1376 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1377 .clkdm_name = "mdm_clkdm",
1314 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 1378 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1315 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 1379 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1316 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), 1380 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
@@ -1325,52 +1389,13 @@ static struct clk mdm_osc_ck = {
1325 .name = "mdm_osc_ck", 1389 .name = "mdm_osc_ck",
1326 .parent = &osc_ck, 1390 .parent = &osc_ck,
1327 .flags = CLOCK_IN_OMAP243X, 1391 .flags = CLOCK_IN_OMAP243X,
1392 .clkdm_name = "mdm_clkdm",
1328 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 1393 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1329 .enable_bit = OMAP2430_EN_OSC_SHIFT, 1394 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1330 .recalc = &followparent_recalc, 1395 .recalc = &followparent_recalc,
1331}; 1396};
1332 1397
1333/* 1398/*
1334 * L4 clock management domain
1335 *
1336 * This domain contains lots of interface clocks from the L4 interface, some
1337 * functional clocks. Fixed APLL functional source clocks are managed in
1338 * this domain.
1339 */
1340static const struct clksel_rate l4_core_l3_rates[] = {
1341 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
1342 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1343 { .div = 0 }
1344};
1345
1346static const struct clksel l4_clksel[] = {
1347 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
1348 { .parent = NULL }
1349};
1350
1351static struct clk l4_ck = { /* used both as an ick and fck */
1352 .name = "l4_ck",
1353 .parent = &core_l3_ck,
1354 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1355 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1356 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1357 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
1358 .clksel = l4_clksel,
1359 .recalc = &omap2_clksel_recalc,
1360 .round_rate = &omap2_clksel_round_rate,
1361 .set_rate = &omap2_clksel_set_rate
1362};
1363
1364static struct clk ssi_l4_ick = {
1365 .name = "ssi_l4_ick",
1366 .parent = &l4_ck,
1367 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1369 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1370 .recalc = &followparent_recalc,
1371};
1372
1373/*
1374 * DSS clock domain 1399 * DSS clock domain
1375 * CLOCKs: 1400 * CLOCKs:
1376 * DSS_L4_ICLK, DSS_L3_ICLK, 1401 * DSS_L4_ICLK, DSS_L3_ICLK,
@@ -1409,6 +1434,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1409 .name = "dss_ick", 1434 .name = "dss_ick",
1410 .parent = &l4_ck, /* really both l3 and l4 */ 1435 .parent = &l4_ck, /* really both l3 and l4 */
1411 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437 .clkdm_name = "dss_clkdm",
1412 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1413 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1439 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1414 .recalc = &followparent_recalc, 1440 .recalc = &followparent_recalc,
@@ -1419,6 +1445,7 @@ static struct clk dss1_fck = {
1419 .parent = &core_ck, /* Core or sys */ 1445 .parent = &core_ck, /* Core or sys */
1420 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1446 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1421 DELAYED_APP, 1447 DELAYED_APP,
1448 .clkdm_name = "dss_clkdm",
1422 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1423 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1450 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
1424 .init = &omap2_init_clksel_parent, 1451 .init = &omap2_init_clksel_parent,
@@ -1451,6 +1478,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
1451 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1478 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1452 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1453 DELAYED_APP, 1480 DELAYED_APP,
1481 .clkdm_name = "dss_clkdm",
1454 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1455 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 1483 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
1456 .init = &omap2_init_clksel_parent, 1484 .init = &omap2_init_clksel_parent,
@@ -1464,6 +1492,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
1464 .name = "dss_54m_fck", /* 54m tv clk */ 1492 .name = "dss_54m_fck", /* 54m tv clk */
1465 .parent = &func_54m_ck, 1493 .parent = &func_54m_ck,
1466 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1494 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1495 .clkdm_name = "dss_clkdm",
1467 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1468 .enable_bit = OMAP24XX_EN_TV_SHIFT, 1497 .enable_bit = OMAP24XX_EN_TV_SHIFT,
1469 .recalc = &followparent_recalc, 1498 .recalc = &followparent_recalc,
@@ -1491,6 +1520,7 @@ static struct clk gpt1_ick = {
1491 .name = "gpt1_ick", 1520 .name = "gpt1_ick",
1492 .parent = &l4_ck, 1521 .parent = &l4_ck,
1493 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1522 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523 .clkdm_name = "core_l4_clkdm",
1494 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1524 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1495 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1525 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1496 .recalc = &followparent_recalc, 1526 .recalc = &followparent_recalc,
@@ -1500,6 +1530,7 @@ static struct clk gpt1_fck = {
1500 .name = "gpt1_fck", 1530 .name = "gpt1_fck",
1501 .parent = &func_32k_ck, 1531 .parent = &func_32k_ck,
1502 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533 .clkdm_name = "core_l4_clkdm",
1503 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 1534 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1504 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1535 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
1505 .init = &omap2_init_clksel_parent, 1536 .init = &omap2_init_clksel_parent,
@@ -1515,6 +1546,7 @@ static struct clk gpt2_ick = {
1515 .name = "gpt2_ick", 1546 .name = "gpt2_ick",
1516 .parent = &l4_ck, 1547 .parent = &l4_ck,
1517 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549 .clkdm_name = "core_l4_clkdm",
1518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1519 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1551 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1520 .recalc = &followparent_recalc, 1552 .recalc = &followparent_recalc,
@@ -1524,6 +1556,7 @@ static struct clk gpt2_fck = {
1524 .name = "gpt2_fck", 1556 .name = "gpt2_fck",
1525 .parent = &func_32k_ck, 1557 .parent = &func_32k_ck,
1526 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1558 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559 .clkdm_name = "core_l4_clkdm",
1527 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1528 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1561 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
1529 .init = &omap2_init_clksel_parent, 1562 .init = &omap2_init_clksel_parent,
@@ -1537,6 +1570,7 @@ static struct clk gpt3_ick = {
1537 .name = "gpt3_ick", 1570 .name = "gpt3_ick",
1538 .parent = &l4_ck, 1571 .parent = &l4_ck,
1539 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573 .clkdm_name = "core_l4_clkdm",
1540 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1541 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1575 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1542 .recalc = &followparent_recalc, 1576 .recalc = &followparent_recalc,
@@ -1546,6 +1580,7 @@ static struct clk gpt3_fck = {
1546 .name = "gpt3_fck", 1580 .name = "gpt3_fck",
1547 .parent = &func_32k_ck, 1581 .parent = &func_32k_ck,
1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1582 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1583 .clkdm_name = "core_l4_clkdm",
1549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1550 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1585 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
1551 .init = &omap2_init_clksel_parent, 1586 .init = &omap2_init_clksel_parent,
@@ -1559,6 +1594,7 @@ static struct clk gpt4_ick = {
1559 .name = "gpt4_ick", 1594 .name = "gpt4_ick",
1560 .parent = &l4_ck, 1595 .parent = &l4_ck,
1561 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597 .clkdm_name = "core_l4_clkdm",
1562 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1563 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1599 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1564 .recalc = &followparent_recalc, 1600 .recalc = &followparent_recalc,
@@ -1568,6 +1604,7 @@ static struct clk gpt4_fck = {
1568 .name = "gpt4_fck", 1604 .name = "gpt4_fck",
1569 .parent = &func_32k_ck, 1605 .parent = &func_32k_ck,
1570 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1606 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607 .clkdm_name = "core_l4_clkdm",
1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1572 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1609 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
1573 .init = &omap2_init_clksel_parent, 1610 .init = &omap2_init_clksel_parent,
@@ -1581,6 +1618,7 @@ static struct clk gpt5_ick = {
1581 .name = "gpt5_ick", 1618 .name = "gpt5_ick",
1582 .parent = &l4_ck, 1619 .parent = &l4_ck,
1583 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621 .clkdm_name = "core_l4_clkdm",
1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1585 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1623 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1586 .recalc = &followparent_recalc, 1624 .recalc = &followparent_recalc,
@@ -1590,6 +1628,7 @@ static struct clk gpt5_fck = {
1590 .name = "gpt5_fck", 1628 .name = "gpt5_fck",
1591 .parent = &func_32k_ck, 1629 .parent = &func_32k_ck,
1592 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631 .clkdm_name = "core_l4_clkdm",
1593 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1633 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
1595 .init = &omap2_init_clksel_parent, 1634 .init = &omap2_init_clksel_parent,
@@ -1603,6 +1642,7 @@ static struct clk gpt6_ick = {
1603 .name = "gpt6_ick", 1642 .name = "gpt6_ick",
1604 .parent = &l4_ck, 1643 .parent = &l4_ck,
1605 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645 .clkdm_name = "core_l4_clkdm",
1606 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1607 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1647 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1608 .recalc = &followparent_recalc, 1648 .recalc = &followparent_recalc,
@@ -1612,6 +1652,7 @@ static struct clk gpt6_fck = {
1612 .name = "gpt6_fck", 1652 .name = "gpt6_fck",
1613 .parent = &func_32k_ck, 1653 .parent = &func_32k_ck,
1614 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655 .clkdm_name = "core_l4_clkdm",
1615 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1616 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1657 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
1617 .init = &omap2_init_clksel_parent, 1658 .init = &omap2_init_clksel_parent,
@@ -1634,6 +1675,7 @@ static struct clk gpt7_fck = {
1634 .name = "gpt7_fck", 1675 .name = "gpt7_fck",
1635 .parent = &func_32k_ck, 1676 .parent = &func_32k_ck,
1636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1677 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1678 .clkdm_name = "core_l4_clkdm",
1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1638 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1680 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1639 .init = &omap2_init_clksel_parent, 1681 .init = &omap2_init_clksel_parent,
@@ -1647,6 +1689,7 @@ static struct clk gpt8_ick = {
1647 .name = "gpt8_ick", 1689 .name = "gpt8_ick",
1648 .parent = &l4_ck, 1690 .parent = &l4_ck,
1649 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1691 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692 .clkdm_name = "core_l4_clkdm",
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1694 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1652 .recalc = &followparent_recalc, 1695 .recalc = &followparent_recalc,
@@ -1656,6 +1699,7 @@ static struct clk gpt8_fck = {
1656 .name = "gpt8_fck", 1699 .name = "gpt8_fck",
1657 .parent = &func_32k_ck, 1700 .parent = &func_32k_ck,
1658 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702 .clkdm_name = "core_l4_clkdm",
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1704 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1661 .init = &omap2_init_clksel_parent, 1705 .init = &omap2_init_clksel_parent,
@@ -1669,6 +1713,7 @@ static struct clk gpt9_ick = {
1669 .name = "gpt9_ick", 1713 .name = "gpt9_ick",
1670 .parent = &l4_ck, 1714 .parent = &l4_ck,
1671 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716 .clkdm_name = "core_l4_clkdm",
1672 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1673 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1718 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1674 .recalc = &followparent_recalc, 1719 .recalc = &followparent_recalc,
@@ -1678,6 +1723,7 @@ static struct clk gpt9_fck = {
1678 .name = "gpt9_fck", 1723 .name = "gpt9_fck",
1679 .parent = &func_32k_ck, 1724 .parent = &func_32k_ck,
1680 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1726 .clkdm_name = "core_l4_clkdm",
1681 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1682 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1728 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1683 .init = &omap2_init_clksel_parent, 1729 .init = &omap2_init_clksel_parent,
@@ -1691,6 +1737,7 @@ static struct clk gpt10_ick = {
1691 .name = "gpt10_ick", 1737 .name = "gpt10_ick",
1692 .parent = &l4_ck, 1738 .parent = &l4_ck,
1693 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740 .clkdm_name = "core_l4_clkdm",
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1742 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1696 .recalc = &followparent_recalc, 1743 .recalc = &followparent_recalc,
@@ -1700,6 +1747,7 @@ static struct clk gpt10_fck = {
1700 .name = "gpt10_fck", 1747 .name = "gpt10_fck",
1701 .parent = &func_32k_ck, 1748 .parent = &func_32k_ck,
1702 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1750 .clkdm_name = "core_l4_clkdm",
1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1704 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1752 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1705 .init = &omap2_init_clksel_parent, 1753 .init = &omap2_init_clksel_parent,
@@ -1713,6 +1761,7 @@ static struct clk gpt11_ick = {
1713 .name = "gpt11_ick", 1761 .name = "gpt11_ick",
1714 .parent = &l4_ck, 1762 .parent = &l4_ck,
1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764 .clkdm_name = "core_l4_clkdm",
1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1717 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1766 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1718 .recalc = &followparent_recalc, 1767 .recalc = &followparent_recalc,
@@ -1722,6 +1771,7 @@ static struct clk gpt11_fck = {
1722 .name = "gpt11_fck", 1771 .name = "gpt11_fck",
1723 .parent = &func_32k_ck, 1772 .parent = &func_32k_ck,
1724 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774 .clkdm_name = "core_l4_clkdm",
1725 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1726 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1776 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1727 .init = &omap2_init_clksel_parent, 1777 .init = &omap2_init_clksel_parent,
@@ -1735,6 +1785,7 @@ static struct clk gpt12_ick = {
1735 .name = "gpt12_ick", 1785 .name = "gpt12_ick",
1736 .parent = &l4_ck, 1786 .parent = &l4_ck,
1737 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788 .clkdm_name = "core_l4_clkdm",
1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1739 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1790 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1740 .recalc = &followparent_recalc, 1791 .recalc = &followparent_recalc,
@@ -1744,6 +1795,7 @@ static struct clk gpt12_fck = {
1744 .name = "gpt12_fck", 1795 .name = "gpt12_fck",
1745 .parent = &func_32k_ck, 1796 .parent = &func_32k_ck,
1746 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1797 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1798 .clkdm_name = "core_l4_clkdm",
1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1748 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1800 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1749 .init = &omap2_init_clksel_parent, 1801 .init = &omap2_init_clksel_parent,
@@ -1758,6 +1810,7 @@ static struct clk mcbsp1_ick = {
1758 .id = 1, 1810 .id = 1,
1759 .parent = &l4_ck, 1811 .parent = &l4_ck,
1760 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1813 .clkdm_name = "core_l4_clkdm",
1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1762 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1815 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1763 .recalc = &followparent_recalc, 1816 .recalc = &followparent_recalc,
@@ -1768,6 +1821,7 @@ static struct clk mcbsp1_fck = {
1768 .id = 1, 1821 .id = 1,
1769 .parent = &func_96m_ck, 1822 .parent = &func_96m_ck,
1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1823 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1824 .clkdm_name = "core_l4_clkdm",
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1772 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1826 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1773 .recalc = &followparent_recalc, 1827 .recalc = &followparent_recalc,
@@ -1778,6 +1832,7 @@ static struct clk mcbsp2_ick = {
1778 .id = 2, 1832 .id = 2,
1779 .parent = &l4_ck, 1833 .parent = &l4_ck,
1780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1834 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1835 .clkdm_name = "core_l4_clkdm",
1781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1782 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1837 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1783 .recalc = &followparent_recalc, 1838 .recalc = &followparent_recalc,
@@ -1788,6 +1843,7 @@ static struct clk mcbsp2_fck = {
1788 .id = 2, 1843 .id = 2,
1789 .parent = &func_96m_ck, 1844 .parent = &func_96m_ck,
1790 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846 .clkdm_name = "core_l4_clkdm",
1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1792 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1848 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1793 .recalc = &followparent_recalc, 1849 .recalc = &followparent_recalc,
@@ -1798,6 +1854,7 @@ static struct clk mcbsp3_ick = {
1798 .id = 3, 1854 .id = 3,
1799 .parent = &l4_ck, 1855 .parent = &l4_ck,
1800 .flags = CLOCK_IN_OMAP243X, 1856 .flags = CLOCK_IN_OMAP243X,
1857 .clkdm_name = "core_l4_clkdm",
1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1802 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1859 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1803 .recalc = &followparent_recalc, 1860 .recalc = &followparent_recalc,
@@ -1808,6 +1865,7 @@ static struct clk mcbsp3_fck = {
1808 .id = 3, 1865 .id = 3,
1809 .parent = &func_96m_ck, 1866 .parent = &func_96m_ck,
1810 .flags = CLOCK_IN_OMAP243X, 1867 .flags = CLOCK_IN_OMAP243X,
1868 .clkdm_name = "core_l4_clkdm",
1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1812 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1870 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1813 .recalc = &followparent_recalc, 1871 .recalc = &followparent_recalc,
@@ -1818,6 +1876,7 @@ static struct clk mcbsp4_ick = {
1818 .id = 4, 1876 .id = 4,
1819 .parent = &l4_ck, 1877 .parent = &l4_ck,
1820 .flags = CLOCK_IN_OMAP243X, 1878 .flags = CLOCK_IN_OMAP243X,
1879 .clkdm_name = "core_l4_clkdm",
1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1822 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1881 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1823 .recalc = &followparent_recalc, 1882 .recalc = &followparent_recalc,
@@ -1828,6 +1887,7 @@ static struct clk mcbsp4_fck = {
1828 .id = 4, 1887 .id = 4,
1829 .parent = &func_96m_ck, 1888 .parent = &func_96m_ck,
1830 .flags = CLOCK_IN_OMAP243X, 1889 .flags = CLOCK_IN_OMAP243X,
1890 .clkdm_name = "core_l4_clkdm",
1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1832 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1892 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1833 .recalc = &followparent_recalc, 1893 .recalc = &followparent_recalc,
@@ -1838,6 +1898,7 @@ static struct clk mcbsp5_ick = {
1838 .id = 5, 1898 .id = 5,
1839 .parent = &l4_ck, 1899 .parent = &l4_ck,
1840 .flags = CLOCK_IN_OMAP243X, 1900 .flags = CLOCK_IN_OMAP243X,
1901 .clkdm_name = "core_l4_clkdm",
1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1842 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1903 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1843 .recalc = &followparent_recalc, 1904 .recalc = &followparent_recalc,
@@ -1848,6 +1909,7 @@ static struct clk mcbsp5_fck = {
1848 .id = 5, 1909 .id = 5,
1849 .parent = &func_96m_ck, 1910 .parent = &func_96m_ck,
1850 .flags = CLOCK_IN_OMAP243X, 1911 .flags = CLOCK_IN_OMAP243X,
1912 .clkdm_name = "core_l4_clkdm",
1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1852 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1914 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1853 .recalc = &followparent_recalc, 1915 .recalc = &followparent_recalc,
@@ -1857,6 +1919,7 @@ static struct clk mcspi1_ick = {
1857 .name = "mcspi_ick", 1919 .name = "mcspi_ick",
1858 .id = 1, 1920 .id = 1,
1859 .parent = &l4_ck, 1921 .parent = &l4_ck,
1922 .clkdm_name = "core_l4_clkdm",
1860 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1862 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1925 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -1868,6 +1931,7 @@ static struct clk mcspi1_fck = {
1868 .id = 1, 1931 .id = 1,
1869 .parent = &func_48m_ck, 1932 .parent = &func_48m_ck,
1870 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1933 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1934 .clkdm_name = "core_l4_clkdm",
1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1872 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1936 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1873 .recalc = &followparent_recalc, 1937 .recalc = &followparent_recalc,
@@ -1878,6 +1942,7 @@ static struct clk mcspi2_ick = {
1878 .id = 2, 1942 .id = 2,
1879 .parent = &l4_ck, 1943 .parent = &l4_ck,
1880 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1944 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1945 .clkdm_name = "core_l4_clkdm",
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1947 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1883 .recalc = &followparent_recalc, 1948 .recalc = &followparent_recalc,
@@ -1888,6 +1953,7 @@ static struct clk mcspi2_fck = {
1888 .id = 2, 1953 .id = 2,
1889 .parent = &func_48m_ck, 1954 .parent = &func_48m_ck,
1890 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956 .clkdm_name = "core_l4_clkdm",
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1892 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1958 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1893 .recalc = &followparent_recalc, 1959 .recalc = &followparent_recalc,
@@ -1898,6 +1964,7 @@ static struct clk mcspi3_ick = {
1898 .id = 3, 1964 .id = 3,
1899 .parent = &l4_ck, 1965 .parent = &l4_ck,
1900 .flags = CLOCK_IN_OMAP243X, 1966 .flags = CLOCK_IN_OMAP243X,
1967 .clkdm_name = "core_l4_clkdm",
1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1902 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1969 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1903 .recalc = &followparent_recalc, 1970 .recalc = &followparent_recalc,
@@ -1908,6 +1975,7 @@ static struct clk mcspi3_fck = {
1908 .id = 3, 1975 .id = 3,
1909 .parent = &func_48m_ck, 1976 .parent = &func_48m_ck,
1910 .flags = CLOCK_IN_OMAP243X, 1977 .flags = CLOCK_IN_OMAP243X,
1978 .clkdm_name = "core_l4_clkdm",
1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1912 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1980 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1913 .recalc = &followparent_recalc, 1981 .recalc = &followparent_recalc,
@@ -1917,6 +1985,7 @@ static struct clk uart1_ick = {
1917 .name = "uart1_ick", 1985 .name = "uart1_ick",
1918 .parent = &l4_ck, 1986 .parent = &l4_ck,
1919 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1987 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1988 .clkdm_name = "core_l4_clkdm",
1920 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1989 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1990 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1922 .recalc = &followparent_recalc, 1991 .recalc = &followparent_recalc,
@@ -1926,6 +1995,7 @@ static struct clk uart1_fck = {
1926 .name = "uart1_fck", 1995 .name = "uart1_fck",
1927 .parent = &func_48m_ck, 1996 .parent = &func_48m_ck,
1928 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1997 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1998 .clkdm_name = "core_l4_clkdm",
1929 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1930 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 2000 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1931 .recalc = &followparent_recalc, 2001 .recalc = &followparent_recalc,
@@ -1935,6 +2005,7 @@ static struct clk uart2_ick = {
1935 .name = "uart2_ick", 2005 .name = "uart2_ick",
1936 .parent = &l4_ck, 2006 .parent = &l4_ck,
1937 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2008 .clkdm_name = "core_l4_clkdm",
1938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1939 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2010 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1940 .recalc = &followparent_recalc, 2011 .recalc = &followparent_recalc,
@@ -1944,6 +2015,7 @@ static struct clk uart2_fck = {
1944 .name = "uart2_fck", 2015 .name = "uart2_fck",
1945 .parent = &func_48m_ck, 2016 .parent = &func_48m_ck,
1946 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2018 .clkdm_name = "core_l4_clkdm",
1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1948 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2020 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1949 .recalc = &followparent_recalc, 2021 .recalc = &followparent_recalc,
@@ -1953,6 +2025,7 @@ static struct clk uart3_ick = {
1953 .name = "uart3_ick", 2025 .name = "uart3_ick",
1954 .parent = &l4_ck, 2026 .parent = &l4_ck,
1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2028 .clkdm_name = "core_l4_clkdm",
1956 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1957 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2030 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1958 .recalc = &followparent_recalc, 2031 .recalc = &followparent_recalc,
@@ -1962,6 +2035,7 @@ static struct clk uart3_fck = {
1962 .name = "uart3_fck", 2035 .name = "uart3_fck",
1963 .parent = &func_48m_ck, 2036 .parent = &func_48m_ck,
1964 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2037 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038 .clkdm_name = "core_l4_clkdm",
1965 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1966 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2040 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1967 .recalc = &followparent_recalc, 2041 .recalc = &followparent_recalc,
@@ -1971,6 +2045,7 @@ static struct clk gpios_ick = {
1971 .name = "gpios_ick", 2045 .name = "gpios_ick",
1972 .parent = &l4_ck, 2046 .parent = &l4_ck,
1973 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2047 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2048 .clkdm_name = "core_l4_clkdm",
1974 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2049 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1975 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2050 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1976 .recalc = &followparent_recalc, 2051 .recalc = &followparent_recalc,
@@ -1980,6 +2055,7 @@ static struct clk gpios_fck = {
1980 .name = "gpios_fck", 2055 .name = "gpios_fck",
1981 .parent = &func_32k_ck, 2056 .parent = &func_32k_ck,
1982 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058 .clkdm_name = "wkup_clkdm",
1983 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2059 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1984 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2060 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1985 .recalc = &followparent_recalc, 2061 .recalc = &followparent_recalc,
@@ -1989,6 +2065,7 @@ static struct clk mpu_wdt_ick = {
1989 .name = "mpu_wdt_ick", 2065 .name = "mpu_wdt_ick",
1990 .parent = &l4_ck, 2066 .parent = &l4_ck,
1991 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2067 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2068 .clkdm_name = "core_l4_clkdm",
1992 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2069 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1993 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2070 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1994 .recalc = &followparent_recalc, 2071 .recalc = &followparent_recalc,
@@ -1998,6 +2075,7 @@ static struct clk mpu_wdt_fck = {
1998 .name = "mpu_wdt_fck", 2075 .name = "mpu_wdt_fck",
1999 .parent = &func_32k_ck, 2076 .parent = &func_32k_ck,
2000 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2077 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2078 .clkdm_name = "wkup_clkdm",
2001 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2079 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2002 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2080 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
2003 .recalc = &followparent_recalc, 2081 .recalc = &followparent_recalc,
@@ -2006,31 +2084,40 @@ static struct clk mpu_wdt_fck = {
2006static struct clk sync_32k_ick = { 2084static struct clk sync_32k_ick = {
2007 .name = "sync_32k_ick", 2085 .name = "sync_32k_ick",
2008 .parent = &l4_ck, 2086 .parent = &l4_ck,
2009 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2087 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2088 ENABLE_ON_INIT,
2089 .clkdm_name = "core_l4_clkdm",
2010 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2090 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2011 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 2091 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
2012 .recalc = &followparent_recalc, 2092 .recalc = &followparent_recalc,
2013}; 2093};
2094
2014static struct clk wdt1_ick = { 2095static struct clk wdt1_ick = {
2015 .name = "wdt1_ick", 2096 .name = "wdt1_ick",
2016 .parent = &l4_ck, 2097 .parent = &l4_ck,
2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2099 .clkdm_name = "core_l4_clkdm",
2018 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2100 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2019 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 2101 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
2020 .recalc = &followparent_recalc, 2102 .recalc = &followparent_recalc,
2021}; 2103};
2104
2022static struct clk omapctrl_ick = { 2105static struct clk omapctrl_ick = {
2023 .name = "omapctrl_ick", 2106 .name = "omapctrl_ick",
2024 .parent = &l4_ck, 2107 .parent = &l4_ck,
2025 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2108 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2109 ENABLE_ON_INIT,
2110 .clkdm_name = "core_l4_clkdm",
2026 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2111 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2027 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 2112 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
2028 .recalc = &followparent_recalc, 2113 .recalc = &followparent_recalc,
2029}; 2114};
2115
2030static struct clk icr_ick = { 2116static struct clk icr_ick = {
2031 .name = "icr_ick", 2117 .name = "icr_ick",
2032 .parent = &l4_ck, 2118 .parent = &l4_ck,
2033 .flags = CLOCK_IN_OMAP243X, 2119 .flags = CLOCK_IN_OMAP243X,
2120 .clkdm_name = "core_l4_clkdm",
2034 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2121 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2035 .enable_bit = OMAP2430_EN_ICR_SHIFT, 2122 .enable_bit = OMAP2430_EN_ICR_SHIFT,
2036 .recalc = &followparent_recalc, 2123 .recalc = &followparent_recalc,
@@ -2040,15 +2127,22 @@ static struct clk cam_ick = {
2040 .name = "cam_ick", 2127 .name = "cam_ick",
2041 .parent = &l4_ck, 2128 .parent = &l4_ck,
2042 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2129 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2130 .clkdm_name = "core_l4_clkdm",
2043 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2044 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2132 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2045 .recalc = &followparent_recalc, 2133 .recalc = &followparent_recalc,
2046}; 2134};
2047 2135
2136/*
2137 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
2138 * split into two separate clocks, since the parent clocks are different
2139 * and the clockdomains are also different.
2140 */
2048static struct clk cam_fck = { 2141static struct clk cam_fck = {
2049 .name = "cam_fck", 2142 .name = "cam_fck",
2050 .parent = &func_96m_ck, 2143 .parent = &func_96m_ck,
2051 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2145 .clkdm_name = "core_l3_clkdm",
2052 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2053 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2147 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
2054 .recalc = &followparent_recalc, 2148 .recalc = &followparent_recalc,
@@ -2058,6 +2152,7 @@ static struct clk mailboxes_ick = {
2058 .name = "mailboxes_ick", 2152 .name = "mailboxes_ick",
2059 .parent = &l4_ck, 2153 .parent = &l4_ck,
2060 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2154 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155 .clkdm_name = "core_l4_clkdm",
2061 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2156 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2062 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 2157 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2063 .recalc = &followparent_recalc, 2158 .recalc = &followparent_recalc,
@@ -2067,6 +2162,7 @@ static struct clk wdt4_ick = {
2067 .name = "wdt4_ick", 2162 .name = "wdt4_ick",
2068 .parent = &l4_ck, 2163 .parent = &l4_ck,
2069 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2165 .clkdm_name = "core_l4_clkdm",
2070 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2166 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2167 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2072 .recalc = &followparent_recalc, 2168 .recalc = &followparent_recalc,
@@ -2076,6 +2172,7 @@ static struct clk wdt4_fck = {
2076 .name = "wdt4_fck", 2172 .name = "wdt4_fck",
2077 .parent = &func_32k_ck, 2173 .parent = &func_32k_ck,
2078 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2174 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2175 .clkdm_name = "core_l4_clkdm",
2079 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2176 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2080 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2177 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
2081 .recalc = &followparent_recalc, 2178 .recalc = &followparent_recalc,
@@ -2085,6 +2182,7 @@ static struct clk wdt3_ick = {
2085 .name = "wdt3_ick", 2182 .name = "wdt3_ick",
2086 .parent = &l4_ck, 2183 .parent = &l4_ck,
2087 .flags = CLOCK_IN_OMAP242X, 2184 .flags = CLOCK_IN_OMAP242X,
2185 .clkdm_name = "core_l4_clkdm",
2088 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2089 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2187 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2090 .recalc = &followparent_recalc, 2188 .recalc = &followparent_recalc,
@@ -2094,6 +2192,7 @@ static struct clk wdt3_fck = {
2094 .name = "wdt3_fck", 2192 .name = "wdt3_fck",
2095 .parent = &func_32k_ck, 2193 .parent = &func_32k_ck,
2096 .flags = CLOCK_IN_OMAP242X, 2194 .flags = CLOCK_IN_OMAP242X,
2195 .clkdm_name = "core_l4_clkdm",
2097 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2098 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2197 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
2099 .recalc = &followparent_recalc, 2198 .recalc = &followparent_recalc,
@@ -2103,6 +2202,7 @@ static struct clk mspro_ick = {
2103 .name = "mspro_ick", 2202 .name = "mspro_ick",
2104 .parent = &l4_ck, 2203 .parent = &l4_ck,
2105 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2205 .clkdm_name = "core_l4_clkdm",
2106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2107 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2207 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2108 .recalc = &followparent_recalc, 2208 .recalc = &followparent_recalc,
@@ -2112,6 +2212,7 @@ static struct clk mspro_fck = {
2112 .name = "mspro_fck", 2212 .name = "mspro_fck",
2113 .parent = &func_96m_ck, 2213 .parent = &func_96m_ck,
2114 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2214 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2215 .clkdm_name = "core_l4_clkdm",
2115 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2116 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2217 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
2117 .recalc = &followparent_recalc, 2218 .recalc = &followparent_recalc,
@@ -2121,6 +2222,7 @@ static struct clk mmc_ick = {
2121 .name = "mmc_ick", 2222 .name = "mmc_ick",
2122 .parent = &l4_ck, 2223 .parent = &l4_ck,
2123 .flags = CLOCK_IN_OMAP242X, 2224 .flags = CLOCK_IN_OMAP242X,
2225 .clkdm_name = "core_l4_clkdm",
2124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2125 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2227 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2126 .recalc = &followparent_recalc, 2228 .recalc = &followparent_recalc,
@@ -2130,6 +2232,7 @@ static struct clk mmc_fck = {
2130 .name = "mmc_fck", 2232 .name = "mmc_fck",
2131 .parent = &func_96m_ck, 2233 .parent = &func_96m_ck,
2132 .flags = CLOCK_IN_OMAP242X, 2234 .flags = CLOCK_IN_OMAP242X,
2235 .clkdm_name = "core_l4_clkdm",
2133 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2134 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2237 .enable_bit = OMAP2420_EN_MMC_SHIFT,
2135 .recalc = &followparent_recalc, 2238 .recalc = &followparent_recalc,
@@ -2139,6 +2242,7 @@ static struct clk fac_ick = {
2139 .name = "fac_ick", 2242 .name = "fac_ick",
2140 .parent = &l4_ck, 2243 .parent = &l4_ck,
2141 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2245 .clkdm_name = "core_l4_clkdm",
2142 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2143 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2247 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2144 .recalc = &followparent_recalc, 2248 .recalc = &followparent_recalc,
@@ -2148,6 +2252,7 @@ static struct clk fac_fck = {
2148 .name = "fac_fck", 2252 .name = "fac_fck",
2149 .parent = &func_12m_ck, 2253 .parent = &func_12m_ck,
2150 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2254 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2255 .clkdm_name = "core_l4_clkdm",
2151 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2152 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2257 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
2153 .recalc = &followparent_recalc, 2258 .recalc = &followparent_recalc,
@@ -2157,6 +2262,7 @@ static struct clk eac_ick = {
2157 .name = "eac_ick", 2262 .name = "eac_ick",
2158 .parent = &l4_ck, 2263 .parent = &l4_ck,
2159 .flags = CLOCK_IN_OMAP242X, 2264 .flags = CLOCK_IN_OMAP242X,
2265 .clkdm_name = "core_l4_clkdm",
2160 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2161 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2267 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2162 .recalc = &followparent_recalc, 2268 .recalc = &followparent_recalc,
@@ -2166,6 +2272,7 @@ static struct clk eac_fck = {
2166 .name = "eac_fck", 2272 .name = "eac_fck",
2167 .parent = &func_96m_ck, 2273 .parent = &func_96m_ck,
2168 .flags = CLOCK_IN_OMAP242X, 2274 .flags = CLOCK_IN_OMAP242X,
2275 .clkdm_name = "core_l4_clkdm",
2169 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2170 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2277 .enable_bit = OMAP2420_EN_EAC_SHIFT,
2171 .recalc = &followparent_recalc, 2278 .recalc = &followparent_recalc,
@@ -2175,6 +2282,7 @@ static struct clk hdq_ick = {
2175 .name = "hdq_ick", 2282 .name = "hdq_ick",
2176 .parent = &l4_ck, 2283 .parent = &l4_ck,
2177 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2285 .clkdm_name = "core_l4_clkdm",
2178 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2179 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2287 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2180 .recalc = &followparent_recalc, 2288 .recalc = &followparent_recalc,
@@ -2184,6 +2292,7 @@ static struct clk hdq_fck = {
2184 .name = "hdq_fck", 2292 .name = "hdq_fck",
2185 .parent = &func_12m_ck, 2293 .parent = &func_12m_ck,
2186 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2294 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2295 .clkdm_name = "core_l4_clkdm",
2187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2188 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2297 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
2189 .recalc = &followparent_recalc, 2298 .recalc = &followparent_recalc,
@@ -2194,6 +2303,7 @@ static struct clk i2c2_ick = {
2194 .id = 2, 2303 .id = 2,
2195 .parent = &l4_ck, 2304 .parent = &l4_ck,
2196 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2305 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2306 .clkdm_name = "core_l4_clkdm",
2197 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2198 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2308 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2199 .recalc = &followparent_recalc, 2309 .recalc = &followparent_recalc,
@@ -2204,6 +2314,7 @@ static struct clk i2c2_fck = {
2204 .id = 2, 2314 .id = 2,
2205 .parent = &func_12m_ck, 2315 .parent = &func_12m_ck,
2206 .flags = CLOCK_IN_OMAP242X, 2316 .flags = CLOCK_IN_OMAP242X,
2317 .clkdm_name = "core_l4_clkdm",
2207 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2208 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2319 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
2209 .recalc = &followparent_recalc, 2320 .recalc = &followparent_recalc,
@@ -2214,6 +2325,7 @@ static struct clk i2chs2_fck = {
2214 .id = 2, 2325 .id = 2,
2215 .parent = &func_96m_ck, 2326 .parent = &func_96m_ck,
2216 .flags = CLOCK_IN_OMAP243X, 2327 .flags = CLOCK_IN_OMAP243X,
2328 .clkdm_name = "core_l4_clkdm",
2217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2218 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, 2330 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
2219 .recalc = &followparent_recalc, 2331 .recalc = &followparent_recalc,
@@ -2224,6 +2336,7 @@ static struct clk i2c1_ick = {
2224 .id = 1, 2336 .id = 1,
2225 .parent = &l4_ck, 2337 .parent = &l4_ck,
2226 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2338 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2339 .clkdm_name = "core_l4_clkdm",
2227 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2228 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2341 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2229 .recalc = &followparent_recalc, 2342 .recalc = &followparent_recalc,
@@ -2234,6 +2347,7 @@ static struct clk i2c1_fck = {
2234 .id = 1, 2347 .id = 1,
2235 .parent = &func_12m_ck, 2348 .parent = &func_12m_ck,
2236 .flags = CLOCK_IN_OMAP242X, 2349 .flags = CLOCK_IN_OMAP242X,
2350 .clkdm_name = "core_l4_clkdm",
2237 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2238 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2352 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
2239 .recalc = &followparent_recalc, 2353 .recalc = &followparent_recalc,
@@ -2244,6 +2358,7 @@ static struct clk i2chs1_fck = {
2244 .id = 1, 2358 .id = 1,
2245 .parent = &func_96m_ck, 2359 .parent = &func_96m_ck,
2246 .flags = CLOCK_IN_OMAP243X, 2360 .flags = CLOCK_IN_OMAP243X,
2361 .clkdm_name = "core_l4_clkdm",
2247 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2248 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, 2363 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
2249 .recalc = &followparent_recalc, 2364 .recalc = &followparent_recalc,
@@ -2252,7 +2367,9 @@ static struct clk i2chs1_fck = {
2252static struct clk gpmc_fck = { 2367static struct clk gpmc_fck = {
2253 .name = "gpmc_fck", 2368 .name = "gpmc_fck",
2254 .parent = &core_l3_ck, 2369 .parent = &core_l3_ck,
2255 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2370 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2371 ENABLE_ON_INIT,
2372 .clkdm_name = "core_l3_clkdm",
2256 .recalc = &followparent_recalc, 2373 .recalc = &followparent_recalc,
2257}; 2374};
2258 2375
@@ -2260,6 +2377,7 @@ static struct clk sdma_fck = {
2260 .name = "sdma_fck", 2377 .name = "sdma_fck",
2261 .parent = &core_l3_ck, 2378 .parent = &core_l3_ck,
2262 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2379 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2380 .clkdm_name = "core_l3_clkdm",
2263 .recalc = &followparent_recalc, 2381 .recalc = &followparent_recalc,
2264}; 2382};
2265 2383
@@ -2267,6 +2385,7 @@ static struct clk sdma_ick = {
2267 .name = "sdma_ick", 2385 .name = "sdma_ick",
2268 .parent = &l4_ck, 2386 .parent = &l4_ck,
2269 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2387 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2388 .clkdm_name = "core_l3_clkdm",
2270 .recalc = &followparent_recalc, 2389 .recalc = &followparent_recalc,
2271}; 2390};
2272 2391
@@ -2274,6 +2393,7 @@ static struct clk vlynq_ick = {
2274 .name = "vlynq_ick", 2393 .name = "vlynq_ick",
2275 .parent = &core_l3_ck, 2394 .parent = &core_l3_ck,
2276 .flags = CLOCK_IN_OMAP242X, 2395 .flags = CLOCK_IN_OMAP242X,
2396 .clkdm_name = "core_l3_clkdm",
2277 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2278 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2398 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2279 .recalc = &followparent_recalc, 2399 .recalc = &followparent_recalc,
@@ -2308,6 +2428,7 @@ static struct clk vlynq_fck = {
2308 .name = "vlynq_fck", 2428 .name = "vlynq_fck",
2309 .parent = &func_96m_ck, 2429 .parent = &func_96m_ck,
2310 .flags = CLOCK_IN_OMAP242X | DELAYED_APP, 2430 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
2431 .clkdm_name = "core_l3_clkdm",
2311 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2312 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2433 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
2313 .init = &omap2_init_clksel_parent, 2434 .init = &omap2_init_clksel_parent,
@@ -2323,6 +2444,7 @@ static struct clk sdrc_ick = {
2323 .name = "sdrc_ick", 2444 .name = "sdrc_ick",
2324 .parent = &l4_ck, 2445 .parent = &l4_ck,
2325 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2446 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2447 .clkdm_name = "core_l4_clkdm",
2326 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 2448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2327 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 2449 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
2328 .recalc = &followparent_recalc, 2450 .recalc = &followparent_recalc,
@@ -2332,6 +2454,7 @@ static struct clk des_ick = {
2332 .name = "des_ick", 2454 .name = "des_ick",
2333 .parent = &l4_ck, 2455 .parent = &l4_ck,
2334 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2456 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2457 .clkdm_name = "core_l4_clkdm",
2335 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2336 .enable_bit = OMAP24XX_EN_DES_SHIFT, 2459 .enable_bit = OMAP24XX_EN_DES_SHIFT,
2337 .recalc = &followparent_recalc, 2460 .recalc = &followparent_recalc,
@@ -2341,6 +2464,7 @@ static struct clk sha_ick = {
2341 .name = "sha_ick", 2464 .name = "sha_ick",
2342 .parent = &l4_ck, 2465 .parent = &l4_ck,
2343 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2466 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2467 .clkdm_name = "core_l4_clkdm",
2344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2468 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2345 .enable_bit = OMAP24XX_EN_SHA_SHIFT, 2469 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
2346 .recalc = &followparent_recalc, 2470 .recalc = &followparent_recalc,
@@ -2350,6 +2474,7 @@ static struct clk rng_ick = {
2350 .name = "rng_ick", 2474 .name = "rng_ick",
2351 .parent = &l4_ck, 2475 .parent = &l4_ck,
2352 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2476 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2477 .clkdm_name = "core_l4_clkdm",
2353 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2354 .enable_bit = OMAP24XX_EN_RNG_SHIFT, 2479 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
2355 .recalc = &followparent_recalc, 2480 .recalc = &followparent_recalc,
@@ -2359,6 +2484,7 @@ static struct clk aes_ick = {
2359 .name = "aes_ick", 2484 .name = "aes_ick",
2360 .parent = &l4_ck, 2485 .parent = &l4_ck,
2361 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2486 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2487 .clkdm_name = "core_l4_clkdm",
2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2363 .enable_bit = OMAP24XX_EN_AES_SHIFT, 2489 .enable_bit = OMAP24XX_EN_AES_SHIFT,
2364 .recalc = &followparent_recalc, 2490 .recalc = &followparent_recalc,
@@ -2368,6 +2494,7 @@ static struct clk pka_ick = {
2368 .name = "pka_ick", 2494 .name = "pka_ick",
2369 .parent = &l4_ck, 2495 .parent = &l4_ck,
2370 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2496 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2497 .clkdm_name = "core_l4_clkdm",
2371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2372 .enable_bit = OMAP24XX_EN_PKA_SHIFT, 2499 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
2373 .recalc = &followparent_recalc, 2500 .recalc = &followparent_recalc,
@@ -2377,6 +2504,7 @@ static struct clk usb_fck = {
2377 .name = "usb_fck", 2504 .name = "usb_fck",
2378 .parent = &func_48m_ck, 2505 .parent = &func_48m_ck,
2379 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2506 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2507 .clkdm_name = "core_l3_clkdm",
2380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2381 .enable_bit = OMAP24XX_EN_USB_SHIFT, 2509 .enable_bit = OMAP24XX_EN_USB_SHIFT,
2382 .recalc = &followparent_recalc, 2510 .recalc = &followparent_recalc,
@@ -2386,6 +2514,7 @@ static struct clk usbhs_ick = {
2386 .name = "usbhs_ick", 2514 .name = "usbhs_ick",
2387 .parent = &core_l3_ck, 2515 .parent = &core_l3_ck,
2388 .flags = CLOCK_IN_OMAP243X, 2516 .flags = CLOCK_IN_OMAP243X,
2517 .clkdm_name = "core_l3_clkdm",
2389 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2390 .enable_bit = OMAP2430_EN_USBHS_SHIFT, 2519 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
2391 .recalc = &followparent_recalc, 2520 .recalc = &followparent_recalc,
@@ -2396,6 +2525,7 @@ static struct clk mmchs1_ick = {
2396 .id = 1, 2525 .id = 1,
2397 .parent = &l4_ck, 2526 .parent = &l4_ck,
2398 .flags = CLOCK_IN_OMAP243X, 2527 .flags = CLOCK_IN_OMAP243X,
2528 .clkdm_name = "core_l4_clkdm",
2399 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2529 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2400 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2530 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2401 .recalc = &followparent_recalc, 2531 .recalc = &followparent_recalc,
@@ -2406,6 +2536,7 @@ static struct clk mmchs1_fck = {
2406 .id = 1, 2536 .id = 1,
2407 .parent = &func_96m_ck, 2537 .parent = &func_96m_ck,
2408 .flags = CLOCK_IN_OMAP243X, 2538 .flags = CLOCK_IN_OMAP243X,
2539 .clkdm_name = "core_l3_clkdm",
2409 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2540 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2410 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2541 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
2411 .recalc = &followparent_recalc, 2542 .recalc = &followparent_recalc,
@@ -2416,6 +2547,7 @@ static struct clk mmchs2_ick = {
2416 .id = 2, 2547 .id = 2,
2417 .parent = &l4_ck, 2548 .parent = &l4_ck,
2418 .flags = CLOCK_IN_OMAP243X, 2549 .flags = CLOCK_IN_OMAP243X,
2550 .clkdm_name = "core_l4_clkdm",
2419 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2551 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2420 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2552 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2421 .recalc = &followparent_recalc, 2553 .recalc = &followparent_recalc,
@@ -2435,6 +2567,7 @@ static struct clk gpio5_ick = {
2435 .name = "gpio5_ick", 2567 .name = "gpio5_ick",
2436 .parent = &l4_ck, 2568 .parent = &l4_ck,
2437 .flags = CLOCK_IN_OMAP243X, 2569 .flags = CLOCK_IN_OMAP243X,
2570 .clkdm_name = "core_l4_clkdm",
2438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2439 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2572 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2440 .recalc = &followparent_recalc, 2573 .recalc = &followparent_recalc,
@@ -2444,6 +2577,7 @@ static struct clk gpio5_fck = {
2444 .name = "gpio5_fck", 2577 .name = "gpio5_fck",
2445 .parent = &func_32k_ck, 2578 .parent = &func_32k_ck,
2446 .flags = CLOCK_IN_OMAP243X, 2579 .flags = CLOCK_IN_OMAP243X,
2580 .clkdm_name = "core_l4_clkdm",
2447 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2581 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2448 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2582 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
2449 .recalc = &followparent_recalc, 2583 .recalc = &followparent_recalc,
@@ -2453,6 +2587,7 @@ static struct clk mdm_intc_ick = {
2453 .name = "mdm_intc_ick", 2587 .name = "mdm_intc_ick",
2454 .parent = &l4_ck, 2588 .parent = &l4_ck,
2455 .flags = CLOCK_IN_OMAP243X, 2589 .flags = CLOCK_IN_OMAP243X,
2590 .clkdm_name = "core_l4_clkdm",
2456 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2591 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2457 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, 2592 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
2458 .recalc = &followparent_recalc, 2593 .recalc = &followparent_recalc,
@@ -2463,6 +2598,7 @@ static struct clk mmchsdb1_fck = {
2463 .id = 1, 2598 .id = 1,
2464 .parent = &func_32k_ck, 2599 .parent = &func_32k_ck,
2465 .flags = CLOCK_IN_OMAP243X, 2600 .flags = CLOCK_IN_OMAP243X,
2601 .clkdm_name = "core_l4_clkdm",
2466 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2602 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2467 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, 2603 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
2468 .recalc = &followparent_recalc, 2604 .recalc = &followparent_recalc,
@@ -2473,6 +2609,7 @@ static struct clk mmchsdb2_fck = {
2473 .id = 2, 2609 .id = 2,
2474 .parent = &func_32k_ck, 2610 .parent = &func_32k_ck,
2475 .flags = CLOCK_IN_OMAP243X, 2611 .flags = CLOCK_IN_OMAP243X,
2612 .clkdm_name = "core_l4_clkdm",
2476 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2613 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2477 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, 2614 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
2478 .recalc = &followparent_recalc, 2615 .recalc = &followparent_recalc,
@@ -2551,7 +2688,6 @@ static struct clk *onchip_24xx_clks[] __initdata = {
2551 &usb_l4_ick, 2688 &usb_l4_ick,
2552 /* L4 domain clocks */ 2689 /* L4 domain clocks */
2553 &l4_ck, /* used as both core_l4 and wu_l4 */ 2690 &l4_ck, /* used as both core_l4 and wu_l4 */
2554 &ssi_l4_ick,
2555 /* virtual meta-group clock */ 2691 /* virtual meta-group clock */
2556 &virt_prcm_set, 2692 &virt_prcm_set,
2557 /* general l4 interface ck, multi-parent functional clk */ 2693 /* general l4 interface ck, multi-parent functional clk */
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index e5b475f21081..084e11082f80 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
62static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) 62static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
63{ 63{
64 const struct dpll_data *dd; 64 const struct dpll_data *dd;
65 u32 v;
65 66
66 dd = clk->dpll_data; 67 dd = clk->dpll_data;
67 68
68 cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask), 69 v = __raw_readl(dd->control_reg);
69 dd->control_reg); 70 v &= ~dd->enable_mask;
71 v |= clken_bits << __ffs(dd->enable_mask);
72 __raw_writel(v, dd->control_reg);
70} 73}
71 74
72/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ 75/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
82 state <<= dd->idlest_bit; 85 state <<= dd->idlest_bit;
83 idlest_mask = 1 << dd->idlest_bit; 86 idlest_mask = 1 << dd->idlest_bit;
84 87
85 while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) && 88 while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
86 i < MAX_DPLL_WAIT_TRIES) { 89 i < MAX_DPLL_WAIT_TRIES) {
87 i++; 90 i++;
88 udelay(1); 91 udelay(1);
@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
285 288
286 dd = clk->dpll_data; 289 dd = clk->dpll_data;
287 290
288 v = cm_read_reg(dd->autoidle_reg); 291 v = __raw_readl(dd->autoidle_reg);
289 v &= dd->autoidle_mask; 292 v &= dd->autoidle_mask;
290 v >>= __ffs(dd->autoidle_mask); 293 v >>= __ffs(dd->autoidle_mask);
291 294
@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
304static void omap3_dpll_allow_idle(struct clk *clk) 307static void omap3_dpll_allow_idle(struct clk *clk)
305{ 308{
306 const struct dpll_data *dd; 309 const struct dpll_data *dd;
310 u32 v;
307 311
308 if (!clk || !clk->dpll_data) 312 if (!clk || !clk->dpll_data)
309 return; 313 return;
@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
315 * by writing 0x5 instead of 0x1. Add some mechanism to 319 * by writing 0x5 instead of 0x1. Add some mechanism to
316 * optionally enter this mode. 320 * optionally enter this mode.
317 */ 321 */
318 cm_rmw_reg_bits(dd->autoidle_mask, 322 v = __raw_readl(dd->autoidle_reg);
319 DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask), 323 v &= ~dd->autoidle_mask;
320 dd->autoidle_reg); 324 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
325 __raw_writel(v, dd->autoidle_reg);
321} 326}
322 327
323/** 328/**
@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
329static void omap3_dpll_deny_idle(struct clk *clk) 334static void omap3_dpll_deny_idle(struct clk *clk)
330{ 335{
331 const struct dpll_data *dd; 336 const struct dpll_data *dd;
337 u32 v;
332 338
333 if (!clk || !clk->dpll_data) 339 if (!clk || !clk->dpll_data)
334 return; 340 return;
335 341
336 dd = clk->dpll_data; 342 dd = clk->dpll_data;
337 343
338 cm_rmw_reg_bits(dd->autoidle_mask, 344 v = __raw_readl(dd->autoidle_reg);
339 DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask), 345 v &= ~dd->autoidle_mask;
340 dd->autoidle_reg); 346 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
347 __raw_writel(v, dd->autoidle_reg);
341} 348}
342 349
343/* Clock control for DPLL outputs */ 350/* Clock control for DPLL outputs */
@@ -482,8 +489,10 @@ int __init omap2_clk_init(void)
482 for (clkp = onchip_34xx_clks; 489 for (clkp = onchip_34xx_clks;
483 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); 490 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
484 clkp++) { 491 clkp++) {
485 if ((*clkp)->flags & cpu_clkflg) 492 if ((*clkp)->flags & cpu_clkflg) {
486 clk_register(*clkp); 493 clk_register(*clkp);
494 omap2_init_clk_clkdm(*clkp);
495 }
487 } 496 }
488 497
489 /* REVISIT: Not yet ready for OMAP3 */ 498 /* REVISIT: Not yet ready for OMAP3 */
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index ec664457a11a..c38a8a09692f 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -478,7 +478,7 @@ static struct clk dpll3_m2_ck = {
478}; 478};
479 479
480static const struct clksel core_ck_clksel[] = { 480static const struct clksel core_ck_clksel[] = {
481 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 481 { .parent = &sys_ck, .rates = dpll_bypass_rates },
482 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, 482 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
483 { .parent = NULL } 483 { .parent = NULL }
484}; 484};
@@ -495,7 +495,7 @@ static struct clk core_ck = {
495}; 495};
496 496
497static const struct clksel dpll3_m2x2_ck_clksel[] = { 497static const struct clksel dpll3_m2x2_ck_clksel[] = {
498 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 498 { .parent = &sys_ck, .rates = dpll_bypass_rates },
499 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, 499 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
500 { .parent = NULL } 500 { .parent = NULL }
501}; 501};
@@ -541,7 +541,7 @@ static struct clk dpll3_m3x2_ck = {
541}; 541};
542 542
543static const struct clksel emu_core_alwon_ck_clksel[] = { 543static const struct clksel emu_core_alwon_ck_clksel[] = {
544 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 544 { .parent = &sys_ck, .rates = dpll_bypass_rates },
545 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, 545 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
546 { .parent = NULL } 546 { .parent = NULL }
547}; 547};
@@ -633,7 +633,7 @@ static struct clk dpll4_m2x2_ck = {
633}; 633};
634 634
635static const struct clksel omap_96m_alwon_fck_clksel[] = { 635static const struct clksel omap_96m_alwon_fck_clksel[] = {
636 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 636 { .parent = &sys_ck, .rates = dpll_bypass_rates },
637 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 637 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
638 { .parent = NULL } 638 { .parent = NULL }
639}; 639};
@@ -659,7 +659,7 @@ static struct clk omap_96m_fck = {
659}; 659};
660 660
661static const struct clksel cm_96m_fck_clksel[] = { 661static const struct clksel cm_96m_fck_clksel[] = {
662 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 662 { .parent = &sys_ck, .rates = dpll_bypass_rates },
663 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 663 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
664 { .parent = NULL } 664 { .parent = NULL }
665}; 665};
@@ -701,7 +701,7 @@ static struct clk dpll4_m3x2_ck = {
701}; 701};
702 702
703static const struct clksel virt_omap_54m_fck_clksel[] = { 703static const struct clksel virt_omap_54m_fck_clksel[] = {
704 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 704 { .parent = &sys_ck, .rates = dpll_bypass_rates },
705 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, 705 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
706 { .parent = NULL } 706 { .parent = NULL }
707}; 707};
@@ -911,7 +911,7 @@ static struct clk dpll5_m2_ck = {
911}; 911};
912 912
913static const struct clksel omap_120m_fck_clksel[] = { 913static const struct clksel omap_120m_fck_clksel[] = {
914 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 914 { .parent = &sys_ck, .rates = dpll_bypass_rates },
915 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, 915 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
916 { .parent = NULL } 916 { .parent = NULL }
917}; 917};
@@ -919,13 +919,13 @@ static const struct clksel omap_120m_fck_clksel[] = {
919static struct clk omap_120m_fck = { 919static struct clk omap_120m_fck = {
920 .name = "omap_120m_fck", 920 .name = "omap_120m_fck",
921 .parent = &dpll5_m2_ck, 921 .parent = &dpll5_m2_ck,
922 .init = &omap2_init_clksel_parent, 922 .init = &omap2_init_clksel_parent,
923 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 923 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
924 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, 924 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
925 .clksel = omap_120m_fck_clksel, 925 .clksel = omap_120m_fck_clksel,
926 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 926 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
927 PARENT_CONTROLS_CLOCK, 927 PARENT_CONTROLS_CLOCK,
928 .recalc = &omap2_clksel_recalc, 928 .recalc = &omap2_clksel_recalc,
929}; 929};
930 930
931/* CM EXTERNAL CLOCK OUTPUTS */ 931/* CM EXTERNAL CLOCK OUTPUTS */
@@ -1034,7 +1034,7 @@ static struct clk dpll1_fck = {
1034 * called 'dpll1_fck' 1034 * called 'dpll1_fck'
1035 */ 1035 */
1036static const struct clksel mpu_clksel[] = { 1036static const struct clksel mpu_clksel[] = {
1037 { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, 1037 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1038 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, 1038 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1039 { .parent = NULL } 1039 { .parent = NULL }
1040}; 1040};
@@ -1048,6 +1048,7 @@ static struct clk mpu_ck = {
1048 .clksel = mpu_clksel, 1048 .clksel = mpu_clksel,
1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1050 PARENT_CONTROLS_CLOCK, 1050 PARENT_CONTROLS_CLOCK,
1051 .clkdm_name = "mpu_clkdm",
1051 .recalc = &omap2_clksel_recalc, 1052 .recalc = &omap2_clksel_recalc,
1052}; 1053};
1053 1054
@@ -1075,6 +1076,8 @@ static struct clk arm_fck = {
1075 .recalc = &omap2_clksel_recalc, 1076 .recalc = &omap2_clksel_recalc,
1076}; 1077};
1077 1078
1079/* XXX What about neon_clkdm ? */
1080
1078/* 1081/*
1079 * REVISIT: This clock is never specifically defined in the 3430 TRM, 1082 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1080 * although it is referenced - so this is a guess 1083 * although it is referenced - so this is a guess
@@ -1107,7 +1110,7 @@ static struct clk dpll2_fck = {
1107 */ 1110 */
1108 1111
1109static const struct clksel iva2_clksel[] = { 1112static const struct clksel iva2_clksel[] = {
1110 { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, 1113 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1111 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, 1114 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1112 { .parent = NULL } 1115 { .parent = NULL }
1113}; 1116};
@@ -1123,6 +1126,7 @@ static struct clk iva2_ck = {
1123 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, 1126 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1124 .clksel = iva2_clksel, 1127 .clksel = iva2_clksel,
1125 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1128 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1129 .clkdm_name = "iva2_clkdm",
1126 .recalc = &omap2_clksel_recalc, 1130 .recalc = &omap2_clksel_recalc,
1127}; 1131};
1128 1132
@@ -1137,6 +1141,7 @@ static struct clk l3_ick = {
1137 .clksel = div2_core_clksel, 1141 .clksel = div2_core_clksel,
1138 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1142 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1139 PARENT_CONTROLS_CLOCK, 1143 PARENT_CONTROLS_CLOCK,
1144 .clkdm_name = "core_l3_clkdm",
1140 .recalc = &omap2_clksel_recalc, 1145 .recalc = &omap2_clksel_recalc,
1141}; 1146};
1142 1147
@@ -1154,6 +1159,7 @@ static struct clk l4_ick = {
1154 .clksel = div2_l3_clksel, 1159 .clksel = div2_l3_clksel,
1155 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1160 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1156 PARENT_CONTROLS_CLOCK, 1161 PARENT_CONTROLS_CLOCK,
1162 .clkdm_name = "core_l4_clkdm",
1157 .recalc = &omap2_clksel_recalc, 1163 .recalc = &omap2_clksel_recalc,
1158 1164
1159}; 1165};
@@ -1183,43 +1189,57 @@ static const struct clksel gfx_l3_clksel[] = {
1183 { .parent = NULL } 1189 { .parent = NULL }
1184}; 1190};
1185 1191
1186static struct clk gfx_l3_fck = { 1192/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1187 .name = "gfx_l3_fck", 1193static struct clk gfx_l3_ck = {
1194 .name = "gfx_l3_ck",
1188 .parent = &l3_ick, 1195 .parent = &l3_ick,
1189 .init = &omap2_init_clksel_parent, 1196 .init = &omap2_init_clksel_parent,
1190 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1197 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1191 .enable_bit = OMAP_EN_GFX_SHIFT, 1198 .enable_bit = OMAP_EN_GFX_SHIFT,
1199 .flags = CLOCK_IN_OMAP3430ES1,
1200 .recalc = &followparent_recalc,
1201};
1202
1203static struct clk gfx_l3_fck = {
1204 .name = "gfx_l3_fck",
1205 .parent = &gfx_l3_ck,
1206 .init = &omap2_init_clksel_parent,
1192 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1207 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1193 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1208 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1194 .clksel = gfx_l3_clksel, 1209 .clksel = gfx_l3_clksel,
1195 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, 1210 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1211 PARENT_CONTROLS_CLOCK,
1212 .clkdm_name = "gfx_3430es1_clkdm",
1196 .recalc = &omap2_clksel_recalc, 1213 .recalc = &omap2_clksel_recalc,
1197}; 1214};
1198 1215
1199static struct clk gfx_l3_ick = { 1216static struct clk gfx_l3_ick = {
1200 .name = "gfx_l3_ick", 1217 .name = "gfx_l3_ick",
1201 .parent = &l3_ick, 1218 .parent = &gfx_l3_ck,
1202 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1219 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1203 .enable_bit = OMAP_EN_GFX_SHIFT, 1220 .clkdm_name = "gfx_3430es1_clkdm",
1204 .flags = CLOCK_IN_OMAP3430ES1,
1205 .recalc = &followparent_recalc, 1221 .recalc = &followparent_recalc,
1206}; 1222};
1207 1223
1208static struct clk gfx_cg1_ck = { 1224static struct clk gfx_cg1_ck = {
1209 .name = "gfx_cg1_ck", 1225 .name = "gfx_cg1_ck",
1210 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1226 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1227 .init = &omap2_init_clk_clkdm,
1211 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1228 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1212 .enable_bit = OMAP3430ES1_EN_2D_SHIFT, 1229 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1213 .flags = CLOCK_IN_OMAP3430ES1, 1230 .flags = CLOCK_IN_OMAP3430ES1,
1231 .clkdm_name = "gfx_3430es1_clkdm",
1214 .recalc = &followparent_recalc, 1232 .recalc = &followparent_recalc,
1215}; 1233};
1216 1234
1217static struct clk gfx_cg2_ck = { 1235static struct clk gfx_cg2_ck = {
1218 .name = "gfx_cg2_ck", 1236 .name = "gfx_cg2_ck",
1219 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1237 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1238 .init = &omap2_init_clk_clkdm,
1220 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1239 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1221 .enable_bit = OMAP3430ES1_EN_3D_SHIFT, 1240 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1222 .flags = CLOCK_IN_OMAP3430ES1, 1241 .flags = CLOCK_IN_OMAP3430ES1,
1242 .clkdm_name = "gfx_3430es1_clkdm",
1223 .recalc = &followparent_recalc, 1243 .recalc = &followparent_recalc,
1224}; 1244};
1225 1245
@@ -1252,15 +1272,18 @@ static struct clk sgx_fck = {
1252 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, 1272 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1253 .clksel = sgx_clksel, 1273 .clksel = sgx_clksel,
1254 .flags = CLOCK_IN_OMAP3430ES2, 1274 .flags = CLOCK_IN_OMAP3430ES2,
1275 .clkdm_name = "sgx_clkdm",
1255 .recalc = &omap2_clksel_recalc, 1276 .recalc = &omap2_clksel_recalc,
1256}; 1277};
1257 1278
1258static struct clk sgx_ick = { 1279static struct clk sgx_ick = {
1259 .name = "sgx_ick", 1280 .name = "sgx_ick",
1260 .parent = &l3_ick, 1281 .parent = &l3_ick,
1282 .init = &omap2_init_clk_clkdm,
1261 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), 1283 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1262 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1284 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1263 .flags = CLOCK_IN_OMAP3430ES2, 1285 .flags = CLOCK_IN_OMAP3430ES2,
1286 .clkdm_name = "sgx_clkdm",
1264 .recalc = &followparent_recalc, 1287 .recalc = &followparent_recalc,
1265}; 1288};
1266 1289
@@ -1269,9 +1292,11 @@ static struct clk sgx_ick = {
1269static struct clk d2d_26m_fck = { 1292static struct clk d2d_26m_fck = {
1270 .name = "d2d_26m_fck", 1293 .name = "d2d_26m_fck",
1271 .parent = &sys_ck, 1294 .parent = &sys_ck,
1295 .init = &omap2_init_clk_clkdm,
1272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1273 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, 1297 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1274 .flags = CLOCK_IN_OMAP3430ES1, 1298 .flags = CLOCK_IN_OMAP3430ES1,
1299 .clkdm_name = "d2d_clkdm",
1275 .recalc = &followparent_recalc, 1300 .recalc = &followparent_recalc,
1276}; 1301};
1277 1302
@@ -1291,6 +1316,7 @@ static struct clk gpt10_fck = {
1291 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, 1316 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1292 .clksel = omap343x_gpt_clksel, 1317 .clksel = omap343x_gpt_clksel,
1293 .flags = CLOCK_IN_OMAP343X, 1318 .flags = CLOCK_IN_OMAP343X,
1319 .clkdm_name = "core_l4_clkdm",
1294 .recalc = &omap2_clksel_recalc, 1320 .recalc = &omap2_clksel_recalc,
1295}; 1321};
1296 1322
@@ -1304,6 +1330,7 @@ static struct clk gpt11_fck = {
1304 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, 1330 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1305 .clksel = omap343x_gpt_clksel, 1331 .clksel = omap343x_gpt_clksel,
1306 .flags = CLOCK_IN_OMAP343X, 1332 .flags = CLOCK_IN_OMAP343X,
1333 .clkdm_name = "core_l4_clkdm",
1307 .recalc = &omap2_clksel_recalc, 1334 .recalc = &omap2_clksel_recalc,
1308}; 1335};
1309 1336
@@ -1341,6 +1368,7 @@ static struct clk core_96m_fck = {
1341 .parent = &omap_96m_fck, 1368 .parent = &omap_96m_fck,
1342 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1369 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1343 PARENT_CONTROLS_CLOCK, 1370 PARENT_CONTROLS_CLOCK,
1371 .clkdm_name = "core_l4_clkdm",
1344 .recalc = &followparent_recalc, 1372 .recalc = &followparent_recalc,
1345}; 1373};
1346 1374
@@ -1351,6 +1379,7 @@ static struct clk mmchs3_fck = {
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1379 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1352 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1380 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1353 .flags = CLOCK_IN_OMAP3430ES2, 1381 .flags = CLOCK_IN_OMAP3430ES2,
1382 .clkdm_name = "core_l4_clkdm",
1354 .recalc = &followparent_recalc, 1383 .recalc = &followparent_recalc,
1355}; 1384};
1356 1385
@@ -1361,6 +1390,7 @@ static struct clk mmchs2_fck = {
1361 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1362 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1391 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1363 .flags = CLOCK_IN_OMAP343X, 1392 .flags = CLOCK_IN_OMAP343X,
1393 .clkdm_name = "core_l4_clkdm",
1364 .recalc = &followparent_recalc, 1394 .recalc = &followparent_recalc,
1365}; 1395};
1366 1396
@@ -1370,6 +1400,7 @@ static struct clk mspro_fck = {
1370 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1401 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1372 .flags = CLOCK_IN_OMAP343X, 1402 .flags = CLOCK_IN_OMAP343X,
1403 .clkdm_name = "core_l4_clkdm",
1373 .recalc = &followparent_recalc, 1404 .recalc = &followparent_recalc,
1374}; 1405};
1375 1406
@@ -1380,6 +1411,7 @@ static struct clk mmchs1_fck = {
1380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1411 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1381 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1412 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1382 .flags = CLOCK_IN_OMAP343X, 1413 .flags = CLOCK_IN_OMAP343X,
1414 .clkdm_name = "core_l4_clkdm",
1383 .recalc = &followparent_recalc, 1415 .recalc = &followparent_recalc,
1384}; 1416};
1385 1417
@@ -1390,16 +1422,18 @@ static struct clk i2c3_fck = {
1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1422 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1423 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1392 .flags = CLOCK_IN_OMAP343X, 1424 .flags = CLOCK_IN_OMAP343X,
1425 .clkdm_name = "core_l4_clkdm",
1393 .recalc = &followparent_recalc, 1426 .recalc = &followparent_recalc,
1394}; 1427};
1395 1428
1396static struct clk i2c2_fck = { 1429static struct clk i2c2_fck = {
1397 .name = "i2c_fck", 1430 .name = "i2c_fck",
1398 .id = 2, 1431 .id = 2,
1399 .parent = &core_96m_fck, 1432 .parent = &core_96m_fck,
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1433 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1434 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1402 .flags = CLOCK_IN_OMAP343X, 1435 .flags = CLOCK_IN_OMAP343X,
1436 .clkdm_name = "core_l4_clkdm",
1403 .recalc = &followparent_recalc, 1437 .recalc = &followparent_recalc,
1404}; 1438};
1405 1439
@@ -1410,6 +1444,7 @@ static struct clk i2c1_fck = {
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1444 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1445 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1412 .flags = CLOCK_IN_OMAP343X, 1446 .flags = CLOCK_IN_OMAP343X,
1447 .clkdm_name = "core_l4_clkdm",
1413 .recalc = &followparent_recalc, 1448 .recalc = &followparent_recalc,
1414}; 1449};
1415 1450
@@ -1443,6 +1478,7 @@ static struct clk mcbsp5_fck = {
1443 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, 1478 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1444 .clksel = mcbsp_15_clksel, 1479 .clksel = mcbsp_15_clksel,
1445 .flags = CLOCK_IN_OMAP343X, 1480 .flags = CLOCK_IN_OMAP343X,
1481 .clkdm_name = "core_l4_clkdm",
1446 .recalc = &omap2_clksel_recalc, 1482 .recalc = &omap2_clksel_recalc,
1447}; 1483};
1448 1484
@@ -1456,6 +1492,7 @@ static struct clk mcbsp1_fck = {
1456 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, 1492 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1457 .clksel = mcbsp_15_clksel, 1493 .clksel = mcbsp_15_clksel,
1458 .flags = CLOCK_IN_OMAP343X, 1494 .flags = CLOCK_IN_OMAP343X,
1495 .clkdm_name = "core_l4_clkdm",
1459 .recalc = &omap2_clksel_recalc, 1496 .recalc = &omap2_clksel_recalc,
1460}; 1497};
1461 1498
@@ -1466,6 +1503,7 @@ static struct clk core_48m_fck = {
1466 .parent = &omap_48m_fck, 1503 .parent = &omap_48m_fck,
1467 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1504 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1468 PARENT_CONTROLS_CLOCK, 1505 PARENT_CONTROLS_CLOCK,
1506 .clkdm_name = "core_l4_clkdm",
1469 .recalc = &followparent_recalc, 1507 .recalc = &followparent_recalc,
1470}; 1508};
1471 1509
@@ -1543,6 +1581,7 @@ static struct clk core_12m_fck = {
1543 .parent = &omap_12m_fck, 1581 .parent = &omap_12m_fck,
1544 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1582 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1545 PARENT_CONTROLS_CLOCK, 1583 PARENT_CONTROLS_CLOCK,
1584 .clkdm_name = "core_l4_clkdm",
1546 .recalc = &followparent_recalc, 1585 .recalc = &followparent_recalc,
1547}; 1586};
1548 1587
@@ -1581,6 +1620,7 @@ static struct clk ssi_ssr_fck = {
1581 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, 1620 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1582 .clksel = ssi_ssr_clksel, 1621 .clksel = ssi_ssr_clksel,
1583 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1622 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1623 .clkdm_name = "core_l4_clkdm",
1584 .recalc = &omap2_clksel_recalc, 1624 .recalc = &omap2_clksel_recalc,
1585}; 1625};
1586 1626
@@ -1596,11 +1636,17 @@ static struct clk ssi_sst_fck = {
1596 1636
1597/* CORE_L3_ICK based clocks */ 1637/* CORE_L3_ICK based clocks */
1598 1638
1639/*
1640 * XXX must add clk_enable/clk_disable for these if standard code won't
1641 * handle it
1642 */
1599static struct clk core_l3_ick = { 1643static struct clk core_l3_ick = {
1600 .name = "core_l3_ick", 1644 .name = "core_l3_ick",
1601 .parent = &l3_ick, 1645 .parent = &l3_ick,
1646 .init = &omap2_init_clk_clkdm,
1602 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1647 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1603 PARENT_CONTROLS_CLOCK, 1648 PARENT_CONTROLS_CLOCK,
1649 .clkdm_name = "core_l3_clkdm",
1604 .recalc = &followparent_recalc, 1650 .recalc = &followparent_recalc,
1605}; 1651};
1606 1652
@@ -1610,6 +1656,7 @@ static struct clk hsotgusb_ick = {
1610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1611 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1657 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1612 .flags = CLOCK_IN_OMAP343X, 1658 .flags = CLOCK_IN_OMAP343X,
1659 .clkdm_name = "core_l3_clkdm",
1613 .recalc = &followparent_recalc, 1660 .recalc = &followparent_recalc,
1614}; 1661};
1615 1662
@@ -1619,6 +1666,7 @@ static struct clk sdrc_ick = {
1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1666 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1620 .enable_bit = OMAP3430_EN_SDRC_SHIFT, 1667 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1621 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1668 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1669 .clkdm_name = "core_l3_clkdm",
1622 .recalc = &followparent_recalc, 1670 .recalc = &followparent_recalc,
1623}; 1671};
1624 1672
@@ -1627,6 +1675,7 @@ static struct clk gpmc_fck = {
1627 .parent = &core_l3_ick, 1675 .parent = &core_l3_ick,
1628 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | 1676 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1629 ENABLE_ON_INIT, 1677 ENABLE_ON_INIT,
1678 .clkdm_name = "core_l3_clkdm",
1630 .recalc = &followparent_recalc, 1679 .recalc = &followparent_recalc,
1631}; 1680};
1632 1681
@@ -1654,8 +1703,10 @@ static struct clk pka_ick = {
1654static struct clk core_l4_ick = { 1703static struct clk core_l4_ick = {
1655 .name = "core_l4_ick", 1704 .name = "core_l4_ick",
1656 .parent = &l4_ick, 1705 .parent = &l4_ick,
1706 .init = &omap2_init_clk_clkdm,
1657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1707 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1658 PARENT_CONTROLS_CLOCK, 1708 PARENT_CONTROLS_CLOCK,
1709 .clkdm_name = "core_l4_clkdm",
1659 .recalc = &followparent_recalc, 1710 .recalc = &followparent_recalc,
1660}; 1711};
1661 1712
@@ -1665,6 +1716,7 @@ static struct clk usbtll_ick = {
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1716 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1666 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1717 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1667 .flags = CLOCK_IN_OMAP3430ES2, 1718 .flags = CLOCK_IN_OMAP3430ES2,
1719 .clkdm_name = "core_l4_clkdm",
1668 .recalc = &followparent_recalc, 1720 .recalc = &followparent_recalc,
1669}; 1721};
1670 1722
@@ -1675,6 +1727,7 @@ static struct clk mmchs3_ick = {
1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1676 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1728 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1677 .flags = CLOCK_IN_OMAP3430ES2, 1729 .flags = CLOCK_IN_OMAP3430ES2,
1730 .clkdm_name = "core_l4_clkdm",
1678 .recalc = &followparent_recalc, 1731 .recalc = &followparent_recalc,
1679}; 1732};
1680 1733
@@ -1685,6 +1738,7 @@ static struct clk icr_ick = {
1685 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1686 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1739 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1687 .flags = CLOCK_IN_OMAP343X, 1740 .flags = CLOCK_IN_OMAP343X,
1741 .clkdm_name = "core_l4_clkdm",
1688 .recalc = &followparent_recalc, 1742 .recalc = &followparent_recalc,
1689}; 1743};
1690 1744
@@ -1694,6 +1748,7 @@ static struct clk aes2_ick = {
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1748 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1749 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1696 .flags = CLOCK_IN_OMAP343X, 1750 .flags = CLOCK_IN_OMAP343X,
1751 .clkdm_name = "core_l4_clkdm",
1697 .recalc = &followparent_recalc, 1752 .recalc = &followparent_recalc,
1698}; 1753};
1699 1754
@@ -1703,6 +1758,7 @@ static struct clk sha12_ick = {
1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1758 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1704 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1759 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1705 .flags = CLOCK_IN_OMAP343X, 1760 .flags = CLOCK_IN_OMAP343X,
1761 .clkdm_name = "core_l4_clkdm",
1706 .recalc = &followparent_recalc, 1762 .recalc = &followparent_recalc,
1707}; 1763};
1708 1764
@@ -1712,6 +1768,7 @@ static struct clk des2_ick = {
1712 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1768 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1713 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1769 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1714 .flags = CLOCK_IN_OMAP343X, 1770 .flags = CLOCK_IN_OMAP343X,
1771 .clkdm_name = "core_l4_clkdm",
1715 .recalc = &followparent_recalc, 1772 .recalc = &followparent_recalc,
1716}; 1773};
1717 1774
@@ -1722,6 +1779,7 @@ static struct clk mmchs2_ick = {
1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1779 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1780 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1724 .flags = CLOCK_IN_OMAP343X, 1781 .flags = CLOCK_IN_OMAP343X,
1782 .clkdm_name = "core_l4_clkdm",
1725 .recalc = &followparent_recalc, 1783 .recalc = &followparent_recalc,
1726}; 1784};
1727 1785
@@ -1732,6 +1790,7 @@ static struct clk mmchs1_ick = {
1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1791 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1734 .flags = CLOCK_IN_OMAP343X, 1792 .flags = CLOCK_IN_OMAP343X,
1793 .clkdm_name = "core_l4_clkdm",
1735 .recalc = &followparent_recalc, 1794 .recalc = &followparent_recalc,
1736}; 1795};
1737 1796
@@ -1741,6 +1800,7 @@ static struct clk mspro_ick = {
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1801 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1743 .flags = CLOCK_IN_OMAP343X, 1802 .flags = CLOCK_IN_OMAP343X,
1803 .clkdm_name = "core_l4_clkdm",
1744 .recalc = &followparent_recalc, 1804 .recalc = &followparent_recalc,
1745}; 1805};
1746 1806
@@ -1750,6 +1810,7 @@ static struct clk hdq_ick = {
1750 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1751 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1811 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1752 .flags = CLOCK_IN_OMAP343X, 1812 .flags = CLOCK_IN_OMAP343X,
1813 .clkdm_name = "core_l4_clkdm",
1753 .recalc = &followparent_recalc, 1814 .recalc = &followparent_recalc,
1754}; 1815};
1755 1816
@@ -1760,6 +1821,7 @@ static struct clk mcspi4_ick = {
1760 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1761 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1822 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1762 .flags = CLOCK_IN_OMAP343X, 1823 .flags = CLOCK_IN_OMAP343X,
1824 .clkdm_name = "core_l4_clkdm",
1763 .recalc = &followparent_recalc, 1825 .recalc = &followparent_recalc,
1764}; 1826};
1765 1827
@@ -1770,6 +1832,7 @@ static struct clk mcspi3_ick = {
1770 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1771 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1833 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1772 .flags = CLOCK_IN_OMAP343X, 1834 .flags = CLOCK_IN_OMAP343X,
1835 .clkdm_name = "core_l4_clkdm",
1773 .recalc = &followparent_recalc, 1836 .recalc = &followparent_recalc,
1774}; 1837};
1775 1838
@@ -1780,6 +1843,7 @@ static struct clk mcspi2_ick = {
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1843 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1781 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1844 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1782 .flags = CLOCK_IN_OMAP343X, 1845 .flags = CLOCK_IN_OMAP343X,
1846 .clkdm_name = "core_l4_clkdm",
1783 .recalc = &followparent_recalc, 1847 .recalc = &followparent_recalc,
1784}; 1848};
1785 1849
@@ -1790,6 +1854,7 @@ static struct clk mcspi1_ick = {
1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1854 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1791 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1855 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1792 .flags = CLOCK_IN_OMAP343X, 1856 .flags = CLOCK_IN_OMAP343X,
1857 .clkdm_name = "core_l4_clkdm",
1793 .recalc = &followparent_recalc, 1858 .recalc = &followparent_recalc,
1794}; 1859};
1795 1860
@@ -1800,6 +1865,7 @@ static struct clk i2c3_ick = {
1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1866 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1802 .flags = CLOCK_IN_OMAP343X, 1867 .flags = CLOCK_IN_OMAP343X,
1868 .clkdm_name = "core_l4_clkdm",
1803 .recalc = &followparent_recalc, 1869 .recalc = &followparent_recalc,
1804}; 1870};
1805 1871
@@ -1810,6 +1876,7 @@ static struct clk i2c2_ick = {
1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1877 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1812 .flags = CLOCK_IN_OMAP343X, 1878 .flags = CLOCK_IN_OMAP343X,
1879 .clkdm_name = "core_l4_clkdm",
1813 .recalc = &followparent_recalc, 1880 .recalc = &followparent_recalc,
1814}; 1881};
1815 1882
@@ -1820,6 +1887,7 @@ static struct clk i2c1_ick = {
1820 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1887 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1888 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1822 .flags = CLOCK_IN_OMAP343X, 1889 .flags = CLOCK_IN_OMAP343X,
1890 .clkdm_name = "core_l4_clkdm",
1823 .recalc = &followparent_recalc, 1891 .recalc = &followparent_recalc,
1824}; 1892};
1825 1893
@@ -1829,6 +1897,7 @@ static struct clk uart2_ick = {
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1897 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1898 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1831 .flags = CLOCK_IN_OMAP343X, 1899 .flags = CLOCK_IN_OMAP343X,
1900 .clkdm_name = "core_l4_clkdm",
1832 .recalc = &followparent_recalc, 1901 .recalc = &followparent_recalc,
1833}; 1902};
1834 1903
@@ -1838,6 +1907,7 @@ static struct clk uart1_ick = {
1838 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1907 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1839 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1908 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1840 .flags = CLOCK_IN_OMAP343X, 1909 .flags = CLOCK_IN_OMAP343X,
1910 .clkdm_name = "core_l4_clkdm",
1841 .recalc = &followparent_recalc, 1911 .recalc = &followparent_recalc,
1842}; 1912};
1843 1913
@@ -1847,6 +1917,7 @@ static struct clk gpt11_ick = {
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1917 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1848 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1918 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1849 .flags = CLOCK_IN_OMAP343X, 1919 .flags = CLOCK_IN_OMAP343X,
1920 .clkdm_name = "core_l4_clkdm",
1850 .recalc = &followparent_recalc, 1921 .recalc = &followparent_recalc,
1851}; 1922};
1852 1923
@@ -1856,6 +1927,7 @@ static struct clk gpt10_ick = {
1856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1927 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1857 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1928 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1858 .flags = CLOCK_IN_OMAP343X, 1929 .flags = CLOCK_IN_OMAP343X,
1930 .clkdm_name = "core_l4_clkdm",
1859 .recalc = &followparent_recalc, 1931 .recalc = &followparent_recalc,
1860}; 1932};
1861 1933
@@ -1866,6 +1938,7 @@ static struct clk mcbsp5_ick = {
1866 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1939 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1868 .flags = CLOCK_IN_OMAP343X, 1940 .flags = CLOCK_IN_OMAP343X,
1941 .clkdm_name = "core_l4_clkdm",
1869 .recalc = &followparent_recalc, 1942 .recalc = &followparent_recalc,
1870}; 1943};
1871 1944
@@ -1876,6 +1949,7 @@ static struct clk mcbsp1_ick = {
1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1949 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1877 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1950 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1878 .flags = CLOCK_IN_OMAP343X, 1951 .flags = CLOCK_IN_OMAP343X,
1952 .clkdm_name = "core_l4_clkdm",
1879 .recalc = &followparent_recalc, 1953 .recalc = &followparent_recalc,
1880}; 1954};
1881 1955
@@ -1885,6 +1959,7 @@ static struct clk fac_ick = {
1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1959 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 1960 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1887 .flags = CLOCK_IN_OMAP3430ES1, 1961 .flags = CLOCK_IN_OMAP3430ES1,
1962 .clkdm_name = "core_l4_clkdm",
1888 .recalc = &followparent_recalc, 1963 .recalc = &followparent_recalc,
1889}; 1964};
1890 1965
@@ -1894,6 +1969,7 @@ static struct clk mailboxes_ick = {
1894 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1969 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1895 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1970 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1896 .flags = CLOCK_IN_OMAP343X, 1971 .flags = CLOCK_IN_OMAP343X,
1972 .clkdm_name = "core_l4_clkdm",
1897 .recalc = &followparent_recalc, 1973 .recalc = &followparent_recalc,
1898}; 1974};
1899 1975
@@ -1913,6 +1989,7 @@ static struct clk ssi_l4_ick = {
1913 .parent = &l4_ick, 1989 .parent = &l4_ick,
1914 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1990 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1915 PARENT_CONTROLS_CLOCK, 1991 PARENT_CONTROLS_CLOCK,
1992 .clkdm_name = "core_l4_clkdm",
1916 .recalc = &followparent_recalc, 1993 .recalc = &followparent_recalc,
1917}; 1994};
1918 1995
@@ -1922,6 +1999,7 @@ static struct clk ssi_ick = {
1922 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2000 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1924 .flags = CLOCK_IN_OMAP343X, 2001 .flags = CLOCK_IN_OMAP343X,
2002 .clkdm_name = "core_l4_clkdm",
1925 .recalc = &followparent_recalc, 2003 .recalc = &followparent_recalc,
1926}; 2004};
1927 2005
@@ -1996,7 +2074,7 @@ static struct clk des1_ick = {
1996 2074
1997/* DSS */ 2075/* DSS */
1998static const struct clksel dss1_alwon_fck_clksel[] = { 2076static const struct clksel dss1_alwon_fck_clksel[] = {
1999 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 2077 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2000 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, 2078 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2001 { .parent = NULL } 2079 { .parent = NULL }
2002}; 2080};
@@ -2011,33 +2089,40 @@ static struct clk dss1_alwon_fck = {
2011 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 2089 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2012 .clksel = dss1_alwon_fck_clksel, 2090 .clksel = dss1_alwon_fck_clksel,
2013 .flags = CLOCK_IN_OMAP343X, 2091 .flags = CLOCK_IN_OMAP343X,
2092 .clkdm_name = "dss_clkdm",
2014 .recalc = &omap2_clksel_recalc, 2093 .recalc = &omap2_clksel_recalc,
2015}; 2094};
2016 2095
2017static struct clk dss_tv_fck = { 2096static struct clk dss_tv_fck = {
2018 .name = "dss_tv_fck", 2097 .name = "dss_tv_fck",
2019 .parent = &omap_54m_fck, 2098 .parent = &omap_54m_fck,
2099 .init = &omap2_init_clk_clkdm,
2020 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2100 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2021 .enable_bit = OMAP3430_EN_TV_SHIFT, 2101 .enable_bit = OMAP3430_EN_TV_SHIFT,
2022 .flags = CLOCK_IN_OMAP343X, 2102 .flags = CLOCK_IN_OMAP343X,
2103 .clkdm_name = "dss_clkdm",
2023 .recalc = &followparent_recalc, 2104 .recalc = &followparent_recalc,
2024}; 2105};
2025 2106
2026static struct clk dss_96m_fck = { 2107static struct clk dss_96m_fck = {
2027 .name = "dss_96m_fck", 2108 .name = "dss_96m_fck",
2028 .parent = &omap_96m_fck, 2109 .parent = &omap_96m_fck,
2110 .init = &omap2_init_clk_clkdm,
2029 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2111 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2030 .enable_bit = OMAP3430_EN_TV_SHIFT, 2112 .enable_bit = OMAP3430_EN_TV_SHIFT,
2031 .flags = CLOCK_IN_OMAP343X, 2113 .flags = CLOCK_IN_OMAP343X,
2114 .clkdm_name = "dss_clkdm",
2032 .recalc = &followparent_recalc, 2115 .recalc = &followparent_recalc,
2033}; 2116};
2034 2117
2035static struct clk dss2_alwon_fck = { 2118static struct clk dss2_alwon_fck = {
2036 .name = "dss2_alwon_fck", 2119 .name = "dss2_alwon_fck",
2037 .parent = &sys_ck, 2120 .parent = &sys_ck,
2121 .init = &omap2_init_clk_clkdm,
2038 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2122 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2039 .enable_bit = OMAP3430_EN_DSS2_SHIFT, 2123 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2040 .flags = CLOCK_IN_OMAP343X, 2124 .flags = CLOCK_IN_OMAP343X,
2125 .clkdm_name = "dss_clkdm",
2041 .recalc = &followparent_recalc, 2126 .recalc = &followparent_recalc,
2042}; 2127};
2043 2128
@@ -2045,16 +2130,18 @@ static struct clk dss_ick = {
2045 /* Handles both L3 and L4 clocks */ 2130 /* Handles both L3 and L4 clocks */
2046 .name = "dss_ick", 2131 .name = "dss_ick",
2047 .parent = &l4_ick, 2132 .parent = &l4_ick,
2133 .init = &omap2_init_clk_clkdm,
2048 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2134 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2049 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2135 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2050 .flags = CLOCK_IN_OMAP343X, 2136 .flags = CLOCK_IN_OMAP343X,
2137 .clkdm_name = "dss_clkdm",
2051 .recalc = &followparent_recalc, 2138 .recalc = &followparent_recalc,
2052}; 2139};
2053 2140
2054/* CAM */ 2141/* CAM */
2055 2142
2056static const struct clksel cam_mclk_clksel[] = { 2143static const struct clksel cam_mclk_clksel[] = {
2057 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 2144 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2058 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, 2145 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2059 { .parent = NULL } 2146 { .parent = NULL }
2060}; 2147};
@@ -2069,24 +2156,19 @@ static struct clk cam_mclk = {
2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2156 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2070 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2157 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2071 .flags = CLOCK_IN_OMAP343X, 2158 .flags = CLOCK_IN_OMAP343X,
2159 .clkdm_name = "cam_clkdm",
2072 .recalc = &omap2_clksel_recalc, 2160 .recalc = &omap2_clksel_recalc,
2073}; 2161};
2074 2162
2075static struct clk cam_l3_ick = { 2163static struct clk cam_ick = {
2076 .name = "cam_l3_ick", 2164 /* Handles both L3 and L4 clocks */
2077 .parent = &l3_ick, 2165 .name = "cam_ick",
2078 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2079 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2080 .flags = CLOCK_IN_OMAP343X,
2081 .recalc = &followparent_recalc,
2082};
2083
2084static struct clk cam_l4_ick = {
2085 .name = "cam_l4_ick",
2086 .parent = &l4_ick, 2166 .parent = &l4_ick,
2167 .init = &omap2_init_clk_clkdm,
2087 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2168 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2088 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2169 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2089 .flags = CLOCK_IN_OMAP343X, 2170 .flags = CLOCK_IN_OMAP343X,
2171 .clkdm_name = "cam_clkdm",
2090 .recalc = &followparent_recalc, 2172 .recalc = &followparent_recalc,
2091}; 2173};
2092 2174
@@ -2095,45 +2177,45 @@ static struct clk cam_l4_ick = {
2095static struct clk usbhost_120m_fck = { 2177static struct clk usbhost_120m_fck = {
2096 .name = "usbhost_120m_fck", 2178 .name = "usbhost_120m_fck",
2097 .parent = &omap_120m_fck, 2179 .parent = &omap_120m_fck,
2180 .init = &omap2_init_clk_clkdm,
2098 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2181 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2099 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, 2182 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2100 .flags = CLOCK_IN_OMAP3430ES2, 2183 .flags = CLOCK_IN_OMAP3430ES2,
2184 .clkdm_name = "usbhost_clkdm",
2101 .recalc = &followparent_recalc, 2185 .recalc = &followparent_recalc,
2102}; 2186};
2103 2187
2104static struct clk usbhost_48m_fck = { 2188static struct clk usbhost_48m_fck = {
2105 .name = "usbhost_48m_fck", 2189 .name = "usbhost_48m_fck",
2106 .parent = &omap_48m_fck, 2190 .parent = &omap_48m_fck,
2191 .init = &omap2_init_clk_clkdm,
2107 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2192 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2108 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 2193 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2109 .flags = CLOCK_IN_OMAP3430ES2, 2194 .flags = CLOCK_IN_OMAP3430ES2,
2195 .clkdm_name = "usbhost_clkdm",
2110 .recalc = &followparent_recalc, 2196 .recalc = &followparent_recalc,
2111}; 2197};
2112 2198
2113static struct clk usbhost_l3_ick = { 2199static struct clk usbhost_ick = {
2114 .name = "usbhost_l3_ick", 2200 /* Handles both L3 and L4 clocks */
2115 .parent = &l3_ick, 2201 .name = "usbhost_ick",
2116 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2117 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2118 .flags = CLOCK_IN_OMAP3430ES2,
2119 .recalc = &followparent_recalc,
2120};
2121
2122static struct clk usbhost_l4_ick = {
2123 .name = "usbhost_l4_ick",
2124 .parent = &l4_ick, 2202 .parent = &l4_ick,
2203 .init = &omap2_init_clk_clkdm,
2125 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2204 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2126 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2205 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2127 .flags = CLOCK_IN_OMAP3430ES2, 2206 .flags = CLOCK_IN_OMAP3430ES2,
2207 .clkdm_name = "usbhost_clkdm",
2128 .recalc = &followparent_recalc, 2208 .recalc = &followparent_recalc,
2129}; 2209};
2130 2210
2131static struct clk usbhost_sar_fck = { 2211static struct clk usbhost_sar_fck = {
2132 .name = "usbhost_sar_fck", 2212 .name = "usbhost_sar_fck",
2133 .parent = &osc_sys_ck, 2213 .parent = &osc_sys_ck,
2214 .init = &omap2_init_clk_clkdm,
2134 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), 2215 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2135 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, 2216 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2136 .flags = CLOCK_IN_OMAP3430ES2, 2217 .flags = CLOCK_IN_OMAP3430ES2,
2218 .clkdm_name = "usbhost_clkdm",
2137 .recalc = &followparent_recalc, 2219 .recalc = &followparent_recalc,
2138}; 2220};
2139 2221
@@ -2175,6 +2257,7 @@ static struct clk usim_fck = {
2175 .recalc = &omap2_clksel_recalc, 2257 .recalc = &omap2_clksel_recalc,
2176}; 2258};
2177 2259
2260/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2178static struct clk gpt1_fck = { 2261static struct clk gpt1_fck = {
2179 .name = "gpt1_fck", 2262 .name = "gpt1_fck",
2180 .init = &omap2_init_clksel_parent, 2263 .init = &omap2_init_clksel_parent,
@@ -2184,13 +2267,16 @@ static struct clk gpt1_fck = {
2184 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, 2267 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2185 .clksel = omap343x_gpt_clksel, 2268 .clksel = omap343x_gpt_clksel,
2186 .flags = CLOCK_IN_OMAP343X, 2269 .flags = CLOCK_IN_OMAP343X,
2270 .clkdm_name = "wkup_clkdm",
2187 .recalc = &omap2_clksel_recalc, 2271 .recalc = &omap2_clksel_recalc,
2188}; 2272};
2189 2273
2190static struct clk wkup_32k_fck = { 2274static struct clk wkup_32k_fck = {
2191 .name = "wkup_32k_fck", 2275 .name = "wkup_32k_fck",
2276 .init = &omap2_init_clk_clkdm,
2192 .parent = &omap_32k_fck, 2277 .parent = &omap_32k_fck,
2193 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2278 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2279 .clkdm_name = "wkup_clkdm",
2194 .recalc = &followparent_recalc, 2280 .recalc = &followparent_recalc,
2195}; 2281};
2196 2282
@@ -2200,6 +2286,7 @@ static struct clk gpio1_fck = {
2200 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2286 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2201 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2287 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2202 .flags = CLOCK_IN_OMAP343X, 2288 .flags = CLOCK_IN_OMAP343X,
2289 .clkdm_name = "wkup_clkdm",
2203 .recalc = &followparent_recalc, 2290 .recalc = &followparent_recalc,
2204}; 2291};
2205 2292
@@ -2209,6 +2296,7 @@ static struct clk wdt2_fck = {
2209 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2296 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2210 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2297 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2211 .flags = CLOCK_IN_OMAP343X, 2298 .flags = CLOCK_IN_OMAP343X,
2299 .clkdm_name = "wkup_clkdm",
2212 .recalc = &followparent_recalc, 2300 .recalc = &followparent_recalc,
2213}; 2301};
2214 2302
@@ -2216,6 +2304,7 @@ static struct clk wkup_l4_ick = {
2216 .name = "wkup_l4_ick", 2304 .name = "wkup_l4_ick",
2217 .parent = &sys_ck, 2305 .parent = &sys_ck,
2218 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2306 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2307 .clkdm_name = "wkup_clkdm",
2219 .recalc = &followparent_recalc, 2308 .recalc = &followparent_recalc,
2220}; 2309};
2221 2310
@@ -2227,6 +2316,7 @@ static struct clk usim_ick = {
2227 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2316 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2228 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2317 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2229 .flags = CLOCK_IN_OMAP3430ES2, 2318 .flags = CLOCK_IN_OMAP3430ES2,
2319 .clkdm_name = "wkup_clkdm",
2230 .recalc = &followparent_recalc, 2320 .recalc = &followparent_recalc,
2231}; 2321};
2232 2322
@@ -2236,6 +2326,7 @@ static struct clk wdt2_ick = {
2236 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2326 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2237 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2327 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2238 .flags = CLOCK_IN_OMAP343X, 2328 .flags = CLOCK_IN_OMAP343X,
2329 .clkdm_name = "wkup_clkdm",
2239 .recalc = &followparent_recalc, 2330 .recalc = &followparent_recalc,
2240}; 2331};
2241 2332
@@ -2245,6 +2336,7 @@ static struct clk wdt1_ick = {
2245 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2336 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2246 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2337 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2247 .flags = CLOCK_IN_OMAP343X, 2338 .flags = CLOCK_IN_OMAP343X,
2339 .clkdm_name = "wkup_clkdm",
2248 .recalc = &followparent_recalc, 2340 .recalc = &followparent_recalc,
2249}; 2341};
2250 2342
@@ -2254,6 +2346,7 @@ static struct clk gpio1_ick = {
2254 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2346 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2255 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2347 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2256 .flags = CLOCK_IN_OMAP343X, 2348 .flags = CLOCK_IN_OMAP343X,
2349 .clkdm_name = "wkup_clkdm",
2257 .recalc = &followparent_recalc, 2350 .recalc = &followparent_recalc,
2258}; 2351};
2259 2352
@@ -2263,15 +2356,18 @@ static struct clk omap_32ksync_ick = {
2263 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2356 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2264 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2357 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2265 .flags = CLOCK_IN_OMAP343X, 2358 .flags = CLOCK_IN_OMAP343X,
2359 .clkdm_name = "wkup_clkdm",
2266 .recalc = &followparent_recalc, 2360 .recalc = &followparent_recalc,
2267}; 2361};
2268 2362
2363/* XXX This clock no longer exists in 3430 TRM rev F */
2269static struct clk gpt12_ick = { 2364static struct clk gpt12_ick = {
2270 .name = "gpt12_ick", 2365 .name = "gpt12_ick",
2271 .parent = &wkup_l4_ick, 2366 .parent = &wkup_l4_ick,
2272 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2367 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2273 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2368 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2274 .flags = CLOCK_IN_OMAP343X, 2369 .flags = CLOCK_IN_OMAP343X,
2370 .clkdm_name = "wkup_clkdm",
2275 .recalc = &followparent_recalc, 2371 .recalc = &followparent_recalc,
2276}; 2372};
2277 2373
@@ -2281,6 +2377,7 @@ static struct clk gpt1_ick = {
2281 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2377 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2282 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2378 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2283 .flags = CLOCK_IN_OMAP343X, 2379 .flags = CLOCK_IN_OMAP343X,
2380 .clkdm_name = "wkup_clkdm",
2284 .recalc = &followparent_recalc, 2381 .recalc = &followparent_recalc,
2285}; 2382};
2286 2383
@@ -2291,16 +2388,20 @@ static struct clk gpt1_ick = {
2291static struct clk per_96m_fck = { 2388static struct clk per_96m_fck = {
2292 .name = "per_96m_fck", 2389 .name = "per_96m_fck",
2293 .parent = &omap_96m_alwon_fck, 2390 .parent = &omap_96m_alwon_fck,
2391 .init = &omap2_init_clk_clkdm,
2294 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2392 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2295 PARENT_CONTROLS_CLOCK, 2393 PARENT_CONTROLS_CLOCK,
2394 .clkdm_name = "per_clkdm",
2296 .recalc = &followparent_recalc, 2395 .recalc = &followparent_recalc,
2297}; 2396};
2298 2397
2299static struct clk per_48m_fck = { 2398static struct clk per_48m_fck = {
2300 .name = "per_48m_fck", 2399 .name = "per_48m_fck",
2301 .parent = &omap_48m_fck, 2400 .parent = &omap_48m_fck,
2401 .init = &omap2_init_clk_clkdm,
2302 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2402 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2303 PARENT_CONTROLS_CLOCK, 2403 PARENT_CONTROLS_CLOCK,
2404 .clkdm_name = "per_clkdm",
2304 .recalc = &followparent_recalc, 2405 .recalc = &followparent_recalc,
2305}; 2406};
2306 2407
@@ -2310,6 +2411,7 @@ static struct clk uart3_fck = {
2310 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2411 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2311 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2412 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2312 .flags = CLOCK_IN_OMAP343X, 2413 .flags = CLOCK_IN_OMAP343X,
2414 .clkdm_name = "per_clkdm",
2313 .recalc = &followparent_recalc, 2415 .recalc = &followparent_recalc,
2314}; 2416};
2315 2417
@@ -2322,6 +2424,7 @@ static struct clk gpt2_fck = {
2322 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, 2424 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2323 .clksel = omap343x_gpt_clksel, 2425 .clksel = omap343x_gpt_clksel,
2324 .flags = CLOCK_IN_OMAP343X, 2426 .flags = CLOCK_IN_OMAP343X,
2427 .clkdm_name = "per_clkdm",
2325 .recalc = &omap2_clksel_recalc, 2428 .recalc = &omap2_clksel_recalc,
2326}; 2429};
2327 2430
@@ -2334,6 +2437,7 @@ static struct clk gpt3_fck = {
2334 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, 2437 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2335 .clksel = omap343x_gpt_clksel, 2438 .clksel = omap343x_gpt_clksel,
2336 .flags = CLOCK_IN_OMAP343X, 2439 .flags = CLOCK_IN_OMAP343X,
2440 .clkdm_name = "per_clkdm",
2337 .recalc = &omap2_clksel_recalc, 2441 .recalc = &omap2_clksel_recalc,
2338}; 2442};
2339 2443
@@ -2346,6 +2450,7 @@ static struct clk gpt4_fck = {
2346 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, 2450 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2347 .clksel = omap343x_gpt_clksel, 2451 .clksel = omap343x_gpt_clksel,
2348 .flags = CLOCK_IN_OMAP343X, 2452 .flags = CLOCK_IN_OMAP343X,
2453 .clkdm_name = "per_clkdm",
2349 .recalc = &omap2_clksel_recalc, 2454 .recalc = &omap2_clksel_recalc,
2350}; 2455};
2351 2456
@@ -2358,6 +2463,7 @@ static struct clk gpt5_fck = {
2358 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, 2463 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2359 .clksel = omap343x_gpt_clksel, 2464 .clksel = omap343x_gpt_clksel,
2360 .flags = CLOCK_IN_OMAP343X, 2465 .flags = CLOCK_IN_OMAP343X,
2466 .clkdm_name = "per_clkdm",
2361 .recalc = &omap2_clksel_recalc, 2467 .recalc = &omap2_clksel_recalc,
2362}; 2468};
2363 2469
@@ -2370,6 +2476,7 @@ static struct clk gpt6_fck = {
2370 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, 2476 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2371 .clksel = omap343x_gpt_clksel, 2477 .clksel = omap343x_gpt_clksel,
2372 .flags = CLOCK_IN_OMAP343X, 2478 .flags = CLOCK_IN_OMAP343X,
2479 .clkdm_name = "per_clkdm",
2373 .recalc = &omap2_clksel_recalc, 2480 .recalc = &omap2_clksel_recalc,
2374}; 2481};
2375 2482
@@ -2382,6 +2489,7 @@ static struct clk gpt7_fck = {
2382 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, 2489 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2383 .clksel = omap343x_gpt_clksel, 2490 .clksel = omap343x_gpt_clksel,
2384 .flags = CLOCK_IN_OMAP343X, 2491 .flags = CLOCK_IN_OMAP343X,
2492 .clkdm_name = "per_clkdm",
2385 .recalc = &omap2_clksel_recalc, 2493 .recalc = &omap2_clksel_recalc,
2386}; 2494};
2387 2495
@@ -2394,6 +2502,7 @@ static struct clk gpt8_fck = {
2394 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, 2502 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2395 .clksel = omap343x_gpt_clksel, 2503 .clksel = omap343x_gpt_clksel,
2396 .flags = CLOCK_IN_OMAP343X, 2504 .flags = CLOCK_IN_OMAP343X,
2505 .clkdm_name = "per_clkdm",
2397 .recalc = &omap2_clksel_recalc, 2506 .recalc = &omap2_clksel_recalc,
2398}; 2507};
2399 2508
@@ -2406,12 +2515,14 @@ static struct clk gpt9_fck = {
2406 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, 2515 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2407 .clksel = omap343x_gpt_clksel, 2516 .clksel = omap343x_gpt_clksel,
2408 .flags = CLOCK_IN_OMAP343X, 2517 .flags = CLOCK_IN_OMAP343X,
2518 .clkdm_name = "per_clkdm",
2409 .recalc = &omap2_clksel_recalc, 2519 .recalc = &omap2_clksel_recalc,
2410}; 2520};
2411 2521
2412static struct clk per_32k_alwon_fck = { 2522static struct clk per_32k_alwon_fck = {
2413 .name = "per_32k_alwon_fck", 2523 .name = "per_32k_alwon_fck",
2414 .parent = &omap_32k_fck, 2524 .parent = &omap_32k_fck,
2525 .clkdm_name = "per_clkdm",
2415 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2526 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2416 .recalc = &followparent_recalc, 2527 .recalc = &followparent_recalc,
2417}; 2528};
@@ -2422,6 +2533,7 @@ static struct clk gpio6_fck = {
2422 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2533 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2423 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2534 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2424 .flags = CLOCK_IN_OMAP343X, 2535 .flags = CLOCK_IN_OMAP343X,
2536 .clkdm_name = "per_clkdm",
2425 .recalc = &followparent_recalc, 2537 .recalc = &followparent_recalc,
2426}; 2538};
2427 2539
@@ -2431,6 +2543,7 @@ static struct clk gpio5_fck = {
2431 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2543 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2432 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2544 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2433 .flags = CLOCK_IN_OMAP343X, 2545 .flags = CLOCK_IN_OMAP343X,
2546 .clkdm_name = "per_clkdm",
2434 .recalc = &followparent_recalc, 2547 .recalc = &followparent_recalc,
2435}; 2548};
2436 2549
@@ -2440,6 +2553,7 @@ static struct clk gpio4_fck = {
2440 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2553 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2441 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2554 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2442 .flags = CLOCK_IN_OMAP343X, 2555 .flags = CLOCK_IN_OMAP343X,
2556 .clkdm_name = "per_clkdm",
2443 .recalc = &followparent_recalc, 2557 .recalc = &followparent_recalc,
2444}; 2558};
2445 2559
@@ -2449,6 +2563,7 @@ static struct clk gpio3_fck = {
2449 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2563 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2450 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2564 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2451 .flags = CLOCK_IN_OMAP343X, 2565 .flags = CLOCK_IN_OMAP343X,
2566 .clkdm_name = "per_clkdm",
2452 .recalc = &followparent_recalc, 2567 .recalc = &followparent_recalc,
2453}; 2568};
2454 2569
@@ -2458,6 +2573,7 @@ static struct clk gpio2_fck = {
2458 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2573 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2459 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2574 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2460 .flags = CLOCK_IN_OMAP343X, 2575 .flags = CLOCK_IN_OMAP343X,
2576 .clkdm_name = "per_clkdm",
2461 .recalc = &followparent_recalc, 2577 .recalc = &followparent_recalc,
2462}; 2578};
2463 2579
@@ -2467,6 +2583,7 @@ static struct clk wdt3_fck = {
2467 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2583 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2468 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2584 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2469 .flags = CLOCK_IN_OMAP343X, 2585 .flags = CLOCK_IN_OMAP343X,
2586 .clkdm_name = "per_clkdm",
2470 .recalc = &followparent_recalc, 2587 .recalc = &followparent_recalc,
2471}; 2588};
2472 2589
@@ -2475,6 +2592,7 @@ static struct clk per_l4_ick = {
2475 .parent = &l4_ick, 2592 .parent = &l4_ick,
2476 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 2593 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2477 PARENT_CONTROLS_CLOCK, 2594 PARENT_CONTROLS_CLOCK,
2595 .clkdm_name = "per_clkdm",
2478 .recalc = &followparent_recalc, 2596 .recalc = &followparent_recalc,
2479}; 2597};
2480 2598
@@ -2484,6 +2602,7 @@ static struct clk gpio6_ick = {
2484 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2602 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2485 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2603 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2486 .flags = CLOCK_IN_OMAP343X, 2604 .flags = CLOCK_IN_OMAP343X,
2605 .clkdm_name = "per_clkdm",
2487 .recalc = &followparent_recalc, 2606 .recalc = &followparent_recalc,
2488}; 2607};
2489 2608
@@ -2493,6 +2612,7 @@ static struct clk gpio5_ick = {
2493 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2612 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2494 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2613 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2495 .flags = CLOCK_IN_OMAP343X, 2614 .flags = CLOCK_IN_OMAP343X,
2615 .clkdm_name = "per_clkdm",
2496 .recalc = &followparent_recalc, 2616 .recalc = &followparent_recalc,
2497}; 2617};
2498 2618
@@ -2502,6 +2622,7 @@ static struct clk gpio4_ick = {
2502 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2622 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2503 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2623 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2504 .flags = CLOCK_IN_OMAP343X, 2624 .flags = CLOCK_IN_OMAP343X,
2625 .clkdm_name = "per_clkdm",
2505 .recalc = &followparent_recalc, 2626 .recalc = &followparent_recalc,
2506}; 2627};
2507 2628
@@ -2511,6 +2632,7 @@ static struct clk gpio3_ick = {
2511 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2632 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2512 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2633 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2513 .flags = CLOCK_IN_OMAP343X, 2634 .flags = CLOCK_IN_OMAP343X,
2635 .clkdm_name = "per_clkdm",
2514 .recalc = &followparent_recalc, 2636 .recalc = &followparent_recalc,
2515}; 2637};
2516 2638
@@ -2520,6 +2642,7 @@ static struct clk gpio2_ick = {
2520 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2642 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2521 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2643 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2522 .flags = CLOCK_IN_OMAP343X, 2644 .flags = CLOCK_IN_OMAP343X,
2645 .clkdm_name = "per_clkdm",
2523 .recalc = &followparent_recalc, 2646 .recalc = &followparent_recalc,
2524}; 2647};
2525 2648
@@ -2529,6 +2652,7 @@ static struct clk wdt3_ick = {
2529 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2652 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2530 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2653 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2531 .flags = CLOCK_IN_OMAP343X, 2654 .flags = CLOCK_IN_OMAP343X,
2655 .clkdm_name = "per_clkdm",
2532 .recalc = &followparent_recalc, 2656 .recalc = &followparent_recalc,
2533}; 2657};
2534 2658
@@ -2538,6 +2662,7 @@ static struct clk uart3_ick = {
2538 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2662 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2539 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2663 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2540 .flags = CLOCK_IN_OMAP343X, 2664 .flags = CLOCK_IN_OMAP343X,
2665 .clkdm_name = "per_clkdm",
2541 .recalc = &followparent_recalc, 2666 .recalc = &followparent_recalc,
2542}; 2667};
2543 2668
@@ -2547,6 +2672,7 @@ static struct clk gpt9_ick = {
2547 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2672 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2548 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2673 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2549 .flags = CLOCK_IN_OMAP343X, 2674 .flags = CLOCK_IN_OMAP343X,
2675 .clkdm_name = "per_clkdm",
2550 .recalc = &followparent_recalc, 2676 .recalc = &followparent_recalc,
2551}; 2677};
2552 2678
@@ -2556,6 +2682,7 @@ static struct clk gpt8_ick = {
2556 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2682 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2557 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2683 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2558 .flags = CLOCK_IN_OMAP343X, 2684 .flags = CLOCK_IN_OMAP343X,
2685 .clkdm_name = "per_clkdm",
2559 .recalc = &followparent_recalc, 2686 .recalc = &followparent_recalc,
2560}; 2687};
2561 2688
@@ -2565,6 +2692,7 @@ static struct clk gpt7_ick = {
2565 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2692 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2566 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2693 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2567 .flags = CLOCK_IN_OMAP343X, 2694 .flags = CLOCK_IN_OMAP343X,
2695 .clkdm_name = "per_clkdm",
2568 .recalc = &followparent_recalc, 2696 .recalc = &followparent_recalc,
2569}; 2697};
2570 2698
@@ -2574,6 +2702,7 @@ static struct clk gpt6_ick = {
2574 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2702 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2575 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2703 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2576 .flags = CLOCK_IN_OMAP343X, 2704 .flags = CLOCK_IN_OMAP343X,
2705 .clkdm_name = "per_clkdm",
2577 .recalc = &followparent_recalc, 2706 .recalc = &followparent_recalc,
2578}; 2707};
2579 2708
@@ -2583,6 +2712,7 @@ static struct clk gpt5_ick = {
2583 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2712 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2584 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2713 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2585 .flags = CLOCK_IN_OMAP343X, 2714 .flags = CLOCK_IN_OMAP343X,
2715 .clkdm_name = "per_clkdm",
2586 .recalc = &followparent_recalc, 2716 .recalc = &followparent_recalc,
2587}; 2717};
2588 2718
@@ -2592,6 +2722,7 @@ static struct clk gpt4_ick = {
2592 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2722 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2593 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2723 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2594 .flags = CLOCK_IN_OMAP343X, 2724 .flags = CLOCK_IN_OMAP343X,
2725 .clkdm_name = "per_clkdm",
2595 .recalc = &followparent_recalc, 2726 .recalc = &followparent_recalc,
2596}; 2727};
2597 2728
@@ -2601,6 +2732,7 @@ static struct clk gpt3_ick = {
2601 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2732 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2602 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2733 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2603 .flags = CLOCK_IN_OMAP343X, 2734 .flags = CLOCK_IN_OMAP343X,
2735 .clkdm_name = "per_clkdm",
2604 .recalc = &followparent_recalc, 2736 .recalc = &followparent_recalc,
2605}; 2737};
2606 2738
@@ -2610,6 +2742,7 @@ static struct clk gpt2_ick = {
2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2742 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2611 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2743 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2612 .flags = CLOCK_IN_OMAP343X, 2744 .flags = CLOCK_IN_OMAP343X,
2745 .clkdm_name = "per_clkdm",
2613 .recalc = &followparent_recalc, 2746 .recalc = &followparent_recalc,
2614}; 2747};
2615 2748
@@ -2620,6 +2753,7 @@ static struct clk mcbsp2_ick = {
2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2753 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2621 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2754 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2622 .flags = CLOCK_IN_OMAP343X, 2755 .flags = CLOCK_IN_OMAP343X,
2756 .clkdm_name = "per_clkdm",
2623 .recalc = &followparent_recalc, 2757 .recalc = &followparent_recalc,
2624}; 2758};
2625 2759
@@ -2630,6 +2764,7 @@ static struct clk mcbsp3_ick = {
2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2764 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2631 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2765 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2632 .flags = CLOCK_IN_OMAP343X, 2766 .flags = CLOCK_IN_OMAP343X,
2767 .clkdm_name = "per_clkdm",
2633 .recalc = &followparent_recalc, 2768 .recalc = &followparent_recalc,
2634}; 2769};
2635 2770
@@ -2640,12 +2775,13 @@ static struct clk mcbsp4_ick = {
2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2775 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2641 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2776 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2642 .flags = CLOCK_IN_OMAP343X, 2777 .flags = CLOCK_IN_OMAP343X,
2778 .clkdm_name = "per_clkdm",
2643 .recalc = &followparent_recalc, 2779 .recalc = &followparent_recalc,
2644}; 2780};
2645 2781
2646static const struct clksel mcbsp_234_clksel[] = { 2782static const struct clksel mcbsp_234_clksel[] = {
2647 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, 2783 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2648 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, 2784 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2649 { .parent = NULL } 2785 { .parent = NULL }
2650}; 2786};
2651 2787
@@ -2659,6 +2795,7 @@ static struct clk mcbsp2_fck = {
2659 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, 2795 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2660 .clksel = mcbsp_234_clksel, 2796 .clksel = mcbsp_234_clksel,
2661 .flags = CLOCK_IN_OMAP343X, 2797 .flags = CLOCK_IN_OMAP343X,
2798 .clkdm_name = "per_clkdm",
2662 .recalc = &omap2_clksel_recalc, 2799 .recalc = &omap2_clksel_recalc,
2663}; 2800};
2664 2801
@@ -2672,6 +2809,7 @@ static struct clk mcbsp3_fck = {
2672 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, 2809 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2673 .clksel = mcbsp_234_clksel, 2810 .clksel = mcbsp_234_clksel,
2674 .flags = CLOCK_IN_OMAP343X, 2811 .flags = CLOCK_IN_OMAP343X,
2812 .clkdm_name = "per_clkdm",
2675 .recalc = &omap2_clksel_recalc, 2813 .recalc = &omap2_clksel_recalc,
2676}; 2814};
2677 2815
@@ -2685,6 +2823,7 @@ static struct clk mcbsp4_fck = {
2685 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, 2823 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2686 .clksel = mcbsp_234_clksel, 2824 .clksel = mcbsp_234_clksel,
2687 .flags = CLOCK_IN_OMAP343X, 2825 .flags = CLOCK_IN_OMAP343X,
2826 .clkdm_name = "per_clkdm",
2688 .recalc = &omap2_clksel_recalc, 2827 .recalc = &omap2_clksel_recalc,
2689}; 2828};
2690 2829
@@ -2732,6 +2871,7 @@ static struct clk emu_src_ck = {
2732 .clksel_mask = OMAP3430_MUX_CTRL_MASK, 2871 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2733 .clksel = emu_src_clksel, 2872 .clksel = emu_src_clksel,
2734 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2873 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2874 .clkdm_name = "emu_clkdm",
2735 .recalc = &omap2_clksel_recalc, 2875 .recalc = &omap2_clksel_recalc,
2736}; 2876};
2737 2877
@@ -2755,6 +2895,7 @@ static struct clk pclk_fck = {
2755 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, 2895 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2756 .clksel = pclk_emu_clksel, 2896 .clksel = pclk_emu_clksel,
2757 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2897 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2898 .clkdm_name = "emu_clkdm",
2758 .recalc = &omap2_clksel_recalc, 2899 .recalc = &omap2_clksel_recalc,
2759}; 2900};
2760 2901
@@ -2777,6 +2918,7 @@ static struct clk pclkx2_fck = {
2777 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, 2918 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2778 .clksel = pclkx2_emu_clksel, 2919 .clksel = pclkx2_emu_clksel,
2779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2920 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2921 .clkdm_name = "emu_clkdm",
2780 .recalc = &omap2_clksel_recalc, 2922 .recalc = &omap2_clksel_recalc,
2781}; 2923};
2782 2924
@@ -2792,6 +2934,7 @@ static struct clk atclk_fck = {
2792 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, 2934 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2793 .clksel = atclk_emu_clksel, 2935 .clksel = atclk_emu_clksel,
2794 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2936 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2937 .clkdm_name = "emu_clkdm",
2795 .recalc = &omap2_clksel_recalc, 2938 .recalc = &omap2_clksel_recalc,
2796}; 2939};
2797 2940
@@ -2802,6 +2945,7 @@ static struct clk traceclk_src_fck = {
2802 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, 2945 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2803 .clksel = emu_src_clksel, 2946 .clksel = emu_src_clksel,
2804 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2947 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2948 .clkdm_name = "emu_clkdm",
2805 .recalc = &omap2_clksel_recalc, 2949 .recalc = &omap2_clksel_recalc,
2806}; 2950};
2807 2951
@@ -2824,6 +2968,7 @@ static struct clk traceclk_fck = {
2824 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, 2968 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2825 .clksel = traceclk_clksel, 2969 .clksel = traceclk_clksel,
2826 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 2970 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2971 .clkdm_name = "emu_clkdm",
2827 .recalc = &omap2_clksel_recalc, 2972 .recalc = &omap2_clksel_recalc,
2828}; 2973};
2829 2974
@@ -2853,11 +2998,13 @@ static struct clk sr_l4_ick = {
2853 .name = "sr_l4_ick", 2998 .name = "sr_l4_ick",
2854 .parent = &l4_ick, 2999 .parent = &l4_ick,
2855 .flags = CLOCK_IN_OMAP343X, 3000 .flags = CLOCK_IN_OMAP343X,
3001 .clkdm_name = "core_l4_clkdm",
2856 .recalc = &followparent_recalc, 3002 .recalc = &followparent_recalc,
2857}; 3003};
2858 3004
2859/* SECURE_32K_FCK clocks */ 3005/* SECURE_32K_FCK clocks */
2860 3006
3007/* XXX This clock no longer exists in 3430 TRM rev F */
2861static struct clk gpt12_fck = { 3008static struct clk gpt12_fck = {
2862 .name = "gpt12_fck", 3009 .name = "gpt12_fck",
2863 .parent = &secure_32k_fck, 3010 .parent = &secure_32k_fck,
@@ -2933,6 +3080,7 @@ static struct clk *onchip_34xx_clks[] __initdata = {
2933 &l3_ick, 3080 &l3_ick,
2934 &l4_ick, 3081 &l4_ick,
2935 &rm_ick, 3082 &rm_ick,
3083 &gfx_l3_ck,
2936 &gfx_l3_fck, 3084 &gfx_l3_fck,
2937 &gfx_l3_ick, 3085 &gfx_l3_ick,
2938 &gfx_cg1_ck, 3086 &gfx_cg1_ck,
@@ -3014,12 +3162,10 @@ static struct clk *onchip_34xx_clks[] __initdata = {
3014 &dss2_alwon_fck, 3162 &dss2_alwon_fck,
3015 &dss_ick, 3163 &dss_ick,
3016 &cam_mclk, 3164 &cam_mclk,
3017 &cam_l3_ick, 3165 &cam_ick,
3018 &cam_l4_ick,
3019 &usbhost_120m_fck, 3166 &usbhost_120m_fck,
3020 &usbhost_48m_fck, 3167 &usbhost_48m_fck,
3021 &usbhost_l3_ick, 3168 &usbhost_ick,
3022 &usbhost_l4_ick,
3023 &usbhost_sar_fck, 3169 &usbhost_sar_fck,
3024 &usim_fck, 3170 &usim_fck,
3025 &gpt1_fck, 3171 &gpt1_fck,
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
new file mode 100644
index 000000000000..4c3ce9cfd948
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -0,0 +1,623 @@
1/*
2 * OMAP2/3 clockdomain framework functions
3 *
4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley and Jouni Högander
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN
14# define DEBUG
15#endif
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/list.h>
21#include <linux/errno.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/limits.h>
25
26#include <linux/io.h>
27
28#include <linux/bitops.h>
29
30#include <mach/clock.h>
31
32#include "prm.h"
33#include "prm-regbits-24xx.h"
34#include "cm.h"
35
36#include <mach/powerdomain.h>
37#include <mach/clockdomain.h>
38
39/* clkdm_list contains all registered struct clockdomains */
40static LIST_HEAD(clkdm_list);
41
42/* clkdm_mutex protects clkdm_list add and del ops */
43static DEFINE_MUTEX(clkdm_mutex);
44
45/* array of powerdomain deps to be added/removed when clkdm in hwsup mode */
46static struct clkdm_pwrdm_autodep *autodeps;
47
48
49/* Private functions */
50
51/*
52 * _autodep_lookup - resolve autodep pwrdm names to pwrdm pointers; store
53 * @autodep: struct clkdm_pwrdm_autodep * to resolve
54 *
55 * Resolve autodep powerdomain names to powerdomain pointers via
56 * pwrdm_lookup() and store the pointers in the autodep structure. An
57 * "autodep" is a powerdomain sleep/wakeup dependency that is
58 * automatically added and removed whenever clocks in the associated
59 * clockdomain are enabled or disabled (respectively) when the
60 * clockdomain is in hardware-supervised mode. Meant to be called
61 * once at clockdomain layer initialization, since these should remain
62 * fixed for a particular architecture. No return value.
63 */
64static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
65{
66 struct powerdomain *pwrdm;
67
68 if (!autodep)
69 return;
70
71 if (!omap_chip_is(autodep->omap_chip))
72 return;
73
74 pwrdm = pwrdm_lookup(autodep->pwrdm_name);
75 if (!pwrdm) {
76 pr_debug("clockdomain: _autodep_lookup: powerdomain %s "
77 "does not exist\n", autodep->pwrdm_name);
78 WARN_ON(1);
79 return;
80 }
81 autodep->pwrdm = pwrdm;
82
83 return;
84}
85
86/*
87 * _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
88 * @clkdm: struct clockdomain *
89 *
90 * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
91 * in hardware-supervised mode. Meant to be called from clock framework
92 * when a clock inside clockdomain 'clkdm' is enabled. No return value.
93 */
94static void _clkdm_add_autodeps(struct clockdomain *clkdm)
95{
96 struct clkdm_pwrdm_autodep *autodep;
97
98 for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
99 if (!autodep->pwrdm)
100 continue;
101
102 pr_debug("clockdomain: adding %s sleepdep/wkdep for "
103 "pwrdm %s\n", autodep->pwrdm_name,
104 clkdm->pwrdm->name);
105
106 pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm);
107 pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm);
108 }
109}
110
111/*
112 * _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm
113 * @clkdm: struct clockdomain *
114 *
115 * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
116 * in hardware-supervised mode. Meant to be called from clock framework
117 * when a clock inside clockdomain 'clkdm' is disabled. No return value.
118 */
119static void _clkdm_del_autodeps(struct clockdomain *clkdm)
120{
121 struct clkdm_pwrdm_autodep *autodep;
122
123 for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
124 if (!autodep->pwrdm)
125 continue;
126
127 pr_debug("clockdomain: removing %s sleepdep/wkdep for "
128 "pwrdm %s\n", autodep->pwrdm_name,
129 clkdm->pwrdm->name);
130
131 pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm);
132 pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm);
133 }
134}
135
136
137static struct clockdomain *_clkdm_lookup(const char *name)
138{
139 struct clockdomain *clkdm, *temp_clkdm;
140
141 if (!name)
142 return NULL;
143
144 clkdm = NULL;
145
146 list_for_each_entry(temp_clkdm, &clkdm_list, node) {
147 if (!strcmp(name, temp_clkdm->name)) {
148 clkdm = temp_clkdm;
149 break;
150 }
151 }
152
153 return clkdm;
154}
155
156
157/* Public functions */
158
159/**
160 * clkdm_init - set up the clockdomain layer
161 * @clkdms: optional pointer to an array of clockdomains to register
162 * @init_autodeps: optional pointer to an array of autodeps to register
163 *
164 * Set up internal state. If a pointer to an array of clockdomains
165 * was supplied, loop through the list of clockdomains, register all
166 * that are available on the current platform. Similarly, if a
167 * pointer to an array of clockdomain-powerdomain autodependencies was
168 * provided, register those. No return value.
169 */
170void clkdm_init(struct clockdomain **clkdms,
171 struct clkdm_pwrdm_autodep *init_autodeps)
172{
173 struct clockdomain **c = NULL;
174 struct clkdm_pwrdm_autodep *autodep = NULL;
175
176 if (clkdms)
177 for (c = clkdms; *c; c++)
178 clkdm_register(*c);
179
180 autodeps = init_autodeps;
181 if (autodeps)
182 for (autodep = autodeps; autodep->pwrdm_name; autodep++)
183 _autodep_lookup(autodep);
184}
185
186/**
187 * clkdm_register - register a clockdomain
188 * @clkdm: struct clockdomain * to register
189 *
190 * Adds a clockdomain to the internal clockdomain list.
191 * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
192 * already registered by the provided name, or 0 upon success.
193 */
194int clkdm_register(struct clockdomain *clkdm)
195{
196 int ret = -EINVAL;
197 struct powerdomain *pwrdm;
198
199 if (!clkdm || !clkdm->name)
200 return -EINVAL;
201
202 if (!omap_chip_is(clkdm->omap_chip))
203 return -EINVAL;
204
205 pwrdm = pwrdm_lookup(clkdm->pwrdm_name);
206 if (!pwrdm) {
207 pr_debug("clockdomain: clkdm_register %s: powerdomain %s "
208 "does not exist\n", clkdm->name, clkdm->pwrdm_name);
209 return -EINVAL;
210 }
211 clkdm->pwrdm = pwrdm;
212
213 mutex_lock(&clkdm_mutex);
214 /* Verify that the clockdomain is not already registered */
215 if (_clkdm_lookup(clkdm->name)) {
216 ret = -EEXIST;
217 goto cr_unlock;
218 };
219
220 list_add(&clkdm->node, &clkdm_list);
221
222 pwrdm_add_clkdm(pwrdm, clkdm);
223
224 pr_debug("clockdomain: registered %s\n", clkdm->name);
225 ret = 0;
226
227cr_unlock:
228 mutex_unlock(&clkdm_mutex);
229
230 return ret;
231}
232
233/**
234 * clkdm_unregister - unregister a clockdomain
235 * @clkdm: struct clockdomain * to unregister
236 *
237 * Removes a clockdomain from the internal clockdomain list. Returns
238 * -EINVAL if clkdm argument is NULL.
239 */
240int clkdm_unregister(struct clockdomain *clkdm)
241{
242 if (!clkdm)
243 return -EINVAL;
244
245 pwrdm_del_clkdm(clkdm->pwrdm, clkdm);
246
247 mutex_lock(&clkdm_mutex);
248 list_del(&clkdm->node);
249 mutex_unlock(&clkdm_mutex);
250
251 pr_debug("clockdomain: unregistered %s\n", clkdm->name);
252
253 return 0;
254}
255
256/**
257 * clkdm_lookup - look up a clockdomain by name, return a pointer
258 * @name: name of clockdomain
259 *
260 * Find a registered clockdomain by its name. Returns a pointer to the
261 * struct clockdomain if found, or NULL otherwise.
262 */
263struct clockdomain *clkdm_lookup(const char *name)
264{
265 struct clockdomain *clkdm, *temp_clkdm;
266
267 if (!name)
268 return NULL;
269
270 clkdm = NULL;
271
272 mutex_lock(&clkdm_mutex);
273 list_for_each_entry(temp_clkdm, &clkdm_list, node) {
274 if (!strcmp(name, temp_clkdm->name)) {
275 clkdm = temp_clkdm;
276 break;
277 }
278 }
279 mutex_unlock(&clkdm_mutex);
280
281 return clkdm;
282}
283
284/**
285 * clkdm_for_each - call function on each registered clockdomain
286 * @fn: callback function *
287 *
288 * Call the supplied function for each registered clockdomain.
289 * The callback function can return anything but 0 to bail
290 * out early from the iterator. The callback function is called with
291 * the clkdm_mutex held, so no clockdomain structure manipulation
292 * functions should be called from the callback, although hardware
293 * clockdomain control functions are fine. Returns the last return
294 * value of the callback function, which should be 0 for success or
295 * anything else to indicate failure; or -EINVAL if the function pointer
296 * is null.
297 */
298int clkdm_for_each(int (*fn)(struct clockdomain *clkdm))
299{
300 struct clockdomain *clkdm;
301 int ret = 0;
302
303 if (!fn)
304 return -EINVAL;
305
306 mutex_lock(&clkdm_mutex);
307 list_for_each_entry(clkdm, &clkdm_list, node) {
308 ret = (*fn)(clkdm);
309 if (ret)
310 break;
311 }
312 mutex_unlock(&clkdm_mutex);
313
314 return ret;
315}
316
317
318/**
319 * clkdm_get_pwrdm - return a ptr to the pwrdm that this clkdm resides in
320 * @clkdm: struct clockdomain *
321 *
322 * Return a pointer to the struct powerdomain that the specified clockdomain
323 * 'clkdm' exists in, or returns NULL if clkdm argument is NULL.
324 */
325struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
326{
327 if (!clkdm)
328 return NULL;
329
330 return clkdm->pwrdm;
331}
332
333
334/* Hardware clockdomain control */
335
336/**
337 * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode
338 * @clk: struct clk * of a clockdomain
339 *
340 * Return the clockdomain's current state transition mode from the
341 * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if clk
342 * is NULL or the current mode upon success.
343 */
344static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
345{
346 u32 v;
347
348 if (!clkdm)
349 return -EINVAL;
350
351 v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
352 v &= clkdm->clktrctrl_mask;
353 v >>= __ffs(clkdm->clktrctrl_mask);
354
355 return v;
356}
357
358/**
359 * omap2_clkdm_sleep - force clockdomain sleep transition
360 * @clkdm: struct clockdomain *
361 *
362 * Instruct the CM to force a sleep transition on the specified
363 * clockdomain 'clkdm'. Returns -EINVAL if clk is NULL or if
364 * clockdomain does not support software-initiated sleep; 0 upon
365 * success.
366 */
367int omap2_clkdm_sleep(struct clockdomain *clkdm)
368{
369 if (!clkdm)
370 return -EINVAL;
371
372 if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
373 pr_debug("clockdomain: %s does not support forcing "
374 "sleep via software\n", clkdm->name);
375 return -EINVAL;
376 }
377
378 pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
379
380 if (cpu_is_omap24xx()) {
381
382 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
383 clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
384
385 } else if (cpu_is_omap34xx()) {
386
387 u32 v = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
388 __ffs(clkdm->clktrctrl_mask));
389
390 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
391 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
392
393 } else {
394 BUG();
395 };
396
397 return 0;
398}
399
400/**
401 * omap2_clkdm_wakeup - force clockdomain wakeup transition
402 * @clkdm: struct clockdomain *
403 *
404 * Instruct the CM to force a wakeup transition on the specified
405 * clockdomain 'clkdm'. Returns -EINVAL if clkdm is NULL or if the
406 * clockdomain does not support software-controlled wakeup; 0 upon
407 * success.
408 */
409int omap2_clkdm_wakeup(struct clockdomain *clkdm)
410{
411 if (!clkdm)
412 return -EINVAL;
413
414 if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
415 pr_debug("clockdomain: %s does not support forcing "
416 "wakeup via software\n", clkdm->name);
417 return -EINVAL;
418 }
419
420 pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
421
422 if (cpu_is_omap24xx()) {
423
424 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
425 clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
426
427 } else if (cpu_is_omap34xx()) {
428
429 u32 v = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
430 __ffs(clkdm->clktrctrl_mask));
431
432 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
433 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
434
435 } else {
436 BUG();
437 };
438
439 return 0;
440}
441
442/**
443 * omap2_clkdm_allow_idle - enable hwsup idle transitions for clkdm
444 * @clkdm: struct clockdomain *
445 *
446 * Allow the hardware to automatically switch the clockdomain into
447 * active or idle states, as needed by downstream clocks. If the
448 * clockdomain has any downstream clocks enabled in the clock
449 * framework, wkdep/sleepdep autodependencies are added; this is so
450 * device drivers can read and write to the device. No return value.
451 */
452void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
453{
454 u32 v;
455
456 if (!clkdm)
457 return;
458
459 if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
460 pr_debug("clock: automatic idle transitions cannot be enabled "
461 "on clockdomain %s\n", clkdm->name);
462 return;
463 }
464
465 pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
466 clkdm->name);
467
468 if (atomic_read(&clkdm->usecount) > 0)
469 _clkdm_add_autodeps(clkdm);
470
471 if (cpu_is_omap24xx())
472 v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
473 else if (cpu_is_omap34xx())
474 v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
475 else
476 BUG();
477
478
479 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
480 v << __ffs(clkdm->clktrctrl_mask),
481 clkdm->pwrdm->prcm_offs,
482 CM_CLKSTCTRL);
483}
484
485/**
486 * omap2_clkdm_deny_idle - disable hwsup idle transitions for clkdm
487 * @clkdm: struct clockdomain *
488 *
489 * Prevent the hardware from automatically switching the clockdomain
490 * into inactive or idle states. If the clockdomain has downstream
491 * clocks enabled in the clock framework, wkdep/sleepdep
492 * autodependencies are removed. No return value.
493 */
494void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
495{
496 u32 v;
497
498 if (!clkdm)
499 return;
500
501 if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
502 pr_debug("clockdomain: automatic idle transitions cannot be "
503 "disabled on %s\n", clkdm->name);
504 return;
505 }
506
507 pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
508 clkdm->name);
509
510 if (cpu_is_omap24xx())
511 v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
512 else if (cpu_is_omap34xx())
513 v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
514 else
515 BUG();
516
517 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
518 v << __ffs(clkdm->clktrctrl_mask),
519 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
520
521 if (atomic_read(&clkdm->usecount) > 0)
522 _clkdm_del_autodeps(clkdm);
523}
524
525
526/* Clockdomain-to-clock framework interface code */
527
528/**
529 * omap2_clkdm_clk_enable - add an enabled downstream clock to this clkdm
530 * @clkdm: struct clockdomain *
531 * @clk: struct clk * of the enabled downstream clock
532 *
533 * Increment the usecount of this clockdomain 'clkdm' and ensure that
534 * it is awake. Intended to be called by clk_enable() code. If the
535 * clockdomain is in software-supervised idle mode, force the
536 * clockdomain to wake. If the clockdomain is in hardware-supervised
537 * idle mode, add clkdm-pwrdm autodependencies, to ensure that devices
538 * in the clockdomain can be read from/written to by on-chip processors.
539 * Returns -EINVAL if passed null pointers; returns 0 upon success or
540 * if the clockdomain is in hwsup idle mode.
541 */
542int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
543{
544 int v;
545
546 /*
547 * XXX Rewrite this code to maintain a list of enabled
548 * downstream clocks for debugging purposes?
549 */
550
551 if (!clkdm || !clk)
552 return -EINVAL;
553
554 if (atomic_inc_return(&clkdm->usecount) > 1)
555 return 0;
556
557 /* Clockdomain now has one enabled downstream clock */
558
559 pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
560 clk->name);
561
562 v = omap2_clkdm_clktrctrl_read(clkdm);
563
564 if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
565 (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
566 _clkdm_add_autodeps(clkdm);
567 else
568 omap2_clkdm_wakeup(clkdm);
569
570 return 0;
571}
572
573/**
574 * omap2_clkdm_clk_disable - remove an enabled downstream clock from this clkdm
575 * @clkdm: struct clockdomain *
576 * @clk: struct clk * of the disabled downstream clock
577 *
578 * Decrement the usecount of this clockdomain 'clkdm'. Intended to be
579 * called by clk_disable() code. If the usecount goes to 0, put the
580 * clockdomain to sleep (software-supervised mode) or remove the
581 * clkdm-pwrdm autodependencies (hardware-supervised mode). Returns
582 * -EINVAL if passed null pointers; -ERANGE if the clkdm usecount
583 * underflows and debugging is enabled; or returns 0 upon success or
584 * if the clockdomain is in hwsup idle mode.
585 */
586int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
587{
588 int v;
589
590 /*
591 * XXX Rewrite this code to maintain a list of enabled
592 * downstream clocks for debugging purposes?
593 */
594
595 if (!clkdm || !clk)
596 return -EINVAL;
597
598#ifdef DEBUG
599 if (atomic_read(&clkdm->usecount) == 0) {
600 WARN_ON(1); /* underflow */
601 return -ERANGE;
602 }
603#endif
604
605 if (atomic_dec_return(&clkdm->usecount) > 0)
606 return 0;
607
608 /* All downstream clocks of this clockdomain are now disabled */
609
610 pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
611 clk->name);
612
613 v = omap2_clkdm_clktrctrl_read(clkdm);
614
615 if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
616 (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
617 _clkdm_del_autodeps(clkdm);
618 else
619 omap2_clkdm_sleep(clkdm);
620
621 return 0;
622}
623
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
new file mode 100644
index 000000000000..cd86dcc7b424
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -0,0 +1,305 @@
1/*
2 * OMAP2/3 clockdomains
3 *
4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 */
9
10#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
11#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
12
13#include <mach/clockdomain.h>
14
15/*
16 * OMAP2/3-common clockdomains
17 */
18
19/* This is an implicit clockdomain - it is never defined as such in TRM */
20static struct clockdomain wkup_clkdm = {
21 .name = "wkup_clkdm",
22 .pwrdm_name = "wkup_pwrdm",
23 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
24};
25
26/*
27 * 2420-only clockdomains
28 */
29
30#if defined(CONFIG_ARCH_OMAP2420)
31
32static struct clockdomain mpu_2420_clkdm = {
33 .name = "mpu_clkdm",
34 .pwrdm_name = "mpu_pwrdm",
35 .flags = CLKDM_CAN_HWSUP,
36 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
37 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
38};
39
40static struct clockdomain iva1_2420_clkdm = {
41 .name = "iva1_clkdm",
42 .pwrdm_name = "dsp_pwrdm",
43 .flags = CLKDM_CAN_HWSUP_SWSUP,
44 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
45 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
46};
47
48#endif /* CONFIG_ARCH_OMAP2420 */
49
50
51/*
52 * 2430-only clockdomains
53 */
54
55#if defined(CONFIG_ARCH_OMAP2430)
56
57static struct clockdomain mpu_2430_clkdm = {
58 .name = "mpu_clkdm",
59 .pwrdm_name = "mpu_pwrdm",
60 .flags = CLKDM_CAN_HWSUP_SWSUP,
61 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
63};
64
65static struct clockdomain mdm_clkdm = {
66 .name = "mdm_clkdm",
67 .pwrdm_name = "mdm_pwrdm",
68 .flags = CLKDM_CAN_HWSUP_SWSUP,
69 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
71};
72
73#endif /* CONFIG_ARCH_OMAP2430 */
74
75
76/*
77 * 24XX-only clockdomains
78 */
79
80#if defined(CONFIG_ARCH_OMAP24XX)
81
82static struct clockdomain dsp_clkdm = {
83 .name = "dsp_clkdm",
84 .pwrdm_name = "dsp_pwrdm",
85 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
88};
89
90static struct clockdomain gfx_24xx_clkdm = {
91 .name = "gfx_clkdm",
92 .pwrdm_name = "gfx_pwrdm",
93 .flags = CLKDM_CAN_HWSUP_SWSUP,
94 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
96};
97
98static struct clockdomain core_l3_24xx_clkdm = {
99 .name = "core_l3_clkdm",
100 .pwrdm_name = "core_pwrdm",
101 .flags = CLKDM_CAN_HWSUP,
102 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
104};
105
106static struct clockdomain core_l4_24xx_clkdm = {
107 .name = "core_l4_clkdm",
108 .pwrdm_name = "core_pwrdm",
109 .flags = CLKDM_CAN_HWSUP,
110 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
112};
113
114static struct clockdomain dss_24xx_clkdm = {
115 .name = "dss_clkdm",
116 .pwrdm_name = "core_pwrdm",
117 .flags = CLKDM_CAN_HWSUP,
118 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
120};
121
122#endif /* CONFIG_ARCH_OMAP24XX */
123
124
125/*
126 * 34xx clockdomains
127 */
128
129#if defined(CONFIG_ARCH_OMAP34XX)
130
131static struct clockdomain mpu_34xx_clkdm = {
132 .name = "mpu_clkdm",
133 .pwrdm_name = "mpu_pwrdm",
134 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
135 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
137};
138
139static struct clockdomain neon_clkdm = {
140 .name = "neon_clkdm",
141 .pwrdm_name = "neon_pwrdm",
142 .flags = CLKDM_CAN_HWSUP_SWSUP,
143 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
144 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
145};
146
147static struct clockdomain iva2_clkdm = {
148 .name = "iva2_clkdm",
149 .pwrdm_name = "iva2_pwrdm",
150 .flags = CLKDM_CAN_HWSUP_SWSUP,
151 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
153};
154
155static struct clockdomain gfx_3430es1_clkdm = {
156 .name = "gfx_clkdm",
157 .pwrdm_name = "gfx_pwrdm",
158 .flags = CLKDM_CAN_HWSUP_SWSUP,
159 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
161};
162
163static struct clockdomain sgx_clkdm = {
164 .name = "sgx_clkdm",
165 .pwrdm_name = "sgx_pwrdm",
166 .flags = CLKDM_CAN_HWSUP_SWSUP,
167 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
169};
170
171/*
172 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
173 * then that information was removed from the 34xx ES2+ TRM. It is
174 * unclear whether the core is still there, but the clockdomain logic
175 * is there, and must be programmed to an appropriate state if the
176 * CORE clockdomain is to become inactive.
177 */
178static struct clockdomain d2d_clkdm = {
179 .name = "d2d_clkdm",
180 .pwrdm_name = "core_pwrdm",
181 .flags = CLKDM_CAN_HWSUP,
182 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
184};
185
186static struct clockdomain core_l3_34xx_clkdm = {
187 .name = "core_l3_clkdm",
188 .pwrdm_name = "core_pwrdm",
189 .flags = CLKDM_CAN_HWSUP,
190 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
192};
193
194static struct clockdomain core_l4_34xx_clkdm = {
195 .name = "core_l4_clkdm",
196 .pwrdm_name = "core_pwrdm",
197 .flags = CLKDM_CAN_HWSUP,
198 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
199 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
200};
201
202static struct clockdomain dss_34xx_clkdm = {
203 .name = "dss_clkdm",
204 .pwrdm_name = "dss_pwrdm",
205 .flags = CLKDM_CAN_HWSUP_SWSUP,
206 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
208};
209
210static struct clockdomain cam_clkdm = {
211 .name = "cam_clkdm",
212 .pwrdm_name = "cam_pwrdm",
213 .flags = CLKDM_CAN_HWSUP_SWSUP,
214 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
216};
217
218static struct clockdomain usbhost_clkdm = {
219 .name = "usbhost_clkdm",
220 .pwrdm_name = "usbhost_pwrdm",
221 .flags = CLKDM_CAN_HWSUP_SWSUP,
222 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
224};
225
226static struct clockdomain per_clkdm = {
227 .name = "per_clkdm",
228 .pwrdm_name = "per_pwrdm",
229 .flags = CLKDM_CAN_HWSUP_SWSUP,
230 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
232};
233
234static struct clockdomain emu_clkdm = {
235 .name = "emu_clkdm",
236 .pwrdm_name = "emu_pwrdm",
237 .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
238 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
240};
241
242#endif /* CONFIG_ARCH_OMAP34XX */
243
244/*
245 * Clockdomain-powerdomain hwsup dependencies (34XX only)
246 */
247
248static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
249 {
250 .pwrdm_name = "mpu_pwrdm",
251 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
252 },
253 {
254 .pwrdm_name = "iva2_pwrdm",
255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
256 },
257 { NULL }
258};
259
260/*
261 *
262 */
263
264static struct clockdomain *clockdomains_omap[] = {
265
266 &wkup_clkdm,
267
268#ifdef CONFIG_ARCH_OMAP2420
269 &mpu_2420_clkdm,
270 &iva1_2420_clkdm,
271#endif
272
273#ifdef CONFIG_ARCH_OMAP2430
274 &mpu_2430_clkdm,
275 &mdm_clkdm,
276#endif
277
278#ifdef CONFIG_ARCH_OMAP24XX
279 &dsp_clkdm,
280 &gfx_24xx_clkdm,
281 &core_l3_24xx_clkdm,
282 &core_l4_24xx_clkdm,
283 &dss_24xx_clkdm,
284#endif
285
286#ifdef CONFIG_ARCH_OMAP34XX
287 &mpu_34xx_clkdm,
288 &neon_clkdm,
289 &iva2_clkdm,
290 &gfx_3430es1_clkdm,
291 &sgx_clkdm,
292 &d2d_clkdm,
293 &core_l3_34xx_clkdm,
294 &core_l4_34xx_clkdm,
295 &dss_34xx_clkdm,
296 &cam_clkdm,
297 &usbhost_clkdm,
298 &per_clkdm,
299 &emu_clkdm,
300#endif
301
302 NULL,
303};
304
305#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 20ac38100678..1098ecfab861 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -63,7 +63,8 @@
63#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) 63#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
64 64
65/* CM_CLKSTCTRL_MPU */ 65/* CM_CLKSTCTRL_MPU */
66#define OMAP24XX_AUTOSTATE_MPU (1 << 0) 66#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
67#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
67 68
68/* CM_FCLKEN1_CORE specific bits*/ 69/* CM_FCLKEN1_CORE specific bits*/
69#define OMAP24XX_EN_TV_SHIFT 2 70#define OMAP24XX_EN_TV_SHIFT 2
@@ -238,9 +239,12 @@
238#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) 239#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
239 240
240/* CM_CLKSTCTRL_CORE */ 241/* CM_CLKSTCTRL_CORE */
241#define OMAP24XX_AUTOSTATE_DSS (1 << 2) 242#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
242#define OMAP24XX_AUTOSTATE_L4 (1 << 1) 243#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
243#define OMAP24XX_AUTOSTATE_L3 (1 << 0) 244#define OMAP24XX_AUTOSTATE_L4_SHIFT 1
245#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
246#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
247#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
244 248
245/* CM_FCLKEN_GFX */ 249/* CM_FCLKEN_GFX */
246#define OMAP24XX_EN_3D_SHIFT 2 250#define OMAP24XX_EN_3D_SHIFT 2
@@ -255,7 +259,8 @@
255/* CM_CLKSEL_GFX specific bits */ 259/* CM_CLKSEL_GFX specific bits */
256 260
257/* CM_CLKSTCTRL_GFX */ 261/* CM_CLKSTCTRL_GFX */
258#define OMAP24XX_AUTOSTATE_GFX (1 << 0) 262#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
263#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
259 264
260/* CM_FCLKEN_WKUP specific bits */ 265/* CM_FCLKEN_WKUP specific bits */
261 266
@@ -367,8 +372,10 @@
367#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) 372#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
368 373
369/* CM_CLKSTCTRL_DSP */ 374/* CM_CLKSTCTRL_DSP */
370#define OMAP2420_AUTOSTATE_IVA (1 << 8) 375#define OMAP2420_AUTOSTATE_IVA_SHIFT 8
371#define OMAP24XX_AUTOSTATE_DSP (1 << 0) 376#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
377#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
378#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
372 379
373/* CM_FCLKEN_MDM */ 380/* CM_FCLKEN_MDM */
374/* 2430 only */ 381/* 2430 only */
@@ -396,6 +403,7 @@
396 403
397/* CM_CLKSTCTRL_MDM */ 404/* CM_CLKSTCTRL_MDM */
398/* 2430 only */ 405/* 2430 only */
399#define OMAP2430_AUTOSTATE_MDM (1 << 0) 406#define OMAP2430_AUTOSTATE_MDM_SHIFT 0
407#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
400 408
401#endif 409#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index ee4c0ca1a708..219f5c8d9659 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -96,7 +96,8 @@
96#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 96#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
97 97
98/* CM_CLKSTST_IVA2 */ 98/* CM_CLKSTST_IVA2 */
99#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) 99#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
100#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
100 101
101/* CM_REVISION specific bits */ 102/* CM_REVISION specific bits */
102 103
@@ -140,7 +141,8 @@
140#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 141#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
141 142
142/* CM_CLKSTST_MPU */ 143/* CM_CLKSTST_MPU */
143#define OMAP3430_CLKACTIVITY_MPU (1 << 0) 144#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
145#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
144 146
145/* CM_FCLKEN1_CORE specific bits */ 147/* CM_FCLKEN1_CORE specific bits */
146 148
@@ -300,9 +302,12 @@
300#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 302#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
301 303
302/* CM_CLKSTST_CORE */ 304/* CM_CLKSTST_CORE */
303#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) 305#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
304#define OMAP3430_CLKACTIVITY_L4 (1 << 1) 306#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
305#define OMAP3430_CLKACTIVITY_L3 (1 << 0) 307#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
308#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
309#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
310#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
306 311
307/* CM_FCLKEN_GFX */ 312/* CM_FCLKEN_GFX */
308#define OMAP3430ES1_EN_3D (1 << 2) 313#define OMAP3430ES1_EN_3D (1 << 2)
@@ -323,7 +328,8 @@
323#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 328#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
324 329
325/* CM_CLKSTST_GFX */ 330/* CM_CLKSTST_GFX */
326#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) 331#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
332#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
327 333
328/* CM_FCLKEN_SGX */ 334/* CM_FCLKEN_SGX */
329#define OMAP3430ES2_EN_SGX_SHIFT 1 335#define OMAP3430ES2_EN_SGX_SHIFT 1
@@ -333,6 +339,14 @@
333#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 339#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
334#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 340#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
335 341
342/* CM_CLKSTCTRL_SGX */
343#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
344#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
345
346/* CM_CLKSTST_SGX */
347#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
348#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
349
336/* CM_FCLKEN_WKUP specific bits */ 350/* CM_FCLKEN_WKUP specific bits */
337#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 351#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
338 352
@@ -498,7 +512,8 @@
498#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 512#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
499 513
500/* CM_CLKSTST_DSS */ 514/* CM_CLKSTST_DSS */
501#define OMAP3430_CLKACTIVITY_DSS (1 << 0) 515#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
516#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
502 517
503/* CM_FCLKEN_CAM specific bits */ 518/* CM_FCLKEN_CAM specific bits */
504 519
@@ -522,7 +537,8 @@
522#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 537#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
523 538
524/* CM_CLKSTST_CAM */ 539/* CM_CLKSTST_CAM */
525#define OMAP3430_CLKACTIVITY_CAM (1 << 0) 540#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
541#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
526 542
527/* CM_FCLKEN_PER specific bits */ 543/* CM_FCLKEN_PER specific bits */
528 544
@@ -598,7 +614,8 @@
598#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 614#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
599 615
600/* CM_CLKSTST_PER */ 616/* CM_CLKSTST_PER */
601#define OMAP3430_CLKACTIVITY_PER (1 << 0) 617#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
618#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
602 619
603/* CM_CLKSEL1_EMU */ 620/* CM_CLKSEL1_EMU */
604#define OMAP3430_DIV_DPLL4_SHIFT 24 621#define OMAP3430_DIV_DPLL4_SHIFT 24
@@ -623,7 +640,8 @@
623#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 640#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
624 641
625/* CM_CLKSTST_EMU */ 642/* CM_CLKSTST_EMU */
626#define OMAP3430_CLKACTIVITY_EMU (1 << 0) 643#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
644#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
627 645
628/* CM_CLKSEL2_EMU specific bits */ 646/* CM_CLKSEL2_EMU specific bits */
629#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 647#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
@@ -673,6 +691,8 @@
673#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 691#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
674#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 692#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
675 693
676 694/* CM_CLKSTST_USBHOST */
695#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
696#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
677 697
678#endif 698#endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 87a44c715aa4..65fdf78c91e1 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -18,7 +18,7 @@
18 18
19#ifndef __ASSEMBLER__ 19#ifndef __ASSEMBLER__
20#define OMAP_CM_REGADDR(module, reg) \ 20#define OMAP_CM_REGADDR(module, reg) \
21 (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) 21 IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
22#else 22#else
23#define OMAP2420_CM_REGADDR(module, reg) \ 23#define OMAP2420_CM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 24 IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2ee954a0bc7c..90af2ac469aa 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -23,50 +23,7 @@
23#include <mach/board.h> 23#include <mach/board.h>
24#include <mach/mux.h> 24#include <mach/mux.h>
25#include <mach/gpio.h> 25#include <mach/gpio.h>
26 26#include <mach/eac.h>
27#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
28
29#define OMAP2_I2C_BASE2 0x48072000
30#define OMAP2_I2C_INT2 57
31
32static struct resource i2c_resources2[] = {
33 {
34 .start = OMAP2_I2C_BASE2,
35 .end = OMAP2_I2C_BASE2 + 0x3f,
36 .flags = IORESOURCE_MEM,
37 },
38 {
39 .start = OMAP2_I2C_INT2,
40 .flags = IORESOURCE_IRQ,
41 },
42};
43
44static struct platform_device omap_i2c_device2 = {
45 .name = "i2c_omap",
46 .id = 2,
47 .num_resources = ARRAY_SIZE(i2c_resources2),
48 .resource = i2c_resources2,
49};
50
51/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
52static void omap_init_i2c(void)
53{
54 /* REVISIT: Second I2C not in use on H4? */
55 if (machine_is_omap_h4())
56 return;
57
58 if (!cpu_is_omap2430()) {
59 omap_cfg_reg(J15_24XX_I2C2_SCL);
60 omap_cfg_reg(H19_24XX_I2C2_SDA);
61 }
62 (void) platform_device_register(&omap_i2c_device2);
63}
64
65#else
66
67static void omap_init_i2c(void) {}
68
69#endif
70 27
71#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 28#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
72#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) 29#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
@@ -104,7 +61,9 @@ static inline void omap_init_mbox(void) { }
104 61
105#if defined(CONFIG_OMAP_STI) 62#if defined(CONFIG_OMAP_STI)
106 63
107#define OMAP2_STI_BASE IO_ADDRESS(0x48068000) 64#if defined(CONFIG_ARCH_OMAP2)
65
66#define OMAP2_STI_BASE 0x48068000
108#define OMAP2_STI_CHANNEL_BASE 0x54000000 67#define OMAP2_STI_CHANNEL_BASE 0x54000000
109#define OMAP2_STI_IRQ 4 68#define OMAP2_STI_IRQ 4
110 69
@@ -124,6 +83,25 @@ static struct resource sti_resources[] = {
124 .flags = IORESOURCE_IRQ, 83 .flags = IORESOURCE_IRQ,
125 } 84 }
126}; 85};
86#elif defined(CONFIG_ARCH_OMAP3)
87
88#define OMAP3_SDTI_BASE 0x54500000
89#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
90
91static struct resource sti_resources[] = {
92 {
93 .start = OMAP3_SDTI_BASE,
94 .end = OMAP3_SDTI_BASE + 0xFFF,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .start = OMAP3_SDTI_CHANNEL_BASE,
99 .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
100 .flags = IORESOURCE_MEM,
101 }
102};
103
104#endif
127 105
128static struct platform_device sti_device = { 106static struct platform_device sti_device = {
129 .name = "sti", 107 .name = "sti",
@@ -140,12 +118,14 @@ static inline void omap_init_sti(void)
140static inline void omap_init_sti(void) {} 118static inline void omap_init_sti(void) {}
141#endif 119#endif
142 120
143#if defined(CONFIG_SPI_OMAP24XX) 121#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
144 122
145#include <mach/mcspi.h> 123#include <mach/mcspi.h>
146 124
147#define OMAP2_MCSPI1_BASE 0x48098000 125#define OMAP2_MCSPI1_BASE 0x48098000
148#define OMAP2_MCSPI2_BASE 0x4809a000 126#define OMAP2_MCSPI2_BASE 0x4809a000
127#define OMAP2_MCSPI3_BASE 0x480b8000
128#define OMAP2_MCSPI4_BASE 0x480ba000
149 129
150static struct omap2_mcspi_platform_config omap2_mcspi1_config = { 130static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
151 .num_cs = 4, 131 .num_cs = 4,
@@ -159,7 +139,7 @@ static struct resource omap2_mcspi1_resources[] = {
159 }, 139 },
160}; 140};
161 141
162struct platform_device omap2_mcspi1 = { 142static struct platform_device omap2_mcspi1 = {
163 .name = "omap2_mcspi", 143 .name = "omap2_mcspi",
164 .id = 1, 144 .id = 1,
165 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), 145 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
@@ -181,7 +161,7 @@ static struct resource omap2_mcspi2_resources[] = {
181 }, 161 },
182}; 162};
183 163
184struct platform_device omap2_mcspi2 = { 164static struct platform_device omap2_mcspi2 = {
185 .name = "omap2_mcspi", 165 .name = "omap2_mcspi",
186 .id = 2, 166 .id = 2,
187 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), 167 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
@@ -191,16 +171,162 @@ struct platform_device omap2_mcspi2 = {
191 }, 171 },
192}; 172};
193 173
174#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
175static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
176 .num_cs = 2,
177};
178
179static struct resource omap2_mcspi3_resources[] = {
180 {
181 .start = OMAP2_MCSPI3_BASE,
182 .end = OMAP2_MCSPI3_BASE + 0xff,
183 .flags = IORESOURCE_MEM,
184 },
185};
186
187static struct platform_device omap2_mcspi3 = {
188 .name = "omap2_mcspi",
189 .id = 3,
190 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
191 .resource = omap2_mcspi3_resources,
192 .dev = {
193 .platform_data = &omap2_mcspi3_config,
194 },
195};
196#endif
197
198#ifdef CONFIG_ARCH_OMAP3
199static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
200 .num_cs = 1,
201};
202
203static struct resource omap2_mcspi4_resources[] = {
204 {
205 .start = OMAP2_MCSPI4_BASE,
206 .end = OMAP2_MCSPI4_BASE + 0xff,
207 .flags = IORESOURCE_MEM,
208 },
209};
210
211static struct platform_device omap2_mcspi4 = {
212 .name = "omap2_mcspi",
213 .id = 4,
214 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
215 .resource = omap2_mcspi4_resources,
216 .dev = {
217 .platform_data = &omap2_mcspi4_config,
218 },
219};
220#endif
221
194static void omap_init_mcspi(void) 222static void omap_init_mcspi(void)
195{ 223{
196 platform_device_register(&omap2_mcspi1); 224 platform_device_register(&omap2_mcspi1);
197 platform_device_register(&omap2_mcspi2); 225 platform_device_register(&omap2_mcspi2);
226#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
227 platform_device_register(&omap2_mcspi3);
228#endif
229#ifdef CONFIG_ARCH_OMAP3
230 platform_device_register(&omap2_mcspi4);
231#endif
198} 232}
199 233
200#else 234#else
201static inline void omap_init_mcspi(void) {} 235static inline void omap_init_mcspi(void) {}
202#endif 236#endif
203 237
238#ifdef CONFIG_SND_OMAP24XX_EAC
239
240#define OMAP2_EAC_BASE 0x48090000
241
242static struct resource omap2_eac_resources[] = {
243 {
244 .start = OMAP2_EAC_BASE,
245 .end = OMAP2_EAC_BASE + 0x109,
246 .flags = IORESOURCE_MEM,
247 },
248};
249
250static struct platform_device omap2_eac_device = {
251 .name = "omap24xx-eac",
252 .id = -1,
253 .num_resources = ARRAY_SIZE(omap2_eac_resources),
254 .resource = omap2_eac_resources,
255 .dev = {
256 .platform_data = NULL,
257 },
258};
259
260void omap_init_eac(struct eac_platform_data *pdata)
261{
262 omap2_eac_device.dev.platform_data = pdata;
263 platform_device_register(&omap2_eac_device);
264}
265
266#else
267void omap_init_eac(struct eac_platform_data *pdata) {}
268#endif
269
270#ifdef CONFIG_OMAP_SHA1_MD5
271static struct resource sha1_md5_resources[] = {
272 {
273 .start = OMAP24XX_SEC_SHA1MD5_BASE,
274 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
275 .flags = IORESOURCE_MEM,
276 },
277 {
278 .start = INT_24XX_SHA1MD5,
279 .flags = IORESOURCE_IRQ,
280 }
281};
282
283static struct platform_device sha1_md5_device = {
284 .name = "OMAP SHA1/MD5",
285 .id = -1,
286 .num_resources = ARRAY_SIZE(sha1_md5_resources),
287 .resource = sha1_md5_resources,
288};
289
290static void omap_init_sha1_md5(void)
291{
292 platform_device_register(&sha1_md5_device);
293}
294#else
295static inline void omap_init_sha1_md5(void) { }
296#endif
297
298#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
299#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
300#define OMAP_HDQ_BASE 0x480B2000
301#endif
302static struct resource omap_hdq_resources[] = {
303 {
304 .start = OMAP_HDQ_BASE,
305 .end = OMAP_HDQ_BASE + 0x1C,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = INT_24XX_HDQ_IRQ,
310 .flags = IORESOURCE_IRQ,
311 },
312};
313static struct platform_device omap_hdq_dev = {
314 .name = "omap_hdq",
315 .id = 0,
316 .dev = {
317 .platform_data = NULL,
318 },
319 .num_resources = ARRAY_SIZE(omap_hdq_resources),
320 .resource = omap_hdq_resources,
321};
322static inline void omap_hdq_init(void)
323{
324 (void) platform_device_register(&omap_hdq_dev);
325}
326#else
327static inline void omap_hdq_init(void) {}
328#endif
329
204/*-------------------------------------------------------------------------*/ 330/*-------------------------------------------------------------------------*/
205 331
206static int __init omap2_init_devices(void) 332static int __init omap2_init_devices(void)
@@ -208,10 +334,11 @@ static int __init omap2_init_devices(void)
208 /* please keep these calls, and their implementations above, 334 /* please keep these calls, and their implementations above,
209 * in alphabetical order so they're easier to sort through. 335 * in alphabetical order so they're easier to sort through.
210 */ 336 */
211 omap_init_i2c();
212 omap_init_mbox(); 337 omap_init_mbox();
213 omap_init_mcspi(); 338 omap_init_mcspi();
339 omap_hdq_init();
214 omap_init_sti(); 340 omap_init_sti();
341 omap_init_sha1_md5();
215 342
216 return 0; 343 return 0;
217} 344}
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index af1081a0b27c..763bdbeaf681 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -9,6 +9,8 @@
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12#undef DEBUG
13
12#include <linux/kernel.h> 14#include <linux/kernel.h>
13#include <linux/init.h> 15#include <linux/init.h>
14#include <linux/err.h> 16#include <linux/err.h>
@@ -16,20 +18,14 @@
16#include <linux/ioport.h> 18#include <linux/ioport.h>
17#include <linux/spinlock.h> 19#include <linux/spinlock.h>
18#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/module.h>
19 22
20#include <asm/mach-types.h> 23#include <asm/mach-types.h>
21#include <mach/gpmc.h> 24#include <mach/gpmc.h>
22 25
23#undef DEBUG 26#include <mach/sdrc.h>
24
25#ifdef CONFIG_ARCH_OMAP2420
26#define GPMC_BASE 0x6800a000
27#endif
28
29#ifdef CONFIG_ARCH_OMAP2430
30#define GPMC_BASE 0x6E000000
31#endif
32 27
28/* GPMC register offsets */
33#define GPMC_REVISION 0x00 29#define GPMC_REVISION 0x00
34#define GPMC_SYSCONFIG 0x10 30#define GPMC_SYSCONFIG 0x10
35#define GPMC_SYSSTATUS 0x14 31#define GPMC_SYSSTATUS 0x14
@@ -51,7 +47,6 @@
51#define GPMC_CS0 0x60 47#define GPMC_CS0 0x60
52#define GPMC_CS_SIZE 0x30 48#define GPMC_CS_SIZE 0x30
53 49
54#define GPMC_CS_NUM 8
55#define GPMC_MEM_START 0x00000000 50#define GPMC_MEM_START 0x00000000
56#define GPMC_MEM_END 0x3FFFFFFF 51#define GPMC_MEM_END 0x3FFFFFFF
57#define BOOT_ROM_SPACE 0x100000 /* 1MB */ 52#define BOOT_ROM_SPACE 0x100000 /* 1MB */
@@ -64,12 +59,9 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
64static DEFINE_SPINLOCK(gpmc_mem_lock); 59static DEFINE_SPINLOCK(gpmc_mem_lock);
65static unsigned gpmc_cs_map; 60static unsigned gpmc_cs_map;
66 61
67static void __iomem *gpmc_base = 62static void __iomem *gpmc_base;
68 (void __iomem *) IO_ADDRESS(GPMC_BASE);
69static void __iomem *gpmc_cs_base =
70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
71 63
72static struct clk *gpmc_fck; 64static struct clk *gpmc_l3_clk;
73 65
74static void gpmc_write_reg(int idx, u32 val) 66static void gpmc_write_reg(int idx, u32 val)
75{ 67{
@@ -85,19 +77,32 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
85{ 77{
86 void __iomem *reg_addr; 78 void __iomem *reg_addr;
87 79
88 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx; 80 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
89 __raw_writel(val, reg_addr); 81 __raw_writel(val, reg_addr);
90} 82}
91 83
92u32 gpmc_cs_read_reg(int cs, int idx) 84u32 gpmc_cs_read_reg(int cs, int idx)
93{ 85{
94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); 86 void __iomem *reg_addr;
87
88 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
89 return __raw_readl(reg_addr);
95} 90}
96 91
92/* TODO: Add support for gpmc_fck to clock framework and use it */
97unsigned long gpmc_get_fclk_period(void) 93unsigned long gpmc_get_fclk_period(void)
98{ 94{
99 /* In picoseconds */ 95 unsigned long rate = clk_get_rate(gpmc_l3_clk);
100 return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000); 96
97 if (rate == 0) {
98 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
99 return 0;
100 }
101
102 rate /= 1000;
103 rate = 1000000000 / rate; /* In picoseconds */
104
105 return rate;
101} 106}
102 107
103unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 108unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -110,6 +115,11 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
110 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 115 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
111} 116}
112 117
118unsigned int gpmc_ticks_to_ns(unsigned int ticks)
119{
120 return ticks * gpmc_get_fclk_period() / 1000;
121}
122
113unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) 123unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
114{ 124{
115 unsigned long ticks = gpmc_ns_to_ticks(time_ns); 125 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
@@ -210,6 +220,11 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
210 220
211 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); 221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
212 222
223 if (cpu_is_omap34xx()) {
224 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
225 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
226 }
227
213 /* caller is expected to have initialized CONFIG1 to cover 228 /* caller is expected to have initialized CONFIG1 to cover
214 * at least sync vs async 229 * at least sync vs async
215 */ 230 */
@@ -350,6 +365,7 @@ out:
350 spin_unlock(&gpmc_mem_lock); 365 spin_unlock(&gpmc_mem_lock);
351 return r; 366 return r;
352} 367}
368EXPORT_SYMBOL(gpmc_cs_request);
353 369
354void gpmc_cs_free(int cs) 370void gpmc_cs_free(int cs)
355{ 371{
@@ -365,8 +381,9 @@ void gpmc_cs_free(int cs)
365 gpmc_cs_set_reserved(cs, 0); 381 gpmc_cs_set_reserved(cs, 0);
366 spin_unlock(&gpmc_mem_lock); 382 spin_unlock(&gpmc_mem_lock);
367} 383}
384EXPORT_SYMBOL(gpmc_cs_free);
368 385
369void __init gpmc_mem_init(void) 386static void __init gpmc_mem_init(void)
370{ 387{
371 int cs; 388 int cs;
372 unsigned long boot_rom_space = 0; 389 unsigned long boot_rom_space = 0;
@@ -396,12 +413,33 @@ void __init gpmc_mem_init(void)
396void __init gpmc_init(void) 413void __init gpmc_init(void)
397{ 414{
398 u32 l; 415 u32 l;
416 char *ck;
417
418 if (cpu_is_omap24xx()) {
419 ck = "core_l3_ck";
420 if (cpu_is_omap2420())
421 l = OMAP2420_GPMC_BASE;
422 else
423 l = OMAP34XX_GPMC_BASE;
424 } else if (cpu_is_omap34xx()) {
425 ck = "gpmc_fck";
426 l = OMAP34XX_GPMC_BASE;
427 }
399 428
400 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ 429 gpmc_l3_clk = clk_get(NULL, ck);
401 if (IS_ERR(gpmc_fck)) 430 if (IS_ERR(gpmc_l3_clk)) {
402 WARN_ON(1); 431 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
403 else 432 return -ENODEV;
404 clk_enable(gpmc_fck); 433 }
434
435 gpmc_base = ioremap(l, SZ_4K);
436 if (!gpmc_base) {
437 clk_put(gpmc_l3_clk);
438 printk(KERN_ERR "Could not get GPMC register memory\n");
439 return -ENOMEM;
440 }
441
442 BUG_ON(IS_ERR(gpmc_l3_clk));
405 443
406 l = gpmc_read_reg(GPMC_REVISION); 444 l = gpmc_read_reg(GPMC_REVISION);
407 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 445 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 209177c7f22f..bf45ff39a7b5 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -18,24 +18,15 @@
18 18
19#include <asm/cputype.h> 19#include <asm/cputype.h>
20 20
21#include <mach/common.h>
21#include <mach/control.h> 22#include <mach/control.h>
22#include <mach/cpu.h> 23#include <mach/cpu.h>
23 24
24#if defined(CONFIG_ARCH_OMAP2420) 25static u32 class;
25#define TAP_BASE io_p2v(0x48014000) 26static void __iomem *tap_base;
26#elif defined(CONFIG_ARCH_OMAP2430) 27static u16 tap_prod_id;
27#define TAP_BASE io_p2v(0x4900A000)
28#elif defined(CONFIG_ARCH_OMAP34XX)
29#define TAP_BASE io_p2v(0x4830A000)
30#endif
31 28
32#define OMAP_TAP_IDCODE 0x0204 29#define OMAP_TAP_IDCODE 0x0204
33#if defined(CONFIG_ARCH_OMAP34XX)
34#define OMAP_TAP_PROD_ID 0x0210
35#else
36#define OMAP_TAP_PROD_ID 0x0208
37#endif
38
39#define OMAP_TAP_DIE_ID_0 0x0218 30#define OMAP_TAP_DIE_ID_0 0x0218
40#define OMAP_TAP_DIE_ID_1 0x021C 31#define OMAP_TAP_DIE_ID_1 0x021C
41#define OMAP_TAP_DIE_ID_2 0x0220 32#define OMAP_TAP_DIE_ID_2 0x0220
@@ -94,18 +85,24 @@ static u32 __init read_tap_reg(int reg)
94 * it means its Cortex r0p0 which is 3430 ES1 85 * it means its Cortex r0p0 which is 3430 ES1
95 */ 86 */
96 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) { 87 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
88
89 if (reg == tap_prod_id) {
90 regval = 0x000F00F0;
91 goto out;
92 }
93
97 switch (reg) { 94 switch (reg) {
98 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break; 95 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
99 /* Making DevType as 0xF in ES1 to differ from ES2 */ 96 /* Making DevType as 0xF in ES1 to differ from ES2 */
100 case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
101 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break; 97 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
102 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break; 98 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
103 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break; 99 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
104 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break; 100 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
105 } 101 }
106 } else 102 } else
107 regval = __raw_readl(TAP_BASE + reg); 103 regval = __raw_readl(tap_base + reg);
108 104
105out:
109 return regval; 106 return regval;
110 107
111} 108}
@@ -204,7 +201,7 @@ void __init omap2_check_revision(void)
204 u8 rev; 201 u8 rev;
205 202
206 idcode = read_tap_reg(OMAP_TAP_IDCODE); 203 idcode = read_tap_reg(OMAP_TAP_IDCODE);
207 prod_id = read_tap_reg(OMAP_TAP_PROD_ID); 204 prod_id = read_tap_reg(tap_prod_id);
208 hawkeye = (idcode >> 12) & 0xffff; 205 hawkeye = (idcode >> 12) & 0xffff;
209 rev = (idcode >> 28) & 0x0f; 206 rev = (idcode >> 28) & 0x0f;
210 dev_type = (prod_id >> 16) & 0x0f; 207 dev_type = (prod_id >> 16) & 0x0f;
@@ -269,3 +266,13 @@ void __init omap2_check_revision(void)
269 266
270} 267}
271 268
269void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
270{
271 class = omap2_globals->class;
272 tap_base = omap2_globals->tap;
273
274 if (class == 0x3430)
275 tap_prod_id = 0x0210;
276 else
277 tap_prod_id = 0x0208;
278}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 7c3d6289c05f..5ea64f926ed5 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -4,8 +4,11 @@
4 * OMAP2 I/O mapping code 4 * OMAP2 I/O mapping code
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 7 * Copyright (C) 2007 Texas Instruments
8 * Updated map desc to add 2430 support : <x0khasim@ti.com> 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
9 * 12 *
10 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
@@ -23,19 +26,26 @@
23 26
24#include <mach/mux.h> 27#include <mach/mux.h>
25#include <mach/omapfb.h> 28#include <mach/omapfb.h>
29#include <mach/sram.h>
30
31#include "memory.h"
32
33#include "clock.h"
34
35#include <mach/powerdomain.h>
36
37#include "powerdomains.h"
26 38
27extern void omap_sram_init(void); 39#include <mach/clockdomain.h>
28extern int omap2_clk_init(void); 40#include "clockdomains.h"
29extern void omap2_check_revision(void);
30extern void omap2_init_memory(void);
31extern void gpmc_init(void);
32extern void omapfb_reserve_sdram(void);
33 41
34/* 42/*
35 * The machine specific code may provide the extra mapping besides the 43 * The machine specific code may provide the extra mapping besides the
36 * default mapping provided here. 44 * default mapping provided here.
37 */ 45 */
38static struct map_desc omap2_io_desc[] __initdata = { 46
47#ifdef CONFIG_ARCH_OMAP24XX
48static struct map_desc omap24xx_io_desc[] __initdata = {
39 { 49 {
40 .virtual = L3_24XX_VIRT, 50 .virtual = L3_24XX_VIRT,
41 .pfn = __phys_to_pfn(L3_24XX_PHYS), 51 .pfn = __phys_to_pfn(L3_24XX_PHYS),
@@ -43,12 +53,39 @@ static struct map_desc omap2_io_desc[] __initdata = {
43 .type = MT_DEVICE 53 .type = MT_DEVICE
44 }, 54 },
45 { 55 {
46 .virtual = L4_24XX_VIRT, 56 .virtual = L4_24XX_VIRT,
47 .pfn = __phys_to_pfn(L4_24XX_PHYS), 57 .pfn = __phys_to_pfn(L4_24XX_PHYS),
48 .length = L4_24XX_SIZE, 58 .length = L4_24XX_SIZE,
49 .type = MT_DEVICE 59 .type = MT_DEVICE
50 }, 60 },
61};
62
63#ifdef CONFIG_ARCH_OMAP2420
64static struct map_desc omap242x_io_desc[] __initdata = {
65 {
66 .virtual = DSP_MEM_24XX_VIRT,
67 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
68 .length = DSP_MEM_24XX_SIZE,
69 .type = MT_DEVICE
70 },
71 {
72 .virtual = DSP_IPI_24XX_VIRT,
73 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
74 .length = DSP_IPI_24XX_SIZE,
75 .type = MT_DEVICE
76 },
77 {
78 .virtual = DSP_MMU_24XX_VIRT,
79 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
80 .length = DSP_MMU_24XX_SIZE,
81 .type = MT_DEVICE
82 },
83};
84
85#endif
86
51#ifdef CONFIG_ARCH_OMAP2430 87#ifdef CONFIG_ARCH_OMAP2430
88static struct map_desc omap243x_io_desc[] __initdata = {
52 { 89 {
53 .virtual = L4_WK_243X_VIRT, 90 .virtual = L4_WK_243X_VIRT,
54 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 91 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
@@ -61,30 +98,90 @@ static struct map_desc omap2_io_desc[] __initdata = {
61 .length = OMAP243X_GPMC_SIZE, 98 .length = OMAP243X_GPMC_SIZE,
62 .type = MT_DEVICE 99 .type = MT_DEVICE
63 }, 100 },
101 {
102 .virtual = OMAP243X_SDRC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
104 .length = OMAP243X_SDRC_SIZE,
105 .type = MT_DEVICE
106 },
107 {
108 .virtual = OMAP243X_SMS_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
110 .length = OMAP243X_SMS_SIZE,
111 .type = MT_DEVICE
112 },
113};
114#endif
64#endif 115#endif
116
117#ifdef CONFIG_ARCH_OMAP34XX
118static struct map_desc omap34xx_io_desc[] __initdata = {
65 { 119 {
66 .virtual = DSP_MEM_24XX_VIRT, 120 .virtual = L3_34XX_VIRT,
67 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS), 121 .pfn = __phys_to_pfn(L3_34XX_PHYS),
68 .length = DSP_MEM_24XX_SIZE, 122 .length = L3_34XX_SIZE,
69 .type = MT_DEVICE 123 .type = MT_DEVICE
70 }, 124 },
71 { 125 {
72 .virtual = DSP_IPI_24XX_VIRT, 126 .virtual = L4_34XX_VIRT,
73 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS), 127 .pfn = __phys_to_pfn(L4_34XX_PHYS),
74 .length = DSP_IPI_24XX_SIZE, 128 .length = L4_34XX_SIZE,
75 .type = MT_DEVICE 129 .type = MT_DEVICE
76 }, 130 },
77 { 131 {
78 .virtual = DSP_MMU_24XX_VIRT, 132 .virtual = L4_WK_34XX_VIRT,
79 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS), 133 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
80 .length = DSP_MMU_24XX_SIZE, 134 .length = L4_WK_34XX_SIZE,
135 .type = MT_DEVICE
136 },
137 {
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
81 .type = MT_DEVICE 141 .type = MT_DEVICE
82 } 142 },
143 {
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
147 .type = MT_DEVICE
148 },
149 {
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
153 .type = MT_DEVICE
154 },
155 {
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
159 .type = MT_DEVICE
160 },
161 {
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
165 .type = MT_DEVICE
166 },
83}; 167};
168#endif
84 169
85void __init omap2_map_common_io(void) 170void __init omap2_map_common_io(void)
86{ 171{
87 iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc)); 172#if defined(CONFIG_ARCH_OMAP2420)
173 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
174 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
175#endif
176
177#if defined(CONFIG_ARCH_OMAP2430)
178 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
179 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
180#endif
181
182#if defined(CONFIG_ARCH_OMAP34XX)
183 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
184#endif
88 185
89 /* Normally devicemaps_init() would flush caches and tlb after 186 /* Normally devicemaps_init() would flush caches and tlb after
90 * mdesc->map_io(), but we must also do it here because of the CPU 187 * mdesc->map_io(), but we must also do it here because of the CPU
@@ -101,12 +198,9 @@ void __init omap2_map_common_io(void)
101void __init omap2_init_common_hw(void) 198void __init omap2_init_common_hw(void)
102{ 199{
103 omap2_mux_init(); 200 omap2_mux_init();
201 pwrdm_init(powerdomains_omap);
202 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
104 omap2_clk_init(); 203 omap2_clk_init();
105/*
106 * Need to Fix this for 2430
107 */
108#ifndef CONFIG_ARCH_OMAP2430
109 omap2_init_memory(); 204 omap2_init_memory();
110#endif
111 gpmc_init(); 205 gpmc_init();
112} 206}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 003901f1e2da..c40fc378a251 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -16,14 +16,20 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <asm/mach/irq.h> 18#include <asm/mach/irq.h>
19#include <asm/irq.h>
20 19
21#define INTC_REVISION 0x0000 20
22#define INTC_SYSCONFIG 0x0010 21/* selected INTC register offsets */
23#define INTC_SYSSTATUS 0x0014 22
24#define INTC_CONTROL 0x0048 23#define INTC_REVISION 0x0000
25#define INTC_MIR_CLEAR0 0x0088 24#define INTC_SYSCONFIG 0x0010
26#define INTC_MIR_SET0 0x008c 25#define INTC_SYSSTATUS 0x0014
26#define INTC_CONTROL 0x0048
27#define INTC_MIR_CLEAR0 0x0088
28#define INTC_MIR_SET0 0x008c
29#define INTC_PENDING_IRQ0 0x0098
30
31/* Number of IRQ state bits in each MIR register */
32#define IRQ_BITS_PER_REG 32
27 33
28/* 34/*
29 * OMAP2 has a number of different interrupt controllers, each interrupt 35 * OMAP2 has a number of different interrupt controllers, each interrupt
@@ -32,48 +38,50 @@
32 * for each bank.. when in doubt, consult the TRM. 38 * for each bank.. when in doubt, consult the TRM.
33 */ 39 */
34static struct omap_irq_bank { 40static struct omap_irq_bank {
35 unsigned long base_reg; 41 void __iomem *base_reg;
36 unsigned int nr_irqs; 42 unsigned int nr_irqs;
37} __attribute__ ((aligned(4))) irq_banks[] = { 43} __attribute__ ((aligned(4))) irq_banks[] = {
38 { 44 {
39 /* MPU INTC */ 45 /* MPU INTC */
40 .base_reg = IO_ADDRESS(OMAP24XX_IC_BASE), 46 .base_reg = 0,
41 .nr_irqs = 96, 47 .nr_irqs = 96,
42 }, { 48 },
43 /* XXX: DSP INTC */
44 }
45}; 49};
46 50
51/* INTC bank register get/set */
52
53static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
54{
55 __raw_writel(val, bank->base_reg + reg);
56}
57
58static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
59{
60 return __raw_readl(bank->base_reg + reg);
61}
62
47/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 63/* XXX: FIQ and additional INTC support (only MPU at the moment) */
48static void omap_ack_irq(unsigned int irq) 64static void omap_ack_irq(unsigned int irq)
49{ 65{
50 __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); 66 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
51} 67}
52 68
53static void omap_mask_irq(unsigned int irq) 69static void omap_mask_irq(unsigned int irq)
54{ 70{
55 int offset = (irq >> 5) << 5; 71 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
56 72
57 if (irq >= 64) { 73 irq &= (IRQ_BITS_PER_REG - 1);
58 irq %= 64;
59 } else if (irq >= 32) {
60 irq %= 32;
61 }
62 74
63 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); 75 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
64} 76}
65 77
66static void omap_unmask_irq(unsigned int irq) 78static void omap_unmask_irq(unsigned int irq)
67{ 79{
68 int offset = (irq >> 5) << 5; 80 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
69 81
70 if (irq >= 64) { 82 irq &= (IRQ_BITS_PER_REG - 1);
71 irq %= 64;
72 } else if (irq >= 32) {
73 irq %= 32;
74 }
75 83
76 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); 84 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
77} 85}
78 86
79static void omap_mask_ack_irq(unsigned int irq) 87static void omap_mask_ack_irq(unsigned int irq)
@@ -93,20 +101,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
93{ 101{
94 unsigned long tmp; 102 unsigned long tmp;
95 103
96 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff; 104 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
97 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx " 105 printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
98 "(revision %ld.%ld) with %d interrupts\n", 106 "(revision %ld.%ld) with %d interrupts\n",
99 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); 107 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
100 108
101 tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG); 109 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
102 tmp |= 1 << 1; /* soft reset */ 110 tmp |= 1 << 1; /* soft reset */
103 __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG); 111 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
104 112
105 while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) 113 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
106 /* Wait for reset to complete */; 114 /* Wait for reset to complete */;
107 115
108 /* Enable autoidle */ 116 /* Enable autoidle */
109 __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG); 117 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
110} 118}
111 119
112void __init omap_init_irq(void) 120void __init omap_init_irq(void)
@@ -118,9 +126,10 @@ void __init omap_init_irq(void)
118 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 126 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
119 struct omap_irq_bank *bank = irq_banks + i; 127 struct omap_irq_bank *bank = irq_banks + i;
120 128
121 /* XXX */ 129 if (cpu_is_omap24xx())
122 if (!bank->base_reg) 130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
123 continue; 131 else if (cpu_is_omap34xx())
132 bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
124 133
125 omap_irq_bank_init_one(bank); 134 omap_irq_bank_init_one(bank);
126 135
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index b261f1f80b5e..cae3ebe249b3 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -89,6 +89,30 @@ static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
89 .disable = omap_mcbsp_clk_disable, 89 .disable = omap_mcbsp_clk_disable,
90 }, 90 },
91 }, 91 },
92 {
93 .clk = {
94 .name = "mcbsp_clk",
95 .id = 3,
96 .enable = omap_mcbsp_clk_enable,
97 .disable = omap_mcbsp_clk_disable,
98 },
99 },
100 {
101 .clk = {
102 .name = "mcbsp_clk",
103 .id = 4,
104 .enable = omap_mcbsp_clk_enable,
105 .disable = omap_mcbsp_clk_disable,
106 },
107 },
108 {
109 .clk = {
110 .name = "mcbsp_clk",
111 .id = 5,
112 .enable = omap_mcbsp_clk_enable,
113 .disable = omap_mcbsp_clk_disable,
114 },
115 },
92}; 116};
93 117
94#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks) 118#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
@@ -117,25 +141,14 @@ static void omap2_mcbsp_request(unsigned int id)
117 omap2_mcbsp2_mux_setup(); 141 omap2_mcbsp2_mux_setup();
118} 142}
119 143
120static int omap2_mcbsp_check(unsigned int id)
121{
122 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
123 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
124 return -ENODEV;
125 }
126 return 0;
127}
128
129static struct omap_mcbsp_ops omap2_mcbsp_ops = { 144static struct omap_mcbsp_ops omap2_mcbsp_ops = {
130 .request = omap2_mcbsp_request, 145 .request = omap2_mcbsp_request,
131 .check = omap2_mcbsp_check,
132}; 146};
133 147
134#ifdef CONFIG_ARCH_OMAP24XX 148#ifdef CONFIG_ARCH_OMAP2420
135static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = { 149static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
136 { 150 {
137 .phys_base = OMAP24XX_MCBSP1_BASE, 151 .phys_base = OMAP24XX_MCBSP1_BASE,
138 .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
139 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 152 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
140 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 153 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
141 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 154 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
@@ -145,7 +158,6 @@ static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
145 }, 158 },
146 { 159 {
147 .phys_base = OMAP24XX_MCBSP2_BASE, 160 .phys_base = OMAP24XX_MCBSP2_BASE,
148 .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
149 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 161 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
150 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 162 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
151 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 163 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
@@ -154,17 +166,70 @@ static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
154 .clk_name = "mcbsp_clk", 166 .clk_name = "mcbsp_clk",
155 }, 167 },
156}; 168};
157#define OMAP24XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap24xx_mcbsp_pdata) 169#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
158#else 170#else
159#define omap24xx_mcbsp_pdata NULL 171#define omap2420_mcbsp_pdata NULL
160#define OMAP24XX_MCBSP_PDATA_SZ 0 172#define OMAP2420_MCBSP_PDATA_SZ 0
173#endif
174
175#ifdef CONFIG_ARCH_OMAP2430
176static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
177 {
178 .phys_base = OMAP24XX_MCBSP1_BASE,
179 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
180 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
181 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
182 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
183 .ops = &omap2_mcbsp_ops,
184 .clk_name = "mcbsp_clk",
185 },
186 {
187 .phys_base = OMAP24XX_MCBSP2_BASE,
188 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
189 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
190 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
191 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
192 .ops = &omap2_mcbsp_ops,
193 .clk_name = "mcbsp_clk",
194 },
195 {
196 .phys_base = OMAP2430_MCBSP3_BASE,
197 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
198 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
199 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
200 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
201 .ops = &omap2_mcbsp_ops,
202 .clk_name = "mcbsp_clk",
203 },
204 {
205 .phys_base = OMAP2430_MCBSP4_BASE,
206 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
207 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
208 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
209 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
210 .ops = &omap2_mcbsp_ops,
211 .clk_name = "mcbsp_clk",
212 },
213 {
214 .phys_base = OMAP2430_MCBSP5_BASE,
215 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
216 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
217 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
218 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
219 .ops = &omap2_mcbsp_ops,
220 .clk_name = "mcbsp_clk",
221 },
222};
223#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
224#else
225#define omap2430_mcbsp_pdata NULL
226#define OMAP2430_MCBSP_PDATA_SZ 0
161#endif 227#endif
162 228
163#ifdef CONFIG_ARCH_OMAP34XX 229#ifdef CONFIG_ARCH_OMAP34XX
164static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { 230static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
165 { 231 {
166 .phys_base = OMAP34XX_MCBSP1_BASE, 232 .phys_base = OMAP34XX_MCBSP1_BASE,
167 .virt_base = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
168 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 233 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
169 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 234 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
170 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 235 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
@@ -174,7 +239,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
174 }, 239 },
175 { 240 {
176 .phys_base = OMAP34XX_MCBSP2_BASE, 241 .phys_base = OMAP34XX_MCBSP2_BASE,
177 .virt_base = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
178 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, 242 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
179 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 243 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
180 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 244 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
@@ -182,6 +246,33 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
182 .ops = &omap2_mcbsp_ops, 246 .ops = &omap2_mcbsp_ops,
183 .clk_name = "mcbsp_clk", 247 .clk_name = "mcbsp_clk",
184 }, 248 },
249 {
250 .phys_base = OMAP34XX_MCBSP3_BASE,
251 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
252 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
253 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
254 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
255 .ops = &omap2_mcbsp_ops,
256 .clk_name = "mcbsp_clk",
257 },
258 {
259 .phys_base = OMAP34XX_MCBSP4_BASE,
260 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
261 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
262 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
263 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
264 .ops = &omap2_mcbsp_ops,
265 .clk_name = "mcbsp_clk",
266 },
267 {
268 .phys_base = OMAP34XX_MCBSP5_BASE,
269 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
270 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
271 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
272 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
273 .ops = &omap2_mcbsp_ops,
274 .clk_name = "mcbsp_clk",
275 },
185}; 276};
186#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) 277#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
187#else 278#else
@@ -189,7 +280,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
189#define OMAP34XX_MCBSP_PDATA_SZ 0 280#define OMAP34XX_MCBSP_PDATA_SZ 0
190#endif 281#endif
191 282
192int __init omap2_mcbsp_init(void) 283static int __init omap2_mcbsp_init(void)
193{ 284{
194 int i; 285 int i;
195 286
@@ -199,10 +290,24 @@ int __init omap2_mcbsp_init(void)
199 clk_register(&omap_mcbsp_clks[i].clk); 290 clk_register(&omap_mcbsp_clks[i].clk);
200 } 291 }
201 292
202 if (cpu_is_omap24xx()) 293 if (cpu_is_omap2420())
203 omap_mcbsp_register_board_cfg(omap24xx_mcbsp_pdata, 294 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
204 OMAP24XX_MCBSP_PDATA_SZ); 295 if (cpu_is_omap2430())
296 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
297 if (cpu_is_omap34xx())
298 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
299
300 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
301 GFP_KERNEL);
302 if (!mcbsp_ptr)
303 return -ENOMEM;
205 304
305 if (cpu_is_omap2420())
306 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
307 OMAP2420_MCBSP_PDATA_SZ);
308 if (cpu_is_omap2430())
309 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
310 OMAP2430_MCBSP_PDATA_SZ);
206 if (cpu_is_omap34xx()) 311 if (cpu_is_omap34xx())
207 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, 312 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
208 OMAP34XX_MCBSP_PDATA_SZ); 313 OMAP34XX_MCBSP_PDATA_SZ);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index ab1462b02e6e..882c70224292 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -101,6 +101,17 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
101 return prev; 101 return prev;
102} 102}
103 103
104#if !defined(CONFIG_ARCH_OMAP2)
105void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
106 u32 base_cs, u32 force_unlock)
107{
108}
109void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
110 u32 mem_type)
111{
112}
113#endif
114
104void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 115void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
105{ 116{
106 unsigned long dll_cnt; 117 unsigned long dll_cnt;
@@ -165,6 +176,9 @@ void __init omap2_init_memory(void)
165{ 176{
166 u32 l; 177 u32 l;
167 178
179 if (!cpu_is_omap2420())
180 return;
181
168 l = sms_read_reg(SMS_SYSCONFIG); 182 l = sms_read_reg(SMS_SYSCONFIG);
169 l &= ~(0x3 << 3); 183 l &= ~(0x3 << 3);
170 l |= (0x2 << 3); 184 l |= (0x2 << 3);
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index 9a280b50a893..bb3db80a7c46 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -14,6 +14,9 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
18#define ARCH_ARM_MACH_OMAP2_MEMORY_H
19
17/* Memory timings */ 20/* Memory timings */
18#define M_DDR 1 21#define M_DDR 1
19#define M_LOCK_CTRL (1 << 2) 22#define M_LOCK_CTRL (1 << 2)
@@ -34,3 +37,7 @@ extern u32 omap2_memory_get_fast_dll_ctrl(void);
34extern u32 omap2_memory_get_type(void); 37extern u32 omap2_memory_get_type(void);
35u32 omap2_dll_force_needed(void); 38u32 omap2_dll_force_needed(void);
36u32 omap2_reprogram_sdrc(u32 level, u32 force); 39u32 omap2_reprogram_sdrc(u32 level, u32 force);
40void __init omap2_init_memory(void);
41void __init gpmc_init(void);
42
43#endif
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 6b7d672058b9..b1393673d95d 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/mux.c 2 * linux/arch/arm/mach-omap2/mux.c
3 * 3 *
4 * OMAP2 pin multiplexing configurations 4 * OMAP2 and OMAP3 pin multiplexing configurations
5 * 5 *
6 * Copyright (C) 2004 - 2008 Texas Instruments Inc. 6 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation 7 * Copyright (C) 2003 - 2008 Nokia Corporation
@@ -220,16 +220,222 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
220#define OMAP24XX_PINS_SZ 0 220#define OMAP24XX_PINS_SZ 0
221#endif /* CONFIG_ARCH_OMAP24XX */ 221#endif /* CONFIG_ARCH_OMAP24XX */
222 222
223#define OMAP24XX_PULL_ENA (1 << 3) 223#ifdef CONFIG_ARCH_OMAP34XX
224#define OMAP24XX_PULL_UP (1 << 4) 224static struct pin_config __initdata_or_module omap34xx_pins[] = {
225/*
226 * Name, reg-offset,
227 * mux-mode | [active-mode | off-mode]
228 */
229
230/* 34xx I2C */
231MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
232 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
233MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
234 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
235MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
236 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
237MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
238 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
239MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
240 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
241MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
242 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
243MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
244 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
245MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
246 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
247
248/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
249MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
250 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
251MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
252 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
253MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
254 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
255MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
256 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
257MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
258 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
259MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
260 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
261MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
262 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
263MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
264 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
265MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
266 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
267MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
268 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
269MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
270 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
271MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
272 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
273
274/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
275MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
276 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
277MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
278 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
279MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
280 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
281MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
282 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
283MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
284 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
285MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
286 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
287MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
288 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
289MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
290 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
291MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
292 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
293MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
294 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
295MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
296 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
297MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
298 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
299
300/* TLL - HSUSB: 12-pin TLL Port 1*/
301MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
302 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
303MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
304 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
305MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
306 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
307MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
308 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
309MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
310 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
311MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
312 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
313MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
314 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
315MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
316 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
317MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
318 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
319MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
320 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
321MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
322 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
323MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
324 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
325
326/* TLL - HSUSB: 12-pin TLL Port 2*/
327MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
328 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
329MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
330 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
331MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
332 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
333MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
334 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
335MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
336 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
337MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
338 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
339MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
340 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
341MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
342 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
343MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
344 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
345MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
346 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
347MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
348 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
349MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
350 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
351
352/* TLL - HSUSB: 12-pin TLL Port 3*/
353MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
354 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
355MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
356 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
357MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
358 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
359MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
360 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
361MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
362 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
363MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
364 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
365MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
366 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
367MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
368 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
369MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
370 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
371MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
372 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
373MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
374 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
375MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
376 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
377
378/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
379MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
380 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
381MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
382 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
383MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
384 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
385MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
386 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
387MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
388 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
389MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
390 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
391
392/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
393MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
394 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
395MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
396 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
397MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
398 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
399MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
400 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
401MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
402 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
403MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
404 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
405
406/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
407MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
408 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
409MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
410 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
411MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
412 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
413MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
414 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
415MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
416 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
417MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
418 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
419
420};
421
422#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
423
424#else
425#define omap34xx_pins NULL
426#define OMAP34XX_PINS_SZ 0
427#endif /* CONFIG_ARCH_OMAP34XX */
225 428
226#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) 429#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
227void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg) 430static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
228{ 431{
229 u16 orig; 432 u16 orig;
230 u8 warn = 0, debug = 0; 433 u8 warn = 0, debug = 0;
231 434
232 orig = omap_ctrl_readb(cfg->mux_reg); 435 if (cpu_is_omap24xx())
436 orig = omap_ctrl_readb(cfg->mux_reg);
437 else
438 orig = omap_ctrl_readw(cfg->mux_reg);
233 439
234#ifdef CONFIG_OMAP_MUX_DEBUG 440#ifdef CONFIG_OMAP_MUX_DEBUG
235 debug = cfg->debug; 441 debug = cfg->debug;
@@ -255,9 +461,9 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
255 spin_lock_irqsave(&mux_spin_lock, flags); 461 spin_lock_irqsave(&mux_spin_lock, flags);
256 reg |= cfg->mask & 0x7; 462 reg |= cfg->mask & 0x7;
257 if (cfg->pull_val) 463 if (cfg->pull_val)
258 reg |= OMAP24XX_PULL_ENA; 464 reg |= OMAP2_PULL_ENA;
259 if (cfg->pu_pd_val) 465 if (cfg->pu_pd_val)
260 reg |= OMAP24XX_PULL_UP; 466 reg |= OMAP2_PULL_UP;
261 omap2_cfg_debug(cfg, reg); 467 omap2_cfg_debug(cfg, reg);
262 omap_ctrl_writeb(reg, cfg->mux_reg); 468 omap_ctrl_writeb(reg, cfg->mux_reg);
263 spin_unlock_irqrestore(&mux_spin_lock, flags); 469 spin_unlock_irqrestore(&mux_spin_lock, flags);
@@ -265,7 +471,26 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
265 return 0; 471 return 0;
266} 472}
267#else 473#else
268#define omap24xx_cfg_reg 0 474#define omap24xx_cfg_reg NULL
475#endif
476
477#ifdef CONFIG_ARCH_OMAP34XX
478static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
479{
480 static DEFINE_SPINLOCK(mux_spin_lock);
481 unsigned long flags;
482 u16 reg = 0;
483
484 spin_lock_irqsave(&mux_spin_lock, flags);
485 reg |= cfg->mux_val;
486 omap2_cfg_debug(cfg, reg);
487 omap_ctrl_writew(reg, cfg->mux_reg);
488 spin_unlock_irqrestore(&mux_spin_lock, flags);
489
490 return 0;
491}
492#else
493#define omap34xx_cfg_reg NULL
269#endif 494#endif
270 495
271int __init omap2_mux_init(void) 496int __init omap2_mux_init(void)
@@ -274,6 +499,10 @@ int __init omap2_mux_init(void)
274 arch_mux_cfg.pins = omap24xx_pins; 499 arch_mux_cfg.pins = omap24xx_pins;
275 arch_mux_cfg.size = OMAP24XX_PINS_SZ; 500 arch_mux_cfg.size = OMAP24XX_PINS_SZ;
276 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; 501 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
502 } else if (cpu_is_omap34xx()) {
503 arch_mux_cfg.pins = omap34xx_pins;
504 arch_mux_cfg.size = OMAP34XX_PINS_SZ;
505 arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
277 } 506 }
278 507
279 return omap_mux_register(&arch_mux_cfg); 508 return omap_mux_register(&arch_mux_cfg);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
new file mode 100644
index 000000000000..73e2971b1757
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -0,0 +1,1113 @@
1/*
2 * OMAP powerdomain control
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifdef CONFIG_OMAP_DEBUG_POWERDOMAIN
14# define DEBUG
15#endif
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/delay.h>
21#include <linux/spinlock.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/err.h>
25#include <linux/io.h>
26
27#include <asm/atomic.h>
28
29#include "cm.h"
30#include "cm-regbits-34xx.h"
31#include "prm.h"
32#include "prm-regbits-34xx.h"
33
34#include <mach/cpu.h>
35#include <mach/powerdomain.h>
36#include <mach/clockdomain.h>
37
38/* pwrdm_list contains all registered struct powerdomains */
39static LIST_HEAD(pwrdm_list);
40
41/*
42 * pwrdm_rwlock protects pwrdm_list add and del ops - also reused to
43 * protect pwrdm_clkdms[] during clkdm add/del ops
44 */
45static DEFINE_RWLOCK(pwrdm_rwlock);
46
47
48/* Private functions */
49
50static u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
51{
52 u32 v;
53
54 v = prm_read_mod_reg(domain, idx);
55 v &= mask;
56 v >>= __ffs(mask);
57
58 return v;
59}
60
61static struct powerdomain *_pwrdm_lookup(const char *name)
62{
63 struct powerdomain *pwrdm, *temp_pwrdm;
64
65 pwrdm = NULL;
66
67 list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
68 if (!strcmp(name, temp_pwrdm->name)) {
69 pwrdm = temp_pwrdm;
70 break;
71 }
72 }
73
74 return pwrdm;
75}
76
77/* _pwrdm_deps_lookup - look up the specified powerdomain in a pwrdm list */
78static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
79 struct pwrdm_dep *deps)
80{
81 struct pwrdm_dep *pd;
82
83 if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip))
84 return ERR_PTR(-EINVAL);
85
86 for (pd = deps; pd; pd++) {
87
88 if (!omap_chip_is(pd->omap_chip))
89 continue;
90
91 if (!pd->pwrdm && pd->pwrdm_name)
92 pd->pwrdm = pwrdm_lookup(pd->pwrdm_name);
93
94 if (pd->pwrdm == pwrdm)
95 break;
96
97 }
98
99 if (!pd)
100 return ERR_PTR(-ENOENT);
101
102 return pd->pwrdm;
103}
104
105
106/* Public functions */
107
108/**
109 * pwrdm_init - set up the powerdomain layer
110 *
111 * Loop through the list of powerdomains, registering all that are
112 * available on the current CPU. If pwrdm_list is supplied and not
113 * null, all of the referenced powerdomains will be registered. No
114 * return value.
115 */
116void pwrdm_init(struct powerdomain **pwrdm_list)
117{
118 struct powerdomain **p = NULL;
119
120 if (pwrdm_list)
121 for (p = pwrdm_list; *p; p++)
122 pwrdm_register(*p);
123}
124
125/**
126 * pwrdm_register - register a powerdomain
127 * @pwrdm: struct powerdomain * to register
128 *
129 * Adds a powerdomain to the internal powerdomain list. Returns
130 * -EINVAL if given a null pointer, -EEXIST if a powerdomain is
131 * already registered by the provided name, or 0 upon success.
132 */
133int pwrdm_register(struct powerdomain *pwrdm)
134{
135 unsigned long flags;
136 int ret = -EINVAL;
137
138 if (!pwrdm)
139 return -EINVAL;
140
141 if (!omap_chip_is(pwrdm->omap_chip))
142 return -EINVAL;
143
144 write_lock_irqsave(&pwrdm_rwlock, flags);
145 if (_pwrdm_lookup(pwrdm->name)) {
146 ret = -EEXIST;
147 goto pr_unlock;
148 }
149
150 list_add(&pwrdm->node, &pwrdm_list);
151
152 pr_debug("powerdomain: registered %s\n", pwrdm->name);
153 ret = 0;
154
155pr_unlock:
156 write_unlock_irqrestore(&pwrdm_rwlock, flags);
157
158 return ret;
159}
160
161/**
162 * pwrdm_unregister - unregister a powerdomain
163 * @pwrdm: struct powerdomain * to unregister
164 *
165 * Removes a powerdomain from the internal powerdomain list. Returns
166 * -EINVAL if pwrdm argument is NULL.
167 */
168int pwrdm_unregister(struct powerdomain *pwrdm)
169{
170 unsigned long flags;
171
172 if (!pwrdm)
173 return -EINVAL;
174
175 write_lock_irqsave(&pwrdm_rwlock, flags);
176 list_del(&pwrdm->node);
177 write_unlock_irqrestore(&pwrdm_rwlock, flags);
178
179 pr_debug("powerdomain: unregistered %s\n", pwrdm->name);
180
181 return 0;
182}
183
184/**
185 * pwrdm_lookup - look up a powerdomain by name, return a pointer
186 * @name: name of powerdomain
187 *
188 * Find a registered powerdomain by its name. Returns a pointer to the
189 * struct powerdomain if found, or NULL otherwise.
190 */
191struct powerdomain *pwrdm_lookup(const char *name)
192{
193 struct powerdomain *pwrdm;
194 unsigned long flags;
195
196 if (!name)
197 return NULL;
198
199 read_lock_irqsave(&pwrdm_rwlock, flags);
200 pwrdm = _pwrdm_lookup(name);
201 read_unlock_irqrestore(&pwrdm_rwlock, flags);
202
203 return pwrdm;
204}
205
206/**
207 * pwrdm_for_each - call function on each registered clockdomain
208 * @fn: callback function *
209 *
210 * Call the supplied function for each registered powerdomain. The
211 * callback function can return anything but 0 to bail out early from
212 * the iterator. The callback function is called with the pwrdm_rwlock
213 * held for reading, so no powerdomain structure manipulation
214 * functions should be called from the callback, although hardware
215 * powerdomain control functions are fine. Returns the last return
216 * value of the callback function, which should be 0 for success or
217 * anything else to indicate failure; or -EINVAL if the function
218 * pointer is null.
219 */
220int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
221{
222 struct powerdomain *temp_pwrdm;
223 unsigned long flags;
224 int ret = 0;
225
226 if (!fn)
227 return -EINVAL;
228
229 read_lock_irqsave(&pwrdm_rwlock, flags);
230 list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
231 ret = (*fn)(temp_pwrdm);
232 if (ret)
233 break;
234 }
235 read_unlock_irqrestore(&pwrdm_rwlock, flags);
236
237 return ret;
238}
239
240/**
241 * pwrdm_add_clkdm - add a clockdomain to a powerdomain
242 * @pwrdm: struct powerdomain * to add the clockdomain to
243 * @clkdm: struct clockdomain * to associate with a powerdomain
244 *
245 * Associate the clockdomain 'clkdm' with a powerdomain 'pwrdm'. This
246 * enables the use of pwrdm_for_each_clkdm(). Returns -EINVAL if
247 * presented with invalid pointers; -ENOMEM if memory could not be allocated;
248 * or 0 upon success.
249 */
250int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
251{
252 unsigned long flags;
253 int i;
254 int ret = -EINVAL;
255
256 if (!pwrdm || !clkdm)
257 return -EINVAL;
258
259 pr_debug("powerdomain: associating clockdomain %s with powerdomain "
260 "%s\n", clkdm->name, pwrdm->name);
261
262 write_lock_irqsave(&pwrdm_rwlock, flags);
263
264 for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
265 if (!pwrdm->pwrdm_clkdms[i])
266 break;
267#ifdef DEBUG
268 if (pwrdm->pwrdm_clkdms[i] == clkdm) {
269 ret = -EINVAL;
270 goto pac_exit;
271 }
272#endif
273 }
274
275 if (i == PWRDM_MAX_CLKDMS) {
276 pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
277 "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
278 WARN_ON(1);
279 ret = -ENOMEM;
280 goto pac_exit;
281 }
282
283 pwrdm->pwrdm_clkdms[i] = clkdm;
284
285 ret = 0;
286
287pac_exit:
288 write_unlock_irqrestore(&pwrdm_rwlock, flags);
289
290 return ret;
291}
292
293/**
294 * pwrdm_del_clkdm - remove a clockdomain from a powerdomain
295 * @pwrdm: struct powerdomain * to add the clockdomain to
296 * @clkdm: struct clockdomain * to associate with a powerdomain
297 *
298 * Dissociate the clockdomain 'clkdm' from the powerdomain
299 * 'pwrdm'. Returns -EINVAL if presented with invalid pointers;
300 * -ENOENT if the clkdm was not associated with the powerdomain, or 0
301 * upon success.
302 */
303int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm)
304{
305 unsigned long flags;
306 int ret = -EINVAL;
307 int i;
308
309 if (!pwrdm || !clkdm)
310 return -EINVAL;
311
312 pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
313 "%s\n", clkdm->name, pwrdm->name);
314
315 write_lock_irqsave(&pwrdm_rwlock, flags);
316
317 for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
318 if (pwrdm->pwrdm_clkdms[i] == clkdm)
319 break;
320
321 if (i == PWRDM_MAX_CLKDMS) {
322 pr_debug("powerdomain: clkdm %s not associated with pwrdm "
323 "%s ?!\n", clkdm->name, pwrdm->name);
324 ret = -ENOENT;
325 goto pdc_exit;
326 }
327
328 pwrdm->pwrdm_clkdms[i] = NULL;
329
330 ret = 0;
331
332pdc_exit:
333 write_unlock_irqrestore(&pwrdm_rwlock, flags);
334
335 return ret;
336}
337
338/**
339 * pwrdm_for_each_clkdm - call function on each clkdm in a pwrdm
340 * @pwrdm: struct powerdomain * to iterate over
341 * @fn: callback function *
342 *
343 * Call the supplied function for each clockdomain in the powerdomain
344 * 'pwrdm'. The callback function can return anything but 0 to bail
345 * out early from the iterator. The callback function is called with
346 * the pwrdm_rwlock held for reading, so no powerdomain structure
347 * manipulation functions should be called from the callback, although
348 * hardware powerdomain control functions are fine. Returns -EINVAL
349 * if presented with invalid pointers; or passes along the last return
350 * value of the callback function, which should be 0 for success or
351 * anything else to indicate failure.
352 */
353int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
354 int (*fn)(struct powerdomain *pwrdm,
355 struct clockdomain *clkdm))
356{
357 unsigned long flags;
358 int ret = 0;
359 int i;
360
361 if (!fn)
362 return -EINVAL;
363
364 read_lock_irqsave(&pwrdm_rwlock, flags);
365
366 for (i = 0; i < PWRDM_MAX_CLKDMS && !ret; i++)
367 ret = (*fn)(pwrdm, pwrdm->pwrdm_clkdms[i]);
368
369 read_unlock_irqrestore(&pwrdm_rwlock, flags);
370
371 return ret;
372}
373
374
375/**
376 * pwrdm_add_wkdep - add a wakeup dependency from pwrdm2 to pwrdm1
377 * @pwrdm1: wake this struct powerdomain * up (dependent)
378 * @pwrdm2: when this struct powerdomain * wakes up (source)
379 *
380 * When the powerdomain represented by pwrdm2 wakes up (due to an
381 * interrupt), wake up pwrdm1. Implemented in hardware on the OMAP,
382 * this feature is designed to reduce wakeup latency of the dependent
383 * powerdomain. Returns -EINVAL if presented with invalid powerdomain
384 * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
385 * 0 upon success.
386 */
387int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
388{
389 struct powerdomain *p;
390
391 if (!pwrdm1)
392 return -EINVAL;
393
394 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
395 if (IS_ERR(p)) {
396 pr_debug("powerdomain: hardware cannot set/clear wake up of "
397 "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
398 return IS_ERR(p);
399 }
400
401 pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n",
402 pwrdm1->name, pwrdm2->name);
403
404 prm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
405 pwrdm1->prcm_offs, PM_WKDEP);
406
407 return 0;
408}
409
410/**
411 * pwrdm_del_wkdep - remove a wakeup dependency from pwrdm2 to pwrdm1
412 * @pwrdm1: wake this struct powerdomain * up (dependent)
413 * @pwrdm2: when this struct powerdomain * wakes up (source)
414 *
415 * Remove a wakeup dependency that causes pwrdm1 to wake up when pwrdm2
416 * wakes up. Returns -EINVAL if presented with invalid powerdomain
417 * pointers, -ENOENT if pwrdm2 cannot wake up pwrdm1 in hardware, or
418 * 0 upon success.
419 */
420int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
421{
422 struct powerdomain *p;
423
424 if (!pwrdm1)
425 return -EINVAL;
426
427 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
428 if (IS_ERR(p)) {
429 pr_debug("powerdomain: hardware cannot set/clear wake up of "
430 "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
431 return IS_ERR(p);
432 }
433
434 pr_debug("powerdomain: hardware will no longer wake up %s after %s "
435 "wakes up\n", pwrdm1->name, pwrdm2->name);
436
437 prm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
438 pwrdm1->prcm_offs, PM_WKDEP);
439
440 return 0;
441}
442
443/**
444 * pwrdm_read_wkdep - read wakeup dependency state from pwrdm2 to pwrdm1
445 * @pwrdm1: wake this struct powerdomain * up (dependent)
446 * @pwrdm2: when this struct powerdomain * wakes up (source)
447 *
448 * Return 1 if a hardware wakeup dependency exists wherein pwrdm1 will be
449 * awoken when pwrdm2 wakes up; 0 if dependency is not set; -EINVAL
450 * if either powerdomain pointer is invalid; or -ENOENT if the hardware
451 * is incapable.
452 *
453 * REVISIT: Currently this function only represents software-controllable
454 * wakeup dependencies. Wakeup dependencies fixed in hardware are not
455 * yet handled here.
456 */
457int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
458{
459 struct powerdomain *p;
460
461 if (!pwrdm1)
462 return -EINVAL;
463
464 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->wkdep_srcs);
465 if (IS_ERR(p)) {
466 pr_debug("powerdomain: hardware cannot set/clear wake up of "
467 "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
468 return IS_ERR(p);
469 }
470
471 return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP,
472 (1 << pwrdm2->dep_bit));
473}
474
475/**
476 * pwrdm_add_sleepdep - add a sleep dependency from pwrdm2 to pwrdm1
477 * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
478 * @pwrdm2: when this struct powerdomain * is active (source)
479 *
480 * Prevent pwrdm1 from automatically going inactive (and then to
481 * retention or off) if pwrdm2 is still active. Returns -EINVAL if
482 * presented with invalid powerdomain pointers or called on a machine
483 * that does not support software-configurable hardware sleep dependencies,
484 * -ENOENT if the specified dependency cannot be set in hardware, or
485 * 0 upon success.
486 */
487int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
488{
489 struct powerdomain *p;
490
491 if (!pwrdm1)
492 return -EINVAL;
493
494 if (!cpu_is_omap34xx())
495 return -EINVAL;
496
497 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
498 if (IS_ERR(p)) {
499 pr_debug("powerdomain: hardware cannot set/clear sleep "
500 "dependency affecting %s from %s\n", pwrdm1->name,
501 pwrdm2->name);
502 return IS_ERR(p);
503 }
504
505 pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n",
506 pwrdm1->name, pwrdm2->name);
507
508 cm_set_mod_reg_bits((1 << pwrdm2->dep_bit),
509 pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
510
511 return 0;
512}
513
514/**
515 * pwrdm_del_sleepdep - remove a sleep dependency from pwrdm2 to pwrdm1
516 * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
517 * @pwrdm2: when this struct powerdomain * is active (source)
518 *
519 * Allow pwrdm1 to automatically go inactive (and then to retention or
520 * off), independent of the activity state of pwrdm2. Returns -EINVAL
521 * if presented with invalid powerdomain pointers or called on a machine
522 * that does not support software-configurable hardware sleep dependencies,
523 * -ENOENT if the specified dependency cannot be cleared in hardware, or
524 * 0 upon success.
525 */
526int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
527{
528 struct powerdomain *p;
529
530 if (!pwrdm1)
531 return -EINVAL;
532
533 if (!cpu_is_omap34xx())
534 return -EINVAL;
535
536 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
537 if (IS_ERR(p)) {
538 pr_debug("powerdomain: hardware cannot set/clear sleep "
539 "dependency affecting %s from %s\n", pwrdm1->name,
540 pwrdm2->name);
541 return IS_ERR(p);
542 }
543
544 pr_debug("powerdomain: will no longer prevent %s from sleeping if "
545 "%s is active\n", pwrdm1->name, pwrdm2->name);
546
547 cm_clear_mod_reg_bits((1 << pwrdm2->dep_bit),
548 pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP);
549
550 return 0;
551}
552
553/**
554 * pwrdm_read_sleepdep - read sleep dependency state from pwrdm2 to pwrdm1
555 * @pwrdm1: prevent this struct powerdomain * from sleeping (dependent)
556 * @pwrdm2: when this struct powerdomain * is active (source)
557 *
558 * Return 1 if a hardware sleep dependency exists wherein pwrdm1 will
559 * not be allowed to automatically go inactive if pwrdm2 is active;
560 * 0 if pwrdm1's automatic power state inactivity transition is independent
561 * of pwrdm2's; -EINVAL if either powerdomain pointer is invalid or called
562 * on a machine that does not support software-configurable hardware sleep
563 * dependencies; or -ENOENT if the hardware is incapable.
564 *
565 * REVISIT: Currently this function only represents software-controllable
566 * sleep dependencies. Sleep dependencies fixed in hardware are not
567 * yet handled here.
568 */
569int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
570{
571 struct powerdomain *p;
572
573 if (!pwrdm1)
574 return -EINVAL;
575
576 if (!cpu_is_omap34xx())
577 return -EINVAL;
578
579 p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
580 if (IS_ERR(p)) {
581 pr_debug("powerdomain: hardware cannot set/clear sleep "
582 "dependency affecting %s from %s\n", pwrdm1->name,
583 pwrdm2->name);
584 return IS_ERR(p);
585 }
586
587 return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP,
588 (1 << pwrdm2->dep_bit));
589}
590
591/**
592 * pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
593 * @pwrdm: struct powerdomain *
594 *
595 * Return the number of controllable memory banks in powerdomain pwrdm,
596 * starting with 1. Returns -EINVAL if the powerdomain pointer is null.
597 */
598int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
599{
600 if (!pwrdm)
601 return -EINVAL;
602
603 return pwrdm->banks;
604}
605
606/**
607 * pwrdm_set_next_pwrst - set next powerdomain power state
608 * @pwrdm: struct powerdomain * to set
609 * @pwrst: one of the PWRDM_POWER_* macros
610 *
611 * Set the powerdomain pwrdm's next power state to pwrst. The powerdomain
612 * may not enter this state immediately if the preconditions for this state
613 * have not been satisfied. Returns -EINVAL if the powerdomain pointer is
614 * null or if the power state is invalid for the powerdomin, or returns 0
615 * upon success.
616 */
617int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
618{
619 if (!pwrdm)
620 return -EINVAL;
621
622 if (!(pwrdm->pwrsts & (1 << pwrst)))
623 return -EINVAL;
624
625 pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
626 pwrdm->name, pwrst);
627
628 prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
629 (pwrst << OMAP_POWERSTATE_SHIFT),
630 pwrdm->prcm_offs, PM_PWSTCTRL);
631
632 return 0;
633}
634
635/**
636 * pwrdm_read_next_pwrst - get next powerdomain power state
637 * @pwrdm: struct powerdomain * to get power state
638 *
639 * Return the powerdomain pwrdm's next power state. Returns -EINVAL
640 * if the powerdomain pointer is null or returns the next power state
641 * upon success.
642 */
643int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
644{
645 if (!pwrdm)
646 return -EINVAL;
647
648 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL,
649 OMAP_POWERSTATE_MASK);
650}
651
652/**
653 * pwrdm_read_pwrst - get current powerdomain power state
654 * @pwrdm: struct powerdomain * to get power state
655 *
656 * Return the powerdomain pwrdm's current power state. Returns -EINVAL
657 * if the powerdomain pointer is null or returns the current power state
658 * upon success.
659 */
660int pwrdm_read_pwrst(struct powerdomain *pwrdm)
661{
662 if (!pwrdm)
663 return -EINVAL;
664
665 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
666 OMAP_POWERSTATEST_MASK);
667}
668
669/**
670 * pwrdm_read_prev_pwrst - get previous powerdomain power state
671 * @pwrdm: struct powerdomain * to get previous power state
672 *
673 * Return the powerdomain pwrdm's previous power state. Returns -EINVAL
674 * if the powerdomain pointer is null or returns the previous power state
675 * upon success.
676 */
677int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
678{
679 if (!pwrdm)
680 return -EINVAL;
681
682 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
683 OMAP3430_LASTPOWERSTATEENTERED_MASK);
684}
685
686/**
687 * pwrdm_set_logic_retst - set powerdomain logic power state upon retention
688 * @pwrdm: struct powerdomain * to set
689 * @pwrst: one of the PWRDM_POWER_* macros
690 *
691 * Set the next power state that the logic portion of the powerdomain
692 * pwrdm will enter when the powerdomain enters retention. This will
693 * be either RETENTION or OFF, if supported. Returns -EINVAL if the
694 * powerdomain pointer is null or the target power state is not not
695 * supported, or returns 0 upon success.
696 */
697int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
698{
699 if (!pwrdm)
700 return -EINVAL;
701
702 if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
703 return -EINVAL;
704
705 pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
706 pwrdm->name, pwrst);
707
708 /*
709 * The register bit names below may not correspond to the
710 * actual names of the bits in each powerdomain's register,
711 * but the type of value returned is the same for each
712 * powerdomain.
713 */
714 prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE,
715 (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)),
716 pwrdm->prcm_offs, PM_PWSTCTRL);
717
718 return 0;
719}
720
721/**
722 * pwrdm_set_mem_onst - set memory power state while powerdomain ON
723 * @pwrdm: struct powerdomain * to set
724 * @bank: memory bank number to set (0-3)
725 * @pwrst: one of the PWRDM_POWER_* macros
726 *
727 * Set the next power state that memory bank x of the powerdomain
728 * pwrdm will enter when the powerdomain enters the ON state. Bank
729 * will be a number from 0 to 3, and represents different types of
730 * memory, depending on the powerdomain. Returns -EINVAL if the
731 * powerdomain pointer is null or the target power state is not not
732 * supported for this memory bank, -EEXIST if the target memory bank
733 * does not exist or is not controllable, or returns 0 upon success.
734 */
735int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
736{
737 u32 m;
738
739 if (!pwrdm)
740 return -EINVAL;
741
742 if (pwrdm->banks < (bank + 1))
743 return -EEXIST;
744
745 if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
746 return -EINVAL;
747
748 pr_debug("powerdomain: setting next memory powerstate for domain %s "
749 "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
750
751 /*
752 * The register bit names below may not correspond to the
753 * actual names of the bits in each powerdomain's register,
754 * but the type of value returned is the same for each
755 * powerdomain.
756 */
757 switch (bank) {
758 case 0:
759 m = OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK;
760 break;
761 case 1:
762 m = OMAP3430_L1FLATMEMONSTATE_MASK;
763 break;
764 case 2:
765 m = OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK;
766 break;
767 case 3:
768 m = OMAP3430_L2FLATMEMONSTATE_MASK;
769 break;
770 default:
771 WARN_ON(1); /* should never happen */
772 return -EEXIST;
773 }
774
775 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),
776 pwrdm->prcm_offs, PM_PWSTCTRL);
777
778 return 0;
779}
780
781/**
782 * pwrdm_set_mem_retst - set memory power state while powerdomain in RET
783 * @pwrdm: struct powerdomain * to set
784 * @bank: memory bank number to set (0-3)
785 * @pwrst: one of the PWRDM_POWER_* macros
786 *
787 * Set the next power state that memory bank x of the powerdomain
788 * pwrdm will enter when the powerdomain enters the RETENTION state.
789 * Bank will be a number from 0 to 3, and represents different types
790 * of memory, depending on the powerdomain. pwrst will be either
791 * RETENTION or OFF, if supported. Returns -EINVAL if the powerdomain
792 * pointer is null or the target power state is not not supported for
793 * this memory bank, -EEXIST if the target memory bank does not exist
794 * or is not controllable, or returns 0 upon success.
795 */
796int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
797{
798 u32 m;
799
800 if (!pwrdm)
801 return -EINVAL;
802
803 if (pwrdm->banks < (bank + 1))
804 return -EEXIST;
805
806 if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
807 return -EINVAL;
808
809 pr_debug("powerdomain: setting next memory powerstate for domain %s "
810 "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
811
812 /*
813 * The register bit names below may not correspond to the
814 * actual names of the bits in each powerdomain's register,
815 * but the type of value returned is the same for each
816 * powerdomain.
817 */
818 switch (bank) {
819 case 0:
820 m = OMAP3430_SHAREDL1CACHEFLATRETSTATE;
821 break;
822 case 1:
823 m = OMAP3430_L1FLATMEMRETSTATE;
824 break;
825 case 2:
826 m = OMAP3430_SHAREDL2CACHEFLATRETSTATE;
827 break;
828 case 3:
829 m = OMAP3430_L2FLATMEMRETSTATE;
830 break;
831 default:
832 WARN_ON(1); /* should never happen */
833 return -EEXIST;
834 }
835
836 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
837 PM_PWSTCTRL);
838
839 return 0;
840}
841
842/**
843 * pwrdm_read_logic_pwrst - get current powerdomain logic retention power state
844 * @pwrdm: struct powerdomain * to get current logic retention power state
845 *
846 * Return the current power state that the logic portion of
847 * powerdomain pwrdm will enter
848 * Returns -EINVAL if the powerdomain pointer is null or returns the
849 * current logic retention power state upon success.
850 */
851int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
852{
853 if (!pwrdm)
854 return -EINVAL;
855
856 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST,
857 OMAP3430_LOGICSTATEST);
858}
859
860/**
861 * pwrdm_read_prev_logic_pwrst - get previous powerdomain logic power state
862 * @pwrdm: struct powerdomain * to get previous logic power state
863 *
864 * Return the powerdomain pwrdm's logic power state. Returns -EINVAL
865 * if the powerdomain pointer is null or returns the previous logic
866 * power state upon success.
867 */
868int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
869{
870 if (!pwrdm)
871 return -EINVAL;
872
873 /*
874 * The register bit names below may not correspond to the
875 * actual names of the bits in each powerdomain's register,
876 * but the type of value returned is the same for each
877 * powerdomain.
878 */
879 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
880 OMAP3430_LASTLOGICSTATEENTERED);
881}
882
883/**
884 * pwrdm_read_mem_pwrst - get current memory bank power state
885 * @pwrdm: struct powerdomain * to get current memory bank power state
886 * @bank: memory bank number (0-3)
887 *
888 * Return the powerdomain pwrdm's current memory power state for bank
889 * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
890 * the target memory bank does not exist or is not controllable, or
891 * returns the current memory power state upon success.
892 */
893int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
894{
895 u32 m;
896
897 if (!pwrdm)
898 return -EINVAL;
899
900 if (pwrdm->banks < (bank + 1))
901 return -EEXIST;
902
903 /*
904 * The register bit names below may not correspond to the
905 * actual names of the bits in each powerdomain's register,
906 * but the type of value returned is the same for each
907 * powerdomain.
908 */
909 switch (bank) {
910 case 0:
911 m = OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK;
912 break;
913 case 1:
914 m = OMAP3430_L1FLATMEMSTATEST_MASK;
915 break;
916 case 2:
917 m = OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK;
918 break;
919 case 3:
920 m = OMAP3430_L2FLATMEMSTATEST_MASK;
921 break;
922 default:
923 WARN_ON(1); /* should never happen */
924 return -EEXIST;
925 }
926
927 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m);
928}
929
930/**
931 * pwrdm_read_prev_mem_pwrst - get previous memory bank power state
932 * @pwrdm: struct powerdomain * to get previous memory bank power state
933 * @bank: memory bank number (0-3)
934 *
935 * Return the powerdomain pwrdm's previous memory power state for bank
936 * x. Returns -EINVAL if the powerdomain pointer is null, -EEXIST if
937 * the target memory bank does not exist or is not controllable, or
938 * returns the previous memory power state upon success.
939 */
940int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
941{
942 u32 m;
943
944 if (!pwrdm)
945 return -EINVAL;
946
947 if (pwrdm->banks < (bank + 1))
948 return -EEXIST;
949
950 /*
951 * The register bit names below may not correspond to the
952 * actual names of the bits in each powerdomain's register,
953 * but the type of value returned is the same for each
954 * powerdomain.
955 */
956 switch (bank) {
957 case 0:
958 m = OMAP3430_LASTMEM1STATEENTERED_MASK;
959 break;
960 case 1:
961 m = OMAP3430_LASTMEM2STATEENTERED_MASK;
962 break;
963 case 2:
964 m = OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
965 break;
966 case 3:
967 m = OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
968 break;
969 default:
970 WARN_ON(1); /* should never happen */
971 return -EEXIST;
972 }
973
974 return prm_read_mod_bits_shift(pwrdm->prcm_offs,
975 OMAP3430_PM_PREPWSTST, m);
976}
977
978/**
979 * pwrdm_clear_all_prev_pwrst - clear previous powerstate register for a pwrdm
980 * @pwrdm: struct powerdomain * to clear
981 *
982 * Clear the powerdomain's previous power state register. Clears the
983 * entire register, including logic and memory bank previous power states.
984 * Returns -EINVAL if the powerdomain pointer is null, or returns 0 upon
985 * success.
986 */
987int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
988{
989 if (!pwrdm)
990 return -EINVAL;
991
992 /*
993 * XXX should get the powerdomain's current state here;
994 * warn & fail if it is not ON.
995 */
996
997 pr_debug("powerdomain: clearing previous power state reg for %s\n",
998 pwrdm->name);
999
1000 prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
1001
1002 return 0;
1003}
1004
1005/**
1006 * pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm
1007 * @pwrdm: struct powerdomain *
1008 *
1009 * Enable automatic context save-and-restore upon power state change
1010 * for some devices in a powerdomain. Warning: this only affects a
1011 * subset of devices in a powerdomain; check the TRM closely. Returns
1012 * -EINVAL if the powerdomain pointer is null or if the powerdomain
1013 * does not support automatic save-and-restore, or returns 0 upon
1014 * success.
1015 */
1016int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
1017{
1018 if (!pwrdm)
1019 return -EINVAL;
1020
1021 if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
1022 return -EINVAL;
1023
1024 pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
1025 pwrdm->name);
1026
1027 prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
1028 pwrdm->prcm_offs, PM_PWSTCTRL);
1029
1030 return 0;
1031}
1032
1033/**
1034 * pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm
1035 * @pwrdm: struct powerdomain *
1036 *
1037 * Disable automatic context save-and-restore upon power state change
1038 * for some devices in a powerdomain. Warning: this only affects a
1039 * subset of devices in a powerdomain; check the TRM closely. Returns
1040 * -EINVAL if the powerdomain pointer is null or if the powerdomain
1041 * does not support automatic save-and-restore, or returns 0 upon
1042 * success.
1043 */
1044int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
1045{
1046 if (!pwrdm)
1047 return -EINVAL;
1048
1049 if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
1050 return -EINVAL;
1051
1052 pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
1053 pwrdm->name);
1054
1055 prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
1056 pwrdm->prcm_offs, PM_PWSTCTRL);
1057
1058 return 0;
1059}
1060
1061/**
1062 * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR
1063 * @pwrdm: struct powerdomain *
1064 *
1065 * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore
1066 * for some devices, or 0 if it does not.
1067 */
1068bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
1069{
1070 return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
1071}
1072
1073/**
1074 * pwrdm_wait_transition - wait for powerdomain power transition to finish
1075 * @pwrdm: struct powerdomain * to wait for
1076 *
1077 * If the powerdomain pwrdm is in the process of a state transition,
1078 * spin until it completes the power transition, or until an iteration
1079 * bailout value is reached. Returns -EINVAL if the powerdomain
1080 * pointer is null, -EAGAIN if the bailout value was reached, or
1081 * returns 0 upon success.
1082 */
1083int pwrdm_wait_transition(struct powerdomain *pwrdm)
1084{
1085 u32 c = 0;
1086
1087 if (!pwrdm)
1088 return -EINVAL;
1089
1090 /*
1091 * REVISIT: pwrdm_wait_transition() may be better implemented
1092 * via a callback and a periodic timer check -- how long do we expect
1093 * powerdomain transitions to take?
1094 */
1095
1096 /* XXX Is this udelay() value meaningful? */
1097 while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) &
1098 OMAP_INTRANSITION) &&
1099 (c++ < PWRDM_TRANSITION_BAILOUT))
1100 udelay(1);
1101
1102 if (c >= PWRDM_TRANSITION_BAILOUT) {
1103 printk(KERN_ERR "powerdomain: waited too long for "
1104 "powerdomain %s to complete transition\n", pwrdm->name);
1105 return -EAGAIN;
1106 }
1107
1108 pr_debug("powerdomain: completed transition in %d loops\n", c);
1109
1110 return 0;
1111}
1112
1113
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
new file mode 100644
index 000000000000..1e151faebbd3
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -0,0 +1,187 @@
1/*
2 * OMAP2/3 common powerdomain definitions
3 *
4 * Copyright (C) 2007-8 Texas Instruments, Inc.
5 * Copyright (C) 2007-8 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
16#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
17
18/*
19 * This file contains all of the powerdomains that have some element
20 * of software control for the OMAP24xx and OMAP34XX chips.
21 *
22 * A few notes:
23 *
24 * This is not an exhaustive listing of powerdomains on the chips; only
25 * powerdomains that can be controlled in software.
26 *
27 * A useful validation rule for struct powerdomain:
28 * Any powerdomain referenced by a wkdep_srcs or sleepdep_srcs array
29 * must have a dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really
30 * just software-controllable dependencies. Non-software-controllable
31 * dependencies do exist, but they are not encoded below (yet).
32 *
33 * 24xx does not support programmable sleep dependencies (SLEEPDEP)
34 *
35 */
36
37/*
38 * The names for the DSP/IVA2 powerdomains are confusing.
39 *
40 * Most OMAP chips have an on-board DSP.
41 *
42 * On the 2420, this is a 'C55 DSP called, simply, the DSP. Its
43 * powerdomain is called the "DSP power domain." On the 2430, the
44 * on-board DSP is a 'C64 DSP, now called the IVA2 or IVA2.1. Its
45 * powerdomain is still called the "DSP power domain." On the 3430,
46 * the DSP is a 'C64 DSP like the 2430, also known as the IVA2; but
47 * its powerdomain is now called the "IVA2 power domain."
48 *
49 * The 2420 also has something called the IVA, which is a separate ARM
50 * core, and has nothing to do with the DSP/IVA2.
51 *
52 * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM
53 * address offset is different between the C55 and C64 DSPs.
54 *
55 * The overly-specific dep_bit names are due to a bit name collision
56 * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
57 * value are the same for all powerdomains: 2
58 */
59
60/*
61 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
62 * sanity check?
63 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
64 */
65
66#include <mach/powerdomain.h>
67
68#include "prcm-common.h"
69#include "prm.h"
70#include "cm.h"
71
72/* OMAP2/3-common powerdomains and wakeup dependencies */
73
74/*
75 * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
76 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
77 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
78 */
79static struct pwrdm_dep gfx_sgx_wkdeps[] = {
80 {
81 .pwrdm_name = "core_pwrdm",
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
83 },
84 {
85 .pwrdm_name = "iva2_pwrdm",
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
87 },
88 {
89 .pwrdm_name = "mpu_pwrdm",
90 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
91 CHIP_IS_OMAP3430)
92 },
93 {
94 .pwrdm_name = "wkup_pwrdm",
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
96 CHIP_IS_OMAP3430)
97 },
98 { NULL },
99};
100
101/*
102 * 3430: CM_SLEEPDEP_CAM: MPU
103 * 3430ES1: CM_SLEEPDEP_GFX: MPU
104 * 3430ES2: CM_SLEEPDEP_SGX: MPU
105 */
106static struct pwrdm_dep cam_gfx_sleepdeps[] = {
107 {
108 .pwrdm_name = "mpu_pwrdm",
109 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
110 },
111 { NULL },
112};
113
114
115#include "powerdomains24xx.h"
116#include "powerdomains34xx.h"
117
118
119/*
120 * OMAP2/3 common powerdomains
121 */
122
123/*
124 * The GFX powerdomain is not present on 3430ES2, but currently we do not
125 * have a macro to filter it out at compile-time.
126 */
127static struct powerdomain gfx_pwrdm = {
128 .name = "gfx_pwrdm",
129 .prcm_offs = GFX_MOD,
130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
131 CHIP_IS_OMAP3430ES1),
132 .wkdep_srcs = gfx_sgx_wkdeps,
133 .sleepdep_srcs = cam_gfx_sleepdeps,
134 .pwrsts = PWRSTS_OFF_RET_ON,
135 .pwrsts_logic_ret = PWRDM_POWER_RET,
136 .banks = 1,
137 .pwrsts_mem_ret = {
138 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
139 },
140 .pwrsts_mem_on = {
141 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
142 },
143};
144
145static struct powerdomain wkup_pwrdm = {
146 .name = "wkup_pwrdm",
147 .prcm_offs = WKUP_MOD,
148 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
149 .dep_bit = OMAP_EN_WKUP_SHIFT,
150};
151
152
153
154/* As powerdomains are added or removed above, this list must also be changed */
155static struct powerdomain *powerdomains_omap[] __initdata = {
156
157 &gfx_pwrdm,
158 &wkup_pwrdm,
159
160#ifdef CONFIG_ARCH_OMAP24XX
161 &dsp_pwrdm,
162 &mpu_24xx_pwrdm,
163 &core_24xx_pwrdm,
164#endif
165
166#ifdef CONFIG_ARCH_OMAP2430
167 &mdm_pwrdm,
168#endif
169
170#ifdef CONFIG_ARCH_OMAP34XX
171 &iva2_pwrdm,
172 &mpu_34xx_pwrdm,
173 &neon_pwrdm,
174 &core_34xx_pwrdm,
175 &cam_pwrdm,
176 &dss_pwrdm,
177 &per_pwrdm,
178 &emu_pwrdm,
179 &sgx_pwrdm,
180 &usbhost_pwrdm,
181#endif
182
183 NULL
184};
185
186
187#endif
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h
new file mode 100644
index 000000000000..9f08dc3f7fd2
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains24xx.h
@@ -0,0 +1,200 @@
1/*
2 * OMAP24XX powerdomain definitions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
16#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
17
18/*
19 * N.B. If powerdomains are added or removed from this file, update
20 * the array in mach-omap2/powerdomains.h.
21 */
22
23#include <mach/powerdomain.h>
24
25#include "prcm-common.h"
26#include "prm.h"
27#include "prm-regbits-24xx.h"
28#include "cm.h"
29#include "cm-regbits-24xx.h"
30
31/* 24XX powerdomains and dependencies */
32
33#ifdef CONFIG_ARCH_OMAP24XX
34
35
36/* Wakeup dependency source arrays */
37
38/*
39 * 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP
40 * 2430 PM_WKDEP_MDM: same as above
41 */
42static struct pwrdm_dep dsp_mdm_24xx_wkdeps[] = {
43 {
44 .pwrdm_name = "core_pwrdm",
45 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
46 },
47 {
48 .pwrdm_name = "mpu_pwrdm",
49 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
50 },
51 {
52 .pwrdm_name = "wkup_pwrdm",
53 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
54 },
55 { NULL },
56};
57
58/*
59 * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
60 * 2430 adds MDM
61 */
62static struct pwrdm_dep mpu_24xx_wkdeps[] = {
63 {
64 .pwrdm_name = "core_pwrdm",
65 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
66 },
67 {
68 .pwrdm_name = "dsp_pwrdm",
69 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
70 },
71 {
72 .pwrdm_name = "wkup_pwrdm",
73 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
74 },
75 {
76 .pwrdm_name = "mdm_pwrdm",
77 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
78 },
79 { NULL },
80};
81
82/*
83 * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
84 * 2430 adds MDM
85 */
86static struct pwrdm_dep core_24xx_wkdeps[] = {
87 {
88 .pwrdm_name = "dsp_pwrdm",
89 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
90 },
91 {
92 .pwrdm_name = "gfx_pwrdm",
93 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
94 },
95 {
96 .pwrdm_name = "mpu_pwrdm",
97 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
98 },
99 {
100 .pwrdm_name = "wkup_pwrdm",
101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
102 },
103 {
104 .pwrdm_name = "mdm_pwrdm",
105 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
106 },
107 { NULL },
108};
109
110
111/* Powerdomains */
112
113static struct powerdomain dsp_pwrdm = {
114 .name = "dsp_pwrdm",
115 .prcm_offs = OMAP24XX_DSP_MOD,
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
117 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
118 .wkdep_srcs = dsp_mdm_24xx_wkdeps,
119 .pwrsts = PWRSTS_OFF_RET_ON,
120 .pwrsts_logic_ret = PWRDM_POWER_RET,
121 .banks = 1,
122 .pwrsts_mem_ret = {
123 [0] = PWRDM_POWER_RET,
124 },
125 .pwrsts_mem_on = {
126 [0] = PWRDM_POWER_ON,
127 },
128};
129
130static struct powerdomain mpu_24xx_pwrdm = {
131 .name = "mpu_pwrdm",
132 .prcm_offs = MPU_MOD,
133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
134 .dep_bit = OMAP24XX_EN_MPU_SHIFT,
135 .wkdep_srcs = mpu_24xx_wkdeps,
136 .pwrsts = PWRSTS_OFF_RET_ON,
137 .pwrsts_logic_ret = PWRSTS_OFF_RET,
138 .banks = 1,
139 .pwrsts_mem_ret = {
140 [0] = PWRDM_POWER_RET,
141 },
142 .pwrsts_mem_on = {
143 [0] = PWRDM_POWER_ON,
144 },
145};
146
147static struct powerdomain core_24xx_pwrdm = {
148 .name = "core_pwrdm",
149 .prcm_offs = CORE_MOD,
150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
151 .wkdep_srcs = core_24xx_wkdeps,
152 .pwrsts = PWRSTS_OFF_RET_ON,
153 .dep_bit = OMAP24XX_EN_CORE_SHIFT,
154 .banks = 3,
155 .pwrsts_mem_ret = {
156 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
157 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
158 [2] = PWRSTS_OFF_RET, /* MEM3RETSTATE */
159 },
160 .pwrsts_mem_on = {
161 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
162 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
163 [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
164 },
165};
166
167#endif /* CONFIG_ARCH_OMAP24XX */
168
169
170
171/*
172 * 2430-specific powerdomains
173 */
174
175#ifdef CONFIG_ARCH_OMAP2430
176
177/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
178
179/* Another case of bit name collisions between several registers: EN_MDM */
180static struct powerdomain mdm_pwrdm = {
181 .name = "mdm_pwrdm",
182 .prcm_offs = OMAP2430_MDM_MOD,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
184 .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
185 .wkdep_srcs = dsp_mdm_24xx_wkdeps,
186 .pwrsts = PWRSTS_OFF_RET_ON,
187 .pwrsts_logic_ret = PWRDM_POWER_RET,
188 .banks = 1,
189 .pwrsts_mem_ret = {
190 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
191 },
192 .pwrsts_mem_on = {
193 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
194 },
195};
196
197#endif /* CONFIG_ARCH_OMAP2430 */
198
199
200#endif
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
new file mode 100644
index 000000000000..f573f7108398
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -0,0 +1,327 @@
1/*
2 * OMAP34XX powerdomain definitions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
16#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
17
18/*
19 * N.B. If powerdomains are added or removed from this file, update
20 * the array in mach-omap2/powerdomains.h.
21 */
22
23#include <mach/powerdomain.h>
24
25#include "prcm-common.h"
26#include "prm.h"
27#include "prm-regbits-34xx.h"
28#include "cm.h"
29#include "cm-regbits-34xx.h"
30
31/*
32 * 34XX-specific powerdomains, dependencies
33 */
34
35#ifdef CONFIG_ARCH_OMAP34XX
36
37/*
38 * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
39 * (USBHOST is ES2 only)
40 */
41static struct pwrdm_dep per_usbhost_wkdeps[] = {
42 {
43 .pwrdm_name = "core_pwrdm",
44 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
45 },
46 {
47 .pwrdm_name = "iva2_pwrdm",
48 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
49 },
50 {
51 .pwrdm_name = "mpu_pwrdm",
52 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
53 },
54 {
55 .pwrdm_name = "wkup_pwrdm",
56 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
57 },
58 { NULL },
59};
60
61/*
62 * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
63 */
64static struct pwrdm_dep mpu_34xx_wkdeps[] = {
65 {
66 .pwrdm_name = "core_pwrdm",
67 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
68 },
69 {
70 .pwrdm_name = "iva2_pwrdm",
71 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
72 },
73 {
74 .pwrdm_name = "dss_pwrdm",
75 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
76 },
77 {
78 .pwrdm_name = "per_pwrdm",
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
80 },
81 { NULL },
82};
83
84/*
85 * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
86 */
87static struct pwrdm_dep iva2_wkdeps[] = {
88 {
89 .pwrdm_name = "core_pwrdm",
90 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
91 },
92 {
93 .pwrdm_name = "mpu_pwrdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
95 },
96 {
97 .pwrdm_name = "wkup_pwrdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
99 },
100 {
101 .pwrdm_name = "dss_pwrdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
103 },
104 {
105 .pwrdm_name = "per_pwrdm",
106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
107 },
108 { NULL },
109};
110
111
112/* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
113static struct pwrdm_dep cam_dss_wkdeps[] = {
114 {
115 .pwrdm_name = "iva2_pwrdm",
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
117 },
118 {
119 .pwrdm_name = "mpu_pwrdm",
120 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
121 },
122 {
123 .pwrdm_name = "wkup_pwrdm",
124 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
125 },
126 { NULL },
127};
128
129/* 3430: PM_WKDEP_NEON: MPU */
130static struct pwrdm_dep neon_wkdeps[] = {
131 {
132 .pwrdm_name = "mpu_pwrdm",
133 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
134 },
135 { NULL },
136};
137
138
139/* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
140
141/*
142 * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
143 * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
144 */
145static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
146 {
147 .pwrdm_name = "mpu_pwrdm",
148 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
149 },
150 {
151 .pwrdm_name = "iva2_pwrdm",
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
153 },
154 { NULL },
155};
156
157
158/*
159 * Powerdomains
160 */
161
162static struct powerdomain iva2_pwrdm = {
163 .name = "iva2_pwrdm",
164 .prcm_offs = OMAP3430_IVA2_MOD,
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
166 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
167 .wkdep_srcs = iva2_wkdeps,
168 .pwrsts = PWRSTS_OFF_RET_ON,
169 .pwrsts_logic_ret = PWRSTS_OFF_RET,
170 .banks = 4,
171 .pwrsts_mem_ret = {
172 [0] = PWRSTS_OFF_RET,
173 [1] = PWRSTS_OFF_RET,
174 [2] = PWRSTS_OFF_RET,
175 [3] = PWRSTS_OFF_RET,
176 },
177 .pwrsts_mem_on = {
178 [0] = PWRDM_POWER_ON,
179 [1] = PWRDM_POWER_ON,
180 [2] = PWRSTS_OFF_ON,
181 [3] = PWRDM_POWER_ON,
182 },
183};
184
185static struct powerdomain mpu_34xx_pwrdm = {
186 .name = "mpu_pwrdm",
187 .prcm_offs = MPU_MOD,
188 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
189 .dep_bit = OMAP3430_EN_MPU_SHIFT,
190 .wkdep_srcs = mpu_34xx_wkdeps,
191 .pwrsts = PWRSTS_OFF_RET_ON,
192 .pwrsts_logic_ret = PWRSTS_OFF_RET,
193 .banks = 1,
194 .pwrsts_mem_ret = {
195 [0] = PWRSTS_OFF_RET,
196 },
197 .pwrsts_mem_on = {
198 [0] = PWRSTS_OFF_ON,
199 },
200};
201
202/* No wkdeps or sleepdeps for 34xx core apparently */
203static struct powerdomain core_34xx_pwrdm = {
204 .name = "core_pwrdm",
205 .prcm_offs = CORE_MOD,
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
207 .pwrsts = PWRSTS_OFF_RET_ON,
208 .dep_bit = OMAP3430_EN_CORE_SHIFT,
209 .banks = 2,
210 .pwrsts_mem_ret = {
211 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
212 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
213 },
214 .pwrsts_mem_on = {
215 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
216 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
217 },
218};
219
220/* Another case of bit name collisions between several registers: EN_DSS */
221static struct powerdomain dss_pwrdm = {
222 .name = "dss_pwrdm",
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
224 .prcm_offs = OMAP3430_DSS_MOD,
225 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
226 .wkdep_srcs = cam_dss_wkdeps,
227 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
228 .pwrsts = PWRSTS_OFF_RET_ON,
229 .pwrsts_logic_ret = PWRDM_POWER_RET,
230 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
233 },
234 .pwrsts_mem_on = {
235 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
236 },
237};
238
239static struct powerdomain sgx_pwrdm = {
240 .name = "sgx_pwrdm",
241 .prcm_offs = OMAP3430ES2_SGX_MOD,
242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
243 .wkdep_srcs = gfx_sgx_wkdeps,
244 .sleepdep_srcs = cam_gfx_sleepdeps,
245 /* XXX This is accurate for 3430 SGX, but what about GFX? */
246 .pwrsts = PWRSTS_OFF_RET_ON,
247 .pwrsts_logic_ret = PWRDM_POWER_RET,
248 .banks = 1,
249 .pwrsts_mem_ret = {
250 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
251 },
252 .pwrsts_mem_on = {
253 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
254 },
255};
256
257static struct powerdomain cam_pwrdm = {
258 .name = "cam_pwrdm",
259 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
260 .prcm_offs = OMAP3430_CAM_MOD,
261 .wkdep_srcs = cam_dss_wkdeps,
262 .sleepdep_srcs = cam_gfx_sleepdeps,
263 .pwrsts = PWRSTS_OFF_RET_ON,
264 .pwrsts_logic_ret = PWRDM_POWER_RET,
265 .banks = 1,
266 .pwrsts_mem_ret = {
267 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
268 },
269 .pwrsts_mem_on = {
270 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
271 },
272};
273
274static struct powerdomain per_pwrdm = {
275 .name = "per_pwrdm",
276 .prcm_offs = OMAP3430_PER_MOD,
277 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
278 .dep_bit = OMAP3430_EN_PER_SHIFT,
279 .wkdep_srcs = per_usbhost_wkdeps,
280 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
281 .pwrsts = PWRSTS_OFF_RET_ON,
282 .pwrsts_logic_ret = PWRSTS_OFF_RET,
283 .banks = 1,
284 .pwrsts_mem_ret = {
285 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
286 },
287 .pwrsts_mem_on = {
288 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
289 },
290};
291
292static struct powerdomain emu_pwrdm = {
293 .name = "emu_pwrdm",
294 .prcm_offs = OMAP3430_EMU_MOD,
295 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
296};
297
298static struct powerdomain neon_pwrdm = {
299 .name = "neon_pwrdm",
300 .prcm_offs = OMAP3430_NEON_MOD,
301 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
302 .wkdep_srcs = neon_wkdeps,
303 .pwrsts = PWRSTS_OFF_RET_ON,
304 .pwrsts_logic_ret = PWRDM_POWER_RET,
305};
306
307static struct powerdomain usbhost_pwrdm = {
308 .name = "usbhost_pwrdm",
309 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
311 .wkdep_srcs = per_usbhost_wkdeps,
312 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
313 .pwrsts = PWRSTS_OFF_RET_ON,
314 .pwrsts_logic_ret = PWRDM_POWER_RET,
315 .banks = 1,
316 .pwrsts_mem_ret = {
317 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
318 },
319 .pwrsts_mem_on = {
320 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
321 },
322};
323
324#endif /* CONFIG_ARCH_OMAP34XX */
325
326
327#endif
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 54c32f482131..4a32822ff3fc 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -312,7 +312,8 @@
312#define OMAP3430_ST_GPT2 (1 << 3) 312#define OMAP3430_ST_GPT2 (1 << 3)
313 313
314/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 314/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
315#define OMAP3430_EN_CORE (1 << 0) 315#define OMAP3430_EN_CORE_SHIFT 0
316#define OMAP3430_EN_CORE_MASK (1 << 0)
316 317
317#endif 318#endif
318 319
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index c6d17a3378ec..4002051c20b9 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -29,8 +29,10 @@
29#define OMAP24XX_WKUP1_EN (1 << 0) 29#define OMAP24XX_WKUP1_EN (1 << 0)
30 30
31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ 31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
32#define OMAP24XX_EN_MPU (1 << 1) 32#define OMAP24XX_EN_MPU_SHIFT 1
33#define OMAP24XX_EN_CORE (1 << 0) 33#define OMAP24XX_EN_MPU_MASK (1 << 1)
34#define OMAP24XX_EN_CORE_SHIFT 0
35#define OMAP24XX_EN_CORE_MASK (1 << 0)
34 36
35/* 37/*
36 * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM 38 * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
@@ -140,8 +142,10 @@
140/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ 142/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
141 143
142/* PM_WKDEP_MPU specific bits */ 144/* PM_WKDEP_MPU specific bits */
143#define OMAP2430_PM_WKDEP_MPU_EN_MDM (1 << 5) 145#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
144#define OMAP24XX_PM_WKDEP_MPU_EN_DSP (1 << 2) 146#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
147#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
148#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
145 149
146/* PM_EVGENCTRL_MPU specific bits */ 150/* PM_EVGENCTRL_MPU specific bits */
147 151
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index b4686bc345ca..5b5ecfe6c999 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -68,7 +68,8 @@
68#define OMAP3430_VPINIDLE (1 << 0) 68#define OMAP3430_VPINIDLE (1 << 0)
69 69
70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ 70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71#define OMAP3430_EN_PER (1 << 7) 71#define OMAP3430_EN_PER_SHIFT 7
72#define OMAP3430_EN_PER_MASK (1 << 7)
72 73
73/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ 74/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
74#define OMAP3430_MEMORYCHANGE (1 << 3) 75#define OMAP3430_MEMORYCHANGE (1 << 3)
@@ -77,7 +78,7 @@
77#define OMAP3430_LOGICSTATEST (1 << 2) 78#define OMAP3430_LOGICSTATEST (1 << 2)
78 79
79/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ 80/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
80#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2) 81#define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
81 82
82/* 83/*
83 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, 84 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
@@ -278,8 +279,10 @@
278#define OMAP3430_EMULATION_MPU_RST (1 << 11) 279#define OMAP3430_EMULATION_MPU_RST (1 << 11)
279 280
280/* PM_WKDEP_MPU specific bits */ 281/* PM_WKDEP_MPU specific bits */
281#define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5) 282#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
282#define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2) 283#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
284#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
285#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
283 286
284/* PM_EVGENCTRL_MPU */ 287/* PM_EVGENCTRL_MPU */
285#define OMAP3430_OFFLOADMODE_SHIFT 3 288#define OMAP3430_OFFLOADMODE_SHIFT 3
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index bbf41fc8e9a9..e4dc4b17881d 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,7 +18,7 @@
18 18
19#ifndef __ASSEMBLER__ 19#ifndef __ASSEMBLER__
20#define OMAP_PRM_REGADDR(module, reg) \ 20#define OMAP_PRM_REGADDR(module, reg) \
21 (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg)) 21 IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
22#else 22#else
23#define OMAP2420_PRM_REGADDR(module, reg) \ 23#define OMAP2420_PRM_REGADDR(module, reg) \
24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) 24 IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
@@ -305,7 +305,8 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
305 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, 305 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
306 * PM_WKDEP_PER 306 * PM_WKDEP_PER
307 */ 307 */
308#define OMAP_EN_WKUP (1 << 4) 308#define OMAP_EN_WKUP_SHIFT 4
309#define OMAP_EN_WKUP_MASK (1 << 4)
309 310
310/* 311/*
311 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, 312 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 7d9444adc5df..4dcf39c285b9 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * OMAP2 serial support. 4 * OMAP2 serial support.
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com> 7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 * 8 *
9 * Based off of arch/arm/mach-omap/omap1/serial.c 9 * Based off of arch/arm/mach-omap/omap1/serial.c
@@ -22,38 +22,34 @@
22#include <mach/common.h> 22#include <mach/common.h>
23#include <mach/board.h> 23#include <mach/board.h>
24 24
25static struct clk * uart1_ick = NULL; 25static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
26static struct clk * uart1_fck = NULL; 26static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
27static struct clk * uart2_ick = NULL;
28static struct clk * uart2_fck = NULL;
29static struct clk * uart3_ick = NULL;
30static struct clk * uart3_fck = NULL;
31 27
32static struct plat_serial8250_port serial_platform_data[] = { 28static struct plat_serial8250_port serial_platform_data[] = {
33 { 29 {
34 .membase = (char *)IO_ADDRESS(OMAP_UART1_BASE), 30 .membase = IO_ADDRESS(OMAP_UART1_BASE),
35 .mapbase = (unsigned long)OMAP_UART1_BASE, 31 .mapbase = OMAP_UART1_BASE,
36 .irq = 72, 32 .irq = 72,
37 .flags = UPF_BOOT_AUTOCONF, 33 .flags = UPF_BOOT_AUTOCONF,
38 .iotype = UPIO_MEM, 34 .iotype = UPIO_MEM,
39 .regshift = 2, 35 .regshift = 2,
40 .uartclk = OMAP16XX_BASE_BAUD * 16, 36 .uartclk = OMAP24XX_BASE_BAUD * 16,
41 }, { 37 }, {
42 .membase = (char *)IO_ADDRESS(OMAP_UART2_BASE), 38 .membase = IO_ADDRESS(OMAP_UART2_BASE),
43 .mapbase = (unsigned long)OMAP_UART2_BASE, 39 .mapbase = OMAP_UART2_BASE,
44 .irq = 73, 40 .irq = 73,
45 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
46 .iotype = UPIO_MEM, 42 .iotype = UPIO_MEM,
47 .regshift = 2, 43 .regshift = 2,
48 .uartclk = OMAP16XX_BASE_BAUD * 16, 44 .uartclk = OMAP24XX_BASE_BAUD * 16,
49 }, { 45 }, {
50 .membase = (char *)IO_ADDRESS(OMAP_UART3_BASE), 46 .membase = IO_ADDRESS(OMAP_UART3_BASE),
51 .mapbase = (unsigned long)OMAP_UART3_BASE, 47 .mapbase = OMAP_UART3_BASE,
52 .irq = 74, 48 .irq = 74,
53 .flags = UPF_BOOT_AUTOCONF, 49 .flags = UPF_BOOT_AUTOCONF,
54 .iotype = UPIO_MEM, 50 .iotype = UPIO_MEM,
55 .regshift = 2, 51 .regshift = 2,
56 .uartclk = OMAP16XX_BASE_BAUD * 16, 52 .uartclk = OMAP24XX_BASE_BAUD * 16,
57 }, { 53 }, {
58 .flags = 0 54 .flags = 0
59 } 55 }
@@ -70,7 +66,7 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
70 int value) 66 int value)
71{ 67{
72 offset <<= p->regshift; 68 offset <<= p->regshift;
73 __raw_writeb(value, (unsigned long)(p->membase + offset)); 69 __raw_writeb(value, p->membase + offset);
74} 70}
75 71
76/* 72/*
@@ -86,10 +82,27 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
86 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); 82 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
87} 83}
88 84
89void __init omap_serial_init() 85void omap_serial_enable_clocks(int enable)
86{
87 int i;
88 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
89 if (uart_ick[i] && uart_fck[i]) {
90 if (enable) {
91 clk_enable(uart_ick[i]);
92 clk_enable(uart_fck[i]);
93 } else {
94 clk_disable(uart_ick[i]);
95 clk_disable(uart_fck[i]);
96 }
97 }
98 }
99}
100
101void __init omap_serial_init(void)
90{ 102{
91 int i; 103 int i;
92 const struct omap_uart_config *info; 104 const struct omap_uart_config *info;
105 char name[16];
93 106
94 /* 107 /*
95 * Make sure the serial ports are muxed on at this point. 108 * Make sure the serial ports are muxed on at this point.
@@ -97,8 +110,7 @@ void __init omap_serial_init()
97 * if not needed. 110 * if not needed.
98 */ 111 */
99 112
100 info = omap_get_config(OMAP_TAG_UART, 113 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
101 struct omap_uart_config);
102 114
103 if (info == NULL) 115 if (info == NULL)
104 return; 116 return;
@@ -107,58 +119,26 @@ void __init omap_serial_init()
107 struct plat_serial8250_port *p = serial_platform_data + i; 119 struct plat_serial8250_port *p = serial_platform_data + i;
108 120
109 if (!(info->enabled_uarts & (1 << i))) { 121 if (!(info->enabled_uarts & (1 << i))) {
110 p->membase = 0; 122 p->membase = NULL;
111 p->mapbase = 0; 123 p->mapbase = 0;
112 continue; 124 continue;
113 } 125 }
114 126
115 switch (i) { 127 sprintf(name, "uart%d_ick", i+1);
116 case 0: 128 uart_ick[i] = clk_get(NULL, name);
117 uart1_ick = clk_get(NULL, "uart1_ick"); 129 if (IS_ERR(uart_ick[i])) {
118 if (IS_ERR(uart1_ick)) 130 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
119 printk("Could not get uart1_ick\n"); 131 uart_ick[i] = NULL;
120 else { 132 } else
121 clk_enable(uart1_ick); 133 clk_enable(uart_ick[i]);
122 } 134
123 135 sprintf(name, "uart%d_fck", i+1);
124 uart1_fck = clk_get(NULL, "uart1_fck"); 136 uart_fck[i] = clk_get(NULL, name);
125 if (IS_ERR(uart1_fck)) 137 if (IS_ERR(uart_fck[i])) {
126 printk("Could not get uart1_fck\n"); 138 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
127 else { 139 uart_fck[i] = NULL;
128 clk_enable(uart1_fck); 140 } else
129 } 141 clk_enable(uart_fck[i]);
130 break;
131 case 1:
132 uart2_ick = clk_get(NULL, "uart2_ick");
133 if (IS_ERR(uart2_ick))
134 printk("Could not get uart2_ick\n");
135 else {
136 clk_enable(uart2_ick);
137 }
138
139 uart2_fck = clk_get(NULL, "uart2_fck");
140 if (IS_ERR(uart2_fck))
141 printk("Could not get uart2_fck\n");
142 else {
143 clk_enable(uart2_fck);
144 }
145 break;
146 case 2:
147 uart3_ick = clk_get(NULL, "uart3_ick");
148 if (IS_ERR(uart3_ick))
149 printk("Could not get uart3_ick\n");
150 else {
151 clk_enable(uart3_ick);
152 }
153
154 uart3_fck = clk_get(NULL, "uart3_fck");
155 if (IS_ERR(uart3_fck))
156 printk("Could not get uart3_fck\n");
157 else {
158 clk_enable(uart3_fck);
159 }
160 break;
161 }
162 142
163 omap_serial_reset(p); 143 omap_serial_reset(p);
164 } 144 }
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep24xx.S
index 87a706fd5f82..43336b93b21c 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -5,6 +5,10 @@
5 * Texas Instruments, <www.ti.com> 5 * Texas Instruments, <www.ti.com>
6 * Richard Woodruff <r-woodruff2@ti.com> 6 * Richard Woodruff <r-woodruff2@ti.com>
7 * 7 *
8 * (C) Copyright 2006 Nokia Corporation
9 * Fixed idle loop sleep
10 * Igor Stoppa <igor.stoppa@nokia.com>
11 *
8 * This program is free software; you can redistribute it and/or 12 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 13 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 14 * published by the Free Software Foundation; either version 2 of
@@ -26,6 +30,8 @@
26#include <mach/io.h> 30#include <mach/io.h>
27#include <mach/pm.h> 31#include <mach/pm.h>
28 32
33#include <mach/omap24xx.h>
34
29#include "sdrc.h" 35#include "sdrc.h"
30 36
31/* First address of reserved address space? apparently valid for OMAP2 & 3 */ 37/* First address of reserved address space? apparently valid for OMAP2 & 3 */
@@ -52,15 +58,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
52 .word . - omap24xx_idle_loop_suspend 58 .word . - omap24xx_idle_loop_suspend
53 59
54/* 60/*
55 * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing 61 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
56 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore 62 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
57 * SDRC. 63 * SDRC.
58 * 64 *
59 * Input: 65 * Input:
60 * R0 : DLL ctrl value pre-Sleep 66 * R0 : DLL ctrl value pre-Sleep
61 * R1 : Processor+Revision 67 * R1 : SDRC_DLLA_CTRL
62 * 2420: 0x21 = 242xES1, 0x26 = 242xES2.2 68 * R2 : SDRC_POWER
63 * 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
64 * 69 *
65 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on 70 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
66 * when we get called, but the DLL probably isn't. We will wait a bit more in 71 * when we get called, but the DLL probably isn't. We will wait a bit more in
@@ -80,15 +85,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
80 */ 85 */
81ENTRY(omap24xx_cpu_suspend) 86ENTRY(omap24xx_cpu_suspend)
82 stmfd sp!, {r0 - r12, lr} @ save registers on stack 87 stmfd sp!, {r0 - r12, lr} @ save registers on stack
83 mov r3, #0x0 @ clear for mrc call 88 mov r3, #0x0 @ clear for mcr call
84 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 89 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
85 nop 90 nop
86 nop 91 nop
87 ldr r3, A_SDRC_POWER @ addr of sdrc power 92 ldr r4, [r2] @ read SDRC_POWER
88 ldr r4, [r3] @ value of sdrc power
89 orr r4, r4, #0x40 @ enable self refresh on idle req 93 orr r4, r4, #0x40 @ enable self refresh on idle req
90 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) 94 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
91 str r4, [r3] @ make it so 95 str r4, [r2] @ make it so
92 mov r2, #0 96 mov r2, #0
93 nop 97 nop
94 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt 98 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
@@ -97,14 +101,13 @@ loop:
97 subs r5, r5, #0x1 @ awake, wait just a bit 101 subs r5, r5, #0x1 @ awake, wait just a bit
98 bne loop 102 bne loop
99 103
100 /* The DPLL has on before we take the DDR out of self refresh */ 104 /* The DPLL has to be on before we take the DDR out of self refresh */
101 bic r4, r4, #0x40 @ now clear self refresh bit. 105 bic r4, r4, #0x40 @ now clear self refresh bit.
102 str r4, [r3] @ put vlaue back. 106 str r4, [r2] @ write to SDRC_POWER
103 ldr r4, A_SDRC0 @ make a clock happen 107 ldr r4, A_SDRC0 @ make a clock happen
104 ldr r4, [r4] 108 ldr r4, [r4] @ read A_SDRC0
105 nop @ start auto refresh only after clk ok 109 nop @ start auto refresh only after clk ok
106 movs r0, r0 @ see if DDR or SDR 110 movs r0, r0 @ see if DDR or SDR
107 ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
108 strne r0, [r1] @ rewrite DLLA to force DLL reload 111 strne r0, [r1] @ rewrite DLLA to force DLL reload
109 addne r1, r1, #0x8 @ move to DLLB 112 addne r1, r1, #0x8 @ move to DLLB
110 strne r0, [r1] @ rewrite DLLB to force DLL reload 113 strne r0, [r1] @ rewrite DLLB to force DLL reload
@@ -116,13 +119,8 @@ loop2:
116 /* resume*/ 119 /* resume*/
117 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 120 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
118 121
119A_SDRC_POWER:
120 .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
121A_SDRC0: 122A_SDRC0:
122 .word A_SDRC0_V 123 .word A_SDRC0_V
123A_SDRC_DLLA_CTRL_S:
124 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
125 124
126ENTRY(omap24xx_cpu_suspend_sz) 125ENTRY(omap24xx_cpu_suspend_sz)
127 .word . - omap24xx_cpu_suspend 126 .word . - omap24xx_cpu_suspend
128
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
new file mode 100644
index 000000000000..2c7146136342
--- /dev/null
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -0,0 +1,179 @@
1/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2007
7 * Texas Instruments Inc.
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * (C) Copyright 2004
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29#include <linux/linkage.h>
30#include <asm/assembler.h>
31#include <mach/hardware.h>
32
33#include <mach/io.h>
34
35#include "sdrc.h"
36#include "cm.h"
37
38 .text
39
40/*
41 * Change frequency of core dpll
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
43 */
44ENTRY(omap3_sram_configure_core_dpll)
45 stmfd sp!, {r1-r12, lr} @ store regs to stack
46 cmp r3, #0x2
47 blne configure_sdrc
48 cmp r3, #0x2
49 blne lock_dll
50 cmp r3, #0x1
51 blne unlock_dll
52 bl sdram_in_selfrefresh @ put the SDRAM in self refresh
53 bl configure_core_dpll
54 bl enable_sdrc
55 cmp r3, #0x1
56 blne wait_dll_unlock
57 cmp r3, #0x2
58 blne wait_dll_lock
59 cmp r3, #0x1
60 blne configure_sdrc
61 mov r0, #0 @ return value
62 ldmfd sp!, {r1-r12, pc} @ restore regs and return
63unlock_dll:
64 ldr r4, omap3_sdrc_dlla_ctrl
65 ldr r5, [r4]
66 orr r5, r5, #0x4
67 str r5, [r4]
68 bx lr
69lock_dll:
70 ldr r4, omap3_sdrc_dlla_ctrl
71 ldr r5, [r4]
72 bic r5, r5, #0x4
73 str r5, [r4]
74 bx lr
75sdram_in_selfrefresh:
76 mov r5, #0x0 @ Move 0 to R5
77 mcr p15, 0, r5, c7, c10, 5 @ memory barrier
78 ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
79 ldr r5, [r4] @ read the contents of SDRC_POWER
80 orr r5, r5, #0x40 @ enable self refresh on idle req
81 str r5, [r4] @ write back to SDRC_POWER register
82 ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
83 ldr r5, [r4]
84 bic r5, r5, #0x2 @ disable iclk bit for SRDC
85 str r5, [r4]
86wait_sdrc_idle:
87 ldr r4, omap3_cm_idlest1_core
88 ldr r5, [r4]
89 and r5, r5, #0x2 @ check for SDRC idle
90 cmp r5, #2
91 bne wait_sdrc_idle
92 bx lr
93configure_core_dpll:
94 ldr r4, omap3_cm_clksel1_pll
95 ldr r5, [r4]
96 ldr r6, core_m2_mask_val @ modify m2 for core dpll
97 and r5, r5, r6
98 orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
99 str r5, [r4]
100 mov r5, #0x800 @ wait for the clock to stabilise
101 cmp r3, #2
102 bne wait_clk_stable
103 bx lr
104wait_clk_stable:
105 subs r5, r5, #1
106 bne wait_clk_stable
107 nop
108 nop
109 nop
110 nop
111 nop
112 nop
113 nop
114 nop
115 nop
116 nop
117 bx lr
118enable_sdrc:
119 ldr r4, omap3_cm_iclken1_core
120 ldr r5, [r4]
121 orr r5, r5, #0x2 @ enable iclk bit for SDRC
122 str r5, [r4]
123wait_sdrc_idle1:
124 ldr r4, omap3_cm_idlest1_core
125 ldr r5, [r4]
126 and r5, r5, #0x2
127 cmp r5, #0
128 bne wait_sdrc_idle1
129 ldr r4, omap3_sdrc_power
130 ldr r5, [r4]
131 bic r5, r5, #0x40
132 str r5, [r4]
133 bx lr
134wait_dll_lock:
135 ldr r4, omap3_sdrc_dlla_status
136 ldr r5, [r4]
137 and r5, r5, #0x4
138 cmp r5, #0x4
139 bne wait_dll_lock
140 bx lr
141wait_dll_unlock:
142 ldr r4, omap3_sdrc_dlla_status
143 ldr r5, [r4]
144 and r5, r5, #0x4
145 cmp r5, #0x0
146 bne wait_dll_unlock
147 bx lr
148configure_sdrc:
149 ldr r4, omap3_sdrc_rfr_ctrl
150 str r0, [r4]
151 ldr r4, omap3_sdrc_actim_ctrla
152 str r1, [r4]
153 ldr r4, omap3_sdrc_actim_ctrlb
154 str r2, [r4]
155 bx lr
156
157omap3_sdrc_power:
158 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
159omap3_cm_clksel1_pll:
160 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
161omap3_cm_idlest1_core:
162 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
163omap3_cm_iclken1_core:
164 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
165omap3_sdrc_rfr_ctrl:
166 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
167omap3_sdrc_actim_ctrla:
168 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
169omap3_sdrc_actim_ctrlb:
170 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
171omap3_sdrc_dlla_status:
172 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
173omap3_sdrc_dlla_ctrl:
174 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
175core_m2_mask_val:
176 .word 0x07FFFFFF
177
178ENTRY(omap3_sram_configure_core_dpll_sz)
179 .word . - omap3_sram_configure_core_dpll
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 07:31:39 -0500