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-rw-r--r--arch/arm/mach-omap2/clock.c35
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/clock24xx.h115
-rw-r--r--arch/arm/mach-omap2/clock34xx.h133
4 files changed, 271 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 21fbe29810ac..8c09711d2eaf 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -264,16 +264,10 @@ static void omap2_clk_wait_ready(struct clk *clk)
264 omap2_wait_clock_ready(st_reg, bit, clk->name); 264 omap2_wait_clock_ready(st_reg, bit, clk->name);
265} 265}
266 266
267/* Enables clock without considering parent dependencies or use count 267static int omap2_dflt_clk_enable_wait(struct clk *clk)
268 * REVISIT: Maybe change this to use clk->enable like on omap1?
269 */
270int _omap2_clk_enable(struct clk *clk)
271{ 268{
272 u32 regval32; 269 u32 regval32;
273 270
274 if (clk->ops && clk->ops->enable)
275 return clk->ops->enable(clk);
276
277 if (unlikely(clk->enable_reg == NULL)) { 271 if (unlikely(clk->enable_reg == NULL)) {
278 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 272 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
279 clk->name); 273 clk->name);
@@ -293,16 +287,10 @@ int _omap2_clk_enable(struct clk *clk)
293 return 0; 287 return 0;
294} 288}
295 289
296/* Disables clock without considering parent dependencies or use count */ 290static void omap2_dflt_clk_disable(struct clk *clk)
297void _omap2_clk_disable(struct clk *clk)
298{ 291{
299 u32 regval32; 292 u32 regval32;
300 293
301 if (clk->ops && clk->ops->disable) {
302 clk->ops->disable(clk);
303 return;
304 }
305
306 if (clk->enable_reg == NULL) { 294 if (clk->enable_reg == NULL) {
307 /* 295 /*
308 * 'Independent' here refers to a clock which is not 296 * 'Independent' here refers to a clock which is not
@@ -322,6 +310,25 @@ void _omap2_clk_disable(struct clk *clk)
322 wmb(); 310 wmb();
323} 311}
324 312
313const struct clkops clkops_omap2_dflt_wait = {
314 .enable = omap2_dflt_clk_enable_wait,
315 .disable = omap2_dflt_clk_disable,
316};
317
318/* Enables clock without considering parent dependencies or use count
319 * REVISIT: Maybe change this to use clk->enable like on omap1?
320 */
321static int _omap2_clk_enable(struct clk *clk)
322{
323 return clk->ops->enable(clk);
324}
325
326/* Disables clock without considering parent dependencies or use count */
327static void _omap2_clk_disable(struct clk *clk)
328{
329 clk->ops->disable(clk);
330}
331
325void omap2_clk_disable(struct clk *clk) 332void omap2_clk_disable(struct clk *clk)
326{ 333{
327 if (clk->usecount > 0 && !(--clk->usecount)) { 334 if (clk->usecount > 0 && !(--clk->usecount)) {
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 1fb330e0847d..d4bdb59b3000 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -51,6 +51,8 @@ u32 omap2_get_dpll_rate(struct clk *clk);
51int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); 51int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
52void omap2_clk_prepare_for_reboot(void); 52void omap2_clk_prepare_for_reboot(void);
53 53
54extern const struct clkops clkops_omap2_dflt_wait;
55
54extern u8 cpu_mask; 56extern u8 cpu_mask;
55 57
56/* clksel_rate data common to 24xx/343x */ 58/* clksel_rate data common to 24xx/343x */
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index adc00e1064af..b59bf902ce7c 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -890,6 +890,7 @@ static const struct clksel common_clkout_src_clksel[] = {
890 890
891static struct clk sys_clkout_src = { 891static struct clk sys_clkout_src = {
892 .name = "sys_clkout_src", 892 .name = "sys_clkout_src",
893 .ops = &clkops_omap2_dflt_wait,
893 .parent = &func_54m_ck, 894 .parent = &func_54m_ck,
894 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 895 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
895 RATE_PROPAGATES, 896 RATE_PROPAGATES,
@@ -936,6 +937,7 @@ static struct clk sys_clkout = {
936/* In 2430, new in 2420 ES2 */ 937/* In 2430, new in 2420 ES2 */
937static struct clk sys_clkout2_src = { 938static struct clk sys_clkout2_src = {
938 .name = "sys_clkout2_src", 939 .name = "sys_clkout2_src",
940 .ops = &clkops_omap2_dflt_wait,
939 .parent = &func_54m_ck, 941 .parent = &func_54m_ck,
940 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, 942 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
941 .clkdm_name = "wkup_clkdm", 943 .clkdm_name = "wkup_clkdm",
@@ -972,6 +974,7 @@ static struct clk sys_clkout2 = {
972 974
973static struct clk emul_ck = { 975static struct clk emul_ck = {
974 .name = "emul_ck", 976 .name = "emul_ck",
977 .ops = &clkops_omap2_dflt_wait,
975 .parent = &func_54m_ck, 978 .parent = &func_54m_ck,
976 .flags = CLOCK_IN_OMAP242X, 979 .flags = CLOCK_IN_OMAP242X,
977 .clkdm_name = "wkup_clkdm", 980 .clkdm_name = "wkup_clkdm",
@@ -1051,6 +1054,7 @@ static const struct clksel dsp_fck_clksel[] = {
1051 1054
1052static struct clk dsp_fck = { 1055static struct clk dsp_fck = {
1053 .name = "dsp_fck", 1056 .name = "dsp_fck",
1057 .ops = &clkops_omap2_dflt_wait,
1054 .parent = &core_ck, 1058 .parent = &core_ck,
1055 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1059 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
1056 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1060 CONFIG_PARTICIPANT | RATE_PROPAGATES,
@@ -1096,6 +1100,7 @@ static struct clk dsp_irate_ick = {
1096/* 2420 only */ 1100/* 2420 only */
1097static struct clk dsp_ick = { 1101static struct clk dsp_ick = {
1098 .name = "dsp_ick", /* apparently ipi and isp */ 1102 .name = "dsp_ick", /* apparently ipi and isp */
1103 .ops = &clkops_omap2_dflt_wait,
1099 .parent = &dsp_irate_ick, 1104 .parent = &dsp_irate_ick,
1100 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, 1105 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT,
1101 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), 1106 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
@@ -1105,6 +1110,7 @@ static struct clk dsp_ick = {
1105/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ 1110/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1106static struct clk iva2_1_ick = { 1111static struct clk iva2_1_ick = {
1107 .name = "iva2_1_ick", 1112 .name = "iva2_1_ick",
1113 .ops = &clkops_omap2_dflt_wait,
1108 .parent = &dsp_irate_ick, 1114 .parent = &dsp_irate_ick,
1109 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1115 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1110 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1116 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
@@ -1118,6 +1124,7 @@ static struct clk iva2_1_ick = {
1118 */ 1124 */
1119static struct clk iva1_ifck = { 1125static struct clk iva1_ifck = {
1120 .name = "iva1_ifck", 1126 .name = "iva1_ifck",
1127 .ops = &clkops_omap2_dflt_wait,
1121 .parent = &core_ck, 1128 .parent = &core_ck,
1122 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | 1129 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
1123 RATE_PROPAGATES | DELAYED_APP, 1130 RATE_PROPAGATES | DELAYED_APP,
@@ -1135,6 +1142,7 @@ static struct clk iva1_ifck = {
1135/* IVA1 mpu/int/i/f clocks are /2 of parent */ 1142/* IVA1 mpu/int/i/f clocks are /2 of parent */
1136static struct clk iva1_mpu_int_ifck = { 1143static struct clk iva1_mpu_int_ifck = {
1137 .name = "iva1_mpu_int_ifck", 1144 .name = "iva1_mpu_int_ifck",
1145 .ops = &clkops_omap2_dflt_wait,
1138 .parent = &iva1_ifck, 1146 .parent = &iva1_ifck,
1139 .flags = CLOCK_IN_OMAP242X, 1147 .flags = CLOCK_IN_OMAP242X,
1140 .clkdm_name = "iva1_clkdm", 1148 .clkdm_name = "iva1_clkdm",
@@ -1211,6 +1219,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
1211/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ 1219/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1212static struct clk usb_l4_ick = { /* FS-USB interface clock */ 1220static struct clk usb_l4_ick = { /* FS-USB interface clock */
1213 .name = "usb_l4_ick", 1221 .name = "usb_l4_ick",
1222 .ops = &clkops_omap2_dflt_wait,
1214 .parent = &core_l3_ck, 1223 .parent = &core_l3_ck,
1215 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1224 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1216 DELAYED_APP | CONFIG_PARTICIPANT, 1225 DELAYED_APP | CONFIG_PARTICIPANT,
@@ -1284,6 +1293,7 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1284 1293
1285static struct clk ssi_ssr_sst_fck = { 1294static struct clk ssi_ssr_sst_fck = {
1286 .name = "ssi_fck", 1295 .name = "ssi_fck",
1296 .ops = &clkops_omap2_dflt_wait,
1287 .parent = &core_ck, 1297 .parent = &core_ck,
1288 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1298 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1289 DELAYED_APP, 1299 DELAYED_APP,
@@ -1320,6 +1330,7 @@ static const struct clksel gfx_fck_clksel[] = {
1320 1330
1321static struct clk gfx_3d_fck = { 1331static struct clk gfx_3d_fck = {
1322 .name = "gfx_3d_fck", 1332 .name = "gfx_3d_fck",
1333 .ops = &clkops_omap2_dflt_wait,
1323 .parent = &core_l3_ck, 1334 .parent = &core_l3_ck,
1324 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1335 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1325 .clkdm_name = "gfx_clkdm", 1336 .clkdm_name = "gfx_clkdm",
@@ -1335,6 +1346,7 @@ static struct clk gfx_3d_fck = {
1335 1346
1336static struct clk gfx_2d_fck = { 1347static struct clk gfx_2d_fck = {
1337 .name = "gfx_2d_fck", 1348 .name = "gfx_2d_fck",
1349 .ops = &clkops_omap2_dflt_wait,
1338 .parent = &core_l3_ck, 1350 .parent = &core_l3_ck,
1339 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1351 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1340 .clkdm_name = "gfx_clkdm", 1352 .clkdm_name = "gfx_clkdm",
@@ -1350,6 +1362,7 @@ static struct clk gfx_2d_fck = {
1350 1362
1351static struct clk gfx_ick = { 1363static struct clk gfx_ick = {
1352 .name = "gfx_ick", /* From l3 */ 1364 .name = "gfx_ick", /* From l3 */
1365 .ops = &clkops_omap2_dflt_wait,
1353 .parent = &core_l3_ck, 1366 .parent = &core_l3_ck,
1354 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1367 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1355 .clkdm_name = "gfx_clkdm", 1368 .clkdm_name = "gfx_clkdm",
@@ -1380,6 +1393,7 @@ static const struct clksel mdm_ick_clksel[] = {
1380 1393
1381static struct clk mdm_ick = { /* used both as a ick and fck */ 1394static struct clk mdm_ick = { /* used both as a ick and fck */
1382 .name = "mdm_ick", 1395 .name = "mdm_ick",
1396 .ops = &clkops_omap2_dflt_wait,
1383 .parent = &core_ck, 1397 .parent = &core_ck,
1384 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1398 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
1385 .clkdm_name = "mdm_clkdm", 1399 .clkdm_name = "mdm_clkdm",
@@ -1395,6 +1409,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
1395 1409
1396static struct clk mdm_osc_ck = { 1410static struct clk mdm_osc_ck = {
1397 .name = "mdm_osc_ck", 1411 .name = "mdm_osc_ck",
1412 .ops = &clkops_omap2_dflt_wait,
1398 .parent = &osc_ck, 1413 .parent = &osc_ck,
1399 .flags = CLOCK_IN_OMAP243X, 1414 .flags = CLOCK_IN_OMAP243X,
1400 .clkdm_name = "mdm_clkdm", 1415 .clkdm_name = "mdm_clkdm",
@@ -1440,6 +1455,7 @@ static const struct clksel dss1_fck_clksel[] = {
1440 1455
1441static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 1456static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1442 .name = "dss_ick", 1457 .name = "dss_ick",
1458 .ops = &clkops_omap2_dflt_wait,
1443 .parent = &l4_ck, /* really both l3 and l4 */ 1459 .parent = &l4_ck, /* really both l3 and l4 */
1444 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1460 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1445 .clkdm_name = "dss_clkdm", 1461 .clkdm_name = "dss_clkdm",
@@ -1450,6 +1466,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1450 1466
1451static struct clk dss1_fck = { 1467static struct clk dss1_fck = {
1452 .name = "dss1_fck", 1468 .name = "dss1_fck",
1469 .ops = &clkops_omap2_dflt_wait,
1453 .parent = &core_ck, /* Core or sys */ 1470 .parent = &core_ck, /* Core or sys */
1454 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1471 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1455 DELAYED_APP, 1472 DELAYED_APP,
@@ -1483,6 +1500,7 @@ static const struct clksel dss2_fck_clksel[] = {
1483 1500
1484static struct clk dss2_fck = { /* Alt clk used in power management */ 1501static struct clk dss2_fck = { /* Alt clk used in power management */
1485 .name = "dss2_fck", 1502 .name = "dss2_fck",
1503 .ops = &clkops_omap2_dflt_wait,
1486 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1504 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1487 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1505 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1488 DELAYED_APP, 1506 DELAYED_APP,
@@ -1498,6 +1516,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
1498 1516
1499static struct clk dss_54m_fck = { /* Alt clk used in power management */ 1517static struct clk dss_54m_fck = { /* Alt clk used in power management */
1500 .name = "dss_54m_fck", /* 54m tv clk */ 1518 .name = "dss_54m_fck", /* 54m tv clk */
1519 .ops = &clkops_omap2_dflt_wait,
1501 .parent = &func_54m_ck, 1520 .parent = &func_54m_ck,
1502 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1521 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1503 .clkdm_name = "dss_clkdm", 1522 .clkdm_name = "dss_clkdm",
@@ -1526,6 +1545,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
1526 1545
1527static struct clk gpt1_ick = { 1546static struct clk gpt1_ick = {
1528 .name = "gpt1_ick", 1547 .name = "gpt1_ick",
1548 .ops = &clkops_omap2_dflt_wait,
1529 .parent = &l4_ck, 1549 .parent = &l4_ck,
1530 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1550 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1531 .clkdm_name = "core_l4_clkdm", 1551 .clkdm_name = "core_l4_clkdm",
@@ -1536,6 +1556,7 @@ static struct clk gpt1_ick = {
1536 1556
1537static struct clk gpt1_fck = { 1557static struct clk gpt1_fck = {
1538 .name = "gpt1_fck", 1558 .name = "gpt1_fck",
1559 .ops = &clkops_omap2_dflt_wait,
1539 .parent = &func_32k_ck, 1560 .parent = &func_32k_ck,
1540 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1561 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1541 .clkdm_name = "core_l4_clkdm", 1562 .clkdm_name = "core_l4_clkdm",
@@ -1552,6 +1573,7 @@ static struct clk gpt1_fck = {
1552 1573
1553static struct clk gpt2_ick = { 1574static struct clk gpt2_ick = {
1554 .name = "gpt2_ick", 1575 .name = "gpt2_ick",
1576 .ops = &clkops_omap2_dflt_wait,
1555 .parent = &l4_ck, 1577 .parent = &l4_ck,
1556 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1578 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1557 .clkdm_name = "core_l4_clkdm", 1579 .clkdm_name = "core_l4_clkdm",
@@ -1562,6 +1584,7 @@ static struct clk gpt2_ick = {
1562 1584
1563static struct clk gpt2_fck = { 1585static struct clk gpt2_fck = {
1564 .name = "gpt2_fck", 1586 .name = "gpt2_fck",
1587 .ops = &clkops_omap2_dflt_wait,
1565 .parent = &func_32k_ck, 1588 .parent = &func_32k_ck,
1566 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1589 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1567 .clkdm_name = "core_l4_clkdm", 1590 .clkdm_name = "core_l4_clkdm",
@@ -1576,6 +1599,7 @@ static struct clk gpt2_fck = {
1576 1599
1577static struct clk gpt3_ick = { 1600static struct clk gpt3_ick = {
1578 .name = "gpt3_ick", 1601 .name = "gpt3_ick",
1602 .ops = &clkops_omap2_dflt_wait,
1579 .parent = &l4_ck, 1603 .parent = &l4_ck,
1580 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1604 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1581 .clkdm_name = "core_l4_clkdm", 1605 .clkdm_name = "core_l4_clkdm",
@@ -1586,6 +1610,7 @@ static struct clk gpt3_ick = {
1586 1610
1587static struct clk gpt3_fck = { 1611static struct clk gpt3_fck = {
1588 .name = "gpt3_fck", 1612 .name = "gpt3_fck",
1613 .ops = &clkops_omap2_dflt_wait,
1589 .parent = &func_32k_ck, 1614 .parent = &func_32k_ck,
1590 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1615 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1591 .clkdm_name = "core_l4_clkdm", 1616 .clkdm_name = "core_l4_clkdm",
@@ -1600,6 +1625,7 @@ static struct clk gpt3_fck = {
1600 1625
1601static struct clk gpt4_ick = { 1626static struct clk gpt4_ick = {
1602 .name = "gpt4_ick", 1627 .name = "gpt4_ick",
1628 .ops = &clkops_omap2_dflt_wait,
1603 .parent = &l4_ck, 1629 .parent = &l4_ck,
1604 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1605 .clkdm_name = "core_l4_clkdm", 1631 .clkdm_name = "core_l4_clkdm",
@@ -1610,6 +1636,7 @@ static struct clk gpt4_ick = {
1610 1636
1611static struct clk gpt4_fck = { 1637static struct clk gpt4_fck = {
1612 .name = "gpt4_fck", 1638 .name = "gpt4_fck",
1639 .ops = &clkops_omap2_dflt_wait,
1613 .parent = &func_32k_ck, 1640 .parent = &func_32k_ck,
1614 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1641 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1615 .clkdm_name = "core_l4_clkdm", 1642 .clkdm_name = "core_l4_clkdm",
@@ -1624,6 +1651,7 @@ static struct clk gpt4_fck = {
1624 1651
1625static struct clk gpt5_ick = { 1652static struct clk gpt5_ick = {
1626 .name = "gpt5_ick", 1653 .name = "gpt5_ick",
1654 .ops = &clkops_omap2_dflt_wait,
1627 .parent = &l4_ck, 1655 .parent = &l4_ck,
1628 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1656 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1629 .clkdm_name = "core_l4_clkdm", 1657 .clkdm_name = "core_l4_clkdm",
@@ -1634,6 +1662,7 @@ static struct clk gpt5_ick = {
1634 1662
1635static struct clk gpt5_fck = { 1663static struct clk gpt5_fck = {
1636 .name = "gpt5_fck", 1664 .name = "gpt5_fck",
1665 .ops = &clkops_omap2_dflt_wait,
1637 .parent = &func_32k_ck, 1666 .parent = &func_32k_ck,
1638 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1667 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1639 .clkdm_name = "core_l4_clkdm", 1668 .clkdm_name = "core_l4_clkdm",
@@ -1648,6 +1677,7 @@ static struct clk gpt5_fck = {
1648 1677
1649static struct clk gpt6_ick = { 1678static struct clk gpt6_ick = {
1650 .name = "gpt6_ick", 1679 .name = "gpt6_ick",
1680 .ops = &clkops_omap2_dflt_wait,
1651 .parent = &l4_ck, 1681 .parent = &l4_ck,
1652 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1682 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1653 .clkdm_name = "core_l4_clkdm", 1683 .clkdm_name = "core_l4_clkdm",
@@ -1658,6 +1688,7 @@ static struct clk gpt6_ick = {
1658 1688
1659static struct clk gpt6_fck = { 1689static struct clk gpt6_fck = {
1660 .name = "gpt6_fck", 1690 .name = "gpt6_fck",
1691 .ops = &clkops_omap2_dflt_wait,
1661 .parent = &func_32k_ck, 1692 .parent = &func_32k_ck,
1662 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1693 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1663 .clkdm_name = "core_l4_clkdm", 1694 .clkdm_name = "core_l4_clkdm",
@@ -1672,6 +1703,7 @@ static struct clk gpt6_fck = {
1672 1703
1673static struct clk gpt7_ick = { 1704static struct clk gpt7_ick = {
1674 .name = "gpt7_ick", 1705 .name = "gpt7_ick",
1706 .ops = &clkops_omap2_dflt_wait,
1675 .parent = &l4_ck, 1707 .parent = &l4_ck,
1676 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1708 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1677 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1681,6 +1713,7 @@ static struct clk gpt7_ick = {
1681 1713
1682static struct clk gpt7_fck = { 1714static struct clk gpt7_fck = {
1683 .name = "gpt7_fck", 1715 .name = "gpt7_fck",
1716 .ops = &clkops_omap2_dflt_wait,
1684 .parent = &func_32k_ck, 1717 .parent = &func_32k_ck,
1685 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1718 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1686 .clkdm_name = "core_l4_clkdm", 1719 .clkdm_name = "core_l4_clkdm",
@@ -1695,6 +1728,7 @@ static struct clk gpt7_fck = {
1695 1728
1696static struct clk gpt8_ick = { 1729static struct clk gpt8_ick = {
1697 .name = "gpt8_ick", 1730 .name = "gpt8_ick",
1731 .ops = &clkops_omap2_dflt_wait,
1698 .parent = &l4_ck, 1732 .parent = &l4_ck,
1699 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1733 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1700 .clkdm_name = "core_l4_clkdm", 1734 .clkdm_name = "core_l4_clkdm",
@@ -1705,6 +1739,7 @@ static struct clk gpt8_ick = {
1705 1739
1706static struct clk gpt8_fck = { 1740static struct clk gpt8_fck = {
1707 .name = "gpt8_fck", 1741 .name = "gpt8_fck",
1742 .ops = &clkops_omap2_dflt_wait,
1708 .parent = &func_32k_ck, 1743 .parent = &func_32k_ck,
1709 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1744 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1710 .clkdm_name = "core_l4_clkdm", 1745 .clkdm_name = "core_l4_clkdm",
@@ -1719,6 +1754,7 @@ static struct clk gpt8_fck = {
1719 1754
1720static struct clk gpt9_ick = { 1755static struct clk gpt9_ick = {
1721 .name = "gpt9_ick", 1756 .name = "gpt9_ick",
1757 .ops = &clkops_omap2_dflt_wait,
1722 .parent = &l4_ck, 1758 .parent = &l4_ck,
1723 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1759 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1724 .clkdm_name = "core_l4_clkdm", 1760 .clkdm_name = "core_l4_clkdm",
@@ -1729,6 +1765,7 @@ static struct clk gpt9_ick = {
1729 1765
1730static struct clk gpt9_fck = { 1766static struct clk gpt9_fck = {
1731 .name = "gpt9_fck", 1767 .name = "gpt9_fck",
1768 .ops = &clkops_omap2_dflt_wait,
1732 .parent = &func_32k_ck, 1769 .parent = &func_32k_ck,
1733 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734 .clkdm_name = "core_l4_clkdm", 1771 .clkdm_name = "core_l4_clkdm",
@@ -1743,6 +1780,7 @@ static struct clk gpt9_fck = {
1743 1780
1744static struct clk gpt10_ick = { 1781static struct clk gpt10_ick = {
1745 .name = "gpt10_ick", 1782 .name = "gpt10_ick",
1783 .ops = &clkops_omap2_dflt_wait,
1746 .parent = &l4_ck, 1784 .parent = &l4_ck,
1747 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1785 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1748 .clkdm_name = "core_l4_clkdm", 1786 .clkdm_name = "core_l4_clkdm",
@@ -1753,6 +1791,7 @@ static struct clk gpt10_ick = {
1753 1791
1754static struct clk gpt10_fck = { 1792static struct clk gpt10_fck = {
1755 .name = "gpt10_fck", 1793 .name = "gpt10_fck",
1794 .ops = &clkops_omap2_dflt_wait,
1756 .parent = &func_32k_ck, 1795 .parent = &func_32k_ck,
1757 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1796 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1758 .clkdm_name = "core_l4_clkdm", 1797 .clkdm_name = "core_l4_clkdm",
@@ -1767,6 +1806,7 @@ static struct clk gpt10_fck = {
1767 1806
1768static struct clk gpt11_ick = { 1807static struct clk gpt11_ick = {
1769 .name = "gpt11_ick", 1808 .name = "gpt11_ick",
1809 .ops = &clkops_omap2_dflt_wait,
1770 .parent = &l4_ck, 1810 .parent = &l4_ck,
1771 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1811 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1772 .clkdm_name = "core_l4_clkdm", 1812 .clkdm_name = "core_l4_clkdm",
@@ -1777,6 +1817,7 @@ static struct clk gpt11_ick = {
1777 1817
1778static struct clk gpt11_fck = { 1818static struct clk gpt11_fck = {
1779 .name = "gpt11_fck", 1819 .name = "gpt11_fck",
1820 .ops = &clkops_omap2_dflt_wait,
1780 .parent = &func_32k_ck, 1821 .parent = &func_32k_ck,
1781 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1782 .clkdm_name = "core_l4_clkdm", 1823 .clkdm_name = "core_l4_clkdm",
@@ -1791,6 +1832,7 @@ static struct clk gpt11_fck = {
1791 1832
1792static struct clk gpt12_ick = { 1833static struct clk gpt12_ick = {
1793 .name = "gpt12_ick", 1834 .name = "gpt12_ick",
1835 .ops = &clkops_omap2_dflt_wait,
1794 .parent = &l4_ck, 1836 .parent = &l4_ck,
1795 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1837 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1796 .clkdm_name = "core_l4_clkdm", 1838 .clkdm_name = "core_l4_clkdm",
@@ -1801,6 +1843,7 @@ static struct clk gpt12_ick = {
1801 1843
1802static struct clk gpt12_fck = { 1844static struct clk gpt12_fck = {
1803 .name = "gpt12_fck", 1845 .name = "gpt12_fck",
1846 .ops = &clkops_omap2_dflt_wait,
1804 .parent = &func_32k_ck, 1847 .parent = &func_32k_ck,
1805 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1806 .clkdm_name = "core_l4_clkdm", 1849 .clkdm_name = "core_l4_clkdm",
@@ -1815,6 +1858,7 @@ static struct clk gpt12_fck = {
1815 1858
1816static struct clk mcbsp1_ick = { 1859static struct clk mcbsp1_ick = {
1817 .name = "mcbsp_ick", 1860 .name = "mcbsp_ick",
1861 .ops = &clkops_omap2_dflt_wait,
1818 .id = 1, 1862 .id = 1,
1819 .parent = &l4_ck, 1863 .parent = &l4_ck,
1820 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1864 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -1826,6 +1870,7 @@ static struct clk mcbsp1_ick = {
1826 1870
1827static struct clk mcbsp1_fck = { 1871static struct clk mcbsp1_fck = {
1828 .name = "mcbsp_fck", 1872 .name = "mcbsp_fck",
1873 .ops = &clkops_omap2_dflt_wait,
1829 .id = 1, 1874 .id = 1,
1830 .parent = &func_96m_ck, 1875 .parent = &func_96m_ck,
1831 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1876 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -1837,6 +1882,7 @@ static struct clk mcbsp1_fck = {
1837 1882
1838static struct clk mcbsp2_ick = { 1883static struct clk mcbsp2_ick = {
1839 .name = "mcbsp_ick", 1884 .name = "mcbsp_ick",
1885 .ops = &clkops_omap2_dflt_wait,
1840 .id = 2, 1886 .id = 2,
1841 .parent = &l4_ck, 1887 .parent = &l4_ck,
1842 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1888 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -1848,6 +1894,7 @@ static struct clk mcbsp2_ick = {
1848 1894
1849static struct clk mcbsp2_fck = { 1895static struct clk mcbsp2_fck = {
1850 .name = "mcbsp_fck", 1896 .name = "mcbsp_fck",
1897 .ops = &clkops_omap2_dflt_wait,
1851 .id = 2, 1898 .id = 2,
1852 .parent = &func_96m_ck, 1899 .parent = &func_96m_ck,
1853 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1900 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -1859,6 +1906,7 @@ static struct clk mcbsp2_fck = {
1859 1906
1860static struct clk mcbsp3_ick = { 1907static struct clk mcbsp3_ick = {
1861 .name = "mcbsp_ick", 1908 .name = "mcbsp_ick",
1909 .ops = &clkops_omap2_dflt_wait,
1862 .id = 3, 1910 .id = 3,
1863 .parent = &l4_ck, 1911 .parent = &l4_ck,
1864 .flags = CLOCK_IN_OMAP243X, 1912 .flags = CLOCK_IN_OMAP243X,
@@ -1870,6 +1918,7 @@ static struct clk mcbsp3_ick = {
1870 1918
1871static struct clk mcbsp3_fck = { 1919static struct clk mcbsp3_fck = {
1872 .name = "mcbsp_fck", 1920 .name = "mcbsp_fck",
1921 .ops = &clkops_omap2_dflt_wait,
1873 .id = 3, 1922 .id = 3,
1874 .parent = &func_96m_ck, 1923 .parent = &func_96m_ck,
1875 .flags = CLOCK_IN_OMAP243X, 1924 .flags = CLOCK_IN_OMAP243X,
@@ -1881,6 +1930,7 @@ static struct clk mcbsp3_fck = {
1881 1930
1882static struct clk mcbsp4_ick = { 1931static struct clk mcbsp4_ick = {
1883 .name = "mcbsp_ick", 1932 .name = "mcbsp_ick",
1933 .ops = &clkops_omap2_dflt_wait,
1884 .id = 4, 1934 .id = 4,
1885 .parent = &l4_ck, 1935 .parent = &l4_ck,
1886 .flags = CLOCK_IN_OMAP243X, 1936 .flags = CLOCK_IN_OMAP243X,
@@ -1892,6 +1942,7 @@ static struct clk mcbsp4_ick = {
1892 1942
1893static struct clk mcbsp4_fck = { 1943static struct clk mcbsp4_fck = {
1894 .name = "mcbsp_fck", 1944 .name = "mcbsp_fck",
1945 .ops = &clkops_omap2_dflt_wait,
1895 .id = 4, 1946 .id = 4,
1896 .parent = &func_96m_ck, 1947 .parent = &func_96m_ck,
1897 .flags = CLOCK_IN_OMAP243X, 1948 .flags = CLOCK_IN_OMAP243X,
@@ -1903,6 +1954,7 @@ static struct clk mcbsp4_fck = {
1903 1954
1904static struct clk mcbsp5_ick = { 1955static struct clk mcbsp5_ick = {
1905 .name = "mcbsp_ick", 1956 .name = "mcbsp_ick",
1957 .ops = &clkops_omap2_dflt_wait,
1906 .id = 5, 1958 .id = 5,
1907 .parent = &l4_ck, 1959 .parent = &l4_ck,
1908 .flags = CLOCK_IN_OMAP243X, 1960 .flags = CLOCK_IN_OMAP243X,
@@ -1914,6 +1966,7 @@ static struct clk mcbsp5_ick = {
1914 1966
1915static struct clk mcbsp5_fck = { 1967static struct clk mcbsp5_fck = {
1916 .name = "mcbsp_fck", 1968 .name = "mcbsp_fck",
1969 .ops = &clkops_omap2_dflt_wait,
1917 .id = 5, 1970 .id = 5,
1918 .parent = &func_96m_ck, 1971 .parent = &func_96m_ck,
1919 .flags = CLOCK_IN_OMAP243X, 1972 .flags = CLOCK_IN_OMAP243X,
@@ -1925,6 +1978,7 @@ static struct clk mcbsp5_fck = {
1925 1978
1926static struct clk mcspi1_ick = { 1979static struct clk mcspi1_ick = {
1927 .name = "mcspi_ick", 1980 .name = "mcspi_ick",
1981 .ops = &clkops_omap2_dflt_wait,
1928 .id = 1, 1982 .id = 1,
1929 .parent = &l4_ck, 1983 .parent = &l4_ck,
1930 .clkdm_name = "core_l4_clkdm", 1984 .clkdm_name = "core_l4_clkdm",
@@ -1936,6 +1990,7 @@ static struct clk mcspi1_ick = {
1936 1990
1937static struct clk mcspi1_fck = { 1991static struct clk mcspi1_fck = {
1938 .name = "mcspi_fck", 1992 .name = "mcspi_fck",
1993 .ops = &clkops_omap2_dflt_wait,
1939 .id = 1, 1994 .id = 1,
1940 .parent = &func_48m_ck, 1995 .parent = &func_48m_ck,
1941 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1996 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -1947,6 +2002,7 @@ static struct clk mcspi1_fck = {
1947 2002
1948static struct clk mcspi2_ick = { 2003static struct clk mcspi2_ick = {
1949 .name = "mcspi_ick", 2004 .name = "mcspi_ick",
2005 .ops = &clkops_omap2_dflt_wait,
1950 .id = 2, 2006 .id = 2,
1951 .parent = &l4_ck, 2007 .parent = &l4_ck,
1952 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2008 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -1958,6 +2014,7 @@ static struct clk mcspi2_ick = {
1958 2014
1959static struct clk mcspi2_fck = { 2015static struct clk mcspi2_fck = {
1960 .name = "mcspi_fck", 2016 .name = "mcspi_fck",
2017 .ops = &clkops_omap2_dflt_wait,
1961 .id = 2, 2018 .id = 2,
1962 .parent = &func_48m_ck, 2019 .parent = &func_48m_ck,
1963 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2020 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -1969,6 +2026,7 @@ static struct clk mcspi2_fck = {
1969 2026
1970static struct clk mcspi3_ick = { 2027static struct clk mcspi3_ick = {
1971 .name = "mcspi_ick", 2028 .name = "mcspi_ick",
2029 .ops = &clkops_omap2_dflt_wait,
1972 .id = 3, 2030 .id = 3,
1973 .parent = &l4_ck, 2031 .parent = &l4_ck,
1974 .flags = CLOCK_IN_OMAP243X, 2032 .flags = CLOCK_IN_OMAP243X,
@@ -1980,6 +2038,7 @@ static struct clk mcspi3_ick = {
1980 2038
1981static struct clk mcspi3_fck = { 2039static struct clk mcspi3_fck = {
1982 .name = "mcspi_fck", 2040 .name = "mcspi_fck",
2041 .ops = &clkops_omap2_dflt_wait,
1983 .id = 3, 2042 .id = 3,
1984 .parent = &func_48m_ck, 2043 .parent = &func_48m_ck,
1985 .flags = CLOCK_IN_OMAP243X, 2044 .flags = CLOCK_IN_OMAP243X,
@@ -1991,6 +2050,7 @@ static struct clk mcspi3_fck = {
1991 2050
1992static struct clk uart1_ick = { 2051static struct clk uart1_ick = {
1993 .name = "uart1_ick", 2052 .name = "uart1_ick",
2053 .ops = &clkops_omap2_dflt_wait,
1994 .parent = &l4_ck, 2054 .parent = &l4_ck,
1995 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2055 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1996 .clkdm_name = "core_l4_clkdm", 2056 .clkdm_name = "core_l4_clkdm",
@@ -2001,6 +2061,7 @@ static struct clk uart1_ick = {
2001 2061
2002static struct clk uart1_fck = { 2062static struct clk uart1_fck = {
2003 .name = "uart1_fck", 2063 .name = "uart1_fck",
2064 .ops = &clkops_omap2_dflt_wait,
2004 .parent = &func_48m_ck, 2065 .parent = &func_48m_ck,
2005 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2066 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2006 .clkdm_name = "core_l4_clkdm", 2067 .clkdm_name = "core_l4_clkdm",
@@ -2011,6 +2072,7 @@ static struct clk uart1_fck = {
2011 2072
2012static struct clk uart2_ick = { 2073static struct clk uart2_ick = {
2013 .name = "uart2_ick", 2074 .name = "uart2_ick",
2075 .ops = &clkops_omap2_dflt_wait,
2014 .parent = &l4_ck, 2076 .parent = &l4_ck,
2015 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2077 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2016 .clkdm_name = "core_l4_clkdm", 2078 .clkdm_name = "core_l4_clkdm",
@@ -2021,6 +2083,7 @@ static struct clk uart2_ick = {
2021 2083
2022static struct clk uart2_fck = { 2084static struct clk uart2_fck = {
2023 .name = "uart2_fck", 2085 .name = "uart2_fck",
2086 .ops = &clkops_omap2_dflt_wait,
2024 .parent = &func_48m_ck, 2087 .parent = &func_48m_ck,
2025 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2088 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2026 .clkdm_name = "core_l4_clkdm", 2089 .clkdm_name = "core_l4_clkdm",
@@ -2031,6 +2094,7 @@ static struct clk uart2_fck = {
2031 2094
2032static struct clk uart3_ick = { 2095static struct clk uart3_ick = {
2033 .name = "uart3_ick", 2096 .name = "uart3_ick",
2097 .ops = &clkops_omap2_dflt_wait,
2034 .parent = &l4_ck, 2098 .parent = &l4_ck,
2035 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2099 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2036 .clkdm_name = "core_l4_clkdm", 2100 .clkdm_name = "core_l4_clkdm",
@@ -2041,6 +2105,7 @@ static struct clk uart3_ick = {
2041 2105
2042static struct clk uart3_fck = { 2106static struct clk uart3_fck = {
2043 .name = "uart3_fck", 2107 .name = "uart3_fck",
2108 .ops = &clkops_omap2_dflt_wait,
2044 .parent = &func_48m_ck, 2109 .parent = &func_48m_ck,
2045 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2110 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2046 .clkdm_name = "core_l4_clkdm", 2111 .clkdm_name = "core_l4_clkdm",
@@ -2051,6 +2116,7 @@ static struct clk uart3_fck = {
2051 2116
2052static struct clk gpios_ick = { 2117static struct clk gpios_ick = {
2053 .name = "gpios_ick", 2118 .name = "gpios_ick",
2119 .ops = &clkops_omap2_dflt_wait,
2054 .parent = &l4_ck, 2120 .parent = &l4_ck,
2055 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2121 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2056 .clkdm_name = "core_l4_clkdm", 2122 .clkdm_name = "core_l4_clkdm",
@@ -2061,6 +2127,7 @@ static struct clk gpios_ick = {
2061 2127
2062static struct clk gpios_fck = { 2128static struct clk gpios_fck = {
2063 .name = "gpios_fck", 2129 .name = "gpios_fck",
2130 .ops = &clkops_omap2_dflt_wait,
2064 .parent = &func_32k_ck, 2131 .parent = &func_32k_ck,
2065 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2132 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2066 .clkdm_name = "wkup_clkdm", 2133 .clkdm_name = "wkup_clkdm",
@@ -2071,6 +2138,7 @@ static struct clk gpios_fck = {
2071 2138
2072static struct clk mpu_wdt_ick = { 2139static struct clk mpu_wdt_ick = {
2073 .name = "mpu_wdt_ick", 2140 .name = "mpu_wdt_ick",
2141 .ops = &clkops_omap2_dflt_wait,
2074 .parent = &l4_ck, 2142 .parent = &l4_ck,
2075 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2143 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2076 .clkdm_name = "core_l4_clkdm", 2144 .clkdm_name = "core_l4_clkdm",
@@ -2081,6 +2149,7 @@ static struct clk mpu_wdt_ick = {
2081 2149
2082static struct clk mpu_wdt_fck = { 2150static struct clk mpu_wdt_fck = {
2083 .name = "mpu_wdt_fck", 2151 .name = "mpu_wdt_fck",
2152 .ops = &clkops_omap2_dflt_wait,
2084 .parent = &func_32k_ck, 2153 .parent = &func_32k_ck,
2085 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2154 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2086 .clkdm_name = "wkup_clkdm", 2155 .clkdm_name = "wkup_clkdm",
@@ -2091,6 +2160,7 @@ static struct clk mpu_wdt_fck = {
2091 2160
2092static struct clk sync_32k_ick = { 2161static struct clk sync_32k_ick = {
2093 .name = "sync_32k_ick", 2162 .name = "sync_32k_ick",
2163 .ops = &clkops_omap2_dflt_wait,
2094 .parent = &l4_ck, 2164 .parent = &l4_ck,
2095 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2165 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2096 ENABLE_ON_INIT, 2166 ENABLE_ON_INIT,
@@ -2102,6 +2172,7 @@ static struct clk sync_32k_ick = {
2102 2172
2103static struct clk wdt1_ick = { 2173static struct clk wdt1_ick = {
2104 .name = "wdt1_ick", 2174 .name = "wdt1_ick",
2175 .ops = &clkops_omap2_dflt_wait,
2105 .parent = &l4_ck, 2176 .parent = &l4_ck,
2106 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2177 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2107 .clkdm_name = "core_l4_clkdm", 2178 .clkdm_name = "core_l4_clkdm",
@@ -2112,6 +2183,7 @@ static struct clk wdt1_ick = {
2112 2183
2113static struct clk omapctrl_ick = { 2184static struct clk omapctrl_ick = {
2114 .name = "omapctrl_ick", 2185 .name = "omapctrl_ick",
2186 .ops = &clkops_omap2_dflt_wait,
2115 .parent = &l4_ck, 2187 .parent = &l4_ck,
2116 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2188 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2117 ENABLE_ON_INIT, 2189 ENABLE_ON_INIT,
@@ -2123,6 +2195,7 @@ static struct clk omapctrl_ick = {
2123 2195
2124static struct clk icr_ick = { 2196static struct clk icr_ick = {
2125 .name = "icr_ick", 2197 .name = "icr_ick",
2198 .ops = &clkops_omap2_dflt_wait,
2126 .parent = &l4_ck, 2199 .parent = &l4_ck,
2127 .flags = CLOCK_IN_OMAP243X, 2200 .flags = CLOCK_IN_OMAP243X,
2128 .clkdm_name = "core_l4_clkdm", 2201 .clkdm_name = "core_l4_clkdm",
@@ -2133,6 +2206,7 @@ static struct clk icr_ick = {
2133 2206
2134static struct clk cam_ick = { 2207static struct clk cam_ick = {
2135 .name = "cam_ick", 2208 .name = "cam_ick",
2209 .ops = &clkops_omap2_dflt_wait,
2136 .parent = &l4_ck, 2210 .parent = &l4_ck,
2137 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2211 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2138 .clkdm_name = "core_l4_clkdm", 2212 .clkdm_name = "core_l4_clkdm",
@@ -2148,6 +2222,7 @@ static struct clk cam_ick = {
2148 */ 2222 */
2149static struct clk cam_fck = { 2223static struct clk cam_fck = {
2150 .name = "cam_fck", 2224 .name = "cam_fck",
2225 .ops = &clkops_omap2_dflt_wait,
2151 .parent = &func_96m_ck, 2226 .parent = &func_96m_ck,
2152 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2227 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2153 .clkdm_name = "core_l3_clkdm", 2228 .clkdm_name = "core_l3_clkdm",
@@ -2158,6 +2233,7 @@ static struct clk cam_fck = {
2158 2233
2159static struct clk mailboxes_ick = { 2234static struct clk mailboxes_ick = {
2160 .name = "mailboxes_ick", 2235 .name = "mailboxes_ick",
2236 .ops = &clkops_omap2_dflt_wait,
2161 .parent = &l4_ck, 2237 .parent = &l4_ck,
2162 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2238 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2163 .clkdm_name = "core_l4_clkdm", 2239 .clkdm_name = "core_l4_clkdm",
@@ -2168,6 +2244,7 @@ static struct clk mailboxes_ick = {
2168 2244
2169static struct clk wdt4_ick = { 2245static struct clk wdt4_ick = {
2170 .name = "wdt4_ick", 2246 .name = "wdt4_ick",
2247 .ops = &clkops_omap2_dflt_wait,
2171 .parent = &l4_ck, 2248 .parent = &l4_ck,
2172 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2249 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2173 .clkdm_name = "core_l4_clkdm", 2250 .clkdm_name = "core_l4_clkdm",
@@ -2178,6 +2255,7 @@ static struct clk wdt4_ick = {
2178 2255
2179static struct clk wdt4_fck = { 2256static struct clk wdt4_fck = {
2180 .name = "wdt4_fck", 2257 .name = "wdt4_fck",
2258 .ops = &clkops_omap2_dflt_wait,
2181 .parent = &func_32k_ck, 2259 .parent = &func_32k_ck,
2182 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2260 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2183 .clkdm_name = "core_l4_clkdm", 2261 .clkdm_name = "core_l4_clkdm",
@@ -2188,6 +2266,7 @@ static struct clk wdt4_fck = {
2188 2266
2189static struct clk wdt3_ick = { 2267static struct clk wdt3_ick = {
2190 .name = "wdt3_ick", 2268 .name = "wdt3_ick",
2269 .ops = &clkops_omap2_dflt_wait,
2191 .parent = &l4_ck, 2270 .parent = &l4_ck,
2192 .flags = CLOCK_IN_OMAP242X, 2271 .flags = CLOCK_IN_OMAP242X,
2193 .clkdm_name = "core_l4_clkdm", 2272 .clkdm_name = "core_l4_clkdm",
@@ -2198,6 +2277,7 @@ static struct clk wdt3_ick = {
2198 2277
2199static struct clk wdt3_fck = { 2278static struct clk wdt3_fck = {
2200 .name = "wdt3_fck", 2279 .name = "wdt3_fck",
2280 .ops = &clkops_omap2_dflt_wait,
2201 .parent = &func_32k_ck, 2281 .parent = &func_32k_ck,
2202 .flags = CLOCK_IN_OMAP242X, 2282 .flags = CLOCK_IN_OMAP242X,
2203 .clkdm_name = "core_l4_clkdm", 2283 .clkdm_name = "core_l4_clkdm",
@@ -2208,6 +2288,7 @@ static struct clk wdt3_fck = {
2208 2288
2209static struct clk mspro_ick = { 2289static struct clk mspro_ick = {
2210 .name = "mspro_ick", 2290 .name = "mspro_ick",
2291 .ops = &clkops_omap2_dflt_wait,
2211 .parent = &l4_ck, 2292 .parent = &l4_ck,
2212 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2293 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2213 .clkdm_name = "core_l4_clkdm", 2294 .clkdm_name = "core_l4_clkdm",
@@ -2218,6 +2299,7 @@ static struct clk mspro_ick = {
2218 2299
2219static struct clk mspro_fck = { 2300static struct clk mspro_fck = {
2220 .name = "mspro_fck", 2301 .name = "mspro_fck",
2302 .ops = &clkops_omap2_dflt_wait,
2221 .parent = &func_96m_ck, 2303 .parent = &func_96m_ck,
2222 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2304 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2223 .clkdm_name = "core_l4_clkdm", 2305 .clkdm_name = "core_l4_clkdm",
@@ -2228,6 +2310,7 @@ static struct clk mspro_fck = {
2228 2310
2229static struct clk mmc_ick = { 2311static struct clk mmc_ick = {
2230 .name = "mmc_ick", 2312 .name = "mmc_ick",
2313 .ops = &clkops_omap2_dflt_wait,
2231 .parent = &l4_ck, 2314 .parent = &l4_ck,
2232 .flags = CLOCK_IN_OMAP242X, 2315 .flags = CLOCK_IN_OMAP242X,
2233 .clkdm_name = "core_l4_clkdm", 2316 .clkdm_name = "core_l4_clkdm",
@@ -2238,6 +2321,7 @@ static struct clk mmc_ick = {
2238 2321
2239static struct clk mmc_fck = { 2322static struct clk mmc_fck = {
2240 .name = "mmc_fck", 2323 .name = "mmc_fck",
2324 .ops = &clkops_omap2_dflt_wait,
2241 .parent = &func_96m_ck, 2325 .parent = &func_96m_ck,
2242 .flags = CLOCK_IN_OMAP242X, 2326 .flags = CLOCK_IN_OMAP242X,
2243 .clkdm_name = "core_l4_clkdm", 2327 .clkdm_name = "core_l4_clkdm",
@@ -2248,6 +2332,7 @@ static struct clk mmc_fck = {
2248 2332
2249static struct clk fac_ick = { 2333static struct clk fac_ick = {
2250 .name = "fac_ick", 2334 .name = "fac_ick",
2335 .ops = &clkops_omap2_dflt_wait,
2251 .parent = &l4_ck, 2336 .parent = &l4_ck,
2252 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2337 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2253 .clkdm_name = "core_l4_clkdm", 2338 .clkdm_name = "core_l4_clkdm",
@@ -2258,6 +2343,7 @@ static struct clk fac_ick = {
2258 2343
2259static struct clk fac_fck = { 2344static struct clk fac_fck = {
2260 .name = "fac_fck", 2345 .name = "fac_fck",
2346 .ops = &clkops_omap2_dflt_wait,
2261 .parent = &func_12m_ck, 2347 .parent = &func_12m_ck,
2262 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2348 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2263 .clkdm_name = "core_l4_clkdm", 2349 .clkdm_name = "core_l4_clkdm",
@@ -2268,6 +2354,7 @@ static struct clk fac_fck = {
2268 2354
2269static struct clk eac_ick = { 2355static struct clk eac_ick = {
2270 .name = "eac_ick", 2356 .name = "eac_ick",
2357 .ops = &clkops_omap2_dflt_wait,
2271 .parent = &l4_ck, 2358 .parent = &l4_ck,
2272 .flags = CLOCK_IN_OMAP242X, 2359 .flags = CLOCK_IN_OMAP242X,
2273 .clkdm_name = "core_l4_clkdm", 2360 .clkdm_name = "core_l4_clkdm",
@@ -2278,6 +2365,7 @@ static struct clk eac_ick = {
2278 2365
2279static struct clk eac_fck = { 2366static struct clk eac_fck = {
2280 .name = "eac_fck", 2367 .name = "eac_fck",
2368 .ops = &clkops_omap2_dflt_wait,
2281 .parent = &func_96m_ck, 2369 .parent = &func_96m_ck,
2282 .flags = CLOCK_IN_OMAP242X, 2370 .flags = CLOCK_IN_OMAP242X,
2283 .clkdm_name = "core_l4_clkdm", 2371 .clkdm_name = "core_l4_clkdm",
@@ -2288,6 +2376,7 @@ static struct clk eac_fck = {
2288 2376
2289static struct clk hdq_ick = { 2377static struct clk hdq_ick = {
2290 .name = "hdq_ick", 2378 .name = "hdq_ick",
2379 .ops = &clkops_omap2_dflt_wait,
2291 .parent = &l4_ck, 2380 .parent = &l4_ck,
2292 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2381 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2293 .clkdm_name = "core_l4_clkdm", 2382 .clkdm_name = "core_l4_clkdm",
@@ -2298,6 +2387,7 @@ static struct clk hdq_ick = {
2298 2387
2299static struct clk hdq_fck = { 2388static struct clk hdq_fck = {
2300 .name = "hdq_fck", 2389 .name = "hdq_fck",
2390 .ops = &clkops_omap2_dflt_wait,
2301 .parent = &func_12m_ck, 2391 .parent = &func_12m_ck,
2302 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2392 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2303 .clkdm_name = "core_l4_clkdm", 2393 .clkdm_name = "core_l4_clkdm",
@@ -2308,6 +2398,7 @@ static struct clk hdq_fck = {
2308 2398
2309static struct clk i2c2_ick = { 2399static struct clk i2c2_ick = {
2310 .name = "i2c_ick", 2400 .name = "i2c_ick",
2401 .ops = &clkops_omap2_dflt_wait,
2311 .id = 2, 2402 .id = 2,
2312 .parent = &l4_ck, 2403 .parent = &l4_ck,
2313 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2404 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -2319,6 +2410,7 @@ static struct clk i2c2_ick = {
2319 2410
2320static struct clk i2c2_fck = { 2411static struct clk i2c2_fck = {
2321 .name = "i2c_fck", 2412 .name = "i2c_fck",
2413 .ops = &clkops_omap2_dflt_wait,
2322 .id = 2, 2414 .id = 2,
2323 .parent = &func_12m_ck, 2415 .parent = &func_12m_ck,
2324 .flags = CLOCK_IN_OMAP242X, 2416 .flags = CLOCK_IN_OMAP242X,
@@ -2330,6 +2422,7 @@ static struct clk i2c2_fck = {
2330 2422
2331static struct clk i2chs2_fck = { 2423static struct clk i2chs2_fck = {
2332 .name = "i2c_fck", 2424 .name = "i2c_fck",
2425 .ops = &clkops_omap2_dflt_wait,
2333 .id = 2, 2426 .id = 2,
2334 .parent = &func_96m_ck, 2427 .parent = &func_96m_ck,
2335 .flags = CLOCK_IN_OMAP243X, 2428 .flags = CLOCK_IN_OMAP243X,
@@ -2341,6 +2434,7 @@ static struct clk i2chs2_fck = {
2341 2434
2342static struct clk i2c1_ick = { 2435static struct clk i2c1_ick = {
2343 .name = "i2c_ick", 2436 .name = "i2c_ick",
2437 .ops = &clkops_omap2_dflt_wait,
2344 .id = 1, 2438 .id = 1,
2345 .parent = &l4_ck, 2439 .parent = &l4_ck,
2346 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2440 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
@@ -2352,6 +2446,7 @@ static struct clk i2c1_ick = {
2352 2446
2353static struct clk i2c1_fck = { 2447static struct clk i2c1_fck = {
2354 .name = "i2c_fck", 2448 .name = "i2c_fck",
2449 .ops = &clkops_omap2_dflt_wait,
2355 .id = 1, 2450 .id = 1,
2356 .parent = &func_12m_ck, 2451 .parent = &func_12m_ck,
2357 .flags = CLOCK_IN_OMAP242X, 2452 .flags = CLOCK_IN_OMAP242X,
@@ -2363,6 +2458,7 @@ static struct clk i2c1_fck = {
2363 2458
2364static struct clk i2chs1_fck = { 2459static struct clk i2chs1_fck = {
2365 .name = "i2c_fck", 2460 .name = "i2c_fck",
2461 .ops = &clkops_omap2_dflt_wait,
2366 .id = 1, 2462 .id = 1,
2367 .parent = &func_96m_ck, 2463 .parent = &func_96m_ck,
2368 .flags = CLOCK_IN_OMAP243X, 2464 .flags = CLOCK_IN_OMAP243X,
@@ -2402,6 +2498,7 @@ static struct clk sdma_ick = {
2402 2498
2403static struct clk vlynq_ick = { 2499static struct clk vlynq_ick = {
2404 .name = "vlynq_ick", 2500 .name = "vlynq_ick",
2501 .ops = &clkops_omap2_dflt_wait,
2405 .parent = &core_l3_ck, 2502 .parent = &core_l3_ck,
2406 .flags = CLOCK_IN_OMAP242X, 2503 .flags = CLOCK_IN_OMAP242X,
2407 .clkdm_name = "core_l3_clkdm", 2504 .clkdm_name = "core_l3_clkdm",
@@ -2437,6 +2534,7 @@ static const struct clksel vlynq_fck_clksel[] = {
2437 2534
2438static struct clk vlynq_fck = { 2535static struct clk vlynq_fck = {
2439 .name = "vlynq_fck", 2536 .name = "vlynq_fck",
2537 .ops = &clkops_omap2_dflt_wait,
2440 .parent = &func_96m_ck, 2538 .parent = &func_96m_ck,
2441 .flags = CLOCK_IN_OMAP242X | DELAYED_APP, 2539 .flags = CLOCK_IN_OMAP242X | DELAYED_APP,
2442 .clkdm_name = "core_l3_clkdm", 2540 .clkdm_name = "core_l3_clkdm",
@@ -2453,6 +2551,7 @@ static struct clk vlynq_fck = {
2453 2551
2454static struct clk sdrc_ick = { 2552static struct clk sdrc_ick = {
2455 .name = "sdrc_ick", 2553 .name = "sdrc_ick",
2554 .ops = &clkops_omap2_dflt_wait,
2456 .parent = &l4_ck, 2555 .parent = &l4_ck,
2457 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2556 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
2458 .clkdm_name = "core_l4_clkdm", 2557 .clkdm_name = "core_l4_clkdm",
@@ -2463,6 +2562,7 @@ static struct clk sdrc_ick = {
2463 2562
2464static struct clk des_ick = { 2563static struct clk des_ick = {
2465 .name = "des_ick", 2564 .name = "des_ick",
2565 .ops = &clkops_omap2_dflt_wait,
2466 .parent = &l4_ck, 2566 .parent = &l4_ck,
2467 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2567 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2468 .clkdm_name = "core_l4_clkdm", 2568 .clkdm_name = "core_l4_clkdm",
@@ -2473,6 +2573,7 @@ static struct clk des_ick = {
2473 2573
2474static struct clk sha_ick = { 2574static struct clk sha_ick = {
2475 .name = "sha_ick", 2575 .name = "sha_ick",
2576 .ops = &clkops_omap2_dflt_wait,
2476 .parent = &l4_ck, 2577 .parent = &l4_ck,
2477 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2578 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2478 .clkdm_name = "core_l4_clkdm", 2579 .clkdm_name = "core_l4_clkdm",
@@ -2483,6 +2584,7 @@ static struct clk sha_ick = {
2483 2584
2484static struct clk rng_ick = { 2585static struct clk rng_ick = {
2485 .name = "rng_ick", 2586 .name = "rng_ick",
2587 .ops = &clkops_omap2_dflt_wait,
2486 .parent = &l4_ck, 2588 .parent = &l4_ck,
2487 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2589 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2488 .clkdm_name = "core_l4_clkdm", 2590 .clkdm_name = "core_l4_clkdm",
@@ -2493,6 +2595,7 @@ static struct clk rng_ick = {
2493 2595
2494static struct clk aes_ick = { 2596static struct clk aes_ick = {
2495 .name = "aes_ick", 2597 .name = "aes_ick",
2598 .ops = &clkops_omap2_dflt_wait,
2496 .parent = &l4_ck, 2599 .parent = &l4_ck,
2497 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2600 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2498 .clkdm_name = "core_l4_clkdm", 2601 .clkdm_name = "core_l4_clkdm",
@@ -2503,6 +2606,7 @@ static struct clk aes_ick = {
2503 2606
2504static struct clk pka_ick = { 2607static struct clk pka_ick = {
2505 .name = "pka_ick", 2608 .name = "pka_ick",
2609 .ops = &clkops_omap2_dflt_wait,
2506 .parent = &l4_ck, 2610 .parent = &l4_ck,
2507 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2611 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2508 .clkdm_name = "core_l4_clkdm", 2612 .clkdm_name = "core_l4_clkdm",
@@ -2513,6 +2617,7 @@ static struct clk pka_ick = {
2513 2617
2514static struct clk usb_fck = { 2618static struct clk usb_fck = {
2515 .name = "usb_fck", 2619 .name = "usb_fck",
2620 .ops = &clkops_omap2_dflt_wait,
2516 .parent = &func_48m_ck, 2621 .parent = &func_48m_ck,
2517 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, 2622 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2518 .clkdm_name = "core_l3_clkdm", 2623 .clkdm_name = "core_l3_clkdm",
@@ -2523,6 +2628,7 @@ static struct clk usb_fck = {
2523 2628
2524static struct clk usbhs_ick = { 2629static struct clk usbhs_ick = {
2525 .name = "usbhs_ick", 2630 .name = "usbhs_ick",
2631 .ops = &clkops_omap2_dflt_wait,
2526 .parent = &core_l3_ck, 2632 .parent = &core_l3_ck,
2527 .flags = CLOCK_IN_OMAP243X, 2633 .flags = CLOCK_IN_OMAP243X,
2528 .clkdm_name = "core_l3_clkdm", 2634 .clkdm_name = "core_l3_clkdm",
@@ -2533,6 +2639,7 @@ static struct clk usbhs_ick = {
2533 2639
2534static struct clk mmchs1_ick = { 2640static struct clk mmchs1_ick = {
2535 .name = "mmchs_ick", 2641 .name = "mmchs_ick",
2642 .ops = &clkops_omap2_dflt_wait,
2536 .parent = &l4_ck, 2643 .parent = &l4_ck,
2537 .flags = CLOCK_IN_OMAP243X, 2644 .flags = CLOCK_IN_OMAP243X,
2538 .clkdm_name = "core_l4_clkdm", 2645 .clkdm_name = "core_l4_clkdm",
@@ -2543,6 +2650,7 @@ static struct clk mmchs1_ick = {
2543 2650
2544static struct clk mmchs1_fck = { 2651static struct clk mmchs1_fck = {
2545 .name = "mmchs_fck", 2652 .name = "mmchs_fck",
2653 .ops = &clkops_omap2_dflt_wait,
2546 .parent = &func_96m_ck, 2654 .parent = &func_96m_ck,
2547 .flags = CLOCK_IN_OMAP243X, 2655 .flags = CLOCK_IN_OMAP243X,
2548 .clkdm_name = "core_l3_clkdm", 2656 .clkdm_name = "core_l3_clkdm",
@@ -2553,6 +2661,7 @@ static struct clk mmchs1_fck = {
2553 2661
2554static struct clk mmchs2_ick = { 2662static struct clk mmchs2_ick = {
2555 .name = "mmchs_ick", 2663 .name = "mmchs_ick",
2664 .ops = &clkops_omap2_dflt_wait,
2556 .id = 1, 2665 .id = 1,
2557 .parent = &l4_ck, 2666 .parent = &l4_ck,
2558 .flags = CLOCK_IN_OMAP243X, 2667 .flags = CLOCK_IN_OMAP243X,
@@ -2564,6 +2673,7 @@ static struct clk mmchs2_ick = {
2564 2673
2565static struct clk mmchs2_fck = { 2674static struct clk mmchs2_fck = {
2566 .name = "mmchs_fck", 2675 .name = "mmchs_fck",
2676 .ops = &clkops_omap2_dflt_wait,
2567 .id = 1, 2677 .id = 1,
2568 .parent = &func_96m_ck, 2678 .parent = &func_96m_ck,
2569 .flags = CLOCK_IN_OMAP243X, 2679 .flags = CLOCK_IN_OMAP243X,
@@ -2574,6 +2684,7 @@ static struct clk mmchs2_fck = {
2574 2684
2575static struct clk gpio5_ick = { 2685static struct clk gpio5_ick = {
2576 .name = "gpio5_ick", 2686 .name = "gpio5_ick",
2687 .ops = &clkops_omap2_dflt_wait,
2577 .parent = &l4_ck, 2688 .parent = &l4_ck,
2578 .flags = CLOCK_IN_OMAP243X, 2689 .flags = CLOCK_IN_OMAP243X,
2579 .clkdm_name = "core_l4_clkdm", 2690 .clkdm_name = "core_l4_clkdm",
@@ -2584,6 +2695,7 @@ static struct clk gpio5_ick = {
2584 2695
2585static struct clk gpio5_fck = { 2696static struct clk gpio5_fck = {
2586 .name = "gpio5_fck", 2697 .name = "gpio5_fck",
2698 .ops = &clkops_omap2_dflt_wait,
2587 .parent = &func_32k_ck, 2699 .parent = &func_32k_ck,
2588 .flags = CLOCK_IN_OMAP243X, 2700 .flags = CLOCK_IN_OMAP243X,
2589 .clkdm_name = "core_l4_clkdm", 2701 .clkdm_name = "core_l4_clkdm",
@@ -2594,6 +2706,7 @@ static struct clk gpio5_fck = {
2594 2706
2595static struct clk mdm_intc_ick = { 2707static struct clk mdm_intc_ick = {
2596 .name = "mdm_intc_ick", 2708 .name = "mdm_intc_ick",
2709 .ops = &clkops_omap2_dflt_wait,
2597 .parent = &l4_ck, 2710 .parent = &l4_ck,
2598 .flags = CLOCK_IN_OMAP243X, 2711 .flags = CLOCK_IN_OMAP243X,
2599 .clkdm_name = "core_l4_clkdm", 2712 .clkdm_name = "core_l4_clkdm",
@@ -2604,6 +2717,7 @@ static struct clk mdm_intc_ick = {
2604 2717
2605static struct clk mmchsdb1_fck = { 2718static struct clk mmchsdb1_fck = {
2606 .name = "mmchsdb_fck", 2719 .name = "mmchsdb_fck",
2720 .ops = &clkops_omap2_dflt_wait,
2607 .parent = &func_32k_ck, 2721 .parent = &func_32k_ck,
2608 .flags = CLOCK_IN_OMAP243X, 2722 .flags = CLOCK_IN_OMAP243X,
2609 .clkdm_name = "core_l4_clkdm", 2723 .clkdm_name = "core_l4_clkdm",
@@ -2614,6 +2728,7 @@ static struct clk mmchsdb1_fck = {
2614 2728
2615static struct clk mmchsdb2_fck = { 2729static struct clk mmchsdb2_fck = {
2616 .name = "mmchsdb_fck", 2730 .name = "mmchsdb_fck",
2731 .ops = &clkops_omap2_dflt_wait,
2617 .id = 1, 2732 .id = 1,
2618 .parent = &func_32k_ck, 2733 .parent = &func_32k_ck,
2619 .flags = CLOCK_IN_OMAP243X, 2734 .flags = CLOCK_IN_OMAP243X,
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 203e2bd3b3b0..0d6a11ca132d 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -216,6 +216,7 @@ static struct clk mcbsp_clks = {
216 216
217static struct clk sys_clkout1 = { 217static struct clk sys_clkout1 = {
218 .name = "sys_clkout1", 218 .name = "sys_clkout1",
219 .ops = &clkops_omap2_dflt_wait,
219 .parent = &osc_sys_ck, 220 .parent = &osc_sys_ck,
220 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, 221 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
221 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, 222 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
@@ -535,6 +536,7 @@ static struct clk dpll3_m3_ck = {
535/* The PWRDN bit is apparently only available on 3430ES2 and above */ 536/* The PWRDN bit is apparently only available on 3430ES2 and above */
536static struct clk dpll3_m3x2_ck = { 537static struct clk dpll3_m3x2_ck = {
537 .name = "dpll3_m3x2_ck", 538 .name = "dpll3_m3x2_ck",
539 .ops = &clkops_omap2_dflt_wait,
538 .parent = &dpll3_m3_ck, 540 .parent = &dpll3_m3_ck,
539 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 541 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
540 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, 542 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
@@ -626,6 +628,7 @@ static struct clk dpll4_m2_ck = {
626/* The PWRDN bit is apparently only available on 3430ES2 and above */ 628/* The PWRDN bit is apparently only available on 3430ES2 and above */
627static struct clk dpll4_m2x2_ck = { 629static struct clk dpll4_m2x2_ck = {
628 .name = "dpll4_m2x2_ck", 630 .name = "dpll4_m2x2_ck",
631 .ops = &clkops_omap2_dflt_wait,
629 .parent = &dpll4_m2_ck, 632 .parent = &dpll4_m2_ck,
630 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 633 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
631 .enable_bit = OMAP3430_PWRDN_96M_SHIFT, 634 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
@@ -693,6 +696,7 @@ static struct clk dpll4_m3_ck = {
693/* The PWRDN bit is apparently only available on 3430ES2 and above */ 696/* The PWRDN bit is apparently only available on 3430ES2 and above */
694static struct clk dpll4_m3x2_ck = { 697static struct clk dpll4_m3x2_ck = {
695 .name = "dpll4_m3x2_ck", 698 .name = "dpll4_m3x2_ck",
699 .ops = &clkops_omap2_dflt_wait,
696 .parent = &dpll4_m3_ck, 700 .parent = &dpll4_m3_ck,
697 .init = &omap2_init_clksel_parent, 701 .init = &omap2_init_clksel_parent,
698 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 702 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
@@ -798,6 +802,7 @@ static struct clk dpll4_m4_ck = {
798/* The PWRDN bit is apparently only available on 3430ES2 and above */ 802/* The PWRDN bit is apparently only available on 3430ES2 and above */
799static struct clk dpll4_m4x2_ck = { 803static struct clk dpll4_m4x2_ck = {
800 .name = "dpll4_m4x2_ck", 804 .name = "dpll4_m4x2_ck",
805 .ops = &clkops_omap2_dflt_wait,
801 .parent = &dpll4_m4_ck, 806 .parent = &dpll4_m4_ck,
802 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 807 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
803 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 808 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
@@ -821,6 +826,7 @@ static struct clk dpll4_m5_ck = {
821/* The PWRDN bit is apparently only available on 3430ES2 and above */ 826/* The PWRDN bit is apparently only available on 3430ES2 and above */
822static struct clk dpll4_m5x2_ck = { 827static struct clk dpll4_m5x2_ck = {
823 .name = "dpll4_m5x2_ck", 828 .name = "dpll4_m5x2_ck",
829 .ops = &clkops_omap2_dflt_wait,
824 .parent = &dpll4_m5_ck, 830 .parent = &dpll4_m5_ck,
825 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 831 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
826 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 832 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
@@ -844,6 +850,7 @@ static struct clk dpll4_m6_ck = {
844/* The PWRDN bit is apparently only available on 3430ES2 and above */ 850/* The PWRDN bit is apparently only available on 3430ES2 and above */
845static struct clk dpll4_m6x2_ck = { 851static struct clk dpll4_m6x2_ck = {
846 .name = "dpll4_m6x2_ck", 852 .name = "dpll4_m6x2_ck",
853 .ops = &clkops_omap2_dflt_wait,
847 .parent = &dpll4_m6_ck, 854 .parent = &dpll4_m6_ck,
848 .init = &omap2_init_clksel_parent, 855 .init = &omap2_init_clksel_parent,
849 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 856 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
@@ -960,6 +967,7 @@ static const struct clksel clkout2_src_clksel[] = {
960 967
961static struct clk clkout2_src_ck = { 968static struct clk clkout2_src_ck = {
962 .name = "clkout2_src_ck", 969 .name = "clkout2_src_ck",
970 .ops = &clkops_omap2_dflt_wait,
963 .init = &omap2_init_clksel_parent, 971 .init = &omap2_init_clksel_parent,
964 .enable_reg = OMAP3430_CM_CLKOUT_CTRL, 972 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
965 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, 973 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
@@ -1118,6 +1126,7 @@ static const struct clksel iva2_clksel[] = {
1118 1126
1119static struct clk iva2_ck = { 1127static struct clk iva2_ck = {
1120 .name = "iva2_ck", 1128 .name = "iva2_ck",
1129 .ops = &clkops_omap2_dflt_wait,
1121 .parent = &dpll2_m2_ck, 1130 .parent = &dpll2_m2_ck,
1122 .init = &omap2_init_clksel_parent, 1131 .init = &omap2_init_clksel_parent,
1123 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1132 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
@@ -1194,6 +1203,7 @@ static const struct clksel gfx_l3_clksel[] = {
1194/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ 1203/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1195static struct clk gfx_l3_ck = { 1204static struct clk gfx_l3_ck = {
1196 .name = "gfx_l3_ck", 1205 .name = "gfx_l3_ck",
1206 .ops = &clkops_omap2_dflt_wait,
1197 .parent = &l3_ick, 1207 .parent = &l3_ick,
1198 .init = &omap2_init_clksel_parent, 1208 .init = &omap2_init_clksel_parent,
1199 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1209 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
@@ -1226,6 +1236,7 @@ static struct clk gfx_l3_ick = {
1226 1236
1227static struct clk gfx_cg1_ck = { 1237static struct clk gfx_cg1_ck = {
1228 .name = "gfx_cg1_ck", 1238 .name = "gfx_cg1_ck",
1239 .ops = &clkops_omap2_dflt_wait,
1229 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1240 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1230 .init = &omap2_init_clk_clkdm, 1241 .init = &omap2_init_clk_clkdm,
1231 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1242 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
@@ -1237,6 +1248,7 @@ static struct clk gfx_cg1_ck = {
1237 1248
1238static struct clk gfx_cg2_ck = { 1249static struct clk gfx_cg2_ck = {
1239 .name = "gfx_cg2_ck", 1250 .name = "gfx_cg2_ck",
1251 .ops = &clkops_omap2_dflt_wait,
1240 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1252 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1241 .init = &omap2_init_clk_clkdm, 1253 .init = &omap2_init_clk_clkdm,
1242 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1254 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
@@ -1268,6 +1280,7 @@ static const struct clksel sgx_clksel[] = {
1268 1280
1269static struct clk sgx_fck = { 1281static struct clk sgx_fck = {
1270 .name = "sgx_fck", 1282 .name = "sgx_fck",
1283 .ops = &clkops_omap2_dflt_wait,
1271 .init = &omap2_init_clksel_parent, 1284 .init = &omap2_init_clksel_parent,
1272 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), 1285 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1273 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1286 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
@@ -1281,6 +1294,7 @@ static struct clk sgx_fck = {
1281 1294
1282static struct clk sgx_ick = { 1295static struct clk sgx_ick = {
1283 .name = "sgx_ick", 1296 .name = "sgx_ick",
1297 .ops = &clkops_omap2_dflt_wait,
1284 .parent = &l3_ick, 1298 .parent = &l3_ick,
1285 .init = &omap2_init_clk_clkdm, 1299 .init = &omap2_init_clk_clkdm,
1286 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), 1300 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
@@ -1294,6 +1308,7 @@ static struct clk sgx_ick = {
1294 1308
1295static struct clk d2d_26m_fck = { 1309static struct clk d2d_26m_fck = {
1296 .name = "d2d_26m_fck", 1310 .name = "d2d_26m_fck",
1311 .ops = &clkops_omap2_dflt_wait,
1297 .parent = &sys_ck, 1312 .parent = &sys_ck,
1298 .init = &omap2_init_clk_clkdm, 1313 .init = &omap2_init_clk_clkdm,
1299 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1314 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1311,6 +1326,7 @@ static const struct clksel omap343x_gpt_clksel[] = {
1311 1326
1312static struct clk gpt10_fck = { 1327static struct clk gpt10_fck = {
1313 .name = "gpt10_fck", 1328 .name = "gpt10_fck",
1329 .ops = &clkops_omap2_dflt_wait,
1314 .parent = &sys_ck, 1330 .parent = &sys_ck,
1315 .init = &omap2_init_clksel_parent, 1331 .init = &omap2_init_clksel_parent,
1316 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1332 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1325,6 +1341,7 @@ static struct clk gpt10_fck = {
1325 1341
1326static struct clk gpt11_fck = { 1342static struct clk gpt11_fck = {
1327 .name = "gpt11_fck", 1343 .name = "gpt11_fck",
1344 .ops = &clkops_omap2_dflt_wait,
1328 .parent = &sys_ck, 1345 .parent = &sys_ck,
1329 .init = &omap2_init_clksel_parent, 1346 .init = &omap2_init_clksel_parent,
1330 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1347 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1339,6 +1356,7 @@ static struct clk gpt11_fck = {
1339 1356
1340static struct clk cpefuse_fck = { 1357static struct clk cpefuse_fck = {
1341 .name = "cpefuse_fck", 1358 .name = "cpefuse_fck",
1359 .ops = &clkops_omap2_dflt_wait,
1342 .parent = &sys_ck, 1360 .parent = &sys_ck,
1343 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1361 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1344 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, 1362 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
@@ -1348,6 +1366,7 @@ static struct clk cpefuse_fck = {
1348 1366
1349static struct clk ts_fck = { 1367static struct clk ts_fck = {
1350 .name = "ts_fck", 1368 .name = "ts_fck",
1369 .ops = &clkops_omap2_dflt_wait,
1351 .parent = &omap_32k_fck, 1370 .parent = &omap_32k_fck,
1352 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1353 .enable_bit = OMAP3430ES2_EN_TS_SHIFT, 1372 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
@@ -1357,6 +1376,7 @@ static struct clk ts_fck = {
1357 1376
1358static struct clk usbtll_fck = { 1377static struct clk usbtll_fck = {
1359 .name = "usbtll_fck", 1378 .name = "usbtll_fck",
1379 .ops = &clkops_omap2_dflt_wait,
1360 .parent = &omap_120m_fck, 1380 .parent = &omap_120m_fck,
1361 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1381 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1362 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1382 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -1377,6 +1397,7 @@ static struct clk core_96m_fck = {
1377 1397
1378static struct clk mmchs3_fck = { 1398static struct clk mmchs3_fck = {
1379 .name = "mmchs_fck", 1399 .name = "mmchs_fck",
1400 .ops = &clkops_omap2_dflt_wait,
1380 .id = 2, 1401 .id = 2,
1381 .parent = &core_96m_fck, 1402 .parent = &core_96m_fck,
1382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1403 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1388,6 +1409,7 @@ static struct clk mmchs3_fck = {
1388 1409
1389static struct clk mmchs2_fck = { 1410static struct clk mmchs2_fck = {
1390 .name = "mmchs_fck", 1411 .name = "mmchs_fck",
1412 .ops = &clkops_omap2_dflt_wait,
1391 .id = 1, 1413 .id = 1,
1392 .parent = &core_96m_fck, 1414 .parent = &core_96m_fck,
1393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1415 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1399,6 +1421,7 @@ static struct clk mmchs2_fck = {
1399 1421
1400static struct clk mspro_fck = { 1422static struct clk mspro_fck = {
1401 .name = "mspro_fck", 1423 .name = "mspro_fck",
1424 .ops = &clkops_omap2_dflt_wait,
1402 .parent = &core_96m_fck, 1425 .parent = &core_96m_fck,
1403 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1426 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1404 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1427 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
@@ -1409,6 +1432,7 @@ static struct clk mspro_fck = {
1409 1432
1410static struct clk mmchs1_fck = { 1433static struct clk mmchs1_fck = {
1411 .name = "mmchs_fck", 1434 .name = "mmchs_fck",
1435 .ops = &clkops_omap2_dflt_wait,
1412 .parent = &core_96m_fck, 1436 .parent = &core_96m_fck,
1413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1437 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1414 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1438 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
@@ -1419,6 +1443,7 @@ static struct clk mmchs1_fck = {
1419 1443
1420static struct clk i2c3_fck = { 1444static struct clk i2c3_fck = {
1421 .name = "i2c_fck", 1445 .name = "i2c_fck",
1446 .ops = &clkops_omap2_dflt_wait,
1422 .id = 3, 1447 .id = 3,
1423 .parent = &core_96m_fck, 1448 .parent = &core_96m_fck,
1424 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1430,6 +1455,7 @@ static struct clk i2c3_fck = {
1430 1455
1431static struct clk i2c2_fck = { 1456static struct clk i2c2_fck = {
1432 .name = "i2c_fck", 1457 .name = "i2c_fck",
1458 .ops = &clkops_omap2_dflt_wait,
1433 .id = 2, 1459 .id = 2,
1434 .parent = &core_96m_fck, 1460 .parent = &core_96m_fck,
1435 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1441,6 +1467,7 @@ static struct clk i2c2_fck = {
1441 1467
1442static struct clk i2c1_fck = { 1468static struct clk i2c1_fck = {
1443 .name = "i2c_fck", 1469 .name = "i2c_fck",
1470 .ops = &clkops_omap2_dflt_wait,
1444 .id = 1, 1471 .id = 1,
1445 .parent = &core_96m_fck, 1472 .parent = &core_96m_fck,
1446 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1473 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1472,6 +1499,7 @@ static const struct clksel mcbsp_15_clksel[] = {
1472 1499
1473static struct clk mcbsp5_fck = { 1500static struct clk mcbsp5_fck = {
1474 .name = "mcbsp_fck", 1501 .name = "mcbsp_fck",
1502 .ops = &clkops_omap2_dflt_wait,
1475 .id = 5, 1503 .id = 5,
1476 .init = &omap2_init_clksel_parent, 1504 .init = &omap2_init_clksel_parent,
1477 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1505 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1486,6 +1514,7 @@ static struct clk mcbsp5_fck = {
1486 1514
1487static struct clk mcbsp1_fck = { 1515static struct clk mcbsp1_fck = {
1488 .name = "mcbsp_fck", 1516 .name = "mcbsp_fck",
1517 .ops = &clkops_omap2_dflt_wait,
1489 .id = 1, 1518 .id = 1,
1490 .init = &omap2_init_clksel_parent, 1519 .init = &omap2_init_clksel_parent,
1491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1520 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1511,6 +1540,7 @@ static struct clk core_48m_fck = {
1511 1540
1512static struct clk mcspi4_fck = { 1541static struct clk mcspi4_fck = {
1513 .name = "mcspi_fck", 1542 .name = "mcspi_fck",
1543 .ops = &clkops_omap2_dflt_wait,
1514 .id = 4, 1544 .id = 4,
1515 .parent = &core_48m_fck, 1545 .parent = &core_48m_fck,
1516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1546 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1521,6 +1551,7 @@ static struct clk mcspi4_fck = {
1521 1551
1522static struct clk mcspi3_fck = { 1552static struct clk mcspi3_fck = {
1523 .name = "mcspi_fck", 1553 .name = "mcspi_fck",
1554 .ops = &clkops_omap2_dflt_wait,
1524 .id = 3, 1555 .id = 3,
1525 .parent = &core_48m_fck, 1556 .parent = &core_48m_fck,
1526 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1557 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1531,6 +1562,7 @@ static struct clk mcspi3_fck = {
1531 1562
1532static struct clk mcspi2_fck = { 1563static struct clk mcspi2_fck = {
1533 .name = "mcspi_fck", 1564 .name = "mcspi_fck",
1565 .ops = &clkops_omap2_dflt_wait,
1534 .id = 2, 1566 .id = 2,
1535 .parent = &core_48m_fck, 1567 .parent = &core_48m_fck,
1536 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1541,6 +1573,7 @@ static struct clk mcspi2_fck = {
1541 1573
1542static struct clk mcspi1_fck = { 1574static struct clk mcspi1_fck = {
1543 .name = "mcspi_fck", 1575 .name = "mcspi_fck",
1576 .ops = &clkops_omap2_dflt_wait,
1544 .id = 1, 1577 .id = 1,
1545 .parent = &core_48m_fck, 1578 .parent = &core_48m_fck,
1546 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1551,6 +1584,7 @@ static struct clk mcspi1_fck = {
1551 1584
1552static struct clk uart2_fck = { 1585static struct clk uart2_fck = {
1553 .name = "uart2_fck", 1586 .name = "uart2_fck",
1587 .ops = &clkops_omap2_dflt_wait,
1554 .parent = &core_48m_fck, 1588 .parent = &core_48m_fck,
1555 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1556 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1590 .enable_bit = OMAP3430_EN_UART2_SHIFT,
@@ -1560,6 +1594,7 @@ static struct clk uart2_fck = {
1560 1594
1561static struct clk uart1_fck = { 1595static struct clk uart1_fck = {
1562 .name = "uart1_fck", 1596 .name = "uart1_fck",
1597 .ops = &clkops_omap2_dflt_wait,
1563 .parent = &core_48m_fck, 1598 .parent = &core_48m_fck,
1564 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1565 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1600 .enable_bit = OMAP3430_EN_UART1_SHIFT,
@@ -1569,6 +1604,7 @@ static struct clk uart1_fck = {
1569 1604
1570static struct clk fshostusb_fck = { 1605static struct clk fshostusb_fck = {
1571 .name = "fshostusb_fck", 1606 .name = "fshostusb_fck",
1607 .ops = &clkops_omap2_dflt_wait,
1572 .parent = &core_48m_fck, 1608 .parent = &core_48m_fck,
1573 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1609 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1574 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, 1610 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
@@ -1589,6 +1625,7 @@ static struct clk core_12m_fck = {
1589 1625
1590static struct clk hdq_fck = { 1626static struct clk hdq_fck = {
1591 .name = "hdq_fck", 1627 .name = "hdq_fck",
1628 .ops = &clkops_omap2_dflt_wait,
1592 .parent = &core_12m_fck, 1629 .parent = &core_12m_fck,
1593 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1630 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1594 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1631 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
@@ -1615,6 +1652,7 @@ static const struct clksel ssi_ssr_clksel[] = {
1615 1652
1616static struct clk ssi_ssr_fck = { 1653static struct clk ssi_ssr_fck = {
1617 .name = "ssi_ssr_fck", 1654 .name = "ssi_ssr_fck",
1655 .ops = &clkops_omap2_dflt_wait,
1618 .init = &omap2_init_clksel_parent, 1656 .init = &omap2_init_clksel_parent,
1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1620 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1658 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -1655,6 +1693,7 @@ static struct clk core_l3_ick = {
1655 1693
1656static struct clk hsotgusb_ick = { 1694static struct clk hsotgusb_ick = {
1657 .name = "hsotgusb_ick", 1695 .name = "hsotgusb_ick",
1696 .ops = &clkops_omap2_dflt_wait,
1658 .parent = &core_l3_ick, 1697 .parent = &core_l3_ick,
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1698 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1660 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1699 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1665,6 +1704,7 @@ static struct clk hsotgusb_ick = {
1665 1704
1666static struct clk sdrc_ick = { 1705static struct clk sdrc_ick = {
1667 .name = "sdrc_ick", 1706 .name = "sdrc_ick",
1707 .ops = &clkops_omap2_dflt_wait,
1668 .parent = &core_l3_ick, 1708 .parent = &core_l3_ick,
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1670 .enable_bit = OMAP3430_EN_SDRC_SHIFT, 1710 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
@@ -1694,6 +1734,7 @@ static struct clk security_l3_ick = {
1694 1734
1695static struct clk pka_ick = { 1735static struct clk pka_ick = {
1696 .name = "pka_ick", 1736 .name = "pka_ick",
1737 .ops = &clkops_omap2_dflt_wait,
1697 .parent = &security_l3_ick, 1738 .parent = &security_l3_ick,
1698 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1739 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1699 .enable_bit = OMAP3430_EN_PKA_SHIFT, 1740 .enable_bit = OMAP3430_EN_PKA_SHIFT,
@@ -1715,6 +1756,7 @@ static struct clk core_l4_ick = {
1715 1756
1716static struct clk usbtll_ick = { 1757static struct clk usbtll_ick = {
1717 .name = "usbtll_ick", 1758 .name = "usbtll_ick",
1759 .ops = &clkops_omap2_dflt_wait,
1718 .parent = &core_l4_ick, 1760 .parent = &core_l4_ick,
1719 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1720 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1762 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -1725,6 +1767,7 @@ static struct clk usbtll_ick = {
1725 1767
1726static struct clk mmchs3_ick = { 1768static struct clk mmchs3_ick = {
1727 .name = "mmchs_ick", 1769 .name = "mmchs_ick",
1770 .ops = &clkops_omap2_dflt_wait,
1728 .id = 2, 1771 .id = 2,
1729 .parent = &core_l4_ick, 1772 .parent = &core_l4_ick,
1730 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1773 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1737,6 +1780,7 @@ static struct clk mmchs3_ick = {
1737/* Intersystem Communication Registers - chassis mode only */ 1780/* Intersystem Communication Registers - chassis mode only */
1738static struct clk icr_ick = { 1781static struct clk icr_ick = {
1739 .name = "icr_ick", 1782 .name = "icr_ick",
1783 .ops = &clkops_omap2_dflt_wait,
1740 .parent = &core_l4_ick, 1784 .parent = &core_l4_ick,
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1785 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1786 .enable_bit = OMAP3430_EN_ICR_SHIFT,
@@ -1747,6 +1791,7 @@ static struct clk icr_ick = {
1747 1791
1748static struct clk aes2_ick = { 1792static struct clk aes2_ick = {
1749 .name = "aes2_ick", 1793 .name = "aes2_ick",
1794 .ops = &clkops_omap2_dflt_wait,
1750 .parent = &core_l4_ick, 1795 .parent = &core_l4_ick,
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1796 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1752 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1797 .enable_bit = OMAP3430_EN_AES2_SHIFT,
@@ -1757,6 +1802,7 @@ static struct clk aes2_ick = {
1757 1802
1758static struct clk sha12_ick = { 1803static struct clk sha12_ick = {
1759 .name = "sha12_ick", 1804 .name = "sha12_ick",
1805 .ops = &clkops_omap2_dflt_wait,
1760 .parent = &core_l4_ick, 1806 .parent = &core_l4_ick,
1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1762 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1808 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
@@ -1767,6 +1813,7 @@ static struct clk sha12_ick = {
1767 1813
1768static struct clk des2_ick = { 1814static struct clk des2_ick = {
1769 .name = "des2_ick", 1815 .name = "des2_ick",
1816 .ops = &clkops_omap2_dflt_wait,
1770 .parent = &core_l4_ick, 1817 .parent = &core_l4_ick,
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1818 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1772 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1819 .enable_bit = OMAP3430_EN_DES2_SHIFT,
@@ -1777,6 +1824,7 @@ static struct clk des2_ick = {
1777 1824
1778static struct clk mmchs2_ick = { 1825static struct clk mmchs2_ick = {
1779 .name = "mmchs_ick", 1826 .name = "mmchs_ick",
1827 .ops = &clkops_omap2_dflt_wait,
1780 .id = 1, 1828 .id = 1,
1781 .parent = &core_l4_ick, 1829 .parent = &core_l4_ick,
1782 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1830 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1788,6 +1836,7 @@ static struct clk mmchs2_ick = {
1788 1836
1789static struct clk mmchs1_ick = { 1837static struct clk mmchs1_ick = {
1790 .name = "mmchs_ick", 1838 .name = "mmchs_ick",
1839 .ops = &clkops_omap2_dflt_wait,
1791 .parent = &core_l4_ick, 1840 .parent = &core_l4_ick,
1792 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1793 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1842 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
@@ -1798,6 +1847,7 @@ static struct clk mmchs1_ick = {
1798 1847
1799static struct clk mspro_ick = { 1848static struct clk mspro_ick = {
1800 .name = "mspro_ick", 1849 .name = "mspro_ick",
1850 .ops = &clkops_omap2_dflt_wait,
1801 .parent = &core_l4_ick, 1851 .parent = &core_l4_ick,
1802 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1803 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1853 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
@@ -1808,6 +1858,7 @@ static struct clk mspro_ick = {
1808 1858
1809static struct clk hdq_ick = { 1859static struct clk hdq_ick = {
1810 .name = "hdq_ick", 1860 .name = "hdq_ick",
1861 .ops = &clkops_omap2_dflt_wait,
1811 .parent = &core_l4_ick, 1862 .parent = &core_l4_ick,
1812 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1863 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1813 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1864 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
@@ -1818,6 +1869,7 @@ static struct clk hdq_ick = {
1818 1869
1819static struct clk mcspi4_ick = { 1870static struct clk mcspi4_ick = {
1820 .name = "mcspi_ick", 1871 .name = "mcspi_ick",
1872 .ops = &clkops_omap2_dflt_wait,
1821 .id = 4, 1873 .id = 4,
1822 .parent = &core_l4_ick, 1874 .parent = &core_l4_ick,
1823 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1875 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1829,6 +1881,7 @@ static struct clk mcspi4_ick = {
1829 1881
1830static struct clk mcspi3_ick = { 1882static struct clk mcspi3_ick = {
1831 .name = "mcspi_ick", 1883 .name = "mcspi_ick",
1884 .ops = &clkops_omap2_dflt_wait,
1832 .id = 3, 1885 .id = 3,
1833 .parent = &core_l4_ick, 1886 .parent = &core_l4_ick,
1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1887 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1840,6 +1893,7 @@ static struct clk mcspi3_ick = {
1840 1893
1841static struct clk mcspi2_ick = { 1894static struct clk mcspi2_ick = {
1842 .name = "mcspi_ick", 1895 .name = "mcspi_ick",
1896 .ops = &clkops_omap2_dflt_wait,
1843 .id = 2, 1897 .id = 2,
1844 .parent = &core_l4_ick, 1898 .parent = &core_l4_ick,
1845 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1899 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1851,6 +1905,7 @@ static struct clk mcspi2_ick = {
1851 1905
1852static struct clk mcspi1_ick = { 1906static struct clk mcspi1_ick = {
1853 .name = "mcspi_ick", 1907 .name = "mcspi_ick",
1908 .ops = &clkops_omap2_dflt_wait,
1854 .id = 1, 1909 .id = 1,
1855 .parent = &core_l4_ick, 1910 .parent = &core_l4_ick,
1856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1862,6 +1917,7 @@ static struct clk mcspi1_ick = {
1862 1917
1863static struct clk i2c3_ick = { 1918static struct clk i2c3_ick = {
1864 .name = "i2c_ick", 1919 .name = "i2c_ick",
1920 .ops = &clkops_omap2_dflt_wait,
1865 .id = 3, 1921 .id = 3,
1866 .parent = &core_l4_ick, 1922 .parent = &core_l4_ick,
1867 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1923 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1873,6 +1929,7 @@ static struct clk i2c3_ick = {
1873 1929
1874static struct clk i2c2_ick = { 1930static struct clk i2c2_ick = {
1875 .name = "i2c_ick", 1931 .name = "i2c_ick",
1932 .ops = &clkops_omap2_dflt_wait,
1876 .id = 2, 1933 .id = 2,
1877 .parent = &core_l4_ick, 1934 .parent = &core_l4_ick,
1878 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1884,6 +1941,7 @@ static struct clk i2c2_ick = {
1884 1941
1885static struct clk i2c1_ick = { 1942static struct clk i2c1_ick = {
1886 .name = "i2c_ick", 1943 .name = "i2c_ick",
1944 .ops = &clkops_omap2_dflt_wait,
1887 .id = 1, 1945 .id = 1,
1888 .parent = &core_l4_ick, 1946 .parent = &core_l4_ick,
1889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1895,6 +1953,7 @@ static struct clk i2c1_ick = {
1895 1953
1896static struct clk uart2_ick = { 1954static struct clk uart2_ick = {
1897 .name = "uart2_ick", 1955 .name = "uart2_ick",
1956 .ops = &clkops_omap2_dflt_wait,
1898 .parent = &core_l4_ick, 1957 .parent = &core_l4_ick,
1899 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1958 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1900 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1959 .enable_bit = OMAP3430_EN_UART2_SHIFT,
@@ -1905,6 +1964,7 @@ static struct clk uart2_ick = {
1905 1964
1906static struct clk uart1_ick = { 1965static struct clk uart1_ick = {
1907 .name = "uart1_ick", 1966 .name = "uart1_ick",
1967 .ops = &clkops_omap2_dflt_wait,
1908 .parent = &core_l4_ick, 1968 .parent = &core_l4_ick,
1909 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1969 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1910 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1970 .enable_bit = OMAP3430_EN_UART1_SHIFT,
@@ -1915,6 +1975,7 @@ static struct clk uart1_ick = {
1915 1975
1916static struct clk gpt11_ick = { 1976static struct clk gpt11_ick = {
1917 .name = "gpt11_ick", 1977 .name = "gpt11_ick",
1978 .ops = &clkops_omap2_dflt_wait,
1918 .parent = &core_l4_ick, 1979 .parent = &core_l4_ick,
1919 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1980 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1920 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1981 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
@@ -1925,6 +1986,7 @@ static struct clk gpt11_ick = {
1925 1986
1926static struct clk gpt10_ick = { 1987static struct clk gpt10_ick = {
1927 .name = "gpt10_ick", 1988 .name = "gpt10_ick",
1989 .ops = &clkops_omap2_dflt_wait,
1928 .parent = &core_l4_ick, 1990 .parent = &core_l4_ick,
1929 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1930 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1992 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
@@ -1935,6 +1997,7 @@ static struct clk gpt10_ick = {
1935 1997
1936static struct clk mcbsp5_ick = { 1998static struct clk mcbsp5_ick = {
1937 .name = "mcbsp_ick", 1999 .name = "mcbsp_ick",
2000 .ops = &clkops_omap2_dflt_wait,
1938 .id = 5, 2001 .id = 5,
1939 .parent = &core_l4_ick, 2002 .parent = &core_l4_ick,
1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2003 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1946,6 +2009,7 @@ static struct clk mcbsp5_ick = {
1946 2009
1947static struct clk mcbsp1_ick = { 2010static struct clk mcbsp1_ick = {
1948 .name = "mcbsp_ick", 2011 .name = "mcbsp_ick",
2012 .ops = &clkops_omap2_dflt_wait,
1949 .id = 1, 2013 .id = 1,
1950 .parent = &core_l4_ick, 2014 .parent = &core_l4_ick,
1951 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1957,6 +2021,7 @@ static struct clk mcbsp1_ick = {
1957 2021
1958static struct clk fac_ick = { 2022static struct clk fac_ick = {
1959 .name = "fac_ick", 2023 .name = "fac_ick",
2024 .ops = &clkops_omap2_dflt_wait,
1960 .parent = &core_l4_ick, 2025 .parent = &core_l4_ick,
1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1962 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 2027 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
@@ -1967,6 +2032,7 @@ static struct clk fac_ick = {
1967 2032
1968static struct clk mailboxes_ick = { 2033static struct clk mailboxes_ick = {
1969 .name = "mailboxes_ick", 2034 .name = "mailboxes_ick",
2035 .ops = &clkops_omap2_dflt_wait,
1970 .parent = &core_l4_ick, 2036 .parent = &core_l4_ick,
1971 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2037 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1972 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 2038 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
@@ -1977,6 +2043,7 @@ static struct clk mailboxes_ick = {
1977 2043
1978static struct clk omapctrl_ick = { 2044static struct clk omapctrl_ick = {
1979 .name = "omapctrl_ick", 2045 .name = "omapctrl_ick",
2046 .ops = &clkops_omap2_dflt_wait,
1980 .parent = &core_l4_ick, 2047 .parent = &core_l4_ick,
1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1982 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, 2049 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
@@ -1997,6 +2064,7 @@ static struct clk ssi_l4_ick = {
1997 2064
1998static struct clk ssi_ick = { 2065static struct clk ssi_ick = {
1999 .name = "ssi_ick", 2066 .name = "ssi_ick",
2067 .ops = &clkops_omap2_dflt_wait,
2000 .parent = &ssi_l4_ick, 2068 .parent = &ssi_l4_ick,
2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2069 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2002 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2070 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2015,6 +2083,7 @@ static const struct clksel usb_l4_clksel[] = {
2015 2083
2016static struct clk usb_l4_ick = { 2084static struct clk usb_l4_ick = {
2017 .name = "usb_l4_ick", 2085 .name = "usb_l4_ick",
2086 .ops = &clkops_omap2_dflt_wait,
2018 .parent = &l4_ick, 2087 .parent = &l4_ick,
2019 .init = &omap2_init_clksel_parent, 2088 .init = &omap2_init_clksel_parent,
2020 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2089 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2040,6 +2109,7 @@ static struct clk security_l4_ick2 = {
2040 2109
2041static struct clk aes1_ick = { 2110static struct clk aes1_ick = {
2042 .name = "aes1_ick", 2111 .name = "aes1_ick",
2112 .ops = &clkops_omap2_dflt_wait,
2043 .parent = &security_l4_ick2, 2113 .parent = &security_l4_ick2,
2044 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2114 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2045 .enable_bit = OMAP3430_EN_AES1_SHIFT, 2115 .enable_bit = OMAP3430_EN_AES1_SHIFT,
@@ -2049,6 +2119,7 @@ static struct clk aes1_ick = {
2049 2119
2050static struct clk rng_ick = { 2120static struct clk rng_ick = {
2051 .name = "rng_ick", 2121 .name = "rng_ick",
2122 .ops = &clkops_omap2_dflt_wait,
2052 .parent = &security_l4_ick2, 2123 .parent = &security_l4_ick2,
2053 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2054 .enable_bit = OMAP3430_EN_RNG_SHIFT, 2125 .enable_bit = OMAP3430_EN_RNG_SHIFT,
@@ -2058,6 +2129,7 @@ static struct clk rng_ick = {
2058 2129
2059static struct clk sha11_ick = { 2130static struct clk sha11_ick = {
2060 .name = "sha11_ick", 2131 .name = "sha11_ick",
2132 .ops = &clkops_omap2_dflt_wait,
2061 .parent = &security_l4_ick2, 2133 .parent = &security_l4_ick2,
2062 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2134 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2063 .enable_bit = OMAP3430_EN_SHA11_SHIFT, 2135 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
@@ -2067,6 +2139,7 @@ static struct clk sha11_ick = {
2067 2139
2068static struct clk des1_ick = { 2140static struct clk des1_ick = {
2069 .name = "des1_ick", 2141 .name = "des1_ick",
2142 .ops = &clkops_omap2_dflt_wait,
2070 .parent = &security_l4_ick2, 2143 .parent = &security_l4_ick2,
2071 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2072 .enable_bit = OMAP3430_EN_DES1_SHIFT, 2145 .enable_bit = OMAP3430_EN_DES1_SHIFT,
@@ -2083,6 +2156,7 @@ static const struct clksel dss1_alwon_fck_clksel[] = {
2083 2156
2084static struct clk dss1_alwon_fck = { 2157static struct clk dss1_alwon_fck = {
2085 .name = "dss1_alwon_fck", 2158 .name = "dss1_alwon_fck",
2159 .ops = &clkops_omap2_dflt_wait,
2086 .parent = &dpll4_m4x2_ck, 2160 .parent = &dpll4_m4x2_ck,
2087 .init = &omap2_init_clksel_parent, 2161 .init = &omap2_init_clksel_parent,
2088 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2162 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
@@ -2097,6 +2171,7 @@ static struct clk dss1_alwon_fck = {
2097 2171
2098static struct clk dss_tv_fck = { 2172static struct clk dss_tv_fck = {
2099 .name = "dss_tv_fck", 2173 .name = "dss_tv_fck",
2174 .ops = &clkops_omap2_dflt_wait,
2100 .parent = &omap_54m_fck, 2175 .parent = &omap_54m_fck,
2101 .init = &omap2_init_clk_clkdm, 2176 .init = &omap2_init_clk_clkdm,
2102 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2177 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
@@ -2108,6 +2183,7 @@ static struct clk dss_tv_fck = {
2108 2183
2109static struct clk dss_96m_fck = { 2184static struct clk dss_96m_fck = {
2110 .name = "dss_96m_fck", 2185 .name = "dss_96m_fck",
2186 .ops = &clkops_omap2_dflt_wait,
2111 .parent = &omap_96m_fck, 2187 .parent = &omap_96m_fck,
2112 .init = &omap2_init_clk_clkdm, 2188 .init = &omap2_init_clk_clkdm,
2113 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2189 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
@@ -2119,6 +2195,7 @@ static struct clk dss_96m_fck = {
2119 2195
2120static struct clk dss2_alwon_fck = { 2196static struct clk dss2_alwon_fck = {
2121 .name = "dss2_alwon_fck", 2197 .name = "dss2_alwon_fck",
2198 .ops = &clkops_omap2_dflt_wait,
2122 .parent = &sys_ck, 2199 .parent = &sys_ck,
2123 .init = &omap2_init_clk_clkdm, 2200 .init = &omap2_init_clk_clkdm,
2124 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2201 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
@@ -2131,6 +2208,7 @@ static struct clk dss2_alwon_fck = {
2131static struct clk dss_ick = { 2208static struct clk dss_ick = {
2132 /* Handles both L3 and L4 clocks */ 2209 /* Handles both L3 and L4 clocks */
2133 .name = "dss_ick", 2210 .name = "dss_ick",
2211 .ops = &clkops_omap2_dflt_wait,
2134 .parent = &l4_ick, 2212 .parent = &l4_ick,
2135 .init = &omap2_init_clk_clkdm, 2213 .init = &omap2_init_clk_clkdm,
2136 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2214 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
@@ -2150,6 +2228,7 @@ static const struct clksel cam_mclk_clksel[] = {
2150 2228
2151static struct clk cam_mclk = { 2229static struct clk cam_mclk = {
2152 .name = "cam_mclk", 2230 .name = "cam_mclk",
2231 .ops = &clkops_omap2_dflt_wait,
2153 .parent = &dpll4_m5x2_ck, 2232 .parent = &dpll4_m5x2_ck,
2154 .init = &omap2_init_clksel_parent, 2233 .init = &omap2_init_clksel_parent,
2155 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 2234 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
@@ -2165,6 +2244,7 @@ static struct clk cam_mclk = {
2165static struct clk cam_ick = { 2244static struct clk cam_ick = {
2166 /* Handles both L3 and L4 clocks */ 2245 /* Handles both L3 and L4 clocks */
2167 .name = "cam_ick", 2246 .name = "cam_ick",
2247 .ops = &clkops_omap2_dflt_wait,
2168 .parent = &l4_ick, 2248 .parent = &l4_ick,
2169 .init = &omap2_init_clk_clkdm, 2249 .init = &omap2_init_clk_clkdm,
2170 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2250 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
@@ -2178,6 +2258,7 @@ static struct clk cam_ick = {
2178 2258
2179static struct clk usbhost_120m_fck = { 2259static struct clk usbhost_120m_fck = {
2180 .name = "usbhost_120m_fck", 2260 .name = "usbhost_120m_fck",
2261 .ops = &clkops_omap2_dflt_wait,
2181 .parent = &omap_120m_fck, 2262 .parent = &omap_120m_fck,
2182 .init = &omap2_init_clk_clkdm, 2263 .init = &omap2_init_clk_clkdm,
2183 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2264 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2189,6 +2270,7 @@ static struct clk usbhost_120m_fck = {
2189 2270
2190static struct clk usbhost_48m_fck = { 2271static struct clk usbhost_48m_fck = {
2191 .name = "usbhost_48m_fck", 2272 .name = "usbhost_48m_fck",
2273 .ops = &clkops_omap2_dflt_wait,
2192 .parent = &omap_48m_fck, 2274 .parent = &omap_48m_fck,
2193 .init = &omap2_init_clk_clkdm, 2275 .init = &omap2_init_clk_clkdm,
2194 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2276 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2201,6 +2283,7 @@ static struct clk usbhost_48m_fck = {
2201static struct clk usbhost_ick = { 2283static struct clk usbhost_ick = {
2202 /* Handles both L3 and L4 clocks */ 2284 /* Handles both L3 and L4 clocks */
2203 .name = "usbhost_ick", 2285 .name = "usbhost_ick",
2286 .ops = &clkops_omap2_dflt_wait,
2204 .parent = &l4_ick, 2287 .parent = &l4_ick,
2205 .init = &omap2_init_clk_clkdm, 2288 .init = &omap2_init_clk_clkdm,
2206 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2289 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
@@ -2212,6 +2295,7 @@ static struct clk usbhost_ick = {
2212 2295
2213static struct clk usbhost_sar_fck = { 2296static struct clk usbhost_sar_fck = {
2214 .name = "usbhost_sar_fck", 2297 .name = "usbhost_sar_fck",
2298 .ops = &clkops_omap2_dflt_wait,
2215 .parent = &osc_sys_ck, 2299 .parent = &osc_sys_ck,
2216 .init = &omap2_init_clk_clkdm, 2300 .init = &omap2_init_clk_clkdm,
2217 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), 2301 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
@@ -2249,6 +2333,7 @@ static const struct clksel usim_clksel[] = {
2249/* 3430ES2 only */ 2333/* 3430ES2 only */
2250static struct clk usim_fck = { 2334static struct clk usim_fck = {
2251 .name = "usim_fck", 2335 .name = "usim_fck",
2336 .ops = &clkops_omap2_dflt_wait,
2252 .init = &omap2_init_clksel_parent, 2337 .init = &omap2_init_clksel_parent,
2253 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2338 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2254 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2339 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2262,6 +2347,7 @@ static struct clk usim_fck = {
2262/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ 2347/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2263static struct clk gpt1_fck = { 2348static struct clk gpt1_fck = {
2264 .name = "gpt1_fck", 2349 .name = "gpt1_fck",
2350 .ops = &clkops_omap2_dflt_wait,
2265 .init = &omap2_init_clksel_parent, 2351 .init = &omap2_init_clksel_parent,
2266 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2352 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2267 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2353 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
@@ -2285,6 +2371,7 @@ static struct clk wkup_32k_fck = {
2285 2371
2286static struct clk gpio1_dbck = { 2372static struct clk gpio1_dbck = {
2287 .name = "gpio1_dbck", 2373 .name = "gpio1_dbck",
2374 .ops = &clkops_omap2_dflt_wait,
2288 .parent = &wkup_32k_fck, 2375 .parent = &wkup_32k_fck,
2289 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2290 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2377 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2295,6 +2382,7 @@ static struct clk gpio1_dbck = {
2295 2382
2296static struct clk wdt2_fck = { 2383static struct clk wdt2_fck = {
2297 .name = "wdt2_fck", 2384 .name = "wdt2_fck",
2385 .ops = &clkops_omap2_dflt_wait,
2298 .parent = &wkup_32k_fck, 2386 .parent = &wkup_32k_fck,
2299 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2387 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2300 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2388 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
@@ -2316,6 +2404,7 @@ static struct clk wkup_l4_ick = {
2316/* Never specifically named in the TRM, so we have to infer a likely name */ 2404/* Never specifically named in the TRM, so we have to infer a likely name */
2317static struct clk usim_ick = { 2405static struct clk usim_ick = {
2318 .name = "usim_ick", 2406 .name = "usim_ick",
2407 .ops = &clkops_omap2_dflt_wait,
2319 .parent = &wkup_l4_ick, 2408 .parent = &wkup_l4_ick,
2320 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2409 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2321 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2410 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2326,6 +2415,7 @@ static struct clk usim_ick = {
2326 2415
2327static struct clk wdt2_ick = { 2416static struct clk wdt2_ick = {
2328 .name = "wdt2_ick", 2417 .name = "wdt2_ick",
2418 .ops = &clkops_omap2_dflt_wait,
2329 .parent = &wkup_l4_ick, 2419 .parent = &wkup_l4_ick,
2330 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2420 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2331 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2421 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
@@ -2336,6 +2426,7 @@ static struct clk wdt2_ick = {
2336 2426
2337static struct clk wdt1_ick = { 2427static struct clk wdt1_ick = {
2338 .name = "wdt1_ick", 2428 .name = "wdt1_ick",
2429 .ops = &clkops_omap2_dflt_wait,
2339 .parent = &wkup_l4_ick, 2430 .parent = &wkup_l4_ick,
2340 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2431 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2341 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2432 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
@@ -2346,6 +2437,7 @@ static struct clk wdt1_ick = {
2346 2437
2347static struct clk gpio1_ick = { 2438static struct clk gpio1_ick = {
2348 .name = "gpio1_ick", 2439 .name = "gpio1_ick",
2440 .ops = &clkops_omap2_dflt_wait,
2349 .parent = &wkup_l4_ick, 2441 .parent = &wkup_l4_ick,
2350 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2442 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2351 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2443 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2356,6 +2448,7 @@ static struct clk gpio1_ick = {
2356 2448
2357static struct clk omap_32ksync_ick = { 2449static struct clk omap_32ksync_ick = {
2358 .name = "omap_32ksync_ick", 2450 .name = "omap_32ksync_ick",
2451 .ops = &clkops_omap2_dflt_wait,
2359 .parent = &wkup_l4_ick, 2452 .parent = &wkup_l4_ick,
2360 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2453 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2361 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2454 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
@@ -2367,6 +2460,7 @@ static struct clk omap_32ksync_ick = {
2367/* XXX This clock no longer exists in 3430 TRM rev F */ 2460/* XXX This clock no longer exists in 3430 TRM rev F */
2368static struct clk gpt12_ick = { 2461static struct clk gpt12_ick = {
2369 .name = "gpt12_ick", 2462 .name = "gpt12_ick",
2463 .ops = &clkops_omap2_dflt_wait,
2370 .parent = &wkup_l4_ick, 2464 .parent = &wkup_l4_ick,
2371 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2465 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2372 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2466 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
@@ -2377,6 +2471,7 @@ static struct clk gpt12_ick = {
2377 2471
2378static struct clk gpt1_ick = { 2472static struct clk gpt1_ick = {
2379 .name = "gpt1_ick", 2473 .name = "gpt1_ick",
2474 .ops = &clkops_omap2_dflt_wait,
2380 .parent = &wkup_l4_ick, 2475 .parent = &wkup_l4_ick,
2381 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2476 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2382 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2477 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
@@ -2411,6 +2506,7 @@ static struct clk per_48m_fck = {
2411 2506
2412static struct clk uart3_fck = { 2507static struct clk uart3_fck = {
2413 .name = "uart3_fck", 2508 .name = "uart3_fck",
2509 .ops = &clkops_omap2_dflt_wait,
2414 .parent = &per_48m_fck, 2510 .parent = &per_48m_fck,
2415 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2511 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2416 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2512 .enable_bit = OMAP3430_EN_UART3_SHIFT,
@@ -2421,6 +2517,7 @@ static struct clk uart3_fck = {
2421 2517
2422static struct clk gpt2_fck = { 2518static struct clk gpt2_fck = {
2423 .name = "gpt2_fck", 2519 .name = "gpt2_fck",
2520 .ops = &clkops_omap2_dflt_wait,
2424 .init = &omap2_init_clksel_parent, 2521 .init = &omap2_init_clksel_parent,
2425 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2522 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2426 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2523 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
@@ -2434,6 +2531,7 @@ static struct clk gpt2_fck = {
2434 2531
2435static struct clk gpt3_fck = { 2532static struct clk gpt3_fck = {
2436 .name = "gpt3_fck", 2533 .name = "gpt3_fck",
2534 .ops = &clkops_omap2_dflt_wait,
2437 .init = &omap2_init_clksel_parent, 2535 .init = &omap2_init_clksel_parent,
2438 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2536 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2439 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2537 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
@@ -2447,6 +2545,7 @@ static struct clk gpt3_fck = {
2447 2545
2448static struct clk gpt4_fck = { 2546static struct clk gpt4_fck = {
2449 .name = "gpt4_fck", 2547 .name = "gpt4_fck",
2548 .ops = &clkops_omap2_dflt_wait,
2450 .init = &omap2_init_clksel_parent, 2549 .init = &omap2_init_clksel_parent,
2451 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2550 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2452 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2551 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
@@ -2460,6 +2559,7 @@ static struct clk gpt4_fck = {
2460 2559
2461static struct clk gpt5_fck = { 2560static struct clk gpt5_fck = {
2462 .name = "gpt5_fck", 2561 .name = "gpt5_fck",
2562 .ops = &clkops_omap2_dflt_wait,
2463 .init = &omap2_init_clksel_parent, 2563 .init = &omap2_init_clksel_parent,
2464 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2564 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2465 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2565 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
@@ -2473,6 +2573,7 @@ static struct clk gpt5_fck = {
2473 2573
2474static struct clk gpt6_fck = { 2574static struct clk gpt6_fck = {
2475 .name = "gpt6_fck", 2575 .name = "gpt6_fck",
2576 .ops = &clkops_omap2_dflt_wait,
2476 .init = &omap2_init_clksel_parent, 2577 .init = &omap2_init_clksel_parent,
2477 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2578 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2478 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2579 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
@@ -2486,6 +2587,7 @@ static struct clk gpt6_fck = {
2486 2587
2487static struct clk gpt7_fck = { 2588static struct clk gpt7_fck = {
2488 .name = "gpt7_fck", 2589 .name = "gpt7_fck",
2590 .ops = &clkops_omap2_dflt_wait,
2489 .init = &omap2_init_clksel_parent, 2591 .init = &omap2_init_clksel_parent,
2490 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2592 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2491 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2593 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
@@ -2499,6 +2601,7 @@ static struct clk gpt7_fck = {
2499 2601
2500static struct clk gpt8_fck = { 2602static struct clk gpt8_fck = {
2501 .name = "gpt8_fck", 2603 .name = "gpt8_fck",
2604 .ops = &clkops_omap2_dflt_wait,
2502 .init = &omap2_init_clksel_parent, 2605 .init = &omap2_init_clksel_parent,
2503 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2606 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2504 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2607 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
@@ -2512,6 +2615,7 @@ static struct clk gpt8_fck = {
2512 2615
2513static struct clk gpt9_fck = { 2616static struct clk gpt9_fck = {
2514 .name = "gpt9_fck", 2617 .name = "gpt9_fck",
2618 .ops = &clkops_omap2_dflt_wait,
2515 .init = &omap2_init_clksel_parent, 2619 .init = &omap2_init_clksel_parent,
2516 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2517 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2621 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
@@ -2534,6 +2638,7 @@ static struct clk per_32k_alwon_fck = {
2534 2638
2535static struct clk gpio6_dbck = { 2639static struct clk gpio6_dbck = {
2536 .name = "gpio6_dbck", 2640 .name = "gpio6_dbck",
2641 .ops = &clkops_omap2_dflt_wait,
2537 .parent = &per_32k_alwon_fck, 2642 .parent = &per_32k_alwon_fck,
2538 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2643 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2539 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2644 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2544,6 +2649,7 @@ static struct clk gpio6_dbck = {
2544 2649
2545static struct clk gpio5_dbck = { 2650static struct clk gpio5_dbck = {
2546 .name = "gpio5_dbck", 2651 .name = "gpio5_dbck",
2652 .ops = &clkops_omap2_dflt_wait,
2547 .parent = &per_32k_alwon_fck, 2653 .parent = &per_32k_alwon_fck,
2548 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2654 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2549 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2655 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2554,6 +2660,7 @@ static struct clk gpio5_dbck = {
2554 2660
2555static struct clk gpio4_dbck = { 2661static struct clk gpio4_dbck = {
2556 .name = "gpio4_dbck", 2662 .name = "gpio4_dbck",
2663 .ops = &clkops_omap2_dflt_wait,
2557 .parent = &per_32k_alwon_fck, 2664 .parent = &per_32k_alwon_fck,
2558 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2665 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2559 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2666 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2564,6 +2671,7 @@ static struct clk gpio4_dbck = {
2564 2671
2565static struct clk gpio3_dbck = { 2672static struct clk gpio3_dbck = {
2566 .name = "gpio3_dbck", 2673 .name = "gpio3_dbck",
2674 .ops = &clkops_omap2_dflt_wait,
2567 .parent = &per_32k_alwon_fck, 2675 .parent = &per_32k_alwon_fck,
2568 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2676 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2569 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2677 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2574,6 +2682,7 @@ static struct clk gpio3_dbck = {
2574 2682
2575static struct clk gpio2_dbck = { 2683static struct clk gpio2_dbck = {
2576 .name = "gpio2_dbck", 2684 .name = "gpio2_dbck",
2685 .ops = &clkops_omap2_dflt_wait,
2577 .parent = &per_32k_alwon_fck, 2686 .parent = &per_32k_alwon_fck,
2578 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2687 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2579 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2688 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -2584,6 +2693,7 @@ static struct clk gpio2_dbck = {
2584 2693
2585static struct clk wdt3_fck = { 2694static struct clk wdt3_fck = {
2586 .name = "wdt3_fck", 2695 .name = "wdt3_fck",
2696 .ops = &clkops_omap2_dflt_wait,
2587 .parent = &per_32k_alwon_fck, 2697 .parent = &per_32k_alwon_fck,
2588 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2698 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2589 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2699 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
@@ -2603,6 +2713,7 @@ static struct clk per_l4_ick = {
2603 2713
2604static struct clk gpio6_ick = { 2714static struct clk gpio6_ick = {
2605 .name = "gpio6_ick", 2715 .name = "gpio6_ick",
2716 .ops = &clkops_omap2_dflt_wait,
2606 .parent = &per_l4_ick, 2717 .parent = &per_l4_ick,
2607 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2718 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2608 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2719 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2613,6 +2724,7 @@ static struct clk gpio6_ick = {
2613 2724
2614static struct clk gpio5_ick = { 2725static struct clk gpio5_ick = {
2615 .name = "gpio5_ick", 2726 .name = "gpio5_ick",
2727 .ops = &clkops_omap2_dflt_wait,
2616 .parent = &per_l4_ick, 2728 .parent = &per_l4_ick,
2617 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2729 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2618 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2730 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2623,6 +2735,7 @@ static struct clk gpio5_ick = {
2623 2735
2624static struct clk gpio4_ick = { 2736static struct clk gpio4_ick = {
2625 .name = "gpio4_ick", 2737 .name = "gpio4_ick",
2738 .ops = &clkops_omap2_dflt_wait,
2626 .parent = &per_l4_ick, 2739 .parent = &per_l4_ick,
2627 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2740 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2628 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2741 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2633,6 +2746,7 @@ static struct clk gpio4_ick = {
2633 2746
2634static struct clk gpio3_ick = { 2747static struct clk gpio3_ick = {
2635 .name = "gpio3_ick", 2748 .name = "gpio3_ick",
2749 .ops = &clkops_omap2_dflt_wait,
2636 .parent = &per_l4_ick, 2750 .parent = &per_l4_ick,
2637 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2751 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2638 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2752 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2643,6 +2757,7 @@ static struct clk gpio3_ick = {
2643 2757
2644static struct clk gpio2_ick = { 2758static struct clk gpio2_ick = {
2645 .name = "gpio2_ick", 2759 .name = "gpio2_ick",
2760 .ops = &clkops_omap2_dflt_wait,
2646 .parent = &per_l4_ick, 2761 .parent = &per_l4_ick,
2647 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2762 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2648 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2763 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -2653,6 +2768,7 @@ static struct clk gpio2_ick = {
2653 2768
2654static struct clk wdt3_ick = { 2769static struct clk wdt3_ick = {
2655 .name = "wdt3_ick", 2770 .name = "wdt3_ick",
2771 .ops = &clkops_omap2_dflt_wait,
2656 .parent = &per_l4_ick, 2772 .parent = &per_l4_ick,
2657 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2773 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2658 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2774 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
@@ -2663,6 +2779,7 @@ static struct clk wdt3_ick = {
2663 2779
2664static struct clk uart3_ick = { 2780static struct clk uart3_ick = {
2665 .name = "uart3_ick", 2781 .name = "uart3_ick",
2782 .ops = &clkops_omap2_dflt_wait,
2666 .parent = &per_l4_ick, 2783 .parent = &per_l4_ick,
2667 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2784 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2668 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2785 .enable_bit = OMAP3430_EN_UART3_SHIFT,
@@ -2673,6 +2790,7 @@ static struct clk uart3_ick = {
2673 2790
2674static struct clk gpt9_ick = { 2791static struct clk gpt9_ick = {
2675 .name = "gpt9_ick", 2792 .name = "gpt9_ick",
2793 .ops = &clkops_omap2_dflt_wait,
2676 .parent = &per_l4_ick, 2794 .parent = &per_l4_ick,
2677 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2795 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2678 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2796 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
@@ -2683,6 +2801,7 @@ static struct clk gpt9_ick = {
2683 2801
2684static struct clk gpt8_ick = { 2802static struct clk gpt8_ick = {
2685 .name = "gpt8_ick", 2803 .name = "gpt8_ick",
2804 .ops = &clkops_omap2_dflt_wait,
2686 .parent = &per_l4_ick, 2805 .parent = &per_l4_ick,
2687 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2806 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2688 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2807 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
@@ -2693,6 +2812,7 @@ static struct clk gpt8_ick = {
2693 2812
2694static struct clk gpt7_ick = { 2813static struct clk gpt7_ick = {
2695 .name = "gpt7_ick", 2814 .name = "gpt7_ick",
2815 .ops = &clkops_omap2_dflt_wait,
2696 .parent = &per_l4_ick, 2816 .parent = &per_l4_ick,
2697 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2817 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2698 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2818 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
@@ -2703,6 +2823,7 @@ static struct clk gpt7_ick = {
2703 2823
2704static struct clk gpt6_ick = { 2824static struct clk gpt6_ick = {
2705 .name = "gpt6_ick", 2825 .name = "gpt6_ick",
2826 .ops = &clkops_omap2_dflt_wait,
2706 .parent = &per_l4_ick, 2827 .parent = &per_l4_ick,
2707 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2828 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2708 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2829 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
@@ -2713,6 +2834,7 @@ static struct clk gpt6_ick = {
2713 2834
2714static struct clk gpt5_ick = { 2835static struct clk gpt5_ick = {
2715 .name = "gpt5_ick", 2836 .name = "gpt5_ick",
2837 .ops = &clkops_omap2_dflt_wait,
2716 .parent = &per_l4_ick, 2838 .parent = &per_l4_ick,
2717 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2839 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2718 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2840 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
@@ -2723,6 +2845,7 @@ static struct clk gpt5_ick = {
2723 2845
2724static struct clk gpt4_ick = { 2846static struct clk gpt4_ick = {
2725 .name = "gpt4_ick", 2847 .name = "gpt4_ick",
2848 .ops = &clkops_omap2_dflt_wait,
2726 .parent = &per_l4_ick, 2849 .parent = &per_l4_ick,
2727 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2850 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2728 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2851 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
@@ -2733,6 +2856,7 @@ static struct clk gpt4_ick = {
2733 2856
2734static struct clk gpt3_ick = { 2857static struct clk gpt3_ick = {
2735 .name = "gpt3_ick", 2858 .name = "gpt3_ick",
2859 .ops = &clkops_omap2_dflt_wait,
2736 .parent = &per_l4_ick, 2860 .parent = &per_l4_ick,
2737 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2861 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2738 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2862 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
@@ -2743,6 +2867,7 @@ static struct clk gpt3_ick = {
2743 2867
2744static struct clk gpt2_ick = { 2868static struct clk gpt2_ick = {
2745 .name = "gpt2_ick", 2869 .name = "gpt2_ick",
2870 .ops = &clkops_omap2_dflt_wait,
2746 .parent = &per_l4_ick, 2871 .parent = &per_l4_ick,
2747 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2872 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2748 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2873 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
@@ -2753,6 +2878,7 @@ static struct clk gpt2_ick = {
2753 2878
2754static struct clk mcbsp2_ick = { 2879static struct clk mcbsp2_ick = {
2755 .name = "mcbsp_ick", 2880 .name = "mcbsp_ick",
2881 .ops = &clkops_omap2_dflt_wait,
2756 .id = 2, 2882 .id = 2,
2757 .parent = &per_l4_ick, 2883 .parent = &per_l4_ick,
2758 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2884 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
@@ -2764,6 +2890,7 @@ static struct clk mcbsp2_ick = {
2764 2890
2765static struct clk mcbsp3_ick = { 2891static struct clk mcbsp3_ick = {
2766 .name = "mcbsp_ick", 2892 .name = "mcbsp_ick",
2893 .ops = &clkops_omap2_dflt_wait,
2767 .id = 3, 2894 .id = 3,
2768 .parent = &per_l4_ick, 2895 .parent = &per_l4_ick,
2769 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2896 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
@@ -2775,6 +2902,7 @@ static struct clk mcbsp3_ick = {
2775 2902
2776static struct clk mcbsp4_ick = { 2903static struct clk mcbsp4_ick = {
2777 .name = "mcbsp_ick", 2904 .name = "mcbsp_ick",
2905 .ops = &clkops_omap2_dflt_wait,
2778 .id = 4, 2906 .id = 4,
2779 .parent = &per_l4_ick, 2907 .parent = &per_l4_ick,
2780 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2908 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
@@ -2792,6 +2920,7 @@ static const struct clksel mcbsp_234_clksel[] = {
2792 2920
2793static struct clk mcbsp2_fck = { 2921static struct clk mcbsp2_fck = {
2794 .name = "mcbsp_fck", 2922 .name = "mcbsp_fck",
2923 .ops = &clkops_omap2_dflt_wait,
2795 .id = 2, 2924 .id = 2,
2796 .init = &omap2_init_clksel_parent, 2925 .init = &omap2_init_clksel_parent,
2797 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2926 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2806,6 +2935,7 @@ static struct clk mcbsp2_fck = {
2806 2935
2807static struct clk mcbsp3_fck = { 2936static struct clk mcbsp3_fck = {
2808 .name = "mcbsp_fck", 2937 .name = "mcbsp_fck",
2938 .ops = &clkops_omap2_dflt_wait,
2809 .id = 3, 2939 .id = 3,
2810 .init = &omap2_init_clksel_parent, 2940 .init = &omap2_init_clksel_parent,
2811 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2941 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2820,6 +2950,7 @@ static struct clk mcbsp3_fck = {
2820 2950
2821static struct clk mcbsp4_fck = { 2951static struct clk mcbsp4_fck = {
2822 .name = "mcbsp_fck", 2952 .name = "mcbsp_fck",
2953 .ops = &clkops_omap2_dflt_wait,
2823 .id = 4, 2954 .id = 4,
2824 .init = &omap2_init_clksel_parent, 2955 .init = &omap2_init_clksel_parent,
2825 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2956 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2988,6 +3119,7 @@ static struct clk traceclk_fck = {
2988/* SmartReflex fclk (VDD1) */ 3119/* SmartReflex fclk (VDD1) */
2989static struct clk sr1_fck = { 3120static struct clk sr1_fck = {
2990 .name = "sr1_fck", 3121 .name = "sr1_fck",
3122 .ops = &clkops_omap2_dflt_wait,
2991 .parent = &sys_ck, 3123 .parent = &sys_ck,
2992 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 3124 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2993 .enable_bit = OMAP3430_EN_SR1_SHIFT, 3125 .enable_bit = OMAP3430_EN_SR1_SHIFT,
@@ -2998,6 +3130,7 @@ static struct clk sr1_fck = {
2998/* SmartReflex fclk (VDD2) */ 3130/* SmartReflex fclk (VDD2) */
2999static struct clk sr2_fck = { 3131static struct clk sr2_fck = {
3000 .name = "sr2_fck", 3132 .name = "sr2_fck",
3133 .ops = &clkops_omap2_dflt_wait,
3001 .parent = &sys_ck, 3134 .parent = &sys_ck,
3002 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 3135 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3003 .enable_bit = OMAP3430_EN_SR2_SHIFT, 3136 .enable_bit = OMAP3430_EN_SR2_SHIFT,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 05:49:40 -0500