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-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c124
1 files changed, 11 insertions, 113 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 1abfefff703b..8c7ab76bc70c 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -39,42 +39,42 @@ static struct clk extalt_clkin_ck = {
39 .name = "extalt_clkin_ck", 39 .name = "extalt_clkin_ck",
40 .rate = 59000000, 40 .rate = 59000000,
41 .ops = &clkops_null, 41 .ops = &clkops_null,
42 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 42 .flags = ALWAYS_ENABLED,
43}; 43};
44 44
45static struct clk pad_clks_ck = { 45static struct clk pad_clks_ck = {
46 .name = "pad_clks_ck", 46 .name = "pad_clks_ck",
47 .rate = 12000000, 47 .rate = 12000000,
48 .ops = &clkops_null, 48 .ops = &clkops_null,
49 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 49 .flags = ALWAYS_ENABLED,
50}; 50};
51 51
52static struct clk pad_slimbus_core_clks_ck = { 52static struct clk pad_slimbus_core_clks_ck = {
53 .name = "pad_slimbus_core_clks_ck", 53 .name = "pad_slimbus_core_clks_ck",
54 .rate = 12000000, 54 .rate = 12000000,
55 .ops = &clkops_null, 55 .ops = &clkops_null,
56 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 56 .flags = ALWAYS_ENABLED,
57}; 57};
58 58
59static struct clk secure_32k_clk_src_ck = { 59static struct clk secure_32k_clk_src_ck = {
60 .name = "secure_32k_clk_src_ck", 60 .name = "secure_32k_clk_src_ck",
61 .rate = 32768, 61 .rate = 32768,
62 .ops = &clkops_null, 62 .ops = &clkops_null,
63 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 63 .flags = ALWAYS_ENABLED,
64}; 64};
65 65
66static struct clk slimbus_clk = { 66static struct clk slimbus_clk = {
67 .name = "slimbus_clk", 67 .name = "slimbus_clk",
68 .rate = 12000000, 68 .rate = 12000000,
69 .ops = &clkops_null, 69 .ops = &clkops_null,
70 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 70 .flags = ALWAYS_ENABLED,
71}; 71};
72 72
73static struct clk sys_32k_ck = { 73static struct clk sys_32k_ck = {
74 .name = "sys_32k_ck", 74 .name = "sys_32k_ck",
75 .rate = 32768, 75 .rate = 32768,
76 .ops = &clkops_null, 76 .ops = &clkops_null,
77 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 77 .flags = ALWAYS_ENABLED,
78}; 78};
79 79
80static struct clk virt_12000000_ck = { 80static struct clk virt_12000000_ck = {
@@ -179,35 +179,35 @@ static struct clk sys_clkin_ck = {
179 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, 179 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
180 .ops = &clkops_null, 180 .ops = &clkops_null,
181 .recalc = &omap2_clksel_recalc, 181 .recalc = &omap2_clksel_recalc,
182 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 182 .flags = ALWAYS_ENABLED,
183}; 183};
184 184
185static struct clk utmi_phy_clkout_ck = { 185static struct clk utmi_phy_clkout_ck = {
186 .name = "utmi_phy_clkout_ck", 186 .name = "utmi_phy_clkout_ck",
187 .rate = 12000000, 187 .rate = 12000000,
188 .ops = &clkops_null, 188 .ops = &clkops_null,
189 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 189 .flags = ALWAYS_ENABLED,
190}; 190};
191 191
192static struct clk xclk60mhsp1_ck = { 192static struct clk xclk60mhsp1_ck = {
193 .name = "xclk60mhsp1_ck", 193 .name = "xclk60mhsp1_ck",
194 .rate = 12000000, 194 .rate = 12000000,
195 .ops = &clkops_null, 195 .ops = &clkops_null,
196 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 196 .flags = ALWAYS_ENABLED,
197}; 197};
198 198
199static struct clk xclk60mhsp2_ck = { 199static struct clk xclk60mhsp2_ck = {
200 .name = "xclk60mhsp2_ck", 200 .name = "xclk60mhsp2_ck",
201 .rate = 12000000, 201 .rate = 12000000,
202 .ops = &clkops_null, 202 .ops = &clkops_null,
203 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 203 .flags = ALWAYS_ENABLED,
204}; 204};
205 205
206static struct clk xclk60motg_ck = { 206static struct clk xclk60motg_ck = {
207 .name = "xclk60motg_ck", 207 .name = "xclk60motg_ck",
208 .rate = 60000000, 208 .rate = 60000000,
209 .ops = &clkops_null, 209 .ops = &clkops_null,
210 .flags = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED, 210 .flags = ALWAYS_ENABLED,
211}; 211};
212 212
213/* Module clocks and DPLL outputs */ 213/* Module clocks and DPLL outputs */
@@ -233,7 +233,6 @@ static struct clk dpll_sys_ref_clk = {
233 .recalc = &omap2_clksel_recalc, 233 .recalc = &omap2_clksel_recalc,
234 .round_rate = &omap2_clksel_round_rate, 234 .round_rate = &omap2_clksel_round_rate,
235 .set_rate = &omap2_clksel_set_rate, 235 .set_rate = &omap2_clksel_set_rate,
236 .flags = CLOCK_IN_OMAP4430,
237}; 236};
238 237
239static const struct clksel abe_dpll_refclk_mux_sel[] = { 238static const struct clksel abe_dpll_refclk_mux_sel[] = {
@@ -251,7 +250,6 @@ static struct clk abe_dpll_refclk_mux_ck = {
251 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 250 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
252 .ops = &clkops_null, 251 .ops = &clkops_null,
253 .recalc = &omap2_clksel_recalc, 252 .recalc = &omap2_clksel_recalc,
254 .flags = CLOCK_IN_OMAP4430,
255}; 253};
256 254
257/* DPLL_ABE */ 255/* DPLL_ABE */
@@ -283,7 +281,6 @@ static struct clk dpll_abe_ck = {
283 .recalc = &omap3_dpll_recalc, 281 .recalc = &omap3_dpll_recalc,
284 .round_rate = &omap2_dpll_round_rate, 282 .round_rate = &omap2_dpll_round_rate,
285 .set_rate = &omap3_noncore_dpll_set_rate, 283 .set_rate = &omap3_noncore_dpll_set_rate,
286 .flags = CLOCK_IN_OMAP4430,
287}; 284};
288 285
289static struct clk dpll_abe_m2x2_ck = { 286static struct clk dpll_abe_m2x2_ck = {
@@ -291,7 +288,6 @@ static struct clk dpll_abe_m2x2_ck = {
291 .parent = &dpll_abe_ck, 288 .parent = &dpll_abe_ck,
292 .ops = &clkops_null, 289 .ops = &clkops_null,
293 .recalc = &followparent_recalc, 290 .recalc = &followparent_recalc,
294 .flags = CLOCK_IN_OMAP4430,
295}; 291};
296 292
297static struct clk abe_24m_fclk = { 293static struct clk abe_24m_fclk = {
@@ -299,7 +295,6 @@ static struct clk abe_24m_fclk = {
299 .parent = &dpll_abe_m2x2_ck, 295 .parent = &dpll_abe_m2x2_ck,
300 .ops = &clkops_null, 296 .ops = &clkops_null,
301 .recalc = &followparent_recalc, 297 .recalc = &followparent_recalc,
302 .flags = CLOCK_IN_OMAP4430,
303}; 298};
304 299
305static const struct clksel_rate div3_1to4_rates[] = { 300static const struct clksel_rate div3_1to4_rates[] = {
@@ -324,7 +319,6 @@ static struct clk abe_clk = {
324 .recalc = &omap2_clksel_recalc, 319 .recalc = &omap2_clksel_recalc,
325 .round_rate = &omap2_clksel_round_rate, 320 .round_rate = &omap2_clksel_round_rate,
326 .set_rate = &omap2_clksel_set_rate, 321 .set_rate = &omap2_clksel_set_rate,
327 .flags = CLOCK_IN_OMAP4430,
328}; 322};
329 323
330static const struct clksel aess_fclk_div[] = { 324static const struct clksel aess_fclk_div[] = {
@@ -342,7 +336,6 @@ static struct clk aess_fclk = {
342 .recalc = &omap2_clksel_recalc, 336 .recalc = &omap2_clksel_recalc,
343 .round_rate = &omap2_clksel_round_rate, 337 .round_rate = &omap2_clksel_round_rate,
344 .set_rate = &omap2_clksel_set_rate, 338 .set_rate = &omap2_clksel_set_rate,
345 .flags = CLOCK_IN_OMAP4430,
346}; 339};
347 340
348static const struct clksel_rate div31_1to31_rates[] = { 341static const struct clksel_rate div31_1to31_rates[] = {
@@ -395,7 +388,6 @@ static struct clk dpll_abe_m3_ck = {
395 .recalc = &omap2_clksel_recalc, 388 .recalc = &omap2_clksel_recalc,
396 .round_rate = &omap2_clksel_round_rate, 389 .round_rate = &omap2_clksel_round_rate,
397 .set_rate = &omap2_clksel_set_rate, 390 .set_rate = &omap2_clksel_set_rate,
398 .flags = CLOCK_IN_OMAP4430,
399}; 391};
400 392
401static const struct clksel core_hsd_byp_clk_mux_sel[] = { 393static const struct clksel core_hsd_byp_clk_mux_sel[] = {
@@ -413,7 +405,6 @@ static struct clk core_hsd_byp_clk_mux_ck = {
413 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, 405 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
414 .ops = &clkops_null, 406 .ops = &clkops_null,
415 .recalc = &omap2_clksel_recalc, 407 .recalc = &omap2_clksel_recalc,
416 .flags = CLOCK_IN_OMAP4430,
417}; 408};
418 409
419/* DPLL_CORE */ 410/* DPLL_CORE */
@@ -443,7 +434,6 @@ static struct clk dpll_core_ck = {
443 .init = &omap2_init_dpll_parent, 434 .init = &omap2_init_dpll_parent,
444 .ops = &clkops_null, 435 .ops = &clkops_null,
445 .recalc = &omap3_dpll_recalc, 436 .recalc = &omap3_dpll_recalc,
446 .flags = CLOCK_IN_OMAP4430,
447}; 437};
448 438
449static const struct clksel dpll_core_m6_div[] = { 439static const struct clksel dpll_core_m6_div[] = {
@@ -461,7 +451,6 @@ static struct clk dpll_core_m6_ck = {
461 .recalc = &omap2_clksel_recalc, 451 .recalc = &omap2_clksel_recalc,
462 .round_rate = &omap2_clksel_round_rate, 452 .round_rate = &omap2_clksel_round_rate,
463 .set_rate = &omap2_clksel_set_rate, 453 .set_rate = &omap2_clksel_set_rate,
464 .flags = CLOCK_IN_OMAP4430,
465}; 454};
466 455
467static const struct clksel dbgclk_mux_sel[] = { 456static const struct clksel dbgclk_mux_sel[] = {
@@ -475,7 +464,6 @@ static struct clk dbgclk_mux_ck = {
475 .parent = &sys_clkin_ck, 464 .parent = &sys_clkin_ck,
476 .ops = &clkops_null, 465 .ops = &clkops_null,
477 .recalc = &followparent_recalc, 466 .recalc = &followparent_recalc,
478 .flags = CLOCK_IN_OMAP4430,
479}; 467};
480 468
481static struct clk dpll_core_m2_ck = { 469static struct clk dpll_core_m2_ck = {
@@ -488,7 +476,6 @@ static struct clk dpll_core_m2_ck = {
488 .recalc = &omap2_clksel_recalc, 476 .recalc = &omap2_clksel_recalc,
489 .round_rate = &omap2_clksel_round_rate, 477 .round_rate = &omap2_clksel_round_rate,
490 .set_rate = &omap2_clksel_set_rate, 478 .set_rate = &omap2_clksel_set_rate,
491 .flags = CLOCK_IN_OMAP4430,
492}; 479};
493 480
494static struct clk ddrphy_ck = { 481static struct clk ddrphy_ck = {
@@ -496,7 +483,6 @@ static struct clk ddrphy_ck = {
496 .parent = &dpll_core_m2_ck, 483 .parent = &dpll_core_m2_ck,
497 .ops = &clkops_null, 484 .ops = &clkops_null,
498 .recalc = &followparent_recalc, 485 .recalc = &followparent_recalc,
499 .flags = CLOCK_IN_OMAP4430,
500}; 486};
501 487
502static struct clk dpll_core_m5_ck = { 488static struct clk dpll_core_m5_ck = {
@@ -509,7 +495,6 @@ static struct clk dpll_core_m5_ck = {
509 .recalc = &omap2_clksel_recalc, 495 .recalc = &omap2_clksel_recalc,
510 .round_rate = &omap2_clksel_round_rate, 496 .round_rate = &omap2_clksel_round_rate,
511 .set_rate = &omap2_clksel_set_rate, 497 .set_rate = &omap2_clksel_set_rate,
512 .flags = CLOCK_IN_OMAP4430,
513}; 498};
514 499
515static const struct clksel div_core_div[] = { 500static const struct clksel div_core_div[] = {
@@ -527,7 +512,6 @@ static struct clk div_core_ck = {
527 .recalc = &omap2_clksel_recalc, 512 .recalc = &omap2_clksel_recalc,
528 .round_rate = &omap2_clksel_round_rate, 513 .round_rate = &omap2_clksel_round_rate,
529 .set_rate = &omap2_clksel_set_rate, 514 .set_rate = &omap2_clksel_set_rate,
530 .flags = CLOCK_IN_OMAP4430,
531}; 515};
532 516
533static const struct clksel_rate div4_1to8_rates[] = { 517static const struct clksel_rate div4_1to8_rates[] = {
@@ -553,7 +537,6 @@ static struct clk div_iva_hs_clk = {
553 .recalc = &omap2_clksel_recalc, 537 .recalc = &omap2_clksel_recalc,
554 .round_rate = &omap2_clksel_round_rate, 538 .round_rate = &omap2_clksel_round_rate,
555 .set_rate = &omap2_clksel_set_rate, 539 .set_rate = &omap2_clksel_set_rate,
556 .flags = CLOCK_IN_OMAP4430,
557}; 540};
558 541
559static struct clk div_mpu_hs_clk = { 542static struct clk div_mpu_hs_clk = {
@@ -566,7 +549,6 @@ static struct clk div_mpu_hs_clk = {
566 .recalc = &omap2_clksel_recalc, 549 .recalc = &omap2_clksel_recalc,
567 .round_rate = &omap2_clksel_round_rate, 550 .round_rate = &omap2_clksel_round_rate,
568 .set_rate = &omap2_clksel_set_rate, 551 .set_rate = &omap2_clksel_set_rate,
569 .flags = CLOCK_IN_OMAP4430,
570}; 552};
571 553
572static struct clk dpll_core_m4_ck = { 554static struct clk dpll_core_m4_ck = {
@@ -579,7 +561,6 @@ static struct clk dpll_core_m4_ck = {
579 .recalc = &omap2_clksel_recalc, 561 .recalc = &omap2_clksel_recalc,
580 .round_rate = &omap2_clksel_round_rate, 562 .round_rate = &omap2_clksel_round_rate,
581 .set_rate = &omap2_clksel_set_rate, 563 .set_rate = &omap2_clksel_set_rate,
582 .flags = CLOCK_IN_OMAP4430,
583}; 564};
584 565
585static struct clk dll_clk_div_ck = { 566static struct clk dll_clk_div_ck = {
@@ -587,7 +568,6 @@ static struct clk dll_clk_div_ck = {
587 .parent = &dpll_core_m4_ck, 568 .parent = &dpll_core_m4_ck,
588 .ops = &clkops_null, 569 .ops = &clkops_null,
589 .recalc = &followparent_recalc, 570 .recalc = &followparent_recalc,
590 .flags = CLOCK_IN_OMAP4430,
591}; 571};
592 572
593static struct clk dpll_abe_m2_ck = { 573static struct clk dpll_abe_m2_ck = {
@@ -600,7 +580,6 @@ static struct clk dpll_abe_m2_ck = {
600 .recalc = &omap2_clksel_recalc, 580 .recalc = &omap2_clksel_recalc,
601 .round_rate = &omap2_clksel_round_rate, 581 .round_rate = &omap2_clksel_round_rate,
602 .set_rate = &omap2_clksel_set_rate, 582 .set_rate = &omap2_clksel_set_rate,
603 .flags = CLOCK_IN_OMAP4430,
604}; 583};
605 584
606static struct clk dpll_core_m3_ck = { 585static struct clk dpll_core_m3_ck = {
@@ -613,7 +592,6 @@ static struct clk dpll_core_m3_ck = {
613 .recalc = &omap2_clksel_recalc, 592 .recalc = &omap2_clksel_recalc,
614 .round_rate = &omap2_clksel_round_rate, 593 .round_rate = &omap2_clksel_round_rate,
615 .set_rate = &omap2_clksel_set_rate, 594 .set_rate = &omap2_clksel_set_rate,
616 .flags = CLOCK_IN_OMAP4430,
617}; 595};
618 596
619static struct clk dpll_core_m7_ck = { 597static struct clk dpll_core_m7_ck = {
@@ -626,7 +604,6 @@ static struct clk dpll_core_m7_ck = {
626 .recalc = &omap2_clksel_recalc, 604 .recalc = &omap2_clksel_recalc,
627 .round_rate = &omap2_clksel_round_rate, 605 .round_rate = &omap2_clksel_round_rate,
628 .set_rate = &omap2_clksel_set_rate, 606 .set_rate = &omap2_clksel_set_rate,
629 .flags = CLOCK_IN_OMAP4430,
630}; 607};
631 608
632static const struct clksel iva_hsd_byp_clk_mux_sel[] = { 609static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
@@ -640,7 +617,6 @@ static struct clk iva_hsd_byp_clk_mux_ck = {
640 .parent = &dpll_sys_ref_clk, 617 .parent = &dpll_sys_ref_clk,
641 .ops = &clkops_null, 618 .ops = &clkops_null,
642 .recalc = &followparent_recalc, 619 .recalc = &followparent_recalc,
643 .flags = CLOCK_IN_OMAP4430,
644}; 620};
645 621
646/* DPLL_IVA */ 622/* DPLL_IVA */
@@ -672,7 +648,6 @@ static struct clk dpll_iva_ck = {
672 .recalc = &omap3_dpll_recalc, 648 .recalc = &omap3_dpll_recalc,
673 .round_rate = &omap2_dpll_round_rate, 649 .round_rate = &omap2_dpll_round_rate,
674 .set_rate = &omap3_noncore_dpll_set_rate, 650 .set_rate = &omap3_noncore_dpll_set_rate,
675 .flags = CLOCK_IN_OMAP4430,
676}; 651};
677 652
678static const struct clksel dpll_iva_m4_div[] = { 653static const struct clksel dpll_iva_m4_div[] = {
@@ -690,7 +665,6 @@ static struct clk dpll_iva_m4_ck = {
690 .recalc = &omap2_clksel_recalc, 665 .recalc = &omap2_clksel_recalc,
691 .round_rate = &omap2_clksel_round_rate, 666 .round_rate = &omap2_clksel_round_rate,
692 .set_rate = &omap2_clksel_set_rate, 667 .set_rate = &omap2_clksel_set_rate,
693 .flags = CLOCK_IN_OMAP4430,
694}; 668};
695 669
696static struct clk dpll_iva_m5_ck = { 670static struct clk dpll_iva_m5_ck = {
@@ -703,7 +677,6 @@ static struct clk dpll_iva_m5_ck = {
703 .recalc = &omap2_clksel_recalc, 677 .recalc = &omap2_clksel_recalc,
704 .round_rate = &omap2_clksel_round_rate, 678 .round_rate = &omap2_clksel_round_rate,
705 .set_rate = &omap2_clksel_set_rate, 679 .set_rate = &omap2_clksel_set_rate,
706 .flags = CLOCK_IN_OMAP4430,
707}; 680};
708 681
709/* DPLL_MPU */ 682/* DPLL_MPU */
@@ -735,7 +708,6 @@ static struct clk dpll_mpu_ck = {
735 .recalc = &omap3_dpll_recalc, 708 .recalc = &omap3_dpll_recalc,
736 .round_rate = &omap2_dpll_round_rate, 709 .round_rate = &omap2_dpll_round_rate,
737 .set_rate = &omap3_noncore_dpll_set_rate, 710 .set_rate = &omap3_noncore_dpll_set_rate,
738 .flags = CLOCK_IN_OMAP4430,
739}; 711};
740 712
741static const struct clksel dpll_mpu_m2_div[] = { 713static const struct clksel dpll_mpu_m2_div[] = {
@@ -753,7 +725,6 @@ static struct clk dpll_mpu_m2_ck = {
753 .recalc = &omap2_clksel_recalc, 725 .recalc = &omap2_clksel_recalc,
754 .round_rate = &omap2_clksel_round_rate, 726 .round_rate = &omap2_clksel_round_rate,
755 .set_rate = &omap2_clksel_set_rate, 727 .set_rate = &omap2_clksel_set_rate,
756 .flags = CLOCK_IN_OMAP4430,
757}; 728};
758 729
759static struct clk per_hs_clk_div_ck = { 730static struct clk per_hs_clk_div_ck = {
@@ -761,7 +732,6 @@ static struct clk per_hs_clk_div_ck = {
761 .parent = &dpll_abe_m3_ck, 732 .parent = &dpll_abe_m3_ck,
762 .ops = &clkops_null, 733 .ops = &clkops_null,
763 .recalc = &followparent_recalc, 734 .recalc = &followparent_recalc,
764 .flags = CLOCK_IN_OMAP4430,
765}; 735};
766 736
767static const struct clksel per_hsd_byp_clk_mux_sel[] = { 737static const struct clksel per_hsd_byp_clk_mux_sel[] = {
@@ -779,7 +749,6 @@ static struct clk per_hsd_byp_clk_mux_ck = {
779 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, 749 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
780 .ops = &clkops_null, 750 .ops = &clkops_null,
781 .recalc = &omap2_clksel_recalc, 751 .recalc = &omap2_clksel_recalc,
782 .flags = CLOCK_IN_OMAP4430,
783}; 752};
784 753
785/* DPLL_PER */ 754/* DPLL_PER */
@@ -811,7 +780,6 @@ static struct clk dpll_per_ck = {
811 .recalc = &omap3_dpll_recalc, 780 .recalc = &omap3_dpll_recalc,
812 .round_rate = &omap2_dpll_round_rate, 781 .round_rate = &omap2_dpll_round_rate,
813 .set_rate = &omap3_noncore_dpll_set_rate, 782 .set_rate = &omap3_noncore_dpll_set_rate,
814 .flags = CLOCK_IN_OMAP4430,
815}; 783};
816 784
817static const struct clksel dpll_per_m2_div[] = { 785static const struct clksel dpll_per_m2_div[] = {
@@ -829,7 +797,6 @@ static struct clk dpll_per_m2_ck = {
829 .recalc = &omap2_clksel_recalc, 797 .recalc = &omap2_clksel_recalc,
830 .round_rate = &omap2_clksel_round_rate, 798 .round_rate = &omap2_clksel_round_rate,
831 .set_rate = &omap2_clksel_set_rate, 799 .set_rate = &omap2_clksel_set_rate,
832 .flags = CLOCK_IN_OMAP4430,
833}; 800};
834 801
835static struct clk dpll_per_m2x2_ck = { 802static struct clk dpll_per_m2x2_ck = {
@@ -837,7 +804,6 @@ static struct clk dpll_per_m2x2_ck = {
837 .parent = &dpll_per_ck, 804 .parent = &dpll_per_ck,
838 .ops = &clkops_null, 805 .ops = &clkops_null,
839 .recalc = &followparent_recalc, 806 .recalc = &followparent_recalc,
840 .flags = CLOCK_IN_OMAP4430,
841}; 807};
842 808
843static struct clk dpll_per_m3_ck = { 809static struct clk dpll_per_m3_ck = {
@@ -850,7 +816,6 @@ static struct clk dpll_per_m3_ck = {
850 .recalc = &omap2_clksel_recalc, 816 .recalc = &omap2_clksel_recalc,
851 .round_rate = &omap2_clksel_round_rate, 817 .round_rate = &omap2_clksel_round_rate,
852 .set_rate = &omap2_clksel_set_rate, 818 .set_rate = &omap2_clksel_set_rate,
853 .flags = CLOCK_IN_OMAP4430,
854}; 819};
855 820
856static struct clk dpll_per_m4_ck = { 821static struct clk dpll_per_m4_ck = {
@@ -863,7 +828,6 @@ static struct clk dpll_per_m4_ck = {
863 .recalc = &omap2_clksel_recalc, 828 .recalc = &omap2_clksel_recalc,
864 .round_rate = &omap2_clksel_round_rate, 829 .round_rate = &omap2_clksel_round_rate,
865 .set_rate = &omap2_clksel_set_rate, 830 .set_rate = &omap2_clksel_set_rate,
866 .flags = CLOCK_IN_OMAP4430,
867}; 831};
868 832
869static struct clk dpll_per_m5_ck = { 833static struct clk dpll_per_m5_ck = {
@@ -876,7 +840,6 @@ static struct clk dpll_per_m5_ck = {
876 .recalc = &omap2_clksel_recalc, 840 .recalc = &omap2_clksel_recalc,
877 .round_rate = &omap2_clksel_round_rate, 841 .round_rate = &omap2_clksel_round_rate,
878 .set_rate = &omap2_clksel_set_rate, 842 .set_rate = &omap2_clksel_set_rate,
879 .flags = CLOCK_IN_OMAP4430,
880}; 843};
881 844
882static struct clk dpll_per_m6_ck = { 845static struct clk dpll_per_m6_ck = {
@@ -889,7 +852,6 @@ static struct clk dpll_per_m6_ck = {
889 .recalc = &omap2_clksel_recalc, 852 .recalc = &omap2_clksel_recalc,
890 .round_rate = &omap2_clksel_round_rate, 853 .round_rate = &omap2_clksel_round_rate,
891 .set_rate = &omap2_clksel_set_rate, 854 .set_rate = &omap2_clksel_set_rate,
892 .flags = CLOCK_IN_OMAP4430,
893}; 855};
894 856
895static struct clk dpll_per_m7_ck = { 857static struct clk dpll_per_m7_ck = {
@@ -902,7 +864,6 @@ static struct clk dpll_per_m7_ck = {
902 .recalc = &omap2_clksel_recalc, 864 .recalc = &omap2_clksel_recalc,
903 .round_rate = &omap2_clksel_round_rate, 865 .round_rate = &omap2_clksel_round_rate,
904 .set_rate = &omap2_clksel_set_rate, 866 .set_rate = &omap2_clksel_set_rate,
905 .flags = CLOCK_IN_OMAP4430,
906}; 867};
907 868
908/* DPLL_UNIPRO */ 869/* DPLL_UNIPRO */
@@ -934,7 +895,6 @@ static struct clk dpll_unipro_ck = {
934 .recalc = &omap3_dpll_recalc, 895 .recalc = &omap3_dpll_recalc,
935 .round_rate = &omap2_dpll_round_rate, 896 .round_rate = &omap2_dpll_round_rate,
936 .set_rate = &omap3_noncore_dpll_set_rate, 897 .set_rate = &omap3_noncore_dpll_set_rate,
937 .flags = CLOCK_IN_OMAP4430,
938}; 898};
939 899
940static const struct clksel dpll_unipro_m2x2_div[] = { 900static const struct clksel dpll_unipro_m2x2_div[] = {
@@ -952,7 +912,6 @@ static struct clk dpll_unipro_m2x2_ck = {
952 .recalc = &omap2_clksel_recalc, 912 .recalc = &omap2_clksel_recalc,
953 .round_rate = &omap2_clksel_round_rate, 913 .round_rate = &omap2_clksel_round_rate,
954 .set_rate = &omap2_clksel_set_rate, 914 .set_rate = &omap2_clksel_set_rate,
955 .flags = CLOCK_IN_OMAP4430,
956}; 915};
957 916
958static struct clk usb_hs_clk_div_ck = { 917static struct clk usb_hs_clk_div_ck = {
@@ -960,7 +919,6 @@ static struct clk usb_hs_clk_div_ck = {
960 .parent = &dpll_abe_m3_ck, 919 .parent = &dpll_abe_m3_ck,
961 .ops = &clkops_null, 920 .ops = &clkops_null,
962 .recalc = &followparent_recalc, 921 .recalc = &followparent_recalc,
963 .flags = CLOCK_IN_OMAP4430,
964}; 922};
965 923
966/* DPLL_USB */ 924/* DPLL_USB */
@@ -993,7 +951,6 @@ static struct clk dpll_usb_ck = {
993 .recalc = &omap3_dpll_recalc, 951 .recalc = &omap3_dpll_recalc,
994 .round_rate = &omap2_dpll_round_rate, 952 .round_rate = &omap2_dpll_round_rate,
995 .set_rate = &omap3_noncore_dpll_set_rate, 953 .set_rate = &omap3_noncore_dpll_set_rate,
996 .flags = CLOCK_IN_OMAP4430,
997}; 954};
998 955
999static struct clk dpll_usb_clkdcoldo_ck = { 956static struct clk dpll_usb_clkdcoldo_ck = {
@@ -1001,7 +958,6 @@ static struct clk dpll_usb_clkdcoldo_ck = {
1001 .parent = &dpll_usb_ck, 958 .parent = &dpll_usb_ck,
1002 .ops = &clkops_null, 959 .ops = &clkops_null,
1003 .recalc = &followparent_recalc, 960 .recalc = &followparent_recalc,
1004 .flags = CLOCK_IN_OMAP4430,
1005}; 961};
1006 962
1007static const struct clksel dpll_usb_m2_div[] = { 963static const struct clksel dpll_usb_m2_div[] = {
@@ -1019,7 +975,6 @@ static struct clk dpll_usb_m2_ck = {
1019 .recalc = &omap2_clksel_recalc, 975 .recalc = &omap2_clksel_recalc,
1020 .round_rate = &omap2_clksel_round_rate, 976 .round_rate = &omap2_clksel_round_rate,
1021 .set_rate = &omap2_clksel_set_rate, 977 .set_rate = &omap2_clksel_set_rate,
1022 .flags = CLOCK_IN_OMAP4430,
1023}; 978};
1024 979
1025static const struct clksel ducati_clk_mux_sel[] = { 980static const struct clksel ducati_clk_mux_sel[] = {
@@ -1037,7 +992,6 @@ static struct clk ducati_clk_mux_ck = {
1037 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 992 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1038 .ops = &clkops_null, 993 .ops = &clkops_null,
1039 .recalc = &omap2_clksel_recalc, 994 .recalc = &omap2_clksel_recalc,
1040 .flags = CLOCK_IN_OMAP4430,
1041}; 995};
1042 996
1043static struct clk func_12m_fclk = { 997static struct clk func_12m_fclk = {
@@ -1045,7 +999,6 @@ static struct clk func_12m_fclk = {
1045 .parent = &dpll_per_m2x2_ck, 999 .parent = &dpll_per_m2x2_ck,
1046 .ops = &clkops_null, 1000 .ops = &clkops_null,
1047 .recalc = &followparent_recalc, 1001 .recalc = &followparent_recalc,
1048 .flags = CLOCK_IN_OMAP4430,
1049}; 1002};
1050 1003
1051static struct clk func_24m_clk = { 1004static struct clk func_24m_clk = {
@@ -1053,7 +1006,6 @@ static struct clk func_24m_clk = {
1053 .parent = &dpll_per_m2_ck, 1006 .parent = &dpll_per_m2_ck,
1054 .ops = &clkops_null, 1007 .ops = &clkops_null,
1055 .recalc = &followparent_recalc, 1008 .recalc = &followparent_recalc,
1056 .flags = CLOCK_IN_OMAP4430,
1057}; 1009};
1058 1010
1059static struct clk func_24mc_fclk = { 1011static struct clk func_24mc_fclk = {
@@ -1061,7 +1013,6 @@ static struct clk func_24mc_fclk = {
1061 .parent = &dpll_per_m2x2_ck, 1013 .parent = &dpll_per_m2x2_ck,
1062 .ops = &clkops_null, 1014 .ops = &clkops_null,
1063 .recalc = &followparent_recalc, 1015 .recalc = &followparent_recalc,
1064 .flags = CLOCK_IN_OMAP4430,
1065}; 1016};
1066 1017
1067static const struct clksel_rate div2_4to8_rates[] = { 1018static const struct clksel_rate div2_4to8_rates[] = {
@@ -1085,7 +1036,6 @@ static struct clk func_48m_fclk = {
1085 .recalc = &omap2_clksel_recalc, 1036 .recalc = &omap2_clksel_recalc,
1086 .round_rate = &omap2_clksel_round_rate, 1037 .round_rate = &omap2_clksel_round_rate,
1087 .set_rate = &omap2_clksel_set_rate, 1038 .set_rate = &omap2_clksel_set_rate,
1088 .flags = CLOCK_IN_OMAP4430,
1089}; 1039};
1090 1040
1091static struct clk func_48mc_fclk = { 1041static struct clk func_48mc_fclk = {
@@ -1093,7 +1043,6 @@ static struct clk func_48mc_fclk = {
1093 .parent = &dpll_per_m2x2_ck, 1043 .parent = &dpll_per_m2x2_ck,
1094 .ops = &clkops_null, 1044 .ops = &clkops_null,
1095 .recalc = &followparent_recalc, 1045 .recalc = &followparent_recalc,
1096 .flags = CLOCK_IN_OMAP4430,
1097}; 1046};
1098 1047
1099static const struct clksel_rate div2_2to4_rates[] = { 1048static const struct clksel_rate div2_2to4_rates[] = {
@@ -1117,7 +1066,6 @@ static struct clk func_64m_fclk = {
1117 .recalc = &omap2_clksel_recalc, 1066 .recalc = &omap2_clksel_recalc,
1118 .round_rate = &omap2_clksel_round_rate, 1067 .round_rate = &omap2_clksel_round_rate,
1119 .set_rate = &omap2_clksel_set_rate, 1068 .set_rate = &omap2_clksel_set_rate,
1120 .flags = CLOCK_IN_OMAP4430,
1121}; 1069};
1122 1070
1123static const struct clksel func_96m_fclk_div[] = { 1071static const struct clksel func_96m_fclk_div[] = {
@@ -1135,7 +1083,6 @@ static struct clk func_96m_fclk = {
1135 .recalc = &omap2_clksel_recalc, 1083 .recalc = &omap2_clksel_recalc,
1136 .round_rate = &omap2_clksel_round_rate, 1084 .round_rate = &omap2_clksel_round_rate,
1137 .set_rate = &omap2_clksel_set_rate, 1085 .set_rate = &omap2_clksel_set_rate,
1138 .flags = CLOCK_IN_OMAP4430,
1139}; 1086};
1140 1087
1141static const struct clksel hsmmc6_fclk_sel[] = { 1088static const struct clksel hsmmc6_fclk_sel[] = {
@@ -1149,7 +1096,6 @@ static struct clk hsmmc6_fclk = {
1149 .parent = &func_64m_fclk, 1096 .parent = &func_64m_fclk,
1150 .ops = &clkops_null, 1097 .ops = &clkops_null,
1151 .recalc = &followparent_recalc, 1098 .recalc = &followparent_recalc,
1152 .flags = CLOCK_IN_OMAP4430,
1153}; 1099};
1154 1100
1155static const struct clksel_rate div2_1to8_rates[] = { 1101static const struct clksel_rate div2_1to8_rates[] = {
@@ -1173,7 +1119,6 @@ static struct clk init_60m_fclk = {
1173 .recalc = &omap2_clksel_recalc, 1119 .recalc = &omap2_clksel_recalc,
1174 .round_rate = &omap2_clksel_round_rate, 1120 .round_rate = &omap2_clksel_round_rate,
1175 .set_rate = &omap2_clksel_set_rate, 1121 .set_rate = &omap2_clksel_set_rate,
1176 .flags = CLOCK_IN_OMAP4430,
1177}; 1122};
1178 1123
1179static const struct clksel l3_div_div[] = { 1124static const struct clksel l3_div_div[] = {
@@ -1191,7 +1136,6 @@ static struct clk l3_div_ck = {
1191 .recalc = &omap2_clksel_recalc, 1136 .recalc = &omap2_clksel_recalc,
1192 .round_rate = &omap2_clksel_round_rate, 1137 .round_rate = &omap2_clksel_round_rate,
1193 .set_rate = &omap2_clksel_set_rate, 1138 .set_rate = &omap2_clksel_set_rate,
1194 .flags = CLOCK_IN_OMAP4430,
1195}; 1139};
1196 1140
1197static const struct clksel l4_div_div[] = { 1141static const struct clksel l4_div_div[] = {
@@ -1209,7 +1153,6 @@ static struct clk l4_div_ck = {
1209 .recalc = &omap2_clksel_recalc, 1153 .recalc = &omap2_clksel_recalc,
1210 .round_rate = &omap2_clksel_round_rate, 1154 .round_rate = &omap2_clksel_round_rate,
1211 .set_rate = &omap2_clksel_set_rate, 1155 .set_rate = &omap2_clksel_set_rate,
1212 .flags = CLOCK_IN_OMAP4430,
1213}; 1156};
1214 1157
1215static struct clk lp_clk_div_ck = { 1158static struct clk lp_clk_div_ck = {
@@ -1217,7 +1160,6 @@ static struct clk lp_clk_div_ck = {
1217 .parent = &dpll_abe_m2x2_ck, 1160 .parent = &dpll_abe_m2x2_ck,
1218 .ops = &clkops_null, 1161 .ops = &clkops_null,
1219 .recalc = &followparent_recalc, 1162 .recalc = &followparent_recalc,
1220 .flags = CLOCK_IN_OMAP4430,
1221}; 1163};
1222 1164
1223static const struct clksel l4_wkup_clk_mux_sel[] = { 1165static const struct clksel l4_wkup_clk_mux_sel[] = {
@@ -1235,7 +1177,6 @@ static struct clk l4_wkup_clk_mux_ck = {
1235 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 1177 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1236 .ops = &clkops_null, 1178 .ops = &clkops_null,
1237 .recalc = &omap2_clksel_recalc, 1179 .recalc = &omap2_clksel_recalc,
1238 .flags = CLOCK_IN_OMAP4430,
1239}; 1180};
1240 1181
1241static const struct clksel per_abe_nc_fclk_div[] = { 1182static const struct clksel per_abe_nc_fclk_div[] = {
@@ -1253,7 +1194,6 @@ static struct clk per_abe_nc_fclk = {
1253 .recalc = &omap2_clksel_recalc, 1194 .recalc = &omap2_clksel_recalc,
1254 .round_rate = &omap2_clksel_round_rate, 1195 .round_rate = &omap2_clksel_round_rate,
1255 .set_rate = &omap2_clksel_set_rate, 1196 .set_rate = &omap2_clksel_set_rate,
1256 .flags = CLOCK_IN_OMAP4430,
1257}; 1197};
1258 1198
1259static const struct clksel mcasp2_fclk_sel[] = { 1199static const struct clksel mcasp2_fclk_sel[] = {
@@ -1267,7 +1207,6 @@ static struct clk mcasp2_fclk = {
1267 .parent = &func_96m_fclk, 1207 .parent = &func_96m_fclk,
1268 .ops = &clkops_null, 1208 .ops = &clkops_null,
1269 .recalc = &followparent_recalc, 1209 .recalc = &followparent_recalc,
1270 .flags = CLOCK_IN_OMAP4430,
1271}; 1210};
1272 1211
1273static struct clk mcasp3_fclk = { 1212static struct clk mcasp3_fclk = {
@@ -1275,7 +1214,6 @@ static struct clk mcasp3_fclk = {
1275 .parent = &func_96m_fclk, 1214 .parent = &func_96m_fclk,
1276 .ops = &clkops_null, 1215 .ops = &clkops_null,
1277 .recalc = &followparent_recalc, 1216 .recalc = &followparent_recalc,
1278 .flags = CLOCK_IN_OMAP4430,
1279}; 1217};
1280 1218
1281static struct clk ocp_abe_iclk = { 1219static struct clk ocp_abe_iclk = {
@@ -1283,7 +1221,6 @@ static struct clk ocp_abe_iclk = {
1283 .parent = &aess_fclk, 1221 .parent = &aess_fclk,
1284 .ops = &clkops_null, 1222 .ops = &clkops_null,
1285 .recalc = &followparent_recalc, 1223 .recalc = &followparent_recalc,
1286 .flags = CLOCK_IN_OMAP4430,
1287}; 1224};
1288 1225
1289static struct clk per_abe_24m_fclk = { 1226static struct clk per_abe_24m_fclk = {
@@ -1291,7 +1228,6 @@ static struct clk per_abe_24m_fclk = {
1291 .parent = &dpll_abe_m2_ck, 1228 .parent = &dpll_abe_m2_ck,
1292 .ops = &clkops_null, 1229 .ops = &clkops_null,
1293 .recalc = &followparent_recalc, 1230 .recalc = &followparent_recalc,
1294 .flags = CLOCK_IN_OMAP4430,
1295}; 1231};
1296 1232
1297static const struct clksel pmd_stm_clock_mux_sel[] = { 1233static const struct clksel pmd_stm_clock_mux_sel[] = {
@@ -1306,7 +1242,6 @@ static struct clk pmd_stm_clock_mux_ck = {
1306 .parent = &sys_clkin_ck, 1242 .parent = &sys_clkin_ck,
1307 .ops = &clkops_null, 1243 .ops = &clkops_null,
1308 .recalc = &followparent_recalc, 1244 .recalc = &followparent_recalc,
1309 .flags = CLOCK_IN_OMAP4430,
1310}; 1245};
1311 1246
1312static struct clk pmd_trace_clk_mux_ck = { 1247static struct clk pmd_trace_clk_mux_ck = {
@@ -1314,7 +1249,6 @@ static struct clk pmd_trace_clk_mux_ck = {
1314 .parent = &sys_clkin_ck, 1249 .parent = &sys_clkin_ck,
1315 .ops = &clkops_null, 1250 .ops = &clkops_null,
1316 .recalc = &followparent_recalc, 1251 .recalc = &followparent_recalc,
1317 .flags = CLOCK_IN_OMAP4430,
1318}; 1252};
1319 1253
1320static struct clk syc_clk_div_ck = { 1254static struct clk syc_clk_div_ck = {
@@ -1327,7 +1261,6 @@ static struct clk syc_clk_div_ck = {
1327 .recalc = &omap2_clksel_recalc, 1261 .recalc = &omap2_clksel_recalc,
1328 .round_rate = &omap2_clksel_round_rate, 1262 .round_rate = &omap2_clksel_round_rate,
1329 .set_rate = &omap2_clksel_set_rate, 1263 .set_rate = &omap2_clksel_set_rate,
1330 .flags = CLOCK_IN_OMAP4430,
1331}; 1264};
1332 1265
1333/* Leaf clocks controlled by modules */ 1266/* Leaf clocks controlled by modules */
@@ -1398,7 +1331,6 @@ static struct clk dmic_sync_mux_ck = {
1398 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1331 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1399 .ops = &clkops_null, 1332 .ops = &clkops_null,
1400 .recalc = &omap2_clksel_recalc, 1333 .recalc = &omap2_clksel_recalc,
1401 .flags = CLOCK_IN_OMAP4430,
1402}; 1334};
1403 1335
1404static const struct clksel func_dmic_abe_gfclk_sel[] = { 1336static const struct clksel func_dmic_abe_gfclk_sel[] = {
@@ -1418,7 +1350,6 @@ static struct clk dmic_ck = {
1418 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1350 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1419 .ops = &clkops_omap2_dflt, 1351 .ops = &clkops_omap2_dflt,
1420 .recalc = &omap2_clksel_recalc, 1352 .recalc = &omap2_clksel_recalc,
1421 .flags = CLOCK_IN_OMAP4430,
1422 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, 1353 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1423 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1354 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1424 .clkdm_name = "abe_clkdm", 1355 .clkdm_name = "abe_clkdm",
@@ -1480,7 +1411,6 @@ static struct clk fdif_ck = {
1480 .recalc = &omap2_clksel_recalc, 1411 .recalc = &omap2_clksel_recalc,
1481 .round_rate = &omap2_clksel_round_rate, 1412 .round_rate = &omap2_clksel_round_rate,
1482 .set_rate = &omap2_clksel_set_rate, 1413 .set_rate = &omap2_clksel_set_rate,
1483 .flags = CLOCK_IN_OMAP4430,
1484 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, 1414 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1485 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1415 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1486 .clkdm_name = "iss_clkdm", 1416 .clkdm_name = "iss_clkdm",
@@ -1501,7 +1431,6 @@ static struct clk per_sgx_fclk = {
1501 .recalc = &omap2_clksel_recalc, 1431 .recalc = &omap2_clksel_recalc,
1502 .round_rate = &omap2_clksel_round_rate, 1432 .round_rate = &omap2_clksel_round_rate,
1503 .set_rate = &omap2_clksel_set_rate, 1433 .set_rate = &omap2_clksel_set_rate,
1504 .flags = CLOCK_IN_OMAP4430,
1505}; 1434};
1506 1435
1507static const struct clksel sgx_clk_mux_sel[] = { 1436static const struct clksel sgx_clk_mux_sel[] = {
@@ -1520,7 +1449,6 @@ static struct clk gfx_ck = {
1520 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, 1449 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1521 .ops = &clkops_omap2_dflt, 1450 .ops = &clkops_omap2_dflt,
1522 .recalc = &omap2_clksel_recalc, 1451 .recalc = &omap2_clksel_recalc,
1523 .flags = CLOCK_IN_OMAP4430,
1524 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, 1452 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1525 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1453 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1526 .clkdm_name = "l3_gfx_clkdm", 1454 .clkdm_name = "l3_gfx_clkdm",
@@ -1612,7 +1540,6 @@ static struct clk gptimer1_ck = {
1612 .clksel_mask = OMAP4430_CLKSEL_MASK, 1540 .clksel_mask = OMAP4430_CLKSEL_MASK,
1613 .ops = &clkops_omap2_dflt, 1541 .ops = &clkops_omap2_dflt,
1614 .recalc = &omap2_clksel_recalc, 1542 .recalc = &omap2_clksel_recalc,
1615 .flags = CLOCK_IN_OMAP4430,
1616 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, 1543 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1617 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1544 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1618 .clkdm_name = "l4_wkup_clkdm", 1545 .clkdm_name = "l4_wkup_clkdm",
@@ -1628,7 +1555,6 @@ static struct clk gptimer10_ck = {
1628 .clksel_mask = OMAP4430_CLKSEL_MASK, 1555 .clksel_mask = OMAP4430_CLKSEL_MASK,
1629 .ops = &clkops_omap2_dflt, 1556 .ops = &clkops_omap2_dflt,
1630 .recalc = &omap2_clksel_recalc, 1557 .recalc = &omap2_clksel_recalc,
1631 .flags = CLOCK_IN_OMAP4430,
1632 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, 1558 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1633 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1559 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1634 .clkdm_name = "l4_per_clkdm", 1560 .clkdm_name = "l4_per_clkdm",
@@ -1644,7 +1570,6 @@ static struct clk gptimer11_ck = {
1644 .clksel_mask = OMAP4430_CLKSEL_MASK, 1570 .clksel_mask = OMAP4430_CLKSEL_MASK,
1645 .ops = &clkops_omap2_dflt, 1571 .ops = &clkops_omap2_dflt,
1646 .recalc = &omap2_clksel_recalc, 1572 .recalc = &omap2_clksel_recalc,
1647 .flags = CLOCK_IN_OMAP4430,
1648 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, 1573 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1649 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1574 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1650 .clkdm_name = "l4_per_clkdm", 1575 .clkdm_name = "l4_per_clkdm",
@@ -1660,7 +1585,6 @@ static struct clk gptimer2_ck = {
1660 .clksel_mask = OMAP4430_CLKSEL_MASK, 1585 .clksel_mask = OMAP4430_CLKSEL_MASK,
1661 .ops = &clkops_omap2_dflt, 1586 .ops = &clkops_omap2_dflt,
1662 .recalc = &omap2_clksel_recalc, 1587 .recalc = &omap2_clksel_recalc,
1663 .flags = CLOCK_IN_OMAP4430,
1664 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, 1588 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1665 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1589 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1666 .clkdm_name = "l4_per_clkdm", 1590 .clkdm_name = "l4_per_clkdm",
@@ -1676,7 +1600,6 @@ static struct clk gptimer3_ck = {
1676 .clksel_mask = OMAP4430_CLKSEL_MASK, 1600 .clksel_mask = OMAP4430_CLKSEL_MASK,
1677 .ops = &clkops_omap2_dflt, 1601 .ops = &clkops_omap2_dflt,
1678 .recalc = &omap2_clksel_recalc, 1602 .recalc = &omap2_clksel_recalc,
1679 .flags = CLOCK_IN_OMAP4430,
1680 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, 1603 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1681 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1604 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1682 .clkdm_name = "l4_per_clkdm", 1605 .clkdm_name = "l4_per_clkdm",
@@ -1692,7 +1615,6 @@ static struct clk gptimer4_ck = {
1692 .clksel_mask = OMAP4430_CLKSEL_MASK, 1615 .clksel_mask = OMAP4430_CLKSEL_MASK,
1693 .ops = &clkops_omap2_dflt, 1616 .ops = &clkops_omap2_dflt,
1694 .recalc = &omap2_clksel_recalc, 1617 .recalc = &omap2_clksel_recalc,
1695 .flags = CLOCK_IN_OMAP4430,
1696 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, 1618 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1697 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1619 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1698 .clkdm_name = "l4_per_clkdm", 1620 .clkdm_name = "l4_per_clkdm",
@@ -1714,7 +1636,6 @@ static struct clk gptimer5_ck = {
1714 .clksel_mask = OMAP4430_CLKSEL_MASK, 1636 .clksel_mask = OMAP4430_CLKSEL_MASK,
1715 .ops = &clkops_omap2_dflt, 1637 .ops = &clkops_omap2_dflt,
1716 .recalc = &omap2_clksel_recalc, 1638 .recalc = &omap2_clksel_recalc,
1717 .flags = CLOCK_IN_OMAP4430,
1718 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, 1639 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1719 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1640 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1720 .clkdm_name = "abe_clkdm", 1641 .clkdm_name = "abe_clkdm",
@@ -1730,7 +1651,6 @@ static struct clk gptimer6_ck = {
1730 .clksel_mask = OMAP4430_CLKSEL_MASK, 1651 .clksel_mask = OMAP4430_CLKSEL_MASK,
1731 .ops = &clkops_omap2_dflt, 1652 .ops = &clkops_omap2_dflt,
1732 .recalc = &omap2_clksel_recalc, 1653 .recalc = &omap2_clksel_recalc,
1733 .flags = CLOCK_IN_OMAP4430,
1734 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, 1654 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1735 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1655 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1736 .clkdm_name = "abe_clkdm", 1656 .clkdm_name = "abe_clkdm",
@@ -1746,7 +1666,6 @@ static struct clk gptimer7_ck = {
1746 .clksel_mask = OMAP4430_CLKSEL_MASK, 1666 .clksel_mask = OMAP4430_CLKSEL_MASK,
1747 .ops = &clkops_omap2_dflt, 1667 .ops = &clkops_omap2_dflt,
1748 .recalc = &omap2_clksel_recalc, 1668 .recalc = &omap2_clksel_recalc,
1749 .flags = CLOCK_IN_OMAP4430,
1750 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, 1669 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1751 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1670 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1752 .clkdm_name = "abe_clkdm", 1671 .clkdm_name = "abe_clkdm",
@@ -1762,7 +1681,6 @@ static struct clk gptimer8_ck = {
1762 .clksel_mask = OMAP4430_CLKSEL_MASK, 1681 .clksel_mask = OMAP4430_CLKSEL_MASK,
1763 .ops = &clkops_omap2_dflt, 1682 .ops = &clkops_omap2_dflt,
1764 .recalc = &omap2_clksel_recalc, 1683 .recalc = &omap2_clksel_recalc,
1765 .flags = CLOCK_IN_OMAP4430,
1766 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, 1684 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1767 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1685 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1768 .clkdm_name = "abe_clkdm", 1686 .clkdm_name = "abe_clkdm",
@@ -1778,7 +1696,6 @@ static struct clk gptimer9_ck = {
1778 .clksel_mask = OMAP4430_CLKSEL_MASK, 1696 .clksel_mask = OMAP4430_CLKSEL_MASK,
1779 .ops = &clkops_omap2_dflt, 1697 .ops = &clkops_omap2_dflt,
1780 .recalc = &omap2_clksel_recalc, 1698 .recalc = &omap2_clksel_recalc,
1781 .flags = CLOCK_IN_OMAP4430,
1782 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1699 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1783 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1700 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1784 .clkdm_name = "l4_per_clkdm", 1701 .clkdm_name = "l4_per_clkdm",
@@ -1805,7 +1722,6 @@ static struct clk hsi_ck = {
1805 .recalc = &omap2_clksel_recalc, 1722 .recalc = &omap2_clksel_recalc,
1806 .round_rate = &omap2_clksel_round_rate, 1723 .round_rate = &omap2_clksel_round_rate,
1807 .set_rate = &omap2_clksel_set_rate, 1724 .set_rate = &omap2_clksel_set_rate,
1808 .flags = CLOCK_IN_OMAP4430,
1809 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 1725 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1810 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1726 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1811 .clkdm_name = "l3_init_clkdm", 1727 .clkdm_name = "l3_init_clkdm",
@@ -1910,7 +1826,6 @@ static struct clk mcasp_sync_mux_ck = {
1910 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1826 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1911 .ops = &clkops_null, 1827 .ops = &clkops_null,
1912 .recalc = &omap2_clksel_recalc, 1828 .recalc = &omap2_clksel_recalc,
1913 .flags = CLOCK_IN_OMAP4430,
1914}; 1829};
1915 1830
1916static const struct clksel func_mcasp_abe_gfclk_sel[] = { 1831static const struct clksel func_mcasp_abe_gfclk_sel[] = {
@@ -1930,7 +1845,6 @@ static struct clk mcasp_ck = {
1930 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1845 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1931 .ops = &clkops_omap2_dflt, 1846 .ops = &clkops_omap2_dflt,
1932 .recalc = &omap2_clksel_recalc, 1847 .recalc = &omap2_clksel_recalc,
1933 .flags = CLOCK_IN_OMAP4430,
1934 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, 1848 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1935 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1849 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1936 .clkdm_name = "abe_clkdm", 1850 .clkdm_name = "abe_clkdm",
@@ -1945,7 +1859,6 @@ static struct clk mcbsp1_sync_mux_ck = {
1945 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1859 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1946 .ops = &clkops_null, 1860 .ops = &clkops_null,
1947 .recalc = &omap2_clksel_recalc, 1861 .recalc = &omap2_clksel_recalc,
1948 .flags = CLOCK_IN_OMAP4430,
1949}; 1862};
1950 1863
1951static const struct clksel func_mcbsp1_gfclk_sel[] = { 1864static const struct clksel func_mcbsp1_gfclk_sel[] = {
@@ -1965,7 +1878,6 @@ static struct clk mcbsp1_ck = {
1965 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1878 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1966 .ops = &clkops_omap2_dflt, 1879 .ops = &clkops_omap2_dflt,
1967 .recalc = &omap2_clksel_recalc, 1880 .recalc = &omap2_clksel_recalc,
1968 .flags = CLOCK_IN_OMAP4430,
1969 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, 1881 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1970 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1882 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1971 .clkdm_name = "abe_clkdm", 1883 .clkdm_name = "abe_clkdm",
@@ -1980,7 +1892,6 @@ static struct clk mcbsp2_sync_mux_ck = {
1980 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1892 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1981 .ops = &clkops_null, 1893 .ops = &clkops_null,
1982 .recalc = &omap2_clksel_recalc, 1894 .recalc = &omap2_clksel_recalc,
1983 .flags = CLOCK_IN_OMAP4430,
1984}; 1895};
1985 1896
1986static const struct clksel func_mcbsp2_gfclk_sel[] = { 1897static const struct clksel func_mcbsp2_gfclk_sel[] = {
@@ -2000,7 +1911,6 @@ static struct clk mcbsp2_ck = {
2000 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1911 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
2001 .ops = &clkops_omap2_dflt, 1912 .ops = &clkops_omap2_dflt,
2002 .recalc = &omap2_clksel_recalc, 1913 .recalc = &omap2_clksel_recalc,
2003 .flags = CLOCK_IN_OMAP4430,
2004 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, 1914 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2005 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1915 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2006 .clkdm_name = "abe_clkdm", 1916 .clkdm_name = "abe_clkdm",
@@ -2015,7 +1925,6 @@ static struct clk mcbsp3_sync_mux_ck = {
2015 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1925 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2016 .ops = &clkops_null, 1926 .ops = &clkops_null,
2017 .recalc = &omap2_clksel_recalc, 1927 .recalc = &omap2_clksel_recalc,
2018 .flags = CLOCK_IN_OMAP4430,
2019}; 1928};
2020 1929
2021static const struct clksel func_mcbsp3_gfclk_sel[] = { 1930static const struct clksel func_mcbsp3_gfclk_sel[] = {
@@ -2035,7 +1944,6 @@ static struct clk mcbsp3_ck = {
2035 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, 1944 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
2036 .ops = &clkops_omap2_dflt, 1945 .ops = &clkops_omap2_dflt,
2037 .recalc = &omap2_clksel_recalc, 1946 .recalc = &omap2_clksel_recalc,
2038 .flags = CLOCK_IN_OMAP4430,
2039 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, 1947 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2040 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1948 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2041 .clkdm_name = "abe_clkdm", 1949 .clkdm_name = "abe_clkdm",
@@ -2050,7 +1958,6 @@ static struct clk mcbsp4_sync_mux_ck = {
2050 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1958 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
2051 .ops = &clkops_null, 1959 .ops = &clkops_null,
2052 .recalc = &omap2_clksel_recalc, 1960 .recalc = &omap2_clksel_recalc,
2053 .flags = CLOCK_IN_OMAP4430,
2054}; 1961};
2055 1962
2056static const struct clksel per_mcbsp4_gfclk_sel[] = { 1963static const struct clksel per_mcbsp4_gfclk_sel[] = {
@@ -2069,7 +1976,6 @@ static struct clk mcbsp4_ck = {
2069 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, 1976 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2070 .ops = &clkops_omap2_dflt, 1977 .ops = &clkops_omap2_dflt,
2071 .recalc = &omap2_clksel_recalc, 1978 .recalc = &omap2_clksel_recalc,
2072 .flags = CLOCK_IN_OMAP4430,
2073 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 1979 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2074 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1980 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2075 .clkdm_name = "l4_per_clkdm", 1981 .clkdm_name = "l4_per_clkdm",
@@ -2125,7 +2031,6 @@ static struct clk mmc1_ck = {
2125 .clksel_mask = OMAP4430_CLKSEL_MASK, 2031 .clksel_mask = OMAP4430_CLKSEL_MASK,
2126 .ops = &clkops_omap2_dflt, 2032 .ops = &clkops_omap2_dflt,
2127 .recalc = &omap2_clksel_recalc, 2033 .recalc = &omap2_clksel_recalc,
2128 .flags = CLOCK_IN_OMAP4430,
2129 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 2034 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2130 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2035 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2131 .clkdm_name = "l3_init_clkdm", 2036 .clkdm_name = "l3_init_clkdm",
@@ -2141,7 +2046,6 @@ static struct clk mmc2_ck = {
2141 .clksel_mask = OMAP4430_CLKSEL_MASK, 2046 .clksel_mask = OMAP4430_CLKSEL_MASK,
2142 .ops = &clkops_omap2_dflt, 2047 .ops = &clkops_omap2_dflt,
2143 .recalc = &omap2_clksel_recalc, 2048 .recalc = &omap2_clksel_recalc,
2144 .flags = CLOCK_IN_OMAP4430,
2145 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 2049 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2146 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2050 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2147 .clkdm_name = "l3_init_clkdm", 2051 .clkdm_name = "l3_init_clkdm",
@@ -2443,7 +2347,6 @@ static struct clk otg_60m_gfclk_ck = {
2443 .clksel_mask = OMAP4430_CLKSEL_60M_MASK, 2347 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2444 .ops = &clkops_null, 2348 .ops = &clkops_null,
2445 .recalc = &omap2_clksel_recalc, 2349 .recalc = &omap2_clksel_recalc,
2446 .flags = CLOCK_IN_OMAP4430,
2447}; 2350};
2448 2351
2449static const struct clksel stm_clk_div_div[] = { 2352static const struct clksel stm_clk_div_div[] = {
@@ -2461,7 +2364,6 @@ static struct clk stm_clk_div_ck = {
2461 .recalc = &omap2_clksel_recalc, 2364 .recalc = &omap2_clksel_recalc,
2462 .round_rate = &omap2_clksel_round_rate, 2365 .round_rate = &omap2_clksel_round_rate,
2463 .set_rate = &omap2_clksel_set_rate, 2366 .set_rate = &omap2_clksel_set_rate,
2464 .flags = CLOCK_IN_OMAP4430,
2465}; 2367};
2466 2368
2467static const struct clksel trace_clk_div_div[] = { 2369static const struct clksel trace_clk_div_div[] = {
@@ -2479,7 +2381,6 @@ static struct clk trace_clk_div_ck = {
2479 .recalc = &omap2_clksel_recalc, 2381 .recalc = &omap2_clksel_recalc,
2480 .round_rate = &omap2_clksel_round_rate, 2382 .round_rate = &omap2_clksel_round_rate,
2481 .set_rate = &omap2_clksel_set_rate, 2383 .set_rate = &omap2_clksel_set_rate,
2482 .flags = CLOCK_IN_OMAP4430,
2483}; 2384};
2484 2385
2485static const struct clksel_rate div2_14to18_rates[] = { 2386static const struct clksel_rate div2_14to18_rates[] = {
@@ -2503,7 +2404,6 @@ static struct clk usim_fclk = {
2503 .recalc = &omap2_clksel_recalc, 2404 .recalc = &omap2_clksel_recalc,
2504 .round_rate = &omap2_clksel_round_rate, 2405 .round_rate = &omap2_clksel_round_rate,
2505 .set_rate = &omap2_clksel_set_rate, 2406 .set_rate = &omap2_clksel_set_rate,
2506 .flags = CLOCK_IN_OMAP4430,
2507}; 2407};
2508 2408
2509static const struct clksel utmi_p1_gfclk_sel[] = { 2409static const struct clksel utmi_p1_gfclk_sel[] = {
@@ -2521,7 +2421,6 @@ static struct clk utmi_p1_gfclk_ck = {
2521 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, 2421 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2522 .ops = &clkops_null, 2422 .ops = &clkops_null,
2523 .recalc = &omap2_clksel_recalc, 2423 .recalc = &omap2_clksel_recalc,
2524 .flags = CLOCK_IN_OMAP4430,
2525}; 2424};
2526 2425
2527static const struct clksel utmi_p2_gfclk_sel[] = { 2426static const struct clksel utmi_p2_gfclk_sel[] = {
@@ -2539,7 +2438,6 @@ static struct clk utmi_p2_gfclk_ck = {
2539 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, 2438 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2540 .ops = &clkops_null, 2439 .ops = &clkops_null,
2541 .recalc = &omap2_clksel_recalc, 2440 .recalc = &omap2_clksel_recalc,
2542 .flags = CLOCK_IN_OMAP4430,
2543}; 2441};
2544 2442
2545/* 2443/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 19:29:01 -0500