diff options
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/Kconfig | 3 | ||||
-rw-r--r-- | arch/arm/mach-omap2/board-am3517evm.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-24xx.h | 318 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-33xx.h | 749 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 632 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-44xx.h | 1558 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cm-regbits-54xx.h | 1633 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/powerdomains54xx_data.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prm-regbits-24xx.h | 247 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prm-regbits-33xx.h | 307 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prm-regbits-34xx.h | 481 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prm-regbits-44xx.h | 2226 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prm-regbits-54xx.h | 2701 | ||||
-rw-r--r-- | arch/arm/mach-omap2/timer.c | 6 |
15 files changed, 6 insertions, 10859 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3ed8acd42ecd..56021c67c89c 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
@@ -37,9 +37,8 @@ config ARCH_OMAP4 | |||
37 | select CACHE_L2X0 | 37 | select CACHE_L2X0 |
38 | select CPU_V7 | 38 | select CPU_V7 |
39 | select HAVE_ARM_SCU if SMP | 39 | select HAVE_ARM_SCU if SMP |
40 | select HAVE_ARM_TWD if LOCAL_TIMERS | 40 | select HAVE_ARM_TWD if SMP |
41 | select HAVE_SMP | 41 | select HAVE_SMP |
42 | select LOCAL_TIMERS if SMP | ||
43 | select OMAP_INTERCONNECT | 42 | select OMAP_INTERCONNECT |
44 | select PL310_ERRATA_588369 | 43 | select PL310_ERRATA_588369 |
45 | select PL310_ERRATA_727915 | 44 | select PL310_ERRATA_727915 |
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 8cc2c9e9fb03..543d9a882de3 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c | |||
@@ -21,7 +21,7 @@ | |||
21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
22 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
23 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
24 | #include <linux/i2c/pca953x.h> | 24 | #include <linux/platform_data/pca953x.h> |
25 | #include <linux/can/platform/ti_hecc.h> | 25 | #include <linux/can/platform/ti_hecc.h> |
26 | #include <linux/davinci_emac.h> | 26 | #include <linux/davinci_emac.h> |
27 | #include <linux/mmc/host.h> | 27 | #include <linux/mmc/host.h> |
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 669ef51b17a8..8538669cc2ad 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
@@ -14,439 +14,121 @@ | |||
14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | /* Bits shared between registers */ | ||
18 | |||
19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | ||
20 | #define OMAP24XX_EN_CAM_SHIFT 31 | 17 | #define OMAP24XX_EN_CAM_SHIFT 31 |
21 | #define OMAP24XX_EN_CAM_MASK (1 << 31) | ||
22 | #define OMAP24XX_EN_WDT4_SHIFT 29 | 18 | #define OMAP24XX_EN_WDT4_SHIFT 29 |
23 | #define OMAP24XX_EN_WDT4_MASK (1 << 29) | ||
24 | #define OMAP2420_EN_WDT3_SHIFT 28 | 19 | #define OMAP2420_EN_WDT3_SHIFT 28 |
25 | #define OMAP2420_EN_WDT3_MASK (1 << 28) | ||
26 | #define OMAP24XX_EN_MSPRO_SHIFT 27 | 20 | #define OMAP24XX_EN_MSPRO_SHIFT 27 |
27 | #define OMAP24XX_EN_MSPRO_MASK (1 << 27) | ||
28 | #define OMAP24XX_EN_FAC_SHIFT 25 | 21 | #define OMAP24XX_EN_FAC_SHIFT 25 |
29 | #define OMAP24XX_EN_FAC_MASK (1 << 25) | ||
30 | #define OMAP2420_EN_EAC_SHIFT 24 | 22 | #define OMAP2420_EN_EAC_SHIFT 24 |
31 | #define OMAP2420_EN_EAC_MASK (1 << 24) | ||
32 | #define OMAP24XX_EN_HDQ_SHIFT 23 | 23 | #define OMAP24XX_EN_HDQ_SHIFT 23 |
33 | #define OMAP24XX_EN_HDQ_MASK (1 << 23) | ||
34 | #define OMAP2420_EN_I2C2_SHIFT 20 | 24 | #define OMAP2420_EN_I2C2_SHIFT 20 |
35 | #define OMAP2420_EN_I2C2_MASK (1 << 20) | ||
36 | #define OMAP2420_EN_I2C1_SHIFT 19 | 25 | #define OMAP2420_EN_I2C1_SHIFT 19 |
37 | #define OMAP2420_EN_I2C1_MASK (1 << 19) | ||
38 | |||
39 | /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ | ||
40 | #define OMAP2430_EN_MCBSP5_SHIFT 5 | 26 | #define OMAP2430_EN_MCBSP5_SHIFT 5 |
41 | #define OMAP2430_EN_MCBSP5_MASK (1 << 5) | ||
42 | #define OMAP2430_EN_MCBSP4_SHIFT 4 | 27 | #define OMAP2430_EN_MCBSP4_SHIFT 4 |
43 | #define OMAP2430_EN_MCBSP4_MASK (1 << 4) | ||
44 | #define OMAP2430_EN_MCBSP3_SHIFT 3 | 28 | #define OMAP2430_EN_MCBSP3_SHIFT 3 |
45 | #define OMAP2430_EN_MCBSP3_MASK (1 << 3) | ||
46 | #define OMAP24XX_EN_SSI_SHIFT 1 | 29 | #define OMAP24XX_EN_SSI_SHIFT 1 |
47 | #define OMAP24XX_EN_SSI_MASK (1 << 1) | ||
48 | |||
49 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | ||
50 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 | 30 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 |
51 | #define OMAP24XX_EN_MPU_WDT_MASK (1 << 3) | ||
52 | |||
53 | /* Bits specific to each register */ | ||
54 | |||
55 | /* CM_IDLEST_MPU */ | ||
56 | /* 2430 only */ | ||
57 | #define OMAP2430_ST_MPU_MASK (1 << 0) | ||
58 | |||
59 | /* CM_CLKSEL_MPU */ | ||
60 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 | 31 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 |
61 | #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) | ||
62 | #define OMAP24XX_CLKSEL_MPU_WIDTH 5 | 32 | #define OMAP24XX_CLKSEL_MPU_WIDTH 5 |
63 | |||
64 | /* CM_CLKSTCTRL_MPU */ | ||
65 | #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 | ||
66 | #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) | 33 | #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) |
67 | |||
68 | /* CM_FCLKEN1_CORE specific bits*/ | ||
69 | #define OMAP24XX_EN_TV_SHIFT 2 | 34 | #define OMAP24XX_EN_TV_SHIFT 2 |
70 | #define OMAP24XX_EN_TV_MASK (1 << 2) | ||
71 | #define OMAP24XX_EN_DSS2_SHIFT 1 | 35 | #define OMAP24XX_EN_DSS2_SHIFT 1 |
72 | #define OMAP24XX_EN_DSS2_MASK (1 << 1) | ||
73 | #define OMAP24XX_EN_DSS1_SHIFT 0 | 36 | #define OMAP24XX_EN_DSS1_SHIFT 0 |
74 | #define OMAP24XX_EN_DSS1_MASK (1 << 0) | 37 | #define OMAP24XX_EN_DSS1_MASK (1 << 0) |
75 | |||
76 | /* CM_FCLKEN2_CORE specific bits */ | ||
77 | #define OMAP2430_EN_I2CHS2_SHIFT 20 | 38 | #define OMAP2430_EN_I2CHS2_SHIFT 20 |
78 | #define OMAP2430_EN_I2CHS2_MASK (1 << 20) | ||
79 | #define OMAP2430_EN_I2CHS1_SHIFT 19 | 39 | #define OMAP2430_EN_I2CHS1_SHIFT 19 |
80 | #define OMAP2430_EN_I2CHS1_MASK (1 << 19) | ||
81 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 | 40 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 |
82 | #define OMAP2430_EN_MMCHSDB2_MASK (1 << 17) | ||
83 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 | 41 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 |
84 | #define OMAP2430_EN_MMCHSDB1_MASK (1 << 16) | ||
85 | |||
86 | /* CM_ICLKEN1_CORE specific bits */ | ||
87 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 | 42 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 |
88 | #define OMAP24XX_EN_MAILBOXES_MASK (1 << 30) | ||
89 | #define OMAP24XX_EN_DSS_SHIFT 0 | ||
90 | #define OMAP24XX_EN_DSS_MASK (1 << 0) | ||
91 | |||
92 | /* CM_ICLKEN2_CORE specific bits */ | ||
93 | |||
94 | /* CM_ICLKEN3_CORE */ | ||
95 | /* 2430 only */ | ||
96 | #define OMAP2430_EN_SDRC_SHIFT 2 | 43 | #define OMAP2430_EN_SDRC_SHIFT 2 |
97 | #define OMAP2430_EN_SDRC_MASK (1 << 2) | ||
98 | |||
99 | /* CM_ICLKEN4_CORE */ | ||
100 | #define OMAP24XX_EN_PKA_SHIFT 4 | 44 | #define OMAP24XX_EN_PKA_SHIFT 4 |
101 | #define OMAP24XX_EN_PKA_MASK (1 << 4) | ||
102 | #define OMAP24XX_EN_AES_SHIFT 3 | 45 | #define OMAP24XX_EN_AES_SHIFT 3 |
103 | #define OMAP24XX_EN_AES_MASK (1 << 3) | ||
104 | #define OMAP24XX_EN_RNG_SHIFT 2 | 46 | #define OMAP24XX_EN_RNG_SHIFT 2 |
105 | #define OMAP24XX_EN_RNG_MASK (1 << 2) | ||
106 | #define OMAP24XX_EN_SHA_SHIFT 1 | 47 | #define OMAP24XX_EN_SHA_SHIFT 1 |
107 | #define OMAP24XX_EN_SHA_MASK (1 << 1) | ||
108 | #define OMAP24XX_EN_DES_SHIFT 0 | 48 | #define OMAP24XX_EN_DES_SHIFT 0 |
109 | #define OMAP24XX_EN_DES_MASK (1 << 0) | ||
110 | |||
111 | /* CM_IDLEST1_CORE specific bits */ | ||
112 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 | 49 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 |
113 | #define OMAP24XX_ST_MAILBOXES_MASK (1 << 30) | ||
114 | #define OMAP24XX_ST_WDT4_SHIFT 29 | ||
115 | #define OMAP24XX_ST_WDT4_MASK (1 << 29) | ||
116 | #define OMAP2420_ST_WDT3_SHIFT 28 | ||
117 | #define OMAP2420_ST_WDT3_MASK (1 << 28) | ||
118 | #define OMAP24XX_ST_MSPRO_SHIFT 27 | ||
119 | #define OMAP24XX_ST_MSPRO_MASK (1 << 27) | ||
120 | #define OMAP24XX_ST_FAC_SHIFT 25 | ||
121 | #define OMAP24XX_ST_FAC_MASK (1 << 25) | ||
122 | #define OMAP2420_ST_EAC_SHIFT 24 | ||
123 | #define OMAP2420_ST_EAC_MASK (1 << 24) | ||
124 | #define OMAP24XX_ST_HDQ_SHIFT 23 | 50 | #define OMAP24XX_ST_HDQ_SHIFT 23 |
125 | #define OMAP24XX_ST_HDQ_MASK (1 << 23) | ||
126 | #define OMAP2420_ST_I2C2_SHIFT 20 | 51 | #define OMAP2420_ST_I2C2_SHIFT 20 |
127 | #define OMAP2420_ST_I2C2_MASK (1 << 20) | ||
128 | #define OMAP2430_ST_I2CHS1_SHIFT 19 | 52 | #define OMAP2430_ST_I2CHS1_SHIFT 19 |
129 | #define OMAP2430_ST_I2CHS1_MASK (1 << 19) | ||
130 | #define OMAP2420_ST_I2C1_SHIFT 19 | 53 | #define OMAP2420_ST_I2C1_SHIFT 19 |
131 | #define OMAP2420_ST_I2C1_MASK (1 << 19) | ||
132 | #define OMAP2430_ST_I2CHS2_SHIFT 20 | 54 | #define OMAP2430_ST_I2CHS2_SHIFT 20 |
133 | #define OMAP2430_ST_I2CHS2_MASK (1 << 20) | ||
134 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 | 55 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 |
135 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) | ||
136 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 | 56 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 |
137 | #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) | ||
138 | #define OMAP24XX_ST_DSS_SHIFT 0 | 57 | #define OMAP24XX_ST_DSS_SHIFT 0 |
139 | #define OMAP24XX_ST_DSS_MASK (1 << 0) | ||
140 | |||
141 | /* CM_IDLEST2_CORE */ | ||
142 | #define OMAP2430_ST_MCBSP5_SHIFT 5 | 58 | #define OMAP2430_ST_MCBSP5_SHIFT 5 |
143 | #define OMAP2430_ST_MCBSP5_MASK (1 << 5) | ||
144 | #define OMAP2430_ST_MCBSP4_SHIFT 4 | 59 | #define OMAP2430_ST_MCBSP4_SHIFT 4 |
145 | #define OMAP2430_ST_MCBSP4_MASK (1 << 4) | ||
146 | #define OMAP2430_ST_MCBSP3_SHIFT 3 | 60 | #define OMAP2430_ST_MCBSP3_SHIFT 3 |
147 | #define OMAP2430_ST_MCBSP3_MASK (1 << 3) | ||
148 | #define OMAP24XX_ST_SSI_SHIFT 1 | ||
149 | #define OMAP24XX_ST_SSI_MASK (1 << 1) | ||
150 | |||
151 | /* CM_IDLEST3_CORE */ | ||
152 | /* 2430 only */ | ||
153 | #define OMAP2430_ST_SDRC_MASK (1 << 2) | ||
154 | |||
155 | /* CM_IDLEST4_CORE */ | ||
156 | #define OMAP24XX_ST_PKA_SHIFT 4 | ||
157 | #define OMAP24XX_ST_PKA_MASK (1 << 4) | ||
158 | #define OMAP24XX_ST_AES_SHIFT 3 | 61 | #define OMAP24XX_ST_AES_SHIFT 3 |
159 | #define OMAP24XX_ST_AES_MASK (1 << 3) | ||
160 | #define OMAP24XX_ST_RNG_SHIFT 2 | 62 | #define OMAP24XX_ST_RNG_SHIFT 2 |
161 | #define OMAP24XX_ST_RNG_MASK (1 << 2) | ||
162 | #define OMAP24XX_ST_SHA_SHIFT 1 | 63 | #define OMAP24XX_ST_SHA_SHIFT 1 |
163 | #define OMAP24XX_ST_SHA_MASK (1 << 1) | ||
164 | #define OMAP24XX_ST_DES_SHIFT 0 | ||
165 | #define OMAP24XX_ST_DES_MASK (1 << 0) | ||
166 | |||
167 | /* CM_AUTOIDLE1_CORE */ | ||
168 | #define OMAP24XX_AUTO_CAM_MASK (1 << 31) | ||
169 | #define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30) | ||
170 | #define OMAP24XX_AUTO_WDT4_MASK (1 << 29) | ||
171 | #define OMAP2420_AUTO_WDT3_MASK (1 << 28) | ||
172 | #define OMAP24XX_AUTO_MSPRO_MASK (1 << 27) | ||
173 | #define OMAP2420_AUTO_MMC_MASK (1 << 26) | ||
174 | #define OMAP24XX_AUTO_FAC_MASK (1 << 25) | ||
175 | #define OMAP2420_AUTO_EAC_MASK (1 << 24) | ||
176 | #define OMAP24XX_AUTO_HDQ_MASK (1 << 23) | ||
177 | #define OMAP24XX_AUTO_UART2_MASK (1 << 22) | ||
178 | #define OMAP24XX_AUTO_UART1_MASK (1 << 21) | ||
179 | #define OMAP24XX_AUTO_I2C2_MASK (1 << 20) | ||
180 | #define OMAP24XX_AUTO_I2C1_MASK (1 << 19) | ||
181 | #define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18) | ||
182 | #define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17) | ||
183 | #define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16) | ||
184 | #define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15) | ||
185 | #define OMAP24XX_AUTO_GPT12_MASK (1 << 14) | ||
186 | #define OMAP24XX_AUTO_GPT11_MASK (1 << 13) | ||
187 | #define OMAP24XX_AUTO_GPT10_MASK (1 << 12) | ||
188 | #define OMAP24XX_AUTO_GPT9_MASK (1 << 11) | ||
189 | #define OMAP24XX_AUTO_GPT8_MASK (1 << 10) | ||
190 | #define OMAP24XX_AUTO_GPT7_MASK (1 << 9) | ||
191 | #define OMAP24XX_AUTO_GPT6_MASK (1 << 8) | ||
192 | #define OMAP24XX_AUTO_GPT5_MASK (1 << 7) | ||
193 | #define OMAP24XX_AUTO_GPT4_MASK (1 << 6) | ||
194 | #define OMAP24XX_AUTO_GPT3_MASK (1 << 5) | ||
195 | #define OMAP24XX_AUTO_GPT2_MASK (1 << 4) | ||
196 | #define OMAP2420_AUTO_VLYNQ_MASK (1 << 3) | ||
197 | #define OMAP24XX_AUTO_DSS_MASK (1 << 0) | ||
198 | |||
199 | /* CM_AUTOIDLE2_CORE */ | ||
200 | #define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11) | ||
201 | #define OMAP2430_AUTO_GPIO5_MASK (1 << 10) | ||
202 | #define OMAP2430_AUTO_MCSPI3_MASK (1 << 9) | ||
203 | #define OMAP2430_AUTO_MMCHS2_MASK (1 << 8) | ||
204 | #define OMAP2430_AUTO_MMCHS1_MASK (1 << 7) | ||
205 | #define OMAP2430_AUTO_USBHS_MASK (1 << 6) | ||
206 | #define OMAP2430_AUTO_MCBSP5_MASK (1 << 5) | ||
207 | #define OMAP2430_AUTO_MCBSP4_MASK (1 << 4) | ||
208 | #define OMAP2430_AUTO_MCBSP3_MASK (1 << 3) | ||
209 | #define OMAP24XX_AUTO_UART3_MASK (1 << 2) | ||
210 | #define OMAP24XX_AUTO_SSI_MASK (1 << 1) | ||
211 | #define OMAP24XX_AUTO_USB_MASK (1 << 0) | ||
212 | |||
213 | /* CM_AUTOIDLE3_CORE */ | ||
214 | #define OMAP24XX_AUTO_SDRC_SHIFT 2 | 64 | #define OMAP24XX_AUTO_SDRC_SHIFT 2 |
215 | #define OMAP24XX_AUTO_SDRC_MASK (1 << 2) | ||
216 | #define OMAP24XX_AUTO_GPMC_SHIFT 1 | 65 | #define OMAP24XX_AUTO_GPMC_SHIFT 1 |
217 | #define OMAP24XX_AUTO_GPMC_MASK (1 << 1) | ||
218 | #define OMAP24XX_AUTO_SDMA_SHIFT 0 | 66 | #define OMAP24XX_AUTO_SDMA_SHIFT 0 |
219 | #define OMAP24XX_AUTO_SDMA_MASK (1 << 0) | ||
220 | |||
221 | /* CM_AUTOIDLE4_CORE */ | ||
222 | #define OMAP24XX_AUTO_PKA_MASK (1 << 4) | ||
223 | #define OMAP24XX_AUTO_AES_MASK (1 << 3) | ||
224 | #define OMAP24XX_AUTO_RNG_MASK (1 << 2) | ||
225 | #define OMAP24XX_AUTO_SHA_MASK (1 << 1) | ||
226 | #define OMAP24XX_AUTO_DES_MASK (1 << 0) | ||
227 | |||
228 | /* CM_CLKSEL1_CORE */ | ||
229 | #define OMAP24XX_CLKSEL_USB_SHIFT 25 | ||
230 | #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) | 67 | #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) |
231 | #define OMAP24XX_CLKSEL_SSI_SHIFT 20 | ||
232 | #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) | 68 | #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) |
233 | #define OMAP2420_CLKSEL_VLYNQ_SHIFT 15 | ||
234 | #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) | 69 | #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) |
235 | #define OMAP24XX_CLKSEL_DSS2_SHIFT 13 | ||
236 | #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) | 70 | #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) |
237 | #define OMAP24XX_CLKSEL_DSS1_SHIFT 8 | ||
238 | #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) | 71 | #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) |
239 | #define OMAP24XX_CLKSEL_L4_SHIFT 5 | 72 | #define OMAP24XX_CLKSEL_L4_SHIFT 5 |
240 | #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) | ||
241 | #define OMAP24XX_CLKSEL_L4_WIDTH 2 | 73 | #define OMAP24XX_CLKSEL_L4_WIDTH 2 |
242 | #define OMAP24XX_CLKSEL_L3_SHIFT 0 | 74 | #define OMAP24XX_CLKSEL_L3_SHIFT 0 |
243 | #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) | ||
244 | #define OMAP24XX_CLKSEL_L3_WIDTH 5 | 75 | #define OMAP24XX_CLKSEL_L3_WIDTH 5 |
245 | |||
246 | /* CM_CLKSEL2_CORE */ | ||
247 | #define OMAP24XX_CLKSEL_GPT12_SHIFT 22 | ||
248 | #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) | 76 | #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) |
249 | #define OMAP24XX_CLKSEL_GPT11_SHIFT 20 | ||
250 | #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) | 77 | #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) |
251 | #define OMAP24XX_CLKSEL_GPT10_SHIFT 18 | ||
252 | #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) | 78 | #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) |
253 | #define OMAP24XX_CLKSEL_GPT9_SHIFT 16 | ||
254 | #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) | 79 | #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) |
255 | #define OMAP24XX_CLKSEL_GPT8_SHIFT 14 | ||
256 | #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) | 80 | #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) |
257 | #define OMAP24XX_CLKSEL_GPT7_SHIFT 12 | ||
258 | #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) | 81 | #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) |
259 | #define OMAP24XX_CLKSEL_GPT6_SHIFT 10 | ||
260 | #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) | 82 | #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) |
261 | #define OMAP24XX_CLKSEL_GPT5_SHIFT 8 | ||
262 | #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) | 83 | #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) |
263 | #define OMAP24XX_CLKSEL_GPT4_SHIFT 6 | ||
264 | #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) | 84 | #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) |
265 | #define OMAP24XX_CLKSEL_GPT3_SHIFT 4 | ||
266 | #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) | 85 | #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) |
267 | #define OMAP24XX_CLKSEL_GPT2_SHIFT 2 | ||
268 | #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) | 86 | #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) |
269 | |||
270 | /* CM_CLKSTCTRL_CORE */ | ||
271 | #define OMAP24XX_AUTOSTATE_DSS_SHIFT 2 | ||
272 | #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) | 87 | #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) |
273 | #define OMAP24XX_AUTOSTATE_L4_SHIFT 1 | ||
274 | #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) | 88 | #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) |
275 | #define OMAP24XX_AUTOSTATE_L3_SHIFT 0 | ||
276 | #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) | 89 | #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) |
277 | |||
278 | /* CM_FCLKEN_GFX */ | ||
279 | #define OMAP24XX_EN_3D_SHIFT 2 | 90 | #define OMAP24XX_EN_3D_SHIFT 2 |
280 | #define OMAP24XX_EN_3D_MASK (1 << 2) | ||
281 | #define OMAP24XX_EN_2D_SHIFT 1 | 91 | #define OMAP24XX_EN_2D_SHIFT 1 |
282 | #define OMAP24XX_EN_2D_MASK (1 << 1) | ||
283 | |||
284 | /* CM_ICLKEN_GFX specific bits */ | ||
285 | |||
286 | /* CM_IDLEST_GFX specific bits */ | ||
287 | |||
288 | /* CM_CLKSEL_GFX specific bits */ | ||
289 | |||
290 | /* CM_CLKSTCTRL_GFX */ | ||
291 | #define OMAP24XX_AUTOSTATE_GFX_SHIFT 0 | ||
292 | #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) | 92 | #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) |
293 | |||
294 | /* CM_FCLKEN_WKUP specific bits */ | ||
295 | |||
296 | /* CM_ICLKEN_WKUP specific bits */ | ||
297 | #define OMAP2430_EN_ICR_SHIFT 6 | 93 | #define OMAP2430_EN_ICR_SHIFT 6 |
298 | #define OMAP2430_EN_ICR_MASK (1 << 6) | ||
299 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 | 94 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 |
300 | #define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5) | ||
301 | #define OMAP24XX_EN_WDT1_SHIFT 4 | 95 | #define OMAP24XX_EN_WDT1_SHIFT 4 |
302 | #define OMAP24XX_EN_WDT1_MASK (1 << 4) | ||
303 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 | 96 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 |
304 | #define OMAP24XX_EN_32KSYNC_MASK (1 << 1) | ||
305 | |||
306 | /* CM_IDLEST_WKUP specific bits */ | ||
307 | #define OMAP2430_ST_ICR_SHIFT 6 | ||
308 | #define OMAP2430_ST_ICR_MASK (1 << 6) | ||
309 | #define OMAP24XX_ST_OMAPCTRL_SHIFT 5 | ||
310 | #define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5) | ||
311 | #define OMAP24XX_ST_WDT1_SHIFT 4 | ||
312 | #define OMAP24XX_ST_WDT1_MASK (1 << 4) | ||
313 | #define OMAP24XX_ST_MPU_WDT_SHIFT 3 | 97 | #define OMAP24XX_ST_MPU_WDT_SHIFT 3 |
314 | #define OMAP24XX_ST_MPU_WDT_MASK (1 << 3) | ||
315 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 | 98 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 |
316 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) | ||
317 | |||
318 | /* CM_AUTOIDLE_WKUP */ | ||
319 | #define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5) | ||
320 | #define OMAP24XX_AUTO_WDT1_MASK (1 << 4) | ||
321 | #define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3) | ||
322 | #define OMAP24XX_AUTO_GPIOS_MASK (1 << 2) | ||
323 | #define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1) | ||
324 | #define OMAP24XX_AUTO_GPT1_MASK (1 << 0) | ||
325 | |||
326 | /* CM_CLKSEL_WKUP */ | ||
327 | #define OMAP24XX_CLKSEL_GPT1_SHIFT 0 | ||
328 | #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) | 99 | #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) |
329 | |||
330 | /* CM_CLKEN_PLL */ | ||
331 | #define OMAP24XX_EN_54M_PLL_SHIFT 6 | 100 | #define OMAP24XX_EN_54M_PLL_SHIFT 6 |
332 | #define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6) | ||
333 | #define OMAP24XX_EN_96M_PLL_SHIFT 2 | 101 | #define OMAP24XX_EN_96M_PLL_SHIFT 2 |
334 | #define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) | ||
335 | #define OMAP24XX_EN_DPLL_SHIFT 0 | ||
336 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) | 102 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) |
337 | |||
338 | /* CM_IDLEST_CKGEN */ | ||
339 | #define OMAP24XX_ST_54M_APLL_SHIFT 9 | 103 | #define OMAP24XX_ST_54M_APLL_SHIFT 9 |
340 | #define OMAP24XX_ST_54M_APLL_MASK (1 << 9) | ||
341 | #define OMAP24XX_ST_96M_APLL_SHIFT 8 | 104 | #define OMAP24XX_ST_96M_APLL_SHIFT 8 |
342 | #define OMAP24XX_ST_96M_APLL_MASK (1 << 8) | ||
343 | #define OMAP24XX_ST_54M_CLK_MASK (1 << 6) | ||
344 | #define OMAP24XX_ST_12M_CLK_MASK (1 << 5) | ||
345 | #define OMAP24XX_ST_48M_CLK_MASK (1 << 4) | ||
346 | #define OMAP24XX_ST_96M_CLK_MASK (1 << 2) | ||
347 | #define OMAP24XX_ST_CORE_CLK_SHIFT 0 | ||
348 | #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) | ||
349 | |||
350 | /* CM_AUTOIDLE_PLL */ | ||
351 | #define OMAP24XX_AUTO_54M_SHIFT 6 | ||
352 | #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) | 105 | #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) |
353 | #define OMAP24XX_AUTO_96M_SHIFT 2 | ||
354 | #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) | 106 | #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) |
355 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 | 107 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 |
356 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) | 108 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) |
357 | |||
358 | /* CM_CLKSEL1_PLL */ | ||
359 | #define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 | ||
360 | #define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28) | ||
361 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 | 109 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 |
362 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) | 110 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) |
363 | #define OMAP24XX_DPLL_MULT_SHIFT 12 | ||
364 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) | 111 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) |
365 | #define OMAP24XX_DPLL_DIV_SHIFT 8 | ||
366 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) | 112 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) |
367 | #define OMAP24XX_54M_SOURCE_SHIFT 5 | 113 | #define OMAP24XX_54M_SOURCE_SHIFT 5 |
368 | #define OMAP24XX_54M_SOURCE_MASK (1 << 5) | ||
369 | #define OMAP24XX_54M_SOURCE_WIDTH 1 | 114 | #define OMAP24XX_54M_SOURCE_WIDTH 1 |
370 | #define OMAP2430_96M_SOURCE_SHIFT 4 | 115 | #define OMAP2430_96M_SOURCE_SHIFT 4 |
371 | #define OMAP2430_96M_SOURCE_MASK (1 << 4) | ||
372 | #define OMAP2430_96M_SOURCE_WIDTH 1 | 116 | #define OMAP2430_96M_SOURCE_WIDTH 1 |
373 | #define OMAP24XX_48M_SOURCE_SHIFT 3 | ||
374 | #define OMAP24XX_48M_SOURCE_MASK (1 << 3) | 117 | #define OMAP24XX_48M_SOURCE_MASK (1 << 3) |
375 | #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 | ||
376 | #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) | ||
377 | |||
378 | /* CM_CLKSEL2_PLL */ | ||
379 | #define OMAP24XX_CORE_CLK_SRC_SHIFT 0 | ||
380 | #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) | 118 | #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) |
381 | |||
382 | /* CM_FCLKEN_DSP */ | ||
383 | #define OMAP2420_EN_IVA_COP_SHIFT 10 | 119 | #define OMAP2420_EN_IVA_COP_SHIFT 10 |
384 | #define OMAP2420_EN_IVA_COP_MASK (1 << 10) | ||
385 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 | 120 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 |
386 | #define OMAP2420_EN_IVA_MPU_MASK (1 << 8) | ||
387 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 | 121 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 |
388 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0) | ||
389 | |||
390 | /* CM_ICLKEN_DSP */ | ||
391 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 | 122 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 |
392 | #define OMAP2420_EN_DSP_IPI_MASK (1 << 1) | ||
393 | |||
394 | /* CM_IDLEST_DSP */ | ||
395 | #define OMAP2420_ST_IVA_MASK (1 << 8) | ||
396 | #define OMAP2420_ST_IPI_MASK (1 << 1) | ||
397 | #define OMAP24XX_ST_DSP_MASK (1 << 0) | ||
398 | |||
399 | /* CM_AUTOIDLE_DSP */ | ||
400 | #define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1) | ||
401 | |||
402 | /* CM_CLKSEL_DSP */ | ||
403 | #define OMAP2420_SYNC_IVA_MASK (1 << 13) | ||
404 | #define OMAP2420_CLKSEL_IVA_SHIFT 8 | ||
405 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) | 123 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) |
406 | #define OMAP24XX_SYNC_DSP_MASK (1 << 7) | ||
407 | #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 | ||
408 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) | 124 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) |
409 | #define OMAP24XX_CLKSEL_DSP_SHIFT 0 | ||
410 | #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) | 125 | #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) |
411 | |||
412 | /* CM_CLKSTCTRL_DSP */ | ||
413 | #define OMAP2420_AUTOSTATE_IVA_SHIFT 8 | ||
414 | #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) | 126 | #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) |
415 | #define OMAP24XX_AUTOSTATE_DSP_SHIFT 0 | ||
416 | #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) | 127 | #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) |
417 | |||
418 | /* CM_FCLKEN_MDM */ | ||
419 | /* 2430 only */ | ||
420 | #define OMAP2430_EN_OSC_SHIFT 1 | 128 | #define OMAP2430_EN_OSC_SHIFT 1 |
421 | #define OMAP2430_EN_OSC_MASK (1 << 1) | ||
422 | |||
423 | /* CM_ICLKEN_MDM */ | ||
424 | /* 2430 only */ | ||
425 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 | 129 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 |
426 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0) | ||
427 | |||
428 | /* CM_IDLEST_MDM specific bits */ | ||
429 | /* 2430 only */ | ||
430 | |||
431 | /* CM_AUTOIDLE_MDM */ | ||
432 | /* 2430 only */ | ||
433 | #define OMAP2430_AUTO_OSC_MASK (1 << 1) | ||
434 | #define OMAP2430_AUTO_MDM_MASK (1 << 0) | ||
435 | |||
436 | /* CM_CLKSEL_MDM */ | ||
437 | /* 2430 only */ | ||
438 | #define OMAP2430_SYNC_MDM_MASK (1 << 4) | ||
439 | #define OMAP2430_CLKSEL_MDM_SHIFT 0 | ||
440 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) | 130 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) |
441 | |||
442 | /* CM_CLKSTCTRL_MDM */ | ||
443 | /* 2430 only */ | ||
444 | #define OMAP2430_AUTOSTATE_MDM_SHIFT 0 | ||
445 | #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) | 131 | #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) |
446 | |||
447 | /* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ | ||
448 | #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 | 132 | #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 |
449 | #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 | 133 | #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 |
450 | |||
451 | |||
452 | #endif | 134 | #endif |
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h index adf7bb79b18f..c0823fd6d5e0 100644 --- a/arch/arm/mach-omap2/cm-regbits-33xx.h +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h | |||
@@ -20,798 +20,49 @@ | |||
20 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H | 20 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H |
21 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H | 21 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H |
22 | 22 | ||
23 | /* | ||
24 | * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, | ||
25 | * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER | ||
26 | */ | ||
27 | #define AM33XX_AUTO_DPLL_MODE_SHIFT 0 | ||
28 | #define AM33XX_AUTO_DPLL_MODE_WIDTH 3 | ||
29 | #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) | ||
30 | |||
31 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
32 | #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 | ||
33 | #define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1 | ||
34 | #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) | ||
35 | |||
36 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
37 | #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 | ||
38 | #define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1 | ||
39 | #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) | ||
40 | |||
41 | /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ | ||
42 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 | ||
43 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1 | ||
44 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) | ||
45 | |||
46 | /* Used by CM_PER_CPSW_CLKSTCTRL */ | ||
47 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 | ||
48 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1 | ||
49 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) | ||
50 | |||
51 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
52 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 | ||
53 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1 | ||
54 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) | ||
55 | |||
56 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
57 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 | ||
58 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1 | ||
59 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) | ||
60 | |||
61 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
62 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 | ||
63 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1 | ||
64 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) | ||
65 | |||
66 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
67 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 | ||
68 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1 | ||
69 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) | ||
70 | |||
71 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
72 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 | ||
73 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1 | ||
74 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) | ||
75 | |||
76 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
77 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 | ||
78 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1 | ||
79 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) | ||
80 | |||
81 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
82 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 | ||
83 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1 | ||
84 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) | ||
85 | |||
86 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
87 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 | ||
88 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1 | ||
89 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) | ||
90 | |||
91 | /* Used by CM_GFX_L3_CLKSTCTRL */ | ||
92 | #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 | ||
93 | #define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1 | ||
94 | #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) | ||
95 | |||
96 | /* Used by CM_GFX_L3_CLKSTCTRL */ | ||
97 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 | ||
98 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1 | ||
99 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) | ||
100 | |||
101 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
102 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 | ||
103 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1 | ||
104 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) | ||
105 | |||
106 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
107 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 | ||
108 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1 | ||
109 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) | ||
110 | |||
111 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
112 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 | ||
113 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1 | ||
114 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) | ||
115 | |||
116 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
117 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 | ||
118 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1 | ||
119 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) | ||
120 | |||
121 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
122 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 | ||
123 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1 | ||
124 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) | ||
125 | |||
126 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
127 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 | ||
128 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1 | ||
129 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) | ||
130 | |||
131 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
132 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 | ||
133 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1 | ||
134 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) | ||
135 | |||
136 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
137 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 | ||
138 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1 | ||
139 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) | ||
140 | |||
141 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
142 | #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 | ||
143 | #define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1 | ||
144 | #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) | ||
145 | |||
146 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
147 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 | ||
148 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1 | ||
149 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) | ||
150 | |||
151 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
152 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 | ||
153 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1 | ||
154 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) | ||
155 | |||
156 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
157 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 | ||
158 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1 | ||
159 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) | ||
160 | |||
161 | /* Used by CM_PER_L3S_CLKSTCTRL */ | ||
162 | #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 | ||
163 | #define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1 | ||
164 | #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) | ||
165 | |||
166 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
167 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 | ||
168 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1 | ||
169 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) | ||
170 | |||
171 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
172 | #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 | ||
173 | #define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1 | ||
174 | #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) | ||
175 | |||
176 | /* Used by CM_PER_L4FW_CLKSTCTRL */ | ||
177 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 | ||
178 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1 | ||
179 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) | ||
180 | |||
181 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
182 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 | ||
183 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1 | ||
184 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) | ||
185 | |||
186 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
187 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 | ||
188 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1 | ||
189 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) | ||
190 | |||
191 | /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ | ||
192 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 | ||
193 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1 | ||
194 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) | ||
195 | |||
196 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
197 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 | ||
198 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1 | ||
199 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) | ||
200 | |||
201 | /* Used by CM_RTC_CLKSTCTRL */ | ||
202 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 | ||
203 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1 | ||
204 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) | ||
205 | |||
206 | /* Used by CM_L4_WKUP_AON_CLKSTCTRL */ | ||
207 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 | ||
208 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1 | ||
209 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) | ||
210 | |||
211 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
212 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 | ||
213 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1 | ||
214 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) | ||
215 | |||
216 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
217 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 | ||
218 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1 | ||
219 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) | ||
220 | |||
221 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | ||
222 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 | ||
223 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1 | ||
224 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) | ||
225 | |||
226 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | ||
227 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 | ||
228 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1 | ||
229 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) | ||
230 | |||
231 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
232 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 | ||
233 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1 | ||
234 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) | ||
235 | |||
236 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
237 | #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 | ||
238 | #define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1 | ||
239 | #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) | ||
240 | |||
241 | /* Used by CM_MPU_CLKSTCTRL */ | ||
242 | #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 | ||
243 | #define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1 | ||
244 | #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) | ||
245 | |||
246 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | ||
247 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 | ||
248 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1 | ||
249 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) | ||
250 | |||
251 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | ||
252 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 | ||
253 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1 | ||
254 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) | ||
255 | |||
256 | /* Used by CM_RTC_CLKSTCTRL */ | ||
257 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 | ||
258 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1 | ||
259 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) | ||
260 | |||
261 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
262 | #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 | ||
263 | #define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1 | ||
264 | #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) | ||
265 | |||
266 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
267 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 | ||
268 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1 | ||
269 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) | ||
270 | |||
271 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
272 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 | ||
273 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1 | ||
274 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) | ||
275 | |||
276 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
277 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 | ||
278 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1 | ||
279 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) | ||
280 | |||
281 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
282 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 | ||
283 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1 | ||
284 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) | ||
285 | |||
286 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
287 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 | ||
288 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1 | ||
289 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) | ||
290 | |||
291 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
292 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 | ||
293 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1 | ||
294 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) | ||
295 | |||
296 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
297 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 | ||
298 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1 | ||
299 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) | ||
300 | |||
301 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
302 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 | ||
303 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1 | ||
304 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) | ||
305 | |||
306 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
307 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 | ||
308 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1 | ||
309 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) | ||
310 | |||
311 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
312 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 | ||
313 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1 | ||
314 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) | ||
315 | |||
316 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
317 | #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 | ||
318 | #define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1 | ||
319 | #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) | ||
320 | |||
321 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
322 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 | ||
323 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1 | ||
324 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) | ||
325 | |||
326 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
327 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 | ||
328 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1 | ||
329 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) | ||
330 | |||
331 | /* Used by CLKSEL_GFX_FCLK */ | ||
332 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 | ||
333 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1 | ||
334 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) | ||
335 | |||
336 | /* Used by CM_CLKOUT_CTRL */ | ||
337 | #define AM33XX_CLKOUT2DIV_SHIFT 3 | 23 | #define AM33XX_CLKOUT2DIV_SHIFT 3 |
338 | #define AM33XX_CLKOUT2DIV_WIDTH 3 | 24 | #define AM33XX_CLKOUT2DIV_WIDTH 3 |
339 | #define AM33XX_CLKOUT2DIV_MASK (0x7 << 3) | ||
340 | |||
341 | /* Used by CM_CLKOUT_CTRL */ | ||
342 | #define AM33XX_CLKOUT2EN_SHIFT 7 | 25 | #define AM33XX_CLKOUT2EN_SHIFT 7 |
343 | #define AM33XX_CLKOUT2EN_WIDTH 1 | ||
344 | #define AM33XX_CLKOUT2EN_MASK (1 << 7) | ||
345 | |||
346 | /* Used by CM_CLKOUT_CTRL */ | ||
347 | #define AM33XX_CLKOUT2SOURCE_SHIFT 0 | ||
348 | #define AM33XX_CLKOUT2SOURCE_WIDTH 3 | ||
349 | #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) | 26 | #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) |
350 | |||
351 | /* | ||
352 | * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, | ||
353 | * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, | ||
354 | * CLKSEL_TIMER7_CLK | ||
355 | */ | ||
356 | #define AM33XX_CLKSEL_SHIFT 0 | ||
357 | #define AM33XX_CLKSEL_WIDTH 1 | ||
358 | #define AM33XX_CLKSEL_MASK (0x01 << 0) | ||
359 | |||
360 | /* | ||
361 | * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, | ||
362 | * CM_CPTS_RFT_CLKSEL | ||
363 | */ | ||
364 | #define AM33XX_CLKSEL_0_0_SHIFT 0 | 27 | #define AM33XX_CLKSEL_0_0_SHIFT 0 |
365 | #define AM33XX_CLKSEL_0_0_WIDTH 1 | 28 | #define AM33XX_CLKSEL_0_0_WIDTH 1 |
366 | #define AM33XX_CLKSEL_0_0_MASK (1 << 0) | 29 | #define AM33XX_CLKSEL_0_0_MASK (1 << 0) |
367 | |||
368 | #define AM33XX_CLKSEL_0_1_SHIFT 0 | ||
369 | #define AM33XX_CLKSEL_0_1_WIDTH 2 | ||
370 | #define AM33XX_CLKSEL_0_1_MASK (3 << 0) | 30 | #define AM33XX_CLKSEL_0_1_MASK (3 << 0) |
371 | |||
372 | /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ | ||
373 | #define AM33XX_CLKSEL_0_2_SHIFT 0 | ||
374 | #define AM33XX_CLKSEL_0_2_WIDTH 3 | ||
375 | #define AM33XX_CLKSEL_0_2_MASK (7 << 0) | 31 | #define AM33XX_CLKSEL_0_2_MASK (7 << 0) |
376 | |||
377 | /* Used by CLKSEL_GFX_FCLK */ | ||
378 | #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 | ||
379 | #define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1 | ||
380 | #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) | 32 | #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) |
381 | |||
382 | /* | ||
383 | * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, | ||
384 | * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, | ||
385 | * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, | ||
386 | * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, | ||
387 | * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, | ||
388 | * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL | ||
389 | */ | ||
390 | #define AM33XX_CLKTRCTRL_SHIFT 0 | 33 | #define AM33XX_CLKTRCTRL_SHIFT 0 |
391 | #define AM33XX_CLKTRCTRL_WIDTH 2 | ||
392 | #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) | 34 | #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) |
393 | |||
394 | /* | ||
395 | * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, | ||
396 | * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, | ||
397 | * CM_SSC_DELTAMSTEP_DPLL_PER | ||
398 | */ | ||
399 | #define AM33XX_DELTAMSTEP_SHIFT 0 | ||
400 | #define AM33XX_DELTAMSTEP_WIDTH 20 | ||
401 | #define AM33XX_DELTAMSTEP_MASK (0xfffff << 0) | ||
402 | |||
403 | /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ | ||
404 | #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 | ||
405 | #define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1 | ||
406 | #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) | ||
407 | |||
408 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
409 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 | ||
410 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1 | ||
411 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) | ||
412 | |||
413 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
414 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 | ||
415 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1 | ||
416 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) | ||
417 | |||
418 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | ||
419 | #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 | 35 | #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 |
420 | #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 | 36 | #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 |
421 | #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
422 | |||
423 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ | ||
424 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 | ||
425 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7 | ||
426 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) | ||
427 | |||
428 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | ||
429 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 | ||
430 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1 | ||
431 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) | ||
432 | |||
433 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ | ||
434 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 | ||
435 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1 | ||
436 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) | ||
437 | |||
438 | /* | ||
439 | * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, | ||
440 | * CM_DIV_M2_DPLL_PER | ||
441 | */ | ||
442 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 | ||
443 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1 | ||
444 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | ||
445 | |||
446 | /* | ||
447 | * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, | ||
448 | * CM_CLKSEL_DPLL_MPU | ||
449 | */ | ||
450 | #define AM33XX_DPLL_DIV_SHIFT 0 | ||
451 | #define AM33XX_DPLL_DIV_WIDTH 7 | ||
452 | #define AM33XX_DPLL_DIV_MASK (0x7f << 0) | 37 | #define AM33XX_DPLL_DIV_MASK (0x7f << 0) |
453 | |||
454 | #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) | 38 | #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) |
455 | |||
456 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ | ||
457 | #define AM33XX_DPLL_DIV_0_7_SHIFT 0 | ||
458 | #define AM33XX_DPLL_DIV_0_7_WIDTH 8 | ||
459 | #define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0) | ||
460 | |||
461 | /* | ||
462 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
463 | * CM_CLKMODE_DPLL_MPU | ||
464 | */ | ||
465 | #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 | ||
466 | #define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1 | ||
467 | #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | ||
468 | |||
469 | /* | ||
470 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
471 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
472 | */ | ||
473 | #define AM33XX_DPLL_EN_SHIFT 0 | ||
474 | #define AM33XX_DPLL_EN_WIDTH 3 | ||
475 | #define AM33XX_DPLL_EN_MASK (0x7 << 0) | 39 | #define AM33XX_DPLL_EN_MASK (0x7 << 0) |
476 | |||
477 | /* | ||
478 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
479 | * CM_CLKMODE_DPLL_MPU | ||
480 | */ | ||
481 | #define AM33XX_DPLL_LPMODE_EN_SHIFT 10 | ||
482 | #define AM33XX_DPLL_LPMODE_EN_WIDTH 1 | ||
483 | #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) | ||
484 | |||
485 | /* | ||
486 | * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, | ||
487 | * CM_CLKSEL_DPLL_MPU | ||
488 | */ | ||
489 | #define AM33XX_DPLL_MULT_SHIFT 8 | ||
490 | #define AM33XX_DPLL_MULT_WIDTH 11 | ||
491 | #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) | 40 | #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) |
492 | |||
493 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ | ||
494 | #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 | ||
495 | #define AM33XX_DPLL_MULT_PERIPH_WIDTH 12 | ||
496 | #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) | 41 | #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) |
497 | |||
498 | /* | ||
499 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
500 | * CM_CLKMODE_DPLL_MPU | ||
501 | */ | ||
502 | #define AM33XX_DPLL_REGM4XEN_SHIFT 11 | ||
503 | #define AM33XX_DPLL_REGM4XEN_WIDTH 1 | ||
504 | #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) | ||
505 | |||
506 | /* Used by CM_CLKSEL_DPLL_PERIPH */ | ||
507 | #define AM33XX_DPLL_SD_DIV_SHIFT 24 | ||
508 | #define AM33XX_DPLL_SD_DIV_WIDTH 8 | ||
509 | #define AM33XX_DPLL_SD_DIV_MASK (0xff << 24) | ||
510 | |||
511 | /* | ||
512 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
513 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
514 | */ | ||
515 | #define AM33XX_DPLL_SSC_ACK_SHIFT 13 | ||
516 | #define AM33XX_DPLL_SSC_ACK_WIDTH 1 | ||
517 | #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) | ||
518 | |||
519 | /* | ||
520 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
521 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
522 | */ | ||
523 | #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 | ||
524 | #define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1 | ||
525 | #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) | ||
526 | |||
527 | /* | ||
528 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
529 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
530 | */ | ||
531 | #define AM33XX_DPLL_SSC_EN_SHIFT 12 | ||
532 | #define AM33XX_DPLL_SSC_EN_WIDTH 1 | ||
533 | #define AM33XX_DPLL_SSC_EN_MASK (1 << 12) | ||
534 | |||
535 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
536 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 | 42 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 |
537 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 | 43 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 |
538 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) | ||
539 | |||
540 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
541 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 | ||
542 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1 | ||
543 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) | ||
544 | |||
545 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
546 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 | ||
547 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1 | ||
548 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) | ||
549 | |||
550 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
551 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 | ||
552 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1 | ||
553 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) | ||
554 | |||
555 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
556 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 | 44 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 |
557 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 | 45 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 |
558 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) | ||
559 | |||
560 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
561 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 | ||
562 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1 | ||
563 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) | ||
564 | |||
565 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
566 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 | ||
567 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1 | ||
568 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) | ||
569 | |||
570 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
571 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 | ||
572 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1 | ||
573 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) | ||
574 | |||
575 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
576 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 | 46 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 |
577 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 | 47 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 |
578 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) | ||
579 | |||
580 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
581 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 | ||
582 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1 | ||
583 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) | ||
584 | |||
585 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
586 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 | ||
587 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1 | ||
588 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) | ||
589 | |||
590 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
591 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 | ||
592 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1 | ||
593 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) | ||
594 | |||
595 | /* | ||
596 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | ||
597 | * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, | ||
598 | * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, | ||
599 | * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, | ||
600 | * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, | ||
601 | * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, | ||
602 | * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, | ||
603 | * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, | ||
604 | * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, | ||
605 | * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, | ||
606 | * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, | ||
607 | * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, | ||
608 | * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, | ||
609 | * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, | ||
610 | * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
611 | * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, | ||
612 | * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, | ||
613 | * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, | ||
614 | * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, | ||
615 | * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, | ||
616 | * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, | ||
617 | * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
618 | * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, | ||
619 | * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, | ||
620 | * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, | ||
621 | * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, | ||
622 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, | ||
623 | * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, | ||
624 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, | ||
625 | * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, | ||
626 | * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL | ||
627 | */ | ||
628 | #define AM33XX_IDLEST_SHIFT 16 | 48 | #define AM33XX_IDLEST_SHIFT 16 |
629 | #define AM33XX_IDLEST_WIDTH 2 | ||
630 | #define AM33XX_IDLEST_MASK (0x3 << 16) | 49 | #define AM33XX_IDLEST_MASK (0x3 << 16) |
631 | |||
632 | /* Used by CM_MAC_CLKSEL */ | ||
633 | #define AM33XX_MII_CLK_SEL_SHIFT 2 | ||
634 | #define AM33XX_MII_CLK_SEL_WIDTH 1 | ||
635 | #define AM33XX_MII_CLK_SEL_MASK (1 << 2) | ||
636 | |||
637 | /* | ||
638 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | ||
639 | * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
640 | * CM_SSC_MODFREQDIV_DPLL_PER | ||
641 | */ | ||
642 | #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 | ||
643 | #define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3 | ||
644 | #define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) | ||
645 | |||
646 | /* | ||
647 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | ||
648 | * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
649 | * CM_SSC_MODFREQDIV_DPLL_PER | ||
650 | */ | ||
651 | #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 | ||
652 | #define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7 | ||
653 | #define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) | ||
654 | |||
655 | /* | ||
656 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | ||
657 | * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, | ||
658 | * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, | ||
659 | * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, | ||
660 | * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, | ||
661 | * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, | ||
662 | * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, | ||
663 | * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, | ||
664 | * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, | ||
665 | * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, | ||
666 | * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, | ||
667 | * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, | ||
668 | * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, | ||
669 | * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, | ||
670 | * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
671 | * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, | ||
672 | * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, | ||
673 | * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, | ||
674 | * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, | ||
675 | * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, | ||
676 | * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, | ||
677 | * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
678 | * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, | ||
679 | * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, | ||
680 | * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, | ||
681 | * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, | ||
682 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, | ||
683 | * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, | ||
684 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, | ||
685 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, | ||
686 | * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, | ||
687 | * CM_CEFUSE_CEFUSE_CLKCTRL | ||
688 | */ | ||
689 | #define AM33XX_MODULEMODE_SHIFT 0 | 50 | #define AM33XX_MODULEMODE_SHIFT 0 |
690 | #define AM33XX_MODULEMODE_WIDTH 2 | ||
691 | #define AM33XX_MODULEMODE_MASK (0x3 << 0) | 51 | #define AM33XX_MODULEMODE_MASK (0x3 << 0) |
692 | |||
693 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
694 | #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 | 52 | #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 |
695 | #define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1 | ||
696 | #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) | ||
697 | |||
698 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
699 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 | 53 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 |
700 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1 | ||
701 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) | ||
702 | |||
703 | /* Used by CM_WKUP_GPIO0_CLKCTRL */ | ||
704 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 | 54 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 |
705 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1 | ||
706 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) | ||
707 | |||
708 | /* Used by CM_PER_GPIO1_CLKCTRL */ | ||
709 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 | 55 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 |
710 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1 | ||
711 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) | ||
712 | |||
713 | /* Used by CM_PER_GPIO2_CLKCTRL */ | ||
714 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 | 56 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 |
715 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1 | ||
716 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) | ||
717 | |||
718 | /* Used by CM_PER_GPIO3_CLKCTRL */ | ||
719 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 | 57 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 |
720 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1 | ||
721 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) | ||
722 | |||
723 | /* Used by CM_PER_GPIO4_CLKCTRL */ | ||
724 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 | ||
725 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1 | ||
726 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) | ||
727 | |||
728 | /* Used by CM_PER_GPIO5_CLKCTRL */ | ||
729 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 | ||
730 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1 | ||
731 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) | ||
732 | |||
733 | /* Used by CM_PER_GPIO6_CLKCTRL */ | ||
734 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 | ||
735 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1 | ||
736 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) | ||
737 | |||
738 | /* | ||
739 | * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, | ||
740 | * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, | ||
741 | * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
742 | * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
743 | * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, | ||
744 | * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL | ||
745 | */ | ||
746 | #define AM33XX_STBYST_SHIFT 18 | ||
747 | #define AM33XX_STBYST_WIDTH 1 | ||
748 | #define AM33XX_STBYST_MASK (1 << 18) | ||
749 | |||
750 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
751 | #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 | 58 | #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 |
752 | #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 | 59 | #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 |
753 | #define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27) | ||
754 | |||
755 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
756 | #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 | 60 | #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 |
757 | #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 | 61 | #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 |
758 | #define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22) | ||
759 | |||
760 | /* | ||
761 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | ||
762 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | ||
763 | */ | ||
764 | #define AM33XX_ST_DPLL_CLK_SHIFT 0 | ||
765 | #define AM33XX_ST_DPLL_CLK_WIDTH 1 | ||
766 | #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) | 62 | #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) |
767 | |||
768 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
769 | #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 | 63 | #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 |
770 | #define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1 | ||
771 | #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) | ||
772 | |||
773 | /* | ||
774 | * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, | ||
775 | * CM_DIV_M2_DPLL_PER | ||
776 | */ | ||
777 | #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 | ||
778 | #define AM33XX_ST_DPLL_CLKOUT_WIDTH 1 | ||
779 | #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) | ||
780 | |||
781 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
782 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 | ||
783 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1 | ||
784 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) | ||
785 | |||
786 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
787 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 | ||
788 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1 | ||
789 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) | ||
790 | |||
791 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
792 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 | ||
793 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1 | ||
794 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) | ||
795 | |||
796 | /* | ||
797 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | ||
798 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | ||
799 | */ | ||
800 | #define AM33XX_ST_MN_BYPASS_SHIFT 8 | ||
801 | #define AM33XX_ST_MN_BYPASS_WIDTH 1 | ||
802 | #define AM33XX_ST_MN_BYPASS_MASK (1 << 8) | ||
803 | |||
804 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
805 | #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 | 64 | #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 |
806 | #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 | 65 | #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 |
807 | #define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24) | ||
808 | |||
809 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
810 | #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 | 66 | #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 |
811 | #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 | 67 | #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 |
812 | #define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20) | ||
813 | |||
814 | /* Used by CONTROL_SEC_CLK_CTRL */ | ||
815 | #define AM33XX_TIMER0_CLKSEL_WIDTH 2 | ||
816 | #define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) | ||
817 | #endif | 68 | #endif |
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index adf78d325804..04dab2fcf862 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
@@ -14,833 +14,201 @@ | |||
14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | /* Bits shared between registers */ | ||
18 | |||
19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | ||
20 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) | ||
21 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 | 17 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 |
22 | #define OMAP3430_EN_MSPRO_MASK (1 << 23) | ||
23 | #define OMAP3430_EN_MSPRO_SHIFT 23 | 18 | #define OMAP3430_EN_MSPRO_SHIFT 23 |
24 | #define OMAP3430_EN_HDQ_MASK (1 << 22) | ||
25 | #define OMAP3430_EN_HDQ_SHIFT 22 | 19 | #define OMAP3430_EN_HDQ_SHIFT 22 |
26 | #define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) | ||
27 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 | 20 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 |
28 | #define OMAP3430ES1_EN_D2D_MASK (1 << 3) | ||
29 | #define OMAP3430ES1_EN_D2D_SHIFT 3 | 21 | #define OMAP3430ES1_EN_D2D_SHIFT 3 |
30 | #define OMAP3430_EN_SSI_MASK (1 << 0) | ||
31 | #define OMAP3430_EN_SSI_SHIFT 0 | 22 | #define OMAP3430_EN_SSI_SHIFT 0 |
32 | |||
33 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ | ||
34 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 | 23 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 |
35 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) | ||
36 | |||
37 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | ||
38 | #define OMAP3430_EN_WDT2_MASK (1 << 5) | ||
39 | #define OMAP3430_EN_WDT2_SHIFT 5 | 24 | #define OMAP3430_EN_WDT2_SHIFT 5 |
40 | |||
41 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ | ||
42 | #define OMAP3430_EN_CAM_MASK (1 << 0) | ||
43 | #define OMAP3430_EN_CAM_SHIFT 0 | 25 | #define OMAP3430_EN_CAM_SHIFT 0 |
44 | |||
45 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ | ||
46 | #define OMAP3430_EN_WDT3_MASK (1 << 12) | ||
47 | #define OMAP3430_EN_WDT3_SHIFT 12 | 26 | #define OMAP3430_EN_WDT3_SHIFT 12 |
48 | |||
49 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ | ||
50 | #define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) | ||
51 | |||
52 | |||
53 | /* Bits specific to each register */ | ||
54 | |||
55 | /* CM_FCLKEN_IVA2 */ | ||
56 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) | 27 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
57 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 | 28 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 |
58 | |||
59 | /* CM_CLKEN_PLL_IVA2 */ | ||
60 | #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 | ||
61 | #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
62 | #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 | ||
63 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) | 29 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) |
64 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 | 30 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 |
65 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
66 | #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 | ||
67 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | 31 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) |
68 | |||
69 | /* CM_IDLEST_IVA2 */ | ||
70 | #define OMAP3430_ST_IVA2_SHIFT 0 | 32 | #define OMAP3430_ST_IVA2_SHIFT 0 |
71 | #define OMAP3430_ST_IVA2_MASK (1 << 0) | ||
72 | |||
73 | /* CM_IDLEST_PLL_IVA2 */ | ||
74 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 | ||
75 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | 33 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) |
76 | |||
77 | /* CM_AUTOIDLE_PLL_IVA2 */ | ||
78 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 | ||
79 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) | 34 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) |
80 | |||
81 | /* CM_CLKSEL1_PLL_IVA2 */ | ||
82 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 | 35 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 |
83 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) | ||
84 | #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 | 36 | #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 |
85 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 | ||
86 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) | 37 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) |
87 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 | ||
88 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) | 38 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) |
89 | |||
90 | /* CM_CLKSEL2_PLL_IVA2 */ | ||
91 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 | 39 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 |
92 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
93 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 | 40 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 |
94 | |||
95 | /* CM_CLKSTCTRL_IVA2 */ | ||
96 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 | ||
97 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) | 41 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) |
98 | |||
99 | /* CM_CLKSTST_IVA2 */ | ||
100 | #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 | ||
101 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) | 42 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) |
102 | |||
103 | /* CM_REVISION specific bits */ | ||
104 | |||
105 | /* CM_SYSCONFIG specific bits */ | ||
106 | |||
107 | /* CM_CLKEN_PLL_MPU */ | ||
108 | #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 | ||
109 | #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
110 | #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 | ||
111 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) | 43 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) |
112 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 | 44 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 |
113 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
114 | #define OMAP3430_EN_MPU_DPLL_SHIFT 0 | ||
115 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) | 45 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) |
116 | |||
117 | /* CM_IDLEST_MPU */ | ||
118 | #define OMAP3430_ST_MPU_MASK (1 << 0) | ||
119 | |||
120 | /* CM_IDLEST_PLL_MPU */ | ||
121 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 | 46 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
122 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) | 47 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) |
123 | #define OMAP3430_ST_MPU_CLK_WIDTH 1 | 48 | #define OMAP3430_ST_MPU_CLK_WIDTH 1 |
124 | |||
125 | /* CM_AUTOIDLE_PLL_MPU */ | ||
126 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 | ||
127 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) | 49 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) |
128 | |||
129 | /* CM_CLKSEL1_PLL_MPU */ | ||
130 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 | 50 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 |
131 | #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) | ||
132 | #define OMAP3430_MPU_CLK_SRC_WIDTH 3 | 51 | #define OMAP3430_MPU_CLK_SRC_WIDTH 3 |
133 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 | ||
134 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) | 52 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) |
135 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 | ||
136 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) | 53 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) |
137 | |||
138 | /* CM_CLKSEL2_PLL_MPU */ | ||
139 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 | 54 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 |
140 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
141 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 | 55 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 |
142 | |||
143 | /* CM_CLKSTCTRL_MPU */ | ||
144 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 | ||
145 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) | 56 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) |
146 | |||
147 | /* CM_CLKSTST_MPU */ | ||
148 | #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 | ||
149 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | ||
150 | |||
151 | /* CM_FCLKEN1_CORE specific bits */ | ||
152 | #define OMAP3430_EN_MODEM_MASK (1 << 31) | ||
153 | #define OMAP3430_EN_MODEM_SHIFT 31 | 57 | #define OMAP3430_EN_MODEM_SHIFT 31 |
154 | |||
155 | /* CM_ICLKEN1_CORE specific bits */ | ||
156 | #define OMAP3430_EN_ICR_MASK (1 << 29) | ||
157 | #define OMAP3430_EN_ICR_SHIFT 29 | 58 | #define OMAP3430_EN_ICR_SHIFT 29 |
158 | #define OMAP3430_EN_AES2_MASK (1 << 28) | ||
159 | #define OMAP3430_EN_AES2_SHIFT 28 | 59 | #define OMAP3430_EN_AES2_SHIFT 28 |
160 | #define OMAP3430_EN_SHA12_MASK (1 << 27) | ||
161 | #define OMAP3430_EN_SHA12_SHIFT 27 | 60 | #define OMAP3430_EN_SHA12_SHIFT 27 |
162 | #define OMAP3430_EN_DES2_MASK (1 << 26) | ||
163 | #define OMAP3430_EN_DES2_SHIFT 26 | 61 | #define OMAP3430_EN_DES2_SHIFT 26 |
164 | #define OMAP3430ES1_EN_FAC_MASK (1 << 8) | ||
165 | #define OMAP3430ES1_EN_FAC_SHIFT 8 | 62 | #define OMAP3430ES1_EN_FAC_SHIFT 8 |
166 | #define OMAP3430_EN_MAILBOXES_MASK (1 << 7) | ||
167 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 | 63 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 |
168 | #define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) | ||
169 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 | 64 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 |
170 | #define OMAP3430_EN_SAD2D_MASK (1 << 3) | ||
171 | #define OMAP3430_EN_SAD2D_SHIFT 3 | 65 | #define OMAP3430_EN_SAD2D_SHIFT 3 |
172 | #define OMAP3430_EN_SDRC_MASK (1 << 1) | ||
173 | #define OMAP3430_EN_SDRC_SHIFT 1 | 66 | #define OMAP3430_EN_SDRC_SHIFT 1 |
174 | |||
175 | /* AM35XX specific CM_ICLKEN1_CORE bits */ | ||
176 | #define AM35XX_EN_IPSS_MASK (1 << 4) | ||
177 | #define AM35XX_EN_IPSS_SHIFT 4 | 67 | #define AM35XX_EN_IPSS_SHIFT 4 |
178 | |||
179 | /* CM_ICLKEN2_CORE */ | ||
180 | #define OMAP3430_EN_PKA_MASK (1 << 4) | ||
181 | #define OMAP3430_EN_PKA_SHIFT 4 | 68 | #define OMAP3430_EN_PKA_SHIFT 4 |
182 | #define OMAP3430_EN_AES1_MASK (1 << 3) | ||
183 | #define OMAP3430_EN_AES1_SHIFT 3 | 69 | #define OMAP3430_EN_AES1_SHIFT 3 |
184 | #define OMAP3430_EN_RNG_MASK (1 << 2) | ||
185 | #define OMAP3430_EN_RNG_SHIFT 2 | 70 | #define OMAP3430_EN_RNG_SHIFT 2 |
186 | #define OMAP3430_EN_SHA11_MASK (1 << 1) | ||
187 | #define OMAP3430_EN_SHA11_SHIFT 1 | 71 | #define OMAP3430_EN_SHA11_SHIFT 1 |
188 | #define OMAP3430_EN_DES1_MASK (1 << 0) | ||
189 | #define OMAP3430_EN_DES1_SHIFT 0 | 72 | #define OMAP3430_EN_DES1_SHIFT 0 |
190 | |||
191 | /* CM_ICLKEN3_CORE */ | ||
192 | #define OMAP3430_EN_MAD2D_SHIFT 3 | 73 | #define OMAP3430_EN_MAD2D_SHIFT 3 |
193 | #define OMAP3430_EN_MAD2D_MASK (1 << 3) | ||
194 | |||
195 | /* CM_FCLKEN3_CORE specific bits */ | ||
196 | #define OMAP3430ES2_EN_TS_SHIFT 1 | 74 | #define OMAP3430ES2_EN_TS_SHIFT 1 |
197 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) | ||
198 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 | 75 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 |
199 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | ||
200 | |||
201 | /* CM_IDLEST1_CORE specific bits */ | ||
202 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 | ||
203 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) | ||
204 | #define OMAP3430_ST_ICR_SHIFT 29 | ||
205 | #define OMAP3430_ST_ICR_MASK (1 << 29) | ||
206 | #define OMAP3430_ST_AES2_SHIFT 28 | 76 | #define OMAP3430_ST_AES2_SHIFT 28 |
207 | #define OMAP3430_ST_AES2_MASK (1 << 28) | ||
208 | #define OMAP3430_ST_SHA12_SHIFT 27 | 77 | #define OMAP3430_ST_SHA12_SHIFT 27 |
209 | #define OMAP3430_ST_SHA12_MASK (1 << 27) | ||
210 | #define OMAP3430_ST_DES2_SHIFT 26 | ||
211 | #define OMAP3430_ST_DES2_MASK (1 << 26) | ||
212 | #define OMAP3430_ST_MSPRO_SHIFT 23 | ||
213 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) | ||
214 | #define AM35XX_ST_UART4_SHIFT 23 | 78 | #define AM35XX_ST_UART4_SHIFT 23 |
215 | #define AM35XX_ST_UART4_MASK (1 << 23) | ||
216 | #define OMAP3430_ST_HDQ_SHIFT 22 | 79 | #define OMAP3430_ST_HDQ_SHIFT 22 |
217 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | ||
218 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | ||
219 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | ||
220 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | 80 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 |
221 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | ||
222 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | 81 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 |
223 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | ||
224 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | ||
225 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | ||
226 | #define OMAP3430_ST_SAD2D_SHIFT 3 | 82 | #define OMAP3430_ST_SAD2D_SHIFT 3 |
227 | #define OMAP3430_ST_SAD2D_MASK (1 << 3) | ||
228 | #define OMAP3430_ST_SDMA_SHIFT 2 | 83 | #define OMAP3430_ST_SDMA_SHIFT 2 |
229 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | ||
230 | #define OMAP3430_ST_SDRC_SHIFT 1 | ||
231 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | ||
232 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | ||
233 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | ||
234 | |||
235 | /* AM35xx specific CM_IDLEST1_CORE bits */ | ||
236 | #define AM35XX_ST_IPSS_SHIFT 5 | 84 | #define AM35XX_ST_IPSS_SHIFT 5 |
237 | #define AM35XX_ST_IPSS_MASK (1 << 5) | ||
238 | |||
239 | /* CM_IDLEST2_CORE */ | ||
240 | #define OMAP3430_ST_PKA_SHIFT 4 | ||
241 | #define OMAP3430_ST_PKA_MASK (1 << 4) | ||
242 | #define OMAP3430_ST_AES1_SHIFT 3 | ||
243 | #define OMAP3430_ST_AES1_MASK (1 << 3) | ||
244 | #define OMAP3430_ST_RNG_SHIFT 2 | ||
245 | #define OMAP3430_ST_RNG_MASK (1 << 2) | ||
246 | #define OMAP3430_ST_SHA11_SHIFT 1 | ||
247 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | ||
248 | #define OMAP3430_ST_DES1_SHIFT 0 | ||
249 | #define OMAP3430_ST_DES1_MASK (1 << 0) | ||
250 | |||
251 | /* CM_IDLEST3_CORE */ | ||
252 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | 85 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 |
253 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | ||
254 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 | ||
255 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | ||
256 | |||
257 | /* CM_AUTOIDLE1_CORE */ | ||
258 | #define OMAP3430_AUTO_MODEM_MASK (1 << 31) | ||
259 | #define OMAP3430_AUTO_MODEM_SHIFT 31 | ||
260 | #define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) | ||
261 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 | ||
262 | #define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) | ||
263 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 | ||
264 | #define OMAP3430_AUTO_AES2_MASK (1 << 28) | ||
265 | #define OMAP3430_AUTO_AES2_SHIFT 28 | ||
266 | #define OMAP3430_AUTO_SHA12_MASK (1 << 27) | ||
267 | #define OMAP3430_AUTO_SHA12_SHIFT 27 | ||
268 | #define OMAP3430_AUTO_DES2_MASK (1 << 26) | ||
269 | #define OMAP3430_AUTO_DES2_SHIFT 26 | ||
270 | #define OMAP3430_AUTO_MMC2_MASK (1 << 25) | ||
271 | #define OMAP3430_AUTO_MMC2_SHIFT 25 | ||
272 | #define OMAP3430_AUTO_MMC1_MASK (1 << 24) | ||
273 | #define OMAP3430_AUTO_MMC1_SHIFT 24 | ||
274 | #define OMAP3430_AUTO_MSPRO_MASK (1 << 23) | ||
275 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 | ||
276 | #define OMAP3430_AUTO_HDQ_MASK (1 << 22) | ||
277 | #define OMAP3430_AUTO_HDQ_SHIFT 22 | ||
278 | #define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) | ||
279 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 | ||
280 | #define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) | ||
281 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 | ||
282 | #define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) | ||
283 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 | ||
284 | #define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) | ||
285 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 | ||
286 | #define OMAP3430_AUTO_I2C3_MASK (1 << 17) | ||
287 | #define OMAP3430_AUTO_I2C3_SHIFT 17 | ||
288 | #define OMAP3430_AUTO_I2C2_MASK (1 << 16) | ||
289 | #define OMAP3430_AUTO_I2C2_SHIFT 16 | ||
290 | #define OMAP3430_AUTO_I2C1_MASK (1 << 15) | ||
291 | #define OMAP3430_AUTO_I2C1_SHIFT 15 | ||
292 | #define OMAP3430_AUTO_UART2_MASK (1 << 14) | ||
293 | #define OMAP3430_AUTO_UART2_SHIFT 14 | ||
294 | #define OMAP3430_AUTO_UART1_MASK (1 << 13) | ||
295 | #define OMAP3430_AUTO_UART1_SHIFT 13 | ||
296 | #define OMAP3430_AUTO_GPT11_MASK (1 << 12) | ||
297 | #define OMAP3430_AUTO_GPT11_SHIFT 12 | ||
298 | #define OMAP3430_AUTO_GPT10_MASK (1 << 11) | ||
299 | #define OMAP3430_AUTO_GPT10_SHIFT 11 | ||
300 | #define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) | ||
301 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 | ||
302 | #define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) | ||
303 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 | ||
304 | #define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) | ||
305 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 | ||
306 | #define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) | ||
307 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 | ||
308 | #define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) | ||
309 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 | ||
310 | #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) | ||
311 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 | ||
312 | #define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) | ||
313 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 | ||
314 | #define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) | ||
315 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 | ||
316 | #define OMAP3430_AUTO_SAD2D_MASK (1 << 3) | ||
317 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 | ||
318 | #define OMAP3430_AUTO_SSI_MASK (1 << 0) | ||
319 | #define OMAP3430_AUTO_SSI_SHIFT 0 | ||
320 | |||
321 | /* CM_AUTOIDLE2_CORE */ | ||
322 | #define OMAP3430_AUTO_PKA_MASK (1 << 4) | ||
323 | #define OMAP3430_AUTO_PKA_SHIFT 4 | ||
324 | #define OMAP3430_AUTO_AES1_MASK (1 << 3) | ||
325 | #define OMAP3430_AUTO_AES1_SHIFT 3 | ||
326 | #define OMAP3430_AUTO_RNG_MASK (1 << 2) | ||
327 | #define OMAP3430_AUTO_RNG_SHIFT 2 | ||
328 | #define OMAP3430_AUTO_SHA11_MASK (1 << 1) | ||
329 | #define OMAP3430_AUTO_SHA11_SHIFT 1 | ||
330 | #define OMAP3430_AUTO_DES1_MASK (1 << 0) | ||
331 | #define OMAP3430_AUTO_DES1_SHIFT 0 | ||
332 | |||
333 | /* CM_AUTOIDLE3_CORE */ | ||
334 | #define OMAP3430ES2_AUTO_USBHOST (1 << 0) | ||
335 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
336 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | ||
337 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 | ||
338 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | ||
339 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 | ||
340 | #define OMAP3430_AUTO_MAD2D_MASK (1 << 3) | ||
341 | |||
342 | /* CM_CLKSEL_CORE */ | ||
343 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | ||
344 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) | 86 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) |
345 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) | 87 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) |
346 | #define OMAP3430_CLKSEL_GPT11_SHIFT 7 | ||
347 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) | 88 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) |
348 | #define OMAP3430_CLKSEL_GPT10_SHIFT 6 | ||
349 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 | ||
350 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) | 89 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) |
351 | #define OMAP3430_CLKSEL_L4_SHIFT 2 | 90 | #define OMAP3430_CLKSEL_L4_SHIFT 2 |
352 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | ||
353 | #define OMAP3430_CLKSEL_L4_WIDTH 2 | 91 | #define OMAP3430_CLKSEL_L4_WIDTH 2 |
354 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | 92 | #define OMAP3430_CLKSEL_L3_SHIFT 0 |
355 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | ||
356 | #define OMAP3430_CLKSEL_L3_WIDTH 2 | 93 | #define OMAP3430_CLKSEL_L3_WIDTH 2 |
357 | #define OMAP3630_CLKSEL_96M_SHIFT 12 | ||
358 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) | 94 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) |
359 | #define OMAP3630_CLKSEL_96M_WIDTH 2 | ||
360 | |||
361 | /* CM_CLKSTCTRL_CORE */ | ||
362 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | ||
363 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) | 95 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) |
364 | #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 | ||
365 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) | 96 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) |
366 | #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 | ||
367 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) | 97 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) |
368 | |||
369 | /* CM_CLKSTST_CORE */ | ||
370 | #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 | ||
371 | #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) | ||
372 | #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 | ||
373 | #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) | ||
374 | #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 | ||
375 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) | ||
376 | |||
377 | /* CM_FCLKEN_GFX */ | ||
378 | #define OMAP3430ES1_EN_3D_MASK (1 << 2) | ||
379 | #define OMAP3430ES1_EN_3D_SHIFT 2 | 98 | #define OMAP3430ES1_EN_3D_SHIFT 2 |
380 | #define OMAP3430ES1_EN_2D_MASK (1 << 1) | ||
381 | #define OMAP3430ES1_EN_2D_SHIFT 1 | 99 | #define OMAP3430ES1_EN_2D_SHIFT 1 |
382 | |||
383 | /* CM_ICLKEN_GFX specific bits */ | ||
384 | |||
385 | /* CM_IDLEST_GFX specific bits */ | ||
386 | |||
387 | /* CM_CLKSEL_GFX specific bits */ | ||
388 | |||
389 | /* CM_SLEEPDEP_GFX specific bits */ | ||
390 | |||
391 | /* CM_CLKSTCTRL_GFX */ | ||
392 | #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 | ||
393 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) | 100 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) |
394 | |||
395 | /* CM_CLKSTST_GFX */ | ||
396 | #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 | ||
397 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | ||
398 | |||
399 | /* CM_FCLKEN_SGX */ | ||
400 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 | 101 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
401 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) | ||
402 | |||
403 | /* CM_IDLEST_SGX */ | ||
404 | #define OMAP3430ES2_ST_SGX_SHIFT 1 | ||
405 | #define OMAP3430ES2_ST_SGX_MASK (1 << 1) | ||
406 | |||
407 | /* CM_ICLKEN_SGX */ | ||
408 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | 102 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 |
409 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | ||
410 | |||
411 | /* CM_CLKSEL_SGX */ | ||
412 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | ||
413 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) | 103 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) |
414 | |||
415 | /* CM_CLKSTCTRL_SGX */ | ||
416 | #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 | ||
417 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) | 104 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) |
418 | |||
419 | /* CM_CLKSTST_SGX */ | ||
420 | #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 | ||
421 | #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) | ||
422 | |||
423 | /* CM_FCLKEN_WKUP specific bits */ | ||
424 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | 105 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 |
425 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) | ||
426 | |||
427 | /* CM_ICLKEN_WKUP specific bits */ | ||
428 | #define OMAP3430_EN_WDT1_MASK (1 << 4) | ||
429 | #define OMAP3430_EN_WDT1_SHIFT 4 | 106 | #define OMAP3430_EN_WDT1_SHIFT 4 |
430 | #define OMAP3430_EN_32KSYNC_MASK (1 << 2) | ||
431 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | 107 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
432 | |||
433 | /* CM_IDLEST_WKUP specific bits */ | ||
434 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 | ||
435 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) | ||
436 | #define OMAP3430_ST_WDT2_SHIFT 5 | 108 | #define OMAP3430_ST_WDT2_SHIFT 5 |
437 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | ||
438 | #define OMAP3430_ST_WDT1_SHIFT 4 | ||
439 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | ||
440 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | 109 | #define OMAP3430_ST_32KSYNC_SHIFT 2 |
441 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | ||
442 | |||
443 | /* CM_AUTOIDLE_WKUP */ | ||
444 | #define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) | ||
445 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 | ||
446 | #define OMAP3430_AUTO_WDT2_MASK (1 << 5) | ||
447 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | ||
448 | #define OMAP3430_AUTO_WDT1_MASK (1 << 4) | ||
449 | #define OMAP3430_AUTO_WDT1_SHIFT 4 | ||
450 | #define OMAP3430_AUTO_GPIO1_MASK (1 << 3) | ||
451 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 | ||
452 | #define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) | ||
453 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 | ||
454 | #define OMAP3430_AUTO_GPT12_MASK (1 << 1) | ||
455 | #define OMAP3430_AUTO_GPT12_SHIFT 1 | ||
456 | #define OMAP3430_AUTO_GPT1_MASK (1 << 0) | ||
457 | #define OMAP3430_AUTO_GPT1_SHIFT 0 | ||
458 | |||
459 | /* CM_CLKSEL_WKUP */ | ||
460 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) | 110 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) |
461 | #define OMAP3430_CLKSEL_RM_SHIFT 1 | 111 | #define OMAP3430_CLKSEL_RM_SHIFT 1 |
462 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) | ||
463 | #define OMAP3430_CLKSEL_RM_WIDTH 2 | 112 | #define OMAP3430_CLKSEL_RM_WIDTH 2 |
464 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 | ||
465 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) | 113 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) |
466 | |||
467 | /* CM_CLKEN_PLL */ | ||
468 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 | 114 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 |
469 | #define OMAP3430_PWRDN_CAM_SHIFT 30 | 115 | #define OMAP3430_PWRDN_CAM_SHIFT 30 |
470 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 | 116 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 |
471 | #define OMAP3430_PWRDN_TV_SHIFT 28 | 117 | #define OMAP3430_PWRDN_TV_SHIFT 28 |
472 | #define OMAP3430_PWRDN_96M_SHIFT 27 | 118 | #define OMAP3430_PWRDN_96M_SHIFT 27 |
473 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 | ||
474 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) | ||
475 | #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 | ||
476 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) | 119 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) |
477 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 | 120 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 |
478 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) | ||
479 | #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 | ||
480 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) | 121 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) |
481 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 | 122 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 |
482 | #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 | ||
483 | #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
484 | #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 | ||
485 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) | 123 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) |
486 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 | 124 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 |
487 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
488 | #define OMAP3430_EN_CORE_DPLL_SHIFT 0 | ||
489 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) | 125 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) |
490 | |||
491 | /* CM_CLKEN2_PLL */ | ||
492 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 | ||
493 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
494 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 | ||
495 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) | 126 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) |
496 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 | 127 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 |
497 | #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 | ||
498 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) | 128 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) |
499 | |||
500 | /* CM_IDLEST_CKGEN */ | ||
501 | #define OMAP3430_ST_54M_CLK_MASK (1 << 5) | ||
502 | #define OMAP3430_ST_12M_CLK_MASK (1 << 4) | ||
503 | #define OMAP3430_ST_48M_CLK_MASK (1 << 3) | ||
504 | #define OMAP3430_ST_96M_CLK_MASK (1 << 2) | ||
505 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 | ||
506 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) | 129 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) |
507 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 | ||
508 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | 130 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) |
509 | |||
510 | /* CM_IDLEST2_CKGEN */ | ||
511 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 | ||
512 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | ||
513 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 | ||
514 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | ||
515 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | ||
516 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) | 131 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) |
517 | |||
518 | /* CM_AUTOIDLE_PLL */ | ||
519 | #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 | ||
520 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) | 132 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) |
521 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 | ||
522 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) | 133 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) |
523 | |||
524 | /* CM_AUTOIDLE2_PLL */ | ||
525 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 | ||
526 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) | 134 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) |
527 | |||
528 | /* CM_CLKSEL1_PLL */ | ||
529 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | ||
530 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | 135 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 |
531 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) | ||
532 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 | 136 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 |
533 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 | ||
534 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | 137 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) |
535 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | ||
536 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | 138 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) |
537 | #define OMAP3430_SOURCE_96M_SHIFT 6 | 139 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
538 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) | ||
539 | #define OMAP3430_SOURCE_96M_WIDTH 1 | 140 | #define OMAP3430_SOURCE_96M_WIDTH 1 |
540 | #define OMAP3430_SOURCE_54M_SHIFT 5 | 141 | #define OMAP3430_SOURCE_54M_SHIFT 5 |
541 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | ||
542 | #define OMAP3430_SOURCE_54M_WIDTH 1 | 142 | #define OMAP3430_SOURCE_54M_WIDTH 1 |
543 | #define OMAP3430_SOURCE_48M_SHIFT 3 | ||
544 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | 143 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) |
545 | |||
546 | /* CM_CLKSEL2_PLL */ | ||
547 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | ||
548 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | 144 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) |
549 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) | 145 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) |
550 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 | ||
551 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | 146 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) |
552 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 | ||
553 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) | 147 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) |
554 | #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 | ||
555 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) | 148 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) |
556 | |||
557 | /* CM_CLKSEL3_PLL */ | ||
558 | #define OMAP3430_DIV_96M_SHIFT 0 | 149 | #define OMAP3430_DIV_96M_SHIFT 0 |
559 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | ||
560 | #define OMAP3430_DIV_96M_WIDTH 5 | ||
561 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) | ||
562 | #define OMAP3630_DIV_96M_WIDTH 6 | 150 | #define OMAP3630_DIV_96M_WIDTH 6 |
563 | |||
564 | /* CM_CLKSEL4_PLL */ | ||
565 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | ||
566 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) | 151 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) |
567 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 | ||
568 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) | 152 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) |
569 | |||
570 | /* CM_CLKSEL5_PLL */ | ||
571 | #define OMAP3430ES2_DIV_120M_SHIFT 0 | 153 | #define OMAP3430ES2_DIV_120M_SHIFT 0 |
572 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) | ||
573 | #define OMAP3430ES2_DIV_120M_WIDTH 5 | 154 | #define OMAP3430ES2_DIV_120M_WIDTH 5 |
574 | |||
575 | /* CM_CLKOUT_CTRL */ | ||
576 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | 155 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 |
577 | #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) | ||
578 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 | 156 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 |
579 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | ||
580 | #define OMAP3430_CLKOUT2_DIV_WIDTH 3 | 157 | #define OMAP3430_CLKOUT2_DIV_WIDTH 3 |
581 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | ||
582 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | 158 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) |
583 | |||
584 | /* CM_FCLKEN_DSS */ | ||
585 | #define OMAP3430_EN_TV_MASK (1 << 2) | ||
586 | #define OMAP3430_EN_TV_SHIFT 2 | 159 | #define OMAP3430_EN_TV_SHIFT 2 |
587 | #define OMAP3430_EN_DSS2_MASK (1 << 1) | ||
588 | #define OMAP3430_EN_DSS2_SHIFT 1 | 160 | #define OMAP3430_EN_DSS2_SHIFT 1 |
589 | #define OMAP3430_EN_DSS1_MASK (1 << 0) | ||
590 | #define OMAP3430_EN_DSS1_SHIFT 0 | 161 | #define OMAP3430_EN_DSS1_SHIFT 0 |
591 | |||
592 | /* CM_ICLKEN_DSS */ | ||
593 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) | ||
594 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | 162 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
595 | |||
596 | /* CM_IDLEST_DSS */ | ||
597 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 | 163 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
598 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | ||
599 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | 164 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 |
600 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | ||
601 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | 165 | #define OMAP3430ES1_ST_DSS_SHIFT 0 |
602 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | ||
603 | |||
604 | /* CM_AUTOIDLE_DSS */ | ||
605 | #define OMAP3430_AUTO_DSS_MASK (1 << 0) | ||
606 | #define OMAP3430_AUTO_DSS_SHIFT 0 | ||
607 | |||
608 | /* CM_CLKSEL_DSS */ | ||
609 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | 166 | #define OMAP3430_CLKSEL_TV_SHIFT 8 |
610 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | ||
611 | #define OMAP3430_CLKSEL_TV_WIDTH 5 | ||
612 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) | ||
613 | #define OMAP3630_CLKSEL_TV_WIDTH 6 | 167 | #define OMAP3630_CLKSEL_TV_WIDTH 6 |
614 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | 168 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
615 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | ||
616 | #define OMAP3430_CLKSEL_DSS1_WIDTH 5 | ||
617 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) | ||
618 | #define OMAP3630_CLKSEL_DSS1_WIDTH 6 | 169 | #define OMAP3630_CLKSEL_DSS1_WIDTH 6 |
619 | |||
620 | /* CM_SLEEPDEP_DSS specific bits */ | ||
621 | |||
622 | /* CM_CLKSTCTRL_DSS */ | ||
623 | #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 | ||
624 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) | 170 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) |
625 | |||
626 | /* CM_CLKSTST_DSS */ | ||
627 | #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 | ||
628 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | ||
629 | |||
630 | /* CM_FCLKEN_CAM specific bits */ | ||
631 | #define OMAP3430_EN_CSI2_MASK (1 << 1) | ||
632 | #define OMAP3430_EN_CSI2_SHIFT 1 | 171 | #define OMAP3430_EN_CSI2_SHIFT 1 |
633 | |||
634 | /* CM_ICLKEN_CAM specific bits */ | ||
635 | |||
636 | /* CM_IDLEST_CAM */ | ||
637 | #define OMAP3430_ST_CAM_MASK (1 << 0) | ||
638 | |||
639 | /* CM_AUTOIDLE_CAM */ | ||
640 | #define OMAP3430_AUTO_CAM_MASK (1 << 0) | ||
641 | #define OMAP3430_AUTO_CAM_SHIFT 0 | ||
642 | |||
643 | /* CM_CLKSEL_CAM */ | ||
644 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | 172 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 |
645 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | ||
646 | #define OMAP3430_CLKSEL_CAM_WIDTH 5 | ||
647 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) | ||
648 | #define OMAP3630_CLKSEL_CAM_WIDTH 6 | 173 | #define OMAP3630_CLKSEL_CAM_WIDTH 6 |
649 | |||
650 | /* CM_SLEEPDEP_CAM specific bits */ | ||
651 | |||
652 | /* CM_CLKSTCTRL_CAM */ | ||
653 | #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 | ||
654 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) | 174 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) |
655 | |||
656 | /* CM_CLKSTST_CAM */ | ||
657 | #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 | ||
658 | #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) | ||
659 | |||
660 | /* CM_FCLKEN_PER specific bits */ | ||
661 | |||
662 | /* CM_ICLKEN_PER specific bits */ | ||
663 | |||
664 | /* CM_IDLEST_PER */ | ||
665 | #define OMAP3430_ST_WDT3_SHIFT 12 | ||
666 | #define OMAP3430_ST_WDT3_MASK (1 << 12) | ||
667 | #define OMAP3430_ST_MCBSP4_SHIFT 2 | 175 | #define OMAP3430_ST_MCBSP4_SHIFT 2 |
668 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) | ||
669 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | 176 | #define OMAP3430_ST_MCBSP3_SHIFT 1 |
670 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | ||
671 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | 177 | #define OMAP3430_ST_MCBSP2_SHIFT 0 |
672 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | ||
673 | |||
674 | /* CM_AUTOIDLE_PER */ | ||
675 | #define OMAP3630_AUTO_UART4_MASK (1 << 18) | ||
676 | #define OMAP3630_AUTO_UART4_SHIFT 18 | ||
677 | #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) | ||
678 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 | ||
679 | #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) | ||
680 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 | ||
681 | #define OMAP3430_AUTO_GPIO4_MASK (1 << 15) | ||
682 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 | ||
683 | #define OMAP3430_AUTO_GPIO3_MASK (1 << 14) | ||
684 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 | ||
685 | #define OMAP3430_AUTO_GPIO2_MASK (1 << 13) | ||
686 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 | ||
687 | #define OMAP3430_AUTO_WDT3_MASK (1 << 12) | ||
688 | #define OMAP3430_AUTO_WDT3_SHIFT 12 | ||
689 | #define OMAP3430_AUTO_UART3_MASK (1 << 11) | ||
690 | #define OMAP3430_AUTO_UART3_SHIFT 11 | ||
691 | #define OMAP3430_AUTO_GPT9_MASK (1 << 10) | ||
692 | #define OMAP3430_AUTO_GPT9_SHIFT 10 | ||
693 | #define OMAP3430_AUTO_GPT8_MASK (1 << 9) | ||
694 | #define OMAP3430_AUTO_GPT8_SHIFT 9 | ||
695 | #define OMAP3430_AUTO_GPT7_MASK (1 << 8) | ||
696 | #define OMAP3430_AUTO_GPT7_SHIFT 8 | ||
697 | #define OMAP3430_AUTO_GPT6_MASK (1 << 7) | ||
698 | #define OMAP3430_AUTO_GPT6_SHIFT 7 | ||
699 | #define OMAP3430_AUTO_GPT5_MASK (1 << 6) | ||
700 | #define OMAP3430_AUTO_GPT5_SHIFT 6 | ||
701 | #define OMAP3430_AUTO_GPT4_MASK (1 << 5) | ||
702 | #define OMAP3430_AUTO_GPT4_SHIFT 5 | ||
703 | #define OMAP3430_AUTO_GPT3_MASK (1 << 4) | ||
704 | #define OMAP3430_AUTO_GPT3_SHIFT 4 | ||
705 | #define OMAP3430_AUTO_GPT2_MASK (1 << 3) | ||
706 | #define OMAP3430_AUTO_GPT2_SHIFT 3 | ||
707 | #define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) | ||
708 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 | ||
709 | #define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) | ||
710 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 | ||
711 | #define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) | ||
712 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 | ||
713 | |||
714 | /* CM_CLKSEL_PER */ | ||
715 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) | 178 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) |
716 | #define OMAP3430_CLKSEL_GPT9_SHIFT 7 | ||
717 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) | 179 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) |
718 | #define OMAP3430_CLKSEL_GPT8_SHIFT 6 | ||
719 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) | 180 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) |
720 | #define OMAP3430_CLKSEL_GPT7_SHIFT 5 | ||
721 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) | 181 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) |
722 | #define OMAP3430_CLKSEL_GPT6_SHIFT 4 | ||
723 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) | 182 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) |
724 | #define OMAP3430_CLKSEL_GPT5_SHIFT 3 | ||
725 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) | 183 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) |
726 | #define OMAP3430_CLKSEL_GPT4_SHIFT 2 | ||
727 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) | 184 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) |
728 | #define OMAP3430_CLKSEL_GPT3_SHIFT 1 | ||
729 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) | 185 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) |
730 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 | ||
731 | |||
732 | /* CM_SLEEPDEP_PER specific bits */ | ||
733 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) | ||
734 | |||
735 | /* CM_CLKSTCTRL_PER */ | ||
736 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 | ||
737 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) | 186 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) |
738 | |||
739 | /* CM_CLKSTST_PER */ | ||
740 | #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 | ||
741 | #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) | ||
742 | |||
743 | /* CM_CLKSEL1_EMU */ | ||
744 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | 187 | #define OMAP3430_DIV_DPLL4_SHIFT 24 |
745 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | ||
746 | #define OMAP3430_DIV_DPLL4_WIDTH 5 | ||
747 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) | ||
748 | #define OMAP3630_DIV_DPLL4_WIDTH 6 | 188 | #define OMAP3630_DIV_DPLL4_WIDTH 6 |
749 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | 189 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
750 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | ||
751 | #define OMAP3430_DIV_DPLL3_WIDTH 5 | 190 | #define OMAP3430_DIV_DPLL3_WIDTH 5 |
752 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | 191 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 |
753 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) | ||
754 | #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 | 192 | #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 |
755 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 | 193 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 |
756 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) | ||
757 | #define OMAP3430_CLKSEL_PCLK_WIDTH 3 | 194 | #define OMAP3430_CLKSEL_PCLK_WIDTH 3 |
758 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 | 195 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 |
759 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) | ||
760 | #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 | 196 | #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 |
761 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 | 197 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 |
762 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) | ||
763 | #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 | 198 | #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 |
764 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 | 199 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 |
765 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) | ||
766 | #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 | 200 | #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 |
767 | #define OMAP3430_MUX_CTRL_SHIFT 0 | ||
768 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) | 201 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) |
769 | #define OMAP3430_MUX_CTRL_WIDTH 2 | ||
770 | |||
771 | /* CM_CLKSTCTRL_EMU */ | ||
772 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 | ||
773 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) | 202 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) |
774 | |||
775 | /* CM_CLKSTST_EMU */ | ||
776 | #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 | ||
777 | #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) | ||
778 | |||
779 | /* CM_CLKSEL2_EMU specific bits */ | ||
780 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 | ||
781 | #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
782 | #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 | ||
783 | #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
784 | |||
785 | /* CM_CLKSEL3_EMU specific bits */ | ||
786 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 | ||
787 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
788 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 | ||
789 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
790 | |||
791 | /* CM_POLCTRL */ | ||
792 | #define OMAP3430_CLKOUT2_POL_MASK (1 << 0) | ||
793 | |||
794 | /* CM_IDLEST_NEON */ | ||
795 | #define OMAP3430_ST_NEON_MASK (1 << 0) | ||
796 | |||
797 | /* CM_CLKSTCTRL_NEON */ | ||
798 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 | ||
799 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) | 203 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) |
800 | |||
801 | /* CM_FCLKEN_USBHOST */ | ||
802 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 | 204 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 |
803 | #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) | ||
804 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 | 205 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 |
805 | #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) | ||
806 | |||
807 | /* CM_ICLKEN_USBHOST */ | ||
808 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 | 206 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 |
809 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | ||
810 | |||
811 | /* CM_IDLEST_USBHOST */ | ||
812 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 | 207 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 |
813 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | ||
814 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | 208 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 |
815 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | ||
816 | |||
817 | /* CM_AUTOIDLE_USBHOST */ | ||
818 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
819 | #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) | ||
820 | |||
821 | /* CM_SLEEPDEP_USBHOST */ | ||
822 | #define OMAP3430ES2_EN_MPU_SHIFT 1 | ||
823 | #define OMAP3430ES2_EN_MPU_MASK (1 << 1) | ||
824 | #define OMAP3430ES2_EN_IVA2_SHIFT 2 | ||
825 | #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) | ||
826 | |||
827 | /* CM_CLKSTCTRL_USBHOST */ | ||
828 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 | ||
829 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) | 209 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) |
830 | |||
831 | /* CM_CLKSTST_USBHOST */ | ||
832 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 | ||
833 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) | ||
834 | |||
835 | /* | ||
836 | * | ||
837 | */ | ||
838 | |||
839 | /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ | ||
840 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 | 210 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 |
841 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 | 211 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 |
842 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 | 212 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 |
843 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 | 213 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 |
844 | |||
845 | |||
846 | #endif | 214 | #endif |
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 4c6c2f7de65b..4dbbd99b6e1e 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h | |||
@@ -22,1683 +22,125 @@ | |||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | 23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
24 | 24 | ||
25 | /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ | ||
26 | #define OMAP4430_ABE_DYNDEP_SHIFT 3 | ||
27 | #define OMAP4430_ABE_DYNDEP_WIDTH 0x1 | ||
28 | #define OMAP4430_ABE_DYNDEP_MASK (1 << 3) | ||
29 | |||
30 | /* | ||
31 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, | ||
32 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
33 | */ | ||
34 | #define OMAP4430_ABE_STATDEP_SHIFT 3 | 25 | #define OMAP4430_ABE_STATDEP_SHIFT 3 |
35 | #define OMAP4430_ABE_STATDEP_WIDTH 0x1 | ||
36 | #define OMAP4430_ABE_STATDEP_MASK (1 << 3) | ||
37 | |||
38 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
39 | #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 | ||
40 | #define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1 | ||
41 | #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) | ||
42 | |||
43 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | ||
44 | #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 | ||
45 | #define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1 | ||
46 | #define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) | ||
47 | |||
48 | /* | ||
49 | * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, | ||
50 | * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, | ||
51 | * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB | ||
52 | */ | ||
53 | #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 | ||
54 | #define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3 | ||
55 | #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) | 26 | #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) |
56 | |||
57 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
58 | #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 | ||
59 | #define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1 | ||
60 | #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) | ||
61 | |||
62 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | ||
63 | #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 | ||
64 | #define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1 | ||
65 | #define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) | ||
66 | |||
67 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
68 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 | ||
69 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 | ||
70 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) | ||
71 | |||
72 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
73 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 | ||
74 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1 | ||
75 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) | ||
76 | |||
77 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
78 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 | ||
79 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 | ||
80 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) | ||
81 | |||
82 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
83 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 | ||
84 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1 | ||
85 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) | ||
86 | |||
87 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
88 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 | ||
89 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 | ||
90 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) | ||
91 | |||
92 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
93 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 | ||
94 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1 | ||
95 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) | ||
96 | |||
97 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
98 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 | ||
99 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1 | ||
100 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) | ||
101 | |||
102 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
103 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 | ||
104 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1 | ||
105 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) | ||
106 | |||
107 | /* Used by CM_CAM_CLKSTCTRL */ | ||
108 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 | ||
109 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1 | ||
110 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) | ||
111 | |||
112 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
113 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 | ||
114 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1 | ||
115 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) | ||
116 | |||
117 | /* Used by CM_EMU_CLKSTCTRL */ | ||
118 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 | ||
119 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1 | ||
120 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) | ||
121 | |||
122 | /* Used by CM_L4CFG_CLKSTCTRL */ | ||
123 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 | ||
124 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1 | ||
125 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) | ||
126 | |||
127 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
128 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 | ||
129 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1 | ||
130 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) | ||
131 | |||
132 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
133 | #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 | ||
134 | #define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1 | ||
135 | #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) | ||
136 | |||
137 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
138 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 | ||
139 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1 | ||
140 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) | ||
141 | |||
142 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
143 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 | ||
144 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1 | ||
145 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) | ||
146 | |||
147 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
148 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 | ||
149 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1 | ||
150 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) | ||
151 | |||
152 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
153 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 | ||
154 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1 | ||
155 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) | ||
156 | |||
157 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
158 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 | ||
159 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1 | ||
160 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) | ||
161 | |||
162 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
163 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 | ||
164 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1 | ||
165 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) | ||
166 | |||
167 | /* Used by CM_DSS_CLKSTCTRL */ | ||
168 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 | ||
169 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1 | ||
170 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) | ||
171 | |||
172 | /* Used by CM_DSS_CLKSTCTRL */ | ||
173 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 | ||
174 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1 | ||
175 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) | ||
176 | |||
177 | /* Used by CM_DUCATI_CLKSTCTRL */ | ||
178 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 | ||
179 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1 | ||
180 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) | ||
181 | |||
182 | /* Used by CM_EMU_CLKSTCTRL */ | ||
183 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 | ||
184 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1 | ||
185 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) | ||
186 | |||
187 | /* Used by CM_CAM_CLKSTCTRL */ | ||
188 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 | ||
189 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1 | ||
190 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) | ||
191 | |||
192 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
193 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 | ||
194 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1 | ||
195 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) | ||
196 | |||
197 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
198 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 | ||
199 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 | ||
200 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) | ||
201 | |||
202 | /* Used by CM_DSS_CLKSTCTRL */ | ||
203 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 | ||
204 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1 | ||
205 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) | ||
206 | |||
207 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
208 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 | ||
209 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 | ||
210 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) | ||
211 | |||
212 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
213 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 | ||
214 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 | ||
215 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) | ||
216 | |||
217 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
218 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 | ||
219 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 | ||
220 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) | ||
221 | |||
222 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
223 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 | ||
224 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 | ||
225 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) | ||
226 | |||
227 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
228 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 | ||
229 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1 | ||
230 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) | ||
231 | |||
232 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
233 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 | ||
234 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1 | ||
235 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) | ||
236 | |||
237 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
238 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 | ||
239 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1 | ||
240 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) | ||
241 | |||
242 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
243 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 | ||
244 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1 | ||
245 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) | ||
246 | |||
247 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
248 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 | ||
249 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1 | ||
250 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) | ||
251 | |||
252 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
253 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 | ||
254 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1 | ||
255 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) | ||
256 | |||
257 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
258 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 | ||
259 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1 | ||
260 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) | ||
261 | |||
262 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
263 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 | ||
264 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1 | ||
265 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) | ||
266 | |||
267 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
268 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 | ||
269 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1 | ||
270 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) | ||
271 | |||
272 | /* Used by CM_CAM_CLKSTCTRL */ | ||
273 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 | ||
274 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1 | ||
275 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) | ||
276 | |||
277 | /* Used by CM_IVAHD_CLKSTCTRL */ | ||
278 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 | ||
279 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1 | ||
280 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) | ||
281 | |||
282 | /* Used by CM_D2D_CLKSTCTRL */ | ||
283 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 | ||
284 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1 | ||
285 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) | ||
286 | |||
287 | /* Used by CM_L3_1_CLKSTCTRL */ | ||
288 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 | ||
289 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1 | ||
290 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) | ||
291 | |||
292 | /* Used by CM_L3_2_CLKSTCTRL */ | ||
293 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 | ||
294 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1 | ||
295 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) | ||
296 | |||
297 | /* Used by CM_D2D_CLKSTCTRL */ | ||
298 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 | ||
299 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1 | ||
300 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) | ||
301 | |||
302 | /* Used by CM_SDMA_CLKSTCTRL */ | ||
303 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 | ||
304 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1 | ||
305 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) | ||
306 | |||
307 | /* Used by CM_DSS_CLKSTCTRL */ | ||
308 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 | ||
309 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1 | ||
310 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) | ||
311 | |||
312 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
313 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 | ||
314 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1 | ||
315 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) | ||
316 | |||
317 | /* Used by CM_GFX_CLKSTCTRL */ | ||
318 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 | ||
319 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1 | ||
320 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) | ||
321 | |||
322 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
323 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 | ||
324 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1 | ||
325 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) | ||
326 | |||
327 | /* Used by CM_L3INSTR_CLKSTCTRL */ | ||
328 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 | ||
329 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1 | ||
330 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) | ||
331 | |||
332 | /* Used by CM_L4SEC_CLKSTCTRL */ | ||
333 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 | ||
334 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1 | ||
335 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) | ||
336 | |||
337 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
338 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 | ||
339 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1 | ||
340 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) | ||
341 | |||
342 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
343 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 | ||
344 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1 | ||
345 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) | ||
346 | |||
347 | /* Used by CM_L4CFG_CLKSTCTRL */ | ||
348 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 | ||
349 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1 | ||
350 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) | ||
351 | |||
352 | /* Used by CM_D2D_CLKSTCTRL */ | ||
353 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 | ||
354 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1 | ||
355 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) | ||
356 | |||
357 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
358 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 | ||
359 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1 | ||
360 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) | ||
361 | |||
362 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
363 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 | ||
364 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1 | ||
365 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) | ||
366 | |||
367 | /* Used by CM_L4SEC_CLKSTCTRL */ | ||
368 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 | ||
369 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1 | ||
370 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) | ||
371 | |||
372 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
373 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 | ||
374 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1 | ||
375 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) | ||
376 | |||
377 | /* Used by CM_MPU_CLKSTCTRL */ | ||
378 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 | ||
379 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1 | ||
380 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) | ||
381 | |||
382 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
383 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 | ||
384 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1 | ||
385 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) | ||
386 | |||
387 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
388 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 | ||
389 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1 | ||
390 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) | ||
391 | |||
392 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
393 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 | ||
394 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 | ||
395 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) | ||
396 | |||
397 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
398 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 | ||
399 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 | ||
400 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) | ||
401 | |||
402 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
403 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 | ||
404 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 | ||
405 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) | ||
406 | |||
407 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
408 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 | ||
409 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1 | ||
410 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) | ||
411 | |||
412 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
413 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 | ||
414 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1 | ||
415 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) | ||
416 | |||
417 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
418 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 | ||
419 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) | ||
420 | |||
421 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
422 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 | ||
423 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1 | ||
424 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) | ||
425 | |||
426 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
427 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 | ||
428 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1 | ||
429 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) | ||
430 | |||
431 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
432 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 | ||
433 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1 | ||
434 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) | ||
435 | |||
436 | /* Used by CM_GFX_CLKSTCTRL */ | ||
437 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 | ||
438 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1 | ||
439 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) | ||
440 | |||
441 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
442 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 | ||
443 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1 | ||
444 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) | ||
445 | |||
446 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
447 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 | ||
448 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1 | ||
449 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) | ||
450 | |||
451 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
452 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 | ||
453 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1 | ||
454 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) | ||
455 | |||
456 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
457 | #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 | ||
458 | #define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1 | ||
459 | #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) | ||
460 | |||
461 | /* Used by CM_TESLA_CLKSTCTRL */ | ||
462 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 | ||
463 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1 | ||
464 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) | ||
465 | |||
466 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
467 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 | ||
468 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 | ||
469 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) | ||
470 | |||
471 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
472 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 | ||
473 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 | ||
474 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) | ||
475 | |||
476 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
477 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 | ||
478 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 | ||
479 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) | ||
480 | |||
481 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
482 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 | ||
483 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1 | ||
484 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) | ||
485 | |||
486 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
487 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 | ||
488 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 | ||
489 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) | ||
490 | |||
491 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
492 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 | ||
493 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 | ||
494 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) | ||
495 | |||
496 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
497 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 | ||
498 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1 | ||
499 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) | ||
500 | |||
501 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
502 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 | ||
503 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 | ||
504 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) | ||
505 | |||
506 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
507 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 | ||
508 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 | ||
509 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) | ||
510 | |||
511 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
512 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 | ||
513 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1 | ||
514 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) | ||
515 | |||
516 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
517 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 | ||
518 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1 | ||
519 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) | ||
520 | |||
521 | /* | ||
522 | * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, | ||
523 | * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | ||
524 | * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, | ||
525 | * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, | ||
526 | * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, | ||
527 | * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL | ||
528 | */ | ||
529 | #define OMAP4430_CLKSEL_SHIFT 24 | 27 | #define OMAP4430_CLKSEL_SHIFT 24 |
530 | #define OMAP4430_CLKSEL_WIDTH 0x1 | 28 | #define OMAP4430_CLKSEL_WIDTH 0x1 |
531 | #define OMAP4430_CLKSEL_MASK (1 << 24) | 29 | #define OMAP4430_CLKSEL_MASK (1 << 24) |
532 | |||
533 | /* | ||
534 | * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, | ||
535 | * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL | ||
536 | */ | ||
537 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 | 30 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 |
538 | #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 | 31 | #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 |
539 | #define OMAP4430_CLKSEL_0_0_MASK (1 << 0) | ||
540 | |||
541 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ | ||
542 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 | 32 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 |
543 | #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 | 33 | #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 |
544 | #define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) | ||
545 | |||
546 | /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ | ||
547 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 | 34 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 |
548 | #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 | 35 | #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 |
549 | #define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) | ||
550 | |||
551 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | ||
552 | #define OMAP4430_CLKSEL_60M_SHIFT 24 | 36 | #define OMAP4430_CLKSEL_60M_SHIFT 24 |
553 | #define OMAP4430_CLKSEL_60M_WIDTH 0x1 | 37 | #define OMAP4430_CLKSEL_60M_WIDTH 0x1 |
554 | #define OMAP4430_CLKSEL_60M_MASK (1 << 24) | ||
555 | |||
556 | /* Used by CM_MPU_MPU_CLKCTRL */ | ||
557 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 | ||
558 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 | ||
559 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) | ||
560 | |||
561 | /* Used by CM1_ABE_AESS_CLKCTRL */ | ||
562 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 | 38 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 |
563 | #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 | 39 | #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 |
564 | #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) | ||
565 | |||
566 | /* Used by CM_CLKSEL_CORE */ | ||
567 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 | 40 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 |
568 | #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 | 41 | #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 |
569 | #define OMAP4430_CLKSEL_CORE_MASK (1 << 0) | ||
570 | |||
571 | /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
572 | #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 | ||
573 | #define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1 | ||
574 | #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) | ||
575 | |||
576 | /* Used by CM_WKUP_USIM_CLKCTRL */ | ||
577 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 | 42 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 |
578 | #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 | 43 | #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 |
579 | #define OMAP4430_CLKSEL_DIV_MASK (1 << 24) | ||
580 | |||
581 | /* Used by CM_MPU_MPU_CLKCTRL */ | ||
582 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 | ||
583 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1 | ||
584 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) | ||
585 | |||
586 | /* Used by CM_CAM_FDIF_CLKCTRL */ | ||
587 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 | 44 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 |
588 | #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 | 45 | #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 |
589 | #define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) | ||
590 | |||
591 | /* Used by CM_L4PER_MCBSP4_CLKCTRL */ | ||
592 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 | 46 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 |
593 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 | 47 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 |
594 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) | ||
595 | |||
596 | /* | ||
597 | * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, | ||
598 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | ||
599 | * CM1_ABE_MCBSP3_CLKCTRL | ||
600 | */ | ||
601 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 | ||
602 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2 | ||
603 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) | ||
604 | |||
605 | /* Used by CM_CLKSEL_CORE */ | ||
606 | #define OMAP4430_CLKSEL_L3_SHIFT 4 | 48 | #define OMAP4430_CLKSEL_L3_SHIFT 4 |
607 | #define OMAP4430_CLKSEL_L3_WIDTH 0x1 | 49 | #define OMAP4430_CLKSEL_L3_WIDTH 0x1 |
608 | #define OMAP4430_CLKSEL_L3_MASK (1 << 4) | ||
609 | |||
610 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
611 | #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 | ||
612 | #define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1 | ||
613 | #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) | ||
614 | |||
615 | /* Used by CM_CLKSEL_CORE */ | ||
616 | #define OMAP4430_CLKSEL_L4_SHIFT 8 | 50 | #define OMAP4430_CLKSEL_L4_SHIFT 8 |
617 | #define OMAP4430_CLKSEL_L4_WIDTH 0x1 | 51 | #define OMAP4430_CLKSEL_L4_WIDTH 0x1 |
618 | #define OMAP4430_CLKSEL_L4_MASK (1 << 8) | ||
619 | |||
620 | /* Used by CM_CLKSEL_ABE */ | ||
621 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 | 52 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 |
622 | #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 | 53 | #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 |
623 | #define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) | ||
624 | |||
625 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
626 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 | 54 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 |
627 | #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 | 55 | #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 |
628 | #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) | ||
629 | |||
630 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
631 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 | ||
632 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3 | ||
633 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) | 56 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) |
634 | |||
635 | /* Used by CM_GFX_GFX_CLKCTRL */ | ||
636 | #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 | ||
637 | #define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1 | ||
638 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) | 57 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) |
639 | |||
640 | /* | ||
641 | * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, | ||
642 | * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL | ||
643 | */ | ||
644 | #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 | ||
645 | #define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2 | ||
646 | #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) | 58 | #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) |
647 | |||
648 | /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ | ||
649 | #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 | ||
650 | #define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1 | ||
651 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) | 59 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) |
652 | |||
653 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
654 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 | 60 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 |
655 | #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 | 61 | #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 |
656 | #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) | ||
657 | |||
658 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
659 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 | 62 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 |
660 | #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 | 63 | #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 |
661 | #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) | ||
662 | |||
663 | /* | ||
664 | * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, | ||
665 | * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, | ||
666 | * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, | ||
667 | * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, | ||
668 | * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, | ||
669 | * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL, | ||
670 | * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL | ||
671 | */ | ||
672 | #define OMAP4430_CLKTRCTRL_SHIFT 0 | 64 | #define OMAP4430_CLKTRCTRL_SHIFT 0 |
673 | #define OMAP4430_CLKTRCTRL_WIDTH 0x2 | ||
674 | #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) | 65 | #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) |
675 | |||
676 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | ||
677 | #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 | ||
678 | #define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7 | ||
679 | #define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
680 | |||
681 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | ||
682 | #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 | ||
683 | #define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb | ||
684 | #define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
685 | |||
686 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
687 | #define OMAP4430_CUSTOM_SHIFT 6 | ||
688 | #define OMAP4430_CUSTOM_WIDTH 0x2 | ||
689 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) | ||
690 | |||
691 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
692 | #define OMAP4430_D2D_DYNDEP_SHIFT 18 | ||
693 | #define OMAP4430_D2D_DYNDEP_WIDTH 0x1 | ||
694 | #define OMAP4430_D2D_DYNDEP_MASK (1 << 18) | ||
695 | |||
696 | /* Used by CM_MPU_STATICDEP */ | ||
697 | #define OMAP4430_D2D_STATDEP_SHIFT 18 | ||
698 | #define OMAP4430_D2D_STATDEP_WIDTH 0x1 | ||
699 | #define OMAP4430_D2D_STATDEP_MASK (1 << 18) | ||
700 | |||
701 | /* Used by CM_CLKSEL_DPLL_MPU */ | ||
702 | #define OMAP4460_DCC_COUNT_MAX_SHIFT 24 | ||
703 | #define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8 | ||
704 | #define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) | ||
705 | |||
706 | /* Used by CM_CLKSEL_DPLL_MPU */ | ||
707 | #define OMAP4460_DCC_EN_SHIFT 22 | ||
708 | #define OMAP4460_DCC_EN_MASK (1 << 22) | ||
709 | |||
710 | /* | ||
711 | * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, | ||
712 | * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, | ||
713 | * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER, | ||
714 | * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB | ||
715 | */ | ||
716 | #define OMAP4430_DELTAMSTEP_SHIFT 0 | ||
717 | #define OMAP4430_DELTAMSTEP_WIDTH 0x14 | ||
718 | #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) | ||
719 | |||
720 | /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ | ||
721 | #define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 | ||
722 | #define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15 | ||
723 | #define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) | ||
724 | |||
725 | /* Used by CM_DLL_CTRL */ | ||
726 | #define OMAP4430_DLL_OVERRIDE_SHIFT 0 | ||
727 | #define OMAP4430_DLL_OVERRIDE_WIDTH 0x1 | ||
728 | #define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) | ||
729 | |||
730 | /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
731 | #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 | ||
732 | #define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1 | ||
733 | #define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) | ||
734 | |||
735 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
736 | #define OMAP4430_DLL_RESET_SHIFT 3 | ||
737 | #define OMAP4430_DLL_RESET_WIDTH 0x1 | ||
738 | #define OMAP4430_DLL_RESET_MASK (1 << 3) | ||
739 | |||
740 | /* | ||
741 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, | ||
742 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | ||
743 | * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB | ||
744 | */ | ||
745 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 | 66 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 |
746 | #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 | 67 | #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 |
747 | #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) | ||
748 | |||
749 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | ||
750 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 | ||
751 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1 | ||
752 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) | ||
753 | |||
754 | /* Used by CM_CLKSEL_DPLL_CORE */ | ||
755 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 | ||
756 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 | ||
757 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) | ||
758 | |||
759 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ | ||
760 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 | ||
761 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5 | ||
762 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) | 68 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) |
763 | |||
764 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ | ||
765 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 | ||
766 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1 | ||
767 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) | ||
768 | |||
769 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ | ||
770 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 | 69 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 |
771 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1 | ||
772 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) | ||
773 | |||
774 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ | ||
775 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 | ||
776 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1 | ||
777 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) | 70 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) |
778 | |||
779 | /* | ||
780 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
781 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO | ||
782 | */ | ||
783 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 | 71 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 |
784 | #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 | 72 | #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 |
785 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | 73 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
786 | |||
787 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ | ||
788 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 | ||
789 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7 | ||
790 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) | 74 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) |
791 | |||
792 | /* | ||
793 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
794 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO | ||
795 | */ | ||
796 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 | ||
797 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1 | ||
798 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) | ||
799 | |||
800 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ | ||
801 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 | ||
802 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1 | ||
803 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) | ||
804 | |||
805 | /* | ||
806 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
807 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB | ||
808 | */ | ||
809 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 | ||
810 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1 | ||
811 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | 75 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) |
812 | |||
813 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
814 | #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 | ||
815 | #define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3 | ||
816 | #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) | ||
817 | |||
818 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
819 | #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 | ||
820 | #define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5 | ||
821 | #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) | ||
822 | |||
823 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
824 | #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 | ||
825 | #define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5 | ||
826 | #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) | ||
827 | |||
828 | /* | ||
829 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, | ||
830 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | ||
831 | * CM_CLKSEL_DPLL_UNIPRO | ||
832 | */ | ||
833 | #define OMAP4430_DPLL_DIV_SHIFT 0 | ||
834 | #define OMAP4430_DPLL_DIV_WIDTH 0x7 | ||
835 | #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) | 76 | #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) |
836 | |||
837 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ | ||
838 | #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 | ||
839 | #define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8 | ||
840 | #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) | 77 | #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) |
841 | |||
842 | /* | ||
843 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
844 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
845 | */ | ||
846 | #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 | ||
847 | #define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1 | ||
848 | #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | ||
849 | |||
850 | /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ | ||
851 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 | ||
852 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1 | ||
853 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) | ||
854 | |||
855 | /* | ||
856 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
857 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
858 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | ||
859 | */ | ||
860 | #define OMAP4430_DPLL_EN_SHIFT 0 | ||
861 | #define OMAP4430_DPLL_EN_WIDTH 0x3 | ||
862 | #define OMAP4430_DPLL_EN_MASK (0x7 << 0) | 78 | #define OMAP4430_DPLL_EN_MASK (0x7 << 0) |
863 | |||
864 | /* | ||
865 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
866 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
867 | * CM_CLKMODE_DPLL_UNIPRO | ||
868 | */ | ||
869 | #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 | ||
870 | #define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1 | ||
871 | #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) | 79 | #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) |
872 | |||
873 | /* | ||
874 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, | ||
875 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | ||
876 | * CM_CLKSEL_DPLL_UNIPRO | ||
877 | */ | ||
878 | #define OMAP4430_DPLL_MULT_SHIFT 8 | ||
879 | #define OMAP4430_DPLL_MULT_WIDTH 0xb | ||
880 | #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) | 80 | #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) |
881 | |||
882 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ | ||
883 | #define OMAP4430_DPLL_MULT_USB_SHIFT 8 | ||
884 | #define OMAP4430_DPLL_MULT_USB_WIDTH 0xc | ||
885 | #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) | 81 | #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) |
886 | |||
887 | /* | ||
888 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
889 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
890 | * CM_CLKMODE_DPLL_UNIPRO | ||
891 | */ | ||
892 | #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 | ||
893 | #define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1 | ||
894 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) | 82 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) |
895 | |||
896 | /* Used by CM_CLKSEL_DPLL_USB */ | ||
897 | #define OMAP4430_DPLL_SD_DIV_SHIFT 24 | ||
898 | #define OMAP4430_DPLL_SD_DIV_WIDTH 0x8 | ||
899 | #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) | 83 | #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) |
900 | |||
901 | /* | ||
902 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
903 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
904 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | ||
905 | */ | ||
906 | #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 | ||
907 | #define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1 | ||
908 | #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) | ||
909 | |||
910 | /* | ||
911 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
912 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
913 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | ||
914 | */ | ||
915 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 | ||
916 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 | ||
917 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) | ||
918 | |||
919 | /* | ||
920 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
921 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
922 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | ||
923 | */ | ||
924 | #define OMAP4430_DPLL_SSC_EN_SHIFT 12 | ||
925 | #define OMAP4430_DPLL_SSC_EN_WIDTH 0x1 | ||
926 | #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) | ||
927 | |||
928 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
929 | #define OMAP4430_DSS_DYNDEP_SHIFT 8 | ||
930 | #define OMAP4430_DSS_DYNDEP_WIDTH 0x1 | ||
931 | #define OMAP4430_DSS_DYNDEP_MASK (1 << 8) | ||
932 | |||
933 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ | ||
934 | #define OMAP4430_DSS_STATDEP_SHIFT 8 | 84 | #define OMAP4430_DSS_STATDEP_SHIFT 8 |
935 | #define OMAP4430_DSS_STATDEP_WIDTH 0x1 | ||
936 | #define OMAP4430_DSS_STATDEP_MASK (1 << 8) | ||
937 | |||
938 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
939 | #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 | ||
940 | #define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1 | ||
941 | #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) | ||
942 | |||
943 | /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ | ||
944 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 | 85 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 |
945 | #define OMAP4430_DUCATI_STATDEP_WIDTH 0x1 | ||
946 | #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) | ||
947 | |||
948 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
949 | #define OMAP4430_FREQ_UPDATE_SHIFT 0 | ||
950 | #define OMAP4430_FREQ_UPDATE_WIDTH 0x1 | ||
951 | #define OMAP4430_FREQ_UPDATE_MASK (1 << 0) | ||
952 | |||
953 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
954 | #define OMAP4430_FUNC_SHIFT 16 | ||
955 | #define OMAP4430_FUNC_WIDTH 0xc | ||
956 | #define OMAP4430_FUNC_MASK (0xfff << 16) | ||
957 | |||
958 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
959 | #define OMAP4430_GFX_DYNDEP_SHIFT 10 | ||
960 | #define OMAP4430_GFX_DYNDEP_WIDTH 0x1 | ||
961 | #define OMAP4430_GFX_DYNDEP_MASK (1 << 10) | ||
962 | |||
963 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
964 | #define OMAP4430_GFX_STATDEP_SHIFT 10 | 86 | #define OMAP4430_GFX_STATDEP_SHIFT 10 |
965 | #define OMAP4430_GFX_STATDEP_WIDTH 0x1 | ||
966 | #define OMAP4430_GFX_STATDEP_MASK (1 << 10) | ||
967 | |||
968 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
969 | #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 | ||
970 | #define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1 | ||
971 | #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) | ||
972 | |||
973 | /* | ||
974 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
975 | * CM_DIV_M4_DPLL_PER | ||
976 | */ | ||
977 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 | ||
978 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5 | ||
979 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) | 87 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) |
980 | |||
981 | /* | ||
982 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
983 | * CM_DIV_M4_DPLL_PER | ||
984 | */ | ||
985 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 | ||
986 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1 | ||
987 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) | ||
988 | |||
989 | /* | ||
990 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
991 | * CM_DIV_M4_DPLL_PER | ||
992 | */ | ||
993 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 | ||
994 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1 | ||
995 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) | ||
996 | |||
997 | /* | ||
998 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
999 | * CM_DIV_M4_DPLL_PER | ||
1000 | */ | ||
1001 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 | ||
1002 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1 | ||
1003 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) | ||
1004 | |||
1005 | /* | ||
1006 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
1007 | * CM_DIV_M5_DPLL_PER | ||
1008 | */ | ||
1009 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 | ||
1010 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5 | ||
1011 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) | 88 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) |
1012 | |||
1013 | /* | ||
1014 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
1015 | * CM_DIV_M5_DPLL_PER | ||
1016 | */ | ||
1017 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 | ||
1018 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1 | ||
1019 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) | ||
1020 | |||
1021 | /* | ||
1022 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
1023 | * CM_DIV_M5_DPLL_PER | ||
1024 | */ | ||
1025 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 | ||
1026 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1 | ||
1027 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) | ||
1028 | |||
1029 | /* | ||
1030 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
1031 | * CM_DIV_M5_DPLL_PER | ||
1032 | */ | ||
1033 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 | ||
1034 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1 | ||
1035 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) | ||
1036 | |||
1037 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
1038 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 | ||
1039 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5 | ||
1040 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) | 89 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) |
1041 | |||
1042 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
1043 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 | ||
1044 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1 | ||
1045 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) | ||
1046 | |||
1047 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
1048 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 | ||
1049 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1 | ||
1050 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) | ||
1051 | |||
1052 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
1053 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 | ||
1054 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1 | ||
1055 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) | ||
1056 | |||
1057 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
1058 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 | ||
1059 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5 | ||
1060 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) | 90 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) |
1061 | |||
1062 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
1063 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 | ||
1064 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1 | ||
1065 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) | ||
1066 | |||
1067 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
1068 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 | ||
1069 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1 | ||
1070 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) | ||
1071 | |||
1072 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
1073 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 | ||
1074 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1 | ||
1075 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) | ||
1076 | |||
1077 | /* | ||
1078 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, | ||
1079 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | ||
1080 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, | ||
1081 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, | ||
1082 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, | ||
1083 | * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | ||
1084 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, | ||
1085 | * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, | ||
1086 | * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | ||
1087 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, | ||
1088 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | ||
1089 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | ||
1090 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | ||
1091 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, | ||
1092 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
1093 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, | ||
1094 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, | ||
1095 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | ||
1096 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, | ||
1097 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, | ||
1098 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, | ||
1099 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, | ||
1100 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, | ||
1101 | * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, | ||
1102 | * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, | ||
1103 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | ||
1104 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, | ||
1105 | * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, | ||
1106 | * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, | ||
1107 | * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, | ||
1108 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, | ||
1109 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, | ||
1110 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, | ||
1111 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, | ||
1112 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, | ||
1113 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, | ||
1114 | * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, | ||
1115 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL | ||
1116 | */ | ||
1117 | #define OMAP4430_IDLEST_SHIFT 16 | 91 | #define OMAP4430_IDLEST_SHIFT 16 |
1118 | #define OMAP4430_IDLEST_WIDTH 0x2 | ||
1119 | #define OMAP4430_IDLEST_MASK (0x3 << 16) | 92 | #define OMAP4430_IDLEST_MASK (0x3 << 16) |
1120 | |||
1121 | /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
1122 | #define OMAP4430_ISS_DYNDEP_SHIFT 9 | ||
1123 | #define OMAP4430_ISS_DYNDEP_WIDTH 0x1 | ||
1124 | #define OMAP4430_ISS_DYNDEP_MASK (1 << 9) | ||
1125 | |||
1126 | /* | ||
1127 | * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, | ||
1128 | * CM_TESLA_STATICDEP | ||
1129 | */ | ||
1130 | #define OMAP4430_ISS_STATDEP_SHIFT 9 | ||
1131 | #define OMAP4430_ISS_STATDEP_WIDTH 0x1 | ||
1132 | #define OMAP4430_ISS_STATDEP_MASK (1 << 9) | ||
1133 | |||
1134 | /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ | ||
1135 | #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 | ||
1136 | #define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1 | ||
1137 | #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) | ||
1138 | |||
1139 | /* | ||
1140 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, | ||
1141 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, | ||
1142 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
1143 | */ | ||
1144 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 | 93 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 |
1145 | #define OMAP4430_IVAHD_STATDEP_WIDTH 0x1 | ||
1146 | #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) | ||
1147 | |||
1148 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
1149 | #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 | ||
1150 | #define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1 | ||
1151 | #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) | ||
1152 | |||
1153 | /* | ||
1154 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, | ||
1155 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
1156 | */ | ||
1157 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 | 94 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 |
1158 | #define OMAP4430_L3INIT_STATDEP_WIDTH 0x1 | ||
1159 | #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) | ||
1160 | |||
1161 | /* | ||
1162 | * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, | ||
1163 | * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | ||
1164 | */ | ||
1165 | #define OMAP4430_L3_1_DYNDEP_SHIFT 5 | ||
1166 | #define OMAP4430_L3_1_DYNDEP_WIDTH 0x1 | ||
1167 | #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) | ||
1168 | |||
1169 | /* | ||
1170 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, | ||
1171 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | ||
1172 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, | ||
1173 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
1174 | */ | ||
1175 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 | 95 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 |
1176 | #define OMAP4430_L3_1_STATDEP_WIDTH 0x1 | ||
1177 | #define OMAP4430_L3_1_STATDEP_MASK (1 << 5) | ||
1178 | |||
1179 | /* | ||
1180 | * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, | ||
1181 | * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP, | ||
1182 | * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
1183 | * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP | ||
1184 | */ | ||
1185 | #define OMAP4430_L3_2_DYNDEP_SHIFT 6 | ||
1186 | #define OMAP4430_L3_2_DYNDEP_WIDTH 0x1 | ||
1187 | #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) | ||
1188 | |||
1189 | /* | ||
1190 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, | ||
1191 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | ||
1192 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, | ||
1193 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
1194 | */ | ||
1195 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 | 96 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 |
1196 | #define OMAP4430_L3_2_STATDEP_WIDTH 0x1 | ||
1197 | #define OMAP4430_L3_2_STATDEP_MASK (1 << 6) | ||
1198 | |||
1199 | /* Used by CM_L3_1_DYNAMICDEP */ | ||
1200 | #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 | ||
1201 | #define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1 | ||
1202 | #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) | ||
1203 | |||
1204 | /* | ||
1205 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, | ||
1206 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
1207 | */ | ||
1208 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 | 97 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 |
1209 | #define OMAP4430_L4CFG_STATDEP_WIDTH 0x1 | ||
1210 | #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) | ||
1211 | |||
1212 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
1213 | #define OMAP4430_L4PER_DYNDEP_SHIFT 13 | ||
1214 | #define OMAP4430_L4PER_DYNDEP_WIDTH 0x1 | ||
1215 | #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) | ||
1216 | |||
1217 | /* | ||
1218 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, | ||
1219 | * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
1220 | */ | ||
1221 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 | 98 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 |
1222 | #define OMAP4430_L4PER_STATDEP_WIDTH 0x1 | ||
1223 | #define OMAP4430_L4PER_STATDEP_MASK (1 << 13) | ||
1224 | |||
1225 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
1226 | #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 | ||
1227 | #define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1 | ||
1228 | #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) | ||
1229 | |||
1230 | /* | ||
1231 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, | ||
1232 | * CM_SDMA_STATICDEP | ||
1233 | */ | ||
1234 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 | 99 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 |
1235 | #define OMAP4430_L4SEC_STATDEP_WIDTH 0x1 | ||
1236 | #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) | ||
1237 | |||
1238 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1239 | #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 | ||
1240 | #define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1 | ||
1241 | #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) | ||
1242 | |||
1243 | /* | ||
1244 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, | ||
1245 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
1246 | */ | ||
1247 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 | 100 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 |
1248 | #define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1 | ||
1249 | #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) | ||
1250 | |||
1251 | /* | ||
1252 | * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
1253 | * CM_MPU_DYNAMICDEP | ||
1254 | */ | ||
1255 | #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 | ||
1256 | #define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1 | ||
1257 | #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) | ||
1258 | |||
1259 | /* | ||
1260 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, | ||
1261 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | ||
1262 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, | ||
1263 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
1264 | */ | ||
1265 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 | 101 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 |
1266 | #define OMAP4430_MEMIF_STATDEP_WIDTH 0x1 | ||
1267 | #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) | ||
1268 | |||
1269 | /* | ||
1270 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, | ||
1271 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, | ||
1272 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, | ||
1273 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB | ||
1274 | */ | ||
1275 | #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 | ||
1276 | #define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3 | ||
1277 | #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) | ||
1278 | |||
1279 | /* | ||
1280 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, | ||
1281 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, | ||
1282 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, | ||
1283 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB | ||
1284 | */ | ||
1285 | #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 | ||
1286 | #define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7 | ||
1287 | #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) | ||
1288 | |||
1289 | /* | ||
1290 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, | ||
1291 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | ||
1292 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, | ||
1293 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, | ||
1294 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, | ||
1295 | * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | ||
1296 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, | ||
1297 | * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, | ||
1298 | * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | ||
1299 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, | ||
1300 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | ||
1301 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | ||
1302 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | ||
1303 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, | ||
1304 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
1305 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, | ||
1306 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, | ||
1307 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | ||
1308 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, | ||
1309 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, | ||
1310 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, | ||
1311 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, | ||
1312 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, | ||
1313 | * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, | ||
1314 | * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, | ||
1315 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | ||
1316 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, | ||
1317 | * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, | ||
1318 | * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, | ||
1319 | * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, | ||
1320 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, | ||
1321 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, | ||
1322 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, | ||
1323 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, | ||
1324 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, | ||
1325 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, | ||
1326 | * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, | ||
1327 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL | ||
1328 | */ | ||
1329 | #define OMAP4430_MODULEMODE_SHIFT 0 | 102 | #define OMAP4430_MODULEMODE_SHIFT 0 |
1330 | #define OMAP4430_MODULEMODE_WIDTH 0x2 | ||
1331 | #define OMAP4430_MODULEMODE_MASK (0x3 << 0) | 103 | #define OMAP4430_MODULEMODE_MASK (0x3 << 0) |
1332 | |||
1333 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1334 | #define OMAP4460_MPU_DYNDEP_SHIFT 19 | ||
1335 | #define OMAP4460_MPU_DYNDEP_WIDTH 0x1 | ||
1336 | #define OMAP4460_MPU_DYNDEP_MASK (1 << 19) | ||
1337 | |||
1338 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1339 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 | 104 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
1340 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 | ||
1341 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) | ||
1342 | |||
1343 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ | ||
1344 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 | 105 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 |
1345 | #define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1 | ||
1346 | #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) | ||
1347 | |||
1348 | /* Used by CM_ALWON_USBPHY_CLKCTRL */ | ||
1349 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 | 106 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 |
1350 | #define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1 | ||
1351 | #define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) | ||
1352 | |||
1353 | /* Used by CM_CAM_ISS_CLKCTRL */ | ||
1354 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 | 107 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 |
1355 | #define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1 | ||
1356 | #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) | ||
1357 | |||
1358 | /* | ||
1359 | * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, | ||
1360 | * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, | ||
1361 | * CM_WKUP_GPIO1_CLKCTRL | ||
1362 | */ | ||
1363 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 | 108 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 |
1364 | #define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1 | ||
1365 | #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) | ||
1366 | |||
1367 | /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ | ||
1368 | #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 | ||
1369 | #define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1 | ||
1370 | #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) | ||
1371 | |||
1372 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1373 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 | 109 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 |
1374 | #define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1 | ||
1375 | #define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) | ||
1376 | |||
1377 | /* Used by CM_WKUP_USIM_CLKCTRL */ | ||
1378 | #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 | 110 | #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 |
1379 | #define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1 | ||
1380 | #define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) | ||
1381 | |||
1382 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
1383 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 | 111 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 |
1384 | #define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1 | ||
1385 | #define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) | ||
1386 | |||
1387 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
1388 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 | 112 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 |
1389 | #define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1 | ||
1390 | #define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) | ||
1391 | |||
1392 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
1393 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 | 113 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 |
1394 | #define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1 | ||
1395 | #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) | ||
1396 | |||
1397 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
1398 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 | 114 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 |
1399 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1 | ||
1400 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) | ||
1401 | |||
1402 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
1403 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 | 115 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
1404 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 | ||
1405 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) | ||
1406 | |||
1407 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
1408 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 | 116 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
1409 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 | ||
1410 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) | ||
1411 | |||
1412 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
1413 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 | 117 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
1414 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 | ||
1415 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) | ||
1416 | |||
1417 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
1418 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 | 118 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
1419 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 | ||
1420 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) | ||
1421 | |||
1422 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
1423 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 | 119 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 |
1424 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1 | ||
1425 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) | ||
1426 | |||
1427 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
1428 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 | 120 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 |
1429 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1 | ||
1430 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) | ||
1431 | |||
1432 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ | ||
1433 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 | 121 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 |
1434 | #define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1 | ||
1435 | #define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) | ||
1436 | |||
1437 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
1438 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 | 122 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 |
1439 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 | ||
1440 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) | ||
1441 | |||
1442 | /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
1443 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 | 123 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 |
1444 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1 | ||
1445 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) | ||
1446 | |||
1447 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1448 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 | 124 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 |
1449 | #define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1 | ||
1450 | #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) | ||
1451 | |||
1452 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ | ||
1453 | #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 | 125 | #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 |
1454 | #define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1 | ||
1455 | #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) | ||
1456 | |||
1457 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1458 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 | 126 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 |
1459 | #define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1 | ||
1460 | #define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) | ||
1461 | |||
1462 | /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ | ||
1463 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 | ||
1464 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1 | ||
1465 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) | ||
1466 | |||
1467 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ | ||
1468 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 | 127 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
1469 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 | ||
1470 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) | ||
1471 | |||
1472 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ | ||
1473 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 | 128 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
1474 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 | ||
1475 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) | ||
1476 | |||
1477 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ | ||
1478 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 | 129 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
1479 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 | ||
1480 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) | ||
1481 | |||
1482 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
1483 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 | 130 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
1484 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 | ||
1485 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) | ||
1486 | |||
1487 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
1488 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 | 131 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
1489 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 | ||
1490 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) | ||
1491 | |||
1492 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
1493 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 | 132 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
1494 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 | ||
1495 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) | ||
1496 | |||
1497 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | ||
1498 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 | 133 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 |
1499 | #define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1 | ||
1500 | #define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) | ||
1501 | |||
1502 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | ||
1503 | #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 | ||
1504 | #define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1 | ||
1505 | #define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) | ||
1506 | |||
1507 | /* Used by CM_CLKSEL_ABE */ | ||
1508 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 | 134 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 |
1509 | #define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1 | ||
1510 | #define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) | ||
1511 | |||
1512 | /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ | ||
1513 | #define OMAP4430_PERF_CURRENT_SHIFT 0 | ||
1514 | #define OMAP4430_PERF_CURRENT_WIDTH 0x8 | ||
1515 | #define OMAP4430_PERF_CURRENT_MASK (0xff << 0) | ||
1516 | |||
1517 | /* | ||
1518 | * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, | ||
1519 | * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, | ||
1520 | * CM_IVA_DVFS_PERF_TESLA | ||
1521 | */ | ||
1522 | #define OMAP4430_PERF_REQ_SHIFT 0 | ||
1523 | #define OMAP4430_PERF_REQ_WIDTH 0x8 | ||
1524 | #define OMAP4430_PERF_REQ_MASK (0xff << 0) | ||
1525 | |||
1526 | /* Used by CM_RESTORE_ST */ | ||
1527 | #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 | ||
1528 | #define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1 | ||
1529 | #define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) | ||
1530 | |||
1531 | /* Used by CM_RESTORE_ST */ | ||
1532 | #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 | ||
1533 | #define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1 | ||
1534 | #define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) | ||
1535 | |||
1536 | /* Used by CM_RESTORE_ST */ | ||
1537 | #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 | ||
1538 | #define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1 | ||
1539 | #define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) | ||
1540 | |||
1541 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
1542 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 | 135 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 |
1543 | #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 | 136 | #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 |
1544 | #define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) | ||
1545 | |||
1546 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
1547 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 | 137 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 |
1548 | #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 | 138 | #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 |
1549 | #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) | ||
1550 | |||
1551 | /* Used by CM_DYN_DEP_PRESCAL */ | ||
1552 | #define OMAP4430_PRESCAL_SHIFT 0 | ||
1553 | #define OMAP4430_PRESCAL_WIDTH 0x6 | ||
1554 | #define OMAP4430_PRESCAL_MASK (0x3f << 0) | ||
1555 | |||
1556 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
1557 | #define OMAP4430_R_RTL_SHIFT 11 | ||
1558 | #define OMAP4430_R_RTL_WIDTH 0x5 | ||
1559 | #define OMAP4430_R_RTL_MASK (0x1f << 11) | ||
1560 | |||
1561 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ | ||
1562 | #define OMAP4430_SAR_MODE_SHIFT 4 | ||
1563 | #define OMAP4430_SAR_MODE_WIDTH 0x1 | ||
1564 | #define OMAP4430_SAR_MODE_MASK (1 << 4) | ||
1565 | |||
1566 | /* Used by CM_SCALE_FCLK */ | ||
1567 | #define OMAP4430_SCALE_FCLK_SHIFT 0 | 139 | #define OMAP4430_SCALE_FCLK_SHIFT 0 |
1568 | #define OMAP4430_SCALE_FCLK_WIDTH 0x1 | 140 | #define OMAP4430_SCALE_FCLK_WIDTH 0x1 |
1569 | #define OMAP4430_SCALE_FCLK_MASK (1 << 0) | ||
1570 | |||
1571 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
1572 | #define OMAP4430_SCHEME_SHIFT 30 | ||
1573 | #define OMAP4430_SCHEME_WIDTH 0x2 | ||
1574 | #define OMAP4430_SCHEME_MASK (0x3 << 30) | ||
1575 | |||
1576 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1577 | #define OMAP4430_SDMA_DYNDEP_SHIFT 11 | ||
1578 | #define OMAP4430_SDMA_DYNDEP_WIDTH 0x1 | ||
1579 | #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) | ||
1580 | |||
1581 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
1582 | #define OMAP4430_SDMA_STATDEP_SHIFT 11 | ||
1583 | #define OMAP4430_SDMA_STATDEP_WIDTH 0x1 | ||
1584 | #define OMAP4430_SDMA_STATDEP_MASK (1 << 11) | ||
1585 | |||
1586 | /* Used by CM_CLKSEL_ABE */ | ||
1587 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 | 141 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 |
1588 | #define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1 | ||
1589 | #define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) | ||
1590 | |||
1591 | /* | ||
1592 | * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, | ||
1593 | * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | ||
1594 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, | ||
1595 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, | ||
1596 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | ||
1597 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, | ||
1598 | * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL | ||
1599 | */ | ||
1600 | #define OMAP4430_STBYST_SHIFT 18 | ||
1601 | #define OMAP4430_STBYST_WIDTH 0x1 | ||
1602 | #define OMAP4430_STBYST_MASK (1 << 18) | ||
1603 | |||
1604 | /* | ||
1605 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, | ||
1606 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, | ||
1607 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB | ||
1608 | */ | ||
1609 | #define OMAP4430_ST_DPLL_CLK_SHIFT 0 | ||
1610 | #define OMAP4430_ST_DPLL_CLK_WIDTH 0x1 | ||
1611 | #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) | 142 | #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) |
1612 | |||
1613 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | ||
1614 | #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 | ||
1615 | #define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1 | ||
1616 | #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) | ||
1617 | |||
1618 | /* | ||
1619 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
1620 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB | ||
1621 | */ | ||
1622 | #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 | ||
1623 | #define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1 | ||
1624 | #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) | ||
1625 | |||
1626 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ | ||
1627 | #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 | ||
1628 | #define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1 | ||
1629 | #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) | ||
1630 | |||
1631 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ | ||
1632 | #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 | ||
1633 | #define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1 | ||
1634 | #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) | ||
1635 | |||
1636 | /* | ||
1637 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
1638 | * CM_DIV_M4_DPLL_PER | ||
1639 | */ | ||
1640 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 | ||
1641 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1 | ||
1642 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) | ||
1643 | |||
1644 | /* | ||
1645 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
1646 | * CM_DIV_M5_DPLL_PER | ||
1647 | */ | ||
1648 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 | ||
1649 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1 | ||
1650 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) | ||
1651 | |||
1652 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
1653 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 | ||
1654 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1 | ||
1655 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) | ||
1656 | |||
1657 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
1658 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 | ||
1659 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1 | ||
1660 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) | ||
1661 | |||
1662 | /* | ||
1663 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, | ||
1664 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, | ||
1665 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB | ||
1666 | */ | ||
1667 | #define OMAP4430_ST_MN_BYPASS_SHIFT 8 | ||
1668 | #define OMAP4430_ST_MN_BYPASS_WIDTH 0x1 | ||
1669 | #define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) | ||
1670 | |||
1671 | /* Used by CM_SYS_CLKSEL */ | ||
1672 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 | 143 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 |
1673 | #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 | 144 | #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 |
1674 | #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) | ||
1675 | |||
1676 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1677 | #define OMAP4430_TESLA_DYNDEP_SHIFT 1 | ||
1678 | #define OMAP4430_TESLA_DYNDEP_WIDTH 0x1 | ||
1679 | #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) | ||
1680 | |||
1681 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
1682 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 | 145 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 |
1683 | #define OMAP4430_TESLA_STATDEP_WIDTH 0x1 | ||
1684 | #define OMAP4430_TESLA_STATDEP_MASK (1 << 1) | ||
1685 | |||
1686 | /* | ||
1687 | * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, | ||
1688 | * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
1689 | * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | ||
1690 | */ | ||
1691 | #define OMAP4430_WINDOWSIZE_SHIFT 24 | ||
1692 | #define OMAP4430_WINDOWSIZE_WIDTH 0x4 | ||
1693 | #define OMAP4430_WINDOWSIZE_MASK (0xf << 24) | ||
1694 | |||
1695 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
1696 | #define OMAP4430_X_MAJOR_SHIFT 8 | ||
1697 | #define OMAP4430_X_MAJOR_WIDTH 0x3 | ||
1698 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) | ||
1699 | |||
1700 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
1701 | #define OMAP4430_Y_MINOR_SHIFT 0 | ||
1702 | #define OMAP4430_Y_MINOR_WIDTH 0x6 | ||
1703 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) | ||
1704 | #endif | 146 | #endif |
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h index e83b8e352b6e..896ae9fc4cfb 100644 --- a/arch/arm/mach-omap2/cm-regbits-54xx.h +++ b/arch/arm/mach-omap2/cm-regbits-54xx.h | |||
@@ -21,1717 +21,84 @@ | |||
21 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H | 21 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H |
22 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H | 22 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H |
23 | 23 | ||
24 | /* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */ | ||
25 | #define OMAP54XX_ABE_DYNDEP_SHIFT 3 | ||
26 | #define OMAP54XX_ABE_DYNDEP_WIDTH 0x1 | ||
27 | #define OMAP54XX_ABE_DYNDEP_MASK (1 << 3) | ||
28 | |||
29 | /* | ||
30 | * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, | ||
31 | * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP | ||
32 | */ | ||
33 | #define OMAP54XX_ABE_STATDEP_SHIFT 3 | 24 | #define OMAP54XX_ABE_STATDEP_SHIFT 3 |
34 | #define OMAP54XX_ABE_STATDEP_WIDTH 0x1 | ||
35 | #define OMAP54XX_ABE_STATDEP_MASK (1 << 3) | ||
36 | |||
37 | /* | ||
38 | * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA, | ||
39 | * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1, | ||
40 | * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB | ||
41 | */ | ||
42 | #define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0 | ||
43 | #define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3 | ||
44 | #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) | 25 | #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) |
45 | |||
46 | /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
47 | #define OMAP54XX_C2C_DYNDEP_SHIFT 18 | ||
48 | #define OMAP54XX_C2C_DYNDEP_WIDTH 0x1 | ||
49 | #define OMAP54XX_C2C_DYNDEP_MASK (1 << 18) | ||
50 | |||
51 | /* Used by CM_MPU_STATICDEP */ | ||
52 | #define OMAP54XX_C2C_STATDEP_SHIFT 18 | ||
53 | #define OMAP54XX_C2C_STATDEP_WIDTH 0x1 | ||
54 | #define OMAP54XX_C2C_STATDEP_MASK (1 << 18) | ||
55 | |||
56 | /* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
57 | #define OMAP54XX_CAM_DYNDEP_SHIFT 9 | ||
58 | #define OMAP54XX_CAM_DYNDEP_WIDTH 0x1 | ||
59 | #define OMAP54XX_CAM_DYNDEP_MASK (1 << 9) | ||
60 | |||
61 | /* | ||
62 | * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, | ||
63 | * CM_MPU_STATICDEP | ||
64 | */ | ||
65 | #define OMAP54XX_CAM_STATDEP_SHIFT 9 | ||
66 | #define OMAP54XX_CAM_STATDEP_WIDTH 0x1 | ||
67 | #define OMAP54XX_CAM_STATDEP_MASK (1 << 9) | ||
68 | |||
69 | /* Used by CM_ABE_CLKSTCTRL */ | ||
70 | #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 | ||
71 | #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 | ||
72 | #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) | ||
73 | |||
74 | /* Used by CM_ABE_CLKSTCTRL */ | ||
75 | #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12 | ||
76 | #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1 | ||
77 | #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12) | ||
78 | |||
79 | /* Used by CM_ABE_CLKSTCTRL */ | ||
80 | #define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9 | ||
81 | #define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1 | ||
82 | #define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9) | ||
83 | |||
84 | /* Used by CM_WKUPAON_CLKSTCTRL */ | ||
85 | #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 | ||
86 | #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 | ||
87 | #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) | ||
88 | |||
89 | /* Used by CM_ABE_CLKSTCTRL */ | ||
90 | #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11 | ||
91 | #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1 | ||
92 | #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11) | ||
93 | |||
94 | /* Used by CM_ABE_CLKSTCTRL */ | ||
95 | #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 | ||
96 | #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 | ||
97 | #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) | ||
98 | |||
99 | /* Used by CM_DSS_CLKSTCTRL */ | ||
100 | #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13 | ||
101 | #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1 | ||
102 | #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13) | ||
103 | |||
104 | /* Used by CM_C2C_CLKSTCTRL */ | ||
105 | #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9 | ||
106 | #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1 | ||
107 | #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9) | ||
108 | |||
109 | /* Used by CM_C2C_CLKSTCTRL */ | ||
110 | #define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10 | ||
111 | #define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1 | ||
112 | #define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10) | ||
113 | |||
114 | /* Used by CM_C2C_CLKSTCTRL */ | ||
115 | #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8 | ||
116 | #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1 | ||
117 | #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8) | ||
118 | |||
119 | /* Used by CM_CAM_CLKSTCTRL */ | ||
120 | #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11 | ||
121 | #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1 | ||
122 | #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11) | ||
123 | |||
124 | /* Used by CM_CAM_CLKSTCTRL */ | ||
125 | #define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8 | ||
126 | #define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1 | ||
127 | #define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8) | ||
128 | |||
129 | /* Used by CM_CAM_CLKSTCTRL */ | ||
130 | #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12 | ||
131 | #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1 | ||
132 | #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12) | ||
133 | |||
134 | /* Used by CM_COREAON_CLKSTCTRL */ | ||
135 | #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12 | ||
136 | #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1 | ||
137 | #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12) | ||
138 | |||
139 | /* Used by CM_COREAON_CLKSTCTRL */ | ||
140 | #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14 | ||
141 | #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1 | ||
142 | #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14) | ||
143 | |||
144 | /* Used by CM_COREAON_CLKSTCTRL */ | ||
145 | #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8 | ||
146 | #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1 | ||
147 | #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8) | ||
148 | |||
149 | /* Used by CM_CAM_CLKSTCTRL */ | ||
150 | #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9 | ||
151 | #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1 | ||
152 | #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9) | ||
153 | |||
154 | /* Used by CM_CUSTEFUSE_CLKSTCTRL */ | ||
155 | #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8 | ||
156 | #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1 | ||
157 | #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8) | ||
158 | |||
159 | /* Used by CM_CUSTEFUSE_CLKSTCTRL */ | ||
160 | #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9 | ||
161 | #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1 | ||
162 | #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9) | ||
163 | |||
164 | /* Used by CM_EMIF_CLKSTCTRL */ | ||
165 | #define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9 | ||
166 | #define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1 | ||
167 | #define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9) | ||
168 | |||
169 | /* Used by CM_DMA_CLKSTCTRL */ | ||
170 | #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8 | ||
171 | #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1 | ||
172 | #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8) | ||
173 | |||
174 | /* Used by CM_DSP_CLKSTCTRL */ | ||
175 | #define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8 | ||
176 | #define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1 | ||
177 | #define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8) | ||
178 | |||
179 | /* Used by CM_DSS_CLKSTCTRL */ | ||
180 | #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9 | ||
181 | #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1 | ||
182 | #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9) | ||
183 | |||
184 | /* Used by CM_DSS_CLKSTCTRL */ | ||
185 | #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8 | ||
186 | #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1 | ||
187 | #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8) | ||
188 | |||
189 | /* Used by CM_DSS_CLKSTCTRL */ | ||
190 | #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10 | ||
191 | #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1 | ||
192 | #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10) | ||
193 | |||
194 | /* Used by CM_EMIF_CLKSTCTRL */ | ||
195 | #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8 | ||
196 | #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1 | ||
197 | #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8) | ||
198 | |||
199 | /* Used by CM_EMIF_CLKSTCTRL */ | ||
200 | #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11 | ||
201 | #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1 | ||
202 | #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11) | ||
203 | |||
204 | /* Used by CM_EMIF_CLKSTCTRL */ | ||
205 | #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10 | ||
206 | #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1 | ||
207 | #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10) | ||
208 | |||
209 | /* Used by CM_EMU_CLKSTCTRL */ | ||
210 | #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8 | ||
211 | #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1 | ||
212 | #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8) | ||
213 | |||
214 | /* Used by CM_CAM_CLKSTCTRL */ | ||
215 | #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10 | ||
216 | #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1 | ||
217 | #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10) | ||
218 | |||
219 | /* Used by CM_ABE_CLKSTCTRL */ | ||
220 | #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 | ||
221 | #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 | ||
222 | #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) | ||
223 | |||
224 | /* Used by CM_GPU_CLKSTCTRL */ | ||
225 | #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9 | ||
226 | #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1 | ||
227 | #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9) | ||
228 | |||
229 | /* Used by CM_GPU_CLKSTCTRL */ | ||
230 | #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10 | ||
231 | #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1 | ||
232 | #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10) | ||
233 | |||
234 | /* Used by CM_GPU_CLKSTCTRL */ | ||
235 | #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8 | ||
236 | #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1 | ||
237 | #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8) | ||
238 | |||
239 | /* Used by CM_DSS_CLKSTCTRL */ | ||
240 | #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12 | ||
241 | #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1 | ||
242 | #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12) | ||
243 | |||
244 | /* Used by CM_DSS_CLKSTCTRL */ | ||
245 | #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11 | ||
246 | #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1 | ||
247 | #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11) | ||
248 | |||
249 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
250 | #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 | ||
251 | #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 | ||
252 | #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) | ||
253 | |||
254 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
255 | #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 | ||
256 | #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 | ||
257 | #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) | ||
258 | |||
259 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
260 | #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 | ||
261 | #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 | ||
262 | #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) | ||
263 | |||
264 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
265 | #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 | ||
266 | #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 | ||
267 | #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) | ||
268 | |||
269 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
270 | #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6 | ||
271 | #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1 | ||
272 | #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6) | ||
273 | |||
274 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
275 | #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7 | ||
276 | #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1 | ||
277 | #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7) | ||
278 | |||
279 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
280 | #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16 | ||
281 | #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1 | ||
282 | #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16) | ||
283 | |||
284 | /* Used by CM_IPU_CLKSTCTRL */ | ||
285 | #define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8 | ||
286 | #define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1 | ||
287 | #define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8) | ||
288 | |||
289 | /* Used by CM_IVA_CLKSTCTRL */ | ||
290 | #define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8 | ||
291 | #define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1 | ||
292 | #define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8) | ||
293 | |||
294 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
295 | #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12 | ||
296 | #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1 | ||
297 | #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12) | ||
298 | |||
299 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
300 | #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28 | ||
301 | #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1 | ||
302 | #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28) | ||
303 | |||
304 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
305 | #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29 | ||
306 | #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1 | ||
307 | #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29) | ||
308 | |||
309 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
310 | #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8 | ||
311 | #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1 | ||
312 | #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8) | ||
313 | |||
314 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
315 | #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9 | ||
316 | #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1 | ||
317 | #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9) | ||
318 | |||
319 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
320 | #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11 | ||
321 | #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1 | ||
322 | #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11) | ||
323 | |||
324 | /* Used by CM_L3INSTR_CLKSTCTRL */ | ||
325 | #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9 | ||
326 | #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1 | ||
327 | #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9) | ||
328 | |||
329 | /* Used by CM_L3INSTR_CLKSTCTRL */ | ||
330 | #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8 | ||
331 | #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1 | ||
332 | #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8) | ||
333 | |||
334 | /* Used by CM_L3INSTR_CLKSTCTRL */ | ||
335 | #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10 | ||
336 | #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1 | ||
337 | #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10) | ||
338 | |||
339 | /* Used by CM_L3MAIN1_CLKSTCTRL */ | ||
340 | #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8 | ||
341 | #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1 | ||
342 | #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8) | ||
343 | |||
344 | /* Used by CM_L3MAIN2_CLKSTCTRL */ | ||
345 | #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8 | ||
346 | #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1 | ||
347 | #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8) | ||
348 | |||
349 | /* Used by CM_L4CFG_CLKSTCTRL */ | ||
350 | #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8 | ||
351 | #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1 | ||
352 | #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8) | ||
353 | |||
354 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
355 | #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8 | ||
356 | #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1 | ||
357 | #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8) | ||
358 | |||
359 | /* Used by CM_L4SEC_CLKSTCTRL */ | ||
360 | #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8 | ||
361 | #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1 | ||
362 | #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8) | ||
363 | |||
364 | /* Used by CM_L4SEC_CLKSTCTRL */ | ||
365 | #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9 | ||
366 | #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1 | ||
367 | #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9) | ||
368 | |||
369 | /* Used by CM_MIPIEXT_CLKSTCTRL */ | ||
370 | #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8 | ||
371 | #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1 | ||
372 | #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8) | ||
373 | |||
374 | /* Used by CM_MIPIEXT_CLKSTCTRL */ | ||
375 | #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11 | ||
376 | #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1 | ||
377 | #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11) | ||
378 | |||
379 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
380 | #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2 | ||
381 | #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1 | ||
382 | #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2) | ||
383 | |||
384 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
385 | #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17 | ||
386 | #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1 | ||
387 | #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17) | ||
388 | |||
389 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
390 | #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18 | ||
391 | #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1 | ||
392 | #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18) | ||
393 | |||
394 | /* Used by CM_MPU_CLKSTCTRL */ | ||
395 | #define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8 | ||
396 | #define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1 | ||
397 | #define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8) | ||
398 | |||
399 | /* Used by CM_ABE_CLKSTCTRL */ | ||
400 | #define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14 | ||
401 | #define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1 | ||
402 | #define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14) | ||
403 | |||
404 | /* Used by CM_ABE_CLKSTCTRL */ | ||
405 | #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15 | ||
406 | #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1 | ||
407 | #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15) | ||
408 | |||
409 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
410 | #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3 | ||
411 | #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1 | ||
412 | #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3) | ||
413 | |||
414 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
415 | #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4 | ||
416 | #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1 | ||
417 | #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4) | ||
418 | |||
419 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
420 | #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15 | ||
421 | #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1 | ||
422 | #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15) | ||
423 | |||
424 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
425 | #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 | ||
426 | #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 | ||
427 | #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) | ||
428 | |||
429 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
430 | #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 | ||
431 | #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 | ||
432 | #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) | ||
433 | |||
434 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
435 | #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 | ||
436 | #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 | ||
437 | #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) | ||
438 | |||
439 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
440 | #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19 | ||
441 | #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1 | ||
442 | #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19) | ||
443 | |||
444 | /* Used by CM_COREAON_CLKSTCTRL */ | ||
445 | #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11 | ||
446 | #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1 | ||
447 | #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11) | ||
448 | |||
449 | /* Used by CM_COREAON_CLKSTCTRL */ | ||
450 | #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10 | ||
451 | #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1 | ||
452 | #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10) | ||
453 | |||
454 | /* Used by CM_COREAON_CLKSTCTRL */ | ||
455 | #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9 | ||
456 | #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1 | ||
457 | #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9) | ||
458 | |||
459 | /* Used by CM_WKUPAON_CLKSTCTRL */ | ||
460 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8 | ||
461 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1 | ||
462 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8) | ||
463 | |||
464 | /* Used by CM_WKUPAON_CLKSTCTRL */ | ||
465 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15 | ||
466 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1 | ||
467 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15) | ||
468 | |||
469 | /* Used by CM_WKUPAON_CLKSTCTRL */ | ||
470 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14 | ||
471 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1 | ||
472 | #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14) | ||
473 | |||
474 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
475 | #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9 | ||
476 | #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1 | ||
477 | #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9) | ||
478 | |||
479 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
480 | #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10 | ||
481 | #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1 | ||
482 | #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10) | ||
483 | |||
484 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
485 | #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11 | ||
486 | #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1 | ||
487 | #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11) | ||
488 | |||
489 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
490 | #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12 | ||
491 | #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1 | ||
492 | #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12) | ||
493 | |||
494 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
495 | #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13 | ||
496 | #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1 | ||
497 | #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13) | ||
498 | |||
499 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
500 | #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14 | ||
501 | #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1 | ||
502 | #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14) | ||
503 | |||
504 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
505 | #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 | ||
506 | #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 | ||
507 | #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) | ||
508 | |||
509 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
510 | #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 | ||
511 | #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 | ||
512 | #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) | ||
513 | |||
514 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
515 | #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 | ||
516 | #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 | ||
517 | #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) | ||
518 | |||
519 | /* Used by CM_MIPIEXT_CLKSTCTRL */ | ||
520 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10 | ||
521 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1 | ||
522 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10) | ||
523 | |||
524 | /* Used by CM_MIPIEXT_CLKSTCTRL */ | ||
525 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13 | ||
526 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1 | ||
527 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13) | ||
528 | |||
529 | /* Used by CM_MIPIEXT_CLKSTCTRL */ | ||
530 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12 | ||
531 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1 | ||
532 | #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12) | ||
533 | |||
534 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
535 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10 | ||
536 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1 | ||
537 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10) | ||
538 | |||
539 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
540 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13 | ||
541 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1 | ||
542 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13) | ||
543 | |||
544 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
545 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5 | ||
546 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1 | ||
547 | #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5) | ||
548 | |||
549 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
550 | #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 | ||
551 | #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 | ||
552 | #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) | ||
553 | |||
554 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
555 | #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 | ||
556 | #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 | ||
557 | #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) | ||
558 | |||
559 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
560 | #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31 | ||
561 | #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1 | ||
562 | #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31) | ||
563 | |||
564 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
565 | #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 | ||
566 | #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 | ||
567 | #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) | ||
568 | |||
569 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
570 | #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 | ||
571 | #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 | ||
572 | #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) | ||
573 | |||
574 | /* Used by CM_WKUPAON_CLKSTCTRL */ | ||
575 | #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11 | ||
576 | #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1 | ||
577 | #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11) | ||
578 | |||
579 | /* Used by CM_WKUPAON_CLKSTCTRL */ | ||
580 | #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12 | ||
581 | #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1 | ||
582 | #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12) | ||
583 | |||
584 | /* Used by CM_WKUPAON_CLKSTCTRL */ | ||
585 | #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13 | ||
586 | #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1 | ||
587 | #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13) | ||
588 | |||
589 | /* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */ | ||
590 | #define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8 | ||
591 | #define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1 | ||
592 | #define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8) | ||
593 | |||
594 | /* | ||
595 | * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, | ||
596 | * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, | ||
597 | * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, | ||
598 | * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL | ||
599 | */ | ||
600 | #define OMAP54XX_CLKSEL_SHIFT 24 | 26 | #define OMAP54XX_CLKSEL_SHIFT 24 |
601 | #define OMAP54XX_CLKSEL_WIDTH 0x1 | 27 | #define OMAP54XX_CLKSEL_WIDTH 0x1 |
602 | #define OMAP54XX_CLKSEL_MASK (1 << 24) | ||
603 | |||
604 | /* | ||
605 | * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF, | ||
606 | * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON | ||
607 | */ | ||
608 | #define OMAP54XX_CLKSEL_0_0_SHIFT 0 | 28 | #define OMAP54XX_CLKSEL_0_0_SHIFT 0 |
609 | #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 | 29 | #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 |
610 | #define OMAP54XX_CLKSEL_0_0_MASK (1 << 0) | ||
611 | |||
612 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ | ||
613 | #define OMAP54XX_CLKSEL_0_1_SHIFT 0 | ||
614 | #define OMAP54XX_CLKSEL_0_1_WIDTH 0x2 | ||
615 | #define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0) | ||
616 | |||
617 | /* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */ | ||
618 | #define OMAP54XX_CLKSEL_24_25_SHIFT 24 | ||
619 | #define OMAP54XX_CLKSEL_24_25_WIDTH 0x2 | ||
620 | #define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24) | ||
621 | |||
622 | /* Used by CM_MPU_MPU_CLKCTRL */ | ||
623 | #define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26 | ||
624 | #define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 | ||
625 | #define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) | ||
626 | |||
627 | /* Used by CM_ABE_AESS_CLKCTRL */ | ||
628 | #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 | 30 | #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 |
629 | #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 | 31 | #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 |
630 | #define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24) | ||
631 | |||
632 | /* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */ | ||
633 | #define OMAP54XX_CLKSEL_DIV_SHIFT 25 | 32 | #define OMAP54XX_CLKSEL_DIV_SHIFT 25 |
634 | #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 | 33 | #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 |
635 | #define OMAP54XX_CLKSEL_DIV_MASK (1 << 25) | ||
636 | |||
637 | /* Used by CM_MPU_MPU_CLKCTRL */ | ||
638 | #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24 | ||
639 | #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2 | ||
640 | #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24) | ||
641 | |||
642 | /* Used by CM_CAM_FDIF_CLKCTRL */ | ||
643 | #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 | 34 | #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 |
644 | #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 | 35 | #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 |
645 | #define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24) | ||
646 | |||
647 | /* Used by CM_GPU_GPU_CLKCTRL */ | ||
648 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 | 36 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 |
649 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 | 37 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 |
650 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) | ||
651 | |||
652 | /* Used by CM_GPU_GPU_CLKCTRL */ | ||
653 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 | 38 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 |
654 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 | 39 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 |
655 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) | ||
656 | |||
657 | /* Used by CM_GPU_GPU_CLKCTRL */ | ||
658 | #define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26 | ||
659 | #define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1 | ||
660 | #define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26) | ||
661 | |||
662 | /* | ||
663 | * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, | ||
664 | * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL | ||
665 | */ | ||
666 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 | 40 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 |
667 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 | 41 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 |
668 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26) | ||
669 | |||
670 | /* Used by CM_CLKSEL_CORE */ | ||
671 | #define OMAP54XX_CLKSEL_L3_SHIFT 4 | ||
672 | #define OMAP54XX_CLKSEL_L3_WIDTH 0x1 | ||
673 | #define OMAP54XX_CLKSEL_L3_MASK (1 << 4) | ||
674 | |||
675 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
676 | #define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1 | ||
677 | #define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1 | ||
678 | #define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1) | ||
679 | |||
680 | /* Used by CM_CLKSEL_CORE */ | ||
681 | #define OMAP54XX_CLKSEL_L4_SHIFT 8 | ||
682 | #define OMAP54XX_CLKSEL_L4_WIDTH 0x1 | ||
683 | #define OMAP54XX_CLKSEL_L4_MASK (1 << 8) | ||
684 | |||
685 | /* Used by CM_EMIF_EMIF1_CLKCTRL */ | ||
686 | #define OMAP54XX_CLKSEL_LL_SHIFT 24 | ||
687 | #define OMAP54XX_CLKSEL_LL_WIDTH 0x1 | ||
688 | #define OMAP54XX_CLKSEL_LL_MASK (1 << 24) | ||
689 | |||
690 | /* Used by CM_CLKSEL_ABE */ | ||
691 | #define OMAP54XX_CLKSEL_OPP_SHIFT 0 | 42 | #define OMAP54XX_CLKSEL_OPP_SHIFT 0 |
692 | #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 | 43 | #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 |
693 | #define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0) | ||
694 | |||
695 | /* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */ | ||
696 | #define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24 | ||
697 | #define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1 | ||
698 | #define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24) | ||
699 | |||
700 | /* | ||
701 | * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, | ||
702 | * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL | ||
703 | */ | ||
704 | #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 | 44 | #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 |
705 | #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 | 45 | #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 |
706 | #define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24) | ||
707 | |||
708 | /* | ||
709 | * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL, | ||
710 | * CM_L3INIT_MMC2_CLKCTRL | ||
711 | */ | ||
712 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 | 46 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 |
713 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 | 47 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 |
714 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24) | ||
715 | |||
716 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
717 | #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 | 48 | #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 |
718 | #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 | 49 | #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 |
719 | #define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24) | ||
720 | |||
721 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
722 | #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 | 50 | #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 |
723 | #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 | 51 | #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 |
724 | #define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25) | ||
725 | |||
726 | /* | ||
727 | * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, | ||
728 | * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, | ||
729 | * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, | ||
730 | * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, | ||
731 | * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE, | ||
732 | * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, | ||
733 | * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB, | ||
734 | * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER | ||
735 | */ | ||
736 | #define OMAP54XX_CLKST_SHIFT 9 | ||
737 | #define OMAP54XX_CLKST_WIDTH 0x1 | ||
738 | #define OMAP54XX_CLKST_MASK (1 << 9) | ||
739 | |||
740 | /* | ||
741 | * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL, | ||
742 | * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, | ||
743 | * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL, | ||
744 | * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL, | ||
745 | * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL, | ||
746 | * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, | ||
747 | * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL | ||
748 | */ | ||
749 | #define OMAP54XX_CLKTRCTRL_SHIFT 0 | ||
750 | #define OMAP54XX_CLKTRCTRL_WIDTH 0x2 | ||
751 | #define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0) | ||
752 | |||
753 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */ | ||
754 | #define OMAP54XX_CLKX2ST_SHIFT 11 | ||
755 | #define OMAP54XX_CLKX2ST_WIDTH 0x1 | ||
756 | #define OMAP54XX_CLKX2ST_MASK (1 << 11) | ||
757 | |||
758 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
759 | #define OMAP54XX_COREAON_DYNDEP_SHIFT 16 | ||
760 | #define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1 | ||
761 | #define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16) | ||
762 | |||
763 | /* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ | ||
764 | #define OMAP54XX_COREAON_STATDEP_SHIFT 16 | ||
765 | #define OMAP54XX_COREAON_STATDEP_WIDTH 0x1 | ||
766 | #define OMAP54XX_COREAON_STATDEP_MASK (1 << 16) | ||
767 | |||
768 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
769 | #define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17 | ||
770 | #define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1 | ||
771 | #define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17) | ||
772 | |||
773 | /* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ | ||
774 | #define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17 | ||
775 | #define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1 | ||
776 | #define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17) | ||
777 | |||
778 | /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ | ||
779 | #define OMAP54XX_CUSTOM_SHIFT 6 | ||
780 | #define OMAP54XX_CUSTOM_WIDTH 0x2 | ||
781 | #define OMAP54XX_CUSTOM_MASK (0x3 << 6) | ||
782 | |||
783 | /* | ||
784 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, | ||
785 | * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, | ||
786 | * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB | ||
787 | */ | ||
788 | #define OMAP54XX_DCC_EN_SHIFT 22 | ||
789 | #define OMAP54XX_DCC_EN_WIDTH 0x1 | ||
790 | #define OMAP54XX_DCC_EN_MASK (1 << 22) | ||
791 | |||
792 | /* | ||
793 | * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS, | ||
794 | * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS, | ||
795 | * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS | ||
796 | */ | ||
797 | #define OMAP54XX_CM_DEBUG_OUT_SHIFT 0 | ||
798 | #define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd | ||
799 | #define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0) | ||
800 | |||
801 | /* | ||
802 | * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS, | ||
803 | * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS | ||
804 | */ | ||
805 | #define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 | ||
806 | #define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 | ||
807 | #define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) | ||
808 | |||
809 | /* | ||
810 | * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS, | ||
811 | * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS | ||
812 | */ | ||
813 | #define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0 | ||
814 | #define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9 | ||
815 | #define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0) | ||
816 | |||
817 | /* | ||
818 | * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS, | ||
819 | * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS | ||
820 | */ | ||
821 | #define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0 | ||
822 | #define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5 | ||
823 | #define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0) | ||
824 | |||
825 | /* | ||
826 | * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS, | ||
827 | * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS | ||
828 | */ | ||
829 | #define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0 | ||
830 | #define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6 | ||
831 | #define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0) | ||
832 | |||
833 | /* | ||
834 | * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS, | ||
835 | * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS | ||
836 | */ | ||
837 | #define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0 | ||
838 | #define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb | ||
839 | #define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0) | ||
840 | |||
841 | /* | ||
842 | * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS, | ||
843 | * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS | ||
844 | */ | ||
845 | #define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 | ||
846 | #define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 | ||
847 | #define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) | ||
848 | |||
849 | /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */ | ||
850 | #define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0 | ||
851 | #define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14 | ||
852 | #define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0) | ||
853 | |||
854 | /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */ | ||
855 | #define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 | ||
856 | #define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa | ||
857 | #define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) | ||
858 | |||
859 | /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */ | ||
860 | #define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0 | ||
861 | #define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b | ||
862 | #define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0) | ||
863 | |||
864 | /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */ | ||
865 | #define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0 | ||
866 | #define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe | ||
867 | #define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0) | ||
868 | |||
869 | /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */ | ||
870 | #define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0 | ||
871 | #define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16 | ||
872 | #define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0) | ||
873 | |||
874 | /* | ||
875 | * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, | ||
876 | * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, | ||
877 | * CM_SSC_DELTAMSTEP_DPLL_PER | ||
878 | */ | ||
879 | #define OMAP54XX_DELTAMSTEP_SHIFT 0 | ||
880 | #define OMAP54XX_DELTAMSTEP_WIDTH 0x14 | ||
881 | #define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0) | ||
882 | |||
883 | /* | ||
884 | * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1, | ||
885 | * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB | ||
886 | */ | ||
887 | #define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0 | ||
888 | #define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15 | ||
889 | #define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0) | ||
890 | |||
891 | /* | ||
892 | * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, | ||
893 | * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, | ||
894 | * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, | ||
895 | * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, | ||
896 | * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE | ||
897 | */ | ||
898 | #define OMAP54XX_DIVHS_SHIFT 0 | ||
899 | #define OMAP54XX_DIVHS_WIDTH 0x6 | ||
900 | #define OMAP54XX_DIVHS_MASK (0x3f << 0) | 52 | #define OMAP54XX_DIVHS_MASK (0x3f << 0) |
901 | |||
902 | /* | ||
903 | * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, | ||
904 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, | ||
905 | * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER | ||
906 | */ | ||
907 | #define OMAP54XX_DIVHS_0_4_SHIFT 0 | ||
908 | #define OMAP54XX_DIVHS_0_4_WIDTH 0x5 | ||
909 | #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) | 53 | #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) |
910 | |||
911 | /* | ||
912 | * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, | ||
913 | * CM_DIV_M2_DPLL_USB | ||
914 | */ | ||
915 | #define OMAP54XX_DIVHS_0_6_SHIFT 0 | ||
916 | #define OMAP54XX_DIVHS_0_6_WIDTH 0x7 | ||
917 | #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) | 54 | #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) |
918 | |||
919 | /* Used by CM_DLL_CTRL */ | ||
920 | #define OMAP54XX_DLL_OVERRIDE_SHIFT 0 | ||
921 | #define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1 | ||
922 | #define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0) | ||
923 | |||
924 | /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
925 | #define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2 | ||
926 | #define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1 | ||
927 | #define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2) | ||
928 | |||
929 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
930 | #define OMAP54XX_DLL_RESET_SHIFT 3 | ||
931 | #define OMAP54XX_DLL_RESET_WIDTH 0x1 | ||
932 | #define OMAP54XX_DLL_RESET_MASK (1 << 3) | ||
933 | |||
934 | /* | ||
935 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, | ||
936 | * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, | ||
937 | * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB | ||
938 | */ | ||
939 | #define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23 | ||
940 | #define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1 | ||
941 | #define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23) | ||
942 | |||
943 | /* Used by CM_CLKSEL_DPLL_CORE */ | ||
944 | #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 | ||
945 | #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 | ||
946 | #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) | ||
947 | |||
948 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
949 | #define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8 | ||
950 | #define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3 | ||
951 | #define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) | ||
952 | |||
953 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
954 | #define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2 | ||
955 | #define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6 | ||
956 | #define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2) | ||
957 | |||
958 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
959 | #define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11 | ||
960 | #define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5 | ||
961 | #define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11) | ||
962 | |||
963 | /* | ||
964 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, | ||
965 | * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER | ||
966 | */ | ||
967 | #define OMAP54XX_DPLL_DIV_SHIFT 0 | ||
968 | #define OMAP54XX_DPLL_DIV_WIDTH 0x7 | ||
969 | #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) | 55 | #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) |
970 | |||
971 | /* | ||
972 | * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1, | ||
973 | * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB | ||
974 | */ | ||
975 | #define OMAP54XX_DPLL_DIV_0_7_SHIFT 0 | ||
976 | #define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8 | ||
977 | #define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0) | ||
978 | |||
979 | /* | ||
980 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, | ||
981 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
982 | */ | ||
983 | #define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8 | ||
984 | #define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1 | ||
985 | #define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | ||
986 | |||
987 | /* | ||
988 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, | ||
989 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, | ||
990 | * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB | ||
991 | */ | ||
992 | #define OMAP54XX_DPLL_EN_SHIFT 0 | ||
993 | #define OMAP54XX_DPLL_EN_WIDTH 0x3 | ||
994 | #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) | 56 | #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) |
995 | |||
996 | /* | ||
997 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, | ||
998 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
999 | */ | ||
1000 | #define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10 | ||
1001 | #define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1 | ||
1002 | #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) | 57 | #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) |
1003 | |||
1004 | /* | ||
1005 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, | ||
1006 | * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER | ||
1007 | */ | ||
1008 | #define OMAP54XX_DPLL_MULT_SHIFT 8 | ||
1009 | #define OMAP54XX_DPLL_MULT_WIDTH 0xb | ||
1010 | #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) | 58 | #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) |
1011 | |||
1012 | /* | ||
1013 | * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1, | ||
1014 | * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB | ||
1015 | */ | ||
1016 | #define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8 | ||
1017 | #define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc | ||
1018 | #define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8) | ||
1019 | |||
1020 | /* | ||
1021 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, | ||
1022 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
1023 | */ | ||
1024 | #define OMAP54XX_DPLL_REGM4XEN_SHIFT 11 | ||
1025 | #define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1 | ||
1026 | #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) | 59 | #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) |
1027 | |||
1028 | /* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ | ||
1029 | #define OMAP54XX_DPLL_SD_DIV_SHIFT 24 | ||
1030 | #define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8 | ||
1031 | #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) | 60 | #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) |
1032 | |||
1033 | /* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ | ||
1034 | #define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21 | ||
1035 | #define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1 | ||
1036 | #define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21) | ||
1037 | |||
1038 | /* | ||
1039 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, | ||
1040 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, | ||
1041 | * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB | ||
1042 | */ | ||
1043 | #define OMAP54XX_DPLL_SSC_ACK_SHIFT 13 | ||
1044 | #define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1 | ||
1045 | #define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13) | ||
1046 | |||
1047 | /* | ||
1048 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, | ||
1049 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, | ||
1050 | * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB | ||
1051 | */ | ||
1052 | #define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 | ||
1053 | #define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 | ||
1054 | #define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) | ||
1055 | |||
1056 | /* | ||
1057 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, | ||
1058 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, | ||
1059 | * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB | ||
1060 | */ | ||
1061 | #define OMAP54XX_DPLL_SSC_EN_SHIFT 12 | ||
1062 | #define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1 | ||
1063 | #define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12) | ||
1064 | |||
1065 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1066 | #define OMAP54XX_DSP_DYNDEP_SHIFT 1 | ||
1067 | #define OMAP54XX_DSP_DYNDEP_WIDTH 0x1 | ||
1068 | #define OMAP54XX_DSP_DYNDEP_MASK (1 << 1) | ||
1069 | |||
1070 | /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ | ||
1071 | #define OMAP54XX_DSP_STATDEP_SHIFT 1 | 61 | #define OMAP54XX_DSP_STATDEP_SHIFT 1 |
1072 | #define OMAP54XX_DSP_STATDEP_WIDTH 0x1 | ||
1073 | #define OMAP54XX_DSP_STATDEP_MASK (1 << 1) | ||
1074 | |||
1075 | /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
1076 | #define OMAP54XX_DSS_DYNDEP_SHIFT 8 | ||
1077 | #define OMAP54XX_DSS_DYNDEP_WIDTH 0x1 | ||
1078 | #define OMAP54XX_DSS_DYNDEP_MASK (1 << 8) | ||
1079 | |||
1080 | /* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ | ||
1081 | #define OMAP54XX_DSS_STATDEP_SHIFT 8 | 62 | #define OMAP54XX_DSS_STATDEP_SHIFT 8 |
1082 | #define OMAP54XX_DSS_STATDEP_WIDTH 0x1 | ||
1083 | #define OMAP54XX_DSS_STATDEP_MASK (1 << 8) | ||
1084 | |||
1085 | /* | ||
1086 | * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
1087 | * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP | ||
1088 | */ | ||
1089 | #define OMAP54XX_EMIF_DYNDEP_SHIFT 4 | ||
1090 | #define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1 | ||
1091 | #define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4) | ||
1092 | |||
1093 | /* | ||
1094 | * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, | ||
1095 | * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, | ||
1096 | * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, | ||
1097 | * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP | ||
1098 | */ | ||
1099 | #define OMAP54XX_EMIF_STATDEP_SHIFT 4 | 63 | #define OMAP54XX_EMIF_STATDEP_SHIFT 4 |
1100 | #define OMAP54XX_EMIF_STATDEP_WIDTH 0x1 | ||
1101 | #define OMAP54XX_EMIF_STATDEP_MASK (1 << 4) | ||
1102 | |||
1103 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
1104 | #define OMAP54XX_FREQ_UPDATE_SHIFT 0 | ||
1105 | #define OMAP54XX_FREQ_UPDATE_WIDTH 0x1 | ||
1106 | #define OMAP54XX_FREQ_UPDATE_MASK (1 << 0) | ||
1107 | |||
1108 | /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ | ||
1109 | #define OMAP54XX_FUNC_SHIFT 16 | ||
1110 | #define OMAP54XX_FUNC_WIDTH 0xc | ||
1111 | #define OMAP54XX_FUNC_MASK (0xfff << 16) | ||
1112 | |||
1113 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
1114 | #define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0 | ||
1115 | #define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1 | ||
1116 | #define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0) | ||
1117 | |||
1118 | /* Used by CM_L3MAIN2_DYNAMICDEP */ | ||
1119 | #define OMAP54XX_GPU_DYNDEP_SHIFT 10 | ||
1120 | #define OMAP54XX_GPU_DYNDEP_WIDTH 0x1 | ||
1121 | #define OMAP54XX_GPU_DYNDEP_MASK (1 << 10) | ||
1122 | |||
1123 | /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ | ||
1124 | #define OMAP54XX_GPU_STATDEP_SHIFT 10 | 64 | #define OMAP54XX_GPU_STATDEP_SHIFT 10 |
1125 | #define OMAP54XX_GPU_STATDEP_WIDTH 0x1 | ||
1126 | #define OMAP54XX_GPU_STATDEP_MASK (1 << 10) | ||
1127 | |||
1128 | /* | ||
1129 | * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, | ||
1130 | * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, | ||
1131 | * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, | ||
1132 | * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, | ||
1133 | * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, | ||
1134 | * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, | ||
1135 | * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, | ||
1136 | * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, | ||
1137 | * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, | ||
1138 | * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, | ||
1139 | * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, | ||
1140 | * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, | ||
1141 | * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, | ||
1142 | * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, | ||
1143 | * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, | ||
1144 | * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | ||
1145 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, | ||
1146 | * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, | ||
1147 | * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, | ||
1148 | * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, | ||
1149 | * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, | ||
1150 | * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
1151 | * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, | ||
1152 | * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, | ||
1153 | * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, | ||
1154 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, | ||
1155 | * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | ||
1156 | * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, | ||
1157 | * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, | ||
1158 | * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, | ||
1159 | * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, | ||
1160 | * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, | ||
1161 | * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | ||
1162 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, | ||
1163 | * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, | ||
1164 | * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, | ||
1165 | * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, | ||
1166 | * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, | ||
1167 | * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, | ||
1168 | * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, | ||
1169 | * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, | ||
1170 | * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, | ||
1171 | * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, | ||
1172 | * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, | ||
1173 | * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, | ||
1174 | * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, | ||
1175 | * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, | ||
1176 | * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL | ||
1177 | */ | ||
1178 | #define OMAP54XX_IDLEST_SHIFT 16 | ||
1179 | #define OMAP54XX_IDLEST_WIDTH 0x2 | ||
1180 | #define OMAP54XX_IDLEST_MASK (0x3 << 16) | ||
1181 | |||
1182 | /* Used by CM_L3MAIN2_DYNAMICDEP */ | ||
1183 | #define OMAP54XX_IPU_DYNDEP_SHIFT 0 | ||
1184 | #define OMAP54XX_IPU_DYNDEP_WIDTH 0x1 | ||
1185 | #define OMAP54XX_IPU_DYNDEP_MASK (1 << 0) | ||
1186 | |||
1187 | /* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */ | ||
1188 | #define OMAP54XX_IPU_STATDEP_SHIFT 0 | 65 | #define OMAP54XX_IPU_STATDEP_SHIFT 0 |
1189 | #define OMAP54XX_IPU_STATDEP_WIDTH 0x1 | ||
1190 | #define OMAP54XX_IPU_STATDEP_MASK (1 << 0) | ||
1191 | |||
1192 | /* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */ | ||
1193 | #define OMAP54XX_IVA_DYNDEP_SHIFT 2 | ||
1194 | #define OMAP54XX_IVA_DYNDEP_WIDTH 0x1 | ||
1195 | #define OMAP54XX_IVA_DYNDEP_MASK (1 << 2) | ||
1196 | |||
1197 | /* | ||
1198 | * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, | ||
1199 | * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, | ||
1200 | * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP | ||
1201 | */ | ||
1202 | #define OMAP54XX_IVA_STATDEP_SHIFT 2 | 66 | #define OMAP54XX_IVA_STATDEP_SHIFT 2 |
1203 | #define OMAP54XX_IVA_STATDEP_WIDTH 0x1 | ||
1204 | #define OMAP54XX_IVA_STATDEP_MASK (1 << 2) | ||
1205 | |||
1206 | /* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
1207 | #define OMAP54XX_L3INIT_DYNDEP_SHIFT 7 | ||
1208 | #define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1 | ||
1209 | #define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7) | ||
1210 | |||
1211 | /* | ||
1212 | * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, | ||
1213 | * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP | ||
1214 | */ | ||
1215 | #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 | 67 | #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 |
1216 | #define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1 | ||
1217 | #define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7) | ||
1218 | |||
1219 | /* | ||
1220 | * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, | ||
1221 | * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP | ||
1222 | */ | ||
1223 | #define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5 | ||
1224 | #define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1 | ||
1225 | #define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5) | ||
1226 | |||
1227 | /* | ||
1228 | * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, | ||
1229 | * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, | ||
1230 | * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, | ||
1231 | * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP | ||
1232 | */ | ||
1233 | #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 | 68 | #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 |
1234 | #define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1 | ||
1235 | #define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5) | ||
1236 | |||
1237 | /* | ||
1238 | * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP, | ||
1239 | * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP, | ||
1240 | * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, | ||
1241 | * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP | ||
1242 | */ | ||
1243 | #define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6 | ||
1244 | #define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1 | ||
1245 | #define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6) | ||
1246 | |||
1247 | /* | ||
1248 | * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, | ||
1249 | * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, | ||
1250 | * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, | ||
1251 | * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP | ||
1252 | */ | ||
1253 | #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 | 69 | #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 |
1254 | #define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1 | ||
1255 | #define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6) | ||
1256 | |||
1257 | /* Used by CM_L3MAIN1_DYNAMICDEP */ | ||
1258 | #define OMAP54XX_L4CFG_DYNDEP_SHIFT 12 | ||
1259 | #define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1 | ||
1260 | #define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12) | ||
1261 | |||
1262 | /* | ||
1263 | * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, | ||
1264 | * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP | ||
1265 | */ | ||
1266 | #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 | 70 | #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 |
1267 | #define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1 | ||
1268 | #define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12) | ||
1269 | |||
1270 | /* Used by CM_L3MAIN2_DYNAMICDEP */ | ||
1271 | #define OMAP54XX_L4PER_DYNDEP_SHIFT 13 | ||
1272 | #define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1 | ||
1273 | #define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13) | ||
1274 | |||
1275 | /* | ||
1276 | * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, | ||
1277 | * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, | ||
1278 | * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP | ||
1279 | */ | ||
1280 | #define OMAP54XX_L4PER_STATDEP_SHIFT 13 | 71 | #define OMAP54XX_L4PER_STATDEP_SHIFT 13 |
1281 | #define OMAP54XX_L4PER_STATDEP_WIDTH 0x1 | ||
1282 | #define OMAP54XX_L4PER_STATDEP_MASK (1 << 13) | ||
1283 | |||
1284 | /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
1285 | #define OMAP54XX_L4SEC_DYNDEP_SHIFT 14 | ||
1286 | #define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1 | ||
1287 | #define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14) | ||
1288 | |||
1289 | /* | ||
1290 | * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, | ||
1291 | * CM_MPU_STATICDEP | ||
1292 | */ | ||
1293 | #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 | 72 | #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 |
1294 | #define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1 | ||
1295 | #define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14) | ||
1296 | |||
1297 | /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
1298 | #define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21 | ||
1299 | #define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1 | ||
1300 | #define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21) | ||
1301 | |||
1302 | /* Used by CM_MPU_STATICDEP */ | ||
1303 | #define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21 | ||
1304 | #define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1 | ||
1305 | #define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21) | ||
1306 | |||
1307 | /* | ||
1308 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, | ||
1309 | * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
1310 | * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, | ||
1311 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB | ||
1312 | */ | ||
1313 | #define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8 | ||
1314 | #define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3 | ||
1315 | #define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) | ||
1316 | |||
1317 | /* | ||
1318 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, | ||
1319 | * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
1320 | * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, | ||
1321 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB | ||
1322 | */ | ||
1323 | #define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0 | ||
1324 | #define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7 | ||
1325 | #define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) | ||
1326 | |||
1327 | /* | ||
1328 | * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, | ||
1329 | * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, | ||
1330 | * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, | ||
1331 | * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, | ||
1332 | * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, | ||
1333 | * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, | ||
1334 | * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, | ||
1335 | * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, | ||
1336 | * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, | ||
1337 | * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, | ||
1338 | * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, | ||
1339 | * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, | ||
1340 | * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, | ||
1341 | * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, | ||
1342 | * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, | ||
1343 | * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | ||
1344 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, | ||
1345 | * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, | ||
1346 | * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, | ||
1347 | * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, | ||
1348 | * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, | ||
1349 | * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
1350 | * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, | ||
1351 | * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, | ||
1352 | * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, | ||
1353 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, | ||
1354 | * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | ||
1355 | * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, | ||
1356 | * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, | ||
1357 | * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, | ||
1358 | * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, | ||
1359 | * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, | ||
1360 | * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | ||
1361 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, | ||
1362 | * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, | ||
1363 | * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, | ||
1364 | * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, | ||
1365 | * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, | ||
1366 | * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, | ||
1367 | * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, | ||
1368 | * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, | ||
1369 | * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, | ||
1370 | * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, | ||
1371 | * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, | ||
1372 | * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, | ||
1373 | * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, | ||
1374 | * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, | ||
1375 | * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL | ||
1376 | */ | ||
1377 | #define OMAP54XX_MODULEMODE_SHIFT 0 | ||
1378 | #define OMAP54XX_MODULEMODE_WIDTH 0x2 | ||
1379 | #define OMAP54XX_MODULEMODE_MASK (0x3 << 0) | ||
1380 | |||
1381 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1382 | #define OMAP54XX_MPU_DYNDEP_SHIFT 19 | ||
1383 | #define OMAP54XX_MPU_DYNDEP_WIDTH 0x1 | ||
1384 | #define OMAP54XX_MPU_DYNDEP_MASK (1 << 19) | ||
1385 | |||
1386 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1387 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 | 73 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 |
1388 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1 | ||
1389 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11) | ||
1390 | |||
1391 | /* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */ | ||
1392 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 | 74 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 |
1393 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1 | ||
1394 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8) | ||
1395 | |||
1396 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1397 | #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 | 75 | #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
1398 | #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 | ||
1399 | #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) | ||
1400 | |||
1401 | /* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */ | ||
1402 | #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 | 76 | #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 |
1403 | #define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1 | ||
1404 | #define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8) | ||
1405 | |||
1406 | /* Used by CM_CAM_ISS_CLKCTRL */ | ||
1407 | #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 | 77 | #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 |
1408 | #define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1 | ||
1409 | #define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8) | ||
1410 | |||
1411 | /* | ||
1412 | * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, | ||
1413 | * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, | ||
1414 | * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL | ||
1415 | */ | ||
1416 | #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 | 78 | #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 |
1417 | #define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1 | ||
1418 | #define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8) | ||
1419 | |||
1420 | /* Used by CM_EMIF_EMIF_DLL_CLKCTRL */ | ||
1421 | #define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8 | ||
1422 | #define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1 | ||
1423 | #define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8) | ||
1424 | |||
1425 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1426 | #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 | 79 | #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 |
1427 | #define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1 | ||
1428 | #define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8) | ||
1429 | |||
1430 | /* Used by CM_ABE_SLIMBUS1_CLKCTRL */ | ||
1431 | #define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8 | ||
1432 | #define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1 | ||
1433 | #define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8) | ||
1434 | |||
1435 | /* Used by CM_ABE_SLIMBUS1_CLKCTRL */ | ||
1436 | #define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9 | ||
1437 | #define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1 | ||
1438 | #define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9) | ||
1439 | |||
1440 | /* Used by CM_ABE_SLIMBUS1_CLKCTRL */ | ||
1441 | #define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10 | ||
1442 | #define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1 | ||
1443 | #define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10) | ||
1444 | |||
1445 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1446 | #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15 | ||
1447 | #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1 | ||
1448 | #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15) | ||
1449 | |||
1450 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1451 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 | 80 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
1452 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 | ||
1453 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) | ||
1454 | |||
1455 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1456 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 | 81 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
1457 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 | ||
1458 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) | ||
1459 | |||
1460 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1461 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 | 82 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 |
1462 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1 | ||
1463 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7) | ||
1464 | |||
1465 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1466 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 | 83 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
1467 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 | ||
1468 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) | ||
1469 | |||
1470 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1471 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 | 84 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
1472 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 | ||
1473 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) | ||
1474 | |||
1475 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1476 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 | 85 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 |
1477 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1 | ||
1478 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6) | ||
1479 | |||
1480 | /* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */ | ||
1481 | #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 | 86 | #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 |
1482 | #define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1 | ||
1483 | #define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8) | ||
1484 | |||
1485 | /* Used by CM_L3INIT_SATA_CLKCTRL */ | ||
1486 | #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 | 87 | #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 |
1487 | #define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1 | ||
1488 | #define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8) | ||
1489 | |||
1490 | /* Used by CM_WKUPAON_SCRM_CLKCTRL */ | ||
1491 | #define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8 | ||
1492 | #define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1 | ||
1493 | #define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8) | ||
1494 | |||
1495 | /* Used by CM_WKUPAON_SCRM_CLKCTRL */ | ||
1496 | #define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9 | ||
1497 | #define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1 | ||
1498 | #define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9) | ||
1499 | |||
1500 | /* Used by CM_ABE_SLIMBUS1_CLKCTRL */ | ||
1501 | #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 | 88 | #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 |
1502 | #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 | ||
1503 | #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11) | ||
1504 | |||
1505 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
1506 | #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 | 89 | #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 |
1507 | #define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1 | ||
1508 | #define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10) | ||
1509 | |||
1510 | /* Used by CM_MIPIEXT_LLI_CLKCTRL */ | ||
1511 | #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 | 90 | #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 |
1512 | #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1 | ||
1513 | #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8) | ||
1514 | |||
1515 | /* Used by CM_MIPIEXT_LLI_CLKCTRL */ | ||
1516 | #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 | 91 | #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 |
1517 | #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1 | ||
1518 | #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9) | ||
1519 | |||
1520 | /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ | ||
1521 | #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 | 92 | #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
1522 | #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 | ||
1523 | #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) | ||
1524 | |||
1525 | /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ | ||
1526 | #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 | 93 | #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
1527 | #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 | ||
1528 | #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) | ||
1529 | |||
1530 | /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ | ||
1531 | #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 | 94 | #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
1532 | #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 | ||
1533 | #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) | ||
1534 | |||
1535 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1536 | #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 | 95 | #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
1537 | #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 | ||
1538 | #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) | ||
1539 | |||
1540 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1541 | #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 | 96 | #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
1542 | #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 | ||
1543 | #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) | ||
1544 | |||
1545 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ | ||
1546 | #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 | 97 | #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
1547 | #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 | ||
1548 | #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) | ||
1549 | |||
1550 | /* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */ | ||
1551 | #define OMAP54XX_OUTPUT_SHIFT 0 | ||
1552 | #define OMAP54XX_OUTPUT_WIDTH 0x20 | ||
1553 | #define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) | ||
1554 | |||
1555 | /* Used by CM_CLKSEL_ABE */ | ||
1556 | #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 | 98 | #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 |
1557 | #define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1 | ||
1558 | #define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8) | ||
1559 | |||
1560 | /* Used by CM_RESTORE_ST */ | ||
1561 | #define OMAP54XX_PHASE1_COMPLETED_SHIFT 0 | ||
1562 | #define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1 | ||
1563 | #define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0) | ||
1564 | |||
1565 | /* Used by CM_RESTORE_ST */ | ||
1566 | #define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1 | ||
1567 | #define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1 | ||
1568 | #define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1) | ||
1569 | |||
1570 | /* Used by CM_RESTORE_ST */ | ||
1571 | #define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2 | ||
1572 | #define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1 | ||
1573 | #define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2) | ||
1574 | |||
1575 | /* Used by CM_DYN_DEP_PRESCAL */ | ||
1576 | #define OMAP54XX_PRESCAL_SHIFT 0 | ||
1577 | #define OMAP54XX_PRESCAL_WIDTH 0x6 | ||
1578 | #define OMAP54XX_PRESCAL_MASK (0x3f << 0) | ||
1579 | |||
1580 | /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ | ||
1581 | #define OMAP54XX_R_RTL_SHIFT 11 | ||
1582 | #define OMAP54XX_R_RTL_WIDTH 0x5 | ||
1583 | #define OMAP54XX_R_RTL_MASK (0x1f << 11) | ||
1584 | |||
1585 | /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */ | ||
1586 | #define OMAP54XX_SAR_MODE_SHIFT 4 | ||
1587 | #define OMAP54XX_SAR_MODE_WIDTH 0x1 | ||
1588 | #define OMAP54XX_SAR_MODE_MASK (1 << 4) | ||
1589 | |||
1590 | /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ | ||
1591 | #define OMAP54XX_SCHEME_SHIFT 30 | ||
1592 | #define OMAP54XX_SCHEME_WIDTH 0x2 | ||
1593 | #define OMAP54XX_SCHEME_MASK (0x3 << 30) | ||
1594 | |||
1595 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
1596 | #define OMAP54XX_SDMA_DYNDEP_SHIFT 11 | ||
1597 | #define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1 | ||
1598 | #define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11) | ||
1599 | |||
1600 | /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ | ||
1601 | #define OMAP54XX_SDMA_STATDEP_SHIFT 11 | ||
1602 | #define OMAP54XX_SDMA_STATDEP_WIDTH 0x1 | ||
1603 | #define OMAP54XX_SDMA_STATDEP_MASK (1 << 11) | ||
1604 | |||
1605 | /* Used by CM_CORE_AON_DEBUG_CFG */ | ||
1606 | #define OMAP54XX_SEL0_SHIFT 0 | ||
1607 | #define OMAP54XX_SEL0_WIDTH 0x7 | ||
1608 | #define OMAP54XX_SEL0_MASK (0x7f << 0) | ||
1609 | |||
1610 | /* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */ | ||
1611 | #define OMAP54XX_SEL0_0_7_SHIFT 0 | ||
1612 | #define OMAP54XX_SEL0_0_7_WIDTH 0x8 | ||
1613 | #define OMAP54XX_SEL0_0_7_MASK (0xff << 0) | ||
1614 | |||
1615 | /* Used by CM_CORE_AON_DEBUG_CFG */ | ||
1616 | #define OMAP54XX_SEL1_SHIFT 8 | ||
1617 | #define OMAP54XX_SEL1_WIDTH 0x7 | ||
1618 | #define OMAP54XX_SEL1_MASK (0x7f << 8) | ||
1619 | |||
1620 | /* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */ | ||
1621 | #define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8 | ||
1622 | #define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8 | ||
1623 | #define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8) | ||
1624 | |||
1625 | /* Used by CM_CORE_AON_DEBUG_CFG */ | ||
1626 | #define OMAP54XX_SEL2_SHIFT 16 | ||
1627 | #define OMAP54XX_SEL2_WIDTH 0x7 | ||
1628 | #define OMAP54XX_SEL2_MASK (0x7f << 16) | ||
1629 | |||
1630 | /* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */ | ||
1631 | #define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16 | ||
1632 | #define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8 | ||
1633 | #define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16) | ||
1634 | |||
1635 | /* Used by CM_CORE_AON_DEBUG_CFG */ | ||
1636 | #define OMAP54XX_SEL3_SHIFT 24 | ||
1637 | #define OMAP54XX_SEL3_WIDTH 0x7 | ||
1638 | #define OMAP54XX_SEL3_MASK (0x7f << 24) | ||
1639 | |||
1640 | /* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */ | ||
1641 | #define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24 | ||
1642 | #define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8 | ||
1643 | #define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24) | ||
1644 | |||
1645 | /* Used by CM_CLKSEL_ABE */ | ||
1646 | #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 | 99 | #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 |
1647 | #define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1 | ||
1648 | #define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10) | ||
1649 | |||
1650 | /* | ||
1651 | * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | ||
1652 | * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL, | ||
1653 | * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, | ||
1654 | * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL, | ||
1655 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, | ||
1656 | * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL, | ||
1657 | * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL, | ||
1658 | * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, | ||
1659 | * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL | ||
1660 | */ | ||
1661 | #define OMAP54XX_STBYST_SHIFT 18 | ||
1662 | #define OMAP54XX_STBYST_WIDTH 0x1 | ||
1663 | #define OMAP54XX_STBYST_MASK (1 << 18) | ||
1664 | |||
1665 | /* | ||
1666 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, | ||
1667 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, | ||
1668 | * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB | ||
1669 | */ | ||
1670 | #define OMAP54XX_ST_DPLL_CLK_SHIFT 0 | ||
1671 | #define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1 | ||
1672 | #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) | 100 | #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) |
1673 | |||
1674 | /* | ||
1675 | * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2, | ||
1676 | * CM_CLKDCOLDO_DPLL_USB | ||
1677 | */ | ||
1678 | #define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9 | ||
1679 | #define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1 | ||
1680 | #define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9) | ||
1681 | |||
1682 | /* | ||
1683 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, | ||
1684 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, | ||
1685 | * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB | ||
1686 | */ | ||
1687 | #define OMAP54XX_ST_DPLL_INIT_SHIFT 4 | ||
1688 | #define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1 | ||
1689 | #define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4) | ||
1690 | |||
1691 | /* | ||
1692 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, | ||
1693 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, | ||
1694 | * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB | ||
1695 | */ | ||
1696 | #define OMAP54XX_ST_DPLL_MODE_SHIFT 1 | ||
1697 | #define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3 | ||
1698 | #define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1) | ||
1699 | |||
1700 | /* Used by CM_CLKSEL_SYS */ | ||
1701 | #define OMAP54XX_SYS_CLKSEL_SHIFT 0 | 101 | #define OMAP54XX_SYS_CLKSEL_SHIFT 0 |
1702 | #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 | 102 | #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 |
1703 | #define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0) | ||
1704 | |||
1705 | /* | ||
1706 | * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP, | ||
1707 | * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, | ||
1708 | * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP, | ||
1709 | * CM_MPU_DYNAMICDEP | ||
1710 | */ | ||
1711 | #define OMAP54XX_WINDOWSIZE_SHIFT 24 | ||
1712 | #define OMAP54XX_WINDOWSIZE_WIDTH 0x4 | ||
1713 | #define OMAP54XX_WINDOWSIZE_MASK (0xf << 24) | ||
1714 | |||
1715 | /* Used by CM_L3MAIN1_DYNAMICDEP */ | ||
1716 | #define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15 | ||
1717 | #define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1 | ||
1718 | #define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15) | ||
1719 | |||
1720 | /* | ||
1721 | * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, | ||
1722 | * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP | ||
1723 | */ | ||
1724 | #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 | 103 | #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 |
1725 | #define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1 | ||
1726 | #define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15) | ||
1727 | |||
1728 | /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ | ||
1729 | #define OMAP54XX_X_MAJOR_SHIFT 8 | ||
1730 | #define OMAP54XX_X_MAJOR_WIDTH 0x3 | ||
1731 | #define OMAP54XX_X_MAJOR_MASK (0x7 << 8) | ||
1732 | |||
1733 | /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ | ||
1734 | #define OMAP54XX_Y_MINOR_SHIFT 0 | ||
1735 | #define OMAP54XX_Y_MINOR_WIDTH 0x6 | ||
1736 | #define OMAP54XX_Y_MINOR_MASK (0x3f << 0) | ||
1737 | #endif | 104 | #endif |
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 3c70f5c1860f..b4d04748576b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include "cm1_54xx.h" | 32 | #include "cm1_54xx.h" |
33 | #include "cm2_54xx.h" | 33 | #include "cm2_54xx.h" |
34 | #include "prm54xx.h" | 34 | #include "prm54xx.h" |
35 | #include "prm-regbits-54xx.h" | ||
36 | #include "i2c.h" | 35 | #include "i2c.h" |
37 | #include "mmc.h" | 36 | #include "mmc.h" |
38 | #include "wd_timer.h" | 37 | #include "wd_timer.h" |
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c index 81f8a7cc26ee..ce1d752af991 100644 --- a/arch/arm/mach-omap2/powerdomains54xx_data.c +++ b/arch/arm/mach-omap2/powerdomains54xx_data.c | |||
@@ -25,7 +25,6 @@ | |||
25 | 25 | ||
26 | #include "prcm-common.h" | 26 | #include "prcm-common.h" |
27 | #include "prcm44xx.h" | 27 | #include "prcm44xx.h" |
28 | #include "prm-regbits-54xx.h" | ||
29 | #include "prm54xx.h" | 28 | #include "prm54xx.h" |
30 | #include "prcm_mpu54xx.h" | 29 | #include "prcm_mpu54xx.h" |
31 | 30 | ||
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 91aa5106d637..37fc905c9636 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h | |||
@@ -16,274 +16,27 @@ | |||
16 | 16 | ||
17 | #include "prm2xxx.h" | 17 | #include "prm2xxx.h" |
18 | 18 | ||
19 | /* Bits shared between registers */ | ||
20 | |||
21 | /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ | ||
22 | #define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2) | ||
23 | #define OMAP24XX_WKUP2_ST_MASK (1 << 1) | ||
24 | #define OMAP24XX_WKUP1_ST_MASK (1 << 0) | ||
25 | |||
26 | /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ | ||
27 | #define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2) | ||
28 | #define OMAP24XX_WKUP2_EN_MASK (1 << 1) | ||
29 | #define OMAP24XX_WKUP1_EN_MASK (1 << 0) | ||
30 | |||
31 | /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ | ||
32 | #define OMAP24XX_EN_MPU_SHIFT 1 | ||
33 | #define OMAP24XX_EN_MPU_MASK (1 << 1) | ||
34 | #define OMAP24XX_EN_CORE_SHIFT 0 | 19 | #define OMAP24XX_EN_CORE_SHIFT 0 |
35 | #define OMAP24XX_EN_CORE_MASK (1 << 0) | ||
36 | |||
37 | /* | ||
38 | * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM | ||
39 | * shared bits | ||
40 | */ | ||
41 | #define OMAP24XX_MEMONSTATE_SHIFT 10 | ||
42 | #define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) | ||
43 | #define OMAP24XX_MEMRETSTATE_MASK (1 << 3) | ||
44 | |||
45 | /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ | ||
46 | #define OMAP24XX_FORCESTATE_MASK (1 << 18) | 20 | #define OMAP24XX_FORCESTATE_MASK (1 << 18) |
47 | |||
48 | /* | ||
49 | * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, | ||
50 | * PM_PWSTST_MDM shared bits | ||
51 | */ | ||
52 | #define OMAP24XX_CLKACTIVITY_MASK (1 << 19) | ||
53 | |||
54 | /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ | ||
55 | #define OMAP24XX_LASTSTATEENTERED_SHIFT 4 | ||
56 | #define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4) | ||
57 | |||
58 | /* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */ | ||
59 | #define OMAP2430_MEMSTATEST_SHIFT 10 | ||
60 | #define OMAP2430_MEMSTATEST_MASK (0x3 << 10) | ||
61 | |||
62 | /* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */ | ||
63 | #define OMAP24XX_POWERSTATEST_SHIFT 0 | ||
64 | #define OMAP24XX_POWERSTATEST_MASK (0x3 << 0) | ||
65 | |||
66 | |||
67 | /* Bits specific to each register */ | ||
68 | |||
69 | /* PRCM_REVISION */ | ||
70 | #define OMAP24XX_REV_SHIFT 0 | ||
71 | #define OMAP24XX_REV_MASK (0xff << 0) | ||
72 | |||
73 | /* PRCM_SYSCONFIG */ | ||
74 | #define OMAP24XX_AUTOIDLE_MASK (1 << 0) | 21 | #define OMAP24XX_AUTOIDLE_MASK (1 << 0) |
75 | |||
76 | /* PRCM_IRQSTATUS_MPU specific bits */ | ||
77 | #define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6) | ||
78 | #define OMAP24XX_TRANSITION_ST_MASK (1 << 5) | ||
79 | #define OMAP24XX_EVGENOFF_ST_MASK (1 << 4) | ||
80 | #define OMAP24XX_EVGENON_ST_MASK (1 << 3) | ||
81 | |||
82 | /* PRCM_IRQENABLE_MPU specific bits */ | ||
83 | #define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6) | ||
84 | #define OMAP24XX_TRANSITION_EN_MASK (1 << 5) | ||
85 | #define OMAP24XX_EVGENOFF_EN_MASK (1 << 4) | ||
86 | #define OMAP24XX_EVGENON_EN_MASK (1 << 3) | ||
87 | |||
88 | /* PRCM_VOLTCTRL */ | ||
89 | #define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) | 22 | #define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) |
90 | #define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14) | ||
91 | #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 | 23 | #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 |
92 | #define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) | ||
93 | #define OMAP24XX_MEMRETCTRL_MASK (1 << 8) | 24 | #define OMAP24XX_MEMRETCTRL_MASK (1 << 8) |
94 | #define OMAP24XX_SETRET_LEVEL_SHIFT 6 | 25 | #define OMAP24XX_SETRET_LEVEL_SHIFT 6 |
95 | #define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) | ||
96 | #define OMAP24XX_VOLT_LEVEL_SHIFT 0 | 26 | #define OMAP24XX_VOLT_LEVEL_SHIFT 0 |
97 | #define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0) | ||
98 | |||
99 | /* PRCM_VOLTST */ | ||
100 | #define OMAP24XX_ST_VOLTLEVEL_SHIFT 0 | ||
101 | #define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0) | ||
102 | |||
103 | /* PRCM_CLKSRC_CTRL specific bits */ | ||
104 | |||
105 | /* PRCM_CLKOUT_CTRL */ | ||
106 | #define OMAP2420_CLKOUT2_EN_SHIFT 15 | 27 | #define OMAP2420_CLKOUT2_EN_SHIFT 15 |
107 | #define OMAP2420_CLKOUT2_EN_MASK (1 << 15) | ||
108 | #define OMAP2420_CLKOUT2_DIV_SHIFT 11 | 28 | #define OMAP2420_CLKOUT2_DIV_SHIFT 11 |
109 | #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) | ||
110 | #define OMAP2420_CLKOUT2_DIV_WIDTH 3 | 29 | #define OMAP2420_CLKOUT2_DIV_WIDTH 3 |
111 | #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 | ||
112 | #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) | 30 | #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) |
113 | #define OMAP24XX_CLKOUT_EN_SHIFT 7 | 31 | #define OMAP24XX_CLKOUT_EN_SHIFT 7 |
114 | #define OMAP24XX_CLKOUT_EN_MASK (1 << 7) | ||
115 | #define OMAP24XX_CLKOUT_DIV_SHIFT 3 | 32 | #define OMAP24XX_CLKOUT_DIV_SHIFT 3 |
116 | #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) | ||
117 | #define OMAP24XX_CLKOUT_DIV_WIDTH 3 | 33 | #define OMAP24XX_CLKOUT_DIV_WIDTH 3 |
118 | #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 | ||
119 | #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) | 34 | #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) |
120 | |||
121 | /* PRCM_CLKEMUL_CTRL */ | ||
122 | #define OMAP24XX_EMULATION_EN_SHIFT 0 | 35 | #define OMAP24XX_EMULATION_EN_SHIFT 0 |
123 | #define OMAP24XX_EMULATION_EN_MASK (1 << 0) | ||
124 | |||
125 | /* PRCM_CLKCFG_CTRL */ | ||
126 | #define OMAP24XX_VALID_CONFIG_MASK (1 << 0) | ||
127 | |||
128 | /* PRCM_CLKCFG_STATUS */ | ||
129 | #define OMAP24XX_CONFIG_STATUS_MASK (1 << 0) | ||
130 | |||
131 | /* PRCM_VOLTSETUP specific bits */ | ||
132 | |||
133 | /* PRCM_CLKSSETUP specific bits */ | ||
134 | |||
135 | /* PRCM_POLCTRL */ | ||
136 | #define OMAP2420_CLKOUT2_POL_MASK (1 << 10) | ||
137 | #define OMAP24XX_CLKOUT_POL_MASK (1 << 9) | ||
138 | #define OMAP24XX_CLKREQ_POL_MASK (1 << 8) | ||
139 | #define OMAP2430_USE_POWEROK_MASK (1 << 2) | ||
140 | #define OMAP2430_POWEROK_POL_MASK (1 << 1) | ||
141 | #define OMAP24XX_EXTVOL_POL_MASK (1 << 0) | ||
142 | |||
143 | /* RM_RSTST_MPU specific bits */ | ||
144 | /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ | ||
145 | |||
146 | /* PM_WKDEP_MPU specific bits */ | ||
147 | #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 | 36 | #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 |
148 | #define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5) | ||
149 | #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 | 37 | #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 |
150 | #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2) | ||
151 | |||
152 | /* PM_EVGENCTRL_MPU specific bits */ | ||
153 | |||
154 | /* PM_EVEGENONTIM_MPU specific bits */ | ||
155 | |||
156 | /* PM_EVEGENOFFTIM_MPU specific bits */ | ||
157 | |||
158 | /* PM_PWSTCTRL_MPU specific bits */ | ||
159 | #define OMAP2430_FORCESTATE_MASK (1 << 18) | ||
160 | |||
161 | /* PM_PWSTST_MPU specific bits */ | ||
162 | /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ | ||
163 | |||
164 | /* PM_WKEN1_CORE specific bits */ | ||
165 | |||
166 | /* PM_WKEN2_CORE specific bits */ | ||
167 | |||
168 | /* PM_WKST1_CORE specific bits*/ | ||
169 | |||
170 | /* PM_WKST2_CORE specific bits */ | ||
171 | |||
172 | /* PM_WKDEP_CORE specific bits*/ | ||
173 | #define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5) | ||
174 | #define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3) | ||
175 | #define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2) | ||
176 | |||
177 | /* PM_PWSTCTRL_CORE specific bits */ | ||
178 | #define OMAP24XX_MEMORYCHANGE_MASK (1 << 20) | ||
179 | #define OMAP24XX_MEM3ONSTATE_SHIFT 14 | ||
180 | #define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) | ||
181 | #define OMAP24XX_MEM2ONSTATE_SHIFT 12 | ||
182 | #define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) | ||
183 | #define OMAP24XX_MEM1ONSTATE_SHIFT 10 | ||
184 | #define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) | ||
185 | #define OMAP24XX_MEM3RETSTATE_MASK (1 << 5) | ||
186 | #define OMAP24XX_MEM2RETSTATE_MASK (1 << 4) | ||
187 | #define OMAP24XX_MEM1RETSTATE_MASK (1 << 3) | ||
188 | |||
189 | /* PM_PWSTST_CORE specific bits */ | ||
190 | #define OMAP24XX_MEM3STATEST_SHIFT 14 | ||
191 | #define OMAP24XX_MEM3STATEST_MASK (0x3 << 14) | ||
192 | #define OMAP24XX_MEM2STATEST_SHIFT 12 | ||
193 | #define OMAP24XX_MEM2STATEST_MASK (0x3 << 12) | ||
194 | #define OMAP24XX_MEM1STATEST_SHIFT 10 | ||
195 | #define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) | ||
196 | |||
197 | /* RM_RSTCTRL_GFX */ | ||
198 | #define OMAP24XX_GFX_RST_MASK (1 << 0) | ||
199 | |||
200 | /* RM_RSTST_GFX specific bits */ | ||
201 | #define OMAP24XX_GFX_SW_RST_MASK (1 << 4) | ||
202 | |||
203 | /* PM_PWSTCTRL_GFX specific bits */ | ||
204 | |||
205 | /* PM_WKDEP_GFX specific bits */ | ||
206 | /* 2430 often calls EN_WAKEUP "EN_WKUP" */ | ||
207 | |||
208 | /* RM_RSTCTRL_WKUP specific bits */ | ||
209 | |||
210 | /* RM_RSTTIME_WKUP specific bits */ | ||
211 | |||
212 | /* RM_RSTST_WKUP specific bits */ | ||
213 | /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ | ||
214 | #define OMAP24XX_EXTWMPU_RST_SHIFT 6 | 38 | #define OMAP24XX_EXTWMPU_RST_SHIFT 6 |
215 | #define OMAP24XX_EXTWMPU_RST_MASK (1 << 6) | ||
216 | #define OMAP24XX_SECU_WD_RST_SHIFT 5 | 39 | #define OMAP24XX_SECU_WD_RST_SHIFT 5 |
217 | #define OMAP24XX_SECU_WD_RST_MASK (1 << 5) | ||
218 | #define OMAP24XX_MPU_WD_RST_SHIFT 4 | 40 | #define OMAP24XX_MPU_WD_RST_SHIFT 4 |
219 | #define OMAP24XX_MPU_WD_RST_MASK (1 << 4) | ||
220 | #define OMAP24XX_SECU_VIOL_RST_SHIFT 3 | 41 | #define OMAP24XX_SECU_VIOL_RST_SHIFT 3 |
221 | #define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3) | ||
222 | |||
223 | /* PM_WKEN_WKUP specific bits */ | ||
224 | |||
225 | /* PM_WKST_WKUP specific bits */ | ||
226 | |||
227 | /* RM_RSTCTRL_DSP */ | ||
228 | #define OMAP2420_RST_IVA_MASK (1 << 8) | ||
229 | #define OMAP24XX_RST2_DSP_MASK (1 << 1) | ||
230 | #define OMAP24XX_RST1_DSP_MASK (1 << 0) | ||
231 | |||
232 | /* RM_RSTST_DSP specific bits */ | ||
233 | /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ | ||
234 | #define OMAP2420_IVA_SW_RST_MASK (1 << 8) | ||
235 | #define OMAP24XX_DSP_SW_RST2_MASK (1 << 5) | ||
236 | #define OMAP24XX_DSP_SW_RST1_MASK (1 << 4) | ||
237 | |||
238 | /* PM_WKDEP_DSP specific bits */ | ||
239 | |||
240 | /* PM_PWSTCTRL_DSP specific bits */ | ||
241 | /* 2430 only: MEMONSTATE, MEMRETSTATE */ | ||
242 | #define OMAP2420_MEMIONSTATE_SHIFT 12 | ||
243 | #define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) | ||
244 | #define OMAP2420_MEMIRETSTATE_MASK (1 << 4) | ||
245 | |||
246 | /* PM_PWSTST_DSP specific bits */ | ||
247 | /* MEMSTATEST is 2430 only */ | ||
248 | #define OMAP2420_MEMISTATEST_SHIFT 12 | ||
249 | #define OMAP2420_MEMISTATEST_MASK (0x3 << 12) | ||
250 | |||
251 | /* PRCM_IRQSTATUS_DSP specific bits */ | ||
252 | |||
253 | /* PRCM_IRQENABLE_DSP specific bits */ | ||
254 | |||
255 | /* RM_RSTCTRL_MDM */ | ||
256 | /* 2430 only */ | ||
257 | #define OMAP2430_PWRON1_MDM_MASK (1 << 1) | ||
258 | #define OMAP2430_RST1_MDM_MASK (1 << 0) | ||
259 | |||
260 | /* RM_RSTST_MDM specific bits */ | ||
261 | /* 2430 only */ | ||
262 | #define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6) | ||
263 | #define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5) | ||
264 | #define OMAP2430_MDM_SW_RST1_MASK (1 << 4) | ||
265 | |||
266 | /* PM_WKEN_MDM */ | ||
267 | /* 2430 only */ | ||
268 | #define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0) | ||
269 | |||
270 | /* PM_WKST_MDM specific bits */ | ||
271 | /* 2430 only */ | ||
272 | |||
273 | /* PM_WKDEP_MDM specific bits */ | ||
274 | /* 2430 only */ | ||
275 | |||
276 | /* PM_PWSTCTRL_MDM specific bits */ | ||
277 | /* 2430 only */ | ||
278 | #define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19) | ||
279 | |||
280 | /* PM_PWSTST_MDM specific bits */ | ||
281 | /* 2430 only */ | ||
282 | |||
283 | /* PRCM_IRQSTATUS_IVA */ | ||
284 | /* 2420 only */ | ||
285 | |||
286 | /* PRCM_IRQENABLE_IVA */ | ||
287 | /* 2420 only */ | ||
288 | |||
289 | #endif | 42 | #endif |
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h index 0221b5c20e87..84feecee4fe6 100644 --- a/arch/arm/mach-omap2/prm-regbits-33xx.h +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h | |||
@@ -18,340 +18,35 @@ | |||
18 | 18 | ||
19 | #include "prm.h" | 19 | #include "prm.h" |
20 | 20 | ||
21 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
22 | #define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 | ||
23 | #define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) | ||
24 | |||
25 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
26 | #define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 | ||
27 | #define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) | ||
28 | |||
29 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
30 | #define AM33XX_AIPOFF_SHIFT 8 | ||
31 | #define AM33XX_AIPOFF_MASK (1 << 8) | ||
32 | |||
33 | /* Used by PM_WKUP_PWRSTST */ | ||
34 | #define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 | ||
35 | #define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) | ||
36 | |||
37 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
38 | #define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 | ||
39 | #define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) | ||
40 | |||
41 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
42 | #define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 | ||
43 | #define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) | ||
44 | |||
45 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
46 | #define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 | ||
47 | #define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) | ||
48 | |||
49 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
50 | #define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 | ||
51 | #define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) | ||
52 | |||
53 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
54 | #define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 | ||
55 | #define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) | ||
56 | |||
57 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
58 | #define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 | ||
59 | #define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) | ||
60 | |||
61 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
62 | #define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 | ||
63 | #define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) | ||
64 | |||
65 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
66 | #define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 | ||
67 | #define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) | ||
68 | |||
69 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
70 | #define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 | ||
71 | #define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) | ||
72 | |||
73 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
74 | #define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 | ||
75 | #define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) | ||
76 | |||
77 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
78 | #define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 | ||
79 | #define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) | ||
80 | |||
81 | /* Used by RM_WKUP_RSTST */ | ||
82 | #define AM33XX_EMULATION_M3_RST_SHIFT 6 | ||
83 | #define AM33XX_EMULATION_M3_RST_MASK (1 << 6) | ||
84 | |||
85 | /* Used by RM_MPU_RSTST */ | ||
86 | #define AM33XX_EMULATION_MPU_RST_SHIFT 5 | ||
87 | #define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) | ||
88 | |||
89 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
90 | #define AM33XX_ENFUNC1_EXPORT_SHIFT 3 | ||
91 | #define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) | ||
92 | |||
93 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
94 | #define AM33XX_ENFUNC3_EXPORT_SHIFT 5 | ||
95 | #define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) | ||
96 | |||
97 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
98 | #define AM33XX_ENFUNC4_SHIFT 6 | ||
99 | #define AM33XX_ENFUNC4_MASK (1 << 6) | ||
100 | |||
101 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
102 | #define AM33XX_ENFUNC5_SHIFT 7 | ||
103 | #define AM33XX_ENFUNC5_MASK (1 << 7) | ||
104 | |||
105 | /* Used by PRM_RSTST */ | ||
106 | #define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 | ||
107 | #define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) | ||
108 | |||
109 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
110 | #define AM33XX_FORCEWKUP_EN_SHIFT 10 | ||
111 | #define AM33XX_FORCEWKUP_EN_MASK (1 << 10) | ||
112 | |||
113 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
114 | #define AM33XX_FORCEWKUP_ST_SHIFT 10 | ||
115 | #define AM33XX_FORCEWKUP_ST_MASK (1 << 10) | ||
116 | |||
117 | /* Used by PM_GFX_PWRSTCTRL */ | ||
118 | #define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 | ||
119 | #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) | 21 | #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) |
120 | |||
121 | /* Used by PM_GFX_PWRSTCTRL */ | ||
122 | #define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 | ||
123 | #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) | 22 | #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) |
124 | |||
125 | /* Used by PM_GFX_PWRSTST */ | ||
126 | #define AM33XX_GFX_MEM_STATEST_SHIFT 4 | ||
127 | #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) | 23 | #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) |
128 | |||
129 | /* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ | ||
130 | #define AM33XX_GFX_RST_SHIFT 0 | ||
131 | #define AM33XX_GFX_RST_MASK (1 << 0) | ||
132 | |||
133 | /* Used by PRM_RSTST */ | ||
134 | #define AM33XX_GLOBAL_COLD_RST_SHIFT 0 | ||
135 | #define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) | ||
136 | |||
137 | /* Used by PRM_RSTST */ | ||
138 | #define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 | ||
139 | #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) | 24 | #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) |
140 | 25 | #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) | |
141 | /* Used by RM_WKUP_RSTST */ | ||
142 | #define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 | ||
143 | #define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) | ||
144 | |||
145 | /* Used by RM_MPU_RSTST */ | ||
146 | #define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 | ||
147 | #define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) | ||
148 | |||
149 | /* Used by PRM_RSTST */ | ||
150 | #define AM33XX_ICEPICK_RST_SHIFT 9 | ||
151 | #define AM33XX_ICEPICK_RST_MASK (1 << 9) | ||
152 | |||
153 | /* Used by RM_PER_RSTCTRL */ | ||
154 | #define AM33XX_PRUSS_LRST_SHIFT 1 | ||
155 | #define AM33XX_PRUSS_LRST_MASK (1 << 1) | ||
156 | |||
157 | /* Used by PM_PER_PWRSTCTRL */ | ||
158 | #define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 | ||
159 | #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) | 26 | #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) |
160 | |||
161 | /* Used by PM_PER_PWRSTCTRL */ | ||
162 | #define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 | ||
163 | #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) | 27 | #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) |
164 | |||
165 | /* Used by PM_PER_PWRSTST */ | ||
166 | #define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 | ||
167 | #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) | 28 | #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) |
168 | |||
169 | /* | ||
170 | * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, | ||
171 | * PM_WKUP_PWRSTST, PM_RTC_PWRSTST | ||
172 | */ | ||
173 | #define AM33XX_INTRANSITION_SHIFT 20 | ||
174 | #define AM33XX_INTRANSITION_MASK (1 << 20) | ||
175 | |||
176 | /* Used by PM_CEFUSE_PWRSTST */ | ||
177 | #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 | 29 | #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 |
178 | #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | 30 | #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) |
179 | |||
180 | /* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ | ||
181 | #define AM33XX_LOGICRETSTATE_SHIFT 2 | ||
182 | #define AM33XX_LOGICRETSTATE_MASK (1 << 2) | 31 | #define AM33XX_LOGICRETSTATE_MASK (1 << 2) |
183 | |||
184 | /* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ | ||
185 | #define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 | ||
186 | #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) | 32 | #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) |
187 | |||
188 | /* | ||
189 | * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, | ||
190 | * PM_WKUP_PWRSTST, PM_RTC_PWRSTST | ||
191 | */ | ||
192 | #define AM33XX_LOGICSTATEST_SHIFT 2 | 33 | #define AM33XX_LOGICSTATEST_SHIFT 2 |
193 | #define AM33XX_LOGICSTATEST_MASK (1 << 2) | 34 | #define AM33XX_LOGICSTATEST_MASK (1 << 2) |
194 | |||
195 | /* | ||
196 | * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, | ||
197 | * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL | ||
198 | */ | ||
199 | #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 | 35 | #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 |
200 | #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) | 36 | #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) |
201 | |||
202 | /* Used by PM_MPU_PWRSTCTRL */ | ||
203 | #define AM33XX_MPU_L1_ONSTATE_SHIFT 18 | ||
204 | #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) | 37 | #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) |
205 | |||
206 | /* Used by PM_MPU_PWRSTCTRL */ | ||
207 | #define AM33XX_MPU_L1_RETSTATE_SHIFT 22 | ||
208 | #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) | 38 | #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) |
209 | |||
210 | /* Used by PM_MPU_PWRSTST */ | ||
211 | #define AM33XX_MPU_L1_STATEST_SHIFT 6 | ||
212 | #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) | 39 | #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) |
213 | |||
214 | /* Used by PM_MPU_PWRSTCTRL */ | ||
215 | #define AM33XX_MPU_L2_ONSTATE_SHIFT 20 | ||
216 | #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) | 40 | #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) |
217 | |||
218 | /* Used by PM_MPU_PWRSTCTRL */ | ||
219 | #define AM33XX_MPU_L2_RETSTATE_SHIFT 23 | ||
220 | #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) | 41 | #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) |
221 | |||
222 | /* Used by PM_MPU_PWRSTST */ | ||
223 | #define AM33XX_MPU_L2_STATEST_SHIFT 8 | ||
224 | #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) | 42 | #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) |
225 | |||
226 | /* Used by PM_MPU_PWRSTCTRL */ | ||
227 | #define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 | ||
228 | #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) | 43 | #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) |
229 | |||
230 | /* Used by PM_MPU_PWRSTCTRL */ | ||
231 | #define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 | ||
232 | #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) | 44 | #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) |
233 | |||
234 | /* Used by PM_MPU_PWRSTST */ | ||
235 | #define AM33XX_MPU_RAM_STATEST_SHIFT 4 | ||
236 | #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) | 45 | #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) |
237 | |||
238 | /* Used by PRM_RSTST */ | ||
239 | #define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 | ||
240 | #define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) | ||
241 | |||
242 | /* Used by PRM_SRAM_COUNT */ | ||
243 | #define AM33XX_PCHARGECNT_VALUE_SHIFT 0 | ||
244 | #define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) | ||
245 | |||
246 | /* Used by RM_PER_RSTCTRL */ | ||
247 | #define AM33XX_PCI_LRST_SHIFT 0 | ||
248 | #define AM33XX_PCI_LRST_MASK (1 << 0) | ||
249 | |||
250 | /* Renamed from PCI_LRST Used by RM_PER_RSTST */ | ||
251 | #define AM33XX_PCI_LRST_5_5_SHIFT 5 | ||
252 | #define AM33XX_PCI_LRST_5_5_MASK (1 << 5) | ||
253 | |||
254 | /* Used by PM_PER_PWRSTCTRL */ | ||
255 | #define AM33XX_PER_MEM_ONSTATE_SHIFT 25 | ||
256 | #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) | 46 | #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) |
257 | |||
258 | /* Used by PM_PER_PWRSTCTRL */ | ||
259 | #define AM33XX_PER_MEM_RETSTATE_SHIFT 29 | ||
260 | #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) | 47 | #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) |
261 | |||
262 | /* Used by PM_PER_PWRSTST */ | ||
263 | #define AM33XX_PER_MEM_STATEST_SHIFT 17 | ||
264 | #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) | 48 | #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) |
265 | |||
266 | /* | ||
267 | * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, | ||
268 | * PM_MPU_PWRSTCTRL | ||
269 | */ | ||
270 | #define AM33XX_POWERSTATE_SHIFT 0 | ||
271 | #define AM33XX_POWERSTATE_MASK (0x3 << 0) | ||
272 | |||
273 | /* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ | ||
274 | #define AM33XX_POWERSTATEST_SHIFT 0 | ||
275 | #define AM33XX_POWERSTATEST_MASK (0x3 << 0) | ||
276 | |||
277 | /* Used by PM_PER_PWRSTCTRL */ | ||
278 | #define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 | ||
279 | #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) | 49 | #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) |
280 | |||
281 | /* Used by PM_PER_PWRSTCTRL */ | ||
282 | #define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 | ||
283 | #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) | 50 | #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) |
284 | |||
285 | /* Used by PM_PER_PWRSTST */ | ||
286 | #define AM33XX_RAM_MEM_STATEST_SHIFT 21 | ||
287 | #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) | 51 | #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) |
288 | |||
289 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
290 | #define AM33XX_RETMODE_ENABLE_SHIFT 0 | ||
291 | #define AM33XX_RETMODE_ENABLE_MASK (1 << 0) | ||
292 | |||
293 | /* Used by REVISION_PRM */ | ||
294 | #define AM33XX_REV_SHIFT 0 | ||
295 | #define AM33XX_REV_MASK (0xff << 0) | ||
296 | |||
297 | /* Used by PRM_RSTTIME */ | ||
298 | #define AM33XX_RSTTIME1_SHIFT 0 | ||
299 | #define AM33XX_RSTTIME1_MASK (0xff << 0) | ||
300 | |||
301 | /* Used by PRM_RSTTIME */ | ||
302 | #define AM33XX_RSTTIME2_SHIFT 8 | ||
303 | #define AM33XX_RSTTIME2_MASK (0x1f << 8) | ||
304 | |||
305 | /* Used by PRM_RSTCTRL */ | ||
306 | #define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 | ||
307 | #define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) | ||
308 | |||
309 | /* Used by PRM_RSTCTRL */ | ||
310 | #define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 | ||
311 | #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) | ||
312 | |||
313 | /* Used by PRM_SRAM_COUNT */ | ||
314 | #define AM33XX_SLPCNT_VALUE_SHIFT 16 | ||
315 | #define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) | ||
316 | |||
317 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
318 | #define AM33XX_SRAMLDO_STATUS_SHIFT 8 | ||
319 | #define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) | ||
320 | |||
321 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
322 | #define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 | ||
323 | #define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) | ||
324 | |||
325 | /* Used by PRM_SRAM_COUNT */ | ||
326 | #define AM33XX_STARTUP_COUNT_SHIFT 24 | ||
327 | #define AM33XX_STARTUP_COUNT_MASK (0xff << 24) | ||
328 | |||
329 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
330 | #define AM33XX_TRANSITION_EN_SHIFT 8 | ||
331 | #define AM33XX_TRANSITION_EN_MASK (1 << 8) | ||
332 | |||
333 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
334 | #define AM33XX_TRANSITION_ST_SHIFT 8 | ||
335 | #define AM33XX_TRANSITION_ST_MASK (1 << 8) | ||
336 | |||
337 | /* Used by PRM_SRAM_COUNT */ | ||
338 | #define AM33XX_VSETUPCNT_VALUE_SHIFT 8 | ||
339 | #define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) | ||
340 | |||
341 | /* Used by PRM_RSTST */ | ||
342 | #define AM33XX_WDT0_RST_SHIFT 3 | ||
343 | #define AM33XX_WDT0_RST_MASK (1 << 3) | ||
344 | |||
345 | /* Used by PRM_RSTST */ | ||
346 | #define AM33XX_WDT1_RST_SHIFT 4 | ||
347 | #define AM33XX_WDT1_RST_MASK (1 << 4) | ||
348 | |||
349 | /* Used by RM_WKUP_RSTCTRL */ | ||
350 | #define AM33XX_WKUP_M3_LRST_SHIFT 3 | ||
351 | #define AM33XX_WKUP_M3_LRST_MASK (1 << 3) | ||
352 | |||
353 | /* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ | ||
354 | #define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 | ||
355 | #define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) | ||
356 | |||
357 | #endif | 52 | #endif |
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index b0a2142eeb91..cebad565ed37 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
@@ -16,115 +16,25 @@ | |||
16 | 16 | ||
17 | #include "prm3xxx.h" | 17 | #include "prm3xxx.h" |
18 | 18 | ||
19 | /* Shared register bits */ | ||
20 | |||
21 | /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */ | ||
22 | #define OMAP3430_ON_SHIFT 24 | ||
23 | #define OMAP3430_ON_MASK (0xff << 24) | ||
24 | #define OMAP3430_ONLP_SHIFT 16 | ||
25 | #define OMAP3430_ONLP_MASK (0xff << 16) | ||
26 | #define OMAP3430_RET_SHIFT 8 | ||
27 | #define OMAP3430_RET_MASK (0xff << 8) | ||
28 | #define OMAP3430_OFF_SHIFT 0 | ||
29 | #define OMAP3430_OFF_MASK (0xff << 0) | ||
30 | |||
31 | /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */ | ||
32 | #define OMAP3430_ERROROFFSET_SHIFT 24 | ||
33 | #define OMAP3430_ERROROFFSET_MASK (0xff << 24) | 19 | #define OMAP3430_ERROROFFSET_MASK (0xff << 24) |
34 | #define OMAP3430_ERRORGAIN_SHIFT 16 | ||
35 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) | 20 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) |
36 | #define OMAP3430_INITVOLTAGE_SHIFT 8 | ||
37 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) | 21 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) |
38 | #define OMAP3430_TIMEOUTEN_MASK (1 << 3) | 22 | #define OMAP3430_TIMEOUTEN_MASK (1 << 3) |
39 | #define OMAP3430_INITVDD_MASK (1 << 2) | 23 | #define OMAP3430_INITVDD_MASK (1 << 2) |
40 | #define OMAP3430_FORCEUPDATE_MASK (1 << 1) | 24 | #define OMAP3430_FORCEUPDATE_MASK (1 << 1) |
41 | #define OMAP3430_VPENABLE_MASK (1 << 0) | 25 | #define OMAP3430_VPENABLE_MASK (1 << 0) |
42 | |||
43 | /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ | ||
44 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 | 26 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 |
45 | #define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8) | ||
46 | #define OMAP3430_VSTEPMIN_SHIFT 0 | 27 | #define OMAP3430_VSTEPMIN_SHIFT 0 |
47 | #define OMAP3430_VSTEPMIN_MASK (0xff << 0) | ||
48 | |||
49 | /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */ | ||
50 | #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 | 28 | #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 |
51 | #define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8) | ||
52 | #define OMAP3430_VSTEPMAX_SHIFT 0 | 29 | #define OMAP3430_VSTEPMAX_SHIFT 0 |
53 | #define OMAP3430_VSTEPMAX_MASK (0xff << 0) | ||
54 | |||
55 | /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */ | ||
56 | #define OMAP3430_VDDMAX_SHIFT 24 | 30 | #define OMAP3430_VDDMAX_SHIFT 24 |
57 | #define OMAP3430_VDDMAX_MASK (0xff << 24) | ||
58 | #define OMAP3430_VDDMIN_SHIFT 16 | 31 | #define OMAP3430_VDDMIN_SHIFT 16 |
59 | #define OMAP3430_VDDMIN_MASK (0xff << 16) | ||
60 | #define OMAP3430_TIMEOUT_SHIFT 0 | 32 | #define OMAP3430_TIMEOUT_SHIFT 0 |
61 | #define OMAP3430_TIMEOUT_MASK (0xffff << 0) | ||
62 | |||
63 | /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */ | ||
64 | #define OMAP3430_VPVOLTAGE_SHIFT 0 | ||
65 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) | 33 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) |
66 | |||
67 | /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ | ||
68 | #define OMAP3430_VPINIDLE_MASK (1 << 0) | ||
69 | |||
70 | /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ | ||
71 | #define OMAP3430_EN_PER_SHIFT 7 | 34 | #define OMAP3430_EN_PER_SHIFT 7 |
72 | #define OMAP3430_EN_PER_MASK (1 << 7) | ||
73 | |||
74 | /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ | ||
75 | #define OMAP3430_MEMORYCHANGE_MASK (1 << 3) | ||
76 | |||
77 | /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ | ||
78 | #define OMAP3430_LOGICSTATEST_MASK (1 << 2) | 35 | #define OMAP3430_LOGICSTATEST_MASK (1 << 2) |
79 | |||
80 | /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ | ||
81 | #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) | 36 | #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) |
82 | |||
83 | /* | ||
84 | * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, | ||
85 | * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, | ||
86 | * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits | ||
87 | */ | ||
88 | #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 | ||
89 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) | 37 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) |
90 | |||
91 | /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ | ||
92 | #define OMAP3430_WKUP_ST_MASK (1 << 0) | ||
93 | |||
94 | /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ | ||
95 | #define OMAP3430_WKUP_EN_MASK (1 << 0) | ||
96 | |||
97 | /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ | ||
98 | #define OMAP3430_GRPSEL_MMC2_MASK (1 << 25) | ||
99 | #define OMAP3430_GRPSEL_MMC1_MASK (1 << 24) | ||
100 | #define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21) | ||
101 | #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) | ||
102 | #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) | ||
103 | #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) | ||
104 | #define OMAP3430_GRPSEL_I2C3_SHIFT 17 | ||
105 | #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) | ||
106 | #define OMAP3430_GRPSEL_I2C2_SHIFT 16 | ||
107 | #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) | ||
108 | #define OMAP3430_GRPSEL_I2C1_SHIFT 15 | ||
109 | #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) | ||
110 | #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) | ||
111 | #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) | ||
112 | #define OMAP3430_GRPSEL_GPT11_MASK (1 << 12) | ||
113 | #define OMAP3430_GRPSEL_GPT10_MASK (1 << 11) | ||
114 | #define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10) | ||
115 | #define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9) | ||
116 | #define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4) | ||
117 | #define OMAP3430_GRPSEL_D2D_MASK (1 << 3) | ||
118 | |||
119 | /* | ||
120 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, | ||
121 | * PM_PWSTCTRL_PER shared bits | ||
122 | */ | ||
123 | #define OMAP3430_MEMONSTATE_SHIFT 16 | ||
124 | #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) | ||
125 | #define OMAP3430_MEMRETSTATE_MASK (1 << 8) | ||
126 | |||
127 | /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ | ||
128 | #define OMAP3630_GRPSEL_UART4_MASK (1 << 18) | 38 | #define OMAP3630_GRPSEL_UART4_MASK (1 << 18) |
129 | #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) | 39 | #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) |
130 | #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) | 40 | #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) |
@@ -132,480 +42,89 @@ | |||
132 | #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) | 42 | #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) |
133 | #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) | 43 | #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) |
134 | #define OMAP3430_GRPSEL_UART3_MASK (1 << 11) | 44 | #define OMAP3430_GRPSEL_UART3_MASK (1 << 11) |
135 | #define OMAP3430_GRPSEL_GPT9_MASK (1 << 10) | ||
136 | #define OMAP3430_GRPSEL_GPT8_MASK (1 << 9) | ||
137 | #define OMAP3430_GRPSEL_GPT7_MASK (1 << 8) | ||
138 | #define OMAP3430_GRPSEL_GPT6_MASK (1 << 7) | ||
139 | #define OMAP3430_GRPSEL_GPT5_MASK (1 << 6) | ||
140 | #define OMAP3430_GRPSEL_GPT4_MASK (1 << 5) | ||
141 | #define OMAP3430_GRPSEL_GPT3_MASK (1 << 4) | ||
142 | #define OMAP3430_GRPSEL_GPT2_MASK (1 << 3) | ||
143 | #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) | 45 | #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) |
144 | #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) | 46 | #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) |
145 | #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) | 47 | #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) |
146 | |||
147 | /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ | ||
148 | #define OMAP3430_GRPSEL_IO_MASK (1 << 8) | ||
149 | #define OMAP3430_GRPSEL_SR2_MASK (1 << 7) | ||
150 | #define OMAP3430_GRPSEL_SR1_MASK (1 << 6) | ||
151 | #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) | 48 | #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) |
152 | #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) | 49 | #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) |
153 | #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) | 50 | #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) |
154 | |||
155 | /* Bits specific to each register */ | ||
156 | |||
157 | /* RM_RSTCTRL_IVA2 */ | ||
158 | #define OMAP3430_RST3_IVA2_MASK (1 << 2) | 51 | #define OMAP3430_RST3_IVA2_MASK (1 << 2) |
159 | #define OMAP3430_RST2_IVA2_MASK (1 << 1) | 52 | #define OMAP3430_RST2_IVA2_MASK (1 << 1) |
160 | #define OMAP3430_RST1_IVA2_MASK (1 << 0) | 53 | #define OMAP3430_RST1_IVA2_MASK (1 << 0) |
161 | |||
162 | /* RM_RSTST_IVA2 specific bits */ | ||
163 | #define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13) | ||
164 | #define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12) | ||
165 | #define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11) | ||
166 | #define OMAP3430_IVA2_SW_RST3_MASK (1 << 10) | ||
167 | #define OMAP3430_IVA2_SW_RST2_MASK (1 << 9) | ||
168 | #define OMAP3430_IVA2_SW_RST1_MASK (1 << 8) | ||
169 | |||
170 | /* PM_WKDEP_IVA2 specific bits */ | ||
171 | |||
172 | /* PM_PWSTCTRL_IVA2 specific bits */ | ||
173 | #define OMAP3430_L2FLATMEMONSTATE_SHIFT 22 | ||
174 | #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) | 54 | #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) |
175 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20 | ||
176 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) | 55 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) |
177 | #define OMAP3430_L1FLATMEMONSTATE_SHIFT 18 | ||
178 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) | 56 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) |
179 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 | ||
180 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) | 57 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) |
181 | #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) | 58 | #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) |
182 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) | 59 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) |
183 | #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) | 60 | #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) |
184 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) | 61 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) |
185 | |||
186 | /* PM_PWSTST_IVA2 specific bits */ | ||
187 | #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 | ||
188 | #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) | 62 | #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) |
189 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8 | ||
190 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) | 63 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) |
191 | #define OMAP3430_L1FLATMEMSTATEST_SHIFT 6 | ||
192 | #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) | 64 | #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) |
193 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4 | ||
194 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) | 65 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) |
195 | |||
196 | /* PM_PREPWSTST_IVA2 specific bits */ | ||
197 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10 | ||
198 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) | 66 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) |
199 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8 | ||
200 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) | 67 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) |
201 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6 | ||
202 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6) | ||
203 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4 | ||
204 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) | ||
205 | |||
206 | /* PRM_IRQSTATUS_IVA2 specific bits */ | ||
207 | #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2) | ||
208 | #define OMAP3430_FORCEWKUP_ST_MASK (1 << 1) | ||
209 | |||
210 | /* PRM_IRQENABLE_IVA2 specific bits */ | ||
211 | #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2) | ||
212 | #define OMAP3430_FORCEWKUP_EN_MASK (1 << 1) | ||
213 | |||
214 | /* PRM_REVISION specific bits */ | ||
215 | |||
216 | /* PRM_SYSCONFIG specific bits */ | ||
217 | |||
218 | /* PRM_IRQSTATUS_MPU specific bits */ | ||
219 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 | 68 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 |
220 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) | ||
221 | #define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) | ||
222 | #define OMAP3430_VC_RAERR_ST_MASK (1 << 23) | ||
223 | #define OMAP3430_VC_SAERR_ST_MASK (1 << 22) | ||
224 | #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) | 69 | #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) |
225 | #define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20) | ||
226 | #define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19) | ||
227 | #define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18) | ||
228 | #define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17) | ||
229 | #define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16) | ||
230 | #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) | 70 | #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) |
231 | #define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14) | ||
232 | #define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13) | ||
233 | #define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12) | ||
234 | #define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11) | ||
235 | #define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10) | ||
236 | #define OMAP3430_IO_ST_MASK (1 << 9) | ||
237 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8) | ||
238 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 | 71 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 |
239 | #define OMAP3430_MPU_DPLL_ST_MASK (1 << 7) | ||
240 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 | 72 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 |
241 | #define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6) | ||
242 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 | 73 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 |
243 | #define OMAP3430_CORE_DPLL_ST_MASK (1 << 5) | ||
244 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 | 74 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 |
245 | #define OMAP3430_TRANSITION_ST_MASK (1 << 4) | ||
246 | #define OMAP3430_EVGENOFF_ST_MASK (1 << 3) | ||
247 | #define OMAP3430_EVGENON_ST_MASK (1 << 2) | ||
248 | #define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) | ||
249 | |||
250 | /* PRM_IRQENABLE_MPU specific bits */ | ||
251 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 | 75 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 |
252 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) | ||
253 | #define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) | ||
254 | #define OMAP3430_VC_RAERR_EN_MASK (1 << 23) | ||
255 | #define OMAP3430_VC_SAERR_EN_MASK (1 << 22) | ||
256 | #define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21) | ||
257 | #define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20) | ||
258 | #define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19) | ||
259 | #define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18) | ||
260 | #define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17) | ||
261 | #define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16) | ||
262 | #define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15) | ||
263 | #define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14) | ||
264 | #define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13) | ||
265 | #define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12) | ||
266 | #define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11) | ||
267 | #define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10) | ||
268 | #define OMAP3430_IO_EN_MASK (1 << 9) | ||
269 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8) | ||
270 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 | 76 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 |
271 | #define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7) | ||
272 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 | 77 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 |
273 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6) | ||
274 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 | 78 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 |
275 | #define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5) | ||
276 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 | 79 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 |
277 | #define OMAP3430_TRANSITION_EN_MASK (1 << 4) | ||
278 | #define OMAP3430_EVGENOFF_EN_MASK (1 << 3) | ||
279 | #define OMAP3430_EVGENON_EN_MASK (1 << 2) | ||
280 | #define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1) | ||
281 | |||
282 | /* RM_RSTST_MPU specific bits */ | ||
283 | #define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11) | ||
284 | |||
285 | /* PM_WKDEP_MPU specific bits */ | ||
286 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 | 80 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 |
287 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5) | ||
288 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 | 81 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 |
289 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2) | ||
290 | |||
291 | /* PM_EVGENCTRL_MPU */ | ||
292 | #define OMAP3430_OFFLOADMODE_SHIFT 3 | ||
293 | #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) | ||
294 | #define OMAP3430_ONLOADMODE_SHIFT 1 | ||
295 | #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) | ||
296 | #define OMAP3430_ENABLE_MASK (1 << 0) | ||
297 | |||
298 | /* PM_EVGENONTIM_MPU */ | ||
299 | #define OMAP3430_ONTIMEVAL_SHIFT 0 | ||
300 | #define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0) | ||
301 | |||
302 | /* PM_EVGENOFFTIM_MPU */ | ||
303 | #define OMAP3430_OFFTIMEVAL_SHIFT 0 | ||
304 | #define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0) | ||
305 | |||
306 | /* PM_PWSTCTRL_MPU specific bits */ | ||
307 | #define OMAP3430_L2CACHEONSTATE_SHIFT 16 | ||
308 | #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) | ||
309 | #define OMAP3430_L2CACHERETSTATE_MASK (1 << 8) | ||
310 | #define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2) | ||
311 | |||
312 | /* PM_PWSTST_MPU specific bits */ | ||
313 | #define OMAP3430_L2CACHESTATEST_SHIFT 6 | ||
314 | #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) | ||
315 | #define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2) | ||
316 | |||
317 | /* PM_PREPWSTST_MPU specific bits */ | ||
318 | #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 | ||
319 | #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) | ||
320 | #define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2) | ||
321 | |||
322 | /* RM_RSTCTRL_CORE */ | ||
323 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) | 82 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) |
324 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) | 83 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) |
325 | |||
326 | /* RM_RSTST_CORE specific bits */ | ||
327 | #define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10) | ||
328 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9) | ||
329 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8) | ||
330 | |||
331 | /* PM_WKEN1_CORE specific bits */ | ||
332 | |||
333 | /* PM_MPUGRPSEL1_CORE specific bits */ | ||
334 | #define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5) | ||
335 | |||
336 | /* PM_IVA2GRPSEL1_CORE specific bits */ | ||
337 | |||
338 | /* PM_WKST1_CORE specific bits */ | ||
339 | |||
340 | /* PM_PWSTCTRL_CORE specific bits */ | ||
341 | #define OMAP3430_MEM2ONSTATE_SHIFT 18 | ||
342 | #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) | ||
343 | #define OMAP3430_MEM1ONSTATE_SHIFT 16 | ||
344 | #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) | ||
345 | #define OMAP3430_MEM2RETSTATE_MASK (1 << 9) | ||
346 | #define OMAP3430_MEM1RETSTATE_MASK (1 << 8) | ||
347 | |||
348 | /* PM_PWSTST_CORE specific bits */ | ||
349 | #define OMAP3430_MEM2STATEST_SHIFT 6 | ||
350 | #define OMAP3430_MEM2STATEST_MASK (0x3 << 6) | ||
351 | #define OMAP3430_MEM1STATEST_SHIFT 4 | ||
352 | #define OMAP3430_MEM1STATEST_MASK (0x3 << 4) | ||
353 | |||
354 | /* PM_PREPWSTST_CORE specific bits */ | ||
355 | #define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6 | ||
356 | #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) | 84 | #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) |
357 | #define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4 | ||
358 | #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) | 85 | #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) |
359 | |||
360 | /* RM_RSTST_GFX specific bits */ | ||
361 | |||
362 | /* PM_WKDEP_GFX specific bits */ | ||
363 | #define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2) | ||
364 | |||
365 | /* PM_PWSTCTRL_GFX specific bits */ | ||
366 | |||
367 | /* PM_PWSTST_GFX specific bits */ | ||
368 | |||
369 | /* PM_PREPWSTST_GFX specific bits */ | ||
370 | |||
371 | /* PM_WKEN_WKUP specific bits */ | ||
372 | #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) | 86 | #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) |
373 | #define OMAP3430_EN_IO_MASK (1 << 8) | 87 | #define OMAP3430_EN_IO_MASK (1 << 8) |
374 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) | 88 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) |
375 | |||
376 | /* PM_MPUGRPSEL_WKUP specific bits */ | ||
377 | |||
378 | /* PM_IVA2GRPSEL_WKUP specific bits */ | ||
379 | |||
380 | /* PM_WKST_WKUP specific bits */ | ||
381 | #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) | 89 | #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) |
382 | #define OMAP3430_ST_IO_MASK (1 << 8) | 90 | #define OMAP3430_ST_IO_MASK (1 << 8) |
383 | |||
384 | /* PRM_CLKSEL */ | ||
385 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 | 91 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 |
386 | #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) | ||
387 | #define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 | 92 | #define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 |
388 | |||
389 | /* PRM_CLKOUT_CTRL */ | ||
390 | #define OMAP3430_CLKOUT_EN_MASK (1 << 7) | ||
391 | #define OMAP3430_CLKOUT_EN_SHIFT 7 | 93 | #define OMAP3430_CLKOUT_EN_SHIFT 7 |
392 | |||
393 | /* RM_RSTST_DSS specific bits */ | ||
394 | |||
395 | /* PM_WKEN_DSS */ | ||
396 | #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) | 94 | #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) |
397 | |||
398 | /* PM_WKDEP_DSS specific bits */ | ||
399 | #define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2) | ||
400 | |||
401 | /* PM_PWSTCTRL_DSS specific bits */ | ||
402 | |||
403 | /* PM_PWSTST_DSS specific bits */ | ||
404 | |||
405 | /* PM_PREPWSTST_DSS specific bits */ | ||
406 | |||
407 | /* RM_RSTST_CAM specific bits */ | ||
408 | |||
409 | /* PM_WKDEP_CAM specific bits */ | ||
410 | #define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2) | ||
411 | |||
412 | /* PM_PWSTCTRL_CAM specific bits */ | ||
413 | |||
414 | /* PM_PWSTST_CAM specific bits */ | ||
415 | |||
416 | /* PM_PREPWSTST_CAM specific bits */ | ||
417 | |||
418 | /* PM_PWSTCTRL_USBHOST specific bits */ | ||
419 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 | 95 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 |
420 | |||
421 | /* RM_RSTST_PER specific bits */ | ||
422 | |||
423 | /* PM_WKEN_PER specific bits */ | ||
424 | |||
425 | /* PM_MPUGRPSEL_PER specific bits */ | ||
426 | |||
427 | /* PM_IVA2GRPSEL_PER specific bits */ | ||
428 | |||
429 | /* PM_WKST_PER specific bits */ | ||
430 | |||
431 | /* PM_WKDEP_PER specific bits */ | ||
432 | #define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2) | ||
433 | |||
434 | /* PM_PWSTCTRL_PER specific bits */ | ||
435 | |||
436 | /* PM_PWSTST_PER specific bits */ | ||
437 | |||
438 | /* PM_PREPWSTST_PER specific bits */ | ||
439 | |||
440 | /* RM_RSTST_EMU specific bits */ | ||
441 | |||
442 | /* PM_PWSTST_EMU specific bits */ | ||
443 | |||
444 | /* PRM_VC_SMPS_SA */ | ||
445 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 | 96 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 |
446 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) | 97 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) |
447 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 | 98 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 |
448 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) | 99 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) |
449 | |||
450 | /* PRM_VC_SMPS_VOL_RA */ | ||
451 | #define OMAP3430_VOLRA1_SHIFT 16 | ||
452 | #define OMAP3430_VOLRA1_MASK (0xff << 16) | 100 | #define OMAP3430_VOLRA1_MASK (0xff << 16) |
453 | #define OMAP3430_VOLRA0_SHIFT 0 | ||
454 | #define OMAP3430_VOLRA0_MASK (0xff << 0) | 101 | #define OMAP3430_VOLRA0_MASK (0xff << 0) |
455 | |||
456 | /* PRM_VC_SMPS_CMD_RA */ | ||
457 | #define OMAP3430_CMDRA1_SHIFT 16 | ||
458 | #define OMAP3430_CMDRA1_MASK (0xff << 16) | 102 | #define OMAP3430_CMDRA1_MASK (0xff << 16) |
459 | #define OMAP3430_CMDRA0_SHIFT 0 | ||
460 | #define OMAP3430_CMDRA0_MASK (0xff << 0) | 103 | #define OMAP3430_CMDRA0_MASK (0xff << 0) |
461 | |||
462 | /* PRM_VC_CMD_VAL_0 specific bits */ | ||
463 | #define OMAP3430_VC_CMD_ON_SHIFT 24 | 104 | #define OMAP3430_VC_CMD_ON_SHIFT 24 |
464 | #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) | 105 | #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) |
465 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 | 106 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 |
466 | #define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16) | ||
467 | #define OMAP3430_VC_CMD_RET_SHIFT 8 | 107 | #define OMAP3430_VC_CMD_RET_SHIFT 8 |
468 | #define OMAP3430_VC_CMD_RET_MASK (0xFF << 8) | ||
469 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 | 108 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 |
470 | #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) | ||
471 | |||
472 | /* PRM_VC_CMD_VAL_1 specific bits */ | ||
473 | |||
474 | /* PRM_VC_CH_CONF */ | ||
475 | #define OMAP3430_CMD1_MASK (1 << 20) | ||
476 | #define OMAP3430_RACEN1_MASK (1 << 19) | ||
477 | #define OMAP3430_RAC1_MASK (1 << 18) | ||
478 | #define OMAP3430_RAV1_MASK (1 << 17) | ||
479 | #define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16) | ||
480 | #define OMAP3430_CMD0_MASK (1 << 4) | ||
481 | #define OMAP3430_RACEN0_MASK (1 << 3) | ||
482 | #define OMAP3430_RAC0_MASK (1 << 2) | ||
483 | #define OMAP3430_RAV0_MASK (1 << 1) | ||
484 | #define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0) | ||
485 | |||
486 | /* PRM_VC_I2C_CFG */ | ||
487 | #define OMAP3430_HSMASTER_MASK (1 << 5) | ||
488 | #define OMAP3430_SREN_MASK (1 << 4) | ||
489 | #define OMAP3430_HSEN_MASK (1 << 3) | 109 | #define OMAP3430_HSEN_MASK (1 << 3) |
490 | #define OMAP3430_MCODE_SHIFT 0 | ||
491 | #define OMAP3430_MCODE_MASK (0x7 << 0) | 110 | #define OMAP3430_MCODE_MASK (0x7 << 0) |
492 | |||
493 | /* PRM_VC_BYPASS_VAL */ | ||
494 | #define OMAP3430_VALID_MASK (1 << 24) | 111 | #define OMAP3430_VALID_MASK (1 << 24) |
495 | #define OMAP3430_DATA_SHIFT 16 | 112 | #define OMAP3430_DATA_SHIFT 16 |
496 | #define OMAP3430_DATA_MASK (0xff << 16) | ||
497 | #define OMAP3430_REGADDR_SHIFT 8 | 113 | #define OMAP3430_REGADDR_SHIFT 8 |
498 | #define OMAP3430_REGADDR_MASK (0xff << 8) | ||
499 | #define OMAP3430_SLAVEADDR_SHIFT 0 | 114 | #define OMAP3430_SLAVEADDR_SHIFT 0 |
500 | #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) | ||
501 | |||
502 | /* PRM_RSTCTRL */ | ||
503 | #define OMAP3430_RST_DPLL3_MASK (1 << 2) | ||
504 | #define OMAP3430_RST_GS_MASK (1 << 1) | ||
505 | |||
506 | /* PRM_RSTTIME */ | ||
507 | #define OMAP3430_RSTTIME2_SHIFT 8 | ||
508 | #define OMAP3430_RSTTIME2_MASK (0x1f << 8) | ||
509 | #define OMAP3430_RSTTIME1_SHIFT 0 | ||
510 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) | ||
511 | |||
512 | /* PRM_RSTST */ | ||
513 | #define OMAP3430_ICECRUSHER_RST_SHIFT 10 | 115 | #define OMAP3430_ICECRUSHER_RST_SHIFT 10 |
514 | #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) | ||
515 | #define OMAP3430_ICEPICK_RST_SHIFT 9 | 116 | #define OMAP3430_ICEPICK_RST_SHIFT 9 |
516 | #define OMAP3430_ICEPICK_RST_MASK (1 << 9) | ||
517 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 | 117 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 |
518 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) | ||
519 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 | 118 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 |
520 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) | ||
521 | #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 | 119 | #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 |
522 | #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) | ||
523 | #define OMAP3430_SECURE_WD_RST_SHIFT 5 | 120 | #define OMAP3430_SECURE_WD_RST_SHIFT 5 |
524 | #define OMAP3430_SECURE_WD_RST_MASK (1 << 5) | ||
525 | #define OMAP3430_MPU_WD_RST_SHIFT 4 | 121 | #define OMAP3430_MPU_WD_RST_SHIFT 4 |
526 | #define OMAP3430_MPU_WD_RST_MASK (1 << 4) | ||
527 | #define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 | 122 | #define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 |
528 | #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) | ||
529 | #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 | 123 | #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 |
530 | #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) | ||
531 | #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 | 124 | #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 |
532 | #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) | 125 | #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) |
533 | |||
534 | /* PRM_VOLTCTRL */ | ||
535 | #define OMAP3430_SEL_VMODE_MASK (1 << 4) | ||
536 | #define OMAP3430_SEL_OFF_MASK (1 << 3) | 126 | #define OMAP3430_SEL_OFF_MASK (1 << 3) |
537 | #define OMAP3430_AUTO_OFF_MASK (1 << 2) | 127 | #define OMAP3430_AUTO_OFF_MASK (1 << 2) |
538 | #define OMAP3430_AUTO_RET_MASK (1 << 1) | ||
539 | #define OMAP3430_AUTO_SLEEP_MASK (1 << 0) | ||
540 | |||
541 | /* PRM_SRAM_PCHARGE */ | ||
542 | #define OMAP3430_PCHARGE_TIME_SHIFT 0 | ||
543 | #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) | ||
544 | |||
545 | /* PRM_CLKSRC_CTRL */ | ||
546 | #define OMAP3430_SYSCLKDIV_SHIFT 6 | ||
547 | #define OMAP3430_SYSCLKDIV_MASK (0x3 << 6) | ||
548 | #define OMAP3430_AUTOEXTCLKMODE_SHIFT 3 | ||
549 | #define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3) | ||
550 | #define OMAP3430_SYSCLKSEL_SHIFT 0 | ||
551 | #define OMAP3430_SYSCLKSEL_MASK (0x3 << 0) | ||
552 | |||
553 | /* PRM_VOLTSETUP1 */ | ||
554 | #define OMAP3430_SETUP_TIME2_SHIFT 16 | ||
555 | #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) | 128 | #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) |
556 | #define OMAP3430_SETUP_TIME1_SHIFT 0 | ||
557 | #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) | 129 | #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) |
558 | |||
559 | /* PRM_VOLTOFFSET */ | ||
560 | #define OMAP3430_OFFSET_TIME_SHIFT 0 | ||
561 | #define OMAP3430_OFFSET_TIME_MASK (0xffff << 0) | ||
562 | |||
563 | /* PRM_CLKSETUP */ | ||
564 | #define OMAP3430_SETUP_TIME_SHIFT 0 | ||
565 | #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) | ||
566 | |||
567 | /* PRM_POLCTRL */ | ||
568 | #define OMAP3430_OFFMODE_POL_MASK (1 << 3) | ||
569 | #define OMAP3430_CLKOUT_POL_MASK (1 << 2) | ||
570 | #define OMAP3430_CLKREQ_POL_MASK (1 << 1) | ||
571 | #define OMAP3430_EXTVOL_POL_MASK (1 << 0) | ||
572 | |||
573 | /* PRM_VOLTSETUP2 */ | ||
574 | #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 | ||
575 | #define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0) | ||
576 | |||
577 | /* PRM_VP1_CONFIG specific bits */ | ||
578 | |||
579 | /* PRM_VP1_VSTEPMIN specific bits */ | ||
580 | |||
581 | /* PRM_VP1_VSTEPMAX specific bits */ | ||
582 | |||
583 | /* PRM_VP1_VLIMITTO specific bits */ | ||
584 | |||
585 | /* PRM_VP1_VOLTAGE specific bits */ | ||
586 | |||
587 | /* PRM_VP1_STATUS specific bits */ | ||
588 | |||
589 | /* PRM_VP2_CONFIG specific bits */ | ||
590 | |||
591 | /* PRM_VP2_VSTEPMIN specific bits */ | ||
592 | |||
593 | /* PRM_VP2_VSTEPMAX specific bits */ | ||
594 | |||
595 | /* PRM_VP2_VLIMITTO specific bits */ | ||
596 | |||
597 | /* PRM_VP2_VOLTAGE specific bits */ | ||
598 | |||
599 | /* PRM_VP2_STATUS specific bits */ | ||
600 | |||
601 | /* RM_RSTST_NEON specific bits */ | ||
602 | |||
603 | /* PM_WKDEP_NEON specific bits */ | ||
604 | |||
605 | /* PM_PWSTCTRL_NEON specific bits */ | ||
606 | |||
607 | /* PM_PWSTST_NEON specific bits */ | ||
608 | |||
609 | /* PM_PREPWSTST_NEON specific bits */ | ||
610 | |||
611 | #endif | 130 | #endif |
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 3cb247bebdaa..b1c7a33e00e7 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h | |||
@@ -22,2306 +22,80 @@ | |||
22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H |
23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | 23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H |
24 | 24 | ||
25 | |||
26 | /* | ||
27 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
28 | * PRM_LDO_SRAM_MPU_SETUP | ||
29 | */ | ||
30 | #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 | ||
31 | #define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) | ||
32 | |||
33 | /* | ||
34 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
35 | * PRM_LDO_SRAM_MPU_SETUP | ||
36 | */ | ||
37 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 | ||
38 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) | ||
39 | |||
40 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
41 | #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 | ||
42 | #define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) | ||
43 | |||
44 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
45 | #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 | ||
46 | #define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) | ||
47 | |||
48 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
49 | #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 | ||
50 | #define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) | ||
51 | |||
52 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
53 | #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 | ||
54 | #define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) | ||
55 | |||
56 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
57 | #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 | ||
58 | #define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) | ||
59 | |||
60 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
61 | #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 | ||
62 | #define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) | ||
63 | |||
64 | /* Used by PM_ABE_PWRSTCTRL */ | ||
65 | #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 | ||
66 | #define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) | ||
67 | |||
68 | /* Used by PM_ABE_PWRSTCTRL */ | ||
69 | #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 | ||
70 | #define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) | ||
71 | |||
72 | /* Used by PM_ABE_PWRSTST */ | ||
73 | #define OMAP4430_AESSMEM_STATEST_SHIFT 4 | ||
74 | #define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) | ||
75 | |||
76 | /* | ||
77 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
78 | * PRM_LDO_SRAM_MPU_SETUP | ||
79 | */ | ||
80 | #define OMAP4430_AIPOFF_SHIFT 8 | ||
81 | #define OMAP4430_AIPOFF_MASK (1 << 8) | ||
82 | |||
83 | /* Used by PRM_VOLTCTRL */ | ||
84 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 | ||
85 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) | ||
86 | |||
87 | /* Used by PRM_VOLTCTRL */ | ||
88 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 | ||
89 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) | ||
90 | |||
91 | /* Used by PRM_VOLTCTRL */ | ||
92 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 | ||
93 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) | ||
94 | |||
95 | /* Used by PRM_VC_ERRST */ | ||
96 | #define OMAP4430_BYPS_RA_ERR_SHIFT 25 | ||
97 | #define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) | ||
98 | |||
99 | /* Used by PRM_VC_ERRST */ | ||
100 | #define OMAP4430_BYPS_SA_ERR_SHIFT 24 | ||
101 | #define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) | ||
102 | |||
103 | /* Used by PRM_VC_ERRST */ | ||
104 | #define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 | ||
105 | #define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) | ||
106 | |||
107 | /* Used by PRM_RSTST */ | ||
108 | #define OMAP4430_C2C_RST_SHIFT 10 | 25 | #define OMAP4430_C2C_RST_SHIFT 10 |
109 | #define OMAP4430_C2C_RST_MASK (1 << 10) | ||
110 | |||
111 | /* Used by PM_CAM_PWRSTCTRL */ | ||
112 | #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 | ||
113 | #define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) | ||
114 | |||
115 | /* Used by PM_CAM_PWRSTST */ | ||
116 | #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 | ||
117 | #define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) | ||
118 | |||
119 | /* Used by PRM_CLKREQCTRL */ | ||
120 | #define OMAP4430_CLKREQ_COND_SHIFT 0 | ||
121 | #define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) | ||
122 | |||
123 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
124 | #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 | ||
125 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) | 26 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) |
126 | |||
127 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
128 | #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 | ||
129 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) | 27 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) |
130 | |||
131 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
132 | #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 | ||
133 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) | 28 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) |
134 | |||
135 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
136 | #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 | ||
137 | #define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) | ||
138 | |||
139 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
140 | #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 | ||
141 | #define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) | ||
142 | |||
143 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
144 | #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 | ||
145 | #define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) | ||
146 | |||
147 | /* Used by PM_CORE_PWRSTCTRL */ | ||
148 | #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 | ||
149 | #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) | ||
150 | |||
151 | /* Used by PM_CORE_PWRSTCTRL */ | ||
152 | #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 | ||
153 | #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) | ||
154 | |||
155 | /* Used by PM_CORE_PWRSTST */ | ||
156 | #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 | ||
157 | #define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) | ||
158 | |||
159 | /* Used by PM_CORE_PWRSTCTRL */ | ||
160 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 | ||
161 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) | ||
162 | |||
163 | /* Used by PM_CORE_PWRSTCTRL */ | ||
164 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 | ||
165 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) | ||
166 | |||
167 | /* Used by PM_CORE_PWRSTST */ | ||
168 | #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 | ||
169 | #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) | ||
170 | |||
171 | /* Used by REVISION_PRM */ | ||
172 | #define OMAP4430_CUSTOM_SHIFT 6 | ||
173 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) | ||
174 | |||
175 | /* Used by PRM_VC_VAL_BYPASS */ | ||
176 | #define OMAP4430_DATA_SHIFT 16 | 29 | #define OMAP4430_DATA_SHIFT 16 |
177 | #define OMAP4430_DATA_MASK (0xff << 16) | ||
178 | |||
179 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
180 | #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 | ||
181 | #define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) | ||
182 | |||
183 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
184 | #define OMAP4430_DFILTEREN_SHIFT 6 | ||
185 | #define OMAP4430_DFILTEREN_MASK (1 << 6) | ||
186 | |||
187 | /* | ||
188 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
189 | * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP | ||
190 | */ | ||
191 | #define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 | ||
192 | #define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) | ||
193 | |||
194 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | ||
195 | #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 | ||
196 | #define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) | ||
197 | |||
198 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | ||
199 | #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 | ||
200 | #define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) | ||
201 | |||
202 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
203 | #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 | ||
204 | #define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) | ||
205 | |||
206 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
207 | #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 | ||
208 | #define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) | ||
209 | |||
210 | /* Used by PRM_IRQENABLE_MPU */ | ||
211 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 | ||
212 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) | ||
213 | |||
214 | /* Used by PRM_IRQSTATUS_MPU */ | ||
215 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 | ||
216 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) | ||
217 | |||
218 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | ||
219 | #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 | ||
220 | #define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) | ||
221 | |||
222 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | ||
223 | #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 | ||
224 | #define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) | ||
225 | |||
226 | /* Used by PRM_IRQENABLE_MPU */ | ||
227 | #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 | ||
228 | #define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) | ||
229 | |||
230 | /* Used by PRM_IRQSTATUS_MPU */ | ||
231 | #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 | ||
232 | #define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) | ||
233 | |||
234 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
235 | #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 | ||
236 | #define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) | ||
237 | |||
238 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
239 | #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 | ||
240 | #define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) | ||
241 | |||
242 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
243 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 | ||
244 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) | ||
245 | |||
246 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
247 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 | ||
248 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) | ||
249 | |||
250 | /* Used by PM_DSS_PWRSTCTRL */ | ||
251 | #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 | ||
252 | #define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) | ||
253 | |||
254 | /* Used by PM_DSS_PWRSTCTRL */ | ||
255 | #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 | ||
256 | #define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) | ||
257 | |||
258 | /* Used by PM_DSS_PWRSTST */ | ||
259 | #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 | ||
260 | #define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) | ||
261 | |||
262 | /* Used by PM_CORE_PWRSTCTRL */ | ||
263 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 | ||
264 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) | ||
265 | |||
266 | /* Used by PM_CORE_PWRSTCTRL */ | ||
267 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 | ||
268 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) | ||
269 | |||
270 | /* Used by PM_CORE_PWRSTST */ | ||
271 | #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 | ||
272 | #define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) | ||
273 | |||
274 | /* Used by PM_CORE_PWRSTCTRL */ | ||
275 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 | ||
276 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) | ||
277 | |||
278 | /* Used by PM_CORE_PWRSTCTRL */ | ||
279 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 | ||
280 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) | ||
281 | |||
282 | /* Used by PM_CORE_PWRSTST */ | ||
283 | #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 | ||
284 | #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) | ||
285 | |||
286 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
287 | #define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8 | ||
288 | #define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) | ||
289 | |||
290 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
291 | #define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9 | ||
292 | #define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) | ||
293 | |||
294 | /* Used by RM_MPU_RSTST */ | ||
295 | #define OMAP4430_EMULATION_RST_SHIFT 0 | ||
296 | #define OMAP4430_EMULATION_RST_MASK (1 << 0) | ||
297 | |||
298 | /* Used by RM_DUCATI_RSTST */ | ||
299 | #define OMAP4430_EMULATION_RST1ST_SHIFT 3 | ||
300 | #define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) | ||
301 | |||
302 | /* Used by RM_DUCATI_RSTST */ | ||
303 | #define OMAP4430_EMULATION_RST2ST_SHIFT 4 | ||
304 | #define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) | ||
305 | |||
306 | /* Used by RM_IVAHD_RSTST */ | ||
307 | #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 | ||
308 | #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) | ||
309 | |||
310 | /* Used by RM_IVAHD_RSTST */ | ||
311 | #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 | ||
312 | #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) | ||
313 | |||
314 | /* Used by PM_EMU_PWRSTCTRL */ | ||
315 | #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 | ||
316 | #define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) | ||
317 | |||
318 | /* Used by PM_EMU_PWRSTST */ | ||
319 | #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 | ||
320 | #define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) | ||
321 | |||
322 | /* | ||
323 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
324 | * PRM_LDO_SRAM_MPU_SETUP | ||
325 | */ | ||
326 | #define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 | ||
327 | #define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) | ||
328 | |||
329 | /* | ||
330 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
331 | * PRM_LDO_SRAM_MPU_SETUP | ||
332 | */ | ||
333 | #define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 | ||
334 | #define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) | ||
335 | |||
336 | /* | ||
337 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
338 | * PRM_LDO_SRAM_MPU_SETUP | ||
339 | */ | ||
340 | #define OMAP4430_ENFUNC4_SHIFT 6 | ||
341 | #define OMAP4430_ENFUNC4_MASK (1 << 6) | ||
342 | |||
343 | /* | ||
344 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
345 | * PRM_LDO_SRAM_MPU_SETUP | ||
346 | */ | ||
347 | #define OMAP4430_ENFUNC5_SHIFT 7 | ||
348 | #define OMAP4430_ENFUNC5_MASK (1 << 7) | ||
349 | |||
350 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
351 | #define OMAP4430_ERRORGAIN_SHIFT 16 | ||
352 | #define OMAP4430_ERRORGAIN_MASK (0xff << 16) | 30 | #define OMAP4430_ERRORGAIN_MASK (0xff << 16) |
353 | |||
354 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
355 | #define OMAP4430_ERROROFFSET_SHIFT 24 | ||
356 | #define OMAP4430_ERROROFFSET_MASK (0xff << 24) | 31 | #define OMAP4430_ERROROFFSET_MASK (0xff << 24) |
357 | |||
358 | /* Used by PRM_RSTST */ | ||
359 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 | 32 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 |
360 | #define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) | ||
361 | |||
362 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
363 | #define OMAP4430_FORCEUPDATE_SHIFT 1 | ||
364 | #define OMAP4430_FORCEUPDATE_MASK (1 << 1) | 33 | #define OMAP4430_FORCEUPDATE_MASK (1 << 1) |
365 | |||
366 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | ||
367 | #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 | ||
368 | #define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) | ||
369 | |||
370 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ | ||
371 | #define OMAP4430_FORCEWKUP_EN_SHIFT 10 | ||
372 | #define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) | ||
373 | |||
374 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ | ||
375 | #define OMAP4430_FORCEWKUP_ST_SHIFT 10 | ||
376 | #define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) | ||
377 | |||
378 | /* Used by REVISION_PRM */ | ||
379 | #define OMAP4430_FUNC_SHIFT 16 | ||
380 | #define OMAP4430_FUNC_MASK (0xfff << 16) | ||
381 | |||
382 | /* Used by PM_GFX_PWRSTCTRL */ | ||
383 | #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 | ||
384 | #define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) | ||
385 | |||
386 | /* Used by PM_GFX_PWRSTST */ | ||
387 | #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 | ||
388 | #define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) | ||
389 | |||
390 | /* Used by PRM_RSTST */ | ||
391 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 | 34 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 |
392 | #define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) | ||
393 | |||
394 | /* Used by PRM_RSTST */ | ||
395 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 | 35 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 |
396 | #define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) | ||
397 | |||
398 | /* Used by PRM_IO_PMCTRL */ | ||
399 | #define OMAP4430_GLOBAL_WUEN_SHIFT 16 | ||
400 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) | 36 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) |
401 | |||
402 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
403 | #define OMAP4430_HSMCODE_SHIFT 0 | ||
404 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) | 37 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) |
405 | |||
406 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
407 | #define OMAP4430_HSMODEEN_SHIFT 3 | ||
408 | #define OMAP4430_HSMODEEN_MASK (1 << 3) | 38 | #define OMAP4430_HSMODEEN_MASK (1 << 3) |
409 | |||
410 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
411 | #define OMAP4430_HSSCLH_SHIFT 16 | ||
412 | #define OMAP4430_HSSCLH_MASK (0xff << 16) | ||
413 | |||
414 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
415 | #define OMAP4430_HSSCLL_SHIFT 24 | 39 | #define OMAP4430_HSSCLL_SHIFT 24 |
416 | #define OMAP4430_HSSCLL_MASK (0xff << 24) | ||
417 | |||
418 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
419 | #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 | ||
420 | #define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) | ||
421 | |||
422 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
423 | #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 | ||
424 | #define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) | ||
425 | |||
426 | /* Used by PM_IVAHD_PWRSTST */ | ||
427 | #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 | ||
428 | #define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) | ||
429 | |||
430 | /* Used by RM_MPU_RSTST */ | ||
431 | #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 | ||
432 | #define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) | ||
433 | |||
434 | /* Used by RM_DUCATI_RSTST */ | ||
435 | #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 | ||
436 | #define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) | ||
437 | |||
438 | /* Used by RM_DUCATI_RSTST */ | ||
439 | #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 | ||
440 | #define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) | ||
441 | |||
442 | /* Used by RM_IVAHD_RSTST */ | ||
443 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 | ||
444 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) | ||
445 | |||
446 | /* Used by RM_IVAHD_RSTST */ | ||
447 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 | ||
448 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) | ||
449 | |||
450 | /* Used by PRM_RSTST */ | ||
451 | #define OMAP4430_ICEPICK_RST_SHIFT 9 | 40 | #define OMAP4430_ICEPICK_RST_SHIFT 9 |
452 | #define OMAP4430_ICEPICK_RST_MASK (1 << 9) | ||
453 | |||
454 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
455 | #define OMAP4430_INITVDD_SHIFT 2 | ||
456 | #define OMAP4430_INITVDD_MASK (1 << 2) | 41 | #define OMAP4430_INITVDD_MASK (1 << 2) |
457 | |||
458 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
459 | #define OMAP4430_INITVOLTAGE_SHIFT 8 | ||
460 | #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) | 42 | #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) |
461 | |||
462 | /* | ||
463 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, | ||
464 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | ||
465 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
466 | */ | ||
467 | #define OMAP4430_INTRANSITION_SHIFT 20 | ||
468 | #define OMAP4430_INTRANSITION_MASK (1 << 20) | ||
469 | |||
470 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
471 | #define OMAP4430_IO_EN_SHIFT 9 | ||
472 | #define OMAP4430_IO_EN_MASK (1 << 9) | ||
473 | |||
474 | /* Used by PRM_IO_PMCTRL */ | ||
475 | #define OMAP4430_IO_ON_STATUS_SHIFT 5 | ||
476 | #define OMAP4430_IO_ON_STATUS_MASK (1 << 5) | ||
477 | |||
478 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
479 | #define OMAP4430_IO_ST_SHIFT 9 | ||
480 | #define OMAP4430_IO_ST_MASK (1 << 9) | ||
481 | |||
482 | /* Used by PRM_IO_PMCTRL */ | ||
483 | #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 | ||
484 | #define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) | ||
485 | |||
486 | /* Used by PRM_IO_PMCTRL */ | ||
487 | #define OMAP4430_ISOCLK_STATUS_SHIFT 1 | ||
488 | #define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) | ||
489 | |||
490 | /* Used by PRM_IO_PMCTRL */ | ||
491 | #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 | ||
492 | #define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) | ||
493 | |||
494 | /* Used by PRM_IO_COUNT */ | ||
495 | #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 | ||
496 | #define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) | ||
497 | |||
498 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
499 | #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 | ||
500 | #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) | ||
501 | |||
502 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
503 | #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 | ||
504 | #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) | ||
505 | |||
506 | /* Used by PM_L3INIT_PWRSTST */ | ||
507 | #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 | ||
508 | #define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) | ||
509 | |||
510 | /* | ||
511 | * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, | ||
512 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
513 | */ | ||
514 | #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 | 43 | #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 |
515 | #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | 44 | #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) |
516 | |||
517 | /* | ||
518 | * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, | ||
519 | * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | ||
520 | * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | ||
521 | */ | ||
522 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 | 45 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 |
523 | #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) | 46 | #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) |
524 | |||
525 | /* | ||
526 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, | ||
527 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | ||
528 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
529 | */ | ||
530 | #define OMAP4430_LOGICSTATEST_SHIFT 2 | 47 | #define OMAP4430_LOGICSTATEST_SHIFT 2 |
531 | #define OMAP4430_LOGICSTATEST_MASK (1 << 2) | 48 | #define OMAP4430_LOGICSTATEST_MASK (1 << 2) |
532 | |||
533 | /* | ||
534 | * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, | ||
535 | * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, | ||
536 | * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, | ||
537 | * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, | ||
538 | * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, | ||
539 | * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, | ||
540 | * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, | ||
541 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, | ||
542 | * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, | ||
543 | * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, | ||
544 | * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, | ||
545 | * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | ||
546 | * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, | ||
547 | * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, | ||
548 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, | ||
549 | * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, | ||
550 | * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, | ||
551 | * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, | ||
552 | * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, | ||
553 | * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, | ||
554 | * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, | ||
555 | * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, | ||
556 | * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, | ||
557 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, | ||
558 | * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, | ||
559 | * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, | ||
560 | * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, | ||
561 | * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, | ||
562 | * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, | ||
563 | * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, | ||
564 | * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, | ||
565 | * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, | ||
566 | * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, | ||
567 | * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT | ||
568 | */ | ||
569 | #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 | ||
570 | #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) | 49 | #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) |
571 | |||
572 | /* | ||
573 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, | ||
574 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, | ||
575 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | ||
576 | * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, | ||
577 | * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, | ||
578 | * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, | ||
579 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, | ||
580 | * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, | ||
581 | * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, | ||
582 | * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, | ||
583 | * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, | ||
584 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, | ||
585 | * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, | ||
586 | * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, | ||
587 | * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, | ||
588 | * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, | ||
589 | * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT | ||
590 | */ | ||
591 | #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 | ||
592 | #define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) | ||
593 | |||
594 | /* Used by RM_ABE_AESS_CONTEXT */ | ||
595 | #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 | ||
596 | #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) | 50 | #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) |
597 | |||
598 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ | ||
599 | #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 | ||
600 | #define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) | ||
601 | |||
602 | /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ | ||
603 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 | ||
604 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) | ||
605 | |||
606 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ | ||
607 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 | ||
608 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) | ||
609 | |||
610 | /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ | ||
611 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 | ||
612 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) | ||
613 | |||
614 | /* | ||
615 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, | ||
616 | * RM_SDMA_SDMA_CONTEXT | ||
617 | */ | ||
618 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 | ||
619 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) | ||
620 | |||
621 | /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ | ||
622 | #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 | ||
623 | #define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) | ||
624 | |||
625 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | ||
626 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 | ||
627 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) | ||
628 | |||
629 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | ||
630 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 | ||
631 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) | ||
632 | |||
633 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ | ||
634 | #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 | ||
635 | #define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) | ||
636 | |||
637 | /* Used by RM_GFX_GFX_CONTEXT */ | ||
638 | #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 | ||
639 | #define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) | ||
640 | |||
641 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
642 | #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 | ||
643 | #define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) | ||
644 | |||
645 | /* | ||
646 | * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, | ||
647 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | ||
648 | * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, | ||
649 | * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | ||
650 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT | ||
651 | */ | ||
652 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 | ||
653 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) | ||
654 | |||
655 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
656 | #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 | ||
657 | #define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) | ||
658 | |||
659 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
660 | #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 | ||
661 | #define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) | ||
662 | |||
663 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
664 | #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 | ||
665 | #define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) | ||
666 | |||
667 | /* | ||
668 | * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, | ||
669 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, | ||
670 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT | ||
671 | */ | ||
672 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 | ||
673 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) | ||
674 | |||
675 | /* | ||
676 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, | ||
677 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT | ||
678 | */ | ||
679 | #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 | ||
680 | #define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) | ||
681 | |||
682 | /* | ||
683 | * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, | ||
684 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, | ||
685 | * RM_L4SEC_CRYPTODMA_CONTEXT | ||
686 | */ | ||
687 | #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 | ||
688 | #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) | ||
689 | |||
690 | /* Used by RM_IVAHD_SL2_CONTEXT */ | ||
691 | #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 | ||
692 | #define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) | ||
693 | |||
694 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
695 | #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 | ||
696 | #define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) | ||
697 | |||
698 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
699 | #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 | ||
700 | #define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) | ||
701 | |||
702 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
703 | #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 | ||
704 | #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) | ||
705 | |||
706 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
707 | #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 | ||
708 | #define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) | ||
709 | |||
710 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
711 | #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 | ||
712 | #define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) | ||
713 | |||
714 | /* Used by RM_WKUP_SARRAM_CONTEXT */ | ||
715 | #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 | ||
716 | #define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) | ||
717 | |||
718 | /* | ||
719 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, | ||
720 | * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, | ||
721 | * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | ||
722 | */ | ||
723 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 | 51 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 |
724 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) | 52 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) |
725 | |||
726 | /* Used by PRM_MODEM_IF_CTRL */ | ||
727 | #define OMAP4430_MODEM_READY_SHIFT 1 | ||
728 | #define OMAP4430_MODEM_READY_MASK (1 << 1) | ||
729 | |||
730 | /* Used by PRM_MODEM_IF_CTRL */ | ||
731 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 | ||
732 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) | ||
733 | |||
734 | /* Used by PRM_MODEM_IF_CTRL */ | ||
735 | #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 | ||
736 | #define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) | ||
737 | |||
738 | /* Used by PRM_MODEM_IF_CTRL */ | ||
739 | #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 | ||
740 | #define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) | ||
741 | |||
742 | /* Used by PM_MPU_PWRSTCTRL */ | ||
743 | #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 | ||
744 | #define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) | ||
745 | |||
746 | /* Used by PM_MPU_PWRSTCTRL */ | ||
747 | #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 | ||
748 | #define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) | ||
749 | |||
750 | /* Used by PM_MPU_PWRSTST */ | ||
751 | #define OMAP4430_MPU_L1_STATEST_SHIFT 4 | ||
752 | #define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) | ||
753 | |||
754 | /* Used by PM_MPU_PWRSTCTRL */ | ||
755 | #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 | ||
756 | #define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) | ||
757 | |||
758 | /* Used by PM_MPU_PWRSTCTRL */ | ||
759 | #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 | ||
760 | #define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) | ||
761 | |||
762 | /* Used by PM_MPU_PWRSTST */ | ||
763 | #define OMAP4430_MPU_L2_STATEST_SHIFT 6 | ||
764 | #define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) | ||
765 | |||
766 | /* Used by PM_MPU_PWRSTCTRL */ | ||
767 | #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 | ||
768 | #define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) | ||
769 | |||
770 | /* Used by PM_MPU_PWRSTCTRL */ | ||
771 | #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 | ||
772 | #define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) | ||
773 | |||
774 | /* Used by PM_MPU_PWRSTST */ | ||
775 | #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 | ||
776 | #define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) | ||
777 | |||
778 | /* Used by PRM_RSTST */ | ||
779 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 | 53 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 |
780 | #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) | ||
781 | |||
782 | /* Used by PRM_RSTST */ | ||
783 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 | 54 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 |
784 | #define OMAP4430_MPU_WDT_RST_MASK (1 << 3) | ||
785 | |||
786 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
787 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 | ||
788 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) | ||
789 | |||
790 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
791 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 | ||
792 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) | ||
793 | |||
794 | /* Used by PM_L4PER_PWRSTST */ | ||
795 | #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 | ||
796 | #define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) | ||
797 | |||
798 | /* Used by PM_CORE_PWRSTCTRL */ | ||
799 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 | ||
800 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) | 55 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) |
801 | |||
802 | /* Used by PM_CORE_PWRSTCTRL */ | ||
803 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 | ||
804 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) | 56 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) |
805 | |||
806 | /* Used by PM_CORE_PWRSTST */ | ||
807 | #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 | ||
808 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) | 57 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) |
809 | |||
810 | /* | ||
811 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
812 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
813 | */ | ||
814 | #define OMAP4430_OFF_SHIFT 0 | 58 | #define OMAP4430_OFF_SHIFT 0 |
815 | #define OMAP4430_OFF_MASK (0xff << 0) | ||
816 | |||
817 | /* | ||
818 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
819 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
820 | */ | ||
821 | #define OMAP4430_ON_SHIFT 24 | 59 | #define OMAP4430_ON_SHIFT 24 |
822 | #define OMAP4430_ON_MASK (0xff << 24) | 60 | #define OMAP4430_ON_MASK (0xff << 24) |
823 | |||
824 | /* | ||
825 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
826 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
827 | */ | ||
828 | #define OMAP4430_ONLP_SHIFT 16 | 61 | #define OMAP4430_ONLP_SHIFT 16 |
829 | #define OMAP4430_ONLP_MASK (0xff << 16) | ||
830 | |||
831 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
832 | #define OMAP4430_OPP_CHANGE_SHIFT 2 | ||
833 | #define OMAP4430_OPP_CHANGE_MASK (1 << 2) | ||
834 | |||
835 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
836 | #define OMAP4430_OPP_SEL_SHIFT 0 | ||
837 | #define OMAP4430_OPP_SEL_MASK (0x3 << 0) | ||
838 | |||
839 | /* Used by PRM_SRAM_COUNT */ | ||
840 | #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 | ||
841 | #define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) | ||
842 | |||
843 | /* Used by PRM_PSCON_COUNT */ | ||
844 | #define OMAP4430_PCHARGE_TIME_SHIFT 0 | ||
845 | #define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) | ||
846 | |||
847 | /* Used by PM_ABE_PWRSTCTRL */ | ||
848 | #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 | ||
849 | #define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) | ||
850 | |||
851 | /* Used by PM_ABE_PWRSTCTRL */ | ||
852 | #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 | ||
853 | #define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) | ||
854 | |||
855 | /* Used by PM_ABE_PWRSTST */ | ||
856 | #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 | ||
857 | #define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) | ||
858 | |||
859 | /* Used by PRM_PHASE1_CNDP */ | ||
860 | #define OMAP4430_PHASE1_CNDP_SHIFT 0 | ||
861 | #define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) | ||
862 | |||
863 | /* Used by PRM_PHASE2A_CNDP */ | ||
864 | #define OMAP4430_PHASE2A_CNDP_SHIFT 0 | ||
865 | #define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) | ||
866 | |||
867 | /* Used by PRM_PHASE2B_CNDP */ | ||
868 | #define OMAP4430_PHASE2B_CNDP_SHIFT 0 | ||
869 | #define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) | ||
870 | |||
871 | /* Used by PRM_PSCON_COUNT */ | ||
872 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 | ||
873 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) | ||
874 | |||
875 | /* | ||
876 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, | ||
877 | * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, | ||
878 | * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | ||
879 | * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | ||
880 | */ | ||
881 | #define OMAP4430_POWERSTATE_SHIFT 0 | ||
882 | #define OMAP4430_POWERSTATE_MASK (0x3 << 0) | ||
883 | |||
884 | /* | ||
885 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, | ||
886 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | ||
887 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
888 | */ | ||
889 | #define OMAP4430_POWERSTATEST_SHIFT 0 | ||
890 | #define OMAP4430_POWERSTATEST_MASK (0x3 << 0) | ||
891 | |||
892 | /* Used by PRM_PWRREQCTRL */ | ||
893 | #define OMAP4430_PWRREQ_COND_SHIFT 0 | ||
894 | #define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) | ||
895 | |||
896 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
897 | #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 | ||
898 | #define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) | ||
899 | |||
900 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
901 | #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 | ||
902 | #define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) | ||
903 | |||
904 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
905 | #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 | ||
906 | #define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) | ||
907 | |||
908 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
909 | #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 | ||
910 | #define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) | ||
911 | |||
912 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
913 | #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 | ||
914 | #define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) | ||
915 | |||
916 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
917 | #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 | ||
918 | #define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) | ||
919 | |||
920 | /* | ||
921 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
922 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
923 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
924 | */ | ||
925 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 | 62 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 |
926 | #define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) | ||
927 | |||
928 | /* | ||
929 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
930 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
931 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
932 | */ | ||
933 | #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 | ||
934 | #define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) | ||
935 | |||
936 | /* | ||
937 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
938 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
939 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
940 | */ | ||
941 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 | 63 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 |
942 | #define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) | ||
943 | |||
944 | /* | ||
945 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
946 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
947 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
948 | */ | ||
949 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 | 64 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 |
950 | #define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) | ||
951 | |||
952 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
953 | #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 | ||
954 | #define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) | ||
955 | |||
956 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
957 | #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 | ||
958 | #define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) | ||
959 | |||
960 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
961 | #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 | ||
962 | #define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) | ||
963 | |||
964 | /* Used by PRM_VC_VAL_BYPASS */ | ||
965 | #define OMAP4430_REGADDR_SHIFT 8 | 65 | #define OMAP4430_REGADDR_SHIFT 8 |
966 | #define OMAP4430_REGADDR_MASK (0xff << 8) | ||
967 | |||
968 | /* | ||
969 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
970 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
971 | */ | ||
972 | #define OMAP4430_RET_SHIFT 8 | 66 | #define OMAP4430_RET_SHIFT 8 |
973 | #define OMAP4430_RET_MASK (0xff << 8) | ||
974 | |||
975 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
976 | #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 | ||
977 | #define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) | ||
978 | |||
979 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
980 | #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 | ||
981 | #define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) | ||
982 | |||
983 | /* Used by PM_L4PER_PWRSTST */ | ||
984 | #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 | ||
985 | #define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) | ||
986 | |||
987 | /* | ||
988 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
989 | * PRM_LDO_SRAM_MPU_CTRL | ||
990 | */ | ||
991 | #define OMAP4430_RETMODE_ENABLE_SHIFT 0 | ||
992 | #define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) | ||
993 | |||
994 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ | ||
995 | #define OMAP4430_RST1_SHIFT 0 | ||
996 | #define OMAP4430_RST1_MASK (1 << 0) | ||
997 | |||
998 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ | ||
999 | #define OMAP4430_RST1ST_SHIFT 0 | ||
1000 | #define OMAP4430_RST1ST_MASK (1 << 0) | ||
1001 | |||
1002 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ | ||
1003 | #define OMAP4430_RST2_SHIFT 1 | ||
1004 | #define OMAP4430_RST2_MASK (1 << 1) | ||
1005 | |||
1006 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ | ||
1007 | #define OMAP4430_RST2ST_SHIFT 1 | ||
1008 | #define OMAP4430_RST2ST_MASK (1 << 1) | ||
1009 | |||
1010 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ | ||
1011 | #define OMAP4430_RST3_SHIFT 2 | ||
1012 | #define OMAP4430_RST3_MASK (1 << 2) | ||
1013 | |||
1014 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ | ||
1015 | #define OMAP4430_RST3ST_SHIFT 2 | ||
1016 | #define OMAP4430_RST3ST_MASK (1 << 2) | ||
1017 | |||
1018 | /* Used by PRM_RSTTIME */ | ||
1019 | #define OMAP4430_RSTTIME1_SHIFT 0 | ||
1020 | #define OMAP4430_RSTTIME1_MASK (0x3ff << 0) | ||
1021 | |||
1022 | /* Used by PRM_RSTTIME */ | ||
1023 | #define OMAP4430_RSTTIME2_SHIFT 10 | ||
1024 | #define OMAP4430_RSTTIME2_MASK (0x1f << 10) | ||
1025 | |||
1026 | /* Used by PRM_RSTCTRL */ | ||
1027 | #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 | ||
1028 | #define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) | ||
1029 | |||
1030 | /* Used by PRM_RSTCTRL */ | ||
1031 | #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 | ||
1032 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) | 67 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) |
1033 | |||
1034 | /* Used by REVISION_PRM */ | ||
1035 | #define OMAP4430_R_RTL_SHIFT 11 | ||
1036 | #define OMAP4430_R_RTL_MASK (0x1f << 11) | ||
1037 | |||
1038 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
1039 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 | 68 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 |
1040 | #define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) | ||
1041 | |||
1042 | /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ | ||
1043 | #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 | ||
1044 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) | 69 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) |
1045 | |||
1046 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
1047 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 | 70 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 |
1048 | #define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) | ||
1049 | |||
1050 | /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ | ||
1051 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 | ||
1052 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) | 71 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) |
1053 | |||
1054 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
1055 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 | 72 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 |
1056 | #define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) | ||
1057 | |||
1058 | /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ | ||
1059 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 | ||
1060 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) | 73 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) |
1061 | |||
1062 | /* Used by REVISION_PRM */ | ||
1063 | #define OMAP4430_SCHEME_SHIFT 30 | ||
1064 | #define OMAP4430_SCHEME_MASK (0x3 << 30) | ||
1065 | |||
1066 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
1067 | #define OMAP4430_SCLH_SHIFT 0 | 74 | #define OMAP4430_SCLH_SHIFT 0 |
1068 | #define OMAP4430_SCLH_MASK (0xff << 0) | ||
1069 | |||
1070 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
1071 | #define OMAP4430_SCLL_SHIFT 8 | 75 | #define OMAP4430_SCLL_SHIFT 8 |
1072 | #define OMAP4430_SCLL_MASK (0xff << 8) | ||
1073 | |||
1074 | /* Used by PRM_RSTST */ | ||
1075 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 | 76 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 |
1076 | #define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) | ||
1077 | |||
1078 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1079 | #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 | ||
1080 | #define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) | ||
1081 | |||
1082 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1083 | #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 | ||
1084 | #define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) | ||
1085 | |||
1086 | /* Used by PM_IVAHD_PWRSTST */ | ||
1087 | #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 | ||
1088 | #define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) | ||
1089 | |||
1090 | /* Used by PRM_VC_VAL_BYPASS */ | ||
1091 | #define OMAP4430_SLAVEADDR_SHIFT 0 | 77 | #define OMAP4430_SLAVEADDR_SHIFT 0 |
1092 | #define OMAP4430_SLAVEADDR_MASK (0x7f << 0) | ||
1093 | |||
1094 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
1095 | #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 | ||
1096 | #define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) | ||
1097 | |||
1098 | /* Used by PRM_SRAM_COUNT */ | ||
1099 | #define OMAP4430_SLPCNT_VALUE_SHIFT 16 | ||
1100 | #define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) | ||
1101 | |||
1102 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | ||
1103 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 | 78 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 |
1104 | #define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) | ||
1105 | |||
1106 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | ||
1107 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 | 79 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 |
1108 | #define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) | ||
1109 | |||
1110 | /* Used by PRM_VC_ERRST */ | ||
1111 | #define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 | ||
1112 | #define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) | ||
1113 | |||
1114 | /* Used by PRM_VC_ERRST */ | ||
1115 | #define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 | ||
1116 | #define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) | ||
1117 | |||
1118 | /* Used by PRM_VC_ERRST */ | ||
1119 | #define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 | ||
1120 | #define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) | ||
1121 | |||
1122 | /* Used by PRM_VC_ERRST */ | ||
1123 | #define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 | ||
1124 | #define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) | ||
1125 | |||
1126 | /* Used by PRM_VC_ERRST */ | ||
1127 | #define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 | ||
1128 | #define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) | ||
1129 | |||
1130 | /* Used by PRM_VC_ERRST */ | ||
1131 | #define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 | ||
1132 | #define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) | ||
1133 | |||
1134 | /* Used by PRM_VC_ERRST */ | ||
1135 | #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 | ||
1136 | #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) | ||
1137 | |||
1138 | /* Used by PRM_VC_ERRST */ | ||
1139 | #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 | ||
1140 | #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) | ||
1141 | |||
1142 | /* Used by PRM_VC_ERRST */ | ||
1143 | #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 | ||
1144 | #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) | ||
1145 | |||
1146 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
1147 | #define OMAP4430_SR2EN_SHIFT 0 | ||
1148 | #define OMAP4430_SR2EN_MASK (1 << 0) | ||
1149 | |||
1150 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
1151 | #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 | ||
1152 | #define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) | ||
1153 | |||
1154 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
1155 | #define OMAP4430_SR2_STATUS_SHIFT 3 | ||
1156 | #define OMAP4430_SR2_STATUS_MASK (0x3 << 3) | ||
1157 | |||
1158 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
1159 | #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 | ||
1160 | #define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) | ||
1161 | |||
1162 | /* | ||
1163 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
1164 | * PRM_LDO_SRAM_MPU_CTRL | ||
1165 | */ | ||
1166 | #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 | ||
1167 | #define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) | ||
1168 | |||
1169 | /* | ||
1170 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
1171 | * PRM_LDO_SRAM_MPU_CTRL | ||
1172 | */ | ||
1173 | #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 | ||
1174 | #define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) | ||
1175 | |||
1176 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
1177 | #define OMAP4430_SRMODEEN_SHIFT 4 | ||
1178 | #define OMAP4430_SRMODEEN_MASK (1 << 4) | ||
1179 | |||
1180 | /* Used by PRM_VOLTSETUP_WARMRESET */ | ||
1181 | #define OMAP4430_STABLE_COUNT_SHIFT 0 | ||
1182 | #define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) | ||
1183 | |||
1184 | /* Used by PRM_VOLTSETUP_WARMRESET */ | ||
1185 | #define OMAP4430_STABLE_PRESCAL_SHIFT 8 | ||
1186 | #define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) | ||
1187 | |||
1188 | /* Used by PRM_LDO_BANDGAP_SETUP */ | ||
1189 | #define OMAP4430_STARTUP_COUNT_SHIFT 0 | ||
1190 | #define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) | ||
1191 | |||
1192 | /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ | ||
1193 | #define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 | ||
1194 | #define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) | ||
1195 | |||
1196 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1197 | #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 | ||
1198 | #define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) | ||
1199 | |||
1200 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1201 | #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 | ||
1202 | #define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) | ||
1203 | |||
1204 | /* Used by PM_IVAHD_PWRSTST */ | ||
1205 | #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 | ||
1206 | #define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) | ||
1207 | |||
1208 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1209 | #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 | ||
1210 | #define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) | ||
1211 | |||
1212 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
1213 | #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 | ||
1214 | #define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) | ||
1215 | |||
1216 | /* Used by PM_IVAHD_PWRSTST */ | ||
1217 | #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 | ||
1218 | #define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) | ||
1219 | |||
1220 | /* Used by RM_TESLA_RSTST */ | ||
1221 | #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 | ||
1222 | #define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) | ||
1223 | |||
1224 | /* Used by RM_TESLA_RSTST */ | ||
1225 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 | ||
1226 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) | ||
1227 | |||
1228 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1229 | #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 | ||
1230 | #define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) | ||
1231 | |||
1232 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1233 | #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 | ||
1234 | #define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) | ||
1235 | |||
1236 | /* Used by PM_TESLA_PWRSTST */ | ||
1237 | #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 | ||
1238 | #define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) | ||
1239 | |||
1240 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1241 | #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 | ||
1242 | #define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) | ||
1243 | |||
1244 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1245 | #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 | ||
1246 | #define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) | ||
1247 | |||
1248 | /* Used by PM_TESLA_PWRSTST */ | ||
1249 | #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 | ||
1250 | #define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) | ||
1251 | |||
1252 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1253 | #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 | ||
1254 | #define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) | ||
1255 | |||
1256 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
1257 | #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 | ||
1258 | #define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) | ||
1259 | |||
1260 | /* Used by PM_TESLA_PWRSTST */ | ||
1261 | #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 | ||
1262 | #define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) | ||
1263 | |||
1264 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1265 | #define OMAP4430_TIMEOUT_SHIFT 0 | 80 | #define OMAP4430_TIMEOUT_SHIFT 0 |
1266 | #define OMAP4430_TIMEOUT_MASK (0xffff << 0) | ||
1267 | |||
1268 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
1269 | #define OMAP4430_TIMEOUTEN_SHIFT 3 | ||
1270 | #define OMAP4430_TIMEOUTEN_MASK (1 << 3) | 81 | #define OMAP4430_TIMEOUTEN_MASK (1 << 3) |
1271 | |||
1272 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1273 | #define OMAP4430_TRANSITION_EN_SHIFT 8 | ||
1274 | #define OMAP4430_TRANSITION_EN_MASK (1 << 8) | ||
1275 | |||
1276 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1277 | #define OMAP4430_TRANSITION_ST_SHIFT 8 | ||
1278 | #define OMAP4430_TRANSITION_ST_MASK (1 << 8) | ||
1279 | |||
1280 | /* Used by PRM_VC_VAL_BYPASS */ | ||
1281 | #define OMAP4430_VALID_SHIFT 24 | ||
1282 | #define OMAP4430_VALID_MASK (1 << 24) | 82 | #define OMAP4430_VALID_MASK (1 << 24) |
1283 | |||
1284 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1285 | #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 | ||
1286 | #define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) | ||
1287 | |||
1288 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1289 | #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 | ||
1290 | #define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) | ||
1291 | |||
1292 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1293 | #define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 | ||
1294 | #define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) | ||
1295 | |||
1296 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1297 | #define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 | ||
1298 | #define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) | ||
1299 | |||
1300 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1301 | #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 | ||
1302 | #define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) | ||
1303 | |||
1304 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1305 | #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 | ||
1306 | #define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) | ||
1307 | |||
1308 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1309 | #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 | ||
1310 | #define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) | ||
1311 | |||
1312 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1313 | #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 | ||
1314 | #define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) | ||
1315 | |||
1316 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1317 | #define OMAP4430_VC_RAERR_EN_SHIFT 12 | ||
1318 | #define OMAP4430_VC_RAERR_EN_MASK (1 << 12) | ||
1319 | |||
1320 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1321 | #define OMAP4430_VC_RAERR_ST_SHIFT 12 | ||
1322 | #define OMAP4430_VC_RAERR_ST_MASK (1 << 12) | ||
1323 | |||
1324 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1325 | #define OMAP4430_VC_SAERR_EN_SHIFT 11 | ||
1326 | #define OMAP4430_VC_SAERR_EN_MASK (1 << 11) | ||
1327 | |||
1328 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1329 | #define OMAP4430_VC_SAERR_ST_SHIFT 11 | ||
1330 | #define OMAP4430_VC_SAERR_ST_MASK (1 << 11) | ||
1331 | |||
1332 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1333 | #define OMAP4430_VC_TOERR_EN_SHIFT 13 | ||
1334 | #define OMAP4430_VC_TOERR_EN_MASK (1 << 13) | ||
1335 | |||
1336 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1337 | #define OMAP4430_VC_TOERR_ST_SHIFT 13 | ||
1338 | #define OMAP4430_VC_TOERR_ST_MASK (1 << 13) | ||
1339 | |||
1340 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1341 | #define OMAP4430_VDDMAX_SHIFT 24 | 83 | #define OMAP4430_VDDMAX_SHIFT 24 |
1342 | #define OMAP4430_VDDMAX_MASK (0xff << 24) | ||
1343 | |||
1344 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1345 | #define OMAP4430_VDDMIN_SHIFT 16 | 84 | #define OMAP4430_VDDMIN_SHIFT 16 |
1346 | #define OMAP4430_VDDMIN_MASK (0xff << 16) | ||
1347 | |||
1348 | /* Used by PRM_VOLTCTRL */ | ||
1349 | #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 | ||
1350 | #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) | ||
1351 | |||
1352 | /* Used by PRM_RSTST */ | ||
1353 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 | 85 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 |
1354 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) | ||
1355 | |||
1356 | /* Used by PRM_VOLTCTRL */ | ||
1357 | #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 | ||
1358 | #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) | ||
1359 | |||
1360 | /* Used by PRM_VOLTCTRL */ | ||
1361 | #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 | ||
1362 | #define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) | ||
1363 | |||
1364 | /* Used by PRM_RSTST */ | ||
1365 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 | 86 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 |
1366 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) | ||
1367 | |||
1368 | /* Used by PRM_VOLTCTRL */ | ||
1369 | #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 | ||
1370 | #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) | ||
1371 | |||
1372 | /* Used by PRM_VOLTCTRL */ | ||
1373 | #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 | ||
1374 | #define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) | ||
1375 | |||
1376 | /* Used by PRM_RSTST */ | ||
1377 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 | 87 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 |
1378 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) | ||
1379 | |||
1380 | /* Used by PRM_VC_ERRST */ | ||
1381 | #define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 | ||
1382 | #define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) | ||
1383 | |||
1384 | /* Used by PRM_VC_ERRST */ | ||
1385 | #define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 | ||
1386 | #define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) | ||
1387 | |||
1388 | /* Used by PRM_VC_ERRST */ | ||
1389 | #define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 | ||
1390 | #define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) | ||
1391 | |||
1392 | /* Used by PRM_VC_ERRST */ | ||
1393 | #define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 | ||
1394 | #define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) | ||
1395 | |||
1396 | /* Used by PRM_VC_ERRST */ | ||
1397 | #define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 | ||
1398 | #define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) | ||
1399 | |||
1400 | /* Used by PRM_VC_ERRST */ | ||
1401 | #define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 | ||
1402 | #define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) | ||
1403 | |||
1404 | /* Used by PRM_VC_ERRST */ | ||
1405 | #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 | ||
1406 | #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) | ||
1407 | |||
1408 | /* Used by PRM_VC_ERRST */ | ||
1409 | #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 | ||
1410 | #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) | ||
1411 | |||
1412 | /* Used by PRM_VC_ERRST */ | ||
1413 | #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 | ||
1414 | #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) | ||
1415 | |||
1416 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
1417 | #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 | ||
1418 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) | 88 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) |
1419 | |||
1420 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
1421 | #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 | ||
1422 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) | 89 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) |
1423 | |||
1424 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
1425 | #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 | ||
1426 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) | 90 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) |
1427 | |||
1428 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
1429 | #define OMAP4430_VPENABLE_SHIFT 0 | ||
1430 | #define OMAP4430_VPENABLE_MASK (1 << 0) | 91 | #define OMAP4430_VPENABLE_MASK (1 << 0) |
1431 | |||
1432 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ | ||
1433 | #define OMAP4430_VPINIDLE_SHIFT 0 | ||
1434 | #define OMAP4430_VPINIDLE_MASK (1 << 0) | ||
1435 | |||
1436 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | ||
1437 | #define OMAP4430_VPVOLTAGE_SHIFT 0 | ||
1438 | #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) | 92 | #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) |
1439 | |||
1440 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1441 | #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 | ||
1442 | #define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) | ||
1443 | |||
1444 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1445 | #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 | ||
1446 | #define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) | ||
1447 | |||
1448 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1449 | #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 | ||
1450 | #define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) | ||
1451 | |||
1452 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1453 | #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 | ||
1454 | #define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) | ||
1455 | |||
1456 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1457 | #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 | ||
1458 | #define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) | ||
1459 | |||
1460 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1461 | #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 | ||
1462 | #define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) | ||
1463 | |||
1464 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1465 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 | ||
1466 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) | ||
1467 | |||
1468 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1469 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 | ||
1470 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) | ||
1471 | |||
1472 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1473 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 | ||
1474 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) | ||
1475 | |||
1476 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1477 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 | ||
1478 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) | ||
1479 | |||
1480 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1481 | #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 | ||
1482 | #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) | ||
1483 | |||
1484 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1485 | #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 | ||
1486 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) | 93 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) |
1487 | |||
1488 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1489 | #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 | ||
1490 | #define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) | ||
1491 | |||
1492 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1493 | #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 | ||
1494 | #define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) | ||
1495 | |||
1496 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1497 | #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 | ||
1498 | #define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) | ||
1499 | |||
1500 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1501 | #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 | ||
1502 | #define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) | ||
1503 | |||
1504 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1505 | #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 | ||
1506 | #define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) | ||
1507 | |||
1508 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1509 | #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 | ||
1510 | #define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) | ||
1511 | |||
1512 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1513 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 | ||
1514 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) | ||
1515 | |||
1516 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1517 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 | ||
1518 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) | ||
1519 | |||
1520 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1521 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 | ||
1522 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) | ||
1523 | |||
1524 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1525 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 | ||
1526 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) | ||
1527 | |||
1528 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
1529 | #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 | ||
1530 | #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) | ||
1531 | |||
1532 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
1533 | #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 | ||
1534 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) | 94 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) |
1535 | |||
1536 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1537 | #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 | ||
1538 | #define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) | ||
1539 | |||
1540 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1541 | #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 | ||
1542 | #define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) | ||
1543 | |||
1544 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1545 | #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 | ||
1546 | #define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) | ||
1547 | |||
1548 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1549 | #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 | ||
1550 | #define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) | ||
1551 | |||
1552 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1553 | #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 | ||
1554 | #define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) | ||
1555 | |||
1556 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1557 | #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 | ||
1558 | #define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) | ||
1559 | |||
1560 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1561 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 | ||
1562 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) | ||
1563 | |||
1564 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1565 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 | ||
1566 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) | ||
1567 | |||
1568 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1569 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 | ||
1570 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) | ||
1571 | |||
1572 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1573 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 | ||
1574 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) | ||
1575 | |||
1576 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1577 | #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 | ||
1578 | #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) | ||
1579 | |||
1580 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1581 | #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 | ||
1582 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) | 95 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) |
1583 | |||
1584 | /* Used by PRM_SRAM_COUNT */ | ||
1585 | #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 | ||
1586 | #define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) | ||
1587 | |||
1588 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | ||
1589 | #define OMAP4430_VSTEPMAX_SHIFT 0 | 96 | #define OMAP4430_VSTEPMAX_SHIFT 0 |
1590 | #define OMAP4430_VSTEPMAX_MASK (0xff << 0) | ||
1591 | |||
1592 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | ||
1593 | #define OMAP4430_VSTEPMIN_SHIFT 0 | 97 | #define OMAP4430_VSTEPMIN_SHIFT 0 |
1594 | #define OMAP4430_VSTEPMIN_MASK (0xff << 0) | ||
1595 | |||
1596 | /* Used by PRM_MODEM_IF_CTRL */ | ||
1597 | #define OMAP4430_WAKE_MODEM_SHIFT 0 | ||
1598 | #define OMAP4430_WAKE_MODEM_MASK (1 << 0) | ||
1599 | |||
1600 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1601 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 | ||
1602 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) | ||
1603 | |||
1604 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1605 | #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 | ||
1606 | #define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) | ||
1607 | |||
1608 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1609 | #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 | ||
1610 | #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) | ||
1611 | |||
1612 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1613 | #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 | ||
1614 | #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) | ||
1615 | |||
1616 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1617 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 | ||
1618 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) | ||
1619 | |||
1620 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1621 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 | ||
1622 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) | ||
1623 | |||
1624 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1625 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 | ||
1626 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) | ||
1627 | |||
1628 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1629 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 | ||
1630 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) | ||
1631 | |||
1632 | /* Used by PM_L4PER_DMTIMER10_WKDEP */ | ||
1633 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 | ||
1634 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) | ||
1635 | |||
1636 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | ||
1637 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 | ||
1638 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) | ||
1639 | |||
1640 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | ||
1641 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 | ||
1642 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) | ||
1643 | |||
1644 | /* Used by PM_L4PER_DMTIMER2_WKDEP */ | ||
1645 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 | ||
1646 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) | ||
1647 | |||
1648 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | ||
1649 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 | ||
1650 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) | ||
1651 | |||
1652 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | ||
1653 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 | ||
1654 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) | ||
1655 | |||
1656 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | ||
1657 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 | ||
1658 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) | ||
1659 | |||
1660 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | ||
1661 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 | ||
1662 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) | ||
1663 | |||
1664 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | ||
1665 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 | ||
1666 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) | ||
1667 | |||
1668 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | ||
1669 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 | ||
1670 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) | ||
1671 | |||
1672 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1673 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 | ||
1674 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) | ||
1675 | |||
1676 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1677 | #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 | ||
1678 | #define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) | ||
1679 | |||
1680 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1681 | #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 | ||
1682 | #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) | ||
1683 | |||
1684 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1685 | #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 | ||
1686 | #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) | ||
1687 | |||
1688 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1689 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 | ||
1690 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) | ||
1691 | |||
1692 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1693 | #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 | ||
1694 | #define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) | ||
1695 | |||
1696 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1697 | #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 | ||
1698 | #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) | ||
1699 | |||
1700 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1701 | #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 | ||
1702 | #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) | ||
1703 | |||
1704 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
1705 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 | ||
1706 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) | ||
1707 | |||
1708 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
1709 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 | ||
1710 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) | ||
1711 | |||
1712 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
1713 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 | ||
1714 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) | ||
1715 | |||
1716 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
1717 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 | ||
1718 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) | ||
1719 | |||
1720 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
1721 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 | ||
1722 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) | ||
1723 | |||
1724 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
1725 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 | ||
1726 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) | ||
1727 | |||
1728 | /* Used by PM_L4PER_GPIO3_WKDEP */ | ||
1729 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 | ||
1730 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) | ||
1731 | |||
1732 | /* Used by PM_L4PER_GPIO3_WKDEP */ | ||
1733 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 | ||
1734 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) | ||
1735 | |||
1736 | /* Used by PM_L4PER_GPIO4_WKDEP */ | ||
1737 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 | ||
1738 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) | ||
1739 | |||
1740 | /* Used by PM_L4PER_GPIO4_WKDEP */ | ||
1741 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 | ||
1742 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) | ||
1743 | |||
1744 | /* Used by PM_L4PER_GPIO5_WKDEP */ | ||
1745 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 | ||
1746 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) | ||
1747 | |||
1748 | /* Used by PM_L4PER_GPIO5_WKDEP */ | ||
1749 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 | ||
1750 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) | ||
1751 | |||
1752 | /* Used by PM_L4PER_GPIO6_WKDEP */ | ||
1753 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 | ||
1754 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) | ||
1755 | |||
1756 | /* Used by PM_L4PER_GPIO6_WKDEP */ | ||
1757 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 | ||
1758 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) | ||
1759 | |||
1760 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1761 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 | ||
1762 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) | ||
1763 | |||
1764 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1765 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 | ||
1766 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) | ||
1767 | |||
1768 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1769 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 | ||
1770 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) | ||
1771 | |||
1772 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1773 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 | ||
1774 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) | ||
1775 | |||
1776 | /* Used by PM_L4PER_HECC1_WKDEP */ | ||
1777 | #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 | ||
1778 | #define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) | ||
1779 | |||
1780 | /* Used by PM_L4PER_HECC2_WKDEP */ | ||
1781 | #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 | ||
1782 | #define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) | ||
1783 | |||
1784 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
1785 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 | ||
1786 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) | ||
1787 | |||
1788 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
1789 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 | ||
1790 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) | ||
1791 | |||
1792 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
1793 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 | ||
1794 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) | ||
1795 | |||
1796 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
1797 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 | ||
1798 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) | ||
1799 | |||
1800 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
1801 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 | ||
1802 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) | ||
1803 | |||
1804 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
1805 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 | ||
1806 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) | ||
1807 | |||
1808 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
1809 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 | ||
1810 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) | ||
1811 | |||
1812 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
1813 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 | ||
1814 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) | ||
1815 | |||
1816 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
1817 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 | ||
1818 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) | ||
1819 | |||
1820 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
1821 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 | ||
1822 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) | ||
1823 | |||
1824 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
1825 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 | ||
1826 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) | ||
1827 | |||
1828 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
1829 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 | ||
1830 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) | ||
1831 | |||
1832 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
1833 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 | ||
1834 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) | ||
1835 | |||
1836 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
1837 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 | ||
1838 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) | ||
1839 | |||
1840 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
1841 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 | ||
1842 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) | ||
1843 | |||
1844 | /* Used by PM_L4PER_I2C5_WKDEP */ | ||
1845 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 | ||
1846 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) | ||
1847 | |||
1848 | /* Used by PM_L4PER_I2C5_WKDEP */ | ||
1849 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 | ||
1850 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) | ||
1851 | |||
1852 | /* Used by PM_WKUP_KEYBOARD_WKDEP */ | ||
1853 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 | ||
1854 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) | ||
1855 | |||
1856 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
1857 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 | ||
1858 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) | ||
1859 | |||
1860 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
1861 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 | ||
1862 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) | ||
1863 | |||
1864 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
1865 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 | ||
1866 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) | ||
1867 | |||
1868 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
1869 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 | ||
1870 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) | ||
1871 | |||
1872 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
1873 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 | ||
1874 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) | ||
1875 | |||
1876 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
1877 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 | ||
1878 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) | ||
1879 | |||
1880 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
1881 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 | ||
1882 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) | ||
1883 | |||
1884 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
1885 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 | ||
1886 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) | ||
1887 | |||
1888 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
1889 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 | ||
1890 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) | ||
1891 | |||
1892 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
1893 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 | ||
1894 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) | ||
1895 | |||
1896 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
1897 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 | ||
1898 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) | ||
1899 | |||
1900 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
1901 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 | ||
1902 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) | ||
1903 | |||
1904 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
1905 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 | ||
1906 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) | ||
1907 | |||
1908 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
1909 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 | ||
1910 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) | ||
1911 | |||
1912 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
1913 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 | ||
1914 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) | ||
1915 | |||
1916 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
1917 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 | ||
1918 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) | ||
1919 | |||
1920 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
1921 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 | ||
1922 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) | ||
1923 | |||
1924 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
1925 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 | ||
1926 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) | ||
1927 | |||
1928 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
1929 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 | ||
1930 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) | ||
1931 | |||
1932 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
1933 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 | ||
1934 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) | ||
1935 | |||
1936 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
1937 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 | ||
1938 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) | ||
1939 | |||
1940 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
1941 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 | ||
1942 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) | ||
1943 | |||
1944 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
1945 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 | ||
1946 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) | ||
1947 | |||
1948 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
1949 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 | ||
1950 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) | ||
1951 | |||
1952 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
1953 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 | ||
1954 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) | ||
1955 | |||
1956 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
1957 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 | ||
1958 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) | ||
1959 | |||
1960 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
1961 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 | ||
1962 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) | ||
1963 | |||
1964 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
1965 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 | ||
1966 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) | ||
1967 | |||
1968 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
1969 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 | ||
1970 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) | ||
1971 | |||
1972 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
1973 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 | ||
1974 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) | ||
1975 | |||
1976 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
1977 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 | ||
1978 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) | ||
1979 | |||
1980 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | ||
1981 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 | ||
1982 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) | ||
1983 | |||
1984 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | ||
1985 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 | ||
1986 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) | ||
1987 | |||
1988 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | ||
1989 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 | ||
1990 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) | ||
1991 | |||
1992 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | ||
1993 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 | ||
1994 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) | ||
1995 | |||
1996 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
1997 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 | ||
1998 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) | ||
1999 | |||
2000 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
2001 | #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 | ||
2002 | #define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) | ||
2003 | |||
2004 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
2005 | #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 | ||
2006 | #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) | ||
2007 | |||
2008 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
2009 | #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 | ||
2010 | #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) | ||
2011 | |||
2012 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
2013 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 | ||
2014 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) | ||
2015 | |||
2016 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
2017 | #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 | ||
2018 | #define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) | ||
2019 | |||
2020 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
2021 | #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 | ||
2022 | #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) | ||
2023 | |||
2024 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
2025 | #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 | ||
2026 | #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) | ||
2027 | |||
2028 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
2029 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 | ||
2030 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) | ||
2031 | |||
2032 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
2033 | #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 | ||
2034 | #define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) | ||
2035 | |||
2036 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
2037 | #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 | ||
2038 | #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) | ||
2039 | |||
2040 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
2041 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 | ||
2042 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) | ||
2043 | |||
2044 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
2045 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 | ||
2046 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) | ||
2047 | |||
2048 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
2049 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 | ||
2050 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) | ||
2051 | |||
2052 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
2053 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 | ||
2054 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) | ||
2055 | |||
2056 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
2057 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 | ||
2058 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) | ||
2059 | |||
2060 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
2061 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 | ||
2062 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) | ||
2063 | |||
2064 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
2065 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 | ||
2066 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) | ||
2067 | |||
2068 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
2069 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 | ||
2070 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) | ||
2071 | |||
2072 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
2073 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 | ||
2074 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) | ||
2075 | |||
2076 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | ||
2077 | #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 | ||
2078 | #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) | ||
2079 | |||
2080 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | ||
2081 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 | ||
2082 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) | ||
2083 | |||
2084 | /* Used by PM_ABE_PDM_WKDEP */ | ||
2085 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 | ||
2086 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) | ||
2087 | |||
2088 | /* Used by PM_ABE_PDM_WKDEP */ | ||
2089 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 | ||
2090 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) | ||
2091 | |||
2092 | /* Used by PM_ABE_PDM_WKDEP */ | ||
2093 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 | ||
2094 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) | ||
2095 | |||
2096 | /* Used by PM_ABE_PDM_WKDEP */ | ||
2097 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 | ||
2098 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) | ||
2099 | |||
2100 | /* Used by PM_WKUP_RTC_WKDEP */ | ||
2101 | #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 | ||
2102 | #define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) | ||
2103 | |||
2104 | /* Used by PM_L3INIT_SATA_WKDEP */ | ||
2105 | #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 | ||
2106 | #define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) | ||
2107 | |||
2108 | /* Used by PM_L3INIT_SATA_WKDEP */ | ||
2109 | #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 | ||
2110 | #define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) | ||
2111 | |||
2112 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
2113 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 | ||
2114 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) | ||
2115 | |||
2116 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
2117 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 | ||
2118 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) | ||
2119 | |||
2120 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
2121 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 | ||
2122 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) | ||
2123 | |||
2124 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
2125 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 | ||
2126 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) | ||
2127 | |||
2128 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
2129 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 | ||
2130 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) | ||
2131 | |||
2132 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
2133 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 | ||
2134 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) | ||
2135 | |||
2136 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
2137 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 | ||
2138 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) | ||
2139 | |||
2140 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
2141 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 | ||
2142 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) | ||
2143 | |||
2144 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | ||
2145 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 | ||
2146 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) | ||
2147 | |||
2148 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | ||
2149 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 | ||
2150 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) | ||
2151 | |||
2152 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | ||
2153 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 | ||
2154 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) | ||
2155 | |||
2156 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | ||
2157 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 | ||
2158 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) | ||
2159 | |||
2160 | /* Used by PM_ALWON_SR_MPU_WKDEP */ | ||
2161 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 | ||
2162 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) | ||
2163 | |||
2164 | /* Used by PM_WKUP_TIMER12_WKDEP */ | ||
2165 | #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 | ||
2166 | #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) | ||
2167 | |||
2168 | /* Used by PM_WKUP_TIMER1_WKDEP */ | ||
2169 | #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 | ||
2170 | #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) | ||
2171 | |||
2172 | /* Used by PM_ABE_TIMER5_WKDEP */ | ||
2173 | #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 | ||
2174 | #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) | ||
2175 | |||
2176 | /* Used by PM_ABE_TIMER5_WKDEP */ | ||
2177 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 | ||
2178 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) | ||
2179 | |||
2180 | /* Used by PM_ABE_TIMER6_WKDEP */ | ||
2181 | #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 | ||
2182 | #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) | ||
2183 | |||
2184 | /* Used by PM_ABE_TIMER6_WKDEP */ | ||
2185 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 | ||
2186 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) | ||
2187 | |||
2188 | /* Used by PM_ABE_TIMER7_WKDEP */ | ||
2189 | #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 | ||
2190 | #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) | ||
2191 | |||
2192 | /* Used by PM_ABE_TIMER7_WKDEP */ | ||
2193 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 | ||
2194 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) | ||
2195 | |||
2196 | /* Used by PM_ABE_TIMER8_WKDEP */ | ||
2197 | #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 | ||
2198 | #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) | ||
2199 | |||
2200 | /* Used by PM_ABE_TIMER8_WKDEP */ | ||
2201 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 | ||
2202 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) | ||
2203 | |||
2204 | /* Used by PM_L4PER_UART1_WKDEP */ | ||
2205 | #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 | ||
2206 | #define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) | ||
2207 | |||
2208 | /* Used by PM_L4PER_UART1_WKDEP */ | ||
2209 | #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 | ||
2210 | #define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) | ||
2211 | |||
2212 | /* Used by PM_L4PER_UART2_WKDEP */ | ||
2213 | #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 | ||
2214 | #define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) | ||
2215 | |||
2216 | /* Used by PM_L4PER_UART2_WKDEP */ | ||
2217 | #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 | ||
2218 | #define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) | ||
2219 | |||
2220 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2221 | #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 | ||
2222 | #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) | ||
2223 | |||
2224 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2225 | #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 | ||
2226 | #define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) | ||
2227 | |||
2228 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2229 | #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 | ||
2230 | #define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) | ||
2231 | |||
2232 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2233 | #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 | ||
2234 | #define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) | ||
2235 | |||
2236 | /* Used by PM_L4PER_UART4_WKDEP */ | ||
2237 | #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 | ||
2238 | #define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) | ||
2239 | |||
2240 | /* Used by PM_L4PER_UART4_WKDEP */ | ||
2241 | #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 | ||
2242 | #define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) | ||
2243 | |||
2244 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | ||
2245 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 | ||
2246 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) | ||
2247 | |||
2248 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | ||
2249 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 | ||
2250 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) | ||
2251 | |||
2252 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | ||
2253 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 | ||
2254 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) | ||
2255 | |||
2256 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | ||
2257 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 | ||
2258 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) | ||
2259 | |||
2260 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | ||
2261 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 | ||
2262 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) | ||
2263 | |||
2264 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | ||
2265 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 | ||
2266 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) | ||
2267 | |||
2268 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | ||
2269 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 | ||
2270 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) | ||
2271 | |||
2272 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | ||
2273 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 | ||
2274 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) | ||
2275 | |||
2276 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | ||
2277 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 | ||
2278 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) | ||
2279 | |||
2280 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | ||
2281 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 | ||
2282 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) | ||
2283 | |||
2284 | /* Used by PM_WKUP_USIM_WKDEP */ | ||
2285 | #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 | ||
2286 | #define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) | ||
2287 | |||
2288 | /* Used by PM_WKUP_USIM_WKDEP */ | ||
2289 | #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 | ||
2290 | #define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) | ||
2291 | |||
2292 | /* Used by PM_WKUP_WDT2_WKDEP */ | ||
2293 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 | ||
2294 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) | ||
2295 | |||
2296 | /* Used by PM_WKUP_WDT2_WKDEP */ | ||
2297 | #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 | ||
2298 | #define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) | ||
2299 | |||
2300 | /* Used by PM_ABE_WDT3_WKDEP */ | ||
2301 | #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 | ||
2302 | #define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) | ||
2303 | |||
2304 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
2305 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 | ||
2306 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) | ||
2307 | |||
2308 | /* Used by PM_L3INIT_XHPI_WKDEP */ | ||
2309 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 | ||
2310 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) | ||
2311 | |||
2312 | /* Used by PRM_IO_PMCTRL */ | ||
2313 | #define OMAP4430_WUCLK_CTRL_SHIFT 8 | ||
2314 | #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) | 98 | #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) |
2315 | |||
2316 | /* Used by PRM_IO_PMCTRL */ | ||
2317 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 | 99 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 |
2318 | #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) | 100 | #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) |
2319 | |||
2320 | /* Used by REVISION_PRM */ | ||
2321 | #define OMAP4430_X_MAJOR_SHIFT 8 | ||
2322 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) | ||
2323 | |||
2324 | /* Used by REVISION_PRM */ | ||
2325 | #define OMAP4430_Y_MINOR_SHIFT 0 | ||
2326 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) | ||
2327 | #endif | 101 | #endif |
diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h deleted file mode 100644 index be31b21aa9c6..000000000000 --- a/arch/arm/mach-omap2/prm-regbits-54xx.h +++ /dev/null | |||
@@ -1,2701 +0,0 @@ | |||
1 | /* | ||
2 | * OMAP54xx Power Management register bits | ||
3 | * | ||
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | ||
5 | * | ||
6 | * Paul Walmsley (paul@pwsan.com) | ||
7 | * Rajendra Nayak (rnayak@ti.com) | ||
8 | * Benoit Cousson (b-cousson@ti.com) | ||
9 | * | ||
10 | * This file is automatically generated from the OMAP hardware databases. | ||
11 | * We respectfully ask that any modifications to this file be coordinated | ||
12 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
13 | * authors above to ensure that the autogeneration scripts are kept | ||
14 | * up-to-date with the file contents. | ||
15 | * | ||
16 | * This program is free software; you can redistribute it and/or modify | ||
17 | * it under the terms of the GNU General Public License version 2 as | ||
18 | * published by the Free Software Foundation. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H | ||
22 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H | ||
23 | |||
24 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ | ||
25 | #define OMAP54XX_ABBOFF_ACT_SHIFT 1 | ||
26 | #define OMAP54XX_ABBOFF_ACT_WIDTH 0x1 | ||
27 | #define OMAP54XX_ABBOFF_ACT_MASK (1 << 1) | ||
28 | |||
29 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ | ||
30 | #define OMAP54XX_ABBOFF_SLEEP_SHIFT 2 | ||
31 | #define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1 | ||
32 | #define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2) | ||
33 | |||
34 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
35 | #define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31 | ||
36 | #define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1 | ||
37 | #define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31) | ||
38 | |||
39 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
40 | #define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31 | ||
41 | #define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1 | ||
42 | #define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31) | ||
43 | |||
44 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
45 | #define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7 | ||
46 | #define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1 | ||
47 | #define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7) | ||
48 | |||
49 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
50 | #define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7 | ||
51 | #define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1 | ||
52 | #define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7) | ||
53 | |||
54 | /* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ | ||
55 | #define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2 | ||
56 | #define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1 | ||
57 | #define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2) | ||
58 | |||
59 | /* Used by PM_ABE_PWRSTCTRL */ | ||
60 | #define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16 | ||
61 | #define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2 | ||
62 | #define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16) | ||
63 | |||
64 | /* Used by PM_ABE_PWRSTCTRL */ | ||
65 | #define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8 | ||
66 | #define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1 | ||
67 | #define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8) | ||
68 | |||
69 | /* Used by PM_ABE_PWRSTST */ | ||
70 | #define OMAP54XX_AESSMEM_STATEST_SHIFT 4 | ||
71 | #define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2 | ||
72 | #define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4) | ||
73 | |||
74 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ | ||
75 | #define OMAP54XX_AIPOFF_SHIFT 8 | ||
76 | #define OMAP54XX_AIPOFF_WIDTH 0x1 | ||
77 | #define OMAP54XX_AIPOFF_MASK (1 << 8) | ||
78 | |||
79 | /* Used by PRM_VOLTCTRL */ | ||
80 | #define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0 | ||
81 | #define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2 | ||
82 | #define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) | ||
83 | |||
84 | /* Used by PRM_VOLTCTRL */ | ||
85 | #define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4 | ||
86 | #define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2 | ||
87 | #define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4) | ||
88 | |||
89 | /* Used by PRM_VOLTCTRL */ | ||
90 | #define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2 | ||
91 | #define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2 | ||
92 | #define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) | ||
93 | |||
94 | /* Used by PRM_VC_BYPASS_ERRST */ | ||
95 | #define OMAP54XX_BYPS_RA_ERR_SHIFT 1 | ||
96 | #define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1 | ||
97 | #define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1) | ||
98 | |||
99 | /* Used by PRM_VC_BYPASS_ERRST */ | ||
100 | #define OMAP54XX_BYPS_SA_ERR_SHIFT 0 | ||
101 | #define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1 | ||
102 | #define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0) | ||
103 | |||
104 | /* Used by PRM_VC_BYPASS_ERRST */ | ||
105 | #define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2 | ||
106 | #define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1 | ||
107 | #define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2) | ||
108 | |||
109 | /* Used by PRM_RSTST */ | ||
110 | #define OMAP54XX_C2C_RST_SHIFT 10 | ||
111 | #define OMAP54XX_C2C_RST_WIDTH 0x1 | ||
112 | #define OMAP54XX_C2C_RST_MASK (1 << 10) | ||
113 | |||
114 | /* Used by PM_CAM_PWRSTCTRL */ | ||
115 | #define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16 | ||
116 | #define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2 | ||
117 | #define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16) | ||
118 | |||
119 | /* Used by PM_CAM_PWRSTST */ | ||
120 | #define OMAP54XX_CAM_MEM_STATEST_SHIFT 4 | ||
121 | #define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2 | ||
122 | #define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4) | ||
123 | |||
124 | /* Used by PRM_CLKREQCTRL */ | ||
125 | #define OMAP54XX_CLKREQ_COND_SHIFT 0 | ||
126 | #define OMAP54XX_CLKREQ_COND_WIDTH 0x3 | ||
127 | #define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0) | ||
128 | |||
129 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ | ||
130 | #define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16 | ||
131 | #define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8 | ||
132 | #define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16) | ||
133 | |||
134 | /* Used by PRM_VC_SMPS_MM_CONFIG */ | ||
135 | #define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16 | ||
136 | #define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8 | ||
137 | #define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16) | ||
138 | |||
139 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ | ||
140 | #define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16 | ||
141 | #define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8 | ||
142 | #define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16) | ||
143 | |||
144 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ | ||
145 | #define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28 | ||
146 | #define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1 | ||
147 | #define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28) | ||
148 | |||
149 | /* Used by PRM_VC_SMPS_MM_CONFIG */ | ||
150 | #define OMAP54XX_CMD_VDD_MM_L_SHIFT 28 | ||
151 | #define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1 | ||
152 | #define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28) | ||
153 | |||
154 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ | ||
155 | #define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28 | ||
156 | #define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1 | ||
157 | #define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28) | ||
158 | |||
159 | /* Used by PM_CORE_PWRSTCTRL */ | ||
160 | #define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18 | ||
161 | #define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2 | ||
162 | #define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) | ||
163 | |||
164 | /* Used by PM_CORE_PWRSTCTRL */ | ||
165 | #define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9 | ||
166 | #define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1 | ||
167 | #define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9) | ||
168 | |||
169 | /* Used by PM_CORE_PWRSTST */ | ||
170 | #define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6 | ||
171 | #define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2 | ||
172 | #define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6) | ||
173 | |||
174 | /* Used by PM_CORE_PWRSTCTRL */ | ||
175 | #define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16 | ||
176 | #define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2 | ||
177 | #define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) | ||
178 | |||
179 | /* Used by PM_CORE_PWRSTCTRL */ | ||
180 | #define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8 | ||
181 | #define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1 | ||
182 | #define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) | ||
183 | |||
184 | /* Used by PM_CORE_PWRSTST */ | ||
185 | #define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4 | ||
186 | #define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2 | ||
187 | #define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) | ||
188 | |||
189 | /* Used by REVISION_PRM */ | ||
190 | #define OMAP54XX_CUSTOM_SHIFT 6 | ||
191 | #define OMAP54XX_CUSTOM_WIDTH 0x2 | ||
192 | #define OMAP54XX_CUSTOM_MASK (0x3 << 6) | ||
193 | |||
194 | /* Used by PRM_VC_VAL_BYPASS */ | ||
195 | #define OMAP54XX_DATA_SHIFT 16 | ||
196 | #define OMAP54XX_DATA_WIDTH 0x8 | ||
197 | #define OMAP54XX_DATA_MASK (0xff << 16) | ||
198 | |||
199 | /* Used by PRM_DEBUG_CORE_RET_TRANS */ | ||
200 | #define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0 | ||
201 | #define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c | ||
202 | #define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0) | ||
203 | |||
204 | /* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */ | ||
205 | #define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 | ||
206 | #define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa | ||
207 | #define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) | ||
208 | |||
209 | /* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */ | ||
210 | #define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 | ||
211 | #define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 | ||
212 | #define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) | ||
213 | |||
214 | /* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */ | ||
215 | #define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 | ||
216 | #define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 | ||
217 | #define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) | ||
218 | |||
219 | /* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */ | ||
220 | #define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0 | ||
221 | #define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc | ||
222 | #define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0) | ||
223 | |||
224 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
225 | #define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0 | ||
226 | #define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1 | ||
227 | #define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0) | ||
228 | |||
229 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
230 | #define OMAP54XX_DFILTEREN_SHIFT 6 | ||
231 | #define OMAP54XX_DFILTEREN_WIDTH 0x1 | ||
232 | #define OMAP54XX_DFILTEREN_MASK (1 << 6) | ||
233 | |||
234 | /* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
235 | #define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4 | ||
236 | #define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1 | ||
237 | #define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4) | ||
238 | |||
239 | /* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
240 | #define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4 | ||
241 | #define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1 | ||
242 | #define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4) | ||
243 | |||
244 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
245 | #define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0 | ||
246 | #define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1 | ||
247 | #define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0) | ||
248 | |||
249 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
250 | #define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0 | ||
251 | #define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1 | ||
252 | #define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0) | ||
253 | |||
254 | /* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
255 | #define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2 | ||
256 | #define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1 | ||
257 | #define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2) | ||
258 | |||
259 | /* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
260 | #define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2 | ||
261 | #define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1 | ||
262 | #define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2) | ||
263 | |||
264 | /* Used by PRM_IRQENABLE_MPU */ | ||
265 | #define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1 | ||
266 | #define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1 | ||
267 | #define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1) | ||
268 | |||
269 | /* Used by PRM_IRQSTATUS_MPU */ | ||
270 | #define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1 | ||
271 | #define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1 | ||
272 | #define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1) | ||
273 | |||
274 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
275 | #define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3 | ||
276 | #define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1 | ||
277 | #define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3) | ||
278 | |||
279 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
280 | #define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3 | ||
281 | #define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1 | ||
282 | #define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3) | ||
283 | |||
284 | /* Used by PM_DSP_PWRSTCTRL */ | ||
285 | #define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20 | ||
286 | #define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2 | ||
287 | #define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20) | ||
288 | |||
289 | /* Used by PM_DSP_PWRSTCTRL */ | ||
290 | #define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10 | ||
291 | #define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1 | ||
292 | #define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10) | ||
293 | |||
294 | /* Used by PM_DSP_PWRSTST */ | ||
295 | #define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8 | ||
296 | #define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2 | ||
297 | #define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8) | ||
298 | |||
299 | /* Used by PM_DSP_PWRSTCTRL */ | ||
300 | #define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16 | ||
301 | #define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2 | ||
302 | #define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16) | ||
303 | |||
304 | /* Used by PM_DSP_PWRSTCTRL */ | ||
305 | #define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8 | ||
306 | #define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1 | ||
307 | #define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8) | ||
308 | |||
309 | /* Used by PM_DSP_PWRSTST */ | ||
310 | #define OMAP54XX_DSP_L1_STATEST_SHIFT 4 | ||
311 | #define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2 | ||
312 | #define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4) | ||
313 | |||
314 | /* Used by PM_DSP_PWRSTCTRL */ | ||
315 | #define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18 | ||
316 | #define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2 | ||
317 | #define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18) | ||
318 | |||
319 | /* Used by PM_DSP_PWRSTCTRL */ | ||
320 | #define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9 | ||
321 | #define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1 | ||
322 | #define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9) | ||
323 | |||
324 | /* Used by PM_DSP_PWRSTST */ | ||
325 | #define OMAP54XX_DSP_L2_STATEST_SHIFT 6 | ||
326 | #define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2 | ||
327 | #define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6) | ||
328 | |||
329 | /* Used by PM_DSS_PWRSTCTRL */ | ||
330 | #define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16 | ||
331 | #define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2 | ||
332 | #define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16) | ||
333 | |||
334 | /* Used by PM_DSS_PWRSTCTRL */ | ||
335 | #define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8 | ||
336 | #define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1 | ||
337 | #define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8) | ||
338 | |||
339 | /* Used by PM_DSS_PWRSTST */ | ||
340 | #define OMAP54XX_DSS_MEM_STATEST_SHIFT 4 | ||
341 | #define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2 | ||
342 | #define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4) | ||
343 | |||
344 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
345 | #define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8 | ||
346 | #define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1 | ||
347 | #define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) | ||
348 | |||
349 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
350 | #define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9 | ||
351 | #define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1 | ||
352 | #define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) | ||
353 | |||
354 | /* Used by PM_EMU_PWRSTCTRL */ | ||
355 | #define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16 | ||
356 | #define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2 | ||
357 | #define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16) | ||
358 | |||
359 | /* Used by PM_EMU_PWRSTST */ | ||
360 | #define OMAP54XX_EMU_BANK_STATEST_SHIFT 4 | ||
361 | #define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2 | ||
362 | #define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4) | ||
363 | |||
364 | /* | ||
365 | * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP, | ||
366 | * PRM_SRAM_WKUP_SETUP | ||
367 | */ | ||
368 | #define OMAP54XX_ENABLE_RTA_SHIFT 0 | ||
369 | #define OMAP54XX_ENABLE_RTA_WIDTH 0x1 | ||
370 | #define OMAP54XX_ENABLE_RTA_MASK (1 << 0) | ||
371 | |||
372 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ | ||
373 | #define OMAP54XX_ENFUNC1_SHIFT 3 | ||
374 | #define OMAP54XX_ENFUNC1_WIDTH 0x1 | ||
375 | #define OMAP54XX_ENFUNC1_MASK (1 << 3) | ||
376 | |||
377 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ | ||
378 | #define OMAP54XX_ENFUNC2_SHIFT 4 | ||
379 | #define OMAP54XX_ENFUNC2_WIDTH 0x1 | ||
380 | #define OMAP54XX_ENFUNC2_MASK (1 << 4) | ||
381 | |||
382 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ | ||
383 | #define OMAP54XX_ENFUNC3_SHIFT 5 | ||
384 | #define OMAP54XX_ENFUNC3_WIDTH 0x1 | ||
385 | #define OMAP54XX_ENFUNC3_MASK (1 << 5) | ||
386 | |||
387 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ | ||
388 | #define OMAP54XX_ENFUNC4_SHIFT 6 | ||
389 | #define OMAP54XX_ENFUNC4_WIDTH 0x1 | ||
390 | #define OMAP54XX_ENFUNC4_MASK (1 << 6) | ||
391 | |||
392 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ | ||
393 | #define OMAP54XX_ENFUNC5_SHIFT 7 | ||
394 | #define OMAP54XX_ENFUNC5_WIDTH 0x1 | ||
395 | #define OMAP54XX_ENFUNC5_MASK (1 << 7) | ||
396 | |||
397 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ | ||
398 | #define OMAP54XX_ERRORGAIN_SHIFT 16 | ||
399 | #define OMAP54XX_ERRORGAIN_WIDTH 0x8 | ||
400 | #define OMAP54XX_ERRORGAIN_MASK (0xff << 16) | ||
401 | |||
402 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ | ||
403 | #define OMAP54XX_ERROROFFSET_SHIFT 24 | ||
404 | #define OMAP54XX_ERROROFFSET_WIDTH 0x8 | ||
405 | #define OMAP54XX_ERROROFFSET_MASK (0xff << 24) | ||
406 | |||
407 | /* Used by PRM_RSTST */ | ||
408 | #define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5 | ||
409 | #define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1 | ||
410 | #define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5) | ||
411 | |||
412 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ | ||
413 | #define OMAP54XX_FORCEUPDATE_SHIFT 1 | ||
414 | #define OMAP54XX_FORCEUPDATE_WIDTH 0x1 | ||
415 | #define OMAP54XX_FORCEUPDATE_MASK (1 << 1) | ||
416 | |||
417 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | ||
418 | #define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8 | ||
419 | #define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18 | ||
420 | #define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8) | ||
421 | |||
422 | /* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */ | ||
423 | #define OMAP54XX_FORCEWKUP_EN_SHIFT 10 | ||
424 | #define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1 | ||
425 | #define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10) | ||
426 | |||
427 | /* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */ | ||
428 | #define OMAP54XX_FORCEWKUP_ST_SHIFT 10 | ||
429 | #define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1 | ||
430 | #define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10) | ||
431 | |||
432 | /* Used by REVISION_PRM */ | ||
433 | #define OMAP54XX_FUNC_SHIFT 16 | ||
434 | #define OMAP54XX_FUNC_WIDTH 0xc | ||
435 | #define OMAP54XX_FUNC_MASK (0xfff << 16) | ||
436 | |||
437 | /* Used by PRM_RSTST */ | ||
438 | #define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0 | ||
439 | #define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1 | ||
440 | #define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0) | ||
441 | |||
442 | /* Used by PRM_RSTST */ | ||
443 | #define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1 | ||
444 | #define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1 | ||
445 | #define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) | ||
446 | |||
447 | /* Used by PRM_IO_PMCTRL */ | ||
448 | #define OMAP54XX_GLOBAL_WUEN_SHIFT 16 | ||
449 | #define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1 | ||
450 | #define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16) | ||
451 | |||
452 | /* Used by PM_GPU_PWRSTCTRL */ | ||
453 | #define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16 | ||
454 | #define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2 | ||
455 | #define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16) | ||
456 | |||
457 | /* Used by PM_GPU_PWRSTST */ | ||
458 | #define OMAP54XX_GPU_MEM_STATEST_SHIFT 4 | ||
459 | #define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2 | ||
460 | #define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4) | ||
461 | |||
462 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
463 | #define OMAP54XX_HSMCODE_SHIFT 0 | ||
464 | #define OMAP54XX_HSMCODE_WIDTH 0x3 | ||
465 | #define OMAP54XX_HSMCODE_MASK (0x7 << 0) | ||
466 | |||
467 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
468 | #define OMAP54XX_HSMODEEN_SHIFT 3 | ||
469 | #define OMAP54XX_HSMODEEN_WIDTH 0x1 | ||
470 | #define OMAP54XX_HSMODEEN_MASK (1 << 3) | ||
471 | |||
472 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
473 | #define OMAP54XX_HSSCLH_SHIFT 16 | ||
474 | #define OMAP54XX_HSSCLH_WIDTH 0x8 | ||
475 | #define OMAP54XX_HSSCLH_MASK (0xff << 16) | ||
476 | |||
477 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
478 | #define OMAP54XX_HSSCLL_SHIFT 24 | ||
479 | #define OMAP54XX_HSSCLL_WIDTH 0x8 | ||
480 | #define OMAP54XX_HSSCLL_MASK (0xff << 24) | ||
481 | |||
482 | /* Used by PM_IVA_PWRSTCTRL */ | ||
483 | #define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16 | ||
484 | #define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2 | ||
485 | #define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16) | ||
486 | |||
487 | /* Used by PM_IVA_PWRSTCTRL */ | ||
488 | #define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8 | ||
489 | #define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1 | ||
490 | #define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8) | ||
491 | |||
492 | /* Used by PM_IVA_PWRSTST */ | ||
493 | #define OMAP54XX_HWA_MEM_STATEST_SHIFT 4 | ||
494 | #define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2 | ||
495 | #define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4) | ||
496 | |||
497 | /* Used by PRM_RSTST */ | ||
498 | #define OMAP54XX_ICEPICK_RST_SHIFT 9 | ||
499 | #define OMAP54XX_ICEPICK_RST_WIDTH 0x1 | ||
500 | #define OMAP54XX_ICEPICK_RST_MASK (1 << 9) | ||
501 | |||
502 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ | ||
503 | #define OMAP54XX_INITVDD_SHIFT 2 | ||
504 | #define OMAP54XX_INITVDD_WIDTH 0x1 | ||
505 | #define OMAP54XX_INITVDD_MASK (1 << 2) | ||
506 | |||
507 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ | ||
508 | #define OMAP54XX_INITVOLTAGE_SHIFT 8 | ||
509 | #define OMAP54XX_INITVOLTAGE_WIDTH 0x8 | ||
510 | #define OMAP54XX_INITVOLTAGE_MASK (0xff << 8) | ||
511 | |||
512 | /* | ||
513 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, | ||
514 | * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, | ||
515 | * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST, | ||
516 | * PRM_VOLTST_MM, PRM_VOLTST_MPU | ||
517 | */ | ||
518 | #define OMAP54XX_INTRANSITION_SHIFT 20 | ||
519 | #define OMAP54XX_INTRANSITION_WIDTH 0x1 | ||
520 | #define OMAP54XX_INTRANSITION_MASK (1 << 20) | ||
521 | |||
522 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
523 | #define OMAP54XX_IO_EN_SHIFT 9 | ||
524 | #define OMAP54XX_IO_EN_WIDTH 0x1 | ||
525 | #define OMAP54XX_IO_EN_MASK (1 << 9) | ||
526 | |||
527 | /* Used by PRM_IO_PMCTRL */ | ||
528 | #define OMAP54XX_IO_ON_STATUS_SHIFT 5 | ||
529 | #define OMAP54XX_IO_ON_STATUS_WIDTH 0x1 | ||
530 | #define OMAP54XX_IO_ON_STATUS_MASK (1 << 5) | ||
531 | |||
532 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
533 | #define OMAP54XX_IO_ST_SHIFT 9 | ||
534 | #define OMAP54XX_IO_ST_WIDTH 0x1 | ||
535 | #define OMAP54XX_IO_ST_MASK (1 << 9) | ||
536 | |||
537 | /* Used by PM_CORE_PWRSTCTRL */ | ||
538 | #define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20 | ||
539 | #define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2 | ||
540 | #define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20) | ||
541 | |||
542 | /* Used by PM_CORE_PWRSTCTRL */ | ||
543 | #define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10 | ||
544 | #define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1 | ||
545 | #define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10) | ||
546 | |||
547 | /* Used by PM_CORE_PWRSTST */ | ||
548 | #define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8 | ||
549 | #define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2 | ||
550 | #define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8) | ||
551 | |||
552 | /* Used by PM_CORE_PWRSTCTRL */ | ||
553 | #define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22 | ||
554 | #define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2 | ||
555 | #define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22) | ||
556 | |||
557 | /* Used by PM_CORE_PWRSTCTRL */ | ||
558 | #define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11 | ||
559 | #define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1 | ||
560 | #define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11) | ||
561 | |||
562 | /* Used by PM_CORE_PWRSTST */ | ||
563 | #define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10 | ||
564 | #define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2 | ||
565 | #define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10) | ||
566 | |||
567 | /* Used by PRM_IO_PMCTRL */ | ||
568 | #define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0 | ||
569 | #define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1 | ||
570 | #define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0) | ||
571 | |||
572 | /* Used by PRM_IO_PMCTRL */ | ||
573 | #define OMAP54XX_ISOCLK_STATUS_SHIFT 1 | ||
574 | #define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1 | ||
575 | #define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1) | ||
576 | |||
577 | /* Used by PRM_IO_PMCTRL */ | ||
578 | #define OMAP54XX_ISOOVR_EXTEND_SHIFT 4 | ||
579 | #define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1 | ||
580 | #define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4) | ||
581 | |||
582 | /* Used by PRM_IO_COUNT */ | ||
583 | #define OMAP54XX_ISO_2_ON_TIME_SHIFT 0 | ||
584 | #define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8 | ||
585 | #define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0) | ||
586 | |||
587 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
588 | #define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16 | ||
589 | #define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2 | ||
590 | #define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) | ||
591 | |||
592 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
593 | #define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8 | ||
594 | #define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1 | ||
595 | #define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8) | ||
596 | |||
597 | /* Used by PM_L3INIT_PWRSTST */ | ||
598 | #define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4 | ||
599 | #define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2 | ||
600 | #define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4) | ||
601 | |||
602 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
603 | #define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18 | ||
604 | #define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2 | ||
605 | #define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18) | ||
606 | |||
607 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
608 | #define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9 | ||
609 | #define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1 | ||
610 | #define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9) | ||
611 | |||
612 | /* Used by PM_L3INIT_PWRSTST */ | ||
613 | #define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6 | ||
614 | #define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2 | ||
615 | #define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6) | ||
616 | |||
617 | /* | ||
618 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, | ||
619 | * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, | ||
620 | * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST | ||
621 | */ | ||
622 | #define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24 | ||
623 | #define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2 | ||
624 | #define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | ||
625 | |||
626 | /* Used by PRM_RSTST */ | ||
627 | #define OMAP54XX_LLI_RST_SHIFT 14 | ||
628 | #define OMAP54XX_LLI_RST_WIDTH 0x1 | ||
629 | #define OMAP54XX_LLI_RST_MASK (1 << 14) | ||
630 | |||
631 | /* | ||
632 | * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL, | ||
633 | * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL | ||
634 | */ | ||
635 | #define OMAP54XX_LOGICRETSTATE_SHIFT 2 | ||
636 | #define OMAP54XX_LOGICRETSTATE_WIDTH 0x1 | ||
637 | #define OMAP54XX_LOGICRETSTATE_MASK (1 << 2) | ||
638 | |||
639 | /* | ||
640 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, | ||
641 | * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, | ||
642 | * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST | ||
643 | */ | ||
644 | #define OMAP54XX_LOGICSTATEST_SHIFT 2 | ||
645 | #define OMAP54XX_LOGICSTATEST_WIDTH 0x1 | ||
646 | #define OMAP54XX_LOGICSTATEST_MASK (1 << 2) | ||
647 | |||
648 | /* | ||
649 | * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, | ||
650 | * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, | ||
651 | * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT, | ||
652 | * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, | ||
653 | * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, | ||
654 | * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, | ||
655 | * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT, | ||
656 | * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, | ||
657 | * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT, | ||
658 | * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, | ||
659 | * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, | ||
660 | * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT, | ||
661 | * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT, | ||
662 | * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT, | ||
663 | * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, | ||
664 | * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, | ||
665 | * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, | ||
666 | * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT, | ||
667 | * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT, | ||
668 | * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, | ||
669 | * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, | ||
670 | * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, | ||
671 | * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, | ||
672 | * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, | ||
673 | * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, | ||
674 | * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, | ||
675 | * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, | ||
676 | * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT, | ||
677 | * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, | ||
678 | * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT, | ||
679 | * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT, | ||
680 | * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT, | ||
681 | * RM_WKUPAON_WD_TIMER2_CONTEXT | ||
682 | */ | ||
683 | #define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0 | ||
684 | #define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1 | ||
685 | #define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0) | ||
686 | |||
687 | /* | ||
688 | * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, | ||
689 | * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT, | ||
690 | * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, | ||
691 | * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT, | ||
692 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | ||
693 | * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT, | ||
694 | * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, | ||
695 | * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, | ||
696 | * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT, | ||
697 | * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT, | ||
698 | * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, | ||
699 | * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, | ||
700 | * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT, | ||
701 | * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, | ||
702 | * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, | ||
703 | * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, | ||
704 | * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT, | ||
705 | * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, | ||
706 | * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT | ||
707 | */ | ||
708 | #define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1 | ||
709 | #define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1 | ||
710 | #define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1) | ||
711 | |||
712 | /* Used by RM_ABE_AESS_CONTEXT */ | ||
713 | #define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8 | ||
714 | #define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1 | ||
715 | #define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8) | ||
716 | |||
717 | /* Used by RM_CAM_CAL_CONTEXT */ | ||
718 | #define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8 | ||
719 | #define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1 | ||
720 | #define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8) | ||
721 | |||
722 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ | ||
723 | #define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8 | ||
724 | #define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1 | ||
725 | #define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8) | ||
726 | |||
727 | /* Used by RM_EMIF_DMM_CONTEXT */ | ||
728 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9 | ||
729 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1 | ||
730 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9) | ||
731 | |||
732 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */ | ||
733 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8 | ||
734 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1 | ||
735 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8) | ||
736 | |||
737 | /* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */ | ||
738 | #define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8 | ||
739 | #define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1 | ||
740 | #define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) | ||
741 | |||
742 | /* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */ | ||
743 | #define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 | ||
744 | #define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1 | ||
745 | #define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) | ||
746 | |||
747 | /* Used by RM_DSP_DSP_CONTEXT */ | ||
748 | #define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10 | ||
749 | #define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1 | ||
750 | #define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10) | ||
751 | |||
752 | /* Used by RM_DSP_DSP_CONTEXT */ | ||
753 | #define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8 | ||
754 | #define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1 | ||
755 | #define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8) | ||
756 | |||
757 | /* Used by RM_DSP_DSP_CONTEXT */ | ||
758 | #define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9 | ||
759 | #define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1 | ||
760 | #define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9) | ||
761 | |||
762 | /* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */ | ||
763 | #define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8 | ||
764 | #define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1 | ||
765 | #define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8) | ||
766 | |||
767 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ | ||
768 | #define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8 | ||
769 | #define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1 | ||
770 | #define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8) | ||
771 | |||
772 | /* Used by RM_GPU_GPU_CONTEXT */ | ||
773 | #define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8 | ||
774 | #define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1 | ||
775 | #define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8) | ||
776 | |||
777 | /* Used by RM_IVA_IVA_CONTEXT */ | ||
778 | #define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10 | ||
779 | #define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1 | ||
780 | #define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10) | ||
781 | |||
782 | /* Used by RM_IPU_IPU_CONTEXT */ | ||
783 | #define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9 | ||
784 | #define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1 | ||
785 | #define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9) | ||
786 | |||
787 | /* Used by RM_IPU_IPU_CONTEXT */ | ||
788 | #define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8 | ||
789 | #define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1 | ||
790 | #define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8) | ||
791 | |||
792 | /* | ||
793 | * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, | ||
794 | * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, | ||
795 | * RM_L3INIT_USB_OTG_SS_CONTEXT | ||
796 | */ | ||
797 | #define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8 | ||
798 | #define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1 | ||
799 | #define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) | ||
800 | |||
801 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
802 | #define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9 | ||
803 | #define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1 | ||
804 | #define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9) | ||
805 | |||
806 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
807 | #define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10 | ||
808 | #define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1 | ||
809 | #define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10) | ||
810 | |||
811 | /* | ||
812 | * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, | ||
813 | * RM_L4SEC_FPKA_CONTEXT | ||
814 | */ | ||
815 | #define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8 | ||
816 | #define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1 | ||
817 | #define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) | ||
818 | |||
819 | /* | ||
820 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, | ||
821 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT | ||
822 | */ | ||
823 | #define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8 | ||
824 | #define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1 | ||
825 | #define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8) | ||
826 | |||
827 | /* | ||
828 | * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, | ||
829 | * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, | ||
830 | * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT | ||
831 | */ | ||
832 | #define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8 | ||
833 | #define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1 | ||
834 | #define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8) | ||
835 | |||
836 | /* Used by RM_IVA_SL2_CONTEXT */ | ||
837 | #define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8 | ||
838 | #define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1 | ||
839 | #define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8) | ||
840 | |||
841 | /* Used by RM_IVA_IVA_CONTEXT */ | ||
842 | #define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8 | ||
843 | #define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1 | ||
844 | #define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8) | ||
845 | |||
846 | /* Used by RM_IVA_IVA_CONTEXT */ | ||
847 | #define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9 | ||
848 | #define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1 | ||
849 | #define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9) | ||
850 | |||
851 | /* Used by RM_WKUPAON_SAR_RAM_CONTEXT */ | ||
852 | #define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8 | ||
853 | #define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1 | ||
854 | #define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8) | ||
855 | |||
856 | /* | ||
857 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, | ||
858 | * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, | ||
859 | * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL | ||
860 | */ | ||
861 | #define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4 | ||
862 | #define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1 | ||
863 | #define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4) | ||
864 | |||
865 | /* Used by PRM_DEBUG_TRANS_CFG */ | ||
866 | #define OMAP54XX_MODE_SHIFT 0 | ||
867 | #define OMAP54XX_MODE_WIDTH 0x2 | ||
868 | #define OMAP54XX_MODE_MASK (0x3 << 0) | ||
869 | |||
870 | /* Used by PRM_MODEM_IF_CTRL */ | ||
871 | #define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9 | ||
872 | #define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1 | ||
873 | #define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) | ||
874 | |||
875 | /* Used by PRM_MODEM_IF_CTRL */ | ||
876 | #define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8 | ||
877 | #define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1 | ||
878 | #define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8) | ||
879 | |||
880 | /* Used by PM_MPU_PWRSTCTRL */ | ||
881 | #define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18 | ||
882 | #define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2 | ||
883 | #define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18) | ||
884 | |||
885 | /* Used by PM_MPU_PWRSTCTRL */ | ||
886 | #define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9 | ||
887 | #define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1 | ||
888 | #define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9) | ||
889 | |||
890 | /* Used by PM_MPU_PWRSTST */ | ||
891 | #define OMAP54XX_MPU_L2_STATEST_SHIFT 6 | ||
892 | #define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2 | ||
893 | #define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6) | ||
894 | |||
895 | /* Used by PM_MPU_PWRSTCTRL */ | ||
896 | #define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20 | ||
897 | #define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2 | ||
898 | #define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20) | ||
899 | |||
900 | /* Used by PM_MPU_PWRSTCTRL */ | ||
901 | #define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10 | ||
902 | #define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1 | ||
903 | #define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10) | ||
904 | |||
905 | /* Used by PM_MPU_PWRSTST */ | ||
906 | #define OMAP54XX_MPU_RAM_STATEST_SHIFT 8 | ||
907 | #define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2 | ||
908 | #define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8) | ||
909 | |||
910 | /* Used by PRM_RSTST */ | ||
911 | #define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2 | ||
912 | #define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1 | ||
913 | #define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) | ||
914 | |||
915 | /* Used by PRM_RSTST */ | ||
916 | #define OMAP54XX_MPU_WDT_RST_SHIFT 3 | ||
917 | #define OMAP54XX_MPU_WDT_RST_WIDTH 0x1 | ||
918 | #define OMAP54XX_MPU_WDT_RST_MASK (1 << 3) | ||
919 | |||
920 | /* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ | ||
921 | #define OMAP54XX_NOCAP_SHIFT 4 | ||
922 | #define OMAP54XX_NOCAP_WIDTH 0x1 | ||
923 | #define OMAP54XX_NOCAP_MASK (1 << 4) | ||
924 | |||
925 | /* Used by PM_CORE_PWRSTCTRL */ | ||
926 | #define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24 | ||
927 | #define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2 | ||
928 | #define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) | ||
929 | |||
930 | /* Used by PM_CORE_PWRSTCTRL */ | ||
931 | #define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12 | ||
932 | #define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1 | ||
933 | #define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) | ||
934 | |||
935 | /* Used by PM_CORE_PWRSTST */ | ||
936 | #define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12 | ||
937 | #define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2 | ||
938 | #define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) | ||
939 | |||
940 | /* | ||
941 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, | ||
942 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
943 | */ | ||
944 | #define OMAP54XX_OFF_SHIFT 0 | ||
945 | #define OMAP54XX_OFF_WIDTH 0x8 | ||
946 | #define OMAP54XX_OFF_MASK (0xff << 0) | ||
947 | |||
948 | /* | ||
949 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, | ||
950 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
951 | */ | ||
952 | #define OMAP54XX_ON_SHIFT 24 | ||
953 | #define OMAP54XX_ON_WIDTH 0x8 | ||
954 | #define OMAP54XX_ON_MASK (0xff << 24) | ||
955 | |||
956 | /* | ||
957 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, | ||
958 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
959 | */ | ||
960 | #define OMAP54XX_ONLP_SHIFT 16 | ||
961 | #define OMAP54XX_ONLP_WIDTH 0x8 | ||
962 | #define OMAP54XX_ONLP_MASK (0xff << 16) | ||
963 | |||
964 | /* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ | ||
965 | #define OMAP54XX_OPP_CHANGE_SHIFT 2 | ||
966 | #define OMAP54XX_OPP_CHANGE_WIDTH 0x1 | ||
967 | #define OMAP54XX_OPP_CHANGE_MASK (1 << 2) | ||
968 | |||
969 | /* Used by PRM_VC_VAL_BYPASS */ | ||
970 | #define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25 | ||
971 | #define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1 | ||
972 | #define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25) | ||
973 | |||
974 | /* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ | ||
975 | #define OMAP54XX_OPP_SEL_SHIFT 0 | ||
976 | #define OMAP54XX_OPP_SEL_WIDTH 0x2 | ||
977 | #define OMAP54XX_OPP_SEL_MASK (0x3 << 0) | ||
978 | |||
979 | /* Used by PRM_DEBUG_OUT */ | ||
980 | #define OMAP54XX_OUTPUT_SHIFT 0 | ||
981 | #define OMAP54XX_OUTPUT_WIDTH 0x20 | ||
982 | #define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) | ||
983 | |||
984 | /* Used by PRM_SRAM_COUNT */ | ||
985 | #define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0 | ||
986 | #define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6 | ||
987 | #define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0) | ||
988 | |||
989 | /* Used by PRM_PSCON_COUNT */ | ||
990 | #define OMAP54XX_PCHARGE_TIME_SHIFT 0 | ||
991 | #define OMAP54XX_PCHARGE_TIME_WIDTH 0x8 | ||
992 | #define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0) | ||
993 | |||
994 | /* Used by PM_ABE_PWRSTCTRL */ | ||
995 | #define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20 | ||
996 | #define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2 | ||
997 | #define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20) | ||
998 | |||
999 | /* Used by PM_ABE_PWRSTCTRL */ | ||
1000 | #define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10 | ||
1001 | #define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1 | ||
1002 | #define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10) | ||
1003 | |||
1004 | /* Used by PM_ABE_PWRSTST */ | ||
1005 | #define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8 | ||
1006 | #define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2 | ||
1007 | #define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8) | ||
1008 | |||
1009 | /* Used by PRM_PHASE1_CNDP */ | ||
1010 | #define OMAP54XX_PHASE1_CNDP_SHIFT 0 | ||
1011 | #define OMAP54XX_PHASE1_CNDP_WIDTH 0x20 | ||
1012 | #define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0) | ||
1013 | |||
1014 | /* Used by PRM_PHASE2A_CNDP */ | ||
1015 | #define OMAP54XX_PHASE2A_CNDP_SHIFT 0 | ||
1016 | #define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20 | ||
1017 | #define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0) | ||
1018 | |||
1019 | /* Used by PRM_PHASE2B_CNDP */ | ||
1020 | #define OMAP54XX_PHASE2B_CNDP_SHIFT 0 | ||
1021 | #define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20 | ||
1022 | #define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0) | ||
1023 | |||
1024 | /* Used by PRM_PSCON_COUNT */ | ||
1025 | #define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8 | ||
1026 | #define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8 | ||
1027 | #define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) | ||
1028 | |||
1029 | /* | ||
1030 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, | ||
1031 | * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, | ||
1032 | * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, | ||
1033 | * PM_MPU_PWRSTCTRL | ||
1034 | */ | ||
1035 | #define OMAP54XX_POWERSTATE_SHIFT 0 | ||
1036 | #define OMAP54XX_POWERSTATE_WIDTH 0x2 | ||
1037 | #define OMAP54XX_POWERSTATE_MASK (0x3 << 0) | ||
1038 | |||
1039 | /* | ||
1040 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, | ||
1041 | * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, | ||
1042 | * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST | ||
1043 | */ | ||
1044 | #define OMAP54XX_POWERSTATEST_SHIFT 0 | ||
1045 | #define OMAP54XX_POWERSTATEST_WIDTH 0x2 | ||
1046 | #define OMAP54XX_POWERSTATEST_MASK (0x3 << 0) | ||
1047 | |||
1048 | /* Used by PRM_PWRREQCTRL */ | ||
1049 | #define OMAP54XX_PWRREQ_COND_SHIFT 0 | ||
1050 | #define OMAP54XX_PWRREQ_COND_WIDTH 0x2 | ||
1051 | #define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0) | ||
1052 | |||
1053 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ | ||
1054 | #define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27 | ||
1055 | #define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1 | ||
1056 | #define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27) | ||
1057 | |||
1058 | /* Used by PRM_VC_SMPS_MM_CONFIG */ | ||
1059 | #define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27 | ||
1060 | #define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1 | ||
1061 | #define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27) | ||
1062 | |||
1063 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ | ||
1064 | #define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27 | ||
1065 | #define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1 | ||
1066 | #define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27) | ||
1067 | |||
1068 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ | ||
1069 | #define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26 | ||
1070 | #define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1 | ||
1071 | #define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26) | ||
1072 | |||
1073 | /* Used by PRM_VC_SMPS_MM_CONFIG */ | ||
1074 | #define OMAP54XX_RAC_VDD_MM_L_SHIFT 26 | ||
1075 | #define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1 | ||
1076 | #define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26) | ||
1077 | |||
1078 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ | ||
1079 | #define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26 | ||
1080 | #define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1 | ||
1081 | #define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26) | ||
1082 | |||
1083 | /* | ||
1084 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
1085 | * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
1086 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
1087 | */ | ||
1088 | #define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16 | ||
1089 | #define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6 | ||
1090 | #define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16) | ||
1091 | |||
1092 | /* | ||
1093 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
1094 | * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
1095 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
1096 | */ | ||
1097 | #define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24 | ||
1098 | #define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2 | ||
1099 | #define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) | ||
1100 | |||
1101 | /* | ||
1102 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
1103 | * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
1104 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
1105 | */ | ||
1106 | #define OMAP54XX_RAMP_UP_COUNT_SHIFT 0 | ||
1107 | #define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6 | ||
1108 | #define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0) | ||
1109 | |||
1110 | /* | ||
1111 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
1112 | * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
1113 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
1114 | */ | ||
1115 | #define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8 | ||
1116 | #define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2 | ||
1117 | #define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8) | ||
1118 | |||
1119 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ | ||
1120 | #define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25 | ||
1121 | #define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1 | ||
1122 | #define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25) | ||
1123 | |||
1124 | /* Used by PRM_VC_SMPS_MM_CONFIG */ | ||
1125 | #define OMAP54XX_RAV_VDD_MM_L_SHIFT 25 | ||
1126 | #define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1 | ||
1127 | #define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25) | ||
1128 | |||
1129 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ | ||
1130 | #define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25 | ||
1131 | #define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1 | ||
1132 | #define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25) | ||
1133 | |||
1134 | /* Used by PRM_VC_VAL_BYPASS */ | ||
1135 | #define OMAP54XX_REGADDR_SHIFT 8 | ||
1136 | #define OMAP54XX_REGADDR_WIDTH 0x8 | ||
1137 | #define OMAP54XX_REGADDR_MASK (0xff << 8) | ||
1138 | |||
1139 | /* | ||
1140 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, | ||
1141 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
1142 | */ | ||
1143 | #define OMAP54XX_RET_SHIFT 8 | ||
1144 | #define OMAP54XX_RET_WIDTH 0x8 | ||
1145 | #define OMAP54XX_RET_MASK (0xff << 8) | ||
1146 | |||
1147 | /* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ | ||
1148 | #define OMAP54XX_RETMODE_ENABLE_SHIFT 0 | ||
1149 | #define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1 | ||
1150 | #define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0) | ||
1151 | |||
1152 | /* Used by PRM_RSTTIME */ | ||
1153 | #define OMAP54XX_RSTTIME1_SHIFT 0 | ||
1154 | #define OMAP54XX_RSTTIME1_WIDTH 0xa | ||
1155 | #define OMAP54XX_RSTTIME1_MASK (0x3ff << 0) | ||
1156 | |||
1157 | /* Used by PRM_RSTTIME */ | ||
1158 | #define OMAP54XX_RSTTIME2_SHIFT 10 | ||
1159 | #define OMAP54XX_RSTTIME2_WIDTH 0x5 | ||
1160 | #define OMAP54XX_RSTTIME2_MASK (0x1f << 10) | ||
1161 | |||
1162 | /* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ | ||
1163 | #define OMAP54XX_RST_CPU0_SHIFT 0 | ||
1164 | #define OMAP54XX_RST_CPU0_WIDTH 0x1 | ||
1165 | #define OMAP54XX_RST_CPU0_MASK (1 << 0) | ||
1166 | |||
1167 | /* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ | ||
1168 | #define OMAP54XX_RST_CPU1_SHIFT 1 | ||
1169 | #define OMAP54XX_RST_CPU1_WIDTH 0x1 | ||
1170 | #define OMAP54XX_RST_CPU1_MASK (1 << 1) | ||
1171 | |||
1172 | /* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ | ||
1173 | #define OMAP54XX_RST_DSP_SHIFT 0 | ||
1174 | #define OMAP54XX_RST_DSP_WIDTH 0x1 | ||
1175 | #define OMAP54XX_RST_DSP_MASK (1 << 0) | ||
1176 | |||
1177 | /* Used by RM_DSP_RSTST */ | ||
1178 | #define OMAP54XX_RST_DSP_EMU_SHIFT 2 | ||
1179 | #define OMAP54XX_RST_DSP_EMU_WIDTH 0x1 | ||
1180 | #define OMAP54XX_RST_DSP_EMU_MASK (1 << 2) | ||
1181 | |||
1182 | /* Used by RM_DSP_RSTST */ | ||
1183 | #define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3 | ||
1184 | #define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1 | ||
1185 | #define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3) | ||
1186 | |||
1187 | /* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ | ||
1188 | #define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1 | ||
1189 | #define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1 | ||
1190 | #define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1) | ||
1191 | |||
1192 | /* Used by RM_IPU_RSTST */ | ||
1193 | #define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3 | ||
1194 | #define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1 | ||
1195 | #define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3) | ||
1196 | |||
1197 | /* Used by RM_IPU_RSTST */ | ||
1198 | #define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4 | ||
1199 | #define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1 | ||
1200 | #define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4) | ||
1201 | |||
1202 | /* Used by RM_IVA_RSTST */ | ||
1203 | #define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3 | ||
1204 | #define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1 | ||
1205 | #define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3) | ||
1206 | |||
1207 | /* Used by RM_IVA_RSTST */ | ||
1208 | #define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4 | ||
1209 | #define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1 | ||
1210 | #define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4) | ||
1211 | |||
1212 | /* Used by PRM_RSTCTRL */ | ||
1213 | #define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1 | ||
1214 | #define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1 | ||
1215 | #define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) | ||
1216 | |||
1217 | /* Used by PRM_RSTCTRL */ | ||
1218 | #define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0 | ||
1219 | #define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1 | ||
1220 | #define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) | ||
1221 | |||
1222 | /* Used by RM_IPU_RSTST */ | ||
1223 | #define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5 | ||
1224 | #define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1 | ||
1225 | #define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5) | ||
1226 | |||
1227 | /* Used by RM_IPU_RSTST */ | ||
1228 | #define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6 | ||
1229 | #define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1 | ||
1230 | #define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6) | ||
1231 | |||
1232 | /* Used by RM_IVA_RSTST */ | ||
1233 | #define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5 | ||
1234 | #define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1 | ||
1235 | #define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5) | ||
1236 | |||
1237 | /* Used by RM_IVA_RSTST */ | ||
1238 | #define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6 | ||
1239 | #define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1 | ||
1240 | #define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6) | ||
1241 | |||
1242 | /* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ | ||
1243 | #define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2 | ||
1244 | #define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1 | ||
1245 | #define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2) | ||
1246 | |||
1247 | /* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ | ||
1248 | #define OMAP54XX_RST_LOGIC_SHIFT 2 | ||
1249 | #define OMAP54XX_RST_LOGIC_WIDTH 0x1 | ||
1250 | #define OMAP54XX_RST_LOGIC_MASK (1 << 2) | ||
1251 | |||
1252 | /* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ | ||
1253 | #define OMAP54XX_RST_SEQ1_SHIFT 0 | ||
1254 | #define OMAP54XX_RST_SEQ1_WIDTH 0x1 | ||
1255 | #define OMAP54XX_RST_SEQ1_MASK (1 << 0) | ||
1256 | |||
1257 | /* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ | ||
1258 | #define OMAP54XX_RST_SEQ2_SHIFT 1 | ||
1259 | #define OMAP54XX_RST_SEQ2_WIDTH 0x1 | ||
1260 | #define OMAP54XX_RST_SEQ2_MASK (1 << 1) | ||
1261 | |||
1262 | /* Used by REVISION_PRM */ | ||
1263 | #define OMAP54XX_R_RTL_SHIFT 11 | ||
1264 | #define OMAP54XX_R_RTL_WIDTH 0x5 | ||
1265 | #define OMAP54XX_R_RTL_MASK (0x1f << 11) | ||
1266 | |||
1267 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ | ||
1268 | #define OMAP54XX_SA_VDD_CORE_L_SHIFT 0 | ||
1269 | #define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7 | ||
1270 | #define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0) | ||
1271 | |||
1272 | /* Used by PRM_VC_SMPS_MM_CONFIG */ | ||
1273 | #define OMAP54XX_SA_VDD_MM_L_SHIFT 0 | ||
1274 | #define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7 | ||
1275 | #define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0) | ||
1276 | |||
1277 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ | ||
1278 | #define OMAP54XX_SA_VDD_MPU_L_SHIFT 0 | ||
1279 | #define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7 | ||
1280 | #define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0) | ||
1281 | |||
1282 | /* Used by REVISION_PRM */ | ||
1283 | #define OMAP54XX_SCHEME_SHIFT 30 | ||
1284 | #define OMAP54XX_SCHEME_WIDTH 0x2 | ||
1285 | #define OMAP54XX_SCHEME_MASK (0x3 << 30) | ||
1286 | |||
1287 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
1288 | #define OMAP54XX_SCLH_SHIFT 0 | ||
1289 | #define OMAP54XX_SCLH_WIDTH 0x8 | ||
1290 | #define OMAP54XX_SCLH_MASK (0xff << 0) | ||
1291 | |||
1292 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
1293 | #define OMAP54XX_SCLL_SHIFT 8 | ||
1294 | #define OMAP54XX_SCLL_WIDTH 0x8 | ||
1295 | #define OMAP54XX_SCLL_MASK (0xff << 8) | ||
1296 | |||
1297 | /* Used by PRM_RSTST */ | ||
1298 | #define OMAP54XX_SECURE_WDT_RST_SHIFT 4 | ||
1299 | #define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1 | ||
1300 | #define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4) | ||
1301 | |||
1302 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ | ||
1303 | #define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24 | ||
1304 | #define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1 | ||
1305 | #define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24) | ||
1306 | |||
1307 | /* Used by PRM_VC_SMPS_MM_CONFIG */ | ||
1308 | #define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24 | ||
1309 | #define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1 | ||
1310 | #define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24) | ||
1311 | |||
1312 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ | ||
1313 | #define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24 | ||
1314 | #define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1 | ||
1315 | #define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24) | ||
1316 | |||
1317 | /* Used by PM_IVA_PWRSTCTRL */ | ||
1318 | #define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18 | ||
1319 | #define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2 | ||
1320 | #define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18) | ||
1321 | |||
1322 | /* Used by PM_IVA_PWRSTCTRL */ | ||
1323 | #define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9 | ||
1324 | #define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1 | ||
1325 | #define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9) | ||
1326 | |||
1327 | /* Used by PM_IVA_PWRSTST */ | ||
1328 | #define OMAP54XX_SL2_MEM_STATEST_SHIFT 6 | ||
1329 | #define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2 | ||
1330 | #define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6) | ||
1331 | |||
1332 | /* Used by PRM_VC_VAL_BYPASS */ | ||
1333 | #define OMAP54XX_SLAVEADDR_SHIFT 0 | ||
1334 | #define OMAP54XX_SLAVEADDR_WIDTH 0x7 | ||
1335 | #define OMAP54XX_SLAVEADDR_MASK (0x7f << 0) | ||
1336 | |||
1337 | /* Used by PRM_SRAM_COUNT */ | ||
1338 | #define OMAP54XX_SLPCNT_VALUE_SHIFT 16 | ||
1339 | #define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8 | ||
1340 | #define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16) | ||
1341 | |||
1342 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | ||
1343 | #define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8 | ||
1344 | #define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10 | ||
1345 | #define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8) | ||
1346 | |||
1347 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | ||
1348 | #define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8 | ||
1349 | #define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10 | ||
1350 | #define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8) | ||
1351 | |||
1352 | /* Used by PRM_VC_CORE_ERRST */ | ||
1353 | #define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1 | ||
1354 | #define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1 | ||
1355 | #define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1) | ||
1356 | |||
1357 | /* Used by PRM_VC_MM_ERRST */ | ||
1358 | #define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1 | ||
1359 | #define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1 | ||
1360 | #define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1) | ||
1361 | |||
1362 | /* Used by PRM_VC_MPU_ERRST */ | ||
1363 | #define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1 | ||
1364 | #define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1 | ||
1365 | #define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1) | ||
1366 | |||
1367 | /* Used by PRM_VC_CORE_ERRST */ | ||
1368 | #define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0 | ||
1369 | #define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1 | ||
1370 | #define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0) | ||
1371 | |||
1372 | /* Used by PRM_VC_MM_ERRST */ | ||
1373 | #define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0 | ||
1374 | #define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1 | ||
1375 | #define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0) | ||
1376 | |||
1377 | /* Used by PRM_VC_MPU_ERRST */ | ||
1378 | #define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0 | ||
1379 | #define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1 | ||
1380 | #define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0) | ||
1381 | |||
1382 | /* Used by PRM_VC_CORE_ERRST */ | ||
1383 | #define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 | ||
1384 | #define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1 | ||
1385 | #define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) | ||
1386 | |||
1387 | /* Used by PRM_VC_MM_ERRST */ | ||
1388 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2 | ||
1389 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1 | ||
1390 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2) | ||
1391 | |||
1392 | /* Used by PRM_VC_MPU_ERRST */ | ||
1393 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2 | ||
1394 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1 | ||
1395 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2) | ||
1396 | |||
1397 | /* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ | ||
1398 | #define OMAP54XX_SR2EN_SHIFT 0 | ||
1399 | #define OMAP54XX_SR2EN_WIDTH 0x1 | ||
1400 | #define OMAP54XX_SR2EN_MASK (1 << 0) | ||
1401 | |||
1402 | /* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ | ||
1403 | #define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6 | ||
1404 | #define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1 | ||
1405 | #define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6) | ||
1406 | |||
1407 | /* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ | ||
1408 | #define OMAP54XX_SR2_STATUS_SHIFT 3 | ||
1409 | #define OMAP54XX_SR2_STATUS_WIDTH 0x2 | ||
1410 | #define OMAP54XX_SR2_STATUS_MASK (0x3 << 3) | ||
1411 | |||
1412 | /* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ | ||
1413 | #define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8 | ||
1414 | #define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8 | ||
1415 | #define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8) | ||
1416 | |||
1417 | /* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ | ||
1418 | #define OMAP54XX_SRAMLDO_STATUS_SHIFT 8 | ||
1419 | #define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1 | ||
1420 | #define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8) | ||
1421 | |||
1422 | /* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ | ||
1423 | #define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9 | ||
1424 | #define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1 | ||
1425 | #define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9) | ||
1426 | |||
1427 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
1428 | #define OMAP54XX_SRMODEEN_SHIFT 4 | ||
1429 | #define OMAP54XX_SRMODEEN_WIDTH 0x1 | ||
1430 | #define OMAP54XX_SRMODEEN_MASK (1 << 4) | ||
1431 | |||
1432 | /* Used by PRM_VOLTSETUP_WARMRESET */ | ||
1433 | #define OMAP54XX_STABLE_COUNT_SHIFT 0 | ||
1434 | #define OMAP54XX_STABLE_COUNT_WIDTH 0x6 | ||
1435 | #define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0) | ||
1436 | |||
1437 | /* Used by PRM_VOLTSETUP_WARMRESET */ | ||
1438 | #define OMAP54XX_STABLE_PRESCAL_SHIFT 8 | ||
1439 | #define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2 | ||
1440 | #define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8) | ||
1441 | |||
1442 | /* Used by PRM_BANDGAP_SETUP */ | ||
1443 | #define OMAP54XX_STARTUP_COUNT_SHIFT 0 | ||
1444 | #define OMAP54XX_STARTUP_COUNT_WIDTH 0x8 | ||
1445 | #define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0) | ||
1446 | |||
1447 | /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ | ||
1448 | #define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24 | ||
1449 | #define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8 | ||
1450 | #define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24) | ||
1451 | |||
1452 | /* Used by PM_IVA_PWRSTCTRL */ | ||
1453 | #define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20 | ||
1454 | #define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2 | ||
1455 | #define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20) | ||
1456 | |||
1457 | /* Used by PM_IVA_PWRSTCTRL */ | ||
1458 | #define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10 | ||
1459 | #define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1 | ||
1460 | #define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10) | ||
1461 | |||
1462 | /* Used by PM_IVA_PWRSTST */ | ||
1463 | #define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8 | ||
1464 | #define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2 | ||
1465 | #define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8) | ||
1466 | |||
1467 | /* Used by PM_IVA_PWRSTCTRL */ | ||
1468 | #define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22 | ||
1469 | #define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2 | ||
1470 | #define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22) | ||
1471 | |||
1472 | /* Used by PM_IVA_PWRSTCTRL */ | ||
1473 | #define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11 | ||
1474 | #define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1 | ||
1475 | #define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11) | ||
1476 | |||
1477 | /* Used by PM_IVA_PWRSTST */ | ||
1478 | #define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10 | ||
1479 | #define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2 | ||
1480 | #define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10) | ||
1481 | |||
1482 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1483 | #define OMAP54XX_TIMEOUT_SHIFT 0 | ||
1484 | #define OMAP54XX_TIMEOUT_WIDTH 0x10 | ||
1485 | #define OMAP54XX_TIMEOUT_MASK (0xffff << 0) | ||
1486 | |||
1487 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ | ||
1488 | #define OMAP54XX_TIMEOUTEN_SHIFT 3 | ||
1489 | #define OMAP54XX_TIMEOUTEN_WIDTH 0x1 | ||
1490 | #define OMAP54XX_TIMEOUTEN_MASK (1 << 3) | ||
1491 | |||
1492 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1493 | #define OMAP54XX_TRANSITION_EN_SHIFT 8 | ||
1494 | #define OMAP54XX_TRANSITION_EN_WIDTH 0x1 | ||
1495 | #define OMAP54XX_TRANSITION_EN_MASK (1 << 8) | ||
1496 | |||
1497 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1498 | #define OMAP54XX_TRANSITION_ST_SHIFT 8 | ||
1499 | #define OMAP54XX_TRANSITION_ST_WIDTH 0x1 | ||
1500 | #define OMAP54XX_TRANSITION_ST_MASK (1 << 8) | ||
1501 | |||
1502 | /* Used by PRM_DEBUG_TRANS_CFG */ | ||
1503 | #define OMAP54XX_TRIGGER_CLEAR_SHIFT 2 | ||
1504 | #define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1 | ||
1505 | #define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2) | ||
1506 | |||
1507 | /* Used by PRM_RSTST */ | ||
1508 | #define OMAP54XX_TSHUT_CORE_RST_SHIFT 13 | ||
1509 | #define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1 | ||
1510 | #define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13) | ||
1511 | |||
1512 | /* Used by PRM_RSTST */ | ||
1513 | #define OMAP54XX_TSHUT_MM_RST_SHIFT 12 | ||
1514 | #define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1 | ||
1515 | #define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12) | ||
1516 | |||
1517 | /* Used by PRM_RSTST */ | ||
1518 | #define OMAP54XX_TSHUT_MPU_RST_SHIFT 11 | ||
1519 | #define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1 | ||
1520 | #define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11) | ||
1521 | |||
1522 | /* Used by PRM_VC_VAL_BYPASS */ | ||
1523 | #define OMAP54XX_VALID_SHIFT 24 | ||
1524 | #define OMAP54XX_VALID_WIDTH 0x1 | ||
1525 | #define OMAP54XX_VALID_MASK (1 << 24) | ||
1526 | |||
1527 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1528 | #define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14 | ||
1529 | #define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1 | ||
1530 | #define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14) | ||
1531 | |||
1532 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1533 | #define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14 | ||
1534 | #define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1 | ||
1535 | #define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14) | ||
1536 | |||
1537 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1538 | #define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22 | ||
1539 | #define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1 | ||
1540 | #define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22) | ||
1541 | |||
1542 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1543 | #define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22 | ||
1544 | #define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1 | ||
1545 | #define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22) | ||
1546 | |||
1547 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1548 | #define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30 | ||
1549 | #define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1 | ||
1550 | #define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30) | ||
1551 | |||
1552 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1553 | #define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30 | ||
1554 | #define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1 | ||
1555 | #define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30) | ||
1556 | |||
1557 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1558 | #define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6 | ||
1559 | #define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1 | ||
1560 | #define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6) | ||
1561 | |||
1562 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1563 | #define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6 | ||
1564 | #define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1 | ||
1565 | #define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6) | ||
1566 | |||
1567 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1568 | #define OMAP54XX_VC_RAERR_EN_SHIFT 12 | ||
1569 | #define OMAP54XX_VC_RAERR_EN_WIDTH 0x1 | ||
1570 | #define OMAP54XX_VC_RAERR_EN_MASK (1 << 12) | ||
1571 | |||
1572 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1573 | #define OMAP54XX_VC_RAERR_ST_SHIFT 12 | ||
1574 | #define OMAP54XX_VC_RAERR_ST_WIDTH 0x1 | ||
1575 | #define OMAP54XX_VC_RAERR_ST_MASK (1 << 12) | ||
1576 | |||
1577 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1578 | #define OMAP54XX_VC_SAERR_EN_SHIFT 11 | ||
1579 | #define OMAP54XX_VC_SAERR_EN_WIDTH 0x1 | ||
1580 | #define OMAP54XX_VC_SAERR_EN_MASK (1 << 11) | ||
1581 | |||
1582 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1583 | #define OMAP54XX_VC_SAERR_ST_SHIFT 11 | ||
1584 | #define OMAP54XX_VC_SAERR_ST_WIDTH 0x1 | ||
1585 | #define OMAP54XX_VC_SAERR_ST_MASK (1 << 11) | ||
1586 | |||
1587 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1588 | #define OMAP54XX_VC_TOERR_EN_SHIFT 13 | ||
1589 | #define OMAP54XX_VC_TOERR_EN_WIDTH 0x1 | ||
1590 | #define OMAP54XX_VC_TOERR_EN_MASK (1 << 13) | ||
1591 | |||
1592 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1593 | #define OMAP54XX_VC_TOERR_ST_SHIFT 13 | ||
1594 | #define OMAP54XX_VC_TOERR_ST_WIDTH 0x1 | ||
1595 | #define OMAP54XX_VC_TOERR_ST_MASK (1 << 13) | ||
1596 | |||
1597 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1598 | #define OMAP54XX_VDDMAX_SHIFT 24 | ||
1599 | #define OMAP54XX_VDDMAX_WIDTH 0x8 | ||
1600 | #define OMAP54XX_VDDMAX_MASK (0xff << 24) | ||
1601 | |||
1602 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
1603 | #define OMAP54XX_VDDMIN_SHIFT 16 | ||
1604 | #define OMAP54XX_VDDMIN_WIDTH 0x8 | ||
1605 | #define OMAP54XX_VDDMIN_MASK (0xff << 16) | ||
1606 | |||
1607 | /* Used by PRM_VOLTCTRL */ | ||
1608 | #define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12 | ||
1609 | #define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1 | ||
1610 | #define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12) | ||
1611 | |||
1612 | /* Used by PRM_RSTST */ | ||
1613 | #define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8 | ||
1614 | #define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1 | ||
1615 | #define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) | ||
1616 | |||
1617 | /* Used by PRM_VOLTCTRL */ | ||
1618 | #define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14 | ||
1619 | #define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1 | ||
1620 | #define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14) | ||
1621 | |||
1622 | /* Used by PRM_VOLTCTRL */ | ||
1623 | #define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9 | ||
1624 | #define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1 | ||
1625 | #define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9) | ||
1626 | |||
1627 | /* Used by PRM_RSTST */ | ||
1628 | #define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7 | ||
1629 | #define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1 | ||
1630 | #define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7) | ||
1631 | |||
1632 | /* Used by PRM_VOLTCTRL */ | ||
1633 | #define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13 | ||
1634 | #define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1 | ||
1635 | #define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13) | ||
1636 | |||
1637 | /* Used by PRM_VOLTCTRL */ | ||
1638 | #define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8 | ||
1639 | #define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1 | ||
1640 | #define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8) | ||
1641 | |||
1642 | /* Used by PRM_RSTST */ | ||
1643 | #define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6 | ||
1644 | #define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1 | ||
1645 | #define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) | ||
1646 | |||
1647 | /* Used by PRM_VC_CORE_ERRST */ | ||
1648 | #define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4 | ||
1649 | #define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1 | ||
1650 | #define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4) | ||
1651 | |||
1652 | /* Used by PRM_VC_MM_ERRST */ | ||
1653 | #define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4 | ||
1654 | #define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1 | ||
1655 | #define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4) | ||
1656 | |||
1657 | /* Used by PRM_VC_MPU_ERRST */ | ||
1658 | #define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4 | ||
1659 | #define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1 | ||
1660 | #define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4) | ||
1661 | |||
1662 | /* Used by PRM_VC_CORE_ERRST */ | ||
1663 | #define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3 | ||
1664 | #define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1 | ||
1665 | #define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3) | ||
1666 | |||
1667 | /* Used by PRM_VC_MM_ERRST */ | ||
1668 | #define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3 | ||
1669 | #define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1 | ||
1670 | #define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3) | ||
1671 | |||
1672 | /* Used by PRM_VC_MPU_ERRST */ | ||
1673 | #define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3 | ||
1674 | #define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1 | ||
1675 | #define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3) | ||
1676 | |||
1677 | /* Used by PRM_VC_CORE_ERRST */ | ||
1678 | #define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 | ||
1679 | #define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1 | ||
1680 | #define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) | ||
1681 | |||
1682 | /* Used by PRM_VC_MM_ERRST */ | ||
1683 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5 | ||
1684 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1 | ||
1685 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5) | ||
1686 | |||
1687 | /* Used by PRM_VC_MPU_ERRST */ | ||
1688 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5 | ||
1689 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1 | ||
1690 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5) | ||
1691 | |||
1692 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ | ||
1693 | #define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8 | ||
1694 | #define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8 | ||
1695 | #define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8) | ||
1696 | |||
1697 | /* Used by PRM_VC_SMPS_MM_CONFIG */ | ||
1698 | #define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8 | ||
1699 | #define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8 | ||
1700 | #define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8) | ||
1701 | |||
1702 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ | ||
1703 | #define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8 | ||
1704 | #define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8 | ||
1705 | #define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8) | ||
1706 | |||
1707 | /* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */ | ||
1708 | #define OMAP54XX_VOLTSTATEST_SHIFT 0 | ||
1709 | #define OMAP54XX_VOLTSTATEST_WIDTH 0x2 | ||
1710 | #define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0) | ||
1711 | |||
1712 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ | ||
1713 | #define OMAP54XX_VPENABLE_SHIFT 0 | ||
1714 | #define OMAP54XX_VPENABLE_WIDTH 0x1 | ||
1715 | #define OMAP54XX_VPENABLE_MASK (1 << 0) | ||
1716 | |||
1717 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */ | ||
1718 | #define OMAP54XX_VPINIDLE_SHIFT 0 | ||
1719 | #define OMAP54XX_VPINIDLE_WIDTH 0x1 | ||
1720 | #define OMAP54XX_VPINIDLE_MASK (1 << 0) | ||
1721 | |||
1722 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | ||
1723 | #define OMAP54XX_VPVOLTAGE_SHIFT 0 | ||
1724 | #define OMAP54XX_VPVOLTAGE_WIDTH 0x8 | ||
1725 | #define OMAP54XX_VPVOLTAGE_MASK (0xff << 0) | ||
1726 | |||
1727 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1728 | #define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20 | ||
1729 | #define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1 | ||
1730 | #define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20) | ||
1731 | |||
1732 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1733 | #define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20 | ||
1734 | #define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1 | ||
1735 | #define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20) | ||
1736 | |||
1737 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1738 | #define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18 | ||
1739 | #define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1 | ||
1740 | #define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18) | ||
1741 | |||
1742 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1743 | #define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18 | ||
1744 | #define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1 | ||
1745 | #define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18) | ||
1746 | |||
1747 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1748 | #define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17 | ||
1749 | #define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1 | ||
1750 | #define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17) | ||
1751 | |||
1752 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1753 | #define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17 | ||
1754 | #define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1 | ||
1755 | #define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17) | ||
1756 | |||
1757 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1758 | #define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19 | ||
1759 | #define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1 | ||
1760 | #define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) | ||
1761 | |||
1762 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1763 | #define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19 | ||
1764 | #define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1 | ||
1765 | #define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) | ||
1766 | |||
1767 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1768 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 | ||
1769 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1 | ||
1770 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) | ||
1771 | |||
1772 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1773 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 | ||
1774 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1 | ||
1775 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) | ||
1776 | |||
1777 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1778 | #define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21 | ||
1779 | #define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1 | ||
1780 | #define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21) | ||
1781 | |||
1782 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1783 | #define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21 | ||
1784 | #define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1 | ||
1785 | #define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21) | ||
1786 | |||
1787 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1788 | #define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28 | ||
1789 | #define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1 | ||
1790 | #define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28) | ||
1791 | |||
1792 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1793 | #define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28 | ||
1794 | #define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1 | ||
1795 | #define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28) | ||
1796 | |||
1797 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1798 | #define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26 | ||
1799 | #define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1 | ||
1800 | #define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26) | ||
1801 | |||
1802 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1803 | #define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26 | ||
1804 | #define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1 | ||
1805 | #define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26) | ||
1806 | |||
1807 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1808 | #define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25 | ||
1809 | #define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1 | ||
1810 | #define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25) | ||
1811 | |||
1812 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1813 | #define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25 | ||
1814 | #define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1 | ||
1815 | #define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25) | ||
1816 | |||
1817 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1818 | #define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27 | ||
1819 | #define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1 | ||
1820 | #define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27) | ||
1821 | |||
1822 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1823 | #define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27 | ||
1824 | #define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1 | ||
1825 | #define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27) | ||
1826 | |||
1827 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1828 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24 | ||
1829 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1 | ||
1830 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24) | ||
1831 | |||
1832 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1833 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24 | ||
1834 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1 | ||
1835 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24) | ||
1836 | |||
1837 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ | ||
1838 | #define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29 | ||
1839 | #define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1 | ||
1840 | #define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29) | ||
1841 | |||
1842 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ | ||
1843 | #define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29 | ||
1844 | #define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1 | ||
1845 | #define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29) | ||
1846 | |||
1847 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1848 | #define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4 | ||
1849 | #define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1 | ||
1850 | #define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4) | ||
1851 | |||
1852 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1853 | #define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4 | ||
1854 | #define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1 | ||
1855 | #define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4) | ||
1856 | |||
1857 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1858 | #define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2 | ||
1859 | #define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1 | ||
1860 | #define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2) | ||
1861 | |||
1862 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1863 | #define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2 | ||
1864 | #define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1 | ||
1865 | #define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2) | ||
1866 | |||
1867 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1868 | #define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1 | ||
1869 | #define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1 | ||
1870 | #define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1) | ||
1871 | |||
1872 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1873 | #define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1 | ||
1874 | #define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1 | ||
1875 | #define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1) | ||
1876 | |||
1877 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1878 | #define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3 | ||
1879 | #define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1 | ||
1880 | #define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) | ||
1881 | |||
1882 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1883 | #define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3 | ||
1884 | #define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1 | ||
1885 | #define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) | ||
1886 | |||
1887 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1888 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 | ||
1889 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1 | ||
1890 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) | ||
1891 | |||
1892 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1893 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 | ||
1894 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1 | ||
1895 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) | ||
1896 | |||
1897 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
1898 | #define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5 | ||
1899 | #define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1 | ||
1900 | #define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5) | ||
1901 | |||
1902 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
1903 | #define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5 | ||
1904 | #define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1 | ||
1905 | #define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5) | ||
1906 | |||
1907 | /* Used by PRM_SRAM_COUNT */ | ||
1908 | #define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8 | ||
1909 | #define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8 | ||
1910 | #define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8) | ||
1911 | |||
1912 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | ||
1913 | #define OMAP54XX_VSTEPMAX_SHIFT 0 | ||
1914 | #define OMAP54XX_VSTEPMAX_WIDTH 0x8 | ||
1915 | #define OMAP54XX_VSTEPMAX_MASK (0xff << 0) | ||
1916 | |||
1917 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | ||
1918 | #define OMAP54XX_VSTEPMIN_SHIFT 0 | ||
1919 | #define OMAP54XX_VSTEPMIN_WIDTH 0x8 | ||
1920 | #define OMAP54XX_VSTEPMIN_MASK (0xff << 0) | ||
1921 | |||
1922 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1923 | #define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2 | ||
1924 | #define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1 | ||
1925 | #define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2) | ||
1926 | |||
1927 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1928 | #define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1 | ||
1929 | #define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1 | ||
1930 | #define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1) | ||
1931 | |||
1932 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1933 | #define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0 | ||
1934 | #define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1 | ||
1935 | #define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0) | ||
1936 | |||
1937 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1938 | #define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3 | ||
1939 | #define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1 | ||
1940 | #define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3) | ||
1941 | |||
1942 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1943 | #define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6 | ||
1944 | #define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1 | ||
1945 | #define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6) | ||
1946 | |||
1947 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1948 | #define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 | ||
1949 | #define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1 | ||
1950 | #define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) | ||
1951 | |||
1952 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1953 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2 | ||
1954 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1 | ||
1955 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2) | ||
1956 | |||
1957 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
1958 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 | ||
1959 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1 | ||
1960 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) | ||
1961 | |||
1962 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1963 | #define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6 | ||
1964 | #define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1 | ||
1965 | #define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6) | ||
1966 | |||
1967 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1968 | #define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5 | ||
1969 | #define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1 | ||
1970 | #define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5) | ||
1971 | |||
1972 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1973 | #define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4 | ||
1974 | #define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1 | ||
1975 | #define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4) | ||
1976 | |||
1977 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1978 | #define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7 | ||
1979 | #define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1 | ||
1980 | #define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7) | ||
1981 | |||
1982 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1983 | #define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10 | ||
1984 | #define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1 | ||
1985 | #define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10) | ||
1986 | |||
1987 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1988 | #define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9 | ||
1989 | #define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1 | ||
1990 | #define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9) | ||
1991 | |||
1992 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1993 | #define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8 | ||
1994 | #define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1 | ||
1995 | #define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8) | ||
1996 | |||
1997 | /* Used by PM_DSS_DSS_WKDEP */ | ||
1998 | #define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11 | ||
1999 | #define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1 | ||
2000 | #define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11) | ||
2001 | |||
2002 | /* Used by PM_DSS_DSS_WKDEP */ | ||
2003 | #define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17 | ||
2004 | #define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1 | ||
2005 | #define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17) | ||
2006 | |||
2007 | /* Used by PM_DSS_DSS_WKDEP */ | ||
2008 | #define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16 | ||
2009 | #define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1 | ||
2010 | #define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16) | ||
2011 | |||
2012 | /* Used by PM_DSS_DSS_WKDEP */ | ||
2013 | #define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15 | ||
2014 | #define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1 | ||
2015 | #define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15) | ||
2016 | |||
2017 | /* Used by PM_DSS_DSS_WKDEP */ | ||
2018 | #define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18 | ||
2019 | #define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1 | ||
2020 | #define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18) | ||
2021 | |||
2022 | /* Used by PM_WKUPAON_GPIO1_WKDEP */ | ||
2023 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1 | ||
2024 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1 | ||
2025 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1) | ||
2026 | |||
2027 | /* Used by PM_WKUPAON_GPIO1_WKDEP */ | ||
2028 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 | ||
2029 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1 | ||
2030 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) | ||
2031 | |||
2032 | /* Used by PM_WKUPAON_GPIO1_WKDEP */ | ||
2033 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6 | ||
2034 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1 | ||
2035 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6) | ||
2036 | |||
2037 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
2038 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1 | ||
2039 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1 | ||
2040 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1) | ||
2041 | |||
2042 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
2043 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 | ||
2044 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1 | ||
2045 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) | ||
2046 | |||
2047 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
2048 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6 | ||
2049 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1 | ||
2050 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6) | ||
2051 | |||
2052 | /* Used by PM_L4PER_GPIO3_WKDEP */ | ||
2053 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 | ||
2054 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1 | ||
2055 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) | ||
2056 | |||
2057 | /* Used by PM_L4PER_GPIO3_WKDEP */ | ||
2058 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6 | ||
2059 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1 | ||
2060 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6) | ||
2061 | |||
2062 | /* Used by PM_L4PER_GPIO4_WKDEP */ | ||
2063 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 | ||
2064 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1 | ||
2065 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) | ||
2066 | |||
2067 | /* Used by PM_L4PER_GPIO4_WKDEP */ | ||
2068 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6 | ||
2069 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1 | ||
2070 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6) | ||
2071 | |||
2072 | /* Used by PM_L4PER_GPIO5_WKDEP */ | ||
2073 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 | ||
2074 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1 | ||
2075 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) | ||
2076 | |||
2077 | /* Used by PM_L4PER_GPIO5_WKDEP */ | ||
2078 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6 | ||
2079 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1 | ||
2080 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6) | ||
2081 | |||
2082 | /* Used by PM_L4PER_GPIO6_WKDEP */ | ||
2083 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 | ||
2084 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1 | ||
2085 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) | ||
2086 | |||
2087 | /* Used by PM_L4PER_GPIO6_WKDEP */ | ||
2088 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6 | ||
2089 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1 | ||
2090 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6) | ||
2091 | |||
2092 | /* Used by PM_L4PER_GPIO7_WKDEP */ | ||
2093 | #define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0 | ||
2094 | #define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1 | ||
2095 | #define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0) | ||
2096 | |||
2097 | /* Used by PM_L4PER_GPIO8_WKDEP */ | ||
2098 | #define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0 | ||
2099 | #define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1 | ||
2100 | #define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0) | ||
2101 | |||
2102 | /* Used by PM_DSS_DSS_WKDEP */ | ||
2103 | #define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 | ||
2104 | #define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1 | ||
2105 | #define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) | ||
2106 | |||
2107 | /* Used by PM_DSS_DSS_WKDEP */ | ||
2108 | #define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14 | ||
2109 | #define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1 | ||
2110 | #define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14) | ||
2111 | |||
2112 | /* Used by PM_DSS_DSS_WKDEP */ | ||
2113 | #define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13 | ||
2114 | #define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1 | ||
2115 | #define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13) | ||
2116 | |||
2117 | /* Used by PM_DSS_DSS_WKDEP */ | ||
2118 | #define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 | ||
2119 | #define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1 | ||
2120 | #define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) | ||
2121 | |||
2122 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
2123 | #define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6 | ||
2124 | #define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1 | ||
2125 | #define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6) | ||
2126 | |||
2127 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
2128 | #define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1 | ||
2129 | #define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1 | ||
2130 | #define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1) | ||
2131 | |||
2132 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
2133 | #define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0 | ||
2134 | #define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1 | ||
2135 | #define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) | ||
2136 | |||
2137 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
2138 | #define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 | ||
2139 | #define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1 | ||
2140 | #define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) | ||
2141 | |||
2142 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
2143 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1 | ||
2144 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1 | ||
2145 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1) | ||
2146 | |||
2147 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
2148 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 | ||
2149 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1 | ||
2150 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) | ||
2151 | |||
2152 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
2153 | #define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 | ||
2154 | #define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1 | ||
2155 | #define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) | ||
2156 | |||
2157 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
2158 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1 | ||
2159 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1 | ||
2160 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1) | ||
2161 | |||
2162 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
2163 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 | ||
2164 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1 | ||
2165 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) | ||
2166 | |||
2167 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
2168 | #define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 | ||
2169 | #define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1 | ||
2170 | #define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) | ||
2171 | |||
2172 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
2173 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1 | ||
2174 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1 | ||
2175 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1) | ||
2176 | |||
2177 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
2178 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 | ||
2179 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1 | ||
2180 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) | ||
2181 | |||
2182 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
2183 | #define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 | ||
2184 | #define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1 | ||
2185 | #define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) | ||
2186 | |||
2187 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
2188 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1 | ||
2189 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1 | ||
2190 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1) | ||
2191 | |||
2192 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
2193 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 | ||
2194 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1 | ||
2195 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) | ||
2196 | |||
2197 | /* Used by PM_L4PER_I2C5_WKDEP */ | ||
2198 | #define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 | ||
2199 | #define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1 | ||
2200 | #define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) | ||
2201 | |||
2202 | /* Used by PM_WKUPAON_KBD_WKDEP */ | ||
2203 | #define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0 | ||
2204 | #define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1 | ||
2205 | #define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0) | ||
2206 | |||
2207 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
2208 | #define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6 | ||
2209 | #define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1 | ||
2210 | #define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6) | ||
2211 | |||
2212 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
2213 | #define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7 | ||
2214 | #define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1 | ||
2215 | #define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7) | ||
2216 | |||
2217 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
2218 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2 | ||
2219 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1 | ||
2220 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2) | ||
2221 | |||
2222 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
2223 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0 | ||
2224 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1 | ||
2225 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0) | ||
2226 | |||
2227 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
2228 | #define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2 | ||
2229 | #define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1 | ||
2230 | #define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2) | ||
2231 | |||
2232 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
2233 | #define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0 | ||
2234 | #define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1 | ||
2235 | #define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) | ||
2236 | |||
2237 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
2238 | #define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3 | ||
2239 | #define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1 | ||
2240 | #define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) | ||
2241 | |||
2242 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
2243 | #define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2 | ||
2244 | #define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1 | ||
2245 | #define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2) | ||
2246 | |||
2247 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
2248 | #define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0 | ||
2249 | #define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1 | ||
2250 | #define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) | ||
2251 | |||
2252 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
2253 | #define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3 | ||
2254 | #define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1 | ||
2255 | #define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) | ||
2256 | |||
2257 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
2258 | #define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2 | ||
2259 | #define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1 | ||
2260 | #define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2) | ||
2261 | |||
2262 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
2263 | #define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0 | ||
2264 | #define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1 | ||
2265 | #define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) | ||
2266 | |||
2267 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
2268 | #define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3 | ||
2269 | #define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1 | ||
2270 | #define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) | ||
2271 | |||
2272 | /* Used by PM_ABE_MCPDM_WKDEP */ | ||
2273 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6 | ||
2274 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1 | ||
2275 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6) | ||
2276 | |||
2277 | /* Used by PM_ABE_MCPDM_WKDEP */ | ||
2278 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7 | ||
2279 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1 | ||
2280 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7) | ||
2281 | |||
2282 | /* Used by PM_ABE_MCPDM_WKDEP */ | ||
2283 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2 | ||
2284 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1 | ||
2285 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2) | ||
2286 | |||
2287 | /* Used by PM_ABE_MCPDM_WKDEP */ | ||
2288 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0 | ||
2289 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1 | ||
2290 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0) | ||
2291 | |||
2292 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
2293 | #define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2 | ||
2294 | #define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1 | ||
2295 | #define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2) | ||
2296 | |||
2297 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
2298 | #define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1 | ||
2299 | #define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1 | ||
2300 | #define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1) | ||
2301 | |||
2302 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
2303 | #define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0 | ||
2304 | #define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1 | ||
2305 | #define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) | ||
2306 | |||
2307 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
2308 | #define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3 | ||
2309 | #define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1 | ||
2310 | #define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) | ||
2311 | |||
2312 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
2313 | #define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1 | ||
2314 | #define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1 | ||
2315 | #define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1) | ||
2316 | |||
2317 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
2318 | #define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0 | ||
2319 | #define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1 | ||
2320 | #define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) | ||
2321 | |||
2322 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
2323 | #define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3 | ||
2324 | #define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1 | ||
2325 | #define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) | ||
2326 | |||
2327 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | ||
2328 | #define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0 | ||
2329 | #define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1 | ||
2330 | #define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) | ||
2331 | |||
2332 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | ||
2333 | #define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3 | ||
2334 | #define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1 | ||
2335 | #define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) | ||
2336 | |||
2337 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | ||
2338 | #define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0 | ||
2339 | #define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1 | ||
2340 | #define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) | ||
2341 | |||
2342 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | ||
2343 | #define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3 | ||
2344 | #define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1 | ||
2345 | #define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) | ||
2346 | |||
2347 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
2348 | #define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2 | ||
2349 | #define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1 | ||
2350 | #define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2) | ||
2351 | |||
2352 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
2353 | #define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1 | ||
2354 | #define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1 | ||
2355 | #define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1) | ||
2356 | |||
2357 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
2358 | #define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0 | ||
2359 | #define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1 | ||
2360 | #define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0) | ||
2361 | |||
2362 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
2363 | #define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3 | ||
2364 | #define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1 | ||
2365 | #define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3) | ||
2366 | |||
2367 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
2368 | #define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2 | ||
2369 | #define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1 | ||
2370 | #define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2) | ||
2371 | |||
2372 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
2373 | #define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1 | ||
2374 | #define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1 | ||
2375 | #define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1) | ||
2376 | |||
2377 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
2378 | #define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0 | ||
2379 | #define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1 | ||
2380 | #define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0) | ||
2381 | |||
2382 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
2383 | #define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3 | ||
2384 | #define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1 | ||
2385 | #define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3) | ||
2386 | |||
2387 | /* Used by PM_L4PER_MMC3_WKDEP */ | ||
2388 | #define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1 | ||
2389 | #define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1 | ||
2390 | #define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1) | ||
2391 | |||
2392 | /* Used by PM_L4PER_MMC3_WKDEP */ | ||
2393 | #define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0 | ||
2394 | #define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1 | ||
2395 | #define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0) | ||
2396 | |||
2397 | /* Used by PM_L4PER_MMC3_WKDEP */ | ||
2398 | #define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3 | ||
2399 | #define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1 | ||
2400 | #define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3) | ||
2401 | |||
2402 | /* Used by PM_L4PER_MMC4_WKDEP */ | ||
2403 | #define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0 | ||
2404 | #define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1 | ||
2405 | #define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0) | ||
2406 | |||
2407 | /* Used by PM_L4PER_MMC4_WKDEP */ | ||
2408 | #define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3 | ||
2409 | #define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1 | ||
2410 | #define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3) | ||
2411 | |||
2412 | /* Used by PM_L4PER_MMC5_WKDEP */ | ||
2413 | #define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0 | ||
2414 | #define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1 | ||
2415 | #define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0) | ||
2416 | |||
2417 | /* Used by PM_L4PER_MMC5_WKDEP */ | ||
2418 | #define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3 | ||
2419 | #define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1 | ||
2420 | #define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3) | ||
2421 | |||
2422 | /* Used by PM_L3INIT_SATA_WKDEP */ | ||
2423 | #define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0 | ||
2424 | #define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1 | ||
2425 | #define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0) | ||
2426 | |||
2427 | /* Used by PM_ABE_SLIMBUS1_WKDEP */ | ||
2428 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6 | ||
2429 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1 | ||
2430 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6) | ||
2431 | |||
2432 | /* Used by PM_ABE_SLIMBUS1_WKDEP */ | ||
2433 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 | ||
2434 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1 | ||
2435 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) | ||
2436 | |||
2437 | /* Used by PM_ABE_SLIMBUS1_WKDEP */ | ||
2438 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2 | ||
2439 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1 | ||
2440 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2) | ||
2441 | |||
2442 | /* Used by PM_ABE_SLIMBUS1_WKDEP */ | ||
2443 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 | ||
2444 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1 | ||
2445 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) | ||
2446 | |||
2447 | /* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ | ||
2448 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1 | ||
2449 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1 | ||
2450 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1) | ||
2451 | |||
2452 | /* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ | ||
2453 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0 | ||
2454 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1 | ||
2455 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0) | ||
2456 | |||
2457 | /* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */ | ||
2458 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0 | ||
2459 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1 | ||
2460 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0) | ||
2461 | |||
2462 | /* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */ | ||
2463 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0 | ||
2464 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1 | ||
2465 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0) | ||
2466 | |||
2467 | /* Used by PM_L4PER_TIMER10_WKDEP */ | ||
2468 | #define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0 | ||
2469 | #define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1 | ||
2470 | #define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0) | ||
2471 | |||
2472 | /* Used by PM_L4PER_TIMER11_WKDEP */ | ||
2473 | #define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1 | ||
2474 | #define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1 | ||
2475 | #define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1) | ||
2476 | |||
2477 | /* Used by PM_L4PER_TIMER11_WKDEP */ | ||
2478 | #define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0 | ||
2479 | #define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1 | ||
2480 | #define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0) | ||
2481 | |||
2482 | /* Used by PM_WKUPAON_TIMER12_WKDEP */ | ||
2483 | #define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0 | ||
2484 | #define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1 | ||
2485 | #define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0) | ||
2486 | |||
2487 | /* Used by PM_WKUPAON_TIMER1_WKDEP */ | ||
2488 | #define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0 | ||
2489 | #define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1 | ||
2490 | #define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0) | ||
2491 | |||
2492 | /* Used by PM_L4PER_TIMER2_WKDEP */ | ||
2493 | #define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0 | ||
2494 | #define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1 | ||
2495 | #define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0) | ||
2496 | |||
2497 | /* Used by PM_L4PER_TIMER3_WKDEP */ | ||
2498 | #define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1 | ||
2499 | #define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1 | ||
2500 | #define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1) | ||
2501 | |||
2502 | /* Used by PM_L4PER_TIMER3_WKDEP */ | ||
2503 | #define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0 | ||
2504 | #define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1 | ||
2505 | #define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0) | ||
2506 | |||
2507 | /* Used by PM_L4PER_TIMER4_WKDEP */ | ||
2508 | #define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1 | ||
2509 | #define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1 | ||
2510 | #define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1) | ||
2511 | |||
2512 | /* Used by PM_L4PER_TIMER4_WKDEP */ | ||
2513 | #define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0 | ||
2514 | #define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1 | ||
2515 | #define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0) | ||
2516 | |||
2517 | /* Used by PM_ABE_TIMER5_WKDEP */ | ||
2518 | #define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2 | ||
2519 | #define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1 | ||
2520 | #define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2) | ||
2521 | |||
2522 | /* Used by PM_ABE_TIMER5_WKDEP */ | ||
2523 | #define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0 | ||
2524 | #define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1 | ||
2525 | #define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0) | ||
2526 | |||
2527 | /* Used by PM_ABE_TIMER6_WKDEP */ | ||
2528 | #define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2 | ||
2529 | #define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1 | ||
2530 | #define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2) | ||
2531 | |||
2532 | /* Used by PM_ABE_TIMER6_WKDEP */ | ||
2533 | #define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0 | ||
2534 | #define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1 | ||
2535 | #define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0) | ||
2536 | |||
2537 | /* Used by PM_ABE_TIMER7_WKDEP */ | ||
2538 | #define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2 | ||
2539 | #define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1 | ||
2540 | #define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2) | ||
2541 | |||
2542 | /* Used by PM_ABE_TIMER7_WKDEP */ | ||
2543 | #define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0 | ||
2544 | #define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1 | ||
2545 | #define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0) | ||
2546 | |||
2547 | /* Used by PM_ABE_TIMER8_WKDEP */ | ||
2548 | #define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2 | ||
2549 | #define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1 | ||
2550 | #define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2) | ||
2551 | |||
2552 | /* Used by PM_ABE_TIMER8_WKDEP */ | ||
2553 | #define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0 | ||
2554 | #define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1 | ||
2555 | #define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0) | ||
2556 | |||
2557 | /* Used by PM_L4PER_TIMER9_WKDEP */ | ||
2558 | #define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1 | ||
2559 | #define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1 | ||
2560 | #define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1) | ||
2561 | |||
2562 | /* Used by PM_L4PER_TIMER9_WKDEP */ | ||
2563 | #define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0 | ||
2564 | #define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1 | ||
2565 | #define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0) | ||
2566 | |||
2567 | /* Used by PM_L4PER_UART1_WKDEP */ | ||
2568 | #define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0 | ||
2569 | #define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1 | ||
2570 | #define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0) | ||
2571 | |||
2572 | /* Used by PM_L4PER_UART1_WKDEP */ | ||
2573 | #define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3 | ||
2574 | #define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1 | ||
2575 | #define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3) | ||
2576 | |||
2577 | /* Used by PM_L4PER_UART2_WKDEP */ | ||
2578 | #define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0 | ||
2579 | #define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1 | ||
2580 | #define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0) | ||
2581 | |||
2582 | /* Used by PM_L4PER_UART2_WKDEP */ | ||
2583 | #define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3 | ||
2584 | #define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1 | ||
2585 | #define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3) | ||
2586 | |||
2587 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2588 | #define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2 | ||
2589 | #define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1 | ||
2590 | #define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2) | ||
2591 | |||
2592 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2593 | #define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1 | ||
2594 | #define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1 | ||
2595 | #define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1) | ||
2596 | |||
2597 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2598 | #define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0 | ||
2599 | #define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1 | ||
2600 | #define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0) | ||
2601 | |||
2602 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
2603 | #define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3 | ||
2604 | #define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1 | ||
2605 | #define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3) | ||
2606 | |||
2607 | /* Used by PM_L4PER_UART4_WKDEP */ | ||
2608 | #define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0 | ||
2609 | #define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1 | ||
2610 | #define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0) | ||
2611 | |||
2612 | /* Used by PM_L4PER_UART4_WKDEP */ | ||
2613 | #define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3 | ||
2614 | #define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1 | ||
2615 | #define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3) | ||
2616 | |||
2617 | /* Used by PM_L4PER_UART5_WKDEP */ | ||
2618 | #define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0 | ||
2619 | #define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1 | ||
2620 | #define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0) | ||
2621 | |||
2622 | /* Used by PM_L4PER_UART5_WKDEP */ | ||
2623 | #define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3 | ||
2624 | #define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1 | ||
2625 | #define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3) | ||
2626 | |||
2627 | /* Used by PM_L4PER_UART6_WKDEP */ | ||
2628 | #define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0 | ||
2629 | #define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1 | ||
2630 | #define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0) | ||
2631 | |||
2632 | /* Used by PM_L4PER_UART6_WKDEP */ | ||
2633 | #define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3 | ||
2634 | #define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1 | ||
2635 | #define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3) | ||
2636 | |||
2637 | /* Used by PM_L3INIT_UNIPRO2_WKDEP */ | ||
2638 | #define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0 | ||
2639 | #define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1 | ||
2640 | #define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0) | ||
2641 | |||
2642 | /* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ | ||
2643 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1 | ||
2644 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1 | ||
2645 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1) | ||
2646 | |||
2647 | /* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ | ||
2648 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0 | ||
2649 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1 | ||
2650 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0) | ||
2651 | |||
2652 | /* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ | ||
2653 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1 | ||
2654 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1 | ||
2655 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1) | ||
2656 | |||
2657 | /* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ | ||
2658 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0 | ||
2659 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1 | ||
2660 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0) | ||
2661 | |||
2662 | /* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ | ||
2663 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1 | ||
2664 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1 | ||
2665 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1) | ||
2666 | |||
2667 | /* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ | ||
2668 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0 | ||
2669 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1 | ||
2670 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0) | ||
2671 | |||
2672 | /* Used by PM_WKUPAON_WD_TIMER2_WKDEP */ | ||
2673 | #define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0 | ||
2674 | #define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1 | ||
2675 | #define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0) | ||
2676 | |||
2677 | /* Used by PM_ABE_WD_TIMER3_WKDEP */ | ||
2678 | #define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0 | ||
2679 | #define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1 | ||
2680 | #define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0) | ||
2681 | |||
2682 | /* Used by PRM_IO_PMCTRL */ | ||
2683 | #define OMAP54XX_WUCLK_CTRL_SHIFT 8 | ||
2684 | #define OMAP54XX_WUCLK_CTRL_WIDTH 0x1 | ||
2685 | #define OMAP54XX_WUCLK_CTRL_MASK (1 << 8) | ||
2686 | |||
2687 | /* Used by PRM_IO_PMCTRL */ | ||
2688 | #define OMAP54XX_WUCLK_STATUS_SHIFT 9 | ||
2689 | #define OMAP54XX_WUCLK_STATUS_WIDTH 0x1 | ||
2690 | #define OMAP54XX_WUCLK_STATUS_MASK (1 << 9) | ||
2691 | |||
2692 | /* Used by REVISION_PRM */ | ||
2693 | #define OMAP54XX_X_MAJOR_SHIFT 8 | ||
2694 | #define OMAP54XX_X_MAJOR_WIDTH 0x3 | ||
2695 | #define OMAP54XX_X_MAJOR_MASK (0x7 << 8) | ||
2696 | |||
2697 | /* Used by REVISION_PRM */ | ||
2698 | #define OMAP54XX_Y_MINOR_SHIFT 0 | ||
2699 | #define OMAP54XX_Y_MINOR_WIDTH 0x6 | ||
2700 | #define OMAP54XX_Y_MINOR_MASK (0x3f << 0) | ||
2701 | #endif | ||
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 9265e031fa2f..801287ee4d98 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
@@ -600,7 +600,7 @@ static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", | |||
600 | #endif | 600 | #endif |
601 | 601 | ||
602 | #ifdef CONFIG_ARCH_OMAP4 | 602 | #ifdef CONFIG_ARCH_OMAP4 |
603 | #ifdef CONFIG_LOCAL_TIMERS | 603 | #ifdef CONFIG_HAVE_ARM_TWD |
604 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); | 604 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); |
605 | void __init omap4_local_timer_init(void) | 605 | void __init omap4_local_timer_init(void) |
606 | { | 606 | { |
@@ -619,12 +619,12 @@ void __init omap4_local_timer_init(void) | |||
619 | pr_err("twd_local_timer_register failed %d\n", err); | 619 | pr_err("twd_local_timer_register failed %d\n", err); |
620 | } | 620 | } |
621 | } | 621 | } |
622 | #else /* CONFIG_LOCAL_TIMERS */ | 622 | #else |
623 | void __init omap4_local_timer_init(void) | 623 | void __init omap4_local_timer_init(void) |
624 | { | 624 | { |
625 | omap4_sync32k_timer_init(); | 625 | omap4_sync32k_timer_init(); |
626 | } | 626 | } |
627 | #endif /* CONFIG_LOCAL_TIMERS */ | 627 | #endif /* CONFIG_HAVE_ARM_TWD */ |
628 | #endif /* CONFIG_ARCH_OMAP4 */ | 628 | #endif /* CONFIG_ARCH_OMAP4 */ |
629 | 629 | ||
630 | #ifdef CONFIG_SOC_OMAP5 | 630 | #ifdef CONFIG_SOC_OMAP5 |