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-rw-r--r--arch/arm/mach-omap2/Kconfig22
-rw-r--r--arch/arm/mach-omap2/Makefile13
-rw-r--r--arch/arm/mach-omap2/Makefile.boot3
-rw-r--r--arch/arm/mach-omap2/board-generic.c80
-rw-r--r--arch/arm/mach-omap2/board-h4.c197
-rw-r--r--arch/arm/mach-omap2/devices.c89
-rw-r--r--arch/arm/mach-omap2/id.c124
-rw-r--r--arch/arm/mach-omap2/io.c53
-rw-r--r--arch/arm/mach-omap2/irq.c149
-rw-r--r--arch/arm/mach-omap2/mux.c65
-rw-r--r--arch/arm/mach-omap2/prcm.h419
-rw-r--r--arch/arm/mach-omap2/serial.c180
-rw-r--r--arch/arm/mach-omap2/sram-fn.S333
-rw-r--r--arch/arm/mach-omap2/timer-gp.c126
14 files changed, 1853 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
new file mode 100644
index 000000000000..578880943cf2
--- /dev/null
+++ b/arch/arm/mach-omap2/Kconfig
@@ -0,0 +1,22 @@
1comment "OMAP Core Type"
2 depends on ARCH_OMAP2
3
4config ARCH_OMAP24XX
5 bool "OMAP24xx Based System"
6 depends on ARCH_OMAP2
7
8config ARCH_OMAP2420
9 bool "OMAP2420 support"
10 depends on ARCH_OMAP24XX
11
12comment "OMAP Board Type"
13 depends on ARCH_OMAP2
14
15config MACH_OMAP_GENERIC
16 bool "Generic OMAP board"
17 depends on ARCH_OMAP2 && ARCH_OMAP24XX
18
19config MACH_OMAP_H4
20 bool "OMAP 2420 H4 board"
21 depends on ARCH_OMAP2 && ARCH_OMAP24XX
22
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
new file mode 100644
index 000000000000..42041166435c
--- /dev/null
+++ b/arch/arm/mach-omap2/Makefile
@@ -0,0 +1,13 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Common support
6obj-y := irq.o id.o io.o sram-fn.o clock.o mux.o devices.o serial.o
7
8obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
9
10# Specific board support
11obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
12obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
13
diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot
new file mode 100644
index 000000000000..565aff7f37a9
--- /dev/null
+++ b/arch/arm/mach-omap2/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x80800000
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
new file mode 100644
index 000000000000..c602e7a3d93e
--- /dev/null
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -0,0 +1,80 @@
1/*
2 * linux/arch/arm/mach-omap/omap2/board-generic.c
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Paul Mundt <paul.mundt@nokia.com>
6 *
7 * Modified from mach-omap/omap1/board-generic.c
8 *
9 * Code for generic OMAP2 board. Should work on many OMAP2 systems where
10 * the bootloader passes the board-specific data to the kernel.
11 * Do not put any board specific code to this file; create a new machine
12 * type if you need custom low-level initializations.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/device.h>
22
23#include <asm/hardware.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27
28#include <asm/arch/gpio.h>
29#include <asm/arch/mux.h>
30#include <asm/arch/usb.h>
31#include <asm/arch/board.h>
32#include <asm/arch/common.h>
33
34static void __init omap_generic_init_irq(void)
35{
36 omap_init_irq();
37}
38
39static struct omap_uart_config generic_uart_config __initdata = {
40 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
41};
42
43static struct omap_mmc_config generic_mmc_config __initdata = {
44 .mmc [0] = {
45 .enabled = 0,
46 .wire4 = 0,
47 .wp_pin = -1,
48 .power_pin = -1,
49 .switch_pin = -1,
50 },
51};
52
53static struct omap_board_config_kernel generic_config[] = {
54 { OMAP_TAG_UART, &generic_uart_config },
55 { OMAP_TAG_MMC, &generic_mmc_config },
56};
57
58static void __init omap_generic_init(void)
59{
60 omap_board_config = generic_config;
61 omap_board_config_size = ARRAY_SIZE(generic_config);
62 omap_serial_init();
63}
64
65static void __init omap_generic_map_io(void)
66{
67 omap_map_common_io();
68}
69
70MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
71 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
72 .phys_ram = 0x80000000,
73 .phys_io = 0x48000000,
74 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
75 .boot_params = 0x80000100,
76 .map_io = omap_generic_map_io,
77 .init_irq = omap_generic_init_irq,
78 .init_machine = omap_generic_init,
79 .timer = &omap_timer,
80MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
new file mode 100644
index 000000000000..f2554469a76a
--- /dev/null
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -0,0 +1,197 @@
1/*
2 * linux/arch/arm/mach-omap/omap2/board-h4.c
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Paul Mundt <paul.mundt@nokia.com>
6 *
7 * Modified from mach-omap/omap1/board-generic.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/mtd.h>
18#include <linux/mtd/partitions.h>
19#include <linux/delay.h>
20
21#include <asm/hardware.h>
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/flash.h>
26
27#include <asm/arch/gpio.h>
28#include <asm/arch/mux.h>
29#include <asm/arch/usb.h>
30#include <asm/arch/board.h>
31#include <asm/arch/common.h>
32#include <asm/arch/prcm.h>
33
34#include <asm/io.h>
35#include <asm/delay.h>
36
37static struct mtd_partition h4_partitions[] = {
38 /* bootloader (U-Boot, etc) in first sector */
39 {
40 .name = "bootloader",
41 .offset = 0,
42 .size = SZ_128K,
43 .mask_flags = MTD_WRITEABLE, /* force read-only */
44 },
45 /* bootloader params in the next sector */
46 {
47 .name = "params",
48 .offset = MTDPART_OFS_APPEND,
49 .size = SZ_128K,
50 .mask_flags = 0,
51 },
52 /* kernel */
53 {
54 .name = "kernel",
55 .offset = MTDPART_OFS_APPEND,
56 .size = SZ_2M,
57 .mask_flags = 0
58 },
59 /* file system */
60 {
61 .name = "filesystem",
62 .offset = MTDPART_OFS_APPEND,
63 .size = MTDPART_SIZ_FULL,
64 .mask_flags = 0
65 }
66};
67
68static struct flash_platform_data h4_flash_data = {
69 .map_name = "cfi_probe",
70 .width = 2,
71 .parts = h4_partitions,
72 .nr_parts = ARRAY_SIZE(h4_partitions),
73};
74
75static struct resource h4_flash_resource = {
76 .start = H4_CS0_BASE,
77 .end = H4_CS0_BASE + SZ_64M - 1,
78 .flags = IORESOURCE_MEM,
79};
80
81static struct platform_device h4_flash_device = {
82 .name = "omapflash",
83 .id = 0,
84 .dev = {
85 .platform_data = &h4_flash_data,
86 },
87 .num_resources = 1,
88 .resource = &h4_flash_resource,
89};
90
91static struct resource h4_smc91x_resources[] = {
92 [0] = {
93 .start = OMAP24XX_ETHR_START, /* Physical */
94 .end = OMAP24XX_ETHR_START + 0xf,
95 .flags = IORESOURCE_MEM,
96 },
97 [1] = {
98 .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
99 .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104static struct platform_device h4_smc91x_device = {
105 .name = "smc91x",
106 .id = -1,
107 .num_resources = ARRAY_SIZE(h4_smc91x_resources),
108 .resource = h4_smc91x_resources,
109};
110
111static struct platform_device *h4_devices[] __initdata = {
112 &h4_smc91x_device,
113 &h4_flash_device,
114};
115
116static inline void __init h4_init_smc91x(void)
117{
118 /* Make sure CS1 timings are correct */
119 GPMC_CONFIG1_1 = 0x00011200;
120 GPMC_CONFIG2_1 = 0x001f1f01;
121 GPMC_CONFIG3_1 = 0x00080803;
122 GPMC_CONFIG4_1 = 0x1c091c09;
123 GPMC_CONFIG5_1 = 0x041f1f1f;
124 GPMC_CONFIG6_1 = 0x000004c4;
125 GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);
126 udelay(100);
127
128 omap_cfg_reg(M15_24XX_GPIO92);
129 if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) {
130 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
131 OMAP24XX_ETHR_GPIO_IRQ);
132 return;
133 }
134 omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
135}
136
137static void __init omap_h4_init_irq(void)
138{
139 omap_init_irq();
140 omap_gpio_init();
141 h4_init_smc91x();
142}
143
144static struct omap_uart_config h4_uart_config __initdata = {
145 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
146};
147
148static struct omap_mmc_config h4_mmc_config __initdata = {
149 .mmc [0] = {
150 .enabled = 1,
151 .wire4 = 1,
152 .wp_pin = -1,
153 .power_pin = -1,
154 .switch_pin = -1,
155 },
156};
157
158static struct omap_lcd_config h4_lcd_config __initdata = {
159 .panel_name = "h4",
160 .ctrl_name = "internal",
161};
162
163static struct omap_board_config_kernel h4_config[] = {
164 { OMAP_TAG_UART, &h4_uart_config },
165 { OMAP_TAG_MMC, &h4_mmc_config },
166 { OMAP_TAG_LCD, &h4_lcd_config },
167};
168
169static void __init omap_h4_init(void)
170{
171 /*
172 * Make sure the serial ports are muxed on at this point.
173 * You have to mux them off in device drivers later on
174 * if not needed.
175 */
176 platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
177 omap_board_config = h4_config;
178 omap_board_config_size = ARRAY_SIZE(h4_config);
179 omap_serial_init();
180}
181
182static void __init omap_h4_map_io(void)
183{
184 omap_map_common_io();
185}
186
187MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
188 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
189 .phys_ram = 0x80000000,
190 .phys_io = 0x48000000,
191 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
192 .boot_params = 0x80000100,
193 .map_io = omap_h4_map_io,
194 .init_irq = omap_h4_init_irq,
195 .init_machine = omap_h4_init,
196 .timer = &omap_timer,
197MACHINE_END
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
new file mode 100644
index 000000000000..7181edb89352
--- /dev/null
+++ b/arch/arm/mach-omap2/devices.c
@@ -0,0 +1,89 @@
1/*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/config.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17
18#include <asm/hardware.h>
19#include <asm/io.h>
20#include <asm/mach-types.h>
21#include <asm/mach/map.h>
22
23#include <asm/arch/tc.h>
24#include <asm/arch/board.h>
25#include <asm/arch/mux.h>
26#include <asm/arch/gpio.h>
27
28extern void omap_nop_release(struct device *dev);
29
30/*-------------------------------------------------------------------------*/
31
32#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
33
34#define OMAP2_I2C_BASE2 0x48072000
35#define OMAP2_I2C_INT2 57
36
37static struct resource i2c_resources2[] = {
38 {
39 .start = OMAP2_I2C_BASE2,
40 .end = OMAP2_I2C_BASE2 + 0x3f,
41 .flags = IORESOURCE_MEM,
42 },
43 {
44 .start = OMAP2_I2C_INT2,
45 .flags = IORESOURCE_IRQ,
46 },
47};
48
49static struct platform_device omap_i2c_device2 = {
50 .name = "i2c_omap",
51 .id = 2,
52 .dev = {
53 .release = omap_nop_release,
54 },
55 .num_resources = ARRAY_SIZE(i2c_resources2),
56 .resource = i2c_resources2,
57};
58
59/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
60static void omap_init_i2c(void)
61{
62 /* REVISIT: Second I2C not in use on H4? */
63 if (machine_is_omap_h4())
64 return;
65
66 omap_cfg_reg(J15_24XX_I2C2_SCL);
67 omap_cfg_reg(H19_24XX_I2C2_SDA);
68 (void) platform_device_register(&omap_i2c_device2);
69}
70
71#else
72
73static void omap_init_i2c(void) {}
74
75#endif
76
77/*-------------------------------------------------------------------------*/
78
79static int __init omap2_init_devices(void)
80{
81 /* please keep these calls, and their implementations above,
82 * in alphabetical order so they're easier to sort through.
83 */
84 omap_init_i2c();
85
86 return 0;
87}
88arch_initcall(omap2_init_devices);
89
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
new file mode 100644
index 000000000000..76187300f2b6
--- /dev/null
+++ b/arch/arm/mach-omap2/id.c
@@ -0,0 +1,124 @@
1/*
2 * linux/arch/arm/mach-omap2/id.c
3 *
4 * OMAP2 CPU identification code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/config.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20
21#define OMAP24XX_TAP_BASE io_p2v(0x48014000)
22
23#define OMAP_TAP_IDCODE 0x0204
24#define OMAP_TAP_PROD_ID 0x0208
25
26#define OMAP_TAP_DIE_ID_0 0x0218
27#define OMAP_TAP_DIE_ID_1 0x021C
28#define OMAP_TAP_DIE_ID_2 0x0220
29#define OMAP_TAP_DIE_ID_3 0x0224
30
31/* system_rev fields for OMAP2 processors:
32 * CPU id bits [31:16],
33 * CPU device type [15:12], (unprg,normal,POP)
34 * CPU revision [11:08]
35 * CPU class bits [07:00]
36 */
37
38struct omap_id {
39 u16 hawkeye; /* Silicon type (Hawkeye id) */
40 u8 dev; /* Device type from production_id reg */
41 u32 type; /* combined type id copied to system_rev */
42};
43
44/* Register values to detect the OMAP version */
45static struct omap_id omap_ids[] __initdata = {
46 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
47 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
48 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
49 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
50 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
51 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
52};
53
54static u32 __init read_tap_reg(int reg)
55{
56 return __raw_readl(OMAP24XX_TAP_BASE + reg);
57}
58
59void __init omap2_check_revision(void)
60{
61 int i, j;
62 u32 idcode;
63 u32 prod_id;
64 u16 hawkeye;
65 u8 dev_type;
66 u8 rev;
67
68 idcode = read_tap_reg(OMAP_TAP_IDCODE);
69 prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
70 hawkeye = (idcode >> 12) & 0xffff;
71 rev = (idcode >> 28) & 0x0f;
72 dev_type = (prod_id >> 16) & 0x0f;
73
74#ifdef DEBUG
75 printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
76 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
77 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_0: 0x%08x\n",
78 read_tap_reg(OMAP_TAP_DIE_ID_0));
79 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
80 read_tap_reg(OMAP_TAP_DIE_ID_1),
81 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
82 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_2: 0x%08x\n",
83 read_tap_reg(OMAP_TAP_DIE_ID_2));
84 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_3: 0x%08x\n",
85 read_tap_reg(OMAP_TAP_DIE_ID_3));
86 printk(KERN_DEBUG "OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
87 prod_id, dev_type);
88#endif
89
90 /* Check hawkeye ids */
91 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
92 if (hawkeye == omap_ids[i].hawkeye)
93 break;
94 }
95
96 if (i == ARRAY_SIZE(omap_ids)) {
97 printk(KERN_ERR "Unknown OMAP CPU id\n");
98 return;
99 }
100
101 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
102 if (dev_type == omap_ids[j].dev)
103 break;
104 }
105
106 if (j == ARRAY_SIZE(omap_ids)) {
107 printk(KERN_ERR "Unknown OMAP device type. "
108 "Handling it as OMAP%04x\n",
109 omap_ids[i].type >> 16);
110 j = i;
111 }
112 system_rev = omap_ids[j].type;
113
114 system_rev |= rev << 8;
115
116 /* Add the cpu class info (24xx) */
117 system_rev |= 0x24;
118
119 pr_info("OMAP%04x", system_rev >> 16);
120 if ((system_rev >> 8) & 0x0f)
121 printk("%x", (system_rev >> 8) & 0x0f);
122 printk("\n");
123}
124
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
new file mode 100644
index 000000000000..8ea67bf196a5
--- /dev/null
+++ b/arch/arm/mach-omap2/io.c
@@ -0,0 +1,53 @@
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/config.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/mach/map.h>
20#include <asm/io.h>
21#include <asm/arch/mux.h>
22
23extern void omap_sram_init(void);
24extern int omap2_clk_init(void);
25extern void omap2_check_revision(void);
26
27/*
28 * The machine specific code may provide the extra mapping besides the
29 * default mapping provided here.
30 */
31static struct map_desc omap2_io_desc[] __initdata = {
32 {
33 .virtual = L3_24XX_VIRT,
34 .pfn = __phys_to_pfn(L3_24XX_PHYS),
35 .length = L3_24XX_SIZE,
36 .type = MT_DEVICE
37 },
38 {
39 .virtual = L4_24XX_VIRT,
40 .pfn = __phys_to_pfn(L4_24XX_PHYS),
41 .length = L4_24XX_SIZE,
42 .type = MT_DEVICE
43 }
44};
45
46void __init omap_map_common_io(void)
47{
48 iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc));
49 omap2_check_revision();
50 omap_sram_init();
51 omap2_mux_init();
52 omap2_clk_init();
53}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
new file mode 100644
index 000000000000..d7baff675cfe
--- /dev/null
+++ b/arch/arm/mach-omap2/irq.c
@@ -0,0 +1,149 @@
1/*
2 * linux/arch/arm/mach-omap/omap2/irq.c
3 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/config.h>
16#include <linux/interrupt.h>
17#include <asm/hardware.h>
18#include <asm/mach/irq.h>
19#include <asm/irq.h>
20#include <asm/io.h>
21
22#define INTC_REVISION 0x0000
23#define INTC_SYSCONFIG 0x0010
24#define INTC_SYSSTATUS 0x0014
25#define INTC_CONTROL 0x0048
26#define INTC_MIR_CLEAR0 0x0088
27#define INTC_MIR_SET0 0x008c
28
29/*
30 * OMAP2 has a number of different interrupt controllers, each interrupt
31 * controller is identified as its own "bank". Register definitions are
32 * fairly consistent for each bank, but not all registers are implemented
33 * for each bank.. when in doubt, consult the TRM.
34 */
35static struct omap_irq_bank {
36 unsigned long base_reg;
37 unsigned int nr_irqs;
38} __attribute__ ((aligned(4))) irq_banks[] = {
39 {
40 /* MPU INTC */
41 .base_reg = OMAP24XX_IC_BASE,
42 .nr_irqs = 96,
43 }, {
44 /* XXX: DSP INTC */
45
46#if 0
47 /*
48 * Commented out for now until we fix the IVA clocking
49 */
50#ifdef CONFIG_ARCH_OMAP2420
51 }, {
52 /* IVA INTC (2420 only) */
53 .base_reg = OMAP24XX_IVA_INTC_BASE,
54 .nr_irqs = 16, /* Actually 32, but only 16 are used */
55#endif
56#endif
57 }
58};
59
60/* XXX: FIQ and additional INTC support (only MPU at the moment) */
61static void omap_ack_irq(unsigned int irq)
62{
63 omap_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
64}
65
66static void omap_mask_irq(unsigned int irq)
67{
68 int offset = (irq >> 5) << 5;
69
70 if (irq >= 64) {
71 irq %= 64;
72 } else if (irq >= 32) {
73 irq %= 32;
74 }
75
76 omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
77}
78
79static void omap_unmask_irq(unsigned int irq)
80{
81 int offset = (irq >> 5) << 5;
82
83 if (irq >= 64) {
84 irq %= 64;
85 } else if (irq >= 32) {
86 irq %= 32;
87 }
88
89 omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
90}
91
92static void omap_mask_ack_irq(unsigned int irq)
93{
94 omap_mask_irq(irq);
95 omap_ack_irq(irq);
96}
97
98static struct irqchip omap_irq_chip = {
99 .ack = omap_mask_ack_irq,
100 .mask = omap_mask_irq,
101 .unmask = omap_unmask_irq,
102};
103
104static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
105{
106 unsigned long tmp;
107
108 tmp = omap_readl(bank->base_reg + INTC_REVISION) & 0xff;
109 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
110 "(revision %ld.%ld) with %d interrupts\n",
111 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
112
113 tmp = omap_readl(bank->base_reg + INTC_SYSCONFIG);
114 tmp |= 1 << 1; /* soft reset */
115 omap_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
116
117 while (!(omap_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
118 /* Wait for reset to complete */;
119}
120
121void __init omap_init_irq(void)
122{
123 unsigned long nr_irqs = 0;
124 unsigned int nr_banks = 0;
125 int i;
126
127 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
128 struct omap_irq_bank *bank = irq_banks + i;
129
130 /* XXX */
131 if (!bank->base_reg)
132 continue;
133
134 omap_irq_bank_init_one(bank);
135
136 nr_irqs += bank->nr_irqs;
137 nr_banks++;
138 }
139
140 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
141 nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
142
143 for (i = 0; i < nr_irqs; i++) {
144 set_irq_chip(i, &omap_irq_chip);
145 set_irq_handler(i, do_level_IRQ);
146 set_irq_flags(i, IRQF_VALID);
147 }
148}
149
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
new file mode 100644
index 000000000000..ea4654815dd1
--- /dev/null
+++ b/arch/arm/mach-omap2/mux.c
@@ -0,0 +1,65 @@
1/*
2 * linux/arch/arm/mach-omap2/mux.c
3 *
4 * OMAP1 pin multiplexing configurations
5 *
6 * Copyright (C) 2003 - 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25#include <linux/config.h>
26#include <linux/module.h>
27#include <linux/init.h>
28#include <asm/system.h>
29#include <asm/io.h>
30#include <linux/spinlock.h>
31
32#include <asm/arch/mux.h>
33
34#ifdef CONFIG_OMAP_MUX
35
36/* NOTE: See mux.h for the enumeration */
37
38struct pin_config __initdata_or_module omap24xx_pins[] = {
39/*
40 * description mux mux pull pull debug
41 * offset mode ena type
42 */
43
44/* 24xx I2C */
45MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1)
46MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1)
47MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 0, 1)
48MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1)
49
50/* Menelaus interrupt */
51MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
52
53/* 24xx GPIO */
54MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
55MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
56
57};
58
59int __init omap2_mux_init(void)
60{
61 omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
62 return 0;
63}
64
65#endif
diff --git a/arch/arm/mach-omap2/prcm.h b/arch/arm/mach-omap2/prcm.h
new file mode 100644
index 000000000000..2eb89b936c83
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm.h
@@ -0,0 +1,419 @@
1/*
2 * prcm.h - Access definations for use in OMAP24XX clock and power management
3 *
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
22#define __ASM_ARM_ARCH_DPM_PRCM_H
23
24/* SET_PERFORMANCE_LEVEL PARAMETERS */
25#define PRCM_HALF_SPEED 1
26#define PRCM_FULL_SPEED 2
27
28#ifndef __ASSEMBLER__
29
30#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
31
32#define PRCM_REVISION PRCM_REG32(0x000)
33#define PRCM_SYSCONFIG PRCM_REG32(0x010)
34#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
35#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
36#define PRCM_VOLTCTRL PRCM_REG32(0x050)
37#define PRCM_VOLTST PRCM_REG32(0x054)
38#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
39#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
40#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
41#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
42#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
43#define PRCM_VOLTSETUP PRCM_REG32(0x090)
44#define PRCM_CLKSSETUP PRCM_REG32(0x094)
45#define PRCM_POLCTRL PRCM_REG32(0x098)
46
47/* GENERAL PURPOSE */
48#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
49#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
50#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
51#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
52#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
53#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
54#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
55#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
56#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
57#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
58#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
59#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
60#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
61#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
62#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
63#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
64#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
65#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
66#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
67#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
68
69/* MPU */
70#define CM_CLKSEL_MPU PRCM_REG32(0x140)
71#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
72#define RM_RSTST_MPU PRCM_REG32(0x158)
73#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
74#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
75#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
76#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
77#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
78#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
79
80/* CORE */
81#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
82#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
83#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
84#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
85#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
86#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
87#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
88#define CM_IDLEST1_CORE PRCM_REG32(0x220)
89#define CM_IDLEST2_CORE PRCM_REG32(0x224)
90#define CM_IDLEST3_CORE PRCM_REG32(0x228)
91#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
92#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
93#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
94#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
95#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
96#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
97#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
98#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
99#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
100#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
101#define PM_WKST1_CORE PRCM_REG32(0x2B0)
102#define PM_WKST2_CORE PRCM_REG32(0x2B4)
103#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
104#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
105#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
106
107/* GFX */
108#define CM_FCLKEN_GFX PRCM_REG32(0x300)
109#define CM_ICLKEN_GFX PRCM_REG32(0x310)
110#define CM_IDLEST_GFX PRCM_REG32(0x320)
111#define CM_CLKSEL_GFX PRCM_REG32(0x340)
112#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
113#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
114#define RM_RSTST_GFX PRCM_REG32(0x358)
115#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
116#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
117#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
118
119/* WAKE-UP */
120#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
121#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
122#define CM_IDLEST_WKUP PRCM_REG32(0x420)
123#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
124#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
125#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
126#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
127#define RM_RSTST_WKUP PRCM_REG32(0x458)
128#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
129#define PM_WKST_WKUP PRCM_REG32(0x4B0)
130
131/* CLOCKS */
132#define CM_CLKEN_PLL PRCM_REG32(0x500)
133#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
134#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
135#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
136#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
137
138/* DSP */
139#define CM_FCLKEN_DSP PRCM_REG32(0x800)
140#define CM_ICLKEN_DSP PRCM_REG32(0x810)
141#define CM_IDLEST_DSP PRCM_REG32(0x820)
142#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
143#define CM_CLKSEL_DSP PRCM_REG32(0x840)
144#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
145#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
146#define RM_RSTST_DSP PRCM_REG32(0x858)
147#define PM_WKEN_DSP PRCM_REG32(0x8A0)
148#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
149#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
150#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
151#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
152#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
153
154/* IVA */
155#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
156#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
157
158/* Modem on 2430 */
159#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
160#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
161#define CM_IDLEST_MDM PRCM_REG32(0xC20)
162#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
163
164/* FIXME: Move to header for 2430 */
165#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000)
166#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
167
168#define GPMC_BASE (OMAP24XX_GPMC_BASE)
169#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset))
170
171#define GPT1_BASE (OMAP24XX_GPT1)
172#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
173
174/* Misc sysconfig */
175#define DISPC_SYSCONFIG DISP_REG32(0x410)
176#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000)
177#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
178#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10)
179
180//#define DSP_MMU_SYSCONFIG 0x5A000010
181#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10)
182//#define IVA_MMU_SYSCONFIG 0x5D000010
183//#define DSP_DMA_SYSCONFIG 0x00FCC02C
184#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)
185#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)
186#define GPMC_SYSCONFIG GPMC_REG32(0x010)
187#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010)
188#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
189#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
190#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
191//#define IVA_SYSCONFIG 0x5C060010
192#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10)
193#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10)
194#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010)
195//#define VLYNQ_SYSCONFIG 0x67FFFE10
196
197/* rkw - good cannidates for PM_ to start what nm was trying */
198#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)
199#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)
200#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)
201#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)
202#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)
203#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)
204#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)
205#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)
206#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)
207#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)
208#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)
209
210#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
211#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
212#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
213#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
214#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
215#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
216#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
217#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
218#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
219#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
220#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
221#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
222
223#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
224
225#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10))
226#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10))
227#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10))
228#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10))
229
230/* GP TIMER 1 */
231#define GPTIMER1_TISTAT GPT1_REG32(0x014)
232#define GPTIMER1_TISR GPT1_REG32(0x018)
233#define GPTIMER1_TIER GPT1_REG32(0x01C)
234#define GPTIMER1_TWER GPT1_REG32(0x020)
235#define GPTIMER1_TCLR GPT1_REG32(0x024)
236#define GPTIMER1_TCRR GPT1_REG32(0x028)
237#define GPTIMER1_TLDR GPT1_REG32(0x02C)
238#define GPTIMER1_TTGR GPT1_REG32(0x030)
239#define GPTIMER1_TWPS GPT1_REG32(0x034)
240#define GPTIMER1_TMAR GPT1_REG32(0x038)
241#define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
242#define GPTIMER1_TSICR GPT1_REG32(0x040)
243#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
244
245/* rkw -- base fix up please... */
246#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018)
247
248/* SDRC */
249#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060)
250#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064)
251#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068)
252#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C)
253#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070)
254#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084)
255
256/* GPIO 1 */
257#define GPIO1_BASE GPIOX_BASE(1)
258#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
259#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
260#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
261#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
262#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
263#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
264#define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
265#define GPIO1_DATAIN GPIO1_REG32(0x038)
266#define GPIO1_OE GPIO1_REG32(0x034)
267#define GPIO1_DATAOUT GPIO1_REG32(0x03C)
268
269/* GPIO2 */
270#define GPIO2_BASE GPIOX_BASE(2)
271#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
272#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
273#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
274#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
275#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
276#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
277#define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
278#define GPIO2_DATAIN GPIO2_REG32(0x038)
279#define GPIO2_OE GPIO2_REG32(0x034)
280#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
281
282/* GPIO 3 */
283#define GPIO3_BASE GPIOX_BASE(3)
284#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
285#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
286#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
287#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
288#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
289#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
290#define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
291#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
292#define GPIO3_DATAIN GPIO3_REG32(0x038)
293#define GPIO3_OE GPIO3_REG32(0x034)
294#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
295#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
296#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
297
298/* GPIO 4 */
299#define GPIO4_BASE GPIOX_BASE(4)
300#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
301#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
302#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
303#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
304#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
305#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
306#define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
307#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
308#define GPIO4_DATAIN GPIO4_REG32(0x038)
309#define GPIO4_OE GPIO4_REG32(0x034)
310#define GPIO4_DATAOUT GPIO4_REG32(0x03C)
311#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
312#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
313
314
315/* IO CONFIG */
316#define CONTROL_BASE (OMAP24XX_CTRL_BASE)
317#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset))
318
319#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
320#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
321#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
322#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
323#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
324#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
325#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC)
326#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
327#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
328
329/* CONTROL */
330#define CONTROL_DEVCONF CONTROL_REG32(0x274)
331
332/* INTERRUPT CONTROLLER */
333#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000)
334#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
335
336#define INTC1_U_BASE INTC_REG32(0x000)
337#define INTC_MIR0 INTC_REG32(0x084)
338#define INTC_MIR_SET0 INTC_REG32(0x08C)
339#define INTC_MIR_CLEAR0 INTC_REG32(0x088)
340#define INTC_ISR_CLEAR0 INTC_REG32(0x094)
341#define INTC_MIR1 INTC_REG32(0x0A4)
342#define INTC_MIR_SET1 INTC_REG32(0x0AC)
343#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
344#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
345#define INTC_MIR2 INTC_REG32(0x0C4)
346#define INTC_MIR_SET2 INTC_REG32(0x0CC)
347#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
348#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
349#define INTC_SIR_IRQ INTC_REG32(0x040)
350#define INTC_CONTROL INTC_REG32(0x048)
351#define INTC_ILR11 INTC_REG32(0x12C)
352#define INTC_ILR32 INTC_REG32(0x180)
353#define INTC_ILR37 INTC_REG32(0x194)
354#define INTC_SYSCONFIG INTC_REG32(0x010)
355
356/* RAM FIREWALL */
357#define RAMFW_BASE (0x68005000)
358#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
359
360#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
361#define RAMFW_READPERM0 RAMFW_REG32(0x050)
362#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
363
364/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
365//#define DEBUG_BOARD_LED_REGISTER 0x04000014
366
367/* GPMC CS0 */
368#define GPMC_CONFIG1_0 GPMC_REG32(0x060)
369#define GPMC_CONFIG2_0 GPMC_REG32(0x064)
370#define GPMC_CONFIG3_0 GPMC_REG32(0x068)
371#define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
372#define GPMC_CONFIG5_0 GPMC_REG32(0x070)
373#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
374#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
375
376/* DSS */
377#define DSS_CONTROL DISP_REG32(0x040)
378#define DISPC_CONTROL DISP_REG32(0x440)
379#define DISPC_SYSSTATUS DISP_REG32(0x414)
380#define DISPC_IRQSTATUS DISP_REG32(0x418)
381#define DISPC_IRQENABLE DISP_REG32(0x41C)
382#define DISPC_CONFIG DISP_REG32(0x444)
383#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
384#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
385#define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
386#define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
387#define DISPC_LINE_NUMBER DISP_REG32(0x460)
388#define DISPC_TIMING_H DISP_REG32(0x464)
389#define DISPC_TIMING_V DISP_REG32(0x468)
390#define DISPC_POL_FREQ DISP_REG32(0x46C)
391#define DISPC_DIVISOR DISP_REG32(0x470)
392#define DISPC_SIZE_DIG DISP_REG32(0x478)
393#define DISPC_SIZE_LCD DISP_REG32(0x47C)
394#define DISPC_GFX_BA0 DISP_REG32(0x480)
395#define DISPC_GFX_BA1 DISP_REG32(0x484)
396#define DISPC_GFX_POSITION DISP_REG32(0x488)
397#define DISPC_GFX_SIZE DISP_REG32(0x48C)
398#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
399#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
400#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
401#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
402#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
403#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
404#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
405#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
406#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
407
408/* Wake up define for board */
409#define GPIO97 (1 << 1)
410#define GPIO88 (1 << 24)
411
412#endif /* __ASSEMBLER__ */
413
414#endif
415
416
417
418
419
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
new file mode 100644
index 000000000000..f4df04fe1dd8
--- /dev/null
+++ b/arch/arm/mach-omap2/serial.c
@@ -0,0 +1,180 @@
1/*
2 * arch/arm/mach-omap/omap2/serial.c
3 *
4 * OMAP2 serial support.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * Based off of arch/arm/mach-omap/omap1/serial.c
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/serial_8250.h>
18#include <linux/serial_reg.h>
19
20#include <asm/io.h>
21#include <asm/hardware/clock.h>
22
23#include <asm/arch/common.h>
24#include <asm/arch/board.h>
25
26static struct clk * uart1_ick = NULL;
27static struct clk * uart1_fck = NULL;
28static struct clk * uart2_ick = NULL;
29static struct clk * uart2_fck = NULL;
30static struct clk * uart3_ick = NULL;
31static struct clk * uart3_fck = NULL;
32
33static struct plat_serial8250_port serial_platform_data[] = {
34 {
35 .membase = (char *)IO_ADDRESS(OMAP_UART1_BASE),
36 .mapbase = (unsigned long)OMAP_UART1_BASE,
37 .irq = 72,
38 .flags = UPF_BOOT_AUTOCONF,
39 .iotype = UPIO_MEM,
40 .regshift = 2,
41 .uartclk = OMAP16XX_BASE_BAUD * 16,
42 }, {
43 .membase = (char *)IO_ADDRESS(OMAP_UART2_BASE),
44 .mapbase = (unsigned long)OMAP_UART2_BASE,
45 .irq = 73,
46 .flags = UPF_BOOT_AUTOCONF,
47 .iotype = UPIO_MEM,
48 .regshift = 2,
49 .uartclk = OMAP16XX_BASE_BAUD * 16,
50 }, {
51 .membase = (char *)IO_ADDRESS(OMAP_UART3_BASE),
52 .mapbase = (unsigned long)OMAP_UART3_BASE,
53 .irq = 74,
54 .flags = UPF_BOOT_AUTOCONF,
55 .iotype = UPIO_MEM,
56 .regshift = 2,
57 .uartclk = OMAP16XX_BASE_BAUD * 16,
58 }, {
59 .flags = 0
60 }
61};
62
63static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
64 int offset)
65{
66 offset <<= up->regshift;
67 return (unsigned int)__raw_readb(up->membase + offset);
68}
69
70static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
71 int value)
72{
73 offset <<= p->regshift;
74 __raw_writeb(value, (unsigned long)(p->membase + offset));
75}
76
77/*
78 * Internal UARTs need to be initialized for the 8250 autoconfig to work
79 * properly. Note that the TX watermark initialization may not be needed
80 * once the 8250.c watermark handling code is merged.
81 */
82static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
83{
84 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
85 serial_write_reg(p, UART_OMAP_SCR, 0x08);
86 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
87 serial_write_reg(p, UART_OMAP_SYSC, 0x01);
88}
89
90void __init omap_serial_init()
91{
92 int i;
93 const struct omap_uart_config *info;
94
95 /*
96 * Make sure the serial ports are muxed on at this point.
97 * You have to mux them off in device drivers later on
98 * if not needed.
99 */
100
101 info = omap_get_config(OMAP_TAG_UART,
102 struct omap_uart_config);
103
104 if (info == NULL)
105 return;
106
107 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
108 struct plat_serial8250_port *p = serial_platform_data + i;
109
110 if (!(info->enabled_uarts & (1 << i))) {
111 p->membase = 0;
112 p->mapbase = 0;
113 continue;
114 }
115
116 switch (i) {
117 case 0:
118 uart1_ick = clk_get(NULL, "uart1_ick");
119 if (IS_ERR(uart1_ick))
120 printk("Could not get uart1_ick\n");
121 else {
122 clk_use(uart1_ick);
123 }
124
125 uart1_fck = clk_get(NULL, "uart1_fck");
126 if (IS_ERR(uart1_fck))
127 printk("Could not get uart1_fck\n");
128 else {
129 clk_use(uart1_fck);
130 }
131 break;
132 case 1:
133 uart2_ick = clk_get(NULL, "uart2_ick");
134 if (IS_ERR(uart2_ick))
135 printk("Could not get uart2_ick\n");
136 else {
137 clk_use(uart2_ick);
138 }
139
140 uart2_fck = clk_get(NULL, "uart2_fck");
141 if (IS_ERR(uart2_fck))
142 printk("Could not get uart2_fck\n");
143 else {
144 clk_use(uart2_fck);
145 }
146 break;
147 case 2:
148 uart3_ick = clk_get(NULL, "uart3_ick");
149 if (IS_ERR(uart3_ick))
150 printk("Could not get uart3_ick\n");
151 else {
152 clk_use(uart3_ick);
153 }
154
155 uart3_fck = clk_get(NULL, "uart3_fck");
156 if (IS_ERR(uart3_fck))
157 printk("Could not get uart3_fck\n");
158 else {
159 clk_use(uart3_fck);
160 }
161 break;
162 }
163
164 omap_serial_reset(p);
165 }
166}
167
168static struct platform_device serial_device = {
169 .name = "serial8250",
170 .id = 0,
171 .dev = {
172 .platform_data = serial_platform_data,
173 },
174};
175
176static int __init omap_init(void)
177{
178 return platform_device_register(&serial_device);
179}
180arch_initcall(omap_init);
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
new file mode 100644
index 000000000000..2a869e203342
--- /dev/null
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -0,0 +1,333 @@
1/*
2 * linux/arch/arm/mach-omap1/sram.S
3 *
4 * Omap2 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2004
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25#include <linux/config.h>
26#include <linux/linkage.h>
27#include <asm/assembler.h>
28#include <asm/arch/io.h>
29#include <asm/hardware.h>
30
31#include <asm/arch/prcm.h>
32
33#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010)
34
35#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
36#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
37#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
38#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
39#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
40#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
41
42#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
43#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
44
45 .text
46
47ENTRY(sram_ddr_init)
48 stmfd sp!, {r0 - r12, lr} @ save registers on stack
49
50 mov r12, r2 @ capture CS1 vs CS0
51 mov r8, r3 @ capture force parameter
52
53 /* frequency shift down */
54 ldr r2, cm_clksel2_pll @ get address of dpllout reg
55 mov r3, #0x1 @ value for 1x operation
56 str r3, [r2] @ go to L1-freq operation
57
58 /* voltage shift down */
59 mov r9, #0x1 @ set up for L1 voltage call
60 bl voltage_shift @ go drop voltage
61
62 /* dll lock mode */
63 ldr r11, sdrc_dlla_ctrl @ addr of dlla ctrl
64 ldr r10, [r11] @ get current val
65 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
66 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
67 mvn r9, #0x4 @ mask to get clear bit2
68 and r10, r10, r9 @ clear bit2 for lock mode.
69 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
70 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
71 str r10, [r11] @ commit to DLLA_CTRL
72 bl i_dll_wait @ wait for dll to lock
73
74 /* get dll value */
75 add r11, r11, #0x4 @ get addr of status reg
76 ldr r10, [r11] @ get locked value
77
78 /* voltage shift up */
79 mov r9, #0x0 @ shift back to L0-voltage
80 bl voltage_shift @ go raise voltage
81
82 /* frequency shift up */
83 mov r3, #0x2 @ value for 2x operation
84 str r3, [r2] @ go to L0-freq operation
85
86 /* reset entry mode for dllctrl */
87 sub r11, r11, #0x4 @ move from status to ctrl
88 cmp r12, #0x1 @ normalize if cs1 based
89 subeq r11, r11, #0x8 @ possibly back to DLLA
90 cmp r8, #0x1 @ if forced unlock exit
91 orreq r1, r1, #0x4 @ make sure exit with unlocked value
92 str r1, [r11] @ restore DLLA_CTRL high value
93 add r11, r11, #0x8 @ move to DLLB_CTRL addr
94 str r1, [r11] @ set value DLLB_CTRL
95 bl i_dll_wait @ wait for possible lock
96
97 /* set up for return, DDR should be good */
98 str r10, [r0] @ write dll_status and return counter
99 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
100
101 /* ensure the DLL has relocked */
102i_dll_wait:
103 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
104i_dll_delay:
105 subs r4, r4, #0x1
106 bne i_dll_delay
107 mov pc, lr
108
109 /*
110 * shift up or down voltage, use R9 as input to tell level.
111 * wait for it to finish, use 32k sync counter, 1tick=31uS.
112 */
113voltage_shift:
114 ldr r4, prcm_voltctrl @ get addr of volt ctrl.
115 ldr r5, [r4] @ get value.
116 ldr r6, prcm_mask_val @ get value of mask
117 and r5, r5, r6 @ apply mask to clear bits
118 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
119 str r5, [r4] @ set up for change.
120 mov r3, #0x4000 @ get val for force
121 orr r5, r5, r3 @ build value for force
122 str r5, [r4] @ Force transition to L1
123
124 ldr r3, timer_32ksynct_cr @ get addr of counter
125 ldr r5, [r3] @ get value
126 add r5, r5, #0x3 @ give it at most 93uS
127volt_delay:
128 ldr r7, [r3] @ get timer value
129 cmp r5, r7 @ time up?
130 bhi volt_delay @ not yet->branch
131 mov pc, lr @ back to caller.
132
133/* relative load constants */
134cm_clksel2_pll:
135 .word CM_CLKSEL2_PLL_V
136sdrc_dlla_ctrl:
137 .word SDRC_DLLA_CTRL_V
138prcm_voltctrl:
139 .word PRCM_VOLTCTRL_V
140prcm_mask_val:
141 .word 0xFFFF3FFC
142timer_32ksynct_cr:
143 .word TIMER_32KSYNCT_CR_V
144ENTRY(sram_ddr_init_sz)
145 .word . - sram_ddr_init
146
147/*
148 * Reprograms memory timings.
149 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
150 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
151 */
152ENTRY(sram_reprogram_sdrc)
153 stmfd sp!, {r0 - r10, lr} @ save registers on stack
154 mov r3, #0x0 @ clear for mrc call
155 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
156 nop
157 nop
158 ldr r6, ddr_sdrc_rfr_ctrl @ get addr of refresh reg
159 ldr r5, [r6] @ get value
160 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
161
162 cmp r0, #0x1 @ going to half speed?
163 movne r9, #0x0 @ if up set flag up for pre up, hi volt
164
165 blne voltage_shift_c @ adjust voltage
166
167 cmp r0, #0x1 @ going to half speed (post branch link)
168 moveq r5, r5, lsr #1 @ divide by 2 if to half
169 movne r5, r5, lsl #1 @ mult by 2 if to full
170 mov r5, r5, lsl #8 @ put rfr field back into place
171 add r5, r5, #0x1 @ turn on burst of 1
172 ldr r4, ddr_cm_clksel2_pll @ get address of out reg
173 ldr r3, [r4] @ get curr value
174 orr r3, r3, #0x3
175 bic r3, r3, #0x3 @ clear lower bits
176 orr r3, r3, r0 @ new state value
177 str r3, [r4] @ set new state (pll/x, x=1 or 2)
178 nop
179 nop
180
181 moveq r9, #0x1 @ if speed down, post down, drop volt
182 bleq voltage_shift_c
183
184 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
185 str r5, [r6] @ set new RFR_1 value
186 add r6, r6, #0x30 @ get RFR_2 addr
187 str r5, [r6] @ set RFR_2
188 nop
189 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
190 bne freq_out @ leave if SDR, no DLL function
191
192 /* With DDR, we need to take care of the DLL for the frequency change */
193 ldr r2, ddr_sdrc_dlla_ctrl @ addr of dlla ctrl
194 str r1, [r2] @ write out new SDRC_DLLA_CTRL
195 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
196 str r1, [r2] @ commit to SDRC_DLLB_CTRL
197 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
198dll_wait:
199 subs r1, r1, #0x1
200 bne dll_wait
201freq_out:
202 ldmfd sp!, {r0 - r10, pc} @ restore regs and return
203
204 /*
205 * shift up or down voltage, use R9 as input to tell level.
206 * wait for it to finish, use 32k sync counter, 1tick=31uS.
207 */
208voltage_shift_c:
209 ldr r10, ddr_prcm_voltctrl @ get addr of volt ctrl
210 ldr r8, [r10] @ get value
211 ldr r7, ddr_prcm_mask_val @ get value of mask
212 and r8, r8, r7 @ apply mask to clear bits
213 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
214 str r8, [r10] @ set up for change.
215 mov r7, #0x4000 @ get val for force
216 orr r8, r8, r7 @ build value for force
217 str r8, [r10] @ Force transition to L1
218
219 ldr r10, ddr_timer_32ksynct @ get addr of counter
220 ldr r8, [r10] @ get value
221 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
222volt_delay_c:
223 ldr r7, [r10] @ get timer value
224 cmp r8, r7 @ time up?
225 bhi volt_delay_c @ not yet->branch
226 mov pc, lr @ back to caller
227
228ddr_cm_clksel2_pll:
229 .word CM_CLKSEL2_PLL_V
230ddr_sdrc_dlla_ctrl:
231 .word SDRC_DLLA_CTRL_V
232ddr_sdrc_rfr_ctrl:
233 .word SDRC_RFR_CTRL_V
234ddr_prcm_voltctrl:
235 .word PRCM_VOLTCTRL_V
236ddr_prcm_mask_val:
237 .word 0xFFFF3FFC
238ddr_timer_32ksynct:
239 .word TIMER_32KSYNCT_CR_V
240
241ENTRY(sram_reprogram_sdrc_sz)
242 .word . - sram_reprogram_sdrc
243
244/*
245 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
246 */
247ENTRY(sram_set_prcm)
248 stmfd sp!, {r0-r12, lr} @ regs to stack
249 adr r4, pbegin @ addr of preload start
250 adr r8, pend @ addr of preload end
251 mcrr p15, 1, r8, r4, c12 @ preload into icache
252pbegin:
253 /* move into fast relock bypass */
254 ldr r8, pll_ctl @ get addr
255 ldr r5, [r8] @ get val
256 mvn r6, #0x3 @ clear mask
257 and r5, r5, r6 @ clear field
258 orr r7, r5, #0x2 @ fast relock val
259 str r7, [r8] @ go to fast relock
260 ldr r4, pll_stat @ addr of stat
261block:
262 /* wait for bypass */
263 ldr r8, [r4] @ stat value
264 and r8, r8, #0x3 @ mask for stat
265 cmp r8, #0x1 @ there yet
266 bne block @ loop if not
267
268 /* set new dpll dividers _after_ in bypass */
269 ldr r4, pll_div @ get addr
270 str r0, [r4] @ set dpll ctrl val
271
272 ldr r4, set_config @ get addr
273 mov r8, #1 @ valid cfg msk
274 str r8, [r4] @ make dividers take
275
276 mov r4, #100 @ dead spin a bit
277wait_a_bit:
278 subs r4, r4, #1 @ dec loop
279 bne wait_a_bit @ delay done?
280
281 /* check if staying in bypass */
282 cmp r2, #0x1 @ stay in bypass?
283 beq pend @ jump over dpll relock
284
285 /* relock DPLL with new vals */
286 ldr r5, pll_stat @ get addr
287 ldr r4, pll_ctl @ get addr
288 orr r8, r7, #0x3 @ val for lock dpll
289 str r8, [r4] @ set val
290 mov r0, #1000 @ dead spin a bit
291wait_more:
292 subs r0, r0, #1 @ dec loop
293 bne wait_more @ delay done?
294wait_lock:
295 ldr r8, [r5] @ get lock val
296 and r8, r8, #3 @ isolate field
297 cmp r8, #2 @ locked?
298 bne wait_lock @ wait if not
299pend:
300 /* update memory timings & briefly lock dll */
301 ldr r4, sdrc_rfr @ get addr
302 str r1, [r4] @ update refresh timing
303 ldr r11, dlla_ctrl @ get addr of DLLA ctrl
304 ldr r10, [r11] @ get current val
305 mvn r9, #0x4 @ mask to get clear bit2
306 and r10, r10, r9 @ clear bit2 for lock mode
307 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
308 str r10, [r11] @ commit to DLLA_CTRL
309 add r11, r11, #0x8 @ move to dllb
310 str r10, [r11] @ hit DLLB also
311
312 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
313wait_dll_lock:
314 subs r4, r4, #0x1
315 bne wait_dll_lock
316 nop
317 ldmfd sp!, {r0-r12, pc} @ restore regs and return
318
319set_config:
320 .word PRCM_CLKCFG_CTRL_V
321pll_ctl:
322 .word CM_CLKEN_PLL_V
323pll_stat:
324 .word CM_IDLEST_CKGEN_V
325pll_div:
326 .word CM_CLKSEL1_PLL_V
327sdrc_rfr:
328 .word SDRC_RFR_CTRL_V
329dlla_ctrl:
330 .word SDRC_DLLA_CTRL_V
331
332ENTRY(sram_set_prcm_sz)
333 .word . - sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
new file mode 100644
index 000000000000..9ec11443200f
--- /dev/null
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -0,0 +1,126 @@
1/*
2 * linux/arch/arm/mach-omap2/timer-gp.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 * Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * Some parts based off of TI's 24xx code:
11 *
12 * Copyright (C) 2004 Texas Instruments, Inc.
13 *
14 * Roughly modelled after the OMAP1 MPU timer code.
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20#include <linux/init.h>
21#include <linux/time.h>
22#include <linux/interrupt.h>
23#include <linux/err.h>
24#include <asm/mach/time.h>
25#include <asm/delay.h>
26#include <asm/io.h>
27#include <asm/hardware/clock.h>
28
29#define OMAP2_GP_TIMER1_BASE 0x48028000
30#define OMAP2_GP_TIMER2_BASE 0x4802a000
31#define OMAP2_GP_TIMER3_BASE 0x48078000
32#define OMAP2_GP_TIMER4_BASE 0x4807a000
33
34#define GP_TIMER_TIDR 0x00
35#define GP_TIMER_TISR 0x18
36#define GP_TIMER_TIER 0x1c
37#define GP_TIMER_TCLR 0x24
38#define GP_TIMER_TCRR 0x28
39#define GP_TIMER_TLDR 0x2c
40#define GP_TIMER_TSICR 0x40
41
42#define OS_TIMER_NR 1 /* GP timer 2 */
43
44static unsigned long timer_base[] = {
45 IO_ADDRESS(OMAP2_GP_TIMER1_BASE),
46 IO_ADDRESS(OMAP2_GP_TIMER2_BASE),
47 IO_ADDRESS(OMAP2_GP_TIMER3_BASE),
48 IO_ADDRESS(OMAP2_GP_TIMER4_BASE),
49};
50
51static inline unsigned int timer_read_reg(int nr, unsigned int reg)
52{
53 return __raw_readl(timer_base[nr] + reg);
54}
55
56static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val)
57{
58 __raw_writel(val, timer_base[nr] + reg);
59}
60
61/* Note that we always enable the clock prescale divider bit */
62static inline void omap2_gp_timer_start(int nr, unsigned long load_val)
63{
64 unsigned int tmp;
65
66 tmp = 0xffffffff - load_val;
67
68 timer_write_reg(nr, GP_TIMER_TLDR, tmp);
69 timer_write_reg(nr, GP_TIMER_TCRR, tmp);
70 timer_write_reg(nr, GP_TIMER_TIER, 1 << 1);
71 timer_write_reg(nr, GP_TIMER_TCLR, (1 << 5) | (1 << 1) | 1);
72}
73
74static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
75 struct pt_regs *regs)
76{
77 write_seqlock(&xtime_lock);
78
79 timer_write_reg(OS_TIMER_NR, GP_TIMER_TISR, 1 << 1);
80 timer_tick(regs);
81
82 write_sequnlock(&xtime_lock);
83
84 return IRQ_HANDLED;
85}
86
87static struct irqaction omap2_gp_timer_irq = {
88 .name = "gp timer",
89 .flags = SA_INTERRUPT,
90 .handler = omap2_gp_timer_interrupt,
91};
92
93static void __init omap2_gp_timer_init(void)
94{
95 struct clk * sys_ck;
96 u32 tick_period = 120000;
97 u32 l;
98
99 /* Reset clock and prescale value */
100 timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0);
101
102 sys_ck = clk_get(NULL, "sys_ck");
103 if (IS_ERR(sys_ck))
104 printk(KERN_ERR "Could not get sys_ck\n");
105 else {
106 clk_use(sys_ck);
107 tick_period = clk_get_rate(sys_ck) / 100;
108 clk_put(sys_ck);
109 }
110
111 tick_period /= 2; /* Minimum prescale divider is 2 */
112 tick_period -= 1;
113
114 l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR);
115 printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n",
116 (l >> 4) & 0x0f, l & 0x0f);
117
118 setup_irq(38, &omap2_gp_timer_irq);
119
120 omap2_gp_timer_start(OS_TIMER_NR, tick_period);
121}
122
123struct sys_timer omap_timer = {
124 .init = omap2_gp_timer_init,
125};
126
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 03:41:26 -0500