aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/gpmc.c432
1 files changed, 0 insertions, 432 deletions
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f5cde49854a5..05aca39f52cb 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -143,7 +143,6 @@ static struct resource gpmc_mem_root;
143static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 143static struct resource gpmc_cs_mem[GPMC_CS_NUM];
144static DEFINE_SPINLOCK(gpmc_mem_lock); 144static DEFINE_SPINLOCK(gpmc_mem_lock);
145static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ 145static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
146static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
147static struct device *gpmc_dev; 146static struct device *gpmc_dev;
148static int gpmc_irq; 147static int gpmc_irq;
149static resource_size_t phys_base, mem_size; 148static resource_size_t phys_base, mem_size;
@@ -164,22 +163,6 @@ static u32 gpmc_read_reg(int idx)
164 return __raw_readl(gpmc_base + idx); 163 return __raw_readl(gpmc_base + idx);
165} 164}
166 165
167static void gpmc_cs_write_byte(int cs, int idx, u8 val)
168{
169 void __iomem *reg_addr;
170
171 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
172 __raw_writeb(val, reg_addr);
173}
174
175static u8 gpmc_cs_read_byte(int cs, int idx)
176{
177 void __iomem *reg_addr;
178
179 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
180 return __raw_readb(reg_addr);
181}
182
183void gpmc_cs_write_reg(int cs, int idx, u32 val) 166void gpmc_cs_write_reg(int cs, int idx, u32 val)
184{ 167{
185 void __iomem *reg_addr; 168 void __iomem *reg_addr;
@@ -515,44 +498,6 @@ void gpmc_cs_free(int cs)
515EXPORT_SYMBOL(gpmc_cs_free); 498EXPORT_SYMBOL(gpmc_cs_free);
516 499
517/** 500/**
518 * gpmc_read_status - read access request to get the different gpmc status
519 * @cmd: command type
520 * @return status
521 */
522int gpmc_read_status(int cmd)
523{
524 int status = -EINVAL;
525 u32 regval = 0;
526
527 switch (cmd) {
528 case GPMC_GET_IRQ_STATUS:
529 status = gpmc_read_reg(GPMC_IRQSTATUS);
530 break;
531
532 case GPMC_PREFETCH_FIFO_CNT:
533 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
534 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
535 break;
536
537 case GPMC_PREFETCH_COUNT:
538 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
539 status = GPMC_PREFETCH_STATUS_COUNT(regval);
540 break;
541
542 case GPMC_STATUS_BUFFER:
543 regval = gpmc_read_reg(GPMC_STATUS);
544 /* 1 : buffer is available to write */
545 status = regval & GPMC_STATUS_BUFF_EMPTY;
546 break;
547
548 default:
549 printk(KERN_ERR "gpmc_read_status: Not supported\n");
550 }
551 return status;
552}
553EXPORT_SYMBOL(gpmc_read_status);
554
555/**
556 * gpmc_cs_configure - write request to configure gpmc 501 * gpmc_cs_configure - write request to configure gpmc
557 * @cs: chip select number 502 * @cs: chip select number
558 * @cmd: command type 503 * @cmd: command type
@@ -620,119 +565,6 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
620} 565}
621EXPORT_SYMBOL(gpmc_cs_configure); 566EXPORT_SYMBOL(gpmc_cs_configure);
622 567
623/**
624 * gpmc_nand_read - nand specific read access request
625 * @cs: chip select number
626 * @cmd: command type
627 */
628int gpmc_nand_read(int cs, int cmd)
629{
630 int rval = -EINVAL;
631
632 switch (cmd) {
633 case GPMC_NAND_DATA:
634 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
635 break;
636
637 default:
638 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
639 }
640 return rval;
641}
642EXPORT_SYMBOL(gpmc_nand_read);
643
644/**
645 * gpmc_nand_write - nand specific write request
646 * @cs: chip select number
647 * @cmd: command type
648 * @wval: value to write
649 */
650int gpmc_nand_write(int cs, int cmd, int wval)
651{
652 int err = 0;
653
654 switch (cmd) {
655 case GPMC_NAND_COMMAND:
656 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
657 break;
658
659 case GPMC_NAND_ADDRESS:
660 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
661 break;
662
663 case GPMC_NAND_DATA:
664 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
665
666 default:
667 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
668 err = -EINVAL;
669 }
670 return err;
671}
672EXPORT_SYMBOL(gpmc_nand_write);
673
674
675
676/**
677 * gpmc_prefetch_enable - configures and starts prefetch transfer
678 * @cs: cs (chip select) number
679 * @fifo_th: fifo threshold to be used for read/ write
680 * @dma_mode: dma mode enable (1) or disable (0)
681 * @u32_count: number of bytes to be transferred
682 * @is_write: prefetch read(0) or write post(1) mode
683 */
684int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
685 unsigned int u32_count, int is_write)
686{
687
688 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
689 pr_err("gpmc: fifo threshold is not supported\n");
690 return -1;
691 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
692 /* Set the amount of bytes to be prefetched */
693 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
694
695 /* Set dma/mpu mode, the prefetch read / post write and
696 * enable the engine. Set which cs is has requested for.
697 */
698 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
699 PREFETCH_FIFOTHRESHOLD(fifo_th) |
700 ENABLE_PREFETCH |
701 (dma_mode << DMA_MPU_MODE) |
702 (0x1 & is_write)));
703
704 /* Start the prefetch engine */
705 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
706 } else {
707 return -EBUSY;
708 }
709
710 return 0;
711}
712EXPORT_SYMBOL(gpmc_prefetch_enable);
713
714/**
715 * gpmc_prefetch_reset - disables and stops the prefetch engine
716 */
717int gpmc_prefetch_reset(int cs)
718{
719 u32 config1;
720
721 /* check if the same module/cs is trying to reset */
722 config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
723 if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
724 return -EINVAL;
725
726 /* Stop the PFPW engine */
727 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
728
729 /* Reset/disable the PFPW engine */
730 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
731
732 return 0;
733}
734EXPORT_SYMBOL(gpmc_prefetch_reset);
735
736void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) 568void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
737{ 569{
738 int i; 570 int i;
@@ -1097,267 +929,3 @@ void omap3_gpmc_restore_context(void)
1097 } 929 }
1098} 930}
1099#endif /* CONFIG_ARCH_OMAP3 */ 931#endif /* CONFIG_ARCH_OMAP3 */
1100
1101/**
1102 * gpmc_enable_hwecc - enable hardware ecc functionality
1103 * @cs: chip select number
1104 * @mode: read/write mode
1105 * @dev_width: device bus width(1 for x16, 0 for x8)
1106 * @ecc_size: bytes for which ECC will be generated
1107 */
1108int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
1109{
1110 unsigned int val;
1111
1112 /* check if ecc module is in used */
1113 if (gpmc_ecc_used != -EINVAL)
1114 return -EINVAL;
1115
1116 gpmc_ecc_used = cs;
1117
1118 /* clear ecc and enable bits */
1119 gpmc_write_reg(GPMC_ECC_CONTROL,
1120 GPMC_ECC_CTRL_ECCCLEAR |
1121 GPMC_ECC_CTRL_ECCREG1);
1122
1123 /* program ecc and result sizes */
1124 val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
1125 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
1126
1127 switch (mode) {
1128 case GPMC_ECC_READ:
1129 case GPMC_ECC_WRITE:
1130 gpmc_write_reg(GPMC_ECC_CONTROL,
1131 GPMC_ECC_CTRL_ECCCLEAR |
1132 GPMC_ECC_CTRL_ECCREG1);
1133 break;
1134 case GPMC_ECC_READSYN:
1135 gpmc_write_reg(GPMC_ECC_CONTROL,
1136 GPMC_ECC_CTRL_ECCCLEAR |
1137 GPMC_ECC_CTRL_ECCDISABLE);
1138 break;
1139 default:
1140 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
1141 break;
1142 }
1143
1144 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
1145 val = (dev_width << 7) | (cs << 1) | (0x1);
1146 gpmc_write_reg(GPMC_ECC_CONFIG, val);
1147 return 0;
1148}
1149EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
1150
1151/**
1152 * gpmc_calculate_ecc - generate non-inverted ecc bytes
1153 * @cs: chip select number
1154 * @dat: data pointer over which ecc is computed
1155 * @ecc_code: ecc code buffer
1156 *
1157 * Using non-inverted ECC is considered ugly since writing a blank
1158 * page (padding) will clear the ECC bytes. This is not a problem as long
1159 * no one is trying to write data on the seemingly unused page. Reading
1160 * an erased page will produce an ECC mismatch between generated and read
1161 * ECC bytes that has to be dealt with separately.
1162 */
1163int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
1164{
1165 unsigned int val = 0x0;
1166
1167 if (gpmc_ecc_used != cs)
1168 return -EINVAL;
1169
1170 /* read ecc result */
1171 val = gpmc_read_reg(GPMC_ECC1_RESULT);
1172 *ecc_code++ = val; /* P128e, ..., P1e */
1173 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
1174 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
1175 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
1176
1177 gpmc_ecc_used = -EINVAL;
1178 return 0;
1179}
1180EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
1181
1182#ifdef CONFIG_ARCH_OMAP3
1183
1184/**
1185 * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
1186 * @cs: chip select number
1187 * @nsectors: how many 512-byte sectors to process
1188 * @nerrors: how many errors to correct per sector (4 or 8)
1189 *
1190 * This function must be executed before any call to gpmc_enable_hwecc_bch.
1191 */
1192int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
1193{
1194 /* check if ecc module is in use */
1195 if (gpmc_ecc_used != -EINVAL)
1196 return -EINVAL;
1197
1198 /* support only OMAP3 class */
1199 if (!cpu_is_omap34xx()) {
1200 printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
1201 return -EINVAL;
1202 }
1203
1204 /*
1205 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
1206 * Other chips may be added if confirmed to work.
1207 */
1208 if ((nerrors == 4) &&
1209 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
1210 printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
1211 return -EINVAL;
1212 }
1213
1214 /* sanity check */
1215 if (nsectors > 8) {
1216 printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
1217 nsectors);
1218 return -EINVAL;
1219 }
1220
1221 return 0;
1222}
1223EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
1224
1225/**
1226 * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
1227 * @cs: chip select number
1228 * @mode: read/write mode
1229 * @dev_width: device bus width(1 for x16, 0 for x8)
1230 * @nsectors: how many 512-byte sectors to process
1231 * @nerrors: how many errors to correct per sector (4 or 8)
1232 */
1233int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
1234 int nerrors)
1235{
1236 unsigned int val;
1237
1238 /* check if ecc module is in use */
1239 if (gpmc_ecc_used != -EINVAL)
1240 return -EINVAL;
1241
1242 gpmc_ecc_used = cs;
1243
1244 /* clear ecc and enable bits */
1245 gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
1246
1247 /*
1248 * When using BCH, sector size is hardcoded to 512 bytes.
1249 * Here we are using wrapping mode 6 both for reading and writing, with:
1250 * size0 = 0 (no additional protected byte in spare area)
1251 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1252 */
1253 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
1254
1255 /* BCH configuration */
1256 val = ((1 << 16) | /* enable BCH */
1257 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1258 (0x06 << 8) | /* wrap mode = 6 */
1259 (dev_width << 7) | /* bus width */
1260 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1261 (cs << 1) | /* ECC CS */
1262 (0x1)); /* enable ECC */
1263
1264 gpmc_write_reg(GPMC_ECC_CONFIG, val);
1265 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
1266 return 0;
1267}
1268EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
1269
1270/**
1271 * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1272 * @cs: chip select number
1273 * @dat: The pointer to data on which ecc is computed
1274 * @ecc: The ecc output buffer
1275 */
1276int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
1277{
1278 int i;
1279 unsigned long nsectors, reg, val1, val2;
1280
1281 if (gpmc_ecc_used != cs)
1282 return -EINVAL;
1283
1284 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1285
1286 for (i = 0; i < nsectors; i++) {
1287
1288 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1289
1290 /* Read hw-computed remainder */
1291 val1 = gpmc_read_reg(reg + 0);
1292 val2 = gpmc_read_reg(reg + 4);
1293
1294 /*
1295 * Add constant polynomial to remainder, in order to get an ecc
1296 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1297 * left-justify the resulting polynomial.
1298 */
1299 *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1300 *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1301 *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1302 *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1303 *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1304 *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
1305 *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
1306 }
1307
1308 gpmc_ecc_used = -EINVAL;
1309 return 0;
1310}
1311EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
1312
1313/**
1314 * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1315 * @cs: chip select number
1316 * @dat: The pointer to data on which ecc is computed
1317 * @ecc: The ecc output buffer
1318 */
1319int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
1320{
1321 int i;
1322 unsigned long nsectors, reg, val1, val2, val3, val4;
1323
1324 if (gpmc_ecc_used != cs)
1325 return -EINVAL;
1326
1327 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1328
1329 for (i = 0; i < nsectors; i++) {
1330
1331 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1332
1333 /* Read hw-computed remainder */
1334 val1 = gpmc_read_reg(reg + 0);
1335 val2 = gpmc_read_reg(reg + 4);
1336 val3 = gpmc_read_reg(reg + 8);
1337 val4 = gpmc_read_reg(reg + 12);
1338
1339 /*
1340 * Add constant polynomial to remainder, in order to get an ecc
1341 * sequence of 0xFFs for a buffer filled with 0xFFs.
1342 */
1343 *ecc++ = 0xef ^ (val4 & 0xFF);
1344 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1345 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1346 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1347 *ecc++ = 0xed ^ (val3 & 0xFF);
1348 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1349 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1350 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1351 *ecc++ = 0x97 ^ (val2 & 0xFF);
1352 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1353 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1354 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1355 *ecc++ = 0xb5 ^ (val1 & 0xFF);
1356 }
1357
1358 gpmc_ecc_used = -EINVAL;
1359 return 0;
1360}
1361EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
1362
1363#endif /* CONFIG_ARCH_OMAP3 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 03:37:34 -0500