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-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c50
-rw-r--r--arch/arm/mach-omap2/common.c14
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c11
-rw-r--r--arch/arm/mach-omap2/include/mach/omap4-common.h4
-rw-r--r--arch/arm/mach-omap2/mailbox.c10
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S2
-rw-r--r--arch/arm/mach-omap2/omap44xx-smc.S8
-rw-r--r--arch/arm/mach-omap2/omap_twl.c60
-rw-r--r--arch/arm/mach-omap2/opp3xxx_data.c3
-rw-r--r--arch/arm/mach-omap2/opp4xxx_data.c3
-rw-r--r--arch/arm/mach-omap2/pm.c4
-rw-r--r--arch/arm/mach-omap2/pm.h1
-rw-r--r--arch/arm/mach-omap2/pm24xx.c8
-rw-r--r--arch/arm/mach-omap2/pm34xx.c25
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S282
-rw-r--r--arch/arm/mach-omap2/smartreflex.c62
-rw-r--r--arch/arm/mach-omap2/sram34xx.S36
17 files changed, 339 insertions, 244 deletions
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index b6752ac5b97e..20c5dbea8953 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -23,6 +23,7 @@
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <linux/input.h> 24#include <linux/input.h>
25#include <linux/gpio_keys.h> 25#include <linux/gpio_keys.h>
26#include <linux/opp.h>
26 27
27#include <linux/mtd/mtd.h> 28#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
@@ -45,10 +46,12 @@
45#include <plat/gpmc.h> 46#include <plat/gpmc.h>
46#include <plat/nand.h> 47#include <plat/nand.h>
47#include <plat/usb.h> 48#include <plat/usb.h>
49#include <plat/omap_device.h>
48 50
49#include "mux.h" 51#include "mux.h"
50#include "hsmmc.h" 52#include "hsmmc.h"
51#include "timer-gp.h" 53#include "timer-gp.h"
54#include "pm.h"
52 55
53#define NAND_BLOCK_SIZE SZ_128K 56#define NAND_BLOCK_SIZE SZ_128K
54 57
@@ -603,6 +606,52 @@ static struct omap_musb_board_data musb_board_data = {
603 .power = 100, 606 .power = 100,
604}; 607};
605 608
609static void __init beagle_opp_init(void)
610{
611 int r = 0;
612
613 /* Initialize the omap3 opp table */
614 if (omap3_opp_init()) {
615 pr_err("%s: opp default init failed\n", __func__);
616 return;
617 }
618
619 /* Custom OPP enabled for XM */
620 if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
621 struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
622 struct omap_hwmod *dh = omap_hwmod_lookup("iva");
623 struct device *dev;
624
625 if (!mh || !dh) {
626 pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
627 __func__, mh, dh);
628 return;
629 }
630 /* Enable MPU 1GHz and lower opps */
631 dev = &mh->od->pdev.dev;
632 r = opp_enable(dev, 800000000);
633 /* TODO: MPU 1GHz needs SR and ABB */
634
635 /* Enable IVA 800MHz and lower opps */
636 dev = &dh->od->pdev.dev;
637 r |= opp_enable(dev, 660000000);
638 /* TODO: DSP 800MHz needs SR and ABB */
639 if (r) {
640 pr_err("%s: failed to enable higher opp %d\n",
641 __func__, r);
642 /*
643 * Cleanup - disable the higher freqs - we dont care
644 * about the results
645 */
646 dev = &mh->od->pdev.dev;
647 opp_disable(dev, 800000000);
648 dev = &dh->od->pdev.dev;
649 opp_disable(dev, 660000000);
650 }
651 }
652 return;
653}
654
606static void __init omap3_beagle_init(void) 655static void __init omap3_beagle_init(void)
607{ 656{
608 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 657 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -627,6 +676,7 @@ static void __init omap3_beagle_init(void)
627 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); 676 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
628 677
629 beagle_display_init(); 678 beagle_display_init();
679 beagle_opp_init();
630} 680}
631 681
632MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") 682MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 48de4513de49..3f20cbb9967b 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -50,9 +50,6 @@ static struct omap_globals omap242x_globals = {
50 .ctrl = OMAP242X_CTRL_BASE, 50 .ctrl = OMAP242X_CTRL_BASE,
51 .prm = OMAP2420_PRM_BASE, 51 .prm = OMAP2420_PRM_BASE,
52 .cm = OMAP2420_CM_BASE, 52 .cm = OMAP2420_CM_BASE,
53 .uart1_phys = OMAP2_UART1_BASE,
54 .uart2_phys = OMAP2_UART2_BASE,
55 .uart3_phys = OMAP2_UART3_BASE,
56}; 53};
57 54
58void __init omap2_set_globals_242x(void) 55void __init omap2_set_globals_242x(void)
@@ -71,9 +68,6 @@ static struct omap_globals omap243x_globals = {
71 .ctrl = OMAP243X_CTRL_BASE, 68 .ctrl = OMAP243X_CTRL_BASE,
72 .prm = OMAP2430_PRM_BASE, 69 .prm = OMAP2430_PRM_BASE,
73 .cm = OMAP2430_CM_BASE, 70 .cm = OMAP2430_CM_BASE,
74 .uart1_phys = OMAP2_UART1_BASE,
75 .uart2_phys = OMAP2_UART2_BASE,
76 .uart3_phys = OMAP2_UART3_BASE,
77}; 71};
78 72
79void __init omap2_set_globals_243x(void) 73void __init omap2_set_globals_243x(void)
@@ -92,10 +86,6 @@ static struct omap_globals omap3_globals = {
92 .ctrl = OMAP343X_CTRL_BASE, 86 .ctrl = OMAP343X_CTRL_BASE,
93 .prm = OMAP3430_PRM_BASE, 87 .prm = OMAP3430_PRM_BASE,
94 .cm = OMAP3430_CM_BASE, 88 .cm = OMAP3430_CM_BASE,
95 .uart1_phys = OMAP3_UART1_BASE,
96 .uart2_phys = OMAP3_UART2_BASE,
97 .uart3_phys = OMAP3_UART3_BASE,
98 .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */
99}; 89};
100 90
101void __init omap2_set_globals_3xxx(void) 91void __init omap2_set_globals_3xxx(void)
@@ -140,10 +130,6 @@ static struct omap_globals omap4_globals = {
140 .prm = OMAP4430_PRM_BASE, 130 .prm = OMAP4430_PRM_BASE,
141 .cm = OMAP4430_CM_BASE, 131 .cm = OMAP4430_CM_BASE,
142 .cm2 = OMAP4430_CM2_BASE, 132 .cm2 = OMAP4430_CM2_BASE,
143 .uart1_phys = OMAP4_UART1_BASE,
144 .uart2_phys = OMAP4_UART2_BASE,
145 .uart3_phys = OMAP4_UART3_BASE,
146 .uart4_phys = OMAP4_UART4_BASE,
147}; 133};
148 134
149void __init omap2_set_globals_443x(void) 135void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f7b22a16f385..cba437dd002b 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -58,6 +58,7 @@ struct omap3_processor_cx {
58 u32 core_state; 58 u32 core_state;
59 u32 threshold; 59 u32 threshold;
60 u32 flags; 60 u32 flags;
61 const char *desc;
61}; 62};
62 63
63struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; 64struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
@@ -365,6 +366,7 @@ void omap_init_power_states(void)
365 omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; 366 omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
366 omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; 367 omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
367 omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; 368 omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
369 omap3_power_states[OMAP3_STATE_C1].desc = "MPU ON + CORE ON";
368 370
369 /* C2 . MPU WFI + Core inactive */ 371 /* C2 . MPU WFI + Core inactive */
370 omap3_power_states[OMAP3_STATE_C2].valid = 372 omap3_power_states[OMAP3_STATE_C2].valid =
@@ -380,6 +382,7 @@ void omap_init_power_states(void)
380 omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; 382 omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
381 omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | 383 omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
382 CPUIDLE_FLAG_CHECK_BM; 384 CPUIDLE_FLAG_CHECK_BM;
385 omap3_power_states[OMAP3_STATE_C2].desc = "MPU ON + CORE ON";
383 386
384 /* C3 . MPU CSWR + Core inactive */ 387 /* C3 . MPU CSWR + Core inactive */
385 omap3_power_states[OMAP3_STATE_C3].valid = 388 omap3_power_states[OMAP3_STATE_C3].valid =
@@ -395,6 +398,7 @@ void omap_init_power_states(void)
395 omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; 398 omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
396 omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | 399 omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
397 CPUIDLE_FLAG_CHECK_BM; 400 CPUIDLE_FLAG_CHECK_BM;
401 omap3_power_states[OMAP3_STATE_C3].desc = "MPU RET + CORE ON";
398 402
399 /* C4 . MPU OFF + Core inactive */ 403 /* C4 . MPU OFF + Core inactive */
400 omap3_power_states[OMAP3_STATE_C4].valid = 404 omap3_power_states[OMAP3_STATE_C4].valid =
@@ -410,6 +414,7 @@ void omap_init_power_states(void)
410 omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; 414 omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
411 omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | 415 omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
412 CPUIDLE_FLAG_CHECK_BM; 416 CPUIDLE_FLAG_CHECK_BM;
417 omap3_power_states[OMAP3_STATE_C4].desc = "MPU OFF + CORE ON";
413 418
414 /* C5 . MPU CSWR + Core CSWR*/ 419 /* C5 . MPU CSWR + Core CSWR*/
415 omap3_power_states[OMAP3_STATE_C5].valid = 420 omap3_power_states[OMAP3_STATE_C5].valid =
@@ -425,6 +430,7 @@ void omap_init_power_states(void)
425 omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; 430 omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
426 omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | 431 omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
427 CPUIDLE_FLAG_CHECK_BM; 432 CPUIDLE_FLAG_CHECK_BM;
433 omap3_power_states[OMAP3_STATE_C5].desc = "MPU RET + CORE RET";
428 434
429 /* C6 . MPU OFF + Core CSWR */ 435 /* C6 . MPU OFF + Core CSWR */
430 omap3_power_states[OMAP3_STATE_C6].valid = 436 omap3_power_states[OMAP3_STATE_C6].valid =
@@ -440,6 +446,7 @@ void omap_init_power_states(void)
440 omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; 446 omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
441 omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | 447 omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
442 CPUIDLE_FLAG_CHECK_BM; 448 CPUIDLE_FLAG_CHECK_BM;
449 omap3_power_states[OMAP3_STATE_C6].desc = "MPU OFF + CORE RET";
443 450
444 /* C7 . MPU OFF + Core OFF */ 451 /* C7 . MPU OFF + Core OFF */
445 omap3_power_states[OMAP3_STATE_C7].valid = 452 omap3_power_states[OMAP3_STATE_C7].valid =
@@ -455,6 +462,7 @@ void omap_init_power_states(void)
455 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; 462 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
456 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | 463 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
457 CPUIDLE_FLAG_CHECK_BM; 464 CPUIDLE_FLAG_CHECK_BM;
465 omap3_power_states[OMAP3_STATE_C7].desc = "MPU OFF + CORE OFF";
458 466
459 /* 467 /*
460 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot 468 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
@@ -464,7 +472,7 @@ void omap_init_power_states(void)
464 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) { 472 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
465 omap3_power_states[OMAP3_STATE_C7].valid = 0; 473 omap3_power_states[OMAP3_STATE_C7].valid = 0;
466 cpuidle_params_table[OMAP3_STATE_C7].valid = 0; 474 cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
467 WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n", 475 pr_warn("%s: core off state C7 disabled due to i583\n",
468 __func__); 476 __func__);
469 } 477 }
470} 478}
@@ -512,6 +520,7 @@ int __init omap3_idle_init(void)
512 if (cx->type == OMAP3_STATE_C1) 520 if (cx->type == OMAP3_STATE_C1)
513 dev->safe_state = state; 521 dev->safe_state = state;
514 sprintf(state->name, "C%d", count+1); 522 sprintf(state->name, "C%d", count+1);
523 strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
515 count++; 524 count++;
516 } 525 }
517 526
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 5b0270b28934..de441c05a6a6 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -17,8 +17,12 @@
17 * wfi used in low power code. Directly opcode is used instead 17 * wfi used in low power code. Directly opcode is used instead
18 * of instruction to avoid mulit-omap build break 18 * of instruction to avoid mulit-omap build break
19 */ 19 */
20#ifdef CONFIG_THUMB2_KERNEL
21#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
22#else
20#define do_wfi() \ 23#define do_wfi() \
21 __asm__ __volatile__ (".word 0xe320f003" : : : "memory") 24 __asm__ __volatile__ (".word 0xe320f003" : : : "memory")
25#endif
22 26
23#ifdef CONFIG_CACHE_L2X0 27#ifdef CONFIG_CACHE_L2X0
24extern void __iomem *l2cache_base; 28extern void __iomem *l2cache_base;
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 6e15e3d7c65e..86d564a640bb 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -138,10 +138,12 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
138 omap_mbox_type_t irq) 138 omap_mbox_type_t irq)
139{ 139{
140 struct omap_mbox2_priv *p = mbox->priv; 140 struct omap_mbox2_priv *p = mbox->priv;
141 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; 141 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
142 l = mbox_read_reg(p->irqdisable); 142
143 l &= ~bit; 143 if (!cpu_is_omap44xx())
144 mbox_write_reg(l, p->irqdisable); 144 bit = mbox_read_reg(p->irqdisable) & ~bit;
145
146 mbox_write_reg(bit, p->irqdisable);
145} 147}
146 148
147static void omap2_mbox_ack_irq(struct omap_mbox *mbox, 149static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 6ae937a06cc1..4ee6aeca885a 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -45,5 +45,5 @@ hold: ldr r12,=0x103
45 * should now contain the SVC stack for this core 45 * should now contain the SVC stack for this core
46 */ 46 */
47 b secondary_startup 47 b secondary_startup
48END(omap_secondary_startup) 48ENDPROC(omap_secondary_startup)
49 49
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
index 1980dc31a1a2..e69d37d95204 100644
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ b/arch/arm/mach-omap2/omap44xx-smc.S
@@ -29,7 +29,7 @@ ENTRY(omap_smc1)
29 dsb 29 dsb
30 smc #0 30 smc #0
31 ldmfd sp!, {r2-r12, pc} 31 ldmfd sp!, {r2-r12, pc}
32END(omap_smc1) 32ENDPROC(omap_smc1)
33 33
34ENTRY(omap_modify_auxcoreboot0) 34ENTRY(omap_modify_auxcoreboot0)
35 stmfd sp!, {r1-r12, lr} 35 stmfd sp!, {r1-r12, lr}
@@ -37,7 +37,7 @@ ENTRY(omap_modify_auxcoreboot0)
37 dsb 37 dsb
38 smc #0 38 smc #0
39 ldmfd sp!, {r1-r12, pc} 39 ldmfd sp!, {r1-r12, pc}
40END(omap_modify_auxcoreboot0) 40ENDPROC(omap_modify_auxcoreboot0)
41 41
42ENTRY(omap_auxcoreboot_addr) 42ENTRY(omap_auxcoreboot_addr)
43 stmfd sp!, {r2-r12, lr} 43 stmfd sp!, {r2-r12, lr}
@@ -45,7 +45,7 @@ ENTRY(omap_auxcoreboot_addr)
45 dsb 45 dsb
46 smc #0 46 smc #0
47 ldmfd sp!, {r2-r12, pc} 47 ldmfd sp!, {r2-r12, pc}
48END(omap_auxcoreboot_addr) 48ENDPROC(omap_auxcoreboot_addr)
49 49
50ENTRY(omap_read_auxcoreboot0) 50ENTRY(omap_read_auxcoreboot0)
51 stmfd sp!, {r2-r12, lr} 51 stmfd sp!, {r2-r12, lr}
@@ -54,4 +54,4 @@ ENTRY(omap_read_auxcoreboot0)
54 smc #0 54 smc #0
55 mov r0, r0, lsr #9 55 mov r0, r0, lsr #9
56 ldmfd sp!, {r2-r12, pc} 56 ldmfd sp!, {r2-r12, pc}
57END(omap_read_auxcoreboot0) 57ENDPROC(omap_read_auxcoreboot0)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 00e1d2b53683..b341c36a93f3 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -59,8 +59,15 @@
59 59
60static bool is_offset_valid; 60static bool is_offset_valid;
61static u8 smps_offset; 61static u8 smps_offset;
62/*
63 * Flag to ensure Smartreflex bit in TWL
64 * being cleared in board file is not overwritten.
65 */
66static bool __initdata twl_sr_enable_autoinit;
62 67
68#define TWL4030_DCDC_GLOBAL_CFG 0x06
63#define REG_SMPS_OFFSET 0xE0 69#define REG_SMPS_OFFSET 0xE0
70#define SMARTREFLEX_ENABLE BIT(3)
64 71
65static unsigned long twl4030_vsel_to_uv(const u8 vsel) 72static unsigned long twl4030_vsel_to_uv(const u8 vsel)
66{ 73{
@@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
269 omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; 276 omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
270 } 277 }
271 278
279 /*
280 * The smartreflex bit on twl4030 specifies if the setting of voltage
281 * is done over the I2C_SR path. Since this setting is independent of
282 * the actual usage of smartreflex AVS module, we enable TWL SR bit
283 * by default irrespective of whether smartreflex AVS module is enabled
284 * on the OMAP side or not. This is because without this bit enabled,
285 * the voltage scaling through vp forceupdate/bypass mechanism of
286 * voltage scaling will not function on TWL over I2C_SR.
287 */
288 if (!twl_sr_enable_autoinit)
289 omap3_twl_set_sr_bit(true);
290
272 voltdm = omap_voltage_domain_lookup("mpu"); 291 voltdm = omap_voltage_domain_lookup("mpu");
273 omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info); 292 omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
274 293
@@ -277,3 +296,44 @@ int __init omap3_twl_init(void)
277 296
278 return 0; 297 return 0;
279} 298}
299
300/**
301 * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
302 * @enable: enable SR mode in twl or not
303 *
304 * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
305 * voltage scaling through OMAP SR works. Else, the smartreflex bit
306 * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
307 * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
308 * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
309 * in those scenarios this bit is to be cleared (enable = false).
310 *
311 * Returns 0 on sucess, error is returned if I2C read/write fails.
312 */
313int __init omap3_twl_set_sr_bit(bool enable)
314{
315 u8 temp;
316 int ret;
317 if (twl_sr_enable_autoinit)
318 pr_warning("%s: unexpected multiple calls\n", __func__);
319
320 ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
321 TWL4030_DCDC_GLOBAL_CFG);
322 if (ret)
323 goto err;
324
325 if (enable)
326 temp |= SMARTREFLEX_ENABLE;
327 else
328 temp &= ~SMARTREFLEX_ENABLE;
329
330 ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
331 TWL4030_DCDC_GLOBAL_CFG);
332 if (!ret) {
333 twl_sr_enable_autoinit = true;
334 return 0;
335 }
336err:
337 pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
338 return ret;
339}
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index 0486fce8a92c..fd3a1af8d51e 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -21,6 +21,7 @@
21#include <plat/cpu.h> 21#include <plat/cpu.h>
22 22
23#include "omap_opp_data.h" 23#include "omap_opp_data.h"
24#include "pm.h"
24 25
25static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { 26static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
26 /* MPU OPP1 */ 27 /* MPU OPP1 */
@@ -88,7 +89,7 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
88/** 89/**
89 * omap3_opp_init() - initialize omap3 opp table 90 * omap3_opp_init() - initialize omap3 opp table
90 */ 91 */
91static int __init omap3_opp_init(void) 92int __init omap3_opp_init(void)
92{ 93{
93 int r = -ENODEV; 94 int r = -ENODEV;
94 95
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index a11fa566d8ee..f0e9939a7217 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -22,6 +22,7 @@
22#include <plat/cpu.h> 22#include <plat/cpu.h>
23 23
24#include "omap_opp_data.h" 24#include "omap_opp_data.h"
25#include "pm.h"
25 26
26static struct omap_opp_def __initdata omap44xx_opp_def_list[] = { 27static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
27 /* MPU OPP1 - OPP50 */ 28 /* MPU OPP1 - OPP50 */
@@ -42,7 +43,7 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
42/** 43/**
43 * omap4_opp_init() - initialize omap4 opp table 44 * omap4_opp_init() - initialize omap4 opp table
44 */ 45 */
45static int __init omap4_opp_init(void) 46int __init omap4_opp_init(void)
46{ 47{
47 int r = -ENODEV; 48 int r = -ENODEV;
48 49
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index d5a102c71989..6e4eb7ff95a8 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -83,7 +83,9 @@ static int _init_omap_device(char *name, struct device **new_dev)
83static void omap2_init_processor_devices(void) 83static void omap2_init_processor_devices(void)
84{ 84{
85 _init_omap_device("mpu", &mpu_dev); 85 _init_omap_device("mpu", &mpu_dev);
86 _init_omap_device("iva", &iva_dev); 86 if (omap3_has_iva())
87 _init_omap_device("iva", &iva_dev);
88
87 if (cpu_is_omap44xx()) { 89 if (cpu_is_omap44xx()) {
88 _init_omap_device("l3_main_1", &l3_dev); 90 _init_omap_device("l3_main_1", &l3_dev);
89 _init_omap_device("dsp", &dsp_dev); 91 _init_omap_device("dsp", &dsp_dev);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 1c1b0ab5b978..f4a5f716422b 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void) {}
127#ifdef CONFIG_TWL4030_CORE 127#ifdef CONFIG_TWL4030_CORE
128extern int omap3_twl_init(void); 128extern int omap3_twl_init(void);
129extern int omap4_twl_init(void); 129extern int omap4_twl_init(void);
130extern int omap3_twl_set_sr_bit(bool enable);
130#else 131#else
131static inline int omap3_twl_init(void) 132static inline int omap3_twl_init(void)
132{ 133{
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 97feb3ab6a69..10f8747ba572 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -363,9 +363,6 @@ static const struct platform_suspend_ops __initdata omap_pm_ops;
363/* XXX This function should be shareable between OMAP2xxx and OMAP3 */ 363/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
364static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 364static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
365{ 365{
366 clkdm_clear_all_wkdeps(clkdm);
367 clkdm_clear_all_sleepdeps(clkdm);
368
369 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 366 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
370 omap2_clkdm_allow_idle(clkdm); 367 omap2_clkdm_allow_idle(clkdm);
371 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 368 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
@@ -411,10 +408,7 @@ static void __init prcm_setup_regs(void)
411 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); 408 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
412 omap2_clkdm_sleep(gfx_clkdm); 409 omap2_clkdm_sleep(gfx_clkdm);
413 410
414 /* 411 /* Enable hardware-supervised idle for all clkdms */
415 * Clear clockdomain wakeup dependencies and enable
416 * hardware-supervised idle for all clkdms
417 */
418 clkdm_for_each(clkdms_setup, NULL); 412 clkdm_for_each(clkdms_setup, NULL);
419 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); 413 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
420 414
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4b085d..1883a464aace 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -311,11 +311,6 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
311 return IRQ_HANDLED; 311 return IRQ_HANDLED;
312} 312}
313 313
314static void restore_control_register(u32 val)
315{
316 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
317}
318
319/* Function to restore the table entry that was modified for enabling MMU */ 314/* Function to restore the table entry that was modified for enabling MMU */
320static void restore_table_entry(void) 315static void restore_table_entry(void)
321{ 316{
@@ -337,7 +332,7 @@ static void restore_table_entry(void)
337 control_reg_value = __raw_readl(scratchpad_address 332 control_reg_value = __raw_readl(scratchpad_address
338 + OMAP343X_CONTROL_REG_VALUE_OFFSET); 333 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
339 /* This will enable caches and prediction */ 334 /* This will enable caches and prediction */
340 restore_control_register(control_reg_value); 335 set_cr(control_reg_value);
341} 336}
342 337
343void omap_sram_idle(void) 338void omap_sram_idle(void)
@@ -695,21 +690,6 @@ static void __init prcm_setup_regs(void)
695 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? 690 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
696 OMAP3630_GRPSEL_UART4_MASK : 0; 691 OMAP3630_GRPSEL_UART4_MASK : 0;
697 692
698
699 /* XXX Reset all wkdeps. This should be done when initializing
700 * powerdomains */
701 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
702 omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
703 omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
704 omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
705 omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
706 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
707 if (omap_rev() > OMAP3430_REV_ES1_0) {
708 omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
709 omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
710 } else
711 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
712
713 /* 693 /*
714 * Enable interface clock autoidle for all modules. 694 * Enable interface clock autoidle for all modules.
715 * Note that in the long run this should be done by clockfw 695 * Note that in the long run this should be done by clockfw
@@ -928,8 +908,7 @@ void omap3_pm_off_mode_enable(int enable)
928 pwrst->pwrdm == core_pwrdm && 908 pwrst->pwrdm == core_pwrdm &&
929 state == PWRDM_POWER_OFF) { 909 state == PWRDM_POWER_OFF) {
930 pwrst->next_state = PWRDM_POWER_RET; 910 pwrst->next_state = PWRDM_POWER_RET;
931 WARN_ONCE(1, 911 pr_warn("%s: Core OFF disabled due to errata i583\n",
932 "%s: Core OFF disabled due to errata i583\n",
933 __func__); 912 __func__);
934 } else { 913 } else {
935 pwrst->next_state = state; 914 pwrst->next_state = state;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 98d8232808b8..e60ac1f71bd4 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -64,6 +64,11 @@
64#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) 64#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
65#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 65#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
66 66
67/*
68 * This file needs be built unconditionally as ARM to interoperate correctly
69 * with non-Thumb-2-capable firmware.
70 */
71 .arm
67 72
68/* 73/*
69 * API functions 74 * API functions
@@ -82,6 +87,8 @@ ENTRY(get_restore_pointer)
82 stmfd sp!, {lr} @ save registers on stack 87 stmfd sp!, {lr} @ save registers on stack
83 adr r0, restore 88 adr r0, restore
84 ldmfd sp!, {pc} @ restore regs and return 89 ldmfd sp!, {pc} @ restore regs and return
90ENDPROC(get_restore_pointer)
91 .align
85ENTRY(get_restore_pointer_sz) 92ENTRY(get_restore_pointer_sz)
86 .word . - get_restore_pointer 93 .word . - get_restore_pointer
87 94
@@ -91,6 +98,8 @@ ENTRY(get_omap3630_restore_pointer)
91 stmfd sp!, {lr} @ save registers on stack 98 stmfd sp!, {lr} @ save registers on stack
92 adr r0, restore_3630 99 adr r0, restore_3630
93 ldmfd sp!, {pc} @ restore regs and return 100 ldmfd sp!, {pc} @ restore regs and return
101ENDPROC(get_omap3630_restore_pointer)
102 .align
94ENTRY(get_omap3630_restore_pointer_sz) 103ENTRY(get_omap3630_restore_pointer_sz)
95 .word . - get_omap3630_restore_pointer 104 .word . - get_omap3630_restore_pointer
96 105
@@ -100,6 +109,8 @@ ENTRY(get_es3_restore_pointer)
100 stmfd sp!, {lr} @ save registers on stack 109 stmfd sp!, {lr} @ save registers on stack
101 adr r0, restore_es3 110 adr r0, restore_es3
102 ldmfd sp!, {pc} @ restore regs and return 111 ldmfd sp!, {pc} @ restore regs and return
112ENDPROC(get_es3_restore_pointer)
113 .align
103ENTRY(get_es3_restore_pointer_sz) 114ENTRY(get_es3_restore_pointer_sz)
104 .word . - get_es3_restore_pointer 115 .word . - get_es3_restore_pointer
105 116
@@ -113,8 +124,10 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
113 stmfd sp!, {lr} @ save registers on stack 124 stmfd sp!, {lr} @ save registers on stack
114 /* Setup so that we will disable and enable l2 */ 125 /* Setup so that we will disable and enable l2 */
115 mov r1, #0x1 126 mov r1, #0x1
116 str r1, l2dis_3630 127 adrl r2, l2dis_3630 @ may be too distant for plain adr
128 str r1, [r2]
117 ldmfd sp!, {pc} @ restore regs and return 129 ldmfd sp!, {pc} @ restore regs and return
130ENDPROC(enable_omap3630_toggle_l2_on_restore)
118 131
119 .text 132 .text
120/* Function to call rom code to save secure ram context */ 133/* Function to call rom code to save secure ram context */
@@ -131,20 +144,22 @@ ENTRY(save_secure_ram_context)
131 mov r1, #0 @ set task id for ROM code in r1 144 mov r1, #0 @ set task id for ROM code in r1
132 mov r2, #4 @ set some flags in r2, r6 145 mov r2, #4 @ set some flags in r2, r6
133 mov r6, #0xff 146 mov r6, #0xff
134 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 147 dsb @ data write barrier
135 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 148 dmb @ data memory barrier
136 .word 0xE1600071 @ call SMI monitor (smi #1) 149 smc #1 @ call SMI monitor (smi #1)
137 nop 150 nop
138 nop 151 nop
139 nop 152 nop
140 nop 153 nop
141 ldmfd sp!, {r1-r12, pc} 154 ldmfd sp!, {r1-r12, pc}
155 .align
142sram_phy_addr_mask: 156sram_phy_addr_mask:
143 .word SRAM_BASE_P 157 .word SRAM_BASE_P
144high_mask: 158high_mask:
145 .word 0xffff 159 .word 0xffff
146api_params: 160api_params:
147 .word 0x4, 0x0, 0x0, 0x1, 0x1 161 .word 0x4, 0x0, 0x0, 0x1, 0x1
162ENDPROC(save_secure_ram_context)
148ENTRY(save_secure_ram_context_sz) 163ENTRY(save_secure_ram_context_sz)
149 .word . - save_secure_ram_context 164 .word . - save_secure_ram_context
150 165
@@ -173,12 +188,12 @@ ENTRY(omap34xx_cpu_suspend)
173 stmfd sp!, {r0-r12, lr} @ save registers on stack 188 stmfd sp!, {r0-r12, lr} @ save registers on stack
174 189
175 /* 190 /*
176 * r0 contains restore pointer in sdram 191 * r0 contains CPU context save/restore pointer in sdram
177 * r1 contains information about saving context: 192 * r1 contains information about saving context:
178 * 0 - No context lost 193 * 0 - No context lost
179 * 1 - Only L1 and logic lost 194 * 1 - Only L1 and logic lost
180 * 2 - Only L2 lost 195 * 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
181 * 3 - Both L1 and L2 lost 196 * 3 - Both L1 and L2 lost and logic lost
182 */ 197 */
183 198
184 /* Directly jump to WFI is the context save is not required */ 199 /* Directly jump to WFI is the context save is not required */
@@ -199,89 +214,74 @@ save_context_wfi:
199 beq clean_caches 214 beq clean_caches
200 215
201l1_logic_lost: 216l1_logic_lost:
202 /* Store sp and spsr to SDRAM */ 217 mov r4, sp @ Store sp
203 mov r4, sp 218 mrs r5, spsr @ Store spsr
204 mrs r5, spsr 219 mov r6, lr @ Store lr
205 mov r6, lr
206 stmia r8!, {r4-r6} 220 stmia r8!, {r4-r6}
207 /* Save all ARM registers */ 221
208 /* Coprocessor access control register */ 222 mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
209 mrc p15, 0, r6, c1, c0, 2 223 mrc p15, 0, r5, c2, c0, 0 @ TTBR0
210 stmia r8!, {r6} 224 mrc p15, 0, r6, c2, c0, 1 @ TTBR1
211 /* TTBR0, TTBR1 and Translation table base control */ 225 mrc p15, 0, r7, c2, c0, 2 @ TTBCR
212 mrc p15, 0, r4, c2, c0, 0
213 mrc p15, 0, r5, c2, c0, 1
214 mrc p15, 0, r6, c2, c0, 2
215 stmia r8!, {r4-r6}
216 /*
217 * Domain access control register, data fault status register,
218 * and instruction fault status register
219 */
220 mrc p15, 0, r4, c3, c0, 0
221 mrc p15, 0, r5, c5, c0, 0
222 mrc p15, 0, r6, c5, c0, 1
223 stmia r8!, {r4-r6}
224 /*
225 * Data aux fault status register, instruction aux fault status,
226 * data fault address register and instruction fault address register
227 */
228 mrc p15, 0, r4, c5, c1, 0
229 mrc p15, 0, r5, c5, c1, 1
230 mrc p15, 0, r6, c6, c0, 0
231 mrc p15, 0, r7, c6, c0, 2
232 stmia r8!, {r4-r7}
233 /*
234 * user r/w thread and process ID, user r/o thread and process ID,
235 * priv only thread and process ID, cache size selection
236 */
237 mrc p15, 0, r4, c13, c0, 2
238 mrc p15, 0, r5, c13, c0, 3
239 mrc p15, 0, r6, c13, c0, 4
240 mrc p15, 2, r7, c0, c0, 0
241 stmia r8!, {r4-r7} 226 stmia r8!, {r4-r7}
242 /* Data TLB lockdown, instruction TLB lockdown registers */
243 mrc p15, 0, r5, c10, c0, 0
244 mrc p15, 0, r6, c10, c0, 1
245 stmia r8!, {r5-r6}
246 /* Secure or non secure vector base address, FCSE PID, Context PID*/
247 mrc p15, 0, r4, c12, c0, 0
248 mrc p15, 0, r5, c13, c0, 0
249 mrc p15, 0, r6, c13, c0, 1
250 stmia r8!, {r4-r6}
251 /* Primary remap, normal remap registers */
252 mrc p15, 0, r4, c10, c2, 0
253 mrc p15, 0, r5, c10, c2, 1
254 stmia r8!,{r4-r5}
255 227
256 /* Store current cpsr*/ 228 mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
257 mrs r2, cpsr 229 mrc p15, 0, r5, c10, c2, 0 @ PRRR
258 stmia r8!, {r2} 230 mrc p15, 0, r6, c10, c2, 1 @ NMRR
231 stmia r8!,{r4-r6}
259 232
260 mrc p15, 0, r4, c1, c0, 0 233 mrc p15, 0, r4, c13, c0, 1 @ Context ID
261 /* save control register */ 234 mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
235 mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
236 mrs r7, cpsr @ Store current cpsr
237 stmia r8!, {r4-r7}
238
239 mrc p15, 0, r4, c1, c0, 0 @ save control register
262 stmia r8!, {r4} 240 stmia r8!, {r4}
263 241
264clean_caches: 242clean_caches:
265 /* 243 /*
266 * Clean Data or unified cache to POU
267 * How to invalidate only L1 cache???? - #FIX_ME#
268 * mcr p15, 0, r11, c7, c11, 1
269 */
270 cmp r1, #0x1 @ Check whether L2 inval is required
271 beq omap3_do_wfi
272
273clean_l2:
274 /*
275 * jump out to kernel flush routine 244 * jump out to kernel flush routine
276 * - reuse that code is better 245 * - reuse that code is better
277 * - it executes in a cached space so is faster than refetch per-block 246 * - it executes in a cached space so is faster than refetch per-block
278 * - should be faster and will change with kernel 247 * - should be faster and will change with kernel
279 * - 'might' have to copy address, load and jump to it 248 * - 'might' have to copy address, load and jump to it
249 * Flush all data from the L1 data cache before disabling
250 * SCTLR.C bit.
280 */ 251 */
281 ldr r1, kernel_flush 252 ldr r1, kernel_flush
282 mov lr, pc 253 mov lr, pc
283 bx r1 254 bx r1
284 255
256 /*
257 * Clear the SCTLR.C bit to prevent further data cache
258 * allocation. Clearing SCTLR.C would make all the data accesses
259 * strongly ordered and would not hit the cache.
260 */
261 mrc p15, 0, r0, c1, c0, 0
262 bic r0, r0, #(1 << 2) @ Disable the C bit
263 mcr p15, 0, r0, c1, c0, 0
264 isb
265
266 /*
267 * Invalidate L1 data cache. Even though only invalidate is
268 * necessary exported flush API is used here. Doing clean
269 * on already clean cache would be almost NOP.
270 */
271 ldr r1, kernel_flush
272 blx r1
273 /*
274 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
275 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
276 * This sequence switches back to ARM. Note that .align may insert a
277 * nop: bx pc needs to be word-aligned in order to work.
278 */
279 THUMB( .thumb )
280 THUMB( .align )
281 THUMB( bx pc )
282 THUMB( nop )
283 .arm
284
285omap3_do_wfi: 285omap3_do_wfi:
286 ldr r4, sdrc_power @ read the SDRC_POWER register 286 ldr r4, sdrc_power @ read the SDRC_POWER register
287 ldr r5, [r4] @ read the contents of SDRC_POWER 287 ldr r5, [r4] @ read the contents of SDRC_POWER
@@ -289,9 +289,8 @@ omap3_do_wfi:
289 str r5, [r4] @ write back to SDRC_POWER register 289 str r5, [r4] @ write back to SDRC_POWER register
290 290
291 /* Data memory barrier and Data sync barrier */ 291 /* Data memory barrier and Data sync barrier */
292 mov r1, #0 292 dsb
293 mcr p15, 0, r1, c7, c10, 4 293 dmb
294 mcr p15, 0, r1, c7, c10, 5
295 294
296/* 295/*
297 * =================================== 296 * ===================================
@@ -317,6 +316,12 @@ omap3_do_wfi:
317 nop 316 nop
318 bl wait_sdrc_ok 317 bl wait_sdrc_ok
319 318
319 mrc p15, 0, r0, c1, c0, 0
320 tst r0, #(1 << 2) @ Check C bit enabled?
321 orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
322 mcreq p15, 0, r0, c1, c0, 0
323 isb
324
320/* 325/*
321 * =================================== 326 * ===================================
322 * == Exit point from non-OFF modes == 327 * == Exit point from non-OFF modes ==
@@ -406,9 +411,9 @@ skipl2dis:
406 mov r2, #4 @ set some flags in r2, r6 411 mov r2, #4 @ set some flags in r2, r6
407 mov r6, #0xff 412 mov r6, #0xff
408 adr r3, l2_inv_api_params @ r3 points to dummy parameters 413 adr r3, l2_inv_api_params @ r3 points to dummy parameters
409 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 414 dsb @ data write barrier
410 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 415 dmb @ data memory barrier
411 .word 0xE1600071 @ call SMI monitor (smi #1) 416 smc #1 @ call SMI monitor (smi #1)
412 /* Write to Aux control register to set some bits */ 417 /* Write to Aux control register to set some bits */
413 mov r0, #42 @ set service ID for PPA 418 mov r0, #42 @ set service ID for PPA
414 mov r12, r0 @ copy secure Service ID in r12 419 mov r12, r0 @ copy secure Service ID in r12
@@ -417,9 +422,9 @@ skipl2dis:
417 mov r6, #0xff 422 mov r6, #0xff
418 ldr r4, scratchpad_base 423 ldr r4, scratchpad_base
419 ldr r3, [r4, #0xBC] @ r3 points to parameters 424 ldr r3, [r4, #0xBC] @ r3 points to parameters
420 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 425 dsb @ data write barrier
421 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 426 dmb @ data memory barrier
422 .word 0xE1600071 @ call SMI monitor (smi #1) 427 smc #1 @ call SMI monitor (smi #1)
423 428
424#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 429#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
425 /* Restore L2 aux control register */ 430 /* Restore L2 aux control register */
@@ -432,29 +437,30 @@ skipl2dis:
432 ldr r4, scratchpad_base 437 ldr r4, scratchpad_base
433 ldr r3, [r4, #0xBC] 438 ldr r3, [r4, #0xBC]
434 adds r3, r3, #8 @ r3 points to parameters 439 adds r3, r3, #8 @ r3 points to parameters
435 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 440 dsb @ data write barrier
436 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 441 dmb @ data memory barrier
437 .word 0xE1600071 @ call SMI monitor (smi #1) 442 smc #1 @ call SMI monitor (smi #1)
438#endif 443#endif
439 b logic_l1_restore 444 b logic_l1_restore
440 445
446 .align
441l2_inv_api_params: 447l2_inv_api_params:
442 .word 0x1, 0x00 448 .word 0x1, 0x00
443l2_inv_gp: 449l2_inv_gp:
444 /* Execute smi to invalidate L2 cache */ 450 /* Execute smi to invalidate L2 cache */
445 mov r12, #0x1 @ set up to invalidate L2 451 mov r12, #0x1 @ set up to invalidate L2
446 .word 0xE1600070 @ Call SMI monitor (smieq) 452 smc #0 @ Call SMI monitor (smieq)
447 /* Write to Aux control register to set some bits */ 453 /* Write to Aux control register to set some bits */
448 ldr r4, scratchpad_base 454 ldr r4, scratchpad_base
449 ldr r3, [r4,#0xBC] 455 ldr r3, [r4,#0xBC]
450 ldr r0, [r3,#4] 456 ldr r0, [r3,#4]
451 mov r12, #0x3 457 mov r12, #0x3
452 .word 0xE1600070 @ Call SMI monitor (smieq) 458 smc #0 @ Call SMI monitor (smieq)
453 ldr r4, scratchpad_base 459 ldr r4, scratchpad_base
454 ldr r3, [r4,#0xBC] 460 ldr r3, [r4,#0xBC]
455 ldr r0, [r3,#12] 461 ldr r0, [r3,#12]
456 mov r12, #0x2 462 mov r12, #0x2
457 .word 0xE1600070 @ Call SMI monitor (smieq) 463 smc #0 @ Call SMI monitor (smieq)
458logic_l1_restore: 464logic_l1_restore:
459 ldr r1, l2dis_3630 465 ldr r1, l2dis_3630
460 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 466 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
@@ -473,68 +479,29 @@ skipl2reen:
473 ldr r4, scratchpad_base 479 ldr r4, scratchpad_base
474 ldr r3, [r4,#0xBC] 480 ldr r3, [r4,#0xBC]
475 adds r3, r3, #16 481 adds r3, r3, #16
482
476 ldmia r3!, {r4-r6} 483 ldmia r3!, {r4-r6}
477 mov sp, r4 484 mov sp, r4 @ Restore sp
478 msr spsr_cxsf, r5 485 msr spsr_cxsf, r5 @ Restore spsr
479 mov lr, r6 486 mov lr, r6 @ Restore lr
480 487
481 ldmia r3!, {r4-r9} 488 ldmia r3!, {r4-r7}
482 /* Coprocessor access Control Register */ 489 mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
483 mcr p15, 0, r4, c1, c0, 2 490 mcr p15, 0, r5, c2, c0, 0 @ TTBR0
484 491 mcr p15, 0, r6, c2, c0, 1 @ TTBR1
485 /* TTBR0 */ 492 mcr p15, 0, r7, c2, c0, 2 @ TTBCR
486 MCR p15, 0, r5, c2, c0, 0 493
487 /* TTBR1 */ 494 ldmia r3!,{r4-r6}
488 MCR p15, 0, r6, c2, c0, 1 495 mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
489 /* Translation table base control register */ 496 mcr p15, 0, r5, c10, c2, 0 @ PRRR
490 MCR p15, 0, r7, c2, c0, 2 497 mcr p15, 0, r6, c10, c2, 1 @ NMRR
491 /* Domain access Control Register */ 498
492 MCR p15, 0, r8, c3, c0, 0
493 /* Data fault status Register */
494 MCR p15, 0, r9, c5, c0, 0
495
496 ldmia r3!,{r4-r8}
497 /* Instruction fault status Register */
498 MCR p15, 0, r4, c5, c0, 1
499 /* Data Auxiliary Fault Status Register */
500 MCR p15, 0, r5, c5, c1, 0
501 /* Instruction Auxiliary Fault Status Register*/
502 MCR p15, 0, r6, c5, c1, 1
503 /* Data Fault Address Register */
504 MCR p15, 0, r7, c6, c0, 0
505 /* Instruction Fault Address Register*/
506 MCR p15, 0, r8, c6, c0, 2
507 ldmia r3!,{r4-r7}
508 499
509 /* User r/w thread and process ID */ 500 ldmia r3!,{r4-r7}
510 MCR p15, 0, r4, c13, c0, 2 501 mcr p15, 0, r4, c13, c0, 1 @ Context ID
511 /* User ro thread and process ID */ 502 mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
512 MCR p15, 0, r5, c13, c0, 3 503 mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
513 /* Privileged only thread and process ID */ 504 msr cpsr, r7 @ store cpsr
514 MCR p15, 0, r6, c13, c0, 4
515 /* Cache size selection */
516 MCR p15, 2, r7, c0, c0, 0
517 ldmia r3!,{r4-r8}
518 /* Data TLB lockdown registers */
519 MCR p15, 0, r4, c10, c0, 0
520 /* Instruction TLB lockdown registers */
521 MCR p15, 0, r5, c10, c0, 1
522 /* Secure or Nonsecure Vector Base Address */
523 MCR p15, 0, r6, c12, c0, 0
524 /* FCSE PID */
525 MCR p15, 0, r7, c13, c0, 0
526 /* Context PID */
527 MCR p15, 0, r8, c13, c0, 1
528
529 ldmia r3!,{r4-r5}
530 /* Primary memory remap register */
531 MCR p15, 0, r4, c10, c2, 0
532 /* Normal memory remap register */
533 MCR p15, 0, r5, c10, c2, 1
534
535 /* Restore cpsr */
536 ldmia r3!,{r4} @ load CPSR from SDRAM
537 msr cpsr, r4 @ store cpsr
538 505
539 /* Enabling MMU here */ 506 /* Enabling MMU here */
540 mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl 507 mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
@@ -592,12 +559,17 @@ usettbr0:
592 ldr r2, cache_pred_disable_mask 559 ldr r2, cache_pred_disable_mask
593 and r4, r2 560 and r4, r2
594 mcr p15, 0, r4, c1, c0, 0 561 mcr p15, 0, r4, c1, c0, 0
562 dsb
563 isb
564 ldr r0, =restoremmu_on
565 bx r0
595 566
596/* 567/*
597 * ============================== 568 * ==============================
598 * == Exit point from OFF mode == 569 * == Exit point from OFF mode ==
599 * ============================== 570 * ==============================
600 */ 571 */
572restoremmu_on:
601 ldmfd sp!, {r0-r12, pc} @ restore regs and return 573 ldmfd sp!, {r0-r12, pc} @ restore regs and return
602 574
603 575
@@ -607,6 +579,7 @@ usettbr0:
607 579
608/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */ 580/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
609 .text 581 .text
582 .align 3
610ENTRY(es3_sdrc_fix) 583ENTRY(es3_sdrc_fix)
611 ldr r4, sdrc_syscfg @ get config addr 584 ldr r4, sdrc_syscfg @ get config addr
612 ldr r5, [r4] @ get value 585 ldr r5, [r4] @ get value
@@ -634,6 +607,7 @@ ENTRY(es3_sdrc_fix)
634 str r5, [r4] @ kick off refreshes 607 str r5, [r4] @ kick off refreshes
635 bx lr 608 bx lr
636 609
610 .align
637sdrc_syscfg: 611sdrc_syscfg:
638 .word SDRC_SYSCONFIG_P 612 .word SDRC_SYSCONFIG_P
639sdrc_mr_0: 613sdrc_mr_0:
@@ -648,6 +622,7 @@ sdrc_emr2_1:
648 .word SDRC_EMR2_1_P 622 .word SDRC_EMR2_1_P
649sdrc_manual_1: 623sdrc_manual_1:
650 .word SDRC_MANUAL_1_P 624 .word SDRC_MANUAL_1_P
625ENDPROC(es3_sdrc_fix)
651ENTRY(es3_sdrc_fix_sz) 626ENTRY(es3_sdrc_fix_sz)
652 .word . - es3_sdrc_fix 627 .word . - es3_sdrc_fix
653 628
@@ -682,6 +657,12 @@ wait_sdrc_ready:
682 bic r5, r5, #0x40 657 bic r5, r5, #0x40
683 str r5, [r4] 658 str r5, [r4]
684 659
660/*
661 * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
662 * base instead.
663 * Be careful not to clobber r7 when maintaing this code.
664 */
665
685is_dll_in_lock_mode: 666is_dll_in_lock_mode:
686 /* Is dll in lock mode? */ 667 /* Is dll in lock mode? */
687 ldr r4, sdrc_dlla_ctrl 668 ldr r4, sdrc_dlla_ctrl
@@ -689,10 +670,11 @@ is_dll_in_lock_mode:
689 tst r5, #0x4 670 tst r5, #0x4
690 bxne lr @ Return if locked 671 bxne lr @ Return if locked
691 /* wait till dll locks */ 672 /* wait till dll locks */
673 adr r7, kick_counter
692wait_dll_lock_timed: 674wait_dll_lock_timed:
693 ldr r4, wait_dll_lock_counter 675 ldr r4, wait_dll_lock_counter
694 add r4, r4, #1 676 add r4, r4, #1
695 str r4, wait_dll_lock_counter 677 str r4, [r7, #wait_dll_lock_counter - kick_counter]
696 ldr r4, sdrc_dlla_status 678 ldr r4, sdrc_dlla_status
697 /* Wait 20uS for lock */ 679 /* Wait 20uS for lock */
698 mov r6, #8 680 mov r6, #8
@@ -718,9 +700,10 @@ kick_dll:
718 dsb 700 dsb
719 ldr r4, kick_counter 701 ldr r4, kick_counter
720 add r4, r4, #1 702 add r4, r4, #1
721 str r4, kick_counter 703 str r4, [r7] @ kick_counter
722 b wait_dll_lock_timed 704 b wait_dll_lock_timed
723 705
706 .align
724cm_idlest1_core: 707cm_idlest1_core:
725 .word CM_IDLEST1_CORE_V 708 .word CM_IDLEST1_CORE_V
726cm_idlest_ckgen: 709cm_idlest_ckgen:
@@ -763,6 +746,7 @@ kick_counter:
763 .word 0 746 .word 0
764wait_dll_lock_counter: 747wait_dll_lock_counter:
765 .word 0 748 .word 0
749ENDPROC(omap34xx_cpu_suspend)
766 750
767ENTRY(omap34xx_cpu_suspend_sz) 751ENTRY(omap34xx_cpu_suspend_sz)
768 .word . - omap34xx_cpu_suspend 752 .word . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 95ac336fe3f7..0ab4dd5081ee 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -54,6 +54,7 @@ struct omap_sr {
54 struct list_head node; 54 struct list_head node;
55 struct omap_sr_nvalue_table *nvalue_table; 55 struct omap_sr_nvalue_table *nvalue_table;
56 struct voltagedomain *voltdm; 56 struct voltagedomain *voltdm;
57 struct dentry *dbg_dir;
57}; 58};
58 59
59/* sr_list contains all the instances of smartreflex module */ 60/* sr_list contains all the instances of smartreflex module */
@@ -260,9 +261,11 @@ static int sr_late_init(struct omap_sr *sr_info)
260 if (sr_class->class_type == SR_CLASS2 && 261 if (sr_class->class_type == SR_CLASS2 &&
261 sr_class->notify_flags && sr_info->irq) { 262 sr_class->notify_flags && sr_info->irq) {
262 263
263 name = kzalloc(SMARTREFLEX_NAME_LEN + 1, GFP_KERNEL); 264 name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
264 strcpy(name, "sr_"); 265 if (name == NULL) {
265 strcat(name, sr_info->voltdm->name); 266 ret = -ENOMEM;
267 goto error;
268 }
266 ret = request_irq(sr_info->irq, sr_interrupt, 269 ret = request_irq(sr_info->irq, sr_interrupt,
267 0, name, (void *)sr_info); 270 0, name, (void *)sr_info);
268 if (ret) 271 if (ret)
@@ -282,6 +285,7 @@ error:
282 dev_err(&sr_info->pdev->dev, "%s: ERROR in registering" 285 dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
283 "interrupt handler. Smartreflex will" 286 "interrupt handler. Smartreflex will"
284 "not function as desired\n", __func__); 287 "not function as desired\n", __func__);
288 kfree(name);
285 kfree(sr_info); 289 kfree(sr_info);
286 return ret; 290 return ret;
287} 291}
@@ -820,7 +824,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
820 struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL); 824 struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
821 struct omap_sr_data *pdata = pdev->dev.platform_data; 825 struct omap_sr_data *pdata = pdev->dev.platform_data;
822 struct resource *mem, *irq; 826 struct resource *mem, *irq;
823 struct dentry *vdd_dbg_dir, *dbg_dir, *nvalue_dir; 827 struct dentry *vdd_dbg_dir, *nvalue_dir;
824 struct omap_volt_data *volt_data; 828 struct omap_volt_data *volt_data;
825 int i, ret = 0; 829 int i, ret = 0;
826 830
@@ -879,7 +883,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
879 ret = sr_late_init(sr_info); 883 ret = sr_late_init(sr_info);
880 if (ret) { 884 if (ret) {
881 pr_warning("%s: Error in SR late init\n", __func__); 885 pr_warning("%s: Error in SR late init\n", __func__);
882 return ret; 886 goto err_release_region;
883 } 887 }
884 } 888 }
885 889
@@ -890,30 +894,34 @@ static int __init omap_sr_probe(struct platform_device *pdev)
890 * not try to create rest of the debugfs entries. 894 * not try to create rest of the debugfs entries.
891 */ 895 */
892 vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm); 896 vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
893 if (!vdd_dbg_dir) 897 if (!vdd_dbg_dir) {
894 return -EINVAL; 898 ret = -EINVAL;
899 goto err_release_region;
900 }
895 901
896 dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir); 902 sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
897 if (IS_ERR(dbg_dir)) { 903 if (IS_ERR(sr_info->dbg_dir)) {
898 dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n", 904 dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
899 __func__); 905 __func__);
900 return PTR_ERR(dbg_dir); 906 ret = PTR_ERR(sr_info->dbg_dir);
907 goto err_release_region;
901 } 908 }
902 909
903 (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir, 910 (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
904 (void *)sr_info, &pm_sr_fops); 911 sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
905 (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir, 912 (void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
906 &sr_info->err_weight); 913 &sr_info->err_weight);
907 (void) debugfs_create_x32("errmaxlimit", S_IRUGO, dbg_dir, 914 (void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
908 &sr_info->err_maxlimit); 915 &sr_info->err_maxlimit);
909 (void) debugfs_create_x32("errminlimit", S_IRUGO, dbg_dir, 916 (void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
910 &sr_info->err_minlimit); 917 &sr_info->err_minlimit);
911 918
912 nvalue_dir = debugfs_create_dir("nvalue", dbg_dir); 919 nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
913 if (IS_ERR(nvalue_dir)) { 920 if (IS_ERR(nvalue_dir)) {
914 dev_err(&pdev->dev, "%s: Unable to create debugfs directory" 921 dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
915 "for n-values\n", __func__); 922 "for n-values\n", __func__);
916 return PTR_ERR(nvalue_dir); 923 ret = PTR_ERR(nvalue_dir);
924 goto err_release_region;
917 } 925 }
918 926
919 omap_voltage_get_volttable(sr_info->voltdm, &volt_data); 927 omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
@@ -922,23 +930,15 @@ static int __init omap_sr_probe(struct platform_device *pdev)
922 " corresponding vdd vdd_%s. Cannot create debugfs" 930 " corresponding vdd vdd_%s. Cannot create debugfs"
923 "entries for n-values\n", 931 "entries for n-values\n",
924 __func__, sr_info->voltdm->name); 932 __func__, sr_info->voltdm->name);
925 return -ENODATA; 933 ret = -ENODATA;
934 goto err_release_region;
926 } 935 }
927 936
928 for (i = 0; i < sr_info->nvalue_count; i++) { 937 for (i = 0; i < sr_info->nvalue_count; i++) {
929 char *name; 938 char name[NVALUE_NAME_LEN + 1];
930 char volt_name[32];
931
932 name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL);
933 if (!name) {
934 dev_err(&pdev->dev, "%s: Unable to allocate memory"
935 " for n-value directory name\n", __func__);
936 return -ENOMEM;
937 }
938 939
939 strcpy(name, "volt_"); 940 snprintf(name, sizeof(name), "volt_%d",
940 sprintf(volt_name, "%d", volt_data[i].volt_nominal); 941 volt_data[i].volt_nominal);
941 strcat(name, volt_name);
942 (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir, 942 (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
943 &(sr_info->nvalue_table[i].nvalue)); 943 &(sr_info->nvalue_table[i].nvalue));
944 } 944 }
@@ -973,6 +973,8 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
973 973
974 if (sr_info->autocomp_active) 974 if (sr_info->autocomp_active)
975 sr_stop_vddautocomp(sr_info); 975 sr_stop_vddautocomp(sr_info);
976 if (sr_info->dbg_dir)
977 debugfs_remove_recursive(sr_info->dbg_dir);
976 978
977 list_del(&sr_info->node); 979 list_del(&sr_info->node);
978 iounmap(sr_info->base); 980 iounmap(sr_info->base);
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 7f893a29d500..1078bfbc25c7 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -34,6 +34,12 @@
34#include "sdrc.h" 34#include "sdrc.h"
35#include "cm2xxx_3xxx.h" 35#include "cm2xxx_3xxx.h"
36 36
37/*
38 * This file needs be built unconditionally as ARM to interoperate correctly
39 * with non-Thumb-2-capable firmware.
40 */
41 .arm
42
37 .text 43 .text
38 44
39/* r1 parameters */ 45/* r1 parameters */
@@ -116,24 +122,36 @@ ENTRY(omap3_sram_configure_core_dpll)
116 122
117 @ pull the extra args off the stack 123 @ pull the extra args off the stack
118 @ and store them in SRAM 124 @ and store them in SRAM
125
126/*
127 * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
128 * in Thumb-2: use a r7 as a base instead.
129 * Be careful not to clobber r7 when maintaing this file.
130 */
131 THUMB( adr r7, omap3_sram_configure_core_dpll )
132 .macro strtext Rt:req, label:req
133 ARM( str \Rt, \label )
134 THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] )
135 .endm
136
119 ldr r4, [sp, #52] 137 ldr r4, [sp, #52]
120 str r4, omap_sdrc_rfr_ctrl_0_val 138 strtext r4, omap_sdrc_rfr_ctrl_0_val
121 ldr r4, [sp, #56] 139 ldr r4, [sp, #56]
122 str r4, omap_sdrc_actim_ctrl_a_0_val 140 strtext r4, omap_sdrc_actim_ctrl_a_0_val
123 ldr r4, [sp, #60] 141 ldr r4, [sp, #60]
124 str r4, omap_sdrc_actim_ctrl_b_0_val 142 strtext r4, omap_sdrc_actim_ctrl_b_0_val
125 ldr r4, [sp, #64] 143 ldr r4, [sp, #64]
126 str r4, omap_sdrc_mr_0_val 144 strtext r4, omap_sdrc_mr_0_val
127 ldr r4, [sp, #68] 145 ldr r4, [sp, #68]
128 str r4, omap_sdrc_rfr_ctrl_1_val 146 strtext r4, omap_sdrc_rfr_ctrl_1_val
129 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0, 147 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
130 beq skip_cs1_params @ do not use cs1 params 148 beq skip_cs1_params @ do not use cs1 params
131 ldr r4, [sp, #72] 149 ldr r4, [sp, #72]
132 str r4, omap_sdrc_actim_ctrl_a_1_val 150 strtext r4, omap_sdrc_actim_ctrl_a_1_val
133 ldr r4, [sp, #76] 151 ldr r4, [sp, #76]
134 str r4, omap_sdrc_actim_ctrl_b_1_val 152 strtext r4, omap_sdrc_actim_ctrl_b_1_val
135 ldr r4, [sp, #80] 153 ldr r4, [sp, #80]
136 str r4, omap_sdrc_mr_1_val 154 strtext r4, omap_sdrc_mr_1_val
137skip_cs1_params: 155skip_cs1_params:
138 mrc p15, 0, r8, c1, c0, 0 @ read ctrl register 156 mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
139 bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction 157 bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
@@ -271,6 +289,7 @@ skip_cs1_prog:
271 ldr r12, [r11] @ posted-write barrier for SDRC 289 ldr r12, [r11] @ posted-write barrier for SDRC
272 bx lr 290 bx lr
273 291
292 .align
274omap3_sdrc_power: 293omap3_sdrc_power:
275 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) 294 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
276omap3_cm_clksel1_pll: 295omap3_cm_clksel1_pll:
@@ -319,6 +338,7 @@ omap3_sdrc_dlla_ctrl:
319 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) 338 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
320core_m2_mask_val: 339core_m2_mask_val:
321 .word 0x07FFFFFF 340 .word 0x07FFFFFF
341ENDPROC(omap3_sram_configure_core_dpll)
322 342
323ENTRY(omap3_sram_configure_core_dpll_sz) 343ENTRY(omap3_sram_configure_core_dpll_sz)
324 .word . - omap3_sram_configure_core_dpll 344 .word . - omap3_sram_configure_core_dpll
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 21:37:15 -0500