aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/board-apollon.c4
-rw-r--r--arch/arm/mach-omap2/board-h4.c6
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_apll.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c10
-rw-r--r--arch/arm/mach-omap2/clkt34xx_dpll3m2.c20
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c86
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c26
-rw-r--r--arch/arm/mach-omap2/clock.c9
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c24
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c23
-rw-r--r--arch/arm/mach-omap2/clock33xx_data.c1
-rw-r--r--arch/arm/mach-omap2/clock3xxx.c8
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c37
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c21
-rw-r--r--arch/arm/mach-omap2/cm-regbits-33xx.h158
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h411
-rw-r--r--arch/arm/mach-omap2/control.h1
-rw-r--r--arch/arm/mach-omap2/display.c4
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c48
-rw-r--r--arch/arm/mach-omap2/gpmc.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c45
-rw-r--r--arch/arm/mach-omap2/pm.c2
23 files changed, 755 insertions, 195 deletions
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 3e2d76f05af4..cea3abace815 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -202,7 +202,7 @@ static inline void __init apollon_init_smc91x(void)
202 return; 202 return;
203 } 203 }
204 204
205 clk_enable(gpmc_fck); 205 clk_prepare_enable(gpmc_fck);
206 rate = clk_get_rate(gpmc_fck); 206 rate = clk_get_rate(gpmc_fck);
207 207
208 eth_cs = APOLLON_ETH_CS; 208 eth_cs = APOLLON_ETH_CS;
@@ -246,7 +246,7 @@ static inline void __init apollon_init_smc91x(void)
246 gpmc_cs_free(APOLLON_ETH_CS); 246 gpmc_cs_free(APOLLON_ETH_CS);
247 } 247 }
248out: 248out:
249 clk_disable(gpmc_fck); 249 clk_disable_unprepare(gpmc_fck);
250 clk_put(gpmc_fck); 250 clk_put(gpmc_fck);
251} 251}
252 252
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 12569cb0eddd..313b3f426a56 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -265,9 +265,9 @@ static inline void __init h4_init_debug(void)
265 return; 265 return;
266 } 266 }
267 267
268 clk_enable(gpmc_fck); 268 clk_prepare_enable(gpmc_fck);
269 rate = clk_get_rate(gpmc_fck); 269 rate = clk_get_rate(gpmc_fck);
270 clk_disable(gpmc_fck); 270 clk_disable_unprepare(gpmc_fck);
271 clk_put(gpmc_fck); 271 clk_put(gpmc_fck);
272 272
273 if (is_gpmc_muxed()) 273 if (is_gpmc_muxed())
@@ -311,7 +311,7 @@ static inline void __init h4_init_debug(void)
311 gpmc_cs_free(eth_cs); 311 gpmc_cs_free(eth_cs);
312 312
313out: 313out:
314 clk_disable(gpmc_fck); 314 clk_disable_unprepare(gpmc_fck);
315 clk_put(gpmc_fck); 315 clk_put(gpmc_fck);
316} 316}
317 317
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 45fe2d3f59b1..8ae2c599dd7f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -171,7 +171,7 @@ static void __init omap4_ehci_init(void)
171 return; 171 return;
172 } 172 }
173 clk_set_rate(phy_ref_clk, 19200000); 173 clk_set_rate(phy_ref_clk, 19200000);
174 clk_enable(phy_ref_clk); 174 clk_prepare_enable(phy_ref_clk);
175 175
176 /* disable the power to the usb hub prior to init and reset phy+hub */ 176 /* disable the power to the usb hub prior to init and reset phy+hub */
177 ret = gpio_request_array(panda_ehci_gpios, 177 ret = gpio_request_array(panda_ehci_gpios,
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7234ae..c2d15212d64d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
59 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); 59 omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
60 60
61 omap2_cm_wait_idlest(cm_idlest_pll, status_mask, 61 omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
62 OMAP24XX_CM_IDLEST_VAL, clk->name); 62 OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
63 63
64 /* 64 /*
65 * REVISIT: Should we return an error code if omap2_wait_clock_ready() 65 * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index cabcfdba5246..3524f0e7b6d5 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
68long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) 68long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
69{ 69{
70 const struct prcm_config *ptr; 70 const struct prcm_config *ptr;
71 long highest_rate; 71 long highest_rate, sys_clk_rate;
72 72
73 highest_rate = -EINVAL; 73 highest_rate = -EINVAL;
74 sys_clk_rate = __clk_get_rate(sclk);
74 75
75 for (ptr = rate_table; ptr->mpu_speed; ptr++) { 76 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
76 if (!(ptr->flags & cpu_mask)) 77 if (!(ptr->flags & cpu_mask))
77 continue; 78 continue;
78 if (ptr->xtal_speed != sclk->rate) 79 if (ptr->xtal_speed != sys_clk_rate)
79 continue; 80 continue;
80 81
81 highest_rate = ptr->mpu_speed; 82 highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
94 const struct prcm_config *prcm; 95 const struct prcm_config *prcm;
95 unsigned long found_speed = 0; 96 unsigned long found_speed = 0;
96 unsigned long flags; 97 unsigned long flags;
98 long sys_clk_rate;
99
100 sys_clk_rate = __clk_get_rate(sclk);
97 101
98 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 102 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
99 if (!(prcm->flags & cpu_mask)) 103 if (!(prcm->flags & cpu_mask))
100 continue; 104 continue;
101 105
102 if (prcm->xtal_speed != sclk->rate) 106 if (prcm->xtal_speed != sys_clk_rate)
103 continue; 107 continue;
104 108
105 if (prcm->mpu_speed <= rate) { 109 if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 298887b5bf66..7c6da2f731dc 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
56 struct omap_sdrc_params *sdrc_cs0; 56 struct omap_sdrc_params *sdrc_cs0;
57 struct omap_sdrc_params *sdrc_cs1; 57 struct omap_sdrc_params *sdrc_cs1;
58 int ret; 58 int ret;
59 unsigned long clkrate;
59 60
60 if (!clk || !rate) 61 if (!clk || !rate)
61 return -EINVAL; 62 return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
64 if (validrate != rate) 65 if (validrate != rate)
65 return -EINVAL; 66 return -EINVAL;
66 67
67 sdrcrate = sdrc_ick_p->rate; 68 sdrcrate = __clk_get_rate(sdrc_ick_p);
68 if (rate > clk->rate) 69 clkrate = __clk_get_rate(clk);
69 sdrcrate <<= ((rate / clk->rate) >> 1); 70 if (rate > clkrate)
71 sdrcrate <<= ((rate / clkrate) >> 1);
70 else 72 else
71 sdrcrate >>= ((clk->rate / rate) >> 1); 73 sdrcrate >>= ((clkrate / rate) >> 1);
72 74
73 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); 75 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
74 if (ret) 76 if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
82 /* 84 /*
83 * XXX This only needs to be done when the CPU frequency changes 85 * XXX This only needs to be done when the CPU frequency changes
84 */ 86 */
85 _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; 87 _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
86 c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; 88 c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
87 c += 1; /* for safety */ 89 c += 1; /* for safety */
88 c *= SDRC_MPURATE_LOOPS; 90 c *= SDRC_MPURATE_LOOPS;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
90 if (c == 0) 92 if (c == 0)
91 c = 1; 93 c = 1;
92 94
93 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, 95 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
94 validrate); 96 clkrate, validrate);
95 pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", 97 pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
96 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 98 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
97 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr); 99 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
@@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
102 104
103 if (sdrc_cs1) 105 if (sdrc_cs1)
104 omap3_configure_core_dpll( 106 omap3_configure_core_dpll(
105 new_div, unlock_dll, c, rate > clk->rate, 107 new_div, unlock_dll, c, rate > clkrate,
106 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 108 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
107 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 109 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
108 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, 110 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
109 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); 111 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
110 else 112 else
111 omap3_configure_core_dpll( 113 omap3_configure_core_dpll(
112 new_div, unlock_dll, c, rate > clk->rate, 114 new_div, unlock_dll, c, rate > clkrate,
113 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, 115 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
114 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 116 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
115 0, 0, 0, 0); 117 0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 19a980956d44..eaed3900a83c 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -72,7 +72,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
72 if (!clks->parent) { 72 if (!clks->parent) {
73 /* This indicates a data problem */ 73 /* This indicates a data problem */
74 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n", 74 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
75 clk->name, src_clk->name); 75 __clk_get_name(clk), __clk_get_name(src_clk));
76 return NULL; 76 return NULL;
77 } 77 }
78 78
@@ -127,7 +127,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
127 if (max_div == 0) { 127 if (max_div == 0) {
128 /* This indicates an error in the clksel data */ 128 /* This indicates an error in the clksel data */
129 WARN(1, "clock: %s: could not find divisor for parent %s\n", 129 WARN(1, "clock: %s: could not find divisor for parent %s\n",
130 clk->name, src_clk->parent->name); 130 __clk_get_name(clk),
131 __clk_get_name(__clk_get_parent(src_clk)));
131 return 0; 132 return 0;
132 } 133 }
133 134
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
176{ 177{
177 const struct clksel *clks; 178 const struct clksel *clks;
178 const struct clksel_rate *clkr; 179 const struct clksel_rate *clkr;
180 struct clk *parent;
179 181
180 clks = _get_clksel_by_parent(clk, clk->parent); 182 parent = __clk_get_parent(clk);
183 clks = _get_clksel_by_parent(clk, parent);
181 if (!clks) 184 if (!clks)
182 return 0; 185 return 0;
183 186
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
191 194
192 if (!clkr->div) { 195 if (!clkr->div) {
193 /* This indicates a data error */ 196 /* This indicates a data error */
194 WARN(1, "clock: %s: could not find fieldval %d parent %s\n", 197 WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
195 clk->name, field_val, clk->parent->name); 198 __clk_get_name(clk), field_val, __clk_get_name(parent));
196 return 0; 199 return 0;
197 } 200 }
198 201
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
213{ 216{
214 const struct clksel *clks; 217 const struct clksel *clks;
215 const struct clksel_rate *clkr; 218 const struct clksel_rate *clkr;
219 struct clk *parent;
216 220
217 /* should never happen */ 221 /* should never happen */
218 WARN_ON(div == 0); 222 WARN_ON(div == 0);
219 223
220 clks = _get_clksel_by_parent(clk, clk->parent); 224 parent = __clk_get_parent(clk);
225 clks = _get_clksel_by_parent(clk, parent);
221 if (!clks) 226 if (!clks)
222 return ~0; 227 return ~0;
223 228
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
230 } 235 }
231 236
232 if (!clkr->div) { 237 if (!clkr->div) {
233 pr_err("clock: %s: could not find divisor %d parent %s\n", 238 pr_err("clock: %s: could not find divisor %d for parent %s\n",
234 clk->name, div, clk->parent->name); 239 __clk_get_name(clk), div, __clk_get_name(parent));
235 return ~0; 240 return ~0;
236 } 241 }
237 242
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
281 const struct clksel *clks; 286 const struct clksel *clks;
282 const struct clksel_rate *clkr; 287 const struct clksel_rate *clkr;
283 u32 last_div = 0; 288 u32 last_div = 0;
289 struct clk *parent;
290 unsigned long parent_rate;
291 const char *clk_name;
292
293 parent = __clk_get_parent(clk);
294 parent_rate = __clk_get_rate(parent);
295 clk_name = __clk_get_name(clk);
284 296
285 if (!clk->clksel || !clk->clksel_mask) 297 if (!clk->clksel || !clk->clksel_mask)
286 return ~0; 298 return ~0;
287 299
288 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", 300 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
289 clk->name, target_rate); 301 clk_name, target_rate);
290 302
291 *new_div = 1; 303 *new_div = 1;
292 304
293 clks = _get_clksel_by_parent(clk, clk->parent); 305 clks = _get_clksel_by_parent(clk, parent);
294 if (!clks) 306 if (!clks)
295 return ~0; 307 return ~0;
296 308
@@ -300,29 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
300 312
301 /* Sanity check */ 313 /* Sanity check */
302 if (clkr->div <= last_div) 314 if (clkr->div <= last_div)
303 pr_err("clock: %s: clksel_rate table not sorted", 315 pr_err("clock: %s: clksel_rate table not sorted\n",
304 clk->name); 316 clk_name);
305 317
306 last_div = clkr->div; 318 last_div = clkr->div;
307 319
308 test_rate = clk->parent->rate / clkr->div; 320 test_rate = parent_rate / clkr->div;
309 321
310 if (test_rate <= target_rate) 322 if (test_rate <= target_rate)
311 break; /* found it */ 323 break; /* found it */
312 } 324 }
313 325
314 if (!clkr->div) { 326 if (!clkr->div) {
315 pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n", 327 pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
316 clk->name, target_rate, clk->parent->name); 328 clk_name, target_rate, __clk_get_name(parent));
317 return ~0; 329 return ~0;
318 } 330 }
319 331
320 *new_div = clkr->div; 332 *new_div = clkr->div;
321 333
322 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, 334 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
323 (clk->parent->rate / clkr->div)); 335 (parent_rate / clkr->div));
324 336
325 return clk->parent->rate / clkr->div; 337 return parent_rate / clkr->div;
326} 338}
327 339
328/* 340/*
@@ -344,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
344 const struct clksel *clks; 356 const struct clksel *clks;
345 const struct clksel_rate *clkr; 357 const struct clksel_rate *clkr;
346 u32 r, found = 0; 358 u32 r, found = 0;
359 struct clk *parent;
360 const char *clk_name;
347 361
348 if (!clk->clksel || !clk->clksel_mask) 362 if (!clk->clksel || !clk->clksel_mask)
349 return; 363 return;
350 364
365 parent = __clk_get_parent(clk);
366 clk_name = __clk_get_name(clk);
367
351 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 368 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
352 r >>= __ffs(clk->clksel_mask); 369 r >>= __ffs(clk->clksel_mask);
353 370
@@ -357,11 +374,13 @@ void omap2_init_clksel_parent(struct clk *clk)
357 continue; 374 continue;
358 375
359 if (clkr->val == r) { 376 if (clkr->val == r) {
360 if (clk->parent != clks->parent) { 377 if (parent != clks->parent) {
361 pr_debug("clock: %s: inited parent to %s (was %s)\n", 378 pr_debug("clock: %s: inited parent to %s (was %s)\n",
362 clk->name, clks->parent->name, 379 clk_name,
363 ((clk->parent) ? 380 __clk_get_name(clks->parent),
364 clk->parent->name : "NULL")); 381 ((parent) ?
382 __clk_get_name(parent) :
383 "NULL"));
365 clk_reparent(clk, clks->parent); 384 clk_reparent(clk, clks->parent);
366 }; 385 };
367 found = 1; 386 found = 1;
@@ -371,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk)
371 390
372 /* This indicates a data error */ 391 /* This indicates a data error */
373 WARN(!found, "clock: %s: init parent: could not find regval %0x\n", 392 WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
374 clk->name, r); 393 clk_name, r);
375 394
376 return; 395 return;
377} 396}
@@ -389,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
389{ 408{
390 unsigned long rate; 409 unsigned long rate;
391 u32 div = 0; 410 u32 div = 0;
411 struct clk *parent;
392 412
393 div = _read_divisor(clk); 413 div = _read_divisor(clk);
394 if (div == 0) 414 if (div == 0)
395 return clk->rate; 415 return __clk_get_rate(clk);
396 416
397 rate = clk->parent->rate / div; 417 parent = __clk_get_parent(clk);
418 rate = __clk_get_rate(parent) / div;
398 419
399 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name, 420 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
400 rate, div); 421 __clk_get_name(clk), rate, div);
401 422
402 return rate; 423 return rate;
403} 424}
@@ -452,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
452 473
453 _write_clksel_reg(clk, field_val); 474 _write_clksel_reg(clk, field_val);
454 475
455 clk->rate = clk->parent->rate / new_div; 476 clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
456 477
457 pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate); 478 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
479 __clk_get_rate(clk));
458 480
459 return 0; 481 return 0;
460} 482}
@@ -496,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
496 clk_reparent(clk, new_parent); 518 clk_reparent(clk, new_parent);
497 519
498 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 520 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
499 clk->rate = new_parent->rate; 521 clk->rate = __clk_get_rate(new_parent);
500 522
501 if (parent_div > 0) 523 if (parent_div > 0)
502 clk->rate /= parent_div; 524 __clk_get_rate(clk) /= parent_div;
503 525
504 pr_debug("clock: %s: set parent to %s (new rate %ld)\n", 526 pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
505 clk->name, clk->parent->name, clk->rate); 527 __clk_get_name(clk),
528 __clk_get_name(__clk_get_parent(clk)),
529 __clk_get_rate(clk));
506 530
507 return 0; 531 return 0;
508} 532}
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 83b658bf385a..80411142f482 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
87 dd = clk->dpll_data; 87 dd = clk->dpll_data;
88 88
89 /* DPLL divider must result in a valid jitter correction val */ 89 /* DPLL divider must result in a valid jitter correction val */
90 fint = clk->parent->rate / n; 90 fint = __clk_get_rate(__clk_get_parent(clk)) / n;
91 91
92 if (cpu_is_omap24xx()) { 92 if (cpu_is_omap24xx()) {
93 /* Should not be called for OMAP2, so warn if it is called */ 93 /* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
252 if (cpu_is_omap24xx()) { 252 if (cpu_is_omap24xx()) {
253 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 253 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
254 v == OMAP2XXX_EN_DPLL_FRBYPASS) 254 v == OMAP2XXX_EN_DPLL_FRBYPASS)
255 return dd->clk_bypass->rate; 255 return __clk_get_rate(dd->clk_bypass);
256 } else if (cpu_is_omap34xx()) { 256 } else if (cpu_is_omap34xx()) {
257 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 257 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
258 v == OMAP3XXX_EN_DPLL_FRBYPASS) 258 v == OMAP3XXX_EN_DPLL_FRBYPASS)
259 return dd->clk_bypass->rate; 259 return __clk_get_rate(dd->clk_bypass);
260 } else if (soc_is_am33xx() || cpu_is_omap44xx()) { 260 } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
261 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 261 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
262 v == OMAP4XXX_EN_DPLL_FRBYPASS || 262 v == OMAP4XXX_EN_DPLL_FRBYPASS ||
263 v == OMAP4XXX_EN_DPLL_MNBYPASS) 263 v == OMAP4XXX_EN_DPLL_MNBYPASS)
264 return dd->clk_bypass->rate; 264 return __clk_get_rate(dd->clk_bypass);
265 } 265 }
266 266
267 v = __raw_readl(dd->mult_div1_reg); 267 v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
270 dpll_div = v & dd->div1_mask; 270 dpll_div = v & dd->div1_mask;
271 dpll_div >>= __ffs(dd->div1_mask); 271 dpll_div >>= __ffs(dd->div1_mask);
272 272
273 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; 273 dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
274 do_div(dpll_clk, dpll_div + 1); 274 do_div(dpll_clk, dpll_div + 1);
275 275
276 return dpll_clk; 276 return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
296 unsigned long scaled_rt_rp; 296 unsigned long scaled_rt_rp;
297 unsigned long new_rate = 0; 297 unsigned long new_rate = 0;
298 struct dpll_data *dd; 298 struct dpll_data *dd;
299 unsigned long ref_rate;
300 const char *clk_name;
299 301
300 if (!clk || !clk->dpll_data) 302 if (!clk || !clk->dpll_data)
301 return ~0; 303 return ~0;
302 304
303 dd = clk->dpll_data; 305 dd = clk->dpll_data;
304 306
307 ref_rate = __clk_get_rate(dd->clk_ref);
308 clk_name = __clk_get_name(clk);
305 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", 309 pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
306 clk->name, target_rate); 310 clk_name, target_rate);
307 311
308 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); 312 scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
309 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 313 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
310 314
311 dd->last_rounded_rate = 0; 315 dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
332 break; 336 break;
333 337
334 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 338 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
335 dd->clk_ref->rate); 339 ref_rate);
336 340
337 /* m can't be set low enough for this n - try with a larger n */ 341 /* m can't be set low enough for this n - try with a larger n */
338 if (r == DPLL_MULT_UNDERFLOW) 342 if (r == DPLL_MULT_UNDERFLOW)
339 continue; 343 continue;
340 344
341 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n", 345 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
342 clk->name, m, n, new_rate); 346 clk_name, m, n, new_rate);
343 347
344 if (target_rate == new_rate) { 348 if (target_rate == new_rate) {
345 dd->last_rounded_m = m; 349 dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
350 } 354 }
351 355
352 if (target_rate != new_rate) { 356 if (target_rate != new_rate) {
353 pr_debug("clock: %s: cannot round to rate %ld\n", clk->name, 357 pr_debug("clock: %s: cannot round to rate %ld\n",
354 target_rate); 358 clk_name, target_rate);
355 return ~0; 359 return ~0;
356 } 360 }
357 361
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e97f98ffe8b2..961ac8f7e13d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -78,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
78 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 78 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
79 79
80 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, 80 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
81 clk->name); 81 __clk_get_name(clk));
82} 82}
83 83
84/* Public functions */ 84/* Public functions */
@@ -94,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
94void omap2_init_clk_clkdm(struct clk *clk) 94void omap2_init_clk_clkdm(struct clk *clk)
95{ 95{
96 struct clockdomain *clkdm; 96 struct clockdomain *clkdm;
97 const char *clk_name;
97 98
98 if (!clk->clkdm_name) 99 if (!clk->clkdm_name)
99 return; 100 return;
100 101
102 clk_name = __clk_get_name(clk);
103
101 clkdm = clkdm_lookup(clk->clkdm_name); 104 clkdm = clkdm_lookup(clk->clkdm_name);
102 if (clkdm) { 105 if (clkdm) {
103 pr_debug("clock: associated clk %s to clkdm %s\n", 106 pr_debug("clock: associated clk %s to clkdm %s\n",
104 clk->name, clk->clkdm_name); 107 clk_name, clk->clkdm_name);
105 clk->clkdm = clkdm; 108 clk->clkdm = clkdm;
106 } else { 109 } else {
107 pr_debug("clock: could not associate clk %s to clkdm %s\n", 110 pr_debug("clock: could not associate clk %s to clkdm %s\n",
108 clk->name, clk->clkdm_name); 111 clk_name, clk->clkdm_name);
109 } 112 }
110} 113}
111 114
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 12c178dbc9f5..c3cde1a2b6de 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {
1804 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), 1804 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
1805 /* DSS domain clocks */ 1805 /* DSS domain clocks */
1806 CLK("omapdss_dss", "ick", &dss_ick, CK_242X), 1806 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
1807 CLK(NULL, "dss_ick", &dss_ick, CK_242X),
1807 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X), 1808 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1808 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X), 1809 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1809 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X), 1810 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
@@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {
1843 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X), 1844 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1844 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X), 1845 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1845 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X), 1846 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
1847 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
1846 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X), 1848 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
1847 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X), 1849 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
1850 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
1848 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X), 1851 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
1849 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X), 1852 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
1853 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
1850 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X), 1854 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
1851 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X), 1855 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
1856 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
1852 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X), 1857 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
1853 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X), 1858 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1854 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X), 1859 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
@@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {
1859 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X), 1864 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1860 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X), 1865 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1861 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X), 1866 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
1867 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
1862 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X), 1868 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
1863 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X), 1869 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1864 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X), 1870 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1865 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X), 1871 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1866 CLK("omap24xxcam", "fck", &cam_fck, CK_242X), 1872 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1873 CLK(NULL, "cam_fck", &cam_fck, CK_242X),
1867 CLK("omap24xxcam", "ick", &cam_ick, CK_242X), 1874 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1875 CLK(NULL, "cam_ick", &cam_ick, CK_242X),
1868 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X), 1876 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1869 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X), 1877 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1870 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X), 1878 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
@@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {
1873 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X), 1881 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1874 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X), 1882 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
1875 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), 1883 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1884 CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
1876 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), 1885 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
1886 CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
1877 CLK(NULL, "fac_ick", &fac_ick, CK_242X), 1887 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1878 CLK(NULL, "fac_fck", &fac_fck, CK_242X), 1888 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
1879 CLK(NULL, "eac_ick", &eac_ick, CK_242X), 1889 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1880 CLK(NULL, "eac_fck", &eac_fck, CK_242X), 1890 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
1881 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), 1891 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
1892 CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
1882 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X), 1893 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
1894 CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
1883 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), 1895 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
1896 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
1884 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X), 1897 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
1885 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), 1898 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
1899 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
1886 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X), 1900 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
1887 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), 1901 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1888 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), 1902 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
@@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = {
1892 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), 1906 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
1893 CLK(NULL, "des_ick", &des_ick, CK_242X), 1907 CLK(NULL, "des_ick", &des_ick, CK_242X),
1894 CLK("omap-sham", "ick", &sha_ick, CK_242X), 1908 CLK("omap-sham", "ick", &sha_ick, CK_242X),
1909 CLK(NULL, "sha_ick", &sha_ick, CK_242X),
1895 CLK("omap_rng", "ick", &rng_ick, CK_242X), 1910 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1911 CLK(NULL, "rng_ick", &rng_ick, CK_242X),
1896 CLK("omap-aes", "ick", &aes_ick, CK_242X), 1912 CLK("omap-aes", "ick", &aes_ick, CK_242X),
1913 CLK(NULL, "aes_ick", &aes_ick, CK_242X),
1897 CLK(NULL, "pka_ick", &pka_ick, CK_242X), 1914 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1898 CLK(NULL, "usb_fck", &usb_fck, CK_242X), 1915 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1899 CLK("musb-hdrc", "fck", &osc_ck, CK_242X), 1916 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
1900 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), 1917 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
1901 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), 1918 CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
1902 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), 1919 CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
1920 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
1903}; 1921};
1904 1922
1905/* 1923/*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 7ea91398217a..22404fe435e7 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1888,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = {
1888 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), 1888 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1889 /* DSS domain clocks */ 1889 /* DSS domain clocks */
1890 CLK("omapdss_dss", "ick", &dss_ick, CK_243X), 1890 CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
1891 CLK(NULL, "dss_ick", &dss_ick, CK_243X),
1891 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X), 1892 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
1892 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X), 1893 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
1893 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X), 1894 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
@@ -1927,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = {
1927 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X), 1928 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1928 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X), 1929 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1929 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X), 1930 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1931 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
1930 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X), 1932 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
1931 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X), 1933 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1934 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
1932 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X), 1935 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
1933 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), 1936 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1937 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
1934 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X), 1938 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
1935 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), 1939 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1940 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
1936 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X), 1941 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
1937 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), 1942 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1943 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
1938 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X), 1944 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
1939 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X), 1945 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1946 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
1940 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X), 1947 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
1941 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X), 1948 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1949 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
1942 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X), 1950 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
1943 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), 1951 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1952 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
1944 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X), 1953 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
1945 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X), 1954 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1946 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X), 1955 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
@@ -1951,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = {
1951 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X), 1960 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1952 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X), 1961 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1953 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X), 1962 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1963 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
1954 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X), 1964 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
1955 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X), 1965 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1956 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X), 1966 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1957 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X), 1967 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1958 CLK(NULL, "icr_ick", &icr_ick, CK_243X), 1968 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1959 CLK("omap24xxcam", "fck", &cam_fck, CK_243X), 1969 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1970 CLK(NULL, "cam_fck", &cam_fck, CK_243X),
1960 CLK("omap24xxcam", "ick", &cam_ick, CK_243X), 1971 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1972 CLK(NULL, "cam_ick", &cam_ick, CK_243X),
1961 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X), 1973 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1962 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X), 1974 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1963 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X), 1975 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
@@ -1966,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = {
1966 CLK(NULL, "fac_ick", &fac_ick, CK_243X), 1978 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1967 CLK(NULL, "fac_fck", &fac_fck, CK_243X), 1979 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1968 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), 1980 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1981 CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
1969 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), 1982 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1983 CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
1970 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), 1984 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
1985 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
1971 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X), 1986 CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
1972 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), 1987 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
1988 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
1973 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X), 1989 CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
1974 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), 1990 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1975 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), 1991 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
@@ -1978,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = {
1978 CLK(NULL, "des_ick", &des_ick, CK_243X), 1994 CLK(NULL, "des_ick", &des_ick, CK_243X),
1979 CLK("omap-sham", "ick", &sha_ick, CK_243X), 1995 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1980 CLK("omap_rng", "ick", &rng_ick, CK_243X), 1996 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1997 CLK(NULL, "rng_ick", &rng_ick, CK_243X),
1981 CLK("omap-aes", "ick", &aes_ick, CK_243X), 1998 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1982 CLK(NULL, "pka_ick", &pka_ick, CK_243X), 1999 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1983 CLK(NULL, "usb_fck", &usb_fck, CK_243X), 2000 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1984 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), 2001 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
2002 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
1985 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), 2003 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
2004 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
1986 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X), 2005 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
1987 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), 2006 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
2007 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
1988 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X), 2008 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
1989 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), 2009 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1990 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), 2010 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
1991 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), 2011 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
1992 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), 2012 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2013 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
1993 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), 2014 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2015 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
1994 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X), 2016 CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
1995 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X), 2017 CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
1996 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X), 2018 CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
2019 CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
1997}; 2020};
1998 2021
1999/* 2022/*
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 2026311a4ff6..b87b88c2638b 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = {
1013 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX), 1013 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
1014 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX), 1014 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
1015 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX), 1015 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
1016 CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
1016 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX), 1017 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
1017 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX), 1018 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
1018 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX), 1019 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 15cdc6471737..83bb01427d40 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -63,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void)
63 63
64 dpll5_clk = clk_get(NULL, "dpll5_ck"); 64 dpll5_clk = clk_get(NULL, "dpll5_ck");
65 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST); 65 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
66 clk_enable(dpll5_clk); 66 clk_prepare_enable(dpll5_clk);
67 67
68 /* Program dpll5_m2_clk divider for no division */ 68 /* Program dpll5_m2_clk divider for no division */
69 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck"); 69 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
70 clk_enable(dpll5_m2_clk); 70 clk_prepare_enable(dpll5_m2_clk);
71 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST); 71 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
72 72
73 clk_disable(dpll5_m2_clk); 73 clk_disable_unprepare(dpll5_m2_clk);
74 clk_disable(dpll5_clk); 74 clk_disable_unprepare(dpll5_clk);
75 return; 75 return;
76} 76}
77 77
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 700317a1bd16..1f42c9d5ecf3 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = {
3215 * clkdev 3215 * clkdev
3216 */ 3216 */
3217 3217
3218/* XXX At some point we should rename this file to clock3xxx_data.c */
3219static struct omap_clk omap3xxx_clks[] = { 3218static struct omap_clk omap3xxx_clks[] = {
3220 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), 3219 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3221 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), 3220 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
@@ -3243,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = {
3243 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), 3242 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3244 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), 3243 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3245 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), 3244 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3245 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3246 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), 3246 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3247 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), 3247 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3248 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), 3248 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3249 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), 3249 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3250 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), 3250 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3251 CLK(NULL, "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
3251 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), 3252 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3252 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), 3253 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3253 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), 3254 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
@@ -3263,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = {
3263 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), 3264 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3264 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), 3265 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3265 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), 3266 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3267 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3266 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), 3268 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3267 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3269 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3268 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3270 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
@@ -3272,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = {
3272 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), 3274 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3273 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), 3275 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3274 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), 3276 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3277 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3275 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), 3278 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3276 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), 3279 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3277 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), 3280 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
@@ -3295,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = {
3295 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3298 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3296 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3299 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3297 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3300 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3301 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3298 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3302 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3299 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3303 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3300 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), 3304 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
@@ -3315,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = {
3315 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), 3319 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3316 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), 3320 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3317 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), 3321 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3322 CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
3318 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), 3323 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3319 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), 3324 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3320 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), 3325 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
@@ -3322,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = {
3322 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), 3327 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3323 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), 3328 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3324 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), 3329 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3330 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3331 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3325 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), 3332 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3326 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), 3333 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3327 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), 3334 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3329,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = {
3329 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3336 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3330 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3337 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3331 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3338 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3339 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3332 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3340 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3341 CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3333 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), 3342 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3334 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), 3343 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3335 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), 3344 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3336 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), 3345 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3337 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), 3346 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3338 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), 3347 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3348 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
3349 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
3339 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), 3350 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3340 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3351 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3352 CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
3341 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3353 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3342 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), 3354 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3343 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), 3355 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3344 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), 3356 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3357 CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
3358 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
3359 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
3360 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
3345 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), 3361 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3346 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), 3362 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3347 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), 3363 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3364 CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
3365 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
3366 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
3348 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), 3367 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3349 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), 3368 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3350 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), 3369 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3351 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), 3370 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3352 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), 3371 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3353 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), 3372 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3373 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
3374 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
3354 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), 3375 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3355 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), 3376 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3356 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), 3377 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
@@ -3369,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = {
3369 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), 3390 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
3370 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), 3391 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
3371 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), 3392 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3393 CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
3372 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3394 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3395 CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3373 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), 3396 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3374 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), 3397 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3375 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), 3398 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
@@ -3385,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = {
3385 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), 3408 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3386 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), 3409 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3387 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), 3410 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3411 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3412 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3388 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX), 3413 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
3389 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), 3414 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3390 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), 3415 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
@@ -3394,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = {
3394 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), 3419 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3395 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), 3420 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3396 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), 3421 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3422 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
3397 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), 3423 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3398 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), 3424 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3399 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), 3425 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3439,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = {
3439 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), 3465 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3440 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), 3466 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3441 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), 3467 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3468 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
3469 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
3470 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
3442 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), 3471 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3443 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), 3472 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3444 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), 3473 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3474 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
3445 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), 3475 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3446 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), 3476 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3447 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), 3477 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
@@ -3457,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = {
3457 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), 3487 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3458 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), 3488 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3459 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), 3489 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3490 CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
3491 CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
3460 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), 3492 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3461 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), 3493 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3494 CLK(NULL, "vpfe_ick", &emac_ick, CK_AM35XX),
3495 CLK(NULL, "vpfe_fck", &emac_fck, CK_AM35XX),
3462 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), 3496 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3463 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), 3497 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3464 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), 3498 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
@@ -3467,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = {
3467 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), 3501 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3468 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), 3502 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3469 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX), 3503 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3504 CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
3470}; 3505};
3471 3506
3472 3507
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 500682c051c1..d661d138f270 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
3156 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), 3156 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
3157 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), 3157 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
3158 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), 3158 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
3159 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
3159 CLK("omapdss_dss", "ick", &dss_fck, CK_443X), 3160 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
3160 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), 3161 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
3161 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), 3162 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
@@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {
3212 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), 3213 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3213 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), 3214 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3214 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), 3215 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
3216 CLK(NULL, "rng_ick", &rng_ick, CK_443X),
3215 CLK("omap_rng", "ick", &rng_ick, CK_443X), 3217 CLK("omap_rng", "ick", &rng_ick, CK_443X),
3216 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 3218 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
3217 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), 3219 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
@@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {
3243 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 3245 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
3244 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 3246 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
3245 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), 3247 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
3248 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
3246 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 3249 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
3247 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), 3250 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
3248 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), 3251 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
@@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = {
3253 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), 3256 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3254 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), 3257 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3255 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), 3258 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3259 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
3256 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), 3260 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
3257 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), 3261 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3258 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), 3262 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3263 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
3259 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), 3264 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
3260 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), 3265 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
3261 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), 3266 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3262 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), 3267 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3263 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), 3268 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3269 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
3264 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 3270 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3271 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3265 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 3272 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3266 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 3273 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3267 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 3274 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
@@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = {
3312 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), 3319 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3313 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), 3320 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
3314 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), 3321 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
3322 CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
3315 CLK("omap_wdt", "ick", &dummy_ck, CK_443X), 3323 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3316 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), 3324 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
3325 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
3317 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), 3326 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3318 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), 3327 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3319 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), 3328 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
@@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = {
3325 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 3334 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3326 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 3335 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3327 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), 3336 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3337 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3338 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3339 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3340 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3341 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3342 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3343 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3344 CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3345 CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3346 CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3347 CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3348 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
3328}; 3349};
3329 3350
3330int __init omap4xxx_clk_init(void) 3351int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index 532027ee3d8d..adf7bb79b18f 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -25,263 +25,328 @@
25 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER 25 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
26 */ 26 */
27#define AM33XX_AUTO_DPLL_MODE_SHIFT 0 27#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
28#define AM33XX_AUTO_DPLL_MODE_WIDTH 3
28#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) 29#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
29 30
30/* Used by CM_WKUP_CLKSTCTRL */ 31/* Used by CM_WKUP_CLKSTCTRL */
31#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 32#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
33#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1
32#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) 34#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
33 35
34/* Used by CM_PER_L4LS_CLKSTCTRL */ 36/* Used by CM_PER_L4LS_CLKSTCTRL */
35#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 37#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
38#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1
36#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) 39#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
37 40
38/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ 41/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
39#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 42#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
43#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1
40#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) 44#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
41 45
42/* Used by CM_PER_CPSW_CLKSTCTRL */ 46/* Used by CM_PER_CPSW_CLKSTCTRL */
43#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 47#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
48#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1
44#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) 49#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
45 50
46/* Used by CM_PER_L4HS_CLKSTCTRL */ 51/* Used by CM_PER_L4HS_CLKSTCTRL */
47#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 52#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
53#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1
48#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) 54#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
49 55
50/* Used by CM_PER_L4HS_CLKSTCTRL */ 56/* Used by CM_PER_L4HS_CLKSTCTRL */
51#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 57#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
58#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1
52#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) 59#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
53 60
54/* Used by CM_PER_L4HS_CLKSTCTRL */ 61/* Used by CM_PER_L4HS_CLKSTCTRL */
55#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 62#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
63#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1
56#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) 64#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
57 65
58/* Used by CM_PER_L3_CLKSTCTRL */ 66/* Used by CM_PER_L3_CLKSTCTRL */
59#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 67#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
68#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1
60#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) 69#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
61 70
62/* Used by CM_CEFUSE_CLKSTCTRL */ 71/* Used by CM_CEFUSE_CLKSTCTRL */
63#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 72#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
73#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1
64#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 74#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
65 75
66/* Used by CM_L3_AON_CLKSTCTRL */ 76/* Used by CM_L3_AON_CLKSTCTRL */
67#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 77#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
78#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1
68#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) 79#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
69 80
70/* Used by CM_L3_AON_CLKSTCTRL */ 81/* Used by CM_L3_AON_CLKSTCTRL */
71#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 82#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
83#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1
72#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) 84#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
73 85
74/* Used by CM_PER_L3_CLKSTCTRL */ 86/* Used by CM_PER_L3_CLKSTCTRL */
75#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 87#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
88#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1
76#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) 89#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
77 90
78/* Used by CM_GFX_L3_CLKSTCTRL */ 91/* Used by CM_GFX_L3_CLKSTCTRL */
79#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 92#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
93#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1
80#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) 94#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
81 95
82/* Used by CM_GFX_L3_CLKSTCTRL */ 96/* Used by CM_GFX_L3_CLKSTCTRL */
83#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 97#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
98#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1
84#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) 99#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
85 100
86/* Used by CM_WKUP_CLKSTCTRL */ 101/* Used by CM_WKUP_CLKSTCTRL */
87#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 102#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
103#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1
88#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) 104#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
89 105
90/* Used by CM_PER_L4LS_CLKSTCTRL */ 106/* Used by CM_PER_L4LS_CLKSTCTRL */
91#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 107#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
108#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1
92#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) 109#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
93 110
94/* Used by CM_PER_L4LS_CLKSTCTRL */ 111/* Used by CM_PER_L4LS_CLKSTCTRL */
95#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 112#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
113#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1
96#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) 114#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
97 115
98/* Used by CM_PER_L4LS_CLKSTCTRL */ 116/* Used by CM_PER_L4LS_CLKSTCTRL */
99#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 117#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
118#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1
100#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) 119#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
101 120
102/* Used by CM_PER_L4LS_CLKSTCTRL */ 121/* Used by CM_PER_L4LS_CLKSTCTRL */
103#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 122#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
123#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1
104#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) 124#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
105 125
106/* Used by CM_PER_L4LS_CLKSTCTRL */ 126/* Used by CM_PER_L4LS_CLKSTCTRL */
107#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 127#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
128#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1
108#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) 129#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
109 130
110/* Used by CM_PER_L4LS_CLKSTCTRL */ 131/* Used by CM_PER_L4LS_CLKSTCTRL */
111#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 132#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
133#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1
112#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) 134#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
113 135
114/* Used by CM_WKUP_CLKSTCTRL */ 136/* Used by CM_WKUP_CLKSTCTRL */
115#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 137#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
138#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1
116#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) 139#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
117 140
118/* Used by CM_PER_L4LS_CLKSTCTRL */ 141/* Used by CM_PER_L4LS_CLKSTCTRL */
119#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 142#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
143#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1
120#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) 144#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
121 145
122/* Used by CM_PER_PRUSS_CLKSTCTRL */ 146/* Used by CM_PER_PRUSS_CLKSTCTRL */
123#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 147#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
148#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1
124#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) 149#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
125 150
126/* Used by CM_PER_PRUSS_CLKSTCTRL */ 151/* Used by CM_PER_PRUSS_CLKSTCTRL */
127#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 152#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
153#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1
128#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) 154#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
129 155
130/* Used by CM_PER_PRUSS_CLKSTCTRL */ 156/* Used by CM_PER_PRUSS_CLKSTCTRL */
131#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 157#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
158#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1
132#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) 159#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
133 160
134/* Used by CM_PER_L3S_CLKSTCTRL */ 161/* Used by CM_PER_L3S_CLKSTCTRL */
135#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 162#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
163#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1
136#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) 164#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
137 165
138/* Used by CM_L3_AON_CLKSTCTRL */ 166/* Used by CM_L3_AON_CLKSTCTRL */
139#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 167#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
168#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1
140#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) 169#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
141 170
142/* Used by CM_PER_L3_CLKSTCTRL */ 171/* Used by CM_PER_L3_CLKSTCTRL */
143#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 172#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
173#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1
144#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) 174#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
145 175
146/* Used by CM_PER_L4FW_CLKSTCTRL */ 176/* Used by CM_PER_L4FW_CLKSTCTRL */
147#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 177#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
178#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1
148#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) 179#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
149 180
150/* Used by CM_PER_L4HS_CLKSTCTRL */ 181/* Used by CM_PER_L4HS_CLKSTCTRL */
151#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 182#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
183#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1
152#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) 184#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
153 185
154/* Used by CM_PER_L4LS_CLKSTCTRL */ 186/* Used by CM_PER_L4LS_CLKSTCTRL */
155#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 187#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
188#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1
156#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) 189#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
157 190
158/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ 191/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
159#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 192#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
193#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1
160#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) 194#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
161 195
162/* Used by CM_CEFUSE_CLKSTCTRL */ 196/* Used by CM_CEFUSE_CLKSTCTRL */
163#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 197#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
198#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1
164#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) 199#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
165 200
166/* Used by CM_RTC_CLKSTCTRL */ 201/* Used by CM_RTC_CLKSTCTRL */
167#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 202#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
203#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1
168#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) 204#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
169 205
170/* Used by CM_L4_WKUP_AON_CLKSTCTRL */ 206/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
171#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 207#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
208#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1
172#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) 209#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
173 210
174/* Used by CM_WKUP_CLKSTCTRL */ 211/* Used by CM_WKUP_CLKSTCTRL */
175#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 212#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
213#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1
176#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) 214#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
177 215
178/* Used by CM_PER_L4LS_CLKSTCTRL */ 216/* Used by CM_PER_L4LS_CLKSTCTRL */
179#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 217#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
218#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1
180#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) 219#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
181 220
182/* Used by CM_PER_LCDC_CLKSTCTRL */ 221/* Used by CM_PER_LCDC_CLKSTCTRL */
183#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 222#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
223#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1
184#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) 224#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
185 225
186/* Used by CM_PER_LCDC_CLKSTCTRL */ 226/* Used by CM_PER_LCDC_CLKSTCTRL */
187#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 227#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
228#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1
188#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) 229#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
189 230
190/* Used by CM_PER_L3_CLKSTCTRL */ 231/* Used by CM_PER_L3_CLKSTCTRL */
191#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 232#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
233#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1
192#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) 234#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
193 235
194/* Used by CM_PER_L3_CLKSTCTRL */ 236/* Used by CM_PER_L3_CLKSTCTRL */
195#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 237#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
238#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1
196#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) 239#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
197 240
198/* Used by CM_MPU_CLKSTCTRL */ 241/* Used by CM_MPU_CLKSTCTRL */
199#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 242#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
243#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1
200#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) 244#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
201 245
202/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ 246/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
203#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 247#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
248#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1
204#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) 249#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
205 250
206/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ 251/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
207#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 252#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
253#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1
208#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) 254#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
209 255
210/* Used by CM_RTC_CLKSTCTRL */ 256/* Used by CM_RTC_CLKSTCTRL */
211#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 257#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
258#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1
212#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) 259#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
213 260
214/* Used by CM_PER_L4LS_CLKSTCTRL */ 261/* Used by CM_PER_L4LS_CLKSTCTRL */
215#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 262#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
263#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1
216#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) 264#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
217 265
218/* Used by CM_WKUP_CLKSTCTRL */ 266/* Used by CM_WKUP_CLKSTCTRL */
219#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 267#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
268#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1
220#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) 269#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
221 270
222/* Used by CM_WKUP_CLKSTCTRL */ 271/* Used by CM_WKUP_CLKSTCTRL */
223#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 272#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
273#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1
224#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) 274#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
225 275
226/* Used by CM_WKUP_CLKSTCTRL */ 276/* Used by CM_WKUP_CLKSTCTRL */
227#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 277#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
278#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1
228#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) 279#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
229 280
230/* Used by CM_PER_L4LS_CLKSTCTRL */ 281/* Used by CM_PER_L4LS_CLKSTCTRL */
231#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 282#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
283#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1
232#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) 284#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
233 285
234/* Used by CM_PER_L4LS_CLKSTCTRL */ 286/* Used by CM_PER_L4LS_CLKSTCTRL */
235#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 287#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
288#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1
236#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) 289#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
237 290
238/* Used by CM_PER_L4LS_CLKSTCTRL */ 291/* Used by CM_PER_L4LS_CLKSTCTRL */
239#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 292#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
293#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1
240#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) 294#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
241 295
242/* Used by CM_PER_L4LS_CLKSTCTRL */ 296/* Used by CM_PER_L4LS_CLKSTCTRL */
243#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 297#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
298#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1
244#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) 299#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
245 300
246/* Used by CM_PER_L4LS_CLKSTCTRL */ 301/* Used by CM_PER_L4LS_CLKSTCTRL */
247#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 302#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
303#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1
248#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) 304#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
249 305
250/* Used by CM_PER_L4LS_CLKSTCTRL */ 306/* Used by CM_PER_L4LS_CLKSTCTRL */
251#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 307#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
308#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1
252#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) 309#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
253 310
254/* Used by CM_WKUP_CLKSTCTRL */ 311/* Used by CM_WKUP_CLKSTCTRL */
255#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 312#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
313#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1
256#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) 314#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
257 315
258/* Used by CM_PER_L4LS_CLKSTCTRL */ 316/* Used by CM_PER_L4LS_CLKSTCTRL */
259#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 317#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
318#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1
260#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) 319#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
261 320
262/* Used by CM_WKUP_CLKSTCTRL */ 321/* Used by CM_WKUP_CLKSTCTRL */
263#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 322#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
323#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1
264#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) 324#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
265 325
266/* Used by CM_WKUP_CLKSTCTRL */ 326/* Used by CM_WKUP_CLKSTCTRL */
267#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 327#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
328#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1
268#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) 329#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
269 330
270/* Used by CLKSEL_GFX_FCLK */ 331/* Used by CLKSEL_GFX_FCLK */
271#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 332#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
333#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1
272#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) 334#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
273 335
274/* Used by CM_CLKOUT_CTRL */ 336/* Used by CM_CLKOUT_CTRL */
275#define AM33XX_CLKOUT2DIV_SHIFT 3 337#define AM33XX_CLKOUT2DIV_SHIFT 3
276#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3) 338#define AM33XX_CLKOUT2DIV_WIDTH 3
339#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
277 340
278/* Used by CM_CLKOUT_CTRL */ 341/* Used by CM_CLKOUT_CTRL */
279#define AM33XX_CLKOUT2EN_SHIFT 7 342#define AM33XX_CLKOUT2EN_SHIFT 7
343#define AM33XX_CLKOUT2EN_WIDTH 1
280#define AM33XX_CLKOUT2EN_MASK (1 << 7) 344#define AM33XX_CLKOUT2EN_MASK (1 << 7)
281 345
282/* Used by CM_CLKOUT_CTRL */ 346/* Used by CM_CLKOUT_CTRL */
283#define AM33XX_CLKOUT2SOURCE_SHIFT 0 347#define AM33XX_CLKOUT2SOURCE_SHIFT 0
284#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0) 348#define AM33XX_CLKOUT2SOURCE_WIDTH 3
349#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
285 350
286/* 351/*
287 * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, 352 * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
@@ -289,6 +354,7 @@
289 * CLKSEL_TIMER7_CLK 354 * CLKSEL_TIMER7_CLK
290 */ 355 */
291#define AM33XX_CLKSEL_SHIFT 0 356#define AM33XX_CLKSEL_SHIFT 0
357#define AM33XX_CLKSEL_WIDTH 1
292#define AM33XX_CLKSEL_MASK (0x01 << 0) 358#define AM33XX_CLKSEL_MASK (0x01 << 0)
293 359
294/* 360/*
@@ -296,17 +362,21 @@
296 * CM_CPTS_RFT_CLKSEL 362 * CM_CPTS_RFT_CLKSEL
297 */ 363 */
298#define AM33XX_CLKSEL_0_0_SHIFT 0 364#define AM33XX_CLKSEL_0_0_SHIFT 0
365#define AM33XX_CLKSEL_0_0_WIDTH 1
299#define AM33XX_CLKSEL_0_0_MASK (1 << 0) 366#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
300 367
301#define AM33XX_CLKSEL_0_1_SHIFT 0 368#define AM33XX_CLKSEL_0_1_SHIFT 0
369#define AM33XX_CLKSEL_0_1_WIDTH 2
302#define AM33XX_CLKSEL_0_1_MASK (3 << 0) 370#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
303 371
304/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ 372/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
305#define AM33XX_CLKSEL_0_2_SHIFT 0 373#define AM33XX_CLKSEL_0_2_SHIFT 0
374#define AM33XX_CLKSEL_0_2_WIDTH 3
306#define AM33XX_CLKSEL_0_2_MASK (7 << 0) 375#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
307 376
308/* Used by CLKSEL_GFX_FCLK */ 377/* Used by CLKSEL_GFX_FCLK */
309#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 378#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
379#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1
310#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) 380#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
311 381
312/* 382/*
@@ -318,6 +388,7 @@
318 * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL 388 * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
319 */ 389 */
320#define AM33XX_CLKTRCTRL_SHIFT 0 390#define AM33XX_CLKTRCTRL_SHIFT 0
391#define AM33XX_CLKTRCTRL_WIDTH 2
321#define AM33XX_CLKTRCTRL_MASK (0x3 << 0) 392#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
322 393
323/* 394/*
@@ -326,34 +397,42 @@
326 * CM_SSC_DELTAMSTEP_DPLL_PER 397 * CM_SSC_DELTAMSTEP_DPLL_PER
327 */ 398 */
328#define AM33XX_DELTAMSTEP_SHIFT 0 399#define AM33XX_DELTAMSTEP_SHIFT 0
329#define AM33XX_DELTAMSTEP_MASK (0x19 << 0) 400#define AM33XX_DELTAMSTEP_WIDTH 20
401#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)
330 402
331/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ 403/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
332#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 404#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
405#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1
333#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) 406#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
334 407
335/* Used by CM_CLKDCOLDO_DPLL_PER */ 408/* Used by CM_CLKDCOLDO_DPLL_PER */
336#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 409#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
410#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1
337#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) 411#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
338 412
339/* Used by CM_CLKDCOLDO_DPLL_PER */ 413/* Used by CM_CLKDCOLDO_DPLL_PER */
340#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 414#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
415#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1
341#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) 416#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
342 417
343/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ 418/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
344#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 419#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
420#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
345#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 421#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
346 422
347/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ 423/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
348#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 424#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
349#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0) 425#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7
426#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
350 427
351/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ 428/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
352#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 429#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
430#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1
353#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) 431#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
354 432
355/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ 433/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
356#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 434#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
435#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1
357#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) 436#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
358 437
359/* 438/*
@@ -361,6 +440,7 @@
361 * CM_DIV_M2_DPLL_PER 440 * CM_DIV_M2_DPLL_PER
362 */ 441 */
363#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 442#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
443#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1
364#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 444#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
365 445
366/* 446/*
@@ -368,19 +448,22 @@
368 * CM_CLKSEL_DPLL_MPU 448 * CM_CLKSEL_DPLL_MPU
369 */ 449 */
370#define AM33XX_DPLL_DIV_SHIFT 0 450#define AM33XX_DPLL_DIV_SHIFT 0
451#define AM33XX_DPLL_DIV_WIDTH 7
371#define AM33XX_DPLL_DIV_MASK (0x7f << 0) 452#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
372 453
373#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) 454#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
374 455
375/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ 456/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
376#define AM33XX_DPLL_DIV_0_7_SHIFT 0 457#define AM33XX_DPLL_DIV_0_7_SHIFT 0
377#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0) 458#define AM33XX_DPLL_DIV_0_7_WIDTH 8
459#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)
378 460
379/* 461/*
380 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, 462 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
381 * CM_CLKMODE_DPLL_MPU 463 * CM_CLKMODE_DPLL_MPU
382 */ 464 */
383#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 465#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
466#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1
384#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 467#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
385 468
386/* 469/*
@@ -388,6 +471,7 @@
388 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 471 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
389 */ 472 */
390#define AM33XX_DPLL_EN_SHIFT 0 473#define AM33XX_DPLL_EN_SHIFT 0
474#define AM33XX_DPLL_EN_WIDTH 3
391#define AM33XX_DPLL_EN_MASK (0x7 << 0) 475#define AM33XX_DPLL_EN_MASK (0x7 << 0)
392 476
393/* 477/*
@@ -395,6 +479,7 @@
395 * CM_CLKMODE_DPLL_MPU 479 * CM_CLKMODE_DPLL_MPU
396 */ 480 */
397#define AM33XX_DPLL_LPMODE_EN_SHIFT 10 481#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
482#define AM33XX_DPLL_LPMODE_EN_WIDTH 1
398#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) 483#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
399 484
400/* 485/*
@@ -402,10 +487,12 @@
402 * CM_CLKSEL_DPLL_MPU 487 * CM_CLKSEL_DPLL_MPU
403 */ 488 */
404#define AM33XX_DPLL_MULT_SHIFT 8 489#define AM33XX_DPLL_MULT_SHIFT 8
490#define AM33XX_DPLL_MULT_WIDTH 11
405#define AM33XX_DPLL_MULT_MASK (0x7ff << 8) 491#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
406 492
407/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ 493/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
408#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 494#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
495#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12
409#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) 496#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
410 497
411/* 498/*
@@ -413,17 +500,20 @@
413 * CM_CLKMODE_DPLL_MPU 500 * CM_CLKMODE_DPLL_MPU
414 */ 501 */
415#define AM33XX_DPLL_REGM4XEN_SHIFT 11 502#define AM33XX_DPLL_REGM4XEN_SHIFT 11
503#define AM33XX_DPLL_REGM4XEN_WIDTH 1
416#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) 504#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
417 505
418/* Used by CM_CLKSEL_DPLL_PERIPH */ 506/* Used by CM_CLKSEL_DPLL_PERIPH */
419#define AM33XX_DPLL_SD_DIV_SHIFT 24 507#define AM33XX_DPLL_SD_DIV_SHIFT 24
420#define AM33XX_DPLL_SD_DIV_MASK (24, 31) 508#define AM33XX_DPLL_SD_DIV_WIDTH 8
509#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)
421 510
422/* 511/*
423 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, 512 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
424 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 513 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
425 */ 514 */
426#define AM33XX_DPLL_SSC_ACK_SHIFT 13 515#define AM33XX_DPLL_SSC_ACK_SHIFT 13
516#define AM33XX_DPLL_SSC_ACK_WIDTH 1
427#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) 517#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
428 518
429/* 519/*
@@ -431,6 +521,7 @@
431 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 521 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
432 */ 522 */
433#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 523#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
524#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1
434#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 525#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
435 526
436/* 527/*
@@ -438,54 +529,67 @@
438 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 529 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
439 */ 530 */
440#define AM33XX_DPLL_SSC_EN_SHIFT 12 531#define AM33XX_DPLL_SSC_EN_SHIFT 12
532#define AM33XX_DPLL_SSC_EN_WIDTH 1
441#define AM33XX_DPLL_SSC_EN_MASK (1 << 12) 533#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
442 534
443/* Used by CM_DIV_M4_DPLL_CORE */ 535/* Used by CM_DIV_M4_DPLL_CORE */
444#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 536#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
537#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
445#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 538#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
446 539
447/* Used by CM_DIV_M4_DPLL_CORE */ 540/* Used by CM_DIV_M4_DPLL_CORE */
448#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 541#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
542#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1
449#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) 543#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
450 544
451/* Used by CM_DIV_M4_DPLL_CORE */ 545/* Used by CM_DIV_M4_DPLL_CORE */
452#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 546#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
547#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1
453#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) 548#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
454 549
455/* Used by CM_DIV_M4_DPLL_CORE */ 550/* Used by CM_DIV_M4_DPLL_CORE */
456#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 551#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
552#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1
457#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) 553#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
458 554
459/* Used by CM_DIV_M5_DPLL_CORE */ 555/* Used by CM_DIV_M5_DPLL_CORE */
460#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 556#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
557#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
461#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 558#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
462 559
463/* Used by CM_DIV_M5_DPLL_CORE */ 560/* Used by CM_DIV_M5_DPLL_CORE */
464#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 561#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
562#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1
465#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) 563#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
466 564
467/* Used by CM_DIV_M5_DPLL_CORE */ 565/* Used by CM_DIV_M5_DPLL_CORE */
468#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 566#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
567#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1
469#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) 568#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
470 569
471/* Used by CM_DIV_M5_DPLL_CORE */ 570/* Used by CM_DIV_M5_DPLL_CORE */
472#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 571#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
572#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1
473#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) 573#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
474 574
475/* Used by CM_DIV_M6_DPLL_CORE */ 575/* Used by CM_DIV_M6_DPLL_CORE */
476#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 576#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
477#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0) 577#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
578#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
478 579
479/* Used by CM_DIV_M6_DPLL_CORE */ 580/* Used by CM_DIV_M6_DPLL_CORE */
480#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 581#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
582#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1
481#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) 583#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
482 584
483/* Used by CM_DIV_M6_DPLL_CORE */ 585/* Used by CM_DIV_M6_DPLL_CORE */
484#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 586#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
587#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1
485#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) 588#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
486 589
487/* Used by CM_DIV_M6_DPLL_CORE */ 590/* Used by CM_DIV_M6_DPLL_CORE */
488#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 591#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
592#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1
489#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) 593#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
490 594
491/* 595/*
@@ -522,11 +626,12 @@
522 * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL 626 * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
523 */ 627 */
524#define AM33XX_IDLEST_SHIFT 16 628#define AM33XX_IDLEST_SHIFT 16
629#define AM33XX_IDLEST_WIDTH 2
525#define AM33XX_IDLEST_MASK (0x3 << 16) 630#define AM33XX_IDLEST_MASK (0x3 << 16)
526#define AM33XX_IDLEST_VAL 0x3
527 631
528/* Used by CM_MAC_CLKSEL */ 632/* Used by CM_MAC_CLKSEL */
529#define AM33XX_MII_CLK_SEL_SHIFT 2 633#define AM33XX_MII_CLK_SEL_SHIFT 2
634#define AM33XX_MII_CLK_SEL_WIDTH 1
530#define AM33XX_MII_CLK_SEL_MASK (1 << 2) 635#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
531 636
532/* 637/*
@@ -535,7 +640,8 @@
535 * CM_SSC_MODFREQDIV_DPLL_PER 640 * CM_SSC_MODFREQDIV_DPLL_PER
536 */ 641 */
537#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 642#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
538#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8) 643#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3
644#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
539 645
540/* 646/*
541 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, 647 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
@@ -543,7 +649,8 @@
543 * CM_SSC_MODFREQDIV_DPLL_PER 649 * CM_SSC_MODFREQDIV_DPLL_PER
544 */ 650 */
545#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 651#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
546#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0) 652#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7
653#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
547 654
548/* 655/*
549 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, 656 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
@@ -580,42 +687,52 @@
580 * CM_CEFUSE_CEFUSE_CLKCTRL 687 * CM_CEFUSE_CEFUSE_CLKCTRL
581 */ 688 */
582#define AM33XX_MODULEMODE_SHIFT 0 689#define AM33XX_MODULEMODE_SHIFT 0
690#define AM33XX_MODULEMODE_WIDTH 2
583#define AM33XX_MODULEMODE_MASK (0x3 << 0) 691#define AM33XX_MODULEMODE_MASK (0x3 << 0)
584 692
585/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ 693/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
586#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 694#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
695#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1
587#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) 696#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
588 697
589/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ 698/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
590#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 699#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
700#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1
591#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) 701#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
592 702
593/* Used by CM_WKUP_GPIO0_CLKCTRL */ 703/* Used by CM_WKUP_GPIO0_CLKCTRL */
594#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 704#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
705#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1
595#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) 706#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
596 707
597/* Used by CM_PER_GPIO1_CLKCTRL */ 708/* Used by CM_PER_GPIO1_CLKCTRL */
598#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 709#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
710#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1
599#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) 711#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
600 712
601/* Used by CM_PER_GPIO2_CLKCTRL */ 713/* Used by CM_PER_GPIO2_CLKCTRL */
602#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 714#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
715#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1
603#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) 716#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
604 717
605/* Used by CM_PER_GPIO3_CLKCTRL */ 718/* Used by CM_PER_GPIO3_CLKCTRL */
606#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 719#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
720#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1
607#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) 721#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
608 722
609/* Used by CM_PER_GPIO4_CLKCTRL */ 723/* Used by CM_PER_GPIO4_CLKCTRL */
610#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 724#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
725#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1
611#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) 726#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
612 727
613/* Used by CM_PER_GPIO5_CLKCTRL */ 728/* Used by CM_PER_GPIO5_CLKCTRL */
614#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 729#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
730#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1
615#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) 731#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
616 732
617/* Used by CM_PER_GPIO6_CLKCTRL */ 733/* Used by CM_PER_GPIO6_CLKCTRL */
618#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 734#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
735#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1
619#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) 736#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
620 737
621/* 738/*
@@ -627,25 +744,30 @@
627 * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL 744 * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
628 */ 745 */
629#define AM33XX_STBYST_SHIFT 18 746#define AM33XX_STBYST_SHIFT 18
747#define AM33XX_STBYST_WIDTH 1
630#define AM33XX_STBYST_MASK (1 << 18) 748#define AM33XX_STBYST_MASK (1 << 18)
631 749
632/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ 750/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
633#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 751#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
634#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27) 752#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
753#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)
635 754
636/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ 755/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
637#define AM33XX_STM_PMD_CLKSEL_SHIFT 22 756#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
638#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22) 757#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
758#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)
639 759
640/* 760/*
641 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, 761 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
642 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER 762 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
643 */ 763 */
644#define AM33XX_ST_DPLL_CLK_SHIFT 0 764#define AM33XX_ST_DPLL_CLK_SHIFT 0
765#define AM33XX_ST_DPLL_CLK_WIDTH 1
645#define AM33XX_ST_DPLL_CLK_MASK (1 << 0) 766#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
646 767
647/* Used by CM_CLKDCOLDO_DPLL_PER */ 768/* Used by CM_CLKDCOLDO_DPLL_PER */
648#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 769#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
770#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1
649#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) 771#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
650 772
651/* 773/*
@@ -653,18 +775,22 @@
653 * CM_DIV_M2_DPLL_PER 775 * CM_DIV_M2_DPLL_PER
654 */ 776 */
655#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 777#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
778#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1
656#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) 779#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
657 780
658/* Used by CM_DIV_M4_DPLL_CORE */ 781/* Used by CM_DIV_M4_DPLL_CORE */
659#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 782#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
783#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1
660#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) 784#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
661 785
662/* Used by CM_DIV_M5_DPLL_CORE */ 786/* Used by CM_DIV_M5_DPLL_CORE */
663#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 787#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
788#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1
664#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) 789#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
665 790
666/* Used by CM_DIV_M6_DPLL_CORE */ 791/* Used by CM_DIV_M6_DPLL_CORE */
667#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 792#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
793#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1
668#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) 794#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
669 795
670/* 796/*
@@ -672,16 +798,20 @@
672 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER 798 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
673 */ 799 */
674#define AM33XX_ST_MN_BYPASS_SHIFT 8 800#define AM33XX_ST_MN_BYPASS_SHIFT 8
801#define AM33XX_ST_MN_BYPASS_WIDTH 1
675#define AM33XX_ST_MN_BYPASS_MASK (1 << 8) 802#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
676 803
677/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ 804/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
678#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 805#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
679#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24) 806#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
807#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)
680 808
681/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ 809/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
682#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 810#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
683#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20) 811#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
812#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)
684 813
685/* Used by CONTROL_SEC_CLK_CTRL */ 814/* Used by CONTROL_SEC_CLK_CTRL */
815#define AM33XX_TIMER0_CLKSEL_WIDTH 2
686#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) 816#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
687#endif 817#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 65597a745638..4c6c2f7de65b 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP44xx Clock Management register bits 2 * OMAP44xx Clock Management register bits
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
@@ -24,6 +24,7 @@
24 24
25/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ 25/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
26#define OMAP4430_ABE_DYNDEP_SHIFT 3 26#define OMAP4430_ABE_DYNDEP_SHIFT 3
27#define OMAP4430_ABE_DYNDEP_WIDTH 0x1
27#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) 28#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
28 29
29/* 30/*
@@ -31,14 +32,17 @@
31 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 32 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
32 */ 33 */
33#define OMAP4430_ABE_STATDEP_SHIFT 3 34#define OMAP4430_ABE_STATDEP_SHIFT 3
35#define OMAP4430_ABE_STATDEP_WIDTH 0x1
34#define OMAP4430_ABE_STATDEP_MASK (1 << 3) 36#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
35 37
36/* Used by CM_L4CFG_DYNAMICDEP */ 38/* Used by CM_L4CFG_DYNAMICDEP */
37#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 39#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
40#define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1
38#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) 41#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
39 42
40/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ 43/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
41#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 44#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16
45#define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1
42#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) 46#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16)
43 47
44/* 48/*
@@ -47,294 +51,367 @@
47 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB 51 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
48 */ 52 */
49#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 53#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
54#define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3
50#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) 55#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
51 56
52/* Used by CM_L4CFG_DYNAMICDEP */ 57/* Used by CM_L4CFG_DYNAMICDEP */
53#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 58#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
59#define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1
54#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) 60#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
55 61
56/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ 62/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
57#define OMAP4430_CEFUSE_STATDEP_SHIFT 17 63#define OMAP4430_CEFUSE_STATDEP_SHIFT 17
64#define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1
58#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) 65#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17)
59 66
60/* Used by CM1_ABE_CLKSTCTRL */ 67/* Used by CM1_ABE_CLKSTCTRL */
61#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 68#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
69#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
62#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) 70#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
63 71
64/* Used by CM1_ABE_CLKSTCTRL */ 72/* Used by CM1_ABE_CLKSTCTRL */
65#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 73#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12
74#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1
66#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) 75#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12)
67 76
68/* Used by CM_WKUP_CLKSTCTRL */ 77/* Used by CM_WKUP_CLKSTCTRL */
69#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 78#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
79#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
70#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) 80#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
71 81
72/* Used by CM1_ABE_CLKSTCTRL */ 82/* Used by CM1_ABE_CLKSTCTRL */
73#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 83#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11
84#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1
74#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) 85#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11)
75 86
76/* Used by CM1_ABE_CLKSTCTRL */ 87/* Used by CM1_ABE_CLKSTCTRL */
77#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 88#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
89#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
78#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) 90#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
79 91
80/* Used by CM_MEMIF_CLKSTCTRL */ 92/* Used by CM_MEMIF_CLKSTCTRL */
81#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 93#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
94#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1
82#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) 95#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
83 96
84/* Used by CM_MEMIF_CLKSTCTRL */ 97/* Used by CM_MEMIF_CLKSTCTRL */
85#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 98#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
99#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1
86#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) 100#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
87 101
88/* Used by CM_MEMIF_CLKSTCTRL */ 102/* Used by CM_MEMIF_CLKSTCTRL */
89#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 103#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
104#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1
90#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) 105#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
91 106
92/* Used by CM_CAM_CLKSTCTRL */ 107/* Used by CM_CAM_CLKSTCTRL */
93#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 108#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9
109#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1
94#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) 110#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9)
95 111
96/* Used by CM_ALWON_CLKSTCTRL */ 112/* Used by CM_ALWON_CLKSTCTRL */
97#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 113#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12
114#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1
98#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) 115#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12)
99 116
100/* Used by CM_EMU_CLKSTCTRL */ 117/* Used by CM_EMU_CLKSTCTRL */
101#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 118#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
119#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1
102#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) 120#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
103 121
104/* Used by CM_L4CFG_CLKSTCTRL */ 122/* Used by CM_L4CFG_CLKSTCTRL */
105#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 123#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
124#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1
106#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) 125#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
107 126
108/* Used by CM_CEFUSE_CLKSTCTRL */ 127/* Used by CM_CEFUSE_CLKSTCTRL */
109#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 128#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
129#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1
110#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 130#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
111 131
112/* Used by CM_MEMIF_CLKSTCTRL */ 132/* Used by CM_MEMIF_CLKSTCTRL */
113#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 133#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
134#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1
114#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) 135#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
115 136
116/* Used by CM_L4PER_CLKSTCTRL */ 137/* Used by CM_L4PER_CLKSTCTRL */
117#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 138#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
139#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1
118#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) 140#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
119 141
120/* Used by CM_L4PER_CLKSTCTRL */ 142/* Used by CM_L4PER_CLKSTCTRL */
121#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 143#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
144#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1
122#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) 145#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
123 146
124/* Used by CM_L4PER_CLKSTCTRL */ 147/* Used by CM_L4PER_CLKSTCTRL */
125#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 148#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
149#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1
126#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) 150#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
127 151
128/* Used by CM_L4PER_CLKSTCTRL */ 152/* Used by CM_L4PER_CLKSTCTRL */
129#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 153#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
154#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1
130#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) 155#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
131 156
132/* Used by CM_L4PER_CLKSTCTRL */ 157/* Used by CM_L4PER_CLKSTCTRL */
133#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 158#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
159#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1
134#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) 160#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
135 161
136/* Used by CM_L4PER_CLKSTCTRL */ 162/* Used by CM_L4PER_CLKSTCTRL */
137#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 163#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
164#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1
138#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) 165#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
139 166
140/* Used by CM_DSS_CLKSTCTRL */ 167/* Used by CM_DSS_CLKSTCTRL */
141#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 168#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10
169#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1
142#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) 170#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10)
143 171
144/* Used by CM_DSS_CLKSTCTRL */ 172/* Used by CM_DSS_CLKSTCTRL */
145#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 173#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9
174#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1
146#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) 175#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9)
147 176
148/* Used by CM_DUCATI_CLKSTCTRL */ 177/* Used by CM_DUCATI_CLKSTCTRL */
149#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 178#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8
179#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1
150#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) 180#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8)
151 181
152/* Used by CM_EMU_CLKSTCTRL */ 182/* Used by CM_EMU_CLKSTCTRL */
153#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 183#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8
184#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1
154#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) 185#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8)
155 186
156/* Used by CM_CAM_CLKSTCTRL */ 187/* Used by CM_CAM_CLKSTCTRL */
157#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 188#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
189#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1
158#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) 190#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
159 191
160/* Used by CM_L4PER_CLKSTCTRL */ 192/* Used by CM_L4PER_CLKSTCTRL */
161#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 193#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
194#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1
162#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) 195#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
163 196
164/* Used by CM1_ABE_CLKSTCTRL */ 197/* Used by CM1_ABE_CLKSTCTRL */
165#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 198#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
199#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
166#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) 200#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
167 201
168/* Used by CM_DSS_CLKSTCTRL */ 202/* Used by CM_DSS_CLKSTCTRL */
169#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 203#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
204#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1
170#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) 205#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
171 206
172/* Used by CM_L3INIT_CLKSTCTRL */ 207/* Used by CM_L3INIT_CLKSTCTRL */
173#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 208#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
209#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
174#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) 210#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
175 211
176/* Used by CM_L3INIT_CLKSTCTRL */ 212/* Used by CM_L3INIT_CLKSTCTRL */
177#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 213#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
214#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
178#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) 215#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
179 216
180/* Used by CM_L3INIT_CLKSTCTRL */ 217/* Used by CM_L3INIT_CLKSTCTRL */
181#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 218#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
219#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
182#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) 220#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
183 221
184/* Used by CM_L3INIT_CLKSTCTRL */ 222/* Used by CM_L3INIT_CLKSTCTRL */
185#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 223#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
224#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
186#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) 225#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
187 226
188/* Used by CM_L3INIT_CLKSTCTRL */ 227/* Used by CM_L3INIT_CLKSTCTRL */
189#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 228#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
229#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1
190#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) 230#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
191 231
192/* Used by CM_L3INIT_CLKSTCTRL */ 232/* Used by CM_L3INIT_CLKSTCTRL */
193#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 233#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
234#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1
194#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) 235#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
195 236
196/* Used by CM_L3INIT_CLKSTCTRL */ 237/* Used by CM_L3INIT_CLKSTCTRL */
197#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 238#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
239#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1
198#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) 240#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
199 241
200/* Used by CM_L3INIT_CLKSTCTRL */ 242/* Used by CM_L3INIT_CLKSTCTRL */
201#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 243#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
244#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1
202#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) 245#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
203 246
204/* Used by CM_L3INIT_CLKSTCTRL */ 247/* Used by CM_L3INIT_CLKSTCTRL */
205#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 248#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
249#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1
206#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) 250#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
207 251
208/* Used by CM_L3INIT_CLKSTCTRL */ 252/* Used by CM_L3INIT_CLKSTCTRL */
209#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 253#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
254#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1
210#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) 255#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
211 256
212/* Used by CM_L3INIT_CLKSTCTRL */ 257/* Used by CM_L3INIT_CLKSTCTRL */
213#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 258#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
259#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1
214#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) 260#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
215 261
216/* Used by CM_L3INIT_CLKSTCTRL */ 262/* Used by CM_L3INIT_CLKSTCTRL */
217#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 263#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
264#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1
218#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) 265#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
219 266
220/* Used by CM_L3INIT_CLKSTCTRL */ 267/* Used by CM_L3INIT_CLKSTCTRL */
221#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 268#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
269#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1
222#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) 270#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
223 271
224/* Used by CM_CAM_CLKSTCTRL */ 272/* Used by CM_CAM_CLKSTCTRL */
225#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 273#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8
274#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1
226#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) 275#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8)
227 276
228/* Used by CM_IVAHD_CLKSTCTRL */ 277/* Used by CM_IVAHD_CLKSTCTRL */
229#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 278#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8
279#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1
230#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) 280#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8)
231 281
232/* Used by CM_D2D_CLKSTCTRL */ 282/* Used by CM_D2D_CLKSTCTRL */
233#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 283#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
284#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1
234#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) 285#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
235 286
236/* Used by CM_L3_1_CLKSTCTRL */ 287/* Used by CM_L3_1_CLKSTCTRL */
237#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 288#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
289#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1
238#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) 290#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
239 291
240/* Used by CM_L3_2_CLKSTCTRL */ 292/* Used by CM_L3_2_CLKSTCTRL */
241#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 293#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
294#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1
242#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) 295#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
243 296
244/* Used by CM_D2D_CLKSTCTRL */ 297/* Used by CM_D2D_CLKSTCTRL */
245#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 298#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8
299#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1
246#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) 300#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8)
247 301
248/* Used by CM_SDMA_CLKSTCTRL */ 302/* Used by CM_SDMA_CLKSTCTRL */
249#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 303#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8
304#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1
250#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) 305#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8)
251 306
252/* Used by CM_DSS_CLKSTCTRL */ 307/* Used by CM_DSS_CLKSTCTRL */
253#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 308#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
309#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1
254#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) 310#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
255 311
256/* Used by CM_MEMIF_CLKSTCTRL */ 312/* Used by CM_MEMIF_CLKSTCTRL */
257#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 313#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
314#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1
258#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) 315#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
259 316
260/* Used by CM_GFX_CLKSTCTRL */ 317/* Used by CM_GFX_CLKSTCTRL */
261#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 318#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
319#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1
262#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) 320#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
263 321
264/* Used by CM_L3INIT_CLKSTCTRL */ 322/* Used by CM_L3INIT_CLKSTCTRL */
265#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 323#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
324#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1
266#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) 325#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
267 326
268/* Used by CM_L3INSTR_CLKSTCTRL */ 327/* Used by CM_L3INSTR_CLKSTCTRL */
269#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 328#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8
329#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1
270#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) 330#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8)
271 331
272/* Used by CM_L4SEC_CLKSTCTRL */ 332/* Used by CM_L4SEC_CLKSTCTRL */
273#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 333#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8
334#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1
274#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) 335#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8)
275 336
276/* Used by CM_ALWON_CLKSTCTRL */ 337/* Used by CM_ALWON_CLKSTCTRL */
277#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 338#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8
339#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1
278#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) 340#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8)
279 341
280/* Used by CM_CEFUSE_CLKSTCTRL */ 342/* Used by CM_CEFUSE_CLKSTCTRL */
281#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 343#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
344#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1
282#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) 345#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
283 346
284/* Used by CM_L4CFG_CLKSTCTRL */ 347/* Used by CM_L4CFG_CLKSTCTRL */
285#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 348#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
349#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1
286#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) 350#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
287 351
288/* Used by CM_D2D_CLKSTCTRL */ 352/* Used by CM_D2D_CLKSTCTRL */
289#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 353#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
354#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1
290#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) 355#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
291 356
292/* Used by CM_L3INIT_CLKSTCTRL */ 357/* Used by CM_L3INIT_CLKSTCTRL */
293#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 358#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
359#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1
294#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) 360#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
295 361
296/* Used by CM_L4PER_CLKSTCTRL */ 362/* Used by CM_L4PER_CLKSTCTRL */
297#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 363#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
364#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1
298#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) 365#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
299 366
300/* Used by CM_L4SEC_CLKSTCTRL */ 367/* Used by CM_L4SEC_CLKSTCTRL */
301#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 368#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9
369#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1
302#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) 370#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9)
303 371
304/* Used by CM_WKUP_CLKSTCTRL */ 372/* Used by CM_WKUP_CLKSTCTRL */
305#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 373#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
374#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1
306#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) 375#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
307 376
308/* Used by CM_MPU_CLKSTCTRL */ 377/* Used by CM_MPU_CLKSTCTRL */
309#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 378#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
379#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1
310#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) 380#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
311 381
312/* Used by CM1_ABE_CLKSTCTRL */ 382/* Used by CM1_ABE_CLKSTCTRL */
313#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 383#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
384#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1
314#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) 385#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
315 386
316/* Used by CM_L4PER_CLKSTCTRL */ 387/* Used by CM_L4PER_CLKSTCTRL */
317#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 388#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
389#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1
318#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) 390#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
319 391
320/* Used by CM_L4PER_CLKSTCTRL */ 392/* Used by CM_L4PER_CLKSTCTRL */
321#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 393#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
394#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
322#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) 395#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
323 396
324/* Used by CM_L4PER_CLKSTCTRL */ 397/* Used by CM_L4PER_CLKSTCTRL */
325#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 398#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
399#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
326#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) 400#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
327 401
328/* Used by CM_L4PER_CLKSTCTRL */ 402/* Used by CM_L4PER_CLKSTCTRL */
329#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 403#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
404#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
330#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) 405#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
331 406
332/* Used by CM_L4PER_CLKSTCTRL */ 407/* Used by CM_L4PER_CLKSTCTRL */
333#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 408#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
409#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1
334#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) 410#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
335 411
336/* Used by CM_L4PER_CLKSTCTRL */ 412/* Used by CM_L4PER_CLKSTCTRL */
337#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 413#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
414#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1
338#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) 415#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
339 416
340/* Used by CM_L4PER_CLKSTCTRL */ 417/* Used by CM_L4PER_CLKSTCTRL */
@@ -343,94 +420,114 @@
343 420
344/* Used by CM_L4PER_CLKSTCTRL */ 421/* Used by CM_L4PER_CLKSTCTRL */
345#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 422#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
423#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1
346#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) 424#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
347 425
348/* Used by CM_L4PER_CLKSTCTRL */ 426/* Used by CM_L4PER_CLKSTCTRL */
349#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 427#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
428#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1
350#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) 429#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
351 430
352/* Used by CM_MEMIF_CLKSTCTRL */ 431/* Used by CM_MEMIF_CLKSTCTRL */
353#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 432#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
433#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1
354#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) 434#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
355 435
356/* Used by CM_GFX_CLKSTCTRL */ 436/* Used by CM_GFX_CLKSTCTRL */
357#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 437#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9
438#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1
358#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) 439#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9)
359 440
360/* Used by CM_ALWON_CLKSTCTRL */ 441/* Used by CM_ALWON_CLKSTCTRL */
361#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 442#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11
443#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1
362#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) 444#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11)
363 445
364/* Used by CM_ALWON_CLKSTCTRL */ 446/* Used by CM_ALWON_CLKSTCTRL */
365#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 447#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10
448#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1
366#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) 449#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10)
367 450
368/* Used by CM_ALWON_CLKSTCTRL */ 451/* Used by CM_ALWON_CLKSTCTRL */
369#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 452#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9
453#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1
370#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) 454#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9)
371 455
372/* Used by CM_WKUP_CLKSTCTRL */ 456/* Used by CM_WKUP_CLKSTCTRL */
373#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 457#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8
458#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1
374#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) 459#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
375 460
376/* Used by CM_TESLA_CLKSTCTRL */ 461/* Used by CM_TESLA_CLKSTCTRL */
377#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 462#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
463#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1
378#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) 464#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
379 465
380/* Used by CM_L3INIT_CLKSTCTRL */ 466/* Used by CM_L3INIT_CLKSTCTRL */
381#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 467#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
468#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
382#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) 469#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
383 470
384/* Used by CM_L3INIT_CLKSTCTRL */ 471/* Used by CM_L3INIT_CLKSTCTRL */
385#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 472#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
473#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
386#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) 474#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
387 475
388/* Used by CM_L3INIT_CLKSTCTRL */ 476/* Used by CM_L3INIT_CLKSTCTRL */
389#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 477#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
478#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
390#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) 479#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
391 480
392/* Used by CM_L3INIT_CLKSTCTRL */ 481/* Used by CM_L3INIT_CLKSTCTRL */
393#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 482#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
483#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1
394#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) 484#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
395 485
396/* Used by CM_L3INIT_CLKSTCTRL */ 486/* Used by CM_L3INIT_CLKSTCTRL */
397#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 487#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
488#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
398#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) 489#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
399 490
400/* Used by CM_L3INIT_CLKSTCTRL */ 491/* Used by CM_L3INIT_CLKSTCTRL */
401#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 492#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
493#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
402#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) 494#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
403 495
404/* Used by CM_WKUP_CLKSTCTRL */ 496/* Used by CM_WKUP_CLKSTCTRL */
405#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 497#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
498#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1
406#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) 499#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
407 500
408/* Used by CM_L3INIT_CLKSTCTRL */ 501/* Used by CM_L3INIT_CLKSTCTRL */
409#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 502#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
503#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
410#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) 504#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
411 505
412/* Used by CM_L3INIT_CLKSTCTRL */ 506/* Used by CM_L3INIT_CLKSTCTRL */
413#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 507#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
508#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
414#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) 509#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
415 510
416/* Used by CM_WKUP_CLKSTCTRL */ 511/* Used by CM_WKUP_CLKSTCTRL */
417#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 512#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
513#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1
418#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) 514#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
419 515
420/* Used by CM_WKUP_CLKSTCTRL */ 516/* Used by CM_WKUP_CLKSTCTRL */
421#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 517#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13
518#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1
422#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) 519#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13)
423 520
424/* 521/*
425 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, 522 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
426 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, 523 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
427 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, 524 * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
428 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, 525 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
429 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, 526 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
430 * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, 527 * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
431 * CM_WKUP_TIMER1_CLKCTRL
432 */ 528 */
433#define OMAP4430_CLKSEL_SHIFT 24 529#define OMAP4430_CLKSEL_SHIFT 24
530#define OMAP4430_CLKSEL_WIDTH 0x1
434#define OMAP4430_CLKSEL_MASK (1 << 24) 531#define OMAP4430_CLKSEL_MASK (1 << 24)
435 532
436/* 533/*
@@ -438,50 +535,62 @@
438 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL 535 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
439 */ 536 */
440#define OMAP4430_CLKSEL_0_0_SHIFT 0 537#define OMAP4430_CLKSEL_0_0_SHIFT 0
538#define OMAP4430_CLKSEL_0_0_WIDTH 0x1
441#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) 539#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
442 540
443/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ 541/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
444#define OMAP4430_CLKSEL_0_1_SHIFT 0 542#define OMAP4430_CLKSEL_0_1_SHIFT 0
543#define OMAP4430_CLKSEL_0_1_WIDTH 0x2
445#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) 544#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0)
446 545
447/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ 546/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
448#define OMAP4430_CLKSEL_24_25_SHIFT 24 547#define OMAP4430_CLKSEL_24_25_SHIFT 24
548#define OMAP4430_CLKSEL_24_25_WIDTH 0x2
449#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) 549#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24)
450 550
451/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ 551/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
452#define OMAP4430_CLKSEL_60M_SHIFT 24 552#define OMAP4430_CLKSEL_60M_SHIFT 24
553#define OMAP4430_CLKSEL_60M_WIDTH 0x1
453#define OMAP4430_CLKSEL_60M_MASK (1 << 24) 554#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
454 555
455/* Used by CM_MPU_MPU_CLKCTRL */ 556/* Used by CM_MPU_MPU_CLKCTRL */
456#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 557#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25
558#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
457#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) 559#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
458 560
459/* Used by CM1_ABE_AESS_CLKCTRL */ 561/* Used by CM1_ABE_AESS_CLKCTRL */
460#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 562#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
563#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1
461#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) 564#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
462 565
463/* Used by CM_CLKSEL_CORE */ 566/* Used by CM_CLKSEL_CORE */
464#define OMAP4430_CLKSEL_CORE_SHIFT 0 567#define OMAP4430_CLKSEL_CORE_SHIFT 0
568#define OMAP4430_CLKSEL_CORE_WIDTH 0x1
465#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) 569#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
466 570
467/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ 571/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
468#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 572#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
573#define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1
469#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) 574#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
470 575
471/* Used by CM_WKUP_USIM_CLKCTRL */ 576/* Used by CM_WKUP_USIM_CLKCTRL */
472#define OMAP4430_CLKSEL_DIV_SHIFT 24 577#define OMAP4430_CLKSEL_DIV_SHIFT 24
578#define OMAP4430_CLKSEL_DIV_WIDTH 0x1
473#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) 579#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
474 580
475/* Used by CM_MPU_MPU_CLKCTRL */ 581/* Used by CM_MPU_MPU_CLKCTRL */
476#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 582#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24
583#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1
477#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) 584#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
478 585
479/* Used by CM_CAM_FDIF_CLKCTRL */ 586/* Used by CM_CAM_FDIF_CLKCTRL */
480#define OMAP4430_CLKSEL_FCLK_SHIFT 24 587#define OMAP4430_CLKSEL_FCLK_SHIFT 24
588#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2
481#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) 589#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
482 590
483/* Used by CM_L4PER_MCBSP4_CLKCTRL */ 591/* Used by CM_L4PER_MCBSP4_CLKCTRL */
484#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 592#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
593#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1
485#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) 594#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25)
486 595
487/* 596/*
@@ -490,34 +599,42 @@
490 * CM1_ABE_MCBSP3_CLKCTRL 599 * CM1_ABE_MCBSP3_CLKCTRL
491 */ 600 */
492#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 601#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
602#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2
493#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) 603#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
494 604
495/* Used by CM_CLKSEL_CORE */ 605/* Used by CM_CLKSEL_CORE */
496#define OMAP4430_CLKSEL_L3_SHIFT 4 606#define OMAP4430_CLKSEL_L3_SHIFT 4
607#define OMAP4430_CLKSEL_L3_WIDTH 0x1
497#define OMAP4430_CLKSEL_L3_MASK (1 << 4) 608#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
498 609
499/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ 610/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
500#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 611#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
612#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1
501#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) 613#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
502 614
503/* Used by CM_CLKSEL_CORE */ 615/* Used by CM_CLKSEL_CORE */
504#define OMAP4430_CLKSEL_L4_SHIFT 8 616#define OMAP4430_CLKSEL_L4_SHIFT 8
617#define OMAP4430_CLKSEL_L4_WIDTH 0x1
505#define OMAP4430_CLKSEL_L4_MASK (1 << 8) 618#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
506 619
507/* Used by CM_CLKSEL_ABE */ 620/* Used by CM_CLKSEL_ABE */
508#define OMAP4430_CLKSEL_OPP_SHIFT 0 621#define OMAP4430_CLKSEL_OPP_SHIFT 0
622#define OMAP4430_CLKSEL_OPP_WIDTH 0x2
509#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) 623#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0)
510 624
511/* Used by CM_EMU_DEBUGSS_CLKCTRL */ 625/* Used by CM_EMU_DEBUGSS_CLKCTRL */
512#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 626#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
627#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3
513#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) 628#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27)
514 629
515/* Used by CM_EMU_DEBUGSS_CLKCTRL */ 630/* Used by CM_EMU_DEBUGSS_CLKCTRL */
516#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 631#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24
632#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3
517#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) 633#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24)
518 634
519/* Used by CM_GFX_GFX_CLKCTRL */ 635/* Used by CM_GFX_GFX_CLKCTRL */
520#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 636#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24
637#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1
521#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) 638#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24)
522 639
523/* 640/*
@@ -525,18 +642,22 @@
525 * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL 642 * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
526 */ 643 */
527#define OMAP4430_CLKSEL_SOURCE_SHIFT 24 644#define OMAP4430_CLKSEL_SOURCE_SHIFT 24
645#define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2
528#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) 646#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24)
529 647
530/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ 648/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
531#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 649#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
650#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1
532#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) 651#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
533 652
534/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 653/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
535#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 654#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
655#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1
536#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) 656#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
537 657
538/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 658/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
539#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 659#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
660#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1
540#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) 661#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
541 662
542/* 663/*
@@ -549,30 +670,37 @@
549 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL 670 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
550 */ 671 */
551#define OMAP4430_CLKTRCTRL_SHIFT 0 672#define OMAP4430_CLKTRCTRL_SHIFT 0
673#define OMAP4430_CLKTRCTRL_WIDTH 0x2
552#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 674#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
553 675
554/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 676/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
555#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 677#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0
678#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7
556#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 679#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
557 680
558/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 681/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
559#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 682#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8
683#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb
560#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 684#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
561 685
562/* Used by REVISION_CM1, REVISION_CM2 */ 686/* Used by REVISION_CM1, REVISION_CM2 */
563#define OMAP4430_CUSTOM_SHIFT 6 687#define OMAP4430_CUSTOM_SHIFT 6
688#define OMAP4430_CUSTOM_WIDTH 0x2
564#define OMAP4430_CUSTOM_MASK (0x3 << 6) 689#define OMAP4430_CUSTOM_MASK (0x3 << 6)
565 690
566/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 691/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
567#define OMAP4430_D2D_DYNDEP_SHIFT 18 692#define OMAP4430_D2D_DYNDEP_SHIFT 18
693#define OMAP4430_D2D_DYNDEP_WIDTH 0x1
568#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) 694#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
569 695
570/* Used by CM_MPU_STATICDEP */ 696/* Used by CM_MPU_STATICDEP */
571#define OMAP4430_D2D_STATDEP_SHIFT 18 697#define OMAP4430_D2D_STATDEP_SHIFT 18
698#define OMAP4430_D2D_STATDEP_WIDTH 0x1
572#define OMAP4430_D2D_STATDEP_MASK (1 << 18) 699#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
573 700
574/* Used by CM_CLKSEL_DPLL_MPU */ 701/* Used by CM_CLKSEL_DPLL_MPU */
575#define OMAP4460_DCC_COUNT_MAX_SHIFT 24 702#define OMAP4460_DCC_COUNT_MAX_SHIFT 24
703#define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8
576#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) 704#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24)
577 705
578/* Used by CM_CLKSEL_DPLL_MPU */ 706/* Used by CM_CLKSEL_DPLL_MPU */
@@ -586,22 +714,27 @@
586 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB 714 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
587 */ 715 */
588#define OMAP4430_DELTAMSTEP_SHIFT 0 716#define OMAP4430_DELTAMSTEP_SHIFT 0
717#define OMAP4430_DELTAMSTEP_WIDTH 0x14
589#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) 718#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
590 719
591/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ 720/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
592#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 721#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0
722#define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15
593#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) 723#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
594 724
595/* Used by CM_DLL_CTRL */ 725/* Used by CM_DLL_CTRL */
596#define OMAP4430_DLL_OVERRIDE_SHIFT 0 726#define OMAP4430_DLL_OVERRIDE_SHIFT 0
727#define OMAP4430_DLL_OVERRIDE_WIDTH 0x1
597#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) 728#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
598 729
599/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ 730/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
600#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 731#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
732#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1
601#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) 733#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
602 734
603/* Used by CM_SHADOW_FREQ_CONFIG1 */ 735/* Used by CM_SHADOW_FREQ_CONFIG1 */
604#define OMAP4430_DLL_RESET_SHIFT 3 736#define OMAP4430_DLL_RESET_SHIFT 3
737#define OMAP4430_DLL_RESET_WIDTH 0x1
605#define OMAP4430_DLL_RESET_MASK (1 << 3) 738#define OMAP4430_DLL_RESET_MASK (1 << 3)
606 739
607/* 740/*
@@ -610,30 +743,37 @@
610 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB 743 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
611 */ 744 */
612#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 745#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
746#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1
613#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) 747#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
614 748
615/* Used by CM_CLKDCOLDO_DPLL_USB */ 749/* Used by CM_CLKDCOLDO_DPLL_USB */
616#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 750#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
751#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1
617#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) 752#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
618 753
619/* Used by CM_CLKSEL_DPLL_CORE */ 754/* Used by CM_CLKSEL_DPLL_CORE */
620#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 755#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
756#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
621#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) 757#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
622 758
623/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ 759/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
624#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 760#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
761#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5
625#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) 762#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
626 763
627/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ 764/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
628#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 765#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
766#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1
629#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) 767#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
630 768
631/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ 769/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
632#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 770#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
771#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1
633#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) 772#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
634 773
635/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ 774/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
636#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 775#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10
776#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1
637#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) 777#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
638 778
639/* 779/*
@@ -641,10 +781,12 @@
641 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO 781 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
642 */ 782 */
643#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 783#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
784#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5
644#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 785#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
645 786
646/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ 787/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
647#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 788#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0
789#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7
648#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) 790#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
649 791
650/* 792/*
@@ -652,10 +794,12 @@
652 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO 794 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
653 */ 795 */
654#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 796#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
797#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1
655#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) 798#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
656 799
657/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ 800/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
658#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 801#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7
802#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1
659#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) 803#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
660 804
661/* 805/*
@@ -663,18 +807,22 @@
663 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB 807 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
664 */ 808 */
665#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 809#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
810#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1
666#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 811#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
667 812
668/* Used by CM_SHADOW_FREQ_CONFIG1 */ 813/* Used by CM_SHADOW_FREQ_CONFIG1 */
669#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 814#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
815#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3
670#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) 816#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
671 817
672/* Used by CM_SHADOW_FREQ_CONFIG1 */ 818/* Used by CM_SHADOW_FREQ_CONFIG1 */
673#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 819#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
820#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5
674#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) 821#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
675 822
676/* Used by CM_SHADOW_FREQ_CONFIG2 */ 823/* Used by CM_SHADOW_FREQ_CONFIG2 */
677#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 824#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
825#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5
678#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) 826#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
679 827
680/* 828/*
@@ -683,10 +831,12 @@
683 * CM_CLKSEL_DPLL_UNIPRO 831 * CM_CLKSEL_DPLL_UNIPRO
684 */ 832 */
685#define OMAP4430_DPLL_DIV_SHIFT 0 833#define OMAP4430_DPLL_DIV_SHIFT 0
834#define OMAP4430_DPLL_DIV_WIDTH 0x7
686#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) 835#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
687 836
688/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ 837/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
689#define OMAP4430_DPLL_DIV_0_7_SHIFT 0 838#define OMAP4430_DPLL_DIV_0_7_SHIFT 0
839#define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8
690#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) 840#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
691 841
692/* 842/*
@@ -694,10 +844,12 @@
694 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 844 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
695 */ 845 */
696#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 846#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
847#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1
697#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 848#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
698 849
699/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ 850/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
700#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 851#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3
852#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1
701#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) 853#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
702 854
703/* 855/*
@@ -706,6 +858,7 @@
706 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB 858 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
707 */ 859 */
708#define OMAP4430_DPLL_EN_SHIFT 0 860#define OMAP4430_DPLL_EN_SHIFT 0
861#define OMAP4430_DPLL_EN_WIDTH 0x3
709#define OMAP4430_DPLL_EN_MASK (0x7 << 0) 862#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
710 863
711/* 864/*
@@ -714,6 +867,7 @@
714 * CM_CLKMODE_DPLL_UNIPRO 867 * CM_CLKMODE_DPLL_UNIPRO
715 */ 868 */
716#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 869#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
870#define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1
717#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) 871#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
718 872
719/* 873/*
@@ -722,10 +876,12 @@
722 * CM_CLKSEL_DPLL_UNIPRO 876 * CM_CLKSEL_DPLL_UNIPRO
723 */ 877 */
724#define OMAP4430_DPLL_MULT_SHIFT 8 878#define OMAP4430_DPLL_MULT_SHIFT 8
879#define OMAP4430_DPLL_MULT_WIDTH 0xb
725#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) 880#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
726 881
727/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ 882/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
728#define OMAP4430_DPLL_MULT_USB_SHIFT 8 883#define OMAP4430_DPLL_MULT_USB_SHIFT 8
884#define OMAP4430_DPLL_MULT_USB_WIDTH 0xc
729#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) 885#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
730 886
731/* 887/*
@@ -734,10 +890,12 @@
734 * CM_CLKMODE_DPLL_UNIPRO 890 * CM_CLKMODE_DPLL_UNIPRO
735 */ 891 */
736#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 892#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
893#define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1
737#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) 894#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
738 895
739/* Used by CM_CLKSEL_DPLL_USB */ 896/* Used by CM_CLKSEL_DPLL_USB */
740#define OMAP4430_DPLL_SD_DIV_SHIFT 24 897#define OMAP4430_DPLL_SD_DIV_SHIFT 24
898#define OMAP4430_DPLL_SD_DIV_WIDTH 0x8
741#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) 899#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
742 900
743/* 901/*
@@ -746,6 +904,7 @@
746 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB 904 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
747 */ 905 */
748#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 906#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
907#define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1
749#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) 908#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
750 909
751/* 910/*
@@ -754,6 +913,7 @@
754 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB 913 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
755 */ 914 */
756#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 915#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
916#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
757#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 917#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
758 918
759/* 919/*
@@ -762,42 +922,52 @@
762 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB 922 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
763 */ 923 */
764#define OMAP4430_DPLL_SSC_EN_SHIFT 12 924#define OMAP4430_DPLL_SSC_EN_SHIFT 12
925#define OMAP4430_DPLL_SSC_EN_WIDTH 0x1
765#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) 926#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
766 927
767/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 928/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
768#define OMAP4430_DSS_DYNDEP_SHIFT 8 929#define OMAP4430_DSS_DYNDEP_SHIFT 8
930#define OMAP4430_DSS_DYNDEP_WIDTH 0x1
769#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) 931#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
770 932
771/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ 933/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
772#define OMAP4430_DSS_STATDEP_SHIFT 8 934#define OMAP4430_DSS_STATDEP_SHIFT 8
935#define OMAP4430_DSS_STATDEP_WIDTH 0x1
773#define OMAP4430_DSS_STATDEP_MASK (1 << 8) 936#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
774 937
775/* Used by CM_L3_2_DYNAMICDEP */ 938/* Used by CM_L3_2_DYNAMICDEP */
776#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 939#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
940#define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1
777#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) 941#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
778 942
779/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ 943/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
780#define OMAP4430_DUCATI_STATDEP_SHIFT 0 944#define OMAP4430_DUCATI_STATDEP_SHIFT 0
945#define OMAP4430_DUCATI_STATDEP_WIDTH 0x1
781#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) 946#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
782 947
783/* Used by CM_SHADOW_FREQ_CONFIG1 */ 948/* Used by CM_SHADOW_FREQ_CONFIG1 */
784#define OMAP4430_FREQ_UPDATE_SHIFT 0 949#define OMAP4430_FREQ_UPDATE_SHIFT 0
950#define OMAP4430_FREQ_UPDATE_WIDTH 0x1
785#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) 951#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
786 952
787/* Used by REVISION_CM1, REVISION_CM2 */ 953/* Used by REVISION_CM1, REVISION_CM2 */
788#define OMAP4430_FUNC_SHIFT 16 954#define OMAP4430_FUNC_SHIFT 16
955#define OMAP4430_FUNC_WIDTH 0xc
789#define OMAP4430_FUNC_MASK (0xfff << 16) 956#define OMAP4430_FUNC_MASK (0xfff << 16)
790 957
791/* Used by CM_L3_2_DYNAMICDEP */ 958/* Used by CM_L3_2_DYNAMICDEP */
792#define OMAP4430_GFX_DYNDEP_SHIFT 10 959#define OMAP4430_GFX_DYNDEP_SHIFT 10
960#define OMAP4430_GFX_DYNDEP_WIDTH 0x1
793#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) 961#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
794 962
795/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 963/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
796#define OMAP4430_GFX_STATDEP_SHIFT 10 964#define OMAP4430_GFX_STATDEP_SHIFT 10
965#define OMAP4430_GFX_STATDEP_WIDTH 0x1
797#define OMAP4430_GFX_STATDEP_MASK (1 << 10) 966#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
798 967
799/* Used by CM_SHADOW_FREQ_CONFIG2 */ 968/* Used by CM_SHADOW_FREQ_CONFIG2 */
800#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 969#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
970#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1
801#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) 971#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
802 972
803/* 973/*
@@ -805,6 +975,7 @@
805 * CM_DIV_M4_DPLL_PER 975 * CM_DIV_M4_DPLL_PER
806 */ 976 */
807#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 977#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
978#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5
808#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 979#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
809 980
810/* 981/*
@@ -812,6 +983,7 @@
812 * CM_DIV_M4_DPLL_PER 983 * CM_DIV_M4_DPLL_PER
813 */ 984 */
814#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 985#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
986#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1
815#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) 987#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
816 988
817/* 989/*
@@ -819,6 +991,7 @@
819 * CM_DIV_M4_DPLL_PER 991 * CM_DIV_M4_DPLL_PER
820 */ 992 */
821#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 993#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
994#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1
822#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) 995#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
823 996
824/* 997/*
@@ -826,6 +999,7 @@
826 * CM_DIV_M4_DPLL_PER 999 * CM_DIV_M4_DPLL_PER
827 */ 1000 */
828#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 1001#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
1002#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1
829#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) 1003#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
830 1004
831/* 1005/*
@@ -833,6 +1007,7 @@
833 * CM_DIV_M5_DPLL_PER 1007 * CM_DIV_M5_DPLL_PER
834 */ 1008 */
835#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 1009#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
1010#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5
836#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 1011#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
837 1012
838/* 1013/*
@@ -840,6 +1015,7 @@
840 * CM_DIV_M5_DPLL_PER 1015 * CM_DIV_M5_DPLL_PER
841 */ 1016 */
842#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 1017#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
1018#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1
843#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) 1019#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
844 1020
845/* 1021/*
@@ -847,6 +1023,7 @@
847 * CM_DIV_M5_DPLL_PER 1023 * CM_DIV_M5_DPLL_PER
848 */ 1024 */
849#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 1025#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
1026#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1
850#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) 1027#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
851 1028
852/* 1029/*
@@ -854,38 +1031,47 @@
854 * CM_DIV_M5_DPLL_PER 1031 * CM_DIV_M5_DPLL_PER
855 */ 1032 */
856#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 1033#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
1034#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1
857#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) 1035#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
858 1036
859/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ 1037/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
860#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 1038#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
1039#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5
861#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) 1040#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
862 1041
863/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ 1042/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
864#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 1043#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
1044#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1
865#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) 1045#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
866 1046
867/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ 1047/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
868#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 1048#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
1049#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1
869#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) 1050#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
870 1051
871/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ 1052/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
872#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 1053#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
1054#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1
873#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) 1055#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
874 1056
875/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ 1057/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
876#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 1058#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
1059#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5
877#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) 1060#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
878 1061
879/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ 1062/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
880#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 1063#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
1064#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1
881#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) 1065#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
882 1066
883/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ 1067/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
884#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 1068#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
1069#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1
885#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) 1070#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
886 1071
887/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ 1072/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
888#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 1073#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
1074#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1
889#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) 1075#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
890 1076
891/* 1077/*
@@ -893,53 +1079,48 @@
893 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, 1079 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
894 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, 1080 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
895 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, 1081 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
896 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 1082 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
897 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 1083 * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
898 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1084 * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
899 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, 1085 * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
900 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 1086 * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
901 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
902 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 1087 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
903 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 1088 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
904 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1089 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
905 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1090 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
906 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1091 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
907 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1092 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
908 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1093 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
909 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL, 1094 * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
910 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL, 1095 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
911 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
912 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
913 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
914 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 1096 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
915 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 1097 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
916 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 1098 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
917 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, 1099 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
918 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, 1100 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
919 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, 1101 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
920 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, 1102 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
921 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, 1103 * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
922 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, 1104 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
923 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, 1105 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
924 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, 1106 * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
925 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, 1107 * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
926 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 1108 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
927 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
928 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
929 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, 1109 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
930 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, 1110 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
931 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, 1111 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
932 * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
933 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, 1112 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
934 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, 1113 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
935 * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, 1114 * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
936 * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL 1115 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
937 */ 1116 */
938#define OMAP4430_IDLEST_SHIFT 16 1117#define OMAP4430_IDLEST_SHIFT 16
1118#define OMAP4430_IDLEST_WIDTH 0x2
939#define OMAP4430_IDLEST_MASK (0x3 << 16) 1119#define OMAP4430_IDLEST_MASK (0x3 << 16)
940 1120
941/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 1121/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
942#define OMAP4430_ISS_DYNDEP_SHIFT 9 1122#define OMAP4430_ISS_DYNDEP_SHIFT 9
1123#define OMAP4430_ISS_DYNDEP_WIDTH 0x1
943#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) 1124#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
944 1125
945/* 1126/*
@@ -947,10 +1128,12 @@
947 * CM_TESLA_STATICDEP 1128 * CM_TESLA_STATICDEP
948 */ 1129 */
949#define OMAP4430_ISS_STATDEP_SHIFT 9 1130#define OMAP4430_ISS_STATDEP_SHIFT 9
1131#define OMAP4430_ISS_STATDEP_WIDTH 0x1
950#define OMAP4430_ISS_STATDEP_MASK (1 << 9) 1132#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
951 1133
952/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ 1134/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
953#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 1135#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
1136#define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1
954#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) 1137#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
955 1138
956/* 1139/*
@@ -959,10 +1142,12 @@
959 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 1142 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
960 */ 1143 */
961#define OMAP4430_IVAHD_STATDEP_SHIFT 2 1144#define OMAP4430_IVAHD_STATDEP_SHIFT 2
1145#define OMAP4430_IVAHD_STATDEP_WIDTH 0x1
962#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) 1146#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
963 1147
964/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 1148/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
965#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 1149#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
1150#define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1
966#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) 1151#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
967 1152
968/* 1153/*
@@ -970,6 +1155,7 @@
970 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 1155 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
971 */ 1156 */
972#define OMAP4430_L3INIT_STATDEP_SHIFT 7 1157#define OMAP4430_L3INIT_STATDEP_SHIFT 7
1158#define OMAP4430_L3INIT_STATDEP_WIDTH 0x1
973#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) 1159#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
974 1160
975/* 1161/*
@@ -977,6 +1163,7 @@
977 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP 1163 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
978 */ 1164 */
979#define OMAP4430_L3_1_DYNDEP_SHIFT 5 1165#define OMAP4430_L3_1_DYNDEP_SHIFT 5
1166#define OMAP4430_L3_1_DYNDEP_WIDTH 0x1
980#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) 1167#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
981 1168
982/* 1169/*
@@ -986,6 +1173,7 @@
986 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 1173 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
987 */ 1174 */
988#define OMAP4430_L3_1_STATDEP_SHIFT 5 1175#define OMAP4430_L3_1_STATDEP_SHIFT 5
1176#define OMAP4430_L3_1_STATDEP_WIDTH 0x1
989#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) 1177#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
990 1178
991/* 1179/*
@@ -995,6 +1183,7 @@
995 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP 1183 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
996 */ 1184 */
997#define OMAP4430_L3_2_DYNDEP_SHIFT 6 1185#define OMAP4430_L3_2_DYNDEP_SHIFT 6
1186#define OMAP4430_L3_2_DYNDEP_WIDTH 0x1
998#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) 1187#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
999 1188
1000/* 1189/*
@@ -1004,10 +1193,12 @@
1004 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 1193 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1005 */ 1194 */
1006#define OMAP4430_L3_2_STATDEP_SHIFT 6 1195#define OMAP4430_L3_2_STATDEP_SHIFT 6
1196#define OMAP4430_L3_2_STATDEP_WIDTH 0x1
1007#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) 1197#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
1008 1198
1009/* Used by CM_L3_1_DYNAMICDEP */ 1199/* Used by CM_L3_1_DYNAMICDEP */
1010#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 1200#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
1201#define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1
1011#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) 1202#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
1012 1203
1013/* 1204/*
@@ -1015,10 +1206,12 @@
1015 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 1206 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1016 */ 1207 */
1017#define OMAP4430_L4CFG_STATDEP_SHIFT 12 1208#define OMAP4430_L4CFG_STATDEP_SHIFT 12
1209#define OMAP4430_L4CFG_STATDEP_WIDTH 0x1
1018#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) 1210#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
1019 1211
1020/* Used by CM_L3_2_DYNAMICDEP */ 1212/* Used by CM_L3_2_DYNAMICDEP */
1021#define OMAP4430_L4PER_DYNDEP_SHIFT 13 1213#define OMAP4430_L4PER_DYNDEP_SHIFT 13
1214#define OMAP4430_L4PER_DYNDEP_WIDTH 0x1
1022#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) 1215#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
1023 1216
1024/* 1217/*
@@ -1026,10 +1219,12 @@
1026 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 1219 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1027 */ 1220 */
1028#define OMAP4430_L4PER_STATDEP_SHIFT 13 1221#define OMAP4430_L4PER_STATDEP_SHIFT 13
1222#define OMAP4430_L4PER_STATDEP_WIDTH 0x1
1029#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) 1223#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
1030 1224
1031/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 1225/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1032#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 1226#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
1227#define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1
1033#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) 1228#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
1034 1229
1035/* 1230/*
@@ -1037,10 +1232,12 @@
1037 * CM_SDMA_STATICDEP 1232 * CM_SDMA_STATICDEP
1038 */ 1233 */
1039#define OMAP4430_L4SEC_STATDEP_SHIFT 14 1234#define OMAP4430_L4SEC_STATDEP_SHIFT 14
1235#define OMAP4430_L4SEC_STATDEP_WIDTH 0x1
1040#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) 1236#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
1041 1237
1042/* Used by CM_L4CFG_DYNAMICDEP */ 1238/* Used by CM_L4CFG_DYNAMICDEP */
1043#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 1239#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
1240#define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1
1044#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) 1241#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
1045 1242
1046/* 1243/*
@@ -1048,6 +1245,7 @@
1048 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 1245 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1049 */ 1246 */
1050#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 1247#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
1248#define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1
1051#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) 1249#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
1052 1250
1053/* 1251/*
@@ -1055,6 +1253,7 @@
1055 * CM_MPU_DYNAMICDEP 1253 * CM_MPU_DYNAMICDEP
1056 */ 1254 */
1057#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 1255#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
1256#define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1
1058#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) 1257#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
1059 1258
1060/* 1259/*
@@ -1064,6 +1263,7 @@
1064 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP 1263 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1065 */ 1264 */
1066#define OMAP4430_MEMIF_STATDEP_SHIFT 4 1265#define OMAP4430_MEMIF_STATDEP_SHIFT 4
1266#define OMAP4430_MEMIF_STATDEP_WIDTH 0x1
1067#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) 1267#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
1068 1268
1069/* 1269/*
@@ -1073,6 +1273,7 @@
1073 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB 1273 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1074 */ 1274 */
1075#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 1275#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
1276#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3
1076#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) 1277#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1077 1278
1078/* 1279/*
@@ -1082,6 +1283,7 @@
1082 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB 1283 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1083 */ 1284 */
1084#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 1285#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
1286#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7
1085#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) 1287#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
1086 1288
1087/* 1289/*
@@ -1089,69 +1291,68 @@
1089 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, 1291 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
1090 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, 1292 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
1091 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, 1293 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
1092 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 1294 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
1093 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 1295 * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
1094 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1296 * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
1095 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, 1297 * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
1096 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 1298 * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1097 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1098 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 1299 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1099 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 1300 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1100 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1301 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1101 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1302 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1102 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1303 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
1103 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1304 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1104 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1305 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
1105 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL, 1306 * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
1106 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL, 1307 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1107 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1108 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1109 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1110 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 1308 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1111 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 1309 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1112 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 1310 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1113 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, 1311 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
1114 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, 1312 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
1115 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, 1313 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
1116 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, 1314 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
1117 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, 1315 * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1118 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, 1316 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1119 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, 1317 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
1120 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, 1318 * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
1121 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, 1319 * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
1122 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 1320 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1123 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1124 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1125 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, 1321 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
1126 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, 1322 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
1127 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, 1323 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1128 * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1129 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, 1324 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
1130 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, 1325 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
1131 * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, 1326 * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
1132 * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL 1327 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
1133 */ 1328 */
1134#define OMAP4430_MODULEMODE_SHIFT 0 1329#define OMAP4430_MODULEMODE_SHIFT 0
1330#define OMAP4430_MODULEMODE_WIDTH 0x2
1135#define OMAP4430_MODULEMODE_MASK (0x3 << 0) 1331#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
1136 1332
1137/* Used by CM_L4CFG_DYNAMICDEP */ 1333/* Used by CM_L4CFG_DYNAMICDEP */
1138#define OMAP4460_MPU_DYNDEP_SHIFT 19 1334#define OMAP4460_MPU_DYNDEP_SHIFT 19
1335#define OMAP4460_MPU_DYNDEP_WIDTH 0x1
1139#define OMAP4460_MPU_DYNDEP_MASK (1 << 19) 1336#define OMAP4460_MPU_DYNDEP_MASK (1 << 19)
1140 1337
1141/* Used by CM_DSS_DSS_CLKCTRL */ 1338/* Used by CM_DSS_DSS_CLKCTRL */
1142#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 1339#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1340#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
1143#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) 1341#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
1144 1342
1145/* Used by CM_WKUP_BANDGAP_CLKCTRL */ 1343/* Used by CM_WKUP_BANDGAP_CLKCTRL */
1146#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 1344#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
1345#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1
1147#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) 1346#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8)
1148 1347
1149/* Used by CM_ALWON_USBPHY_CLKCTRL */ 1348/* Used by CM_ALWON_USBPHY_CLKCTRL */
1150#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 1349#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8
1350#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1
1151#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) 1351#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8)
1152 1352
1153/* Used by CM_CAM_ISS_CLKCTRL */ 1353/* Used by CM_CAM_ISS_CLKCTRL */
1154#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 1354#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
1355#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1
1155#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) 1356#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1156 1357
1157/* 1358/*
@@ -1160,126 +1361,157 @@
1160 * CM_WKUP_GPIO1_CLKCTRL 1361 * CM_WKUP_GPIO1_CLKCTRL
1161 */ 1362 */
1162#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 1363#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
1364#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1
1163#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) 1365#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
1164 1366
1165/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ 1367/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
1166#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 1368#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8
1369#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1
1167#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) 1370#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
1168 1371
1169/* Used by CM_DSS_DSS_CLKCTRL */ 1372/* Used by CM_DSS_DSS_CLKCTRL */
1170#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 1373#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
1374#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1
1171#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) 1375#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8)
1172 1376
1173/* Used by CM_WKUP_USIM_CLKCTRL */ 1377/* Used by CM_WKUP_USIM_CLKCTRL */
1174#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 1378#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8
1379#define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1
1175#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) 1380#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8)
1176 1381
1177/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1382/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1178#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 1383#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
1384#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1
1179#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) 1385#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8)
1180 1386
1181/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1387/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1182#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 1388#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
1389#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1
1183#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) 1390#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9)
1184 1391
1185/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1392/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1186#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 1393#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
1394#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1
1187#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) 1395#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
1188 1396
1189/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 1397/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1190#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 1398#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
1399#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1
1191#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) 1400#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
1192 1401
1193/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 1402/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1194#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1403#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1404#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
1195#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) 1405#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1196 1406
1197/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 1407/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1198#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1408#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1409#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
1199#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) 1410#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1200 1411
1201/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 1412/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1202#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1413#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1414#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
1203#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) 1415#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1204 1416
1205/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 1417/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1206#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1418#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1419#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
1207#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) 1420#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1208 1421
1209/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1422/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1210#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 1423#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
1424#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1
1211#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) 1425#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8)
1212 1426
1213/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1427/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1214#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 1428#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
1429#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1
1215#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) 1430#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9)
1216 1431
1217/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ 1432/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
1218#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 1433#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
1434#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1
1219#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) 1435#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8)
1220 1436
1221/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1437/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1222#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 1438#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
1439#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
1223#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) 1440#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10)
1224 1441
1225/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1442/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
1226#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 1443#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
1444#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1
1227#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) 1445#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11)
1228 1446
1229/* Used by CM_DSS_DSS_CLKCTRL */ 1447/* Used by CM_DSS_DSS_CLKCTRL */
1230#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 1448#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
1449#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1
1231#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) 1450#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1232 1451
1233/* Used by CM_WKUP_BANDGAP_CLKCTRL */ 1452/* Used by CM_WKUP_BANDGAP_CLKCTRL */
1234#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 1453#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
1454#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1
1235#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) 1455#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8)
1236 1456
1237/* Used by CM_DSS_DSS_CLKCTRL */ 1457/* Used by CM_DSS_DSS_CLKCTRL */
1238#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 1458#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
1459#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1
1239#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) 1460#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
1240 1461
1241/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ 1462/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
1242#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 1463#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
1464#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1
1243#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) 1465#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
1244 1466
1245/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ 1467/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1246#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1468#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1469#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
1247#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) 1470#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1248 1471
1249/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ 1472/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1250#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1473#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1474#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
1251#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) 1475#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1252 1476
1253/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ 1477/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1254#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1478#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1479#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
1255#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) 1480#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1256 1481
1257/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 1482/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1258#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1483#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1484#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
1259#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) 1485#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1260 1486
1261/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 1487/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1262#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1488#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1489#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
1263#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) 1490#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1264 1491
1265/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ 1492/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1266#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1493#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1494#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
1267#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) 1495#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1268 1496
1269/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ 1497/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
1270#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 1498#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
1499#define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1
1271#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) 1500#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8)
1272 1501
1273/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 1502/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
1274#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 1503#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19
1504#define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1
1275#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) 1505#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19)
1276 1506
1277/* Used by CM_CLKSEL_ABE */ 1507/* Used by CM_CLKSEL_ABE */
1278#define OMAP4430_PAD_CLKS_GATE_SHIFT 8 1508#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
1509#define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1
1279#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) 1510#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8)
1280 1511
1281/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ 1512/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
1282#define OMAP4430_PERF_CURRENT_SHIFT 0 1513#define OMAP4430_PERF_CURRENT_SHIFT 0
1514#define OMAP4430_PERF_CURRENT_WIDTH 0x8
1283#define OMAP4430_PERF_CURRENT_MASK (0xff << 0) 1515#define OMAP4430_PERF_CURRENT_MASK (0xff << 0)
1284 1516
1285/* 1517/*
@@ -1288,74 +1520,85 @@
1288 * CM_IVA_DVFS_PERF_TESLA 1520 * CM_IVA_DVFS_PERF_TESLA
1289 */ 1521 */
1290#define OMAP4430_PERF_REQ_SHIFT 0 1522#define OMAP4430_PERF_REQ_SHIFT 0
1523#define OMAP4430_PERF_REQ_WIDTH 0x8
1291#define OMAP4430_PERF_REQ_MASK (0xff << 0) 1524#define OMAP4430_PERF_REQ_MASK (0xff << 0)
1292 1525
1293/* Used by CM_RESTORE_ST */ 1526/* Used by CM_RESTORE_ST */
1294#define OMAP4430_PHASE1_COMPLETED_SHIFT 0 1527#define OMAP4430_PHASE1_COMPLETED_SHIFT 0
1528#define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1
1295#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) 1529#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0)
1296 1530
1297/* Used by CM_RESTORE_ST */ 1531/* Used by CM_RESTORE_ST */
1298#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 1532#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1
1533#define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1
1299#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) 1534#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1)
1300 1535
1301/* Used by CM_RESTORE_ST */ 1536/* Used by CM_RESTORE_ST */
1302#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 1537#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2
1538#define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1
1303#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) 1539#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2)
1304 1540
1305/* Used by CM_EMU_DEBUGSS_CLKCTRL */ 1541/* Used by CM_EMU_DEBUGSS_CLKCTRL */
1306#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 1542#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
1543#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2
1307#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) 1544#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20)
1308 1545
1309/* Used by CM_EMU_DEBUGSS_CLKCTRL */ 1546/* Used by CM_EMU_DEBUGSS_CLKCTRL */
1310#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 1547#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
1548#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2
1311#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) 1549#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
1312 1550
1313/* Used by CM_DYN_DEP_PRESCAL */ 1551/* Used by CM_DYN_DEP_PRESCAL */
1314#define OMAP4430_PRESCAL_SHIFT 0 1552#define OMAP4430_PRESCAL_SHIFT 0
1553#define OMAP4430_PRESCAL_WIDTH 0x6
1315#define OMAP4430_PRESCAL_MASK (0x3f << 0) 1554#define OMAP4430_PRESCAL_MASK (0x3f << 0)
1316 1555
1317/* Used by REVISION_CM1, REVISION_CM2 */ 1556/* Used by REVISION_CM1, REVISION_CM2 */
1318#define OMAP4430_R_RTL_SHIFT 11 1557#define OMAP4430_R_RTL_SHIFT 11
1558#define OMAP4430_R_RTL_WIDTH 0x5
1319#define OMAP4430_R_RTL_MASK (0x1f << 11) 1559#define OMAP4430_R_RTL_MASK (0x1f << 11)
1320 1560
1321/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ 1561/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
1322#define OMAP4430_SAR_MODE_SHIFT 4 1562#define OMAP4430_SAR_MODE_SHIFT 4
1563#define OMAP4430_SAR_MODE_WIDTH 0x1
1323#define OMAP4430_SAR_MODE_MASK (1 << 4) 1564#define OMAP4430_SAR_MODE_MASK (1 << 4)
1324 1565
1325/* Used by CM_SCALE_FCLK */ 1566/* Used by CM_SCALE_FCLK */
1326#define OMAP4430_SCALE_FCLK_SHIFT 0 1567#define OMAP4430_SCALE_FCLK_SHIFT 0
1568#define OMAP4430_SCALE_FCLK_WIDTH 0x1
1327#define OMAP4430_SCALE_FCLK_MASK (1 << 0) 1569#define OMAP4430_SCALE_FCLK_MASK (1 << 0)
1328 1570
1329/* Used by REVISION_CM1, REVISION_CM2 */ 1571/* Used by REVISION_CM1, REVISION_CM2 */
1330#define OMAP4430_SCHEME_SHIFT 30 1572#define OMAP4430_SCHEME_SHIFT 30
1573#define OMAP4430_SCHEME_WIDTH 0x2
1331#define OMAP4430_SCHEME_MASK (0x3 << 30) 1574#define OMAP4430_SCHEME_MASK (0x3 << 30)
1332 1575
1333/* Used by CM_L4CFG_DYNAMICDEP */ 1576/* Used by CM_L4CFG_DYNAMICDEP */
1334#define OMAP4430_SDMA_DYNDEP_SHIFT 11 1577#define OMAP4430_SDMA_DYNDEP_SHIFT 11
1578#define OMAP4430_SDMA_DYNDEP_WIDTH 0x1
1335#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) 1579#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
1336 1580
1337/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 1581/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1338#define OMAP4430_SDMA_STATDEP_SHIFT 11 1582#define OMAP4430_SDMA_STATDEP_SHIFT 11
1583#define OMAP4430_SDMA_STATDEP_WIDTH 0x1
1339#define OMAP4430_SDMA_STATDEP_MASK (1 << 11) 1584#define OMAP4430_SDMA_STATDEP_MASK (1 << 11)
1340 1585
1341/* Used by CM_CLKSEL_ABE */ 1586/* Used by CM_CLKSEL_ABE */
1342#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 1587#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
1588#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1
1343#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) 1589#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10)
1344 1590
1345/* 1591/*
1346 * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, 1592 * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
1347 * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, 1593 * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1348 * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, 1594 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1349 * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1350 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1595 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1351 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1352 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1353 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, 1596 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1354 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, 1597 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1355 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, 1598 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
1356 * CM_TESLA_TESLA_CLKCTRL
1357 */ 1599 */
1358#define OMAP4430_STBYST_SHIFT 18 1600#define OMAP4430_STBYST_SHIFT 18
1601#define OMAP4430_STBYST_WIDTH 0x1
1359#define OMAP4430_STBYST_MASK (1 << 18) 1602#define OMAP4430_STBYST_MASK (1 << 18)
1360 1603
1361/* 1604/*
@@ -1364,10 +1607,12 @@
1364 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB 1607 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1365 */ 1608 */
1366#define OMAP4430_ST_DPLL_CLK_SHIFT 0 1609#define OMAP4430_ST_DPLL_CLK_SHIFT 0
1610#define OMAP4430_ST_DPLL_CLK_WIDTH 0x1
1367#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) 1611#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0)
1368 1612
1369/* Used by CM_CLKDCOLDO_DPLL_USB */ 1613/* Used by CM_CLKDCOLDO_DPLL_USB */
1370#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 1614#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9
1615#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1
1371#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) 1616#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1372 1617
1373/* 1618/*
@@ -1375,14 +1620,17 @@
1375 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB 1620 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1376 */ 1621 */
1377#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 1622#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
1623#define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1
1378#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) 1624#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
1379 1625
1380/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ 1626/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
1381#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 1627#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
1628#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1
1382#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) 1629#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
1383 1630
1384/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ 1631/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
1385#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 1632#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11
1633#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1
1386#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) 1634#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
1387 1635
1388/* 1636/*
@@ -1390,6 +1638,7 @@
1390 * CM_DIV_M4_DPLL_PER 1638 * CM_DIV_M4_DPLL_PER
1391 */ 1639 */
1392#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 1640#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
1641#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1
1393#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) 1642#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
1394 1643
1395/* 1644/*
@@ -1397,14 +1646,17 @@
1397 * CM_DIV_M5_DPLL_PER 1646 * CM_DIV_M5_DPLL_PER
1398 */ 1647 */
1399#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 1648#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
1649#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1
1400#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) 1650#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
1401 1651
1402/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ 1652/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1403#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 1653#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
1654#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1
1404#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) 1655#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
1405 1656
1406/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ 1657/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1407#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 1658#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
1659#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1
1408#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) 1660#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
1409 1661
1410/* 1662/*
@@ -1413,18 +1665,22 @@
1413 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB 1665 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1414 */ 1666 */
1415#define OMAP4430_ST_MN_BYPASS_SHIFT 8 1667#define OMAP4430_ST_MN_BYPASS_SHIFT 8
1668#define OMAP4430_ST_MN_BYPASS_WIDTH 0x1
1416#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) 1669#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8)
1417 1670
1418/* Used by CM_SYS_CLKSEL */ 1671/* Used by CM_SYS_CLKSEL */
1419#define OMAP4430_SYS_CLKSEL_SHIFT 0 1672#define OMAP4430_SYS_CLKSEL_SHIFT 0
1673#define OMAP4430_SYS_CLKSEL_WIDTH 0x3
1420#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) 1674#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
1421 1675
1422/* Used by CM_L4CFG_DYNAMICDEP */ 1676/* Used by CM_L4CFG_DYNAMICDEP */
1423#define OMAP4430_TESLA_DYNDEP_SHIFT 1 1677#define OMAP4430_TESLA_DYNDEP_SHIFT 1
1678#define OMAP4430_TESLA_DYNDEP_WIDTH 0x1
1424#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) 1679#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
1425 1680
1426/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 1681/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1427#define OMAP4430_TESLA_STATDEP_SHIFT 1 1682#define OMAP4430_TESLA_STATDEP_SHIFT 1
1683#define OMAP4430_TESLA_STATDEP_WIDTH 0x1
1428#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) 1684#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
1429 1685
1430/* 1686/*
@@ -1433,13 +1689,16 @@
1433 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP 1689 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1434 */ 1690 */
1435#define OMAP4430_WINDOWSIZE_SHIFT 24 1691#define OMAP4430_WINDOWSIZE_SHIFT 24
1692#define OMAP4430_WINDOWSIZE_WIDTH 0x4
1436#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) 1693#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
1437 1694
1438/* Used by REVISION_CM1, REVISION_CM2 */ 1695/* Used by REVISION_CM1, REVISION_CM2 */
1439#define OMAP4430_X_MAJOR_SHIFT 8 1696#define OMAP4430_X_MAJOR_SHIFT 8
1697#define OMAP4430_X_MAJOR_WIDTH 0x3
1440#define OMAP4430_X_MAJOR_MASK (0x7 << 8) 1698#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
1441 1699
1442/* Used by REVISION_CM1, REVISION_CM2 */ 1700/* Used by REVISION_CM1, REVISION_CM2 */
1443#define OMAP4430_Y_MINOR_SHIFT 0 1701#define OMAP4430_Y_MINOR_SHIFT 0
1702#define OMAP4430_Y_MINOR_WIDTH 0x6
1444#define OMAP4430_Y_MINOR_MASK (0x3f << 0) 1703#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
1445#endif 1704#endif
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index c1a5cab0f236..5594b42372ee 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -354,6 +354,7 @@
354 354
355/* AM33XX CONTROL_STATUS bitfields (partial) */ 355/* AM33XX CONTROL_STATUS bitfields (partial) */
356#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 356#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
357#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2
357#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) 358#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
358 359
359/* CONTROL OMAP STATUS register to identify OMAP3 features */ 360/* CONTROL OMAP STATUS register to identify OMAP3 features */
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index af1ed7d24a1f..5a3afd2b737d 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
488 488
489 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 489 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
490 if (oc->_clk) 490 if (oc->_clk)
491 clk_enable(oc->_clk); 491 clk_prepare_enable(oc->_clk);
492 492
493 dispc_disable_outputs(); 493 dispc_disable_outputs();
494 494
@@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
515 515
516 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 516 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
517 if (oc->_clk) 517 if (oc->_clk)
518 clk_disable(oc->_clk); 518 clk_disable_unprepare(oc->_clk);
519 519
520 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; 520 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
521 521
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 27d79deb4ba2..814e1808e158 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
63 const struct dpll_data *dd; 63 const struct dpll_data *dd;
64 int i = 0; 64 int i = 0;
65 int ret = -EINVAL; 65 int ret = -EINVAL;
66 const char *clk_name;
66 67
67 dd = clk->dpll_data; 68 dd = clk->dpll_data;
69 clk_name = __clk_get_name(clk);
68 70
69 state <<= __ffs(dd->idlest_mask); 71 state <<= __ffs(dd->idlest_mask);
70 72
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
76 78
77 if (i == MAX_DPLL_WAIT_TRIES) { 79 if (i == MAX_DPLL_WAIT_TRIES) {
78 printk(KERN_ERR "clock: %s failed transition to '%s'\n", 80 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
79 clk->name, (state) ? "locked" : "bypassed"); 81 clk_name, (state) ? "locked" : "bypassed");
80 } else { 82 } else {
81 pr_debug("clock: %s transition to '%s' in %d loops\n", 83 pr_debug("clock: %s transition to '%s' in %d loops\n",
82 clk->name, (state) ? "locked" : "bypassed", i); 84 clk_name, (state) ? "locked" : "bypassed", i);
83 85
84 ret = 0; 86 ret = 0;
85 } 87 }
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
93 unsigned long fint; 95 unsigned long fint;
94 u16 f = 0; 96 u16 f = 0;
95 97
96 fint = clk->dpll_data->clk_ref->rate / n; 98 fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
97 99
98 pr_debug("clock: fint is %lu\n", fint); 100 pr_debug("clock: fint is %lu\n", fint);
99 101
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
140 u8 state = 1; 142 u8 state = 1;
141 int r = 0; 143 int r = 0;
142 144
143 pr_debug("clock: locking DPLL %s\n", clk->name); 145 pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
144 146
145 dd = clk->dpll_data; 147 dd = clk->dpll_data;
146 state <<= __ffs(dd->idlest_mask); 148 state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
187 return -EINVAL; 189 return -EINVAL;
188 190
189 pr_debug("clock: configuring DPLL %s for low-power bypass\n", 191 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
190 clk->name); 192 __clk_get_name(clk));
191 193
192 ai = omap3_dpll_autoidle_read(clk); 194 ai = omap3_dpll_autoidle_read(clk);
193 195
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
217 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) 219 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
218 return -EINVAL; 220 return -EINVAL;
219 221
220 pr_debug("clock: stopping DPLL %s\n", clk->name); 222 pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
221 223
222 ai = omap3_dpll_autoidle_read(clk); 224 ai = omap3_dpll_autoidle_read(clk);
223 225
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
245{ 247{
246 unsigned long fint, clkinp; /* watch out for overflow */ 248 unsigned long fint, clkinp; /* watch out for overflow */
247 249
248 clkinp = clk->parent->rate; 250 clkinp = __clk_get_rate(__clk_get_parent(clk));
249 fint = (clkinp / n) * m; 251 fint = (clkinp / n) * m;
250 252
251 if (fint < 1000000000) 253 if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
271 unsigned long clkinp, sd; /* watch out for overflow */ 273 unsigned long clkinp, sd; /* watch out for overflow */
272 int mod1, mod2; 274 int mod1, mod2;
273 275
274 clkinp = clk->parent->rate; 276 clkinp = __clk_get_rate(__clk_get_parent(clk));
275 277
276 /* 278 /*
277 * target sigma-delta to near 250MHz 279 * target sigma-delta to near 250MHz
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
380{ 382{
381 int r; 383 int r;
382 struct dpll_data *dd; 384 struct dpll_data *dd;
385 struct clk *parent;
383 386
384 dd = clk->dpll_data; 387 dd = clk->dpll_data;
385 if (!dd) 388 if (!dd)
386 return -EINVAL; 389 return -EINVAL;
387 390
388 if (clk->rate == dd->clk_bypass->rate) { 391 parent = __clk_get_parent(clk);
389 WARN_ON(clk->parent != dd->clk_bypass); 392
393 if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
394 WARN_ON(parent != dd->clk_bypass);
390 r = _omap3_noncore_dpll_bypass(clk); 395 r = _omap3_noncore_dpll_bypass(clk);
391 } else { 396 } else {
392 WARN_ON(clk->parent != dd->clk_ref); 397 WARN_ON(parent != dd->clk_ref);
393 r = _omap3_noncore_dpll_lock(clk); 398 r = _omap3_noncore_dpll_lock(clk);
394 } 399 }
395 /* 400 /*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
432int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) 437int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
433{ 438{
434 struct clk *new_parent = NULL; 439 struct clk *new_parent = NULL;
435 unsigned long hw_rate; 440 unsigned long hw_rate, bypass_rate;
436 u16 freqsel = 0; 441 u16 freqsel = 0;
437 struct dpll_data *dd; 442 struct dpll_data *dd;
438 int ret; 443 int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
456 omap2_clk_enable(dd->clk_bypass); 461 omap2_clk_enable(dd->clk_bypass);
457 omap2_clk_enable(dd->clk_ref); 462 omap2_clk_enable(dd->clk_ref);
458 463
459 if (dd->clk_bypass->rate == rate && 464 bypass_rate = __clk_get_rate(dd->clk_bypass);
465 if (bypass_rate == rate &&
460 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 466 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
461 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); 467 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
462 468
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
479 } 485 }
480 486
481 pr_debug("clock: %s: set rate: locking rate to %lu.\n", 487 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
482 clk->name, rate); 488 __clk_get_name(clk), rate);
483 489
484 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, 490 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
485 dd->last_rounded_n, freqsel); 491 dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
557 563
558 if (!dd->autoidle_reg) { 564 if (!dd->autoidle_reg) {
559 pr_debug("clock: DPLL %s: autoidle not supported\n", 565 pr_debug("clock: DPLL %s: autoidle not supported\n",
560 clk->name); 566 __clk_get_name(clk));
561 return; 567 return;
562 } 568 }
563 569
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
591 597
592 if (!dd->autoidle_reg) { 598 if (!dd->autoidle_reg) {
593 pr_debug("clock: DPLL %s: autoidle not supported\n", 599 pr_debug("clock: DPLL %s: autoidle not supported\n",
594 clk->name); 600 __clk_get_name(clk));
595 return; 601 return;
596 } 602 }
597 603
@@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
617 unsigned long rate; 623 unsigned long rate;
618 u32 v; 624 u32 v;
619 struct clk *pclk; 625 struct clk *pclk;
626 unsigned long parent_rate;
620 627
621 /* Walk up the parents of clk, looking for a DPLL */ 628 /* Walk up the parents of clk, looking for a DPLL */
622 pclk = clk->parent; 629 pclk = __clk_get_parent(clk);
623 while (pclk && !pclk->dpll_data) 630 while (pclk && !pclk->dpll_data)
624 pclk = pclk->parent; 631 pclk = __clk_get_parent(pclk);
625 632
626 /* clk does not have a DPLL as a parent? error in the clock data */ 633 /* clk does not have a DPLL as a parent? error in the clock data */
627 if (!pclk) { 634 if (!pclk) {
@@ -633,12 +640,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
633 640
634 WARN_ON(!dd->enable_mask); 641 WARN_ON(!dd->enable_mask);
635 642
643 parent_rate = __clk_get_rate(__clk_get_parent(clk));
636 v = __raw_readl(dd->control_reg) & dd->enable_mask; 644 v = __raw_readl(dd->control_reg) & dd->enable_mask;
637 v >>= __ffs(dd->enable_mask); 645 v >>= __ffs(dd->enable_mask);
638 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) 646 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
639 rate = clk->parent->rate; 647 rate = parent_rate;
640 else 648 else
641 rate = clk->parent->rate * 2; 649 rate = parent_rate * 2;
642 return rate; 650 return rate;
643} 651}
644 652
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 72428bd45efc..fe75656f9900 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -879,7 +879,7 @@ static int __init gpmc_init(void)
879 BUG(); 879 BUG();
880 } 880 }
881 881
882 clk_enable(gpmc_l3_clk); 882 clk_prepare_enable(gpmc_l3_clk);
883 883
884 l = gpmc_read_reg(GPMC_REVISION); 884 l = gpmc_read_reg(GPMC_REVISION);
885 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 885 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7d843cd3b33d..5c8c5e0449b6 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -679,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh)
679 if (!oh->main_clk) 679 if (!oh->main_clk)
680 return 0; 680 return 0;
681 681
682 oh->_clk = omap_clk_get_by_name(oh->main_clk); 682 oh->_clk = clk_get(NULL, oh->main_clk);
683 if (!oh->_clk) { 683 if (IS_ERR(oh->_clk)) {
684 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", 684 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
685 oh->name, oh->main_clk); 685 oh->name, oh->main_clk);
686 return -EINVAL; 686 return -EINVAL;
687 } 687 }
688 /*
689 * HACK: This needs a re-visit once clk_prepare() is implemented
690 * to do something meaningful. Today its just a no-op.
691 * If clk_prepare() is used at some point to do things like
692 * voltage scaling etc, then this would have to be moved to
693 * some point where subsystems like i2c and pmic become
694 * available.
695 */
696 clk_prepare(oh->_clk);
688 697
689 if (!oh->_clk->clkdm) 698 if (!oh->_clk->clkdm)
690 pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", 699 pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
691 oh->main_clk, oh->_clk->name); 700 oh->name, oh->main_clk);
692 701
693 return ret; 702 return ret;
694} 703}
@@ -715,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh)
715 if (!os->clk) 724 if (!os->clk)
716 continue; 725 continue;
717 726
718 c = omap_clk_get_by_name(os->clk); 727 c = clk_get(NULL, os->clk);
719 if (!c) { 728 if (IS_ERR(c)) {
720 pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", 729 pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
721 oh->name, os->clk); 730 oh->name, os->clk);
722 ret = -EINVAL; 731 ret = -EINVAL;
723 } 732 }
724 os->_clk = c; 733 os->_clk = c;
734 /*
735 * HACK: This needs a re-visit once clk_prepare() is implemented
736 * to do something meaningful. Today its just a no-op.
737 * If clk_prepare() is used at some point to do things like
738 * voltage scaling etc, then this would have to be moved to
739 * some point where subsystems like i2c and pmic become
740 * available.
741 */
742 clk_prepare(os->_clk);
725 } 743 }
726 744
727 return ret; 745 return ret;
@@ -742,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
742 int ret = 0; 760 int ret = 0;
743 761
744 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { 762 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
745 c = omap_clk_get_by_name(oc->clk); 763 c = clk_get(NULL, oc->clk);
746 if (!c) { 764 if (IS_ERR(c)) {
747 pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", 765 pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
748 oh->name, oc->clk); 766 oh->name, oc->clk);
749 ret = -EINVAL; 767 ret = -EINVAL;
750 } 768 }
751 oc->_clk = c; 769 oc->_clk = c;
770 /*
771 * HACK: This needs a re-visit once clk_prepare() is implemented
772 * to do something meaningful. Today its just a no-op.
773 * If clk_prepare() is used at some point to do things like
774 * voltage scaling etc, then this would have to be moved to
775 * some point where subsystems like i2c and pmic become
776 * available.
777 */
778 clk_prepare(oc->_clk);
752 } 779 }
753 780
754 return ret; 781 return ret;
@@ -827,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
827 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 854 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
828 if (oc->_clk) { 855 if (oc->_clk) {
829 pr_debug("omap_hwmod: enable %s:%s\n", oc->role, 856 pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
830 oc->_clk->name); 857 __clk_get_name(oc->_clk));
831 clk_enable(oc->_clk); 858 clk_enable(oc->_clk);
832 } 859 }
833} 860}
@@ -842,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
842 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 869 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
843 if (oc->_clk) { 870 if (oc->_clk) {
844 pr_debug("omap_hwmod: disable %s:%s\n", oc->role, 871 pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
845 oc->_clk->name); 872 __clk_get_name(oc->_clk));
846 clk_disable(oc->_clk); 873 clk_disable(oc->_clk);
847 } 874 }
848} 875}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 939bd6f70b51..f6f05b67f86a 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -188,7 +188,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
188 goto exit; 188 goto exit;
189 } 189 }
190 190
191 freq = clk->rate; 191 freq = clk_get_rate(clk);
192 clk_put(clk); 192 clk_put(clk);
193 193
194 rcu_read_lock(); 194 rcu_read_lock();
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 19:27:11 -0400